include/opcode/ia64.h

   1 /* ia64.h -- Header file for ia64 opcode table
   2    Copyright (C) 1998, 1999, 2000, 2002, 2005, 2006
   3    Free Software Foundation, Inc.
   4    Contributed by David Mosberger-Tang <davidm@hpl.hp.com> */
   5
   6 #ifndef opcode_ia64_h
   7 #define opcode_ia64_h
   8
   9 #include <sys/types.h>
  10
  11 #include "bfd.h"
  12
  13
  14 typedef BFD_HOST_U_64_BIT ia64_insn;
  15
  16 enum ia64_insn_type
  17   {
  18     IA64_TYPE_NIL = 0,  /* illegal type */
  19     IA64_TYPE_A,        /* integer alu (I- or M-unit) */
  20     IA64_TYPE_I,        /* non-alu integer (I-unit) */
  21     IA64_TYPE_M,        /* memory (M-unit) */
  22     IA64_TYPE_B,        /* branch (B-unit) */
  23     IA64_TYPE_F,        /* floating-point (F-unit) */
  24     IA64_TYPE_X,        /* long encoding (X-unit) */
  25     IA64_TYPE_DYN,      /* Dynamic opcode */
  26     IA64_NUM_TYPES
  27   };
  28
  29 enum ia64_unit
  30   {
  31     IA64_UNIT_NIL = 0,  /* illegal unit */
  32     IA64_UNIT_I,        /* integer unit */
  33     IA64_UNIT_M,        /* memory unit */
  34     IA64_UNIT_B,        /* branching unit */
  35     IA64_UNIT_F,        /* floating-point unit */
  36     IA64_UNIT_L,        /* long "unit" */
  37     IA64_UNIT_X,        /* may be integer or branch unit */
  38     IA64_NUM_UNITS
  39   };
  40
  41 /* Changes to this enumeration must be propagated to the operand table in
  42    bfd/cpu-ia64-opc.c
  43  */
  44 enum ia64_opnd
  45   {
  46     IA64_OPND_NIL,      /* no operand---MUST BE FIRST!*/
  47
  48     /* constants */
  49     IA64_OPND_AR_CSD,   /* application register csd (ar.csd) */
  50     IA64_OPND_AR_CCV,   /* application register ccv (ar.ccv) */
  51     IA64_OPND_AR_PFS,   /* application register pfs (ar.pfs) */
  52     IA64_OPND_C1,       /* the constant 1 */
  53     IA64_OPND_C8,       /* the constant 8 */
  54     IA64_OPND_C16,      /* the constant 16 */
  55     IA64_OPND_GR0,      /* gr0 */
  56     IA64_OPND_IP,       /* instruction pointer (ip) */
  57     IA64_OPND_PR,       /* predicate register (pr) */
  58     IA64_OPND_PR_ROT,   /* rotating predicate register (pr.rot) */
  59     IA64_OPND_PSR,      /* processor status register (psr) */
  60     IA64_OPND_PSR_L,    /* processor status register L (psr.l) */
  61     IA64_OPND_PSR_UM,   /* processor status register UM (psr.um) */
  62
  63     /* register operands: */
  64     IA64_OPND_AR3,      /* third application register # (bits 20-26) */
  65     IA64_OPND_B1,       /* branch register # (bits 6-8) */
  66     IA64_OPND_B2,       /* branch register # (bits 13-15) */
  67     IA64_OPND_CR3,      /* third control register # (bits 20-26) */
  68     IA64_OPND_F1,       /* first floating-point register # */
  69     IA64_OPND_F2,       /* second floating-point register # */
  70     IA64_OPND_F3,       /* third floating-point register # */
  71     IA64_OPND_F4,       /* fourth floating-point register # */
  72     IA64_OPND_P1,       /* first predicate # */
  73     IA64_OPND_P2,       /* second predicate # */
  74     IA64_OPND_R1,       /* first register # */
  75     IA64_OPND_R2,       /* second register # */
  76     IA64_OPND_R3,       /* third register # */
  77     IA64_OPND_R3_2,     /* third register # (limited to gr0-gr3) */
  78
  79     /* memory operands: */
  80     IA64_OPND_MR3,      /* memory at addr of third register # */
  81
  82     /* indirect operands: */
  83     IA64_OPND_CPUID_R3, /* cpuid[reg] */
  84     IA64_OPND_DBR_R3,   /* dbr[reg] */
  85     IA64_OPND_DTR_R3,   /* dtr[reg] */
  86     IA64_OPND_ITR_R3,   /* itr[reg] */
  87     IA64_OPND_IBR_R3,   /* ibr[reg] */
  88     IA64_OPND_MSR_R3,   /* msr[reg] */
  89     IA64_OPND_PKR_R3,   /* pkr[reg] */
  90     IA64_OPND_PMC_R3,   /* pmc[reg] */
  91     IA64_OPND_PMD_R3,   /* pmd[reg] */
  92     IA64_OPND_RR_R3,    /* rr[reg] */
  93
  94     /* immediate operands: */
  95     IA64_OPND_CCNT5,    /* 5-bit count (31 - bits 20-24) */
  96     IA64_OPND_CNT2a,    /* 2-bit count (1 + bits 27-28) */
  97     IA64_OPND_CNT2b,    /* 2-bit count (bits 27-28): 1, 2, 3 */
  98     IA64_OPND_CNT2c,    /* 2-bit count (bits 30-31): 0, 7, 15, or 16 */
  99     IA64_OPND_CNT5,     /* 5-bit count (bits 14-18) */
 100     IA64_OPND_CNT6,     /* 6-bit count (bits 27-32) */
 101     IA64_OPND_CPOS6a,   /* 6-bit count (63 - bits 20-25) */
 102     IA64_OPND_CPOS6b,   /* 6-bit count (63 - bits 14-19) */
 103     IA64_OPND_CPOS6c,   /* 6-bit count (63 - bits 31-36) */
 104     IA64_OPND_IMM1,     /* signed 1-bit immediate (bit 36) */
 105     IA64_OPND_IMMU2,    /* unsigned 2-bit immediate (bits 13-14) */
 106     IA64_OPND_IMMU5b,   /* unsigned 5-bit immediate (32 + bits 14-18) */
 107     IA64_OPND_IMMU7a,   /* unsigned 7-bit immediate (bits 13-19) */
 108     IA64_OPND_IMMU7b,   /* unsigned 7-bit immediate (bits 20-26) */
 109     IA64_OPND_SOF,      /* 8-bit stack frame size */
 110     IA64_OPND_SOL,      /* 8-bit size of locals */
 111     IA64_OPND_SOR,      /* 6-bit number of rotating registers (scaled by 8) */
 112     IA64_OPND_IMM8,     /* signed 8-bit immediate (bits 13-19 & 36) */
 113     IA64_OPND_IMM8U4,   /* cmp4*u signed 8-bit immediate (bits 13-19 & 36) */
 114     IA64_OPND_IMM8M1,   /* signed 8-bit immediate -1 (bits 13-19 & 36) */
 115     IA64_OPND_IMM8M1U4, /* cmp4*u signed 8-bit immediate -1 (bits 13-19 & 36)*/
 116     IA64_OPND_IMM8M1U8, /* cmp*u signed 8-bit immediate -1 (bits 13-19 & 36) */
 117     IA64_OPND_IMMU9,    /* unsigned 9-bit immediate (bits 33-34, 20-26) */
 118     IA64_OPND_IMM9a,    /* signed 9-bit immediate (bits 6-12, 27, 36) */
 119     IA64_OPND_IMM9b,    /* signed 9-bit immediate (bits 13-19, 27, 36) */
 120     IA64_OPND_IMM14,    /* signed 14-bit immediate (bits 13-19, 27-32, 36) */
 121     IA64_OPND_IMM17,    /* signed 17-bit immediate (2*bits 6-12, 24-31, 36) */
 122     IA64_OPND_IMMU21,   /* unsigned 21-bit immediate (bits 6-25, 36) */
 123     IA64_OPND_IMM22,    /* signed 22-bit immediate (bits 13-19, 22-36) */
 124     IA64_OPND_IMMU24,   /* unsigned 24-bit immediate (bits 6-26, 31-32, 36) */
 125     IA64_OPND_IMM44,    /* signed 44-bit immediate (2^16*bits 6-32, 36) */
 126     IA64_OPND_IMMU62,   /* unsigned 62-bit immediate */
 127     IA64_OPND_IMMU64,   /* unsigned 64-bit immediate (lotsa bits...) */
 128     IA64_OPND_INC3,     /* signed 3-bit (bits 13-15): +/-1, 4, 8, 16 */
 129     IA64_OPND_LEN4,     /* 4-bit count (bits 27-30 + 1) */
 130     IA64_OPND_LEN6,     /* 6-bit count (bits 27-32 + 1) */
 131     IA64_OPND_MBTYPE4,  /* 4-bit mux type (bits 20-23) */
 132     IA64_OPND_MHTYPE8,  /* 8-bit mux type (bits 20-27) */
 133     IA64_OPND_POS6,     /* 6-bit count (bits 14-19) */
 134     IA64_OPND_TAG13,    /* signed 13-bit tag (ip + 16*bits 6-12, 33-34) */
 135     IA64_OPND_TAG13b,   /* signed 13-bit tag (ip + 16*bits 24-32) */
 136     IA64_OPND_TGT25,    /* signed 25-bit (ip + 16*bits 6-25, 36) */
 137     IA64_OPND_TGT25b,   /* signed 25-bit (ip + 16*bits 6-12, 20-32, 36) */
 138     IA64_OPND_TGT25c,   /* signed 25-bit (ip + 16*bits 13-32, 36) */
 139     IA64_OPND_TGT64,    /* 64-bit (ip + 16*bits 13-32, 36, 2-40(L)) */
 140     IA64_OPND_LDXMOV,   /* any symbol, generates R_IA64_LDXMOV.  */
 141
 142     IA64_OPND_COUNT     /* # of operand types (MUST BE LAST!) */
 143   };
 144
 145 enum ia64_dependency_mode
 146 {
 147   IA64_DV_RAW,
 148   IA64_DV_WAW,
 149   IA64_DV_WAR,
 150 };
 151
 152 enum ia64_dependency_semantics
 153 {
 154   IA64_DVS_NONE,
 155   IA64_DVS_IMPLIED,
 156   IA64_DVS_IMPLIEDF,
 157   IA64_DVS_DATA,
 158   IA64_DVS_INSTR,
 159   IA64_DVS_SPECIFIC,
 160   IA64_DVS_STOP,
 161   IA64_DVS_OTHER,
 162 };
 163
 164 enum ia64_resource_specifier
 165 {
 166   IA64_RS_ANY,
 167   IA64_RS_AR_K,
 168   IA64_RS_AR_UNAT,
 169   IA64_RS_AR, /* 8-15, 20, 22-23, 31, 33-35, 37-39, 41-43, 45-47, 67-111 */
 170   IA64_RS_ARb, /* 48-63, 112-127 */
 171   IA64_RS_BR,
 172   IA64_RS_CFM,
 173   IA64_RS_CPUID,
 174   IA64_RS_CR_IIB,
 175   IA64_RS_CR_IRR,
 176   IA64_RS_CR_LRR,
 177   IA64_RS_CR, /* 3-7,10-15,18,28-63,75-79,82-127 */
 178   IA64_RS_DBR,
 179   IA64_RS_FR,
 180   IA64_RS_FRb,
 181   IA64_RS_GR0,
 182   IA64_RS_GR,
 183   IA64_RS_IBR,
 184   IA64_RS_INSERVICE, /* CR[EOI] or CR[IVR] */
 185   IA64_RS_MSR,
 186   IA64_RS_PKR,
 187   IA64_RS_PMC,
 188   IA64_RS_PMD,
 189   IA64_RS_PR,  /* non-rotating, 1-15 */
 190   IA64_RS_PRr, /* rotating, 16-62 */
 191   IA64_RS_PR63,
 192   IA64_RS_RR,
 193
 194   IA64_RS_ARX, /* ARs not in RS_AR or RS_ARb */
 195   IA64_RS_CRX, /* CRs not in RS_CR */
 196   IA64_RS_PSR, /* PSR bits */
 197   IA64_RS_RSE, /* implementation-specific RSE resources */
 198   IA64_RS_AR_FPSR,
 199 };
 200
 201 enum ia64_rse_resource
 202 {
 203   IA64_RSE_N_STACKED_PHYS,
 204   IA64_RSE_BOF,
 205   IA64_RSE_STORE_REG,
 206   IA64_RSE_LOAD_REG,
 207   IA64_RSE_BSPLOAD,
 208   IA64_RSE_RNATBITINDEX,
 209   IA64_RSE_CFLE,
 210   IA64_RSE_NDIRTY,
 211 };
 212
 213 /* Information about a given resource dependency */
 214 struct ia64_dependency
 215 {
 216   /* Name of the resource */
 217   const char *name;
 218   /* Does this dependency need further specification? */
 219   enum ia64_resource_specifier specifier;
 220   /* Mode of dependency */
 221   enum ia64_dependency_mode mode;
 222   /* Dependency semantics */
 223   enum ia64_dependency_semantics semantics;
 224   /* Register index, if applicable (distinguishes AR, CR, and PSR deps) */
 225 #define REG_NONE (-1)
 226   int regindex;
 227   /* Special info on semantics */
 228   const char *info;
 229 };
 230
 231 /* Two arrays of indexes into the ia64_dependency table.
 232    chks are dependencies to check for conflicts when an opcode is
 233    encountered; regs are dependencies to register (mark as used) when an
 234    opcode is used.  chks correspond to readers (RAW) or writers (WAW or
 235    WAR) of a resource, while regs correspond to writers (RAW or WAW) and
 236    readers (WAR) of a resource.  */
 237 struct ia64_opcode_dependency
 238 {
 239   int nchks;
 240   const unsigned short *chks;
 241   int nregs;
 242   const unsigned short *regs;
 243 };
 244
 245 /* encode/extract the note/index for a dependency */
 246 #define RDEP(N,X) (((N)<<11)|(X))
 247 #define NOTE(X) (((X)>>11)&0x1F)
 248 #define DEP(X) ((X)&0x7FF)
 249
 250 /* A template descriptor describes the execution units that are active
 251    for each of the three slots.  It also specifies the location of
 252    instruction group boundaries that may be present between two slots.  */
 253 struct ia64_templ_desc
 254   {
 255     int group_boundary; /* 0=no boundary, 1=between slot 0 & 1, etc. */
 256     enum ia64_unit exec_unit[3];
 257     const char *name;
 258   };
 259
 260 /* The opcode table is an array of struct ia64_opcode.  */
 261
 262 struct ia64_opcode
 263   {
 264     /* The opcode name.  */
 265     const char *name;
 266
 267     /* The type of the instruction: */
 268     enum ia64_insn_type type;
 269
 270     /* Number of output operands: */
 271     int num_outputs;
 272
 273     /* The opcode itself.  Those bits which will be filled in with
 274        operands are zeroes.  */
 275     ia64_insn opcode;
 276
 277     /* The opcode mask.  This is used by the disassembler.  This is a
 278        mask containing ones indicating those bits which must match the
 279        opcode field, and zeroes indicating those bits which need not
 280        match (and are presumably filled in by operands).  */
 281     ia64_insn mask;
 282
 283     /* An array of operand codes.  Each code is an index into the
 284        operand table.  They appear in the order which the operands must
 285        appear in assembly code, and are terminated by a zero.  */
 286     enum ia64_opnd operands[5];
 287
 288     /* One bit flags for the opcode.  These are primarily used to
 289        indicate specific processors and environments support the
 290        instructions.  The defined values are listed below. */
 291     unsigned int flags;
 292
 293     /* Used by ia64_find_next_opcode (). */
 294     short ent_index;
 295
 296     /* Opcode dependencies. */
 297     const struct ia64_opcode_dependency *dependencies;
 298   };
 299
 300 /* Values defined for the flags field of a struct ia64_opcode.  */
 301
 302 #define IA64_OPCODE_FIRST       (1<<0)  /* must be first in an insn group */
 303 #define IA64_OPCODE_X_IN_MLX    (1<<1)  /* insn is allowed in X slot of MLX */
 304 #define IA64_OPCODE_LAST        (1<<2)  /* must be last in an insn group */
 305 #define IA64_OPCODE_PRIV        (1<<3)  /* privileged instruct */
 306 #define IA64_OPCODE_SLOT2       (1<<4)  /* insn allowed in slot 2 only */
 307 #define IA64_OPCODE_NO_PRED     (1<<5)  /* insn cannot be predicated */
 308 #define IA64_OPCODE_PSEUDO      (1<<6)  /* insn is a pseudo-op */
 309 #define IA64_OPCODE_F2_EQ_F3    (1<<7)  /* constraint: F2 == F3 */
 310 #define IA64_OPCODE_LEN_EQ_64MCNT       (1<<8)  /* constraint: LEN == 64-CNT */
 311 #define IA64_OPCODE_MOD_RRBS    (1<<9)  /* modifies all rrbs in CFM */
 312 #define IA64_OPCODE_POSTINC     (1<<10) /* postincrement MR3 operand */
 313
 314 /* A macro to extract the major opcode from an instruction.  */
 315 #define IA64_OP(i)      (((i) >> 37) & 0xf)
 316
 317 enum ia64_operand_class
 318   {
 319     IA64_OPND_CLASS_CST,        /* constant */
 320     IA64_OPND_CLASS_REG,        /* register */
 321     IA64_OPND_CLASS_IND,        /* indirect register */
 322     IA64_OPND_CLASS_ABS,        /* absolute value */
 323     IA64_OPND_CLASS_REL,        /* IP-relative value */
 324   };
 325
 326 /* The operands table is an array of struct ia64_operand.  */
 327
 328 struct ia64_operand
 329 {
 330   enum ia64_operand_class class;
 331
 332   /* Set VALUE as the operand bits for the operand of type SELF in the
 333      instruction pointed to by CODE.  If an error occurs, *CODE is not
 334      modified and the returned string describes the cause of the
 335      error.  If no error occurs, NULL is returned.  */
 336   const char *(*insert) (const struct ia64_operand *self, ia64_insn value,
 337                          ia64_insn *code);
 338
 339   /* Extract the operand bits for an operand of type SELF from
 340      instruction CODE store them in *VALUE.  If an error occurs, the
 341      cause of the error is described by the string returned.  If no
 342      error occurs, NULL is returned.  */
 343   const char *(*extract) (const struct ia64_operand *self, ia64_insn code,
 344                           ia64_insn *value);
 345
 346   /* A string whose meaning depends on the operand class.  */
 347
 348   const char *str;
 349
 350   struct bit_field
 351     {
 352       /* The number of bits in the operand.  */
 353       int bits;
 354
 355       /* How far the operand is left shifted in the instruction.  */
 356       int shift;
 357     }
 358   field[4];             /* no operand has more than this many bit-fields */
 359
 360   unsigned int flags;
 361
 362   const char *desc;     /* brief description */
 363 };
 364
 365 /* Values defined for the flags field of a struct ia64_operand.  */
 366
 367 /* Disassemble as signed decimal (instead of hex): */
 368 #define IA64_OPND_FLAG_DECIMAL_SIGNED   (1<<0)
 369 /* Disassemble as unsigned decimal (instead of hex): */
 370 #define IA64_OPND_FLAG_DECIMAL_UNSIGNED (1<<1)
 371
 372 extern const struct ia64_templ_desc ia64_templ_desc[16];
 373
 374 /* The tables are sorted by major opcode number and are otherwise in
 375    the order in which the disassembler should consider instructions.  */
 376 extern struct ia64_opcode ia64_opcodes_a[];
 377 extern struct ia64_opcode ia64_opcodes_i[];
 378 extern struct ia64_opcode ia64_opcodes_m[];
 379 extern struct ia64_opcode ia64_opcodes_b[];
 380 extern struct ia64_opcode ia64_opcodes_f[];
 381 extern struct ia64_opcode ia64_opcodes_d[];
 382
 383
 384 extern struct ia64_opcode *ia64_find_opcode (const char *name);
 385 extern struct ia64_opcode *ia64_find_next_opcode (struct ia64_opcode *ent);
 386
 387 extern struct ia64_opcode *ia64_dis_opcode (ia64_insn insn,
 388                                             enum ia64_insn_type type);
 389
 390 extern void ia64_free_opcode (struct ia64_opcode *ent);
 391 extern const struct ia64_dependency *ia64_find_dependency (int index);
 392
 393 /* To avoid circular library dependencies, this array is implemented
 394    in bfd/cpu-ia64-opc.c: */
 395 extern const struct ia64_operand elf64_ia64_operands[IA64_OPND_COUNT];
 396
 397 #endif /* opcode_ia64_h */