include/opcode/v850.h

   1 /* v850.h -- Header file for NEC V850 opcode table
   2    Copyright 1996, 1997, 2001, 2003 Free Software Foundation, Inc.
   3    Written by J.T. Conklin, Cygnus Support
   4
   5 This file is part of GDB, GAS, and the GNU binutils.
   6
   7 GDB, GAS, and the GNU binutils are free software; you can redistribute
   8 them and/or modify them under the terms of the GNU General Public
   9 License as published by the Free Software Foundation; either version
  10 1, or (at your option) any later version.
  11
  12 GDB, GAS, and the GNU binutils are distributed in the hope that they
  13 will be useful, but WITHOUT ANY WARRANTY; without even the implied
  14 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
  15 the GNU General Public License for more details.
  16
  17 You should have received a copy of the GNU General Public License
  18 along with this file; see the file COPYING.  If not, write to the Free
  19 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
  20
  21 #ifndef V850_H
  22 #define V850_H
  23
  24 /* The opcode table is an array of struct v850_opcode.  */
  25
  26 struct v850_opcode
  27 {
  28   /* The opcode name.  */
  29   const char *name;
  30
  31   /* The opcode itself.  Those bits which will be filled in with
  32      operands are zeroes.  */
  33   unsigned long opcode;
  34
  35   /* The opcode mask.  This is used by the disassembler.  This is a
  36      mask containing ones indicating those bits which must match the
  37      opcode field, and zeroes indicating those bits which need not
  38      match (and are presumably filled in by operands).  */
  39   unsigned long mask;
  40
  41   /* An array of operand codes.  Each code is an index into the
  42      operand table.  They appear in the order which the operands must
  43      appear in assembly code, and are terminated by a zero.  */
  44   unsigned char operands[8];
  45
  46   /* Which (if any) operand is a memory operand.  */
  47   unsigned int memop;
  48
  49   /* Target processor(s).  A bit field of processors which support
  50      this instruction.  Note a bit field is used as some instructions
  51      are available on multiple, different processor types, whereas
  52      other instructions are only available on one specific type.  */
  53   unsigned int processors;
  54 };
  55
  56 /* Values for the processors field in the v850_opcode structure.  */
  57 #define PROCESSOR_V850          (1 << 0)                /* Just the V850.  */
  58 #define PROCESSOR_ALL           -1                      /* Any processor.  */
  59 #define PROCESSOR_V850E         (1 << 1)                /* Just the V850E. */
  60 #define PROCESSOR_NOT_V850      (~ PROCESSOR_V850)      /* Any processor except the V850.  */
  61 #define PROCESSOR_V850EA        (1 << 2)                /* Just the V850EA. */
  62 #define PROCESSOR_V850E1        (1 << 3)                /* Just the V850E1. */
  63
  64 /* The table itself is sorted by major opcode number, and is otherwise
  65    in the order in which the disassembler should consider
  66    instructions.  */
  67 extern const struct v850_opcode v850_opcodes[];
  68 extern const int v850_num_opcodes;
  69
  70 \f
  71 /* The operands table is an array of struct v850_operand.  */
  72
  73 struct v850_operand
  74 {
  75   /* The number of bits in the operand.  */
  76   /* If this value is -1 then the operand's bits are in a discontinous distribution in the instruction. */
  77   int bits;
  78
  79   /* (bits >= 0):  How far the operand is left shifted in the instruction.  */
  80   /* (bits == -1): Bit mask of the bits in the operand.  */
  81   int shift;
  82
  83   /* Insertion function.  This is used by the assembler.  To insert an
  84      operand value into an instruction, check this field.
  85
  86      If it is NULL, execute
  87          i |= (op & ((1 << o->bits) - 1)) << o->shift;
  88      (i is the instruction which we are filling in, o is a pointer to
  89      this structure, and op is the opcode value; this assumes twos
  90      complement arithmetic).
  91
  92      If this field is not NULL, then simply call it with the
  93      instruction and the operand value.  It will return the new value
  94      of the instruction.  If the ERRMSG argument is not NULL, then if
  95      the operand value is illegal, *ERRMSG will be set to a warning
  96      string (the operand will be inserted in any case).  If the
  97      operand value is legal, *ERRMSG will be unchanged (most operands
  98      can accept any value).  */
  99   unsigned long (* insert)
 100     (unsigned long instruction, long op, const char ** errmsg);
 101
 102   /* Extraction function.  This is used by the disassembler.  To
 103      extract this operand type from an instruction, check this field.
 104
 105      If it is NULL, compute
 106          op = o->bits == -1 ? ((i) & o->shift) : ((i) >> o->shift) & ((1 << o->bits) - 1);
 107          if (o->flags & V850_OPERAND_SIGNED)
 108              op = (op << (32 - o->bits)) >> (32 - o->bits);
 109      (i is the instruction, o is a pointer to this structure, and op
 110      is the result; this assumes twos complement arithmetic).
 111
 112      If this field is not NULL, then simply call it with the
 113      instruction value.  It will return the value of the operand.  If
 114      the INVALID argument is not NULL, *INVALID will be set to
 115      non-zero if this operand type can not actually be extracted from
 116      this operand (i.e., the instruction does not match).  If the
 117      operand is valid, *INVALID will not be changed.  */
 118   unsigned long (* extract) (unsigned long instruction, int * invalid);
 119
 120   /* One bit syntax flags.  */
 121   int flags;
 122 };
 123
 124 /* Elements in the table are retrieved by indexing with values from
 125    the operands field of the v850_opcodes table.  */
 126
 127 extern const struct v850_operand v850_operands[];
 128
 129 /* Values defined for the flags field of a struct v850_operand.  */
 130
 131 /* This operand names a general purpose register */
 132 #define V850_OPERAND_REG        0x01
 133
 134 /* This operand names a system register */
 135 #define V850_OPERAND_SRG        0x02
 136
 137 /* This operand names a condition code used in the setf instruction */
 138 #define V850_OPERAND_CC         0x04
 139
 140 /* This operand takes signed values */
 141 #define V850_OPERAND_SIGNED     0x08
 142
 143 /* This operand is the ep register.  */
 144 #define V850_OPERAND_EP         0x10
 145
 146 /* This operand is a PC displacement */
 147 #define V850_OPERAND_DISP       0x20
 148
 149 /* This is a relaxable operand.   Only used for D9->D22 branch relaxing
 150    right now.  We may need others in the future (or maybe handle them like
 151    promoted operands on the mn10300?)  */
 152 #define V850_OPERAND_RELAX      0x40
 153
 154 /* The register specified must not be r0 */
 155 #define V850_NOT_R0             0x80
 156
 157 /* push/pop type instruction, V850E specific.  */
 158 #define V850E_PUSH_POP          0x100
 159
 160 /* 16 bit immediate follows instruction, V850E specific.  */
 161 #define V850E_IMMEDIATE16       0x200
 162
 163 /* 32 bit immediate follows instruction, V850E specific.  */
 164 #define V850E_IMMEDIATE32       0x400
 165
 166 #endif /* V850_H */