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* elf32-spu.c (build_stub): Fix malloc under-allocation.
[binutils.git] / gas / config / tc-m32c.c
blob9c523e27811d9f154520fbdf09ef66bd43117b1a
1 /* tc-m32c.c -- Assembler for the Renesas M32C.
2 Copyright (C) 2005, 2006, 2007, 2008, 2009, 2010 Free Software Foundation.
3 Contributed by RedHat.
4
5 This file is part of GAS, the GNU Assembler.
6
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
10 any later version.
11
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
21
22 #include "as.h"
23 #include "subsegs.h"
24 #include "symcat.h"
25 #include "opcodes/m32c-desc.h"
26 #include "opcodes/m32c-opc.h"
27 #include "cgen.h"
28 #include "elf/common.h"
29 #include "elf/m32c.h"
30 #include "libbfd.h"
31 #include "safe-ctype.h"
32
33 /* Structure to hold all of the different components
34 describing an individual instruction. */
35 typedef struct
36 {
37 const CGEN_INSN * insn;
38 const CGEN_INSN * orig_insn;
39 CGEN_FIELDS fields;
40 #if CGEN_INT_INSN_P
41 CGEN_INSN_INT buffer [1];
42 #define INSN_VALUE(buf) (*(buf))
43 #else
44 unsigned char buffer [CGEN_MAX_INSN_SIZE];
45 #define INSN_VALUE(buf) (buf)
46 #endif
47 char * addr;
48 fragS * frag;
49 int num_fixups;
50 fixS * fixups [GAS_CGEN_MAX_FIXUPS];
51 int indices [MAX_OPERAND_INSTANCES];
52 }
53 m32c_insn;
54
55 #define rl_for(_insn) (CGEN_ATTR_CGEN_INSN_RL_TYPE_VALUE (&((_insn).insn->base->attrs)))
56 #define relaxable(_insn) (CGEN_ATTR_CGEN_INSN_RELAXABLE_VALUE (&((_insn).insn->base->attrs)))
57
58 const char comment_chars[] = ";";
59 const char line_comment_chars[] = "#";
60 const char line_separator_chars[] = "|";
61 const char EXP_CHARS[] = "eE";
62 const char FLT_CHARS[] = "dD";
63 \f
64 #define M32C_SHORTOPTS ""
65 const char * md_shortopts = M32C_SHORTOPTS;
66
67 /* assembler options */
68 #define OPTION_CPU_M16C (OPTION_MD_BASE)
69 #define OPTION_CPU_M32C (OPTION_MD_BASE + 1)
70 #define OPTION_LINKRELAX (OPTION_MD_BASE + 2)
71 #define OPTION_H_TICK_HEX (OPTION_MD_BASE + 3)
72
73 struct option md_longopts[] =
74 {
75 { "m16c", no_argument, NULL, OPTION_CPU_M16C },
76 { "m32c", no_argument, NULL, OPTION_CPU_M32C },
77 { "relax", no_argument, NULL, OPTION_LINKRELAX },
78 { "h-tick-hex", no_argument, NULL, OPTION_H_TICK_HEX },
79 {NULL, no_argument, NULL, 0}
80 };
81 size_t md_longopts_size = sizeof (md_longopts);
82
83 /* Default machine */
84
85 #define DEFAULT_MACHINE bfd_mach_m16c
86 #define DEFAULT_FLAGS EF_M32C_CPU_M16C
87
88 static unsigned long m32c_mach = bfd_mach_m16c;
89 static int cpu_mach = (1 << MACH_M16C);
90 static int insn_size;
91 static int m32c_relax = 0;
92
93 /* Flags to set in the elf header */
94 static flagword m32c_flags = DEFAULT_FLAGS;
95
96 static char default_isa = 1 << (7 - ISA_M16C);
97 static CGEN_BITSET m32c_isa = {1, & default_isa};
98
99 static void
100 set_isa (enum isa_attr isa_num)
101 {
102 cgen_bitset_set (& m32c_isa, isa_num);
103 }
104
105 static void s_bss (int);
106
107 int
108 md_parse_option (int c, char * arg ATTRIBUTE_UNUSED)
109 {
110 switch (c)
111 {
112 case OPTION_CPU_M16C:
113 m32c_flags = (m32c_flags & ~EF_M32C_CPU_MASK) | EF_M32C_CPU_M16C;
114 m32c_mach = bfd_mach_m16c;
115 cpu_mach = (1 << MACH_M16C);
116 set_isa (ISA_M16C);
117 break;
118
119 case OPTION_CPU_M32C:
120 m32c_flags = (m32c_flags & ~EF_M32C_CPU_MASK) | EF_M32C_CPU_M32C;
121 m32c_mach = bfd_mach_m32c;
122 cpu_mach = (1 << MACH_M32C);
123 set_isa (ISA_M32C);
124 break;
125
126 case OPTION_LINKRELAX:
127 m32c_relax = 1;
128 break;
129
130 case OPTION_H_TICK_HEX:
131 enable_h_tick_hex = 1;
132 break;
133
134 default:
135 return 0;
136 }
137 return 1;
138 }
139
140 void
141 md_show_usage (FILE * stream)
142 {
143 fprintf (stream, _(" M32C specific command line options:\n"));
144 }
145
146 static void
147 s_bss (int ignore ATTRIBUTE_UNUSED)
148 {
149 int temp;
150
151 temp = get_absolute_expression ();
152 subseg_set (bss_section, (subsegT) temp);
153 demand_empty_rest_of_line ();
154 }
155
156 /* The target specific pseudo-ops which we support. */
157 const pseudo_typeS md_pseudo_table[] =
158 {
159 { "bss", s_bss, 0},
160 { "3byte", cons, 3 },
161 { "word", cons, 4 },
162 { NULL, NULL, 0 }
163 };
164
165 \f
166 void
167 md_begin (void)
168 {
169 /* Initialize the `cgen' interface. */
170
171 /* Set the machine number and endian. */
172 gas_cgen_cpu_desc = m32c_cgen_cpu_open (CGEN_CPU_OPEN_MACHS, cpu_mach,
173 CGEN_CPU_OPEN_ENDIAN,
174 CGEN_ENDIAN_BIG,
175 CGEN_CPU_OPEN_ISAS, & m32c_isa,
176 CGEN_CPU_OPEN_END);
177
178 m32c_cgen_init_asm (gas_cgen_cpu_desc);
179
180 /* This is a callback from cgen to gas to parse operands. */
181 cgen_set_parse_operand_fn (gas_cgen_cpu_desc, gas_cgen_parse_operand);
182
183 /* Set the ELF flags if desired. */
184 if (m32c_flags)
185 bfd_set_private_flags (stdoutput, m32c_flags);
186
187 /* Set the machine type */
188 bfd_default_set_arch_mach (stdoutput, bfd_arch_m32c, m32c_mach);
189
190 insn_size = 0;
191 }
192
193 void
194 m32c_md_end (void)
195 {
196 int i, n_nops;
197
198 if (bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE)
199 {
200 /* Pad with nops for objdump. */
201 n_nops = (32 - ((insn_size) % 32)) / 8;
202 for (i = 1; i <= n_nops; i++)
203 md_assemble ("nop");
204 }
205 }
206
207 void
208 m32c_start_line_hook (void)
209 {
210 #if 0 /* not necessary....handled in the .cpu file */
211 char *s = input_line_pointer;
212 char *sg;
213
214 for (s = input_line_pointer ; s && s[0] != '\n'; s++)
215 {
216 if (s[0] == ':')
217 {
218 /* Remove :g suffix. Squeeze out blanks. */
219 if (s[1] == 'g')
220 {
221 for (sg = s - 1; sg && sg >= input_line_pointer; sg--)
222 {
223 sg[2] = sg[0];
224 }
225 sg[1] = ' ';
226 sg[2] = ' ';
227 input_line_pointer += 2;
228 }
229 }
230 }
231 #endif
232 }
233
234 /* Process [[indirect-operands]] in instruction str. */
235
236 static bfd_boolean
237 m32c_indirect_operand (char *str)
238 {
239 char *new_str;
240 char *s;
241 char *ns;
242 int ns_len;
243 char *ns_end;
244 enum indirect_type {none, relative, absolute} ;
245 enum indirect_type indirection [3] = { none, none, none };
246 int brace_n [3] = { 0, 0, 0 };
247 int operand;
248
249 s = str;
250 operand = 1;
251 for (s = str; *s; s++)
252 {
253 if (s[0] == ',')
254 operand = 2;
255 /* [abs] where abs is not a0 or a1 */
256 if (s[1] == '[' && ! (s[2] == 'a' && (s[3] == '0' || s[3] == '1'))
257 && (ISBLANK (s[0]) || s[0] == ','))
258 indirection[operand] = absolute;
259 if (s[0] == ']' && s[1] == ']')
260 indirection[operand] = relative;
261 if (s[0] == '[' && s[1] == '[')
262 indirection[operand] = relative;
263 }
264
265 if (indirection[1] == none && indirection[2] == none)
266 return FALSE;
267
268 operand = 1;
269 ns_len = strlen (str);
270 new_str = (char*) xmalloc (ns_len);
271 ns = new_str;
272 ns_end = ns + ns_len;
273
274 for (s = str; *s; s++)
275 {
276 if (s[0] == ',')
277 operand = 2;
278
279 if (s[0] == '[' && ! brace_n[operand])
280 {
281 brace_n[operand] += 1;
282 /* Squeeze [[ to [ if this is an indirect operand. */
283 if (indirection[operand] != none)
284 continue;
285 }
286
287 else if (s[0] == '[' && brace_n[operand])
288 {
289 brace_n[operand] += 1;
290 }
291 else if (s[0] == ']' && s[1] == ']' && indirection[operand] == relative)
292 {
293 s += 1; /* skip one ]. */
294 brace_n[operand] -= 2; /* allow for 2 [. */
295 }
296 else if (s[0] == ']' && indirection[operand] == absolute)
297 {
298 brace_n[operand] -= 1;
299 continue; /* skip closing ]. */
300 }
301 else if (s[0] == ']')
302 {
303 brace_n[operand] -= 1;
304 }
305 *ns = s[0];
306 ns += 1;
307 if (ns >= ns_end)
308 return FALSE;
309 if (s[0] == 0)
310 break;
311 }
312 *ns = '\0';
313 for (operand = 1; operand <= 2; operand++)
314 if (brace_n[operand])
315 {
316 fprintf (stderr, "Unmatched [[operand-%d]] %d\n", operand, brace_n[operand]);
317 }
318
319 if (indirection[1] != none && indirection[2] != none)
320 md_assemble ("src-dest-indirect");
321 else if (indirection[1] != none)
322 md_assemble ("src-indirect");
323 else if (indirection[2] != none)
324 md_assemble ("dest-indirect");
325
326 md_assemble (new_str);
327 free (new_str);
328 return TRUE;
329 }
330
331 void
332 md_assemble (char * str)
333 {
334 static int last_insn_had_delay_slot = 0;
335 m32c_insn insn;
336 char * errmsg;
337 finished_insnS results;
338 int rl_type;
339
340 if (m32c_mach == bfd_mach_m32c && m32c_indirect_operand (str))
341 return;
342
343 /* Initialize GAS's cgen interface for a new instruction. */
344 gas_cgen_init_parse ();
345
346 insn.insn = m32c_cgen_assemble_insn
347 (gas_cgen_cpu_desc, str, & insn.fields, insn.buffer, & errmsg);
348
349 if (!insn.insn)
350 {
351 as_bad ("%s", errmsg);
352 return;
353 }
354
355 results.num_fixups = 0;
356 /* Doesn't really matter what we pass for RELAX_P here. */
357 gas_cgen_finish_insn (insn.insn, insn.buffer,
358 CGEN_FIELDS_BITSIZE (& insn.fields), 1, &results);
359
360 last_insn_had_delay_slot
361 = CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_DELAY_SLOT);
362 (void) last_insn_had_delay_slot;
363 insn_size = CGEN_INSN_BITSIZE(insn.insn);
364
365 rl_type = rl_for (insn);
366
367 /* We have to mark all the jumps, because we need to adjust them
368 when we delete bytes, but we only need to mark the displacements
369 if they're symbolic - if they're not, we've already picked the
370 shortest opcode by now. The linker, however, will still have to
371 check any operands to see if they're the displacement type, since
372 we don't know (nor record) *which* operands are relaxable. */
373 if (m32c_relax
374 && rl_type != RL_TYPE_NONE
375 && (rl_type == RL_TYPE_JUMP || results.num_fixups)
376 && !relaxable (insn))
377 {
378 int reloc = 0;
379 int addend = results.num_fixups + 16 * insn_size/8;
380
381 switch (rl_for (insn))
382 {
383 case RL_TYPE_JUMP: reloc = BFD_RELOC_M32C_RL_JUMP; break;
384 case RL_TYPE_1ADDR: reloc = BFD_RELOC_M32C_RL_1ADDR; break;
385 case RL_TYPE_2ADDR: reloc = BFD_RELOC_M32C_RL_2ADDR; break;
386 }
387 if (insn.insn->base->num == M32C_INSN_JMP16_S
388 || insn.insn->base->num == M32C_INSN_JMP32_S)
389 addend = 0x10;
390
391 fix_new (results.frag,
392 results.addr - results.frag->fr_literal,
393 0, abs_section_sym, addend, 0,
394 reloc);
395 }
396 }
397
398 /* The syntax in the manual says constants begin with '#'.
399 We just ignore it. */
400
401 void
402 md_operand (expressionS * exp)
403 {
404 /* In case of a syntax error, escape back to try next syntax combo. */
405 if (exp->X_op == O_absent)
406 gas_cgen_md_operand (exp);
407 }
408
409 valueT
410 md_section_align (segT segment, valueT size)
411 {
412 int align = bfd_get_section_alignment (stdoutput, segment);
413 return ((size + (1 << align) - 1) & (-1 << align));
414 }
415
416 symbolS *
417 md_undefined_symbol (char * name ATTRIBUTE_UNUSED)
418 {
419 return 0;
420 }
421 \f
422 const relax_typeS md_relax_table[] =
423 {
424 /* The fields are:
425 1) most positive reach of this state,
426 2) most negative reach of this state,
427 3) how many bytes this mode will have in the variable part of the frag
428 4) which index into the table to try if we can't fit into this one. */
429
430 /* 0 */ { 0, 0, 0, 0 }, /* unused */
431 /* 1 */ { 0, 0, 0, 0 }, /* marker for "don't know yet" */
432
433 /* 2 */ { 127, -128, 2, 3 }, /* jcnd16_5.b */
434 /* 3 */ { 32767, -32768, 5, 4 }, /* jcnd16_5.w */
435 /* 4 */ { 0, 0, 6, 0 }, /* jcnd16_5.a */
436
437 /* 5 */ { 127, -128, 2, 6 }, /* jcnd16.b */
438 /* 6 */ { 32767, -32768, 5, 7 }, /* jcnd16.w */
439 /* 7 */ { 0, 0, 6, 0 }, /* jcnd16.a */
440
441 /* 8 */ { 8, 1, 1, 9 }, /* jmp16.s */
442 /* 9 */ { 127, -128, 2, 10 }, /* jmp16.b */
443 /* 10 */ { 32767, -32768, 3, 11 }, /* jmp16.w */
444 /* 11 */ { 0, 0, 4, 0 }, /* jmp16.a */
445
446 /* 12 */ { 127, -128, 2, 13 }, /* jcnd32.b */
447 /* 13 */ { 32767, -32768, 5, 14 }, /* jcnd32.w */
448 /* 14 */ { 0, 0, 6, 0 }, /* jcnd32.a */
449
450 /* 15 */ { 8, 1, 1, 16 }, /* jmp32.s */
451 /* 16 */ { 127, -128, 2, 17 }, /* jmp32.b */
452 /* 17 */ { 32767, -32768, 3, 18 }, /* jmp32.w */
453 /* 18 */ { 0, 0, 4, 0 }, /* jmp32.a */
454
455 /* 19 */ { 32767, -32768, 3, 20 }, /* jsr16.w */
456 /* 20 */ { 0, 0, 4, 0 }, /* jsr16.a */
457 /* 21 */ { 32767, -32768, 3, 11 }, /* jsr32.w */
458 /* 22 */ { 0, 0, 4, 0 }, /* jsr32.a */
459
460 /* 23 */ { 0, 0, 3, 0 }, /* adjnz pc8 */
461 /* 24 */ { 0, 0, 4, 0 }, /* adjnz disp8 pc8 */
462 /* 25 */ { 0, 0, 5, 0 }, /* adjnz disp16 pc8 */
463 /* 26 */ { 0, 0, 6, 0 } /* adjnz disp24 pc8 */
464 };
465
466 enum {
467 M32C_MACRO_JCND16_5_W,
468 M32C_MACRO_JCND16_5_A,
469 M32C_MACRO_JCND16_W,
470 M32C_MACRO_JCND16_A,
471 M32C_MACRO_JCND32_W,
472 M32C_MACRO_JCND32_A,
473 /* the digit is the array index of the pcrel byte */
474 M32C_MACRO_ADJNZ_2,
475 M32C_MACRO_ADJNZ_3,
476 M32C_MACRO_ADJNZ_4,
477 M32C_MACRO_ADJNZ_5,
478 } M32C_Macros;
479
480 static struct {
481 int insn;
482 int bytes;
483 int insn_for_extern;
484 int pcrel_aim_offset;
485 } subtype_mappings[] = {
486 /* 0 */ { 0, 0, 0, 0 },
487 /* 1 */ { 0, 0, 0, 0 },
488
489 /* 2 */ { M32C_INSN_JCND16_5, 2, -M32C_MACRO_JCND16_5_A, 1 },
490 /* 3 */ { -M32C_MACRO_JCND16_5_W, 5, -M32C_MACRO_JCND16_5_A, 4 },
491 /* 4 */ { -M32C_MACRO_JCND16_5_A, 6, -M32C_MACRO_JCND16_5_A, 0 },
492
493 /* 5 */ { M32C_INSN_JCND16, 3, -M32C_MACRO_JCND16_A, 1 },
494 /* 6 */ { -M32C_MACRO_JCND16_W, 6, -M32C_MACRO_JCND16_A, 4 },
495 /* 7 */ { -M32C_MACRO_JCND16_A, 7, -M32C_MACRO_JCND16_A, 0 },
496
497 /* 8 */ { M32C_INSN_JMP16_S, 1, M32C_INSN_JMP16_A, 0 },
498 /* 9 */ { M32C_INSN_JMP16_B, 2, M32C_INSN_JMP16_A, 1 },
499 /* 10 */ { M32C_INSN_JMP16_W, 3, M32C_INSN_JMP16_A, 2 },
500 /* 11 */ { M32C_INSN_JMP16_A, 4, M32C_INSN_JMP16_A, 0 },
501
502 /* 12 */ { M32C_INSN_JCND32, 2, -M32C_MACRO_JCND32_A, 1 },
503 /* 13 */ { -M32C_MACRO_JCND32_W, 5, -M32C_MACRO_JCND32_A, 4 },
504 /* 14 */ { -M32C_MACRO_JCND32_A, 6, -M32C_MACRO_JCND32_A, 0 },
505
506 /* 15 */ { M32C_INSN_JMP32_S, 1, M32C_INSN_JMP32_A, 0 },
507 /* 16 */ { M32C_INSN_JMP32_B, 2, M32C_INSN_JMP32_A, 1 },
508 /* 17 */ { M32C_INSN_JMP32_W, 3, M32C_INSN_JMP32_A, 2 },
509 /* 18 */ { M32C_INSN_JMP32_A, 4, M32C_INSN_JMP32_A, 0 },
510
511 /* 19 */ { M32C_INSN_JSR16_W, 3, M32C_INSN_JSR16_A, 2 },
512 /* 20 */ { M32C_INSN_JSR16_A, 4, M32C_INSN_JSR16_A, 0 },
513 /* 21 */ { M32C_INSN_JSR32_W, 3, M32C_INSN_JSR32_A, 2 },
514 /* 22 */ { M32C_INSN_JSR32_A, 4, M32C_INSN_JSR32_A, 0 },
515
516 /* 23 */ { -M32C_MACRO_ADJNZ_2, 3, -M32C_MACRO_ADJNZ_2, 0 },
517 /* 24 */ { -M32C_MACRO_ADJNZ_3, 4, -M32C_MACRO_ADJNZ_3, 0 },
518 /* 25 */ { -M32C_MACRO_ADJNZ_4, 5, -M32C_MACRO_ADJNZ_4, 0 },
519 /* 26 */ { -M32C_MACRO_ADJNZ_5, 6, -M32C_MACRO_ADJNZ_5, 0 }
520 };
521 #define NUM_MAPPINGS (sizeof (subtype_mappings) / sizeof (subtype_mappings[0]))
522
523 void
524 m32c_prepare_relax_scan (fragS *fragP, offsetT *aim, relax_substateT this_state)
525 {
526 symbolS *symbolP = fragP->fr_symbol;
527 if (symbolP && !S_IS_DEFINED (symbolP))
528 *aim = 0;
529 /* Adjust for m32c pcrel not being relative to the next opcode. */
530 *aim += subtype_mappings[this_state].pcrel_aim_offset;
531 }
532
533 static int
534 insn_to_subtype (int inum, const CGEN_INSN *insn)
535 {
536 unsigned int i;
537
538 if (insn
539 && (strncmp (insn->base->mnemonic, "adjnz", 5) == 0
540 || strncmp (insn->base->mnemonic, "sbjnz", 5) == 0))
541 {
542 i = 23 + insn->base->bitsize/8 - 3;
543 /*printf("mapping %d used for %s\n", i, insn->base->mnemonic);*/
544 return i;
545 }
546
547 for (i=0; i<NUM_MAPPINGS; i++)
548 if (inum == subtype_mappings[i].insn)
549 {
550 /*printf("mapping %d used\n", i);*/
551 return i;
552 }
553 abort ();
554 }
555
556 /* Return an initial guess of the length by which a fragment must grow to
557 hold a branch to reach its destination.
558 Also updates fr_type/fr_subtype as necessary.
559
560 Called just before doing relaxation.
561 Any symbol that is now undefined will not become defined.
562 The guess for fr_var is ACTUALLY the growth beyond fr_fix.
563 Whatever we do to grow fr_fix or fr_var contributes to our returned value.
564 Although it may not be explicit in the frag, pretend fr_var starts with a
565 0 value. */
566
567 int
568 md_estimate_size_before_relax (fragS * fragP, segT segment ATTRIBUTE_UNUSED)
569 {
570 int where = fragP->fr_opcode - fragP->fr_literal;
571
572 if (fragP->fr_subtype == 1)
573 fragP->fr_subtype = insn_to_subtype (fragP->fr_cgen.insn->base->num, fragP->fr_cgen.insn);
574
575 if (S_GET_SEGMENT (fragP->fr_symbol) != segment)
576 {
577 int new_insn;
578
579 new_insn = subtype_mappings[fragP->fr_subtype].insn_for_extern;
580 fragP->fr_subtype = insn_to_subtype (new_insn, 0);
581 }
582
583 if (fragP->fr_cgen.insn->base
584 && fragP->fr_cgen.insn->base->num
585 != subtype_mappings[fragP->fr_subtype].insn
586 && subtype_mappings[fragP->fr_subtype].insn > 0)
587 {
588 int new_insn= subtype_mappings[fragP->fr_subtype].insn;
589 if (new_insn >= 0)
590 {
591 fragP->fr_cgen.insn = (fragP->fr_cgen.insn
592 - fragP->fr_cgen.insn->base->num
593 + new_insn);
594 }
595 }
596
597 return subtype_mappings[fragP->fr_subtype].bytes - (fragP->fr_fix - where);
598 }
599
600 /* *fragP has been relaxed to its final size, and now needs to have
601 the bytes inside it modified to conform to the new size.
602
603 Called after relaxation is finished.
604 fragP->fr_type == rs_machine_dependent.
605 fragP->fr_subtype is the subtype of what the address relaxed to. */
606
607 static int
608 target_address_for (fragS *frag)
609 {
610 int rv = frag->fr_offset;
611 symbolS *sym = frag->fr_symbol;
612
613 if (sym)
614 rv += S_GET_VALUE (sym);
615
616 /*printf("target_address_for returns %d\n", rv);*/
617 return rv;
618 }
619
620 void
621 md_convert_frag (bfd * abfd ATTRIBUTE_UNUSED,
622 segT sec ATTRIBUTE_UNUSED,
623 fragS * fragP ATTRIBUTE_UNUSED)
624 {
625 int addend;
626 int operand;
627 int where = fragP->fr_opcode - fragP->fr_literal;
628 int rl_where = fragP->fr_opcode - fragP->fr_literal;
629 unsigned char *op = (unsigned char *)fragP->fr_opcode;
630 int rl_addend = 0;
631
632 addend = target_address_for (fragP) - (fragP->fr_address + where);
633
634 fragP->fr_fix = where + subtype_mappings[fragP->fr_subtype].bytes;
635
636 switch (subtype_mappings[fragP->fr_subtype].insn)
637 {
638 case M32C_INSN_JCND16_5:
639 op[1] = addend - 1;
640 operand = M32C_OPERAND_LAB_8_8;
641 rl_addend = 0x21;
642 break;
643
644 case -M32C_MACRO_JCND16_5_W:
645 op[0] ^= 0x04;
646 op[1] = 4;
647 op[2] = 0xf4;
648 op[3] = addend - 3;
649 op[4] = (addend - 3) >> 8;
650 operand = M32C_OPERAND_LAB_8_16;
651 where += 2;
652 rl_addend = 0x51;
653 break;
654
655 case -M32C_MACRO_JCND16_5_A:
656 op[0] ^= 0x04;
657 op[1] = 5;
658 op[2] = 0xfc;
659 operand = M32C_OPERAND_LAB_8_24;
660 where += 2;
661 rl_addend = 0x61;
662 break;
663
664
665 case M32C_INSN_JCND16:
666 op[2] = addend - 2;
667 operand = M32C_OPERAND_LAB_16_8;
668 rl_addend = 0x31;
669 break;
670
671 case -M32C_MACRO_JCND16_W:
672 op[1] ^= 0x04;
673 op[2] = 4;
674 op[3] = 0xf4;
675 op[4] = addend - 4;
676 op[5] = (addend - 4) >> 8;
677 operand = M32C_OPERAND_LAB_8_16;
678 where += 3;
679 rl_addend = 0x61;
680 break;
681
682 case -M32C_MACRO_JCND16_A:
683 op[1] ^= 0x04;
684 op[2] = 5;
685 op[3] = 0xfc;
686 operand = M32C_OPERAND_LAB_8_24;
687 where += 3;
688 rl_addend = 0x71;
689 break;
690
691 case M32C_INSN_JMP16_S:
692 op[0] = 0x60 | ((addend-2) & 0x07);
693 operand = M32C_OPERAND_LAB_5_3;
694 rl_addend = 0x10;
695 break;
696
697 case M32C_INSN_JMP16_B:
698 op[0] = 0xfe;
699 op[1] = addend - 1;
700 operand = M32C_OPERAND_LAB_8_8;
701 rl_addend = 0x21;
702 break;
703
704 case M32C_INSN_JMP16_W:
705 op[0] = 0xf4;
706 op[1] = addend - 1;
707 op[2] = (addend - 1) >> 8;
708 operand = M32C_OPERAND_LAB_8_16;
709 rl_addend = 0x31;
710 break;
711
712 case M32C_INSN_JMP16_A:
713 op[0] = 0xfc;
714 op[1] = 0;
715 op[2] = 0;
716 op[3] = 0;
717 operand = M32C_OPERAND_LAB_8_24;
718 rl_addend = 0x41;
719 break;
720
721 case M32C_INSN_JCND32:
722 op[1] = addend - 1;
723 operand = M32C_OPERAND_LAB_8_8;
724 rl_addend = 0x21;
725 break;
726
727 case -M32C_MACRO_JCND32_W:
728 op[0] ^= 0x40;
729 op[1] = 4;
730 op[2] = 0xce;
731 op[3] = addend - 3;
732 op[4] = (addend - 3) >> 8;
733 operand = M32C_OPERAND_LAB_8_16;
734 where += 2;
735 rl_addend = 0x51;
736 break;
737
738 case -M32C_MACRO_JCND32_A:
739 op[0] ^= 0x40;
740 op[1] = 5;
741 op[2] = 0xcc;
742 operand = M32C_OPERAND_LAB_8_24;
743 where += 2;
744 rl_addend = 0x61;
745 break;
746
747 case M32C_INSN_JMP32_S:
748 addend = ((addend-2) & 0x07);
749 op[0] = 0x4a | (addend & 0x01) | ((addend << 3) & 0x30);
750 operand = M32C_OPERAND_LAB32_JMP_S;
751 rl_addend = 0x10;
752 break;
753
754 case M32C_INSN_JMP32_B:
755 op[0] = 0xbb;
756 op[1] = addend - 1;
757 operand = M32C_OPERAND_LAB_8_8;
758 rl_addend = 0x21;
759 break;
760
761 case M32C_INSN_JMP32_W:
762 op[0] = 0xce;
763 op[1] = addend - 1;
764 op[2] = (addend - 1) >> 8;
765 operand = M32C_OPERAND_LAB_8_16;
766 rl_addend = 0x31;
767 break;
768
769 case M32C_INSN_JMP32_A:
770 op[0] = 0xcc;
771 op[1] = 0;
772 op[2] = 0;
773 op[3] = 0;
774 operand = M32C_OPERAND_LAB_8_24;
775 rl_addend = 0x41;
776 break;
777
778
779 case M32C_INSN_JSR16_W:
780 op[0] = 0xf5;
781 op[1] = addend - 1;
782 op[2] = (addend - 1) >> 8;
783 operand = M32C_OPERAND_LAB_8_16;
784 rl_addend = 0x31;
785 break;
786
787 case M32C_INSN_JSR16_A:
788 op[0] = 0xfd;
789 op[1] = 0;
790 op[2] = 0;
791 op[3] = 0;
792 operand = M32C_OPERAND_LAB_8_24;
793 rl_addend = 0x41;
794 break;
795
796 case M32C_INSN_JSR32_W:
797 op[0] = 0xcf;
798 op[1] = addend - 1;
799 op[2] = (addend - 1) >> 8;
800 operand = M32C_OPERAND_LAB_8_16;
801 rl_addend = 0x31;
802 break;
803
804 case M32C_INSN_JSR32_A:
805 op[0] = 0xcd;
806 op[1] = 0;
807 op[2] = 0;
808 op[3] = 0;
809 operand = M32C_OPERAND_LAB_8_24;
810 rl_addend = 0x41;
811 break;
812
813 case -M32C_MACRO_ADJNZ_2:
814 rl_addend = 0x31;
815 op[2] = addend - 2;
816 operand = M32C_OPERAND_LAB_16_8;
817 break;
818 case -M32C_MACRO_ADJNZ_3:
819 rl_addend = 0x41;
820 op[3] = addend - 2;
821 operand = M32C_OPERAND_LAB_24_8;
822 break;
823 case -M32C_MACRO_ADJNZ_4:
824 rl_addend = 0x51;
825 op[4] = addend - 2;
826 operand = M32C_OPERAND_LAB_32_8;
827 break;
828 case -M32C_MACRO_ADJNZ_5:
829 rl_addend = 0x61;
830 op[5] = addend - 2;
831 operand = M32C_OPERAND_LAB_40_8;
832 break;
833
834 default:
835 printf("\nHey! Need more opcode converters! missing: %d %s\n\n",
836 fragP->fr_subtype,
837 fragP->fr_cgen.insn->base->name);
838 abort();
839 }
840
841 if (m32c_relax)
842 {
843 if (operand != M32C_OPERAND_LAB_8_24)
844 fragP->fr_offset = (fragP->fr_address + where);
845
846 fix_new (fragP,
847 rl_where,
848 0, abs_section_sym, rl_addend, 0,
849 BFD_RELOC_M32C_RL_JUMP);
850 }
851
852 if (S_GET_SEGMENT (fragP->fr_symbol) != sec
853 || operand == M32C_OPERAND_LAB_8_24
854 || (m32c_relax && (operand != M32C_OPERAND_LAB_5_3
855 && operand != M32C_OPERAND_LAB32_JMP_S)))
856 {
857 gas_assert (fragP->fr_cgen.insn != 0);
858 gas_cgen_record_fixup (fragP,
859 where,
860 fragP->fr_cgen.insn,
861 (fragP->fr_fix - where) * 8,
862 cgen_operand_lookup_by_num (gas_cgen_cpu_desc,
863 operand),
864 fragP->fr_cgen.opinfo,
865 fragP->fr_symbol,
866 fragP->fr_offset);
867 }
868 }
869 \f
870 /* Functions concerning relocs. */
871
872 /* The location from which a PC relative jump should be calculated,
873 given a PC relative reloc. */
874
875 long
876 md_pcrel_from_section (fixS * fixP, segT sec)
877 {
878 if (fixP->fx_addsy != (symbolS *) NULL
879 && (! S_IS_DEFINED (fixP->fx_addsy)
880 || S_GET_SEGMENT (fixP->fx_addsy) != sec))
881 /* The symbol is undefined (or is defined but not in this section).
882 Let the linker figure it out. */
883 return 0;
884
885 return (fixP->fx_frag->fr_address + fixP->fx_where);
886 }
887
888 /* Return the bfd reloc type for OPERAND of INSN at fixup FIXP.
889 Returns BFD_RELOC_NONE if no reloc type can be found.
890 *FIXP may be modified if desired. */
891
892 bfd_reloc_code_real_type
893 md_cgen_lookup_reloc (const CGEN_INSN * insn ATTRIBUTE_UNUSED,
894 const CGEN_OPERAND * operand,
895 fixS * fixP ATTRIBUTE_UNUSED)
896 {
897 static const struct op_reloc {
898 /* A CGEN operand type that can be a relocatable expression. */
899 CGEN_OPERAND_TYPE operand;
900
901 /* The appropriate BFD reloc type to use for that. */
902 bfd_reloc_code_real_type reloc;
903
904 /* The offset from the start of the instruction to the field to be
905 relocated, in bytes. */
906 int offset;
907 } op_reloc_table[] = {
908
909 /* PC-REL relocs for 8-bit fields. */
910 { M32C_OPERAND_LAB_8_8, BFD_RELOC_8_PCREL, 1 },
911 { M32C_OPERAND_LAB_16_8, BFD_RELOC_8_PCREL, 2 },
912 { M32C_OPERAND_LAB_24_8, BFD_RELOC_8_PCREL, 3 },
913 { M32C_OPERAND_LAB_32_8, BFD_RELOC_8_PCREL, 4 },
914 { M32C_OPERAND_LAB_40_8, BFD_RELOC_8_PCREL, 5 },
915
916 /* PC-REL relocs for 16-bit fields. */
917 { M32C_OPERAND_LAB_8_16, BFD_RELOC_16_PCREL, 1 },
918
919 /* Absolute relocs for 8-bit fields. */
920 { M32C_OPERAND_IMM_8_QI, BFD_RELOC_8, 1 },
921 { M32C_OPERAND_IMM_16_QI, BFD_RELOC_8, 2 },
922 { M32C_OPERAND_IMM_24_QI, BFD_RELOC_8, 3 },
923 { M32C_OPERAND_IMM_32_QI, BFD_RELOC_8, 4 },
924 { M32C_OPERAND_IMM_40_QI, BFD_RELOC_8, 5 },
925 { M32C_OPERAND_IMM_48_QI, BFD_RELOC_8, 6 },
926 { M32C_OPERAND_IMM_56_QI, BFD_RELOC_8, 7 },
927 { M32C_OPERAND_DSP_8_S8, BFD_RELOC_8, 1 },
928 { M32C_OPERAND_DSP_16_S8, BFD_RELOC_8, 2 },
929 { M32C_OPERAND_DSP_24_S8, BFD_RELOC_8, 3 },
930 { M32C_OPERAND_DSP_32_S8, BFD_RELOC_8, 4 },
931 { M32C_OPERAND_DSP_40_S8, BFD_RELOC_8, 5 },
932 { M32C_OPERAND_DSP_48_S8, BFD_RELOC_8, 6 },
933 { M32C_OPERAND_DSP_8_U8, BFD_RELOC_8, 1 },
934 { M32C_OPERAND_DSP_16_U8, BFD_RELOC_8, 2 },
935 { M32C_OPERAND_DSP_24_U8, BFD_RELOC_8, 3 },
936 { M32C_OPERAND_DSP_32_U8, BFD_RELOC_8, 4 },
937 { M32C_OPERAND_DSP_40_U8, BFD_RELOC_8, 5 },
938 { M32C_OPERAND_DSP_48_U8, BFD_RELOC_8, 6 },
939 { M32C_OPERAND_BITBASE32_16_S11_UNPREFIXED, BFD_RELOC_8, 2 },
940 { M32C_OPERAND_BITBASE32_16_U11_UNPREFIXED, BFD_RELOC_8, 2 },
941 { M32C_OPERAND_BITBASE32_24_S11_PREFIXED, BFD_RELOC_8, 3 },
942 { M32C_OPERAND_BITBASE32_24_U11_PREFIXED, BFD_RELOC_8, 3 },
943
944 /* Absolute relocs for 16-bit fields. */
945 { M32C_OPERAND_IMM_8_HI, BFD_RELOC_16, 1 },
946 { M32C_OPERAND_IMM_16_HI, BFD_RELOC_16, 2 },
947 { M32C_OPERAND_IMM_24_HI, BFD_RELOC_16, 3 },
948 { M32C_OPERAND_IMM_32_HI, BFD_RELOC_16, 4 },
949 { M32C_OPERAND_IMM_40_HI, BFD_RELOC_16, 5 },
950 { M32C_OPERAND_IMM_48_HI, BFD_RELOC_16, 6 },
951 { M32C_OPERAND_IMM_56_HI, BFD_RELOC_16, 7 },
952 { M32C_OPERAND_IMM_64_HI, BFD_RELOC_16, 8 },
953 { M32C_OPERAND_DSP_16_S16, BFD_RELOC_16, 2 },
954 { M32C_OPERAND_DSP_24_S16, BFD_RELOC_16, 3 },
955 { M32C_OPERAND_DSP_32_S16, BFD_RELOC_16, 4 },
956 { M32C_OPERAND_DSP_40_S16, BFD_RELOC_16, 5 },
957 { M32C_OPERAND_DSP_8_U16, BFD_RELOC_16, 1 },
958 { M32C_OPERAND_DSP_16_U16, BFD_RELOC_16, 2 },
959 { M32C_OPERAND_DSP_24_U16, BFD_RELOC_16, 3 },
960 { M32C_OPERAND_DSP_32_U16, BFD_RELOC_16, 4 },
961 { M32C_OPERAND_DSP_40_U16, BFD_RELOC_16, 5 },
962 { M32C_OPERAND_DSP_48_U16, BFD_RELOC_16, 6 },
963 { M32C_OPERAND_BITBASE32_16_S19_UNPREFIXED, BFD_RELOC_16, 2 },
964 { M32C_OPERAND_BITBASE32_16_U19_UNPREFIXED, BFD_RELOC_16, 2 },
965 { M32C_OPERAND_BITBASE32_24_S19_PREFIXED, BFD_RELOC_16, 3 },
966 { M32C_OPERAND_BITBASE32_24_U19_PREFIXED, BFD_RELOC_16, 3 },
967
968 /* Absolute relocs for 24-bit fields. */
969 { M32C_OPERAND_LAB_8_24, BFD_RELOC_24, 1 },
970 { M32C_OPERAND_DSP_8_S24, BFD_RELOC_24, 1 },
971 { M32C_OPERAND_DSP_8_U24, BFD_RELOC_24, 1 },
972 { M32C_OPERAND_DSP_16_U24, BFD_RELOC_24, 2 },
973 { M32C_OPERAND_DSP_24_U24, BFD_RELOC_24, 3 },
974 { M32C_OPERAND_DSP_32_U24, BFD_RELOC_24, 4 },
975 { M32C_OPERAND_DSP_40_U24, BFD_RELOC_24, 5 },
976 { M32C_OPERAND_DSP_48_U24, BFD_RELOC_24, 6 },
977 { M32C_OPERAND_DSP_16_U20, BFD_RELOC_24, 2 },
978 { M32C_OPERAND_DSP_24_U20, BFD_RELOC_24, 3 },
979 { M32C_OPERAND_DSP_32_U20, BFD_RELOC_24, 4 },
980 { M32C_OPERAND_BITBASE32_16_U27_UNPREFIXED, BFD_RELOC_24, 2 },
981 { M32C_OPERAND_BITBASE32_24_U27_PREFIXED, BFD_RELOC_24, 3 },
982
983 /* Absolute relocs for 32-bit fields. */
984 { M32C_OPERAND_IMM_16_SI, BFD_RELOC_32, 2 },
985 { M32C_OPERAND_IMM_24_SI, BFD_RELOC_32, 3 },
986 { M32C_OPERAND_IMM_32_SI, BFD_RELOC_32, 4 },
987 { M32C_OPERAND_IMM_40_SI, BFD_RELOC_32, 5 },
988
989 };
990
991 int i;
992
993 for (i = ARRAY_SIZE (op_reloc_table); --i >= 0; )
994 {
995 const struct op_reloc *or = &op_reloc_table[i];
996
997 if (or->operand == operand->type)
998 {
999 fixP->fx_where += or->offset;
1000 fixP->fx_size -= or->offset;
1001
1002 if (fixP->fx_cgen.opinfo
1003 && fixP->fx_cgen.opinfo != BFD_RELOC_NONE)
1004 return fixP->fx_cgen.opinfo;
1005
1006 return or->reloc;
1007 }
1008 }
1009
1010 fprintf
1011 (stderr,
1012 "Error: tc-m32c.c:md_cgen_lookup_reloc Unimplemented relocation for operand %s\n",
1013 operand->name);
1014
1015 return BFD_RELOC_NONE;
1016 }
1017
1018 void
1019 m32c_cons_fix_new (fragS * frag,
1020 int where,
1021 int size,
1022 expressionS *exp)
1023 {
1024 bfd_reloc_code_real_type type;
1025
1026 switch (size)
1027 {
1028 case 1:
1029 type = BFD_RELOC_8;
1030 break;
1031 case 2:
1032 type = BFD_RELOC_16;
1033 break;
1034 case 3:
1035 type = BFD_RELOC_24;
1036 break;
1037 case 4:
1038 default:
1039 type = BFD_RELOC_32;
1040 break;
1041 case 8:
1042 type = BFD_RELOC_64;
1043 break;
1044 }
1045
1046 fix_new_exp (frag, where, (int) size, exp, 0, type);
1047 }
1048
1049 void
1050 m32c_apply_fix (struct fix *f, valueT *t, segT s)
1051 {
1052 if (f->fx_r_type == BFD_RELOC_M32C_RL_JUMP
1053 || f->fx_r_type == BFD_RELOC_M32C_RL_1ADDR
1054 || f->fx_r_type == BFD_RELOC_M32C_RL_2ADDR)
1055 return;
1056 gas_cgen_md_apply_fix (f, t, s);
1057 }
1058
1059 arelent *
1060 tc_gen_reloc (asection *sec, fixS *fx)
1061 {
1062 if (fx->fx_r_type == BFD_RELOC_M32C_RL_JUMP
1063 || fx->fx_r_type == BFD_RELOC_M32C_RL_1ADDR
1064 || fx->fx_r_type == BFD_RELOC_M32C_RL_2ADDR)
1065 {
1066 arelent * reloc;
1067
1068 reloc = xmalloc (sizeof (* reloc));
1069
1070 reloc->sym_ptr_ptr = xmalloc (sizeof (asymbol *));
1071 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fx->fx_addsy);
1072 reloc->address = fx->fx_frag->fr_address + fx->fx_where;
1073 reloc->howto = bfd_reloc_type_lookup (stdoutput, fx->fx_r_type);
1074 reloc->addend = fx->fx_offset;
1075 return reloc;
1076
1077 }
1078 return gas_cgen_tc_gen_reloc (sec, fx);
1079 }
1080
1081 /* See whether we need to force a relocation into the output file.
1082 This is used to force out switch and PC relative relocations when
1083 relaxing. */
1084
1085 int
1086 m32c_force_relocation (fixS * fixp)
1087 {
1088 int reloc = fixp->fx_r_type;
1089
1090 if (reloc > (int)BFD_RELOC_UNUSED)
1091 {
1092 reloc -= (int)BFD_RELOC_UNUSED;
1093 switch (reloc)
1094 {
1095 case M32C_OPERAND_DSP_32_S16:
1096 case M32C_OPERAND_DSP_32_U16:
1097 case M32C_OPERAND_IMM_32_HI:
1098 case M32C_OPERAND_DSP_16_S16:
1099 case M32C_OPERAND_DSP_16_U16:
1100 case M32C_OPERAND_IMM_16_HI:
1101 case M32C_OPERAND_DSP_24_S16:
1102 case M32C_OPERAND_DSP_24_U16:
1103 case M32C_OPERAND_IMM_24_HI:
1104 return 1;
1105
1106 /* If we're doing linker relaxing, we need to keep all the
1107 pc-relative jumps in case we need to fix them due to
1108 deleted bytes between the jump and its destination. */
1109 case M32C_OPERAND_LAB_8_8:
1110 case M32C_OPERAND_LAB_8_16:
1111 case M32C_OPERAND_LAB_8_24:
1112 case M32C_OPERAND_LAB_16_8:
1113 case M32C_OPERAND_LAB_24_8:
1114 case M32C_OPERAND_LAB_32_8:
1115 case M32C_OPERAND_LAB_40_8:
1116 if (m32c_relax)
1117 return 1;
1118 default:
1119 break;
1120 }
1121 }
1122 else
1123 {
1124 switch (fixp->fx_r_type)
1125 {
1126 case BFD_RELOC_16:
1127 return 1;
1128
1129 case BFD_RELOC_M32C_RL_JUMP:
1130 case BFD_RELOC_M32C_RL_1ADDR:
1131 case BFD_RELOC_M32C_RL_2ADDR:
1132 case BFD_RELOC_8_PCREL:
1133 case BFD_RELOC_16_PCREL:
1134 if (m32c_relax)
1135 return 1;
1136 default:
1137 break;
1138 }
1139 }
1140
1141 return generic_force_reloc (fixp);
1142 }
1143 \f
1144 /* Write a value out to the object file, using the appropriate endianness. */
1145
1146 void
1147 md_number_to_chars (char * buf, valueT val, int n)
1148 {
1149 number_to_chars_littleendian (buf, val, n);
1150 }
1151
1152 /* Turn a string in input_line_pointer into a floating point constant of type
1153 type, and store the appropriate bytes in *litP. The number of LITTLENUMS
1154 emitted is stored in *sizeP . An error message is returned, or NULL on OK. */
1155
1156 /* Equal to MAX_PRECISION in atof-ieee.c. */
1157 #define MAX_LITTLENUMS 6
1158
1159 char *
1160 md_atof (int type, char * litP, int * sizeP)
1161 {
1162 return ieee_md_atof (type, litP, sizeP, TRUE);
1163 }
1164
1165 bfd_boolean
1166 m32c_fix_adjustable (fixS * fixP)
1167 {
1168 int reloc;
1169 if (fixP->fx_addsy == NULL)
1170 return 1;
1171
1172 /* We need the symbol name for the VTABLE entries. */
1173 reloc = fixP->fx_r_type;
1174 if (reloc > (int)BFD_RELOC_UNUSED)
1175 {
1176 reloc -= (int)BFD_RELOC_UNUSED;
1177 switch (reloc)
1178 {
1179 case M32C_OPERAND_DSP_32_S16:
1180 case M32C_OPERAND_DSP_32_U16:
1181 case M32C_OPERAND_IMM_32_HI:
1182 case M32C_OPERAND_DSP_16_S16:
1183 case M32C_OPERAND_DSP_16_U16:
1184 case M32C_OPERAND_IMM_16_HI:
1185 case M32C_OPERAND_DSP_24_S16:
1186 case M32C_OPERAND_DSP_24_U16:
1187 case M32C_OPERAND_IMM_24_HI:
1188 return 0;
1189 }
1190 }
1191 else
1192 {
1193 if (fixP->fx_r_type == BFD_RELOC_16)
1194 return 0;
1195 }
1196
1197 /* Do not adjust relocations involving symbols in merged sections.
1198
1199 A reloc patching in the value of some symbol S plus some addend A
1200 can be produced in different ways:
1201
1202 1) It might simply be a reference to the data at S + A. Clearly,
1203 if linker merging shift that data around, the value patched in
1204 by the reloc needs to be adjusted accordingly.
1205
1206 2) Or, it might be a reference to S, with A added in as a constant
1207 bias. For example, given code like this:
1208
1209 static int S[100];
1210
1211 ... S[i - 8] ...
1212
1213 it would be reasonable for the compiler to rearrange the array
1214 reference to something like:
1215
1216 ... (S-8)[i] ...
1217
1218 and emit assembly code that refers to S - (8 * sizeof (int)),
1219 so the subtraction is done entirely at compile-time. In this
1220 case, the reloc's addend A would be -(8 * sizeof (int)), and
1221 shifting around code or data at S + A should not affect the
1222 reloc: the reloc isn't referring to that code or data at all.
1223
1224 The linker has no way of knowing which case it has in hand. So,
1225 to disambiguate, we have the linker always treat reloc addends as
1226 in case 2): they're constants that should be simply added to the
1227 symbol value, just like the reloc says. And we express case 1)
1228 in different way: we have the compiler place a label at the real
1229 target, and reference that label with an addend of zero. (The
1230 compiler is unlikely to reference code using a label plus an
1231 offset anyway, since it doesn't know the sizes of the
1232 instructions.)
1233
1234 The simplification being done by gas/write.c:adjust_reloc_syms,
1235 however, turns the explicit-label usage into the label-plus-
1236 offset usage, re-introducing the ambiguity the compiler avoided.
1237 So we need to disable that simplification for symbols referring
1238 to merged data.
1239
1240 This only affects object size a little bit. */
1241 if (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE)
1242 return 0;
1243
1244 if (m32c_relax)
1245 return 0;
1246
1247 return 1;
1248 }
1249
1250 /* Worker function for m32c_is_colon_insn(). */
1251 static char
1252 restore_colon (int advance_i_l_p_by)
1253 {
1254 char c;
1255
1256 /* Restore the colon, and advance input_line_pointer to
1257 the end of the new symbol. */
1258 * input_line_pointer = ':';
1259 input_line_pointer += advance_i_l_p_by;
1260 c = * input_line_pointer;
1261 * input_line_pointer = 0;
1262
1263 return c;
1264 }
1265
1266 /* Determines if the symbol starting at START and ending in
1267 a colon that was at the location pointed to by INPUT_LINE_POINTER
1268 (but which has now been replaced bu a NUL) is in fact an
1269 :Z, :S, :Q, or :G suffix.
1270 If it is, then it restores the colon, advances INPUT_LINE_POINTER
1271 to the real end of the instruction/symbol, and returns the character
1272 that really terminated the symbol. Otherwise it returns 0. */
1273 char
1274 m32c_is_colon_insn (char *start ATTRIBUTE_UNUSED)
1275 {
1276 char * i_l_p = input_line_pointer;
1277
1278 /* Check to see if the text following the colon is 'G' */
1279 if (TOLOWER (i_l_p[1]) == 'g' && (i_l_p[2] == ' ' || i_l_p[2] == '\t'))
1280 return restore_colon (2);
1281
1282 /* Check to see if the text following the colon is 'Q' */
1283 if (TOLOWER (i_l_p[1]) == 'q' && (i_l_p[2] == ' ' || i_l_p[2] == '\t'))
1284 return restore_colon (2);
1285
1286 /* Check to see if the text following the colon is 'S' */
1287 if (TOLOWER (i_l_p[1]) == 's' && (i_l_p[2] == ' ' || i_l_p[2] == '\t'))
1288 return restore_colon (2);
1289
1290 /* Check to see if the text following the colon is 'Z' */
1291 if (TOLOWER (i_l_p[1]) == 'z' && (i_l_p[2] == ' ' || i_l_p[2] == '\t'))
1292 return restore_colon (2);
1293
1294 return 0;
1295 }
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