* elf32-spu.c (build_stub): Fix malloc under-allocation.
[binutils.git] / include / opcode / mn10300.h
blob16a139bce5d6582728ab5cd07f1d29f8c103c7e3
1 /* mn10300.h -- Header file for Matsushita 10300 opcode table
2 Copyright 1996, 1997, 1998, 1999, 2003, 2010 Free Software Foundation, Inc.
3 Written by Jeff Law, Cygnus Support
5 This file is part of GDB, GAS, and the GNU binutils.
7 GDB, GAS, and the GNU binutils are free software; you can redistribute
8 them and/or modify them under the terms of the GNU General Public
9 License as published by the Free Software Foundation; either version 3,
10 or (at your option) any later version.
12 GDB, GAS, and the GNU binutils are distributed in the hope that they
13 will be useful, but WITHOUT ANY WARRANTY; without even the implied
14 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
15 the GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this file; see the file COPYING3. If not, write to the Free
19 Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
20 MA 02110-1301, USA. */
22 #ifndef MN10300_H
23 #define MN10300_H
25 /* The opcode table is an array of struct mn10300_opcode. */
27 #define MN10300_MAX_OPERANDS 8
28 struct mn10300_opcode
30 /* The opcode name. */
31 const char *name;
33 /* The opcode itself. Those bits which will be filled in with
34 operands are zeroes. */
35 unsigned long opcode;
37 /* The opcode mask. This is used by the disassembler. This is a
38 mask containing ones indicating those bits which must match the
39 opcode field, and zeroes indicating those bits which need not
40 match (and are presumably filled in by operands). */
41 unsigned long mask;
43 /* A bitmask. For each operand, nonzero if it must not have the same
44 register specification as all other operands with a nonzero bit in
45 this flag. ie 0x81 would indicate that operands 7 and 0 must not
46 match. Note that we count operands from left to right as they appear
47 in the operands specification below. */
48 unsigned int no_match_operands;
50 /* The format of this opcode. */
51 unsigned char format;
53 /* Bitmask indicating what cpu variants this opcode is available on.
54 We assume mn10300 base opcodes are available everywhere, so we only
55 have to note opcodes which are available on other variants. */
56 unsigned int machine;
58 /* An array of operand codes. Each code is an index into the
59 operand table. They appear in the order which the operands must
60 appear in assembly code, and are terminated by a zero. */
61 unsigned char operands[MN10300_MAX_OPERANDS];
64 /* The table itself is sorted by major opcode number, and is otherwise
65 in the order in which the disassembler should consider
66 instructions. */
67 extern const struct mn10300_opcode mn10300_opcodes[];
68 extern const int mn10300_num_opcodes;
71 /* The operands table is an array of struct mn10300_operand. */
73 struct mn10300_operand
75 /* The number of bits in the operand. */
76 int bits;
78 /* How far the operand is left shifted in the instruction. */
79 int shift;
81 /* One bit syntax flags. */
82 int flags;
85 /* Elements in the table are retrieved by indexing with values from
86 the operands field of the mn10300_opcodes table. */
88 extern const struct mn10300_operand mn10300_operands[];
90 /* Values defined for the flags field of a struct mn10300_operand. */
91 #define MN10300_OPERAND_DREG 0x1
93 #define MN10300_OPERAND_AREG 0x2
95 #define MN10300_OPERAND_SP 0x4
97 #define MN10300_OPERAND_PSW 0x8
99 #define MN10300_OPERAND_MDR 0x10
101 #define MN10300_OPERAND_SIGNED 0x20
103 #define MN10300_OPERAND_PROMOTE 0x40
105 #define MN10300_OPERAND_PAREN 0x80
107 #define MN10300_OPERAND_REPEATED 0x100
109 #define MN10300_OPERAND_EXTENDED 0x200
111 #define MN10300_OPERAND_SPLIT 0x400
113 #define MN10300_OPERAND_REG_LIST 0x800
115 #define MN10300_OPERAND_PCREL 0x1000
117 #define MN10300_OPERAND_MEMADDR 0x2000
119 #define MN10300_OPERAND_RELAX 0x4000
121 #define MN10300_OPERAND_USP 0x8000
123 #define MN10300_OPERAND_SSP 0x10000
125 #define MN10300_OPERAND_MSP 0x20000
127 #define MN10300_OPERAND_PC 0x40000
129 #define MN10300_OPERAND_EPSW 0x80000
131 #define MN10300_OPERAND_RREG 0x100000
133 #define MN10300_OPERAND_XRREG 0x200000
135 #define MN10300_OPERAND_PLUS 0x400000
137 #define MN10300_OPERAND_24BIT 0x800000
139 #define MN10300_OPERAND_FSREG 0x1000000
141 #define MN10300_OPERAND_FDREG 0x2000000
143 #define MN10300_OPERAND_FPCR 0x4000000
145 /* Opcode Formats. */
146 #define FMT_S0 1
147 #define FMT_S1 2
148 #define FMT_S2 3
149 #define FMT_S4 4
150 #define FMT_S6 5
151 #define FMT_D0 6
152 #define FMT_D1 7
153 #define FMT_D2 8
154 #define FMT_D4 9
155 #define FMT_D5 10
156 #define FMT_D6 11
157 #define FMT_D7 12
158 #define FMT_D8 13
159 #define FMT_D9 14
160 #define FMT_D10 15
161 #define FMT_D3 16
163 /* Variants of the mn10300 which have additional opcodes. */
164 #define MN103 300
165 #define AM30 300
167 #define AM33 330
168 #define AM33_2 332
170 #endif /* MN10300_H */