* elf32-spu.c (build_stub): Fix malloc under-allocation.
[binutils.git] / include / opcode / spu.h
blobc6468303bc0d117f2c9bc45c3a6e3d785177a152
1 /* SPU ELF support for BFD.
3 Copyright 2006, 2010 Free Software Foundation, Inc.
5 This file is part of GDB, GAS, and the GNU binutils.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software Foundation,
19 Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
21 /* These two enums are from rel_apu/common/spu_asm_format.h */
22 /* definition of instruction format */
23 typedef enum {
24 RRR,
25 RI18,
26 RI16,
27 RI10,
28 RI8,
29 RI7,
30 RR,
31 LBT,
32 LBTI,
33 IDATA,
34 UNKNOWN_IFORMAT
35 } spu_iformat;
37 /* These values describe assembly instruction arguments. They indicate
38 * how to encode, range checking and which relocation to use. */
39 typedef enum {
40 A_T, /* register at pos 0 */
41 A_A, /* register at pos 7 */
42 A_B, /* register at pos 14 */
43 A_C, /* register at pos 21 */
44 A_S, /* special purpose register at pos 7 */
45 A_H, /* channel register at pos 7 */
46 A_P, /* parenthesis, this has to separate regs from immediates */
47 A_S3,
48 A_S6,
49 A_S7N,
50 A_S7,
51 A_U7A,
52 A_U7B,
53 A_S10B,
54 A_S10,
55 A_S11,
56 A_S11I,
57 A_S14,
58 A_S16,
59 A_S18,
60 A_R18,
61 A_U3,
62 A_U5,
63 A_U6,
64 A_U7,
65 A_U14,
66 A_X16,
67 A_U18,
68 A_MAX
69 } spu_aformat;
71 enum spu_insns {
72 #define APUOP(TAG,MACFORMAT,OPCODE,MNEMONIC,ASMFORMAT,DEP,PIPE) \
73 TAG,
74 #define APUOPFB(TAG,MACFORMAT,OPCODE,FB,MNEMONIC,ASMFORMAT,DEP,PIPE) \
75 TAG,
76 #include "opcode/spu-insns.h"
77 #undef APUOP
78 #undef APUOPFB
79 M_SPU_MAX
82 struct spu_opcode
84 spu_iformat insn_type;
85 unsigned int opcode;
86 char *mnemonic;
87 int arg[5];
90 #define SIGNED_EXTRACT(insn,size,pos) (((int)((insn) << (32-size-pos))) >> (32-size))
91 #define UNSIGNED_EXTRACT(insn,size,pos) (((insn) >> pos) & ((1 << size)-1))
93 #define DECODE_INSN_RT(insn) (insn & 0x7f)
94 #define DECODE_INSN_RA(insn) ((insn >> 7) & 0x7f)
95 #define DECODE_INSN_RB(insn) ((insn >> 14) & 0x7f)
96 #define DECODE_INSN_RC(insn) ((insn >> 21) & 0x7f)
98 #define DECODE_INSN_I10(insn) SIGNED_EXTRACT(insn,10,14)
99 #define DECODE_INSN_U10(insn) UNSIGNED_EXTRACT(insn,10,14)
101 /* For branching, immediate loads, hbr and lqa/stqa. */
102 #define DECODE_INSN_I16(insn) SIGNED_EXTRACT(insn,16,7)
103 #define DECODE_INSN_U16(insn) UNSIGNED_EXTRACT(insn,16,7)
105 /* for stop */
106 #define DECODE_INSN_U14(insn) UNSIGNED_EXTRACT(insn,14,0)
108 /* For ila */
109 #define DECODE_INSN_I18(insn) SIGNED_EXTRACT(insn,18,7)
110 #define DECODE_INSN_U18(insn) UNSIGNED_EXTRACT(insn,18,7)
112 /* For rotate and shift and generate control mask */
113 #define DECODE_INSN_I7(insn) SIGNED_EXTRACT(insn,7,14)
114 #define DECODE_INSN_U7(insn) UNSIGNED_EXTRACT(insn,7,14)
116 /* For float <-> int conversion */
117 #define DECODE_INSN_I8(insn) SIGNED_EXTRACT(insn,8,14)
118 #define DECODE_INSN_U8(insn) UNSIGNED_EXTRACT(insn,8,14)
120 /* For hbr */
121 #define DECODE_INSN_I9a(insn) ((SIGNED_EXTRACT(insn,2,23) << 7) | UNSIGNED_EXTRACT(insn,7,0))
122 #define DECODE_INSN_I9b(insn) ((SIGNED_EXTRACT(insn,2,14) << 7) | UNSIGNED_EXTRACT(insn,7,0))
123 #define DECODE_INSN_U9a(insn) ((UNSIGNED_EXTRACT(insn,2,23) << 7) | UNSIGNED_EXTRACT(insn,7,0))
124 #define DECODE_INSN_U9b(insn) ((UNSIGNED_EXTRACT(insn,2,14) << 7) | UNSIGNED_EXTRACT(insn,7,0))