opcodes/i386-dis.c

   1 /* Print i386 instructions for GDB, the GNU debugger.
   2    Copyright 1988, 1989, 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
   3    2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
   4    Free Software Foundation, Inc.
   5
   6    This file is part of the GNU opcodes library.
   7
   8    This library is free software; you can redistribute it and/or modify
   9    it under the terms of the GNU General Public License as published by
  10    the Free Software Foundation; either version 3, or (at your option)
  11    any later version.
  12
  13    It is distributed in the hope that it will be useful, but WITHOUT
  14    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  15    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  16    License for more details.
  17
  18    You should have received a copy of the GNU General Public License
  19    along with this program; if not, write to the Free Software
  20    Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
  21    MA 02110-1301, USA.  */
  22
  23
  24 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
  25    July 1988
  26     modified by John Hassey (hassey@dg-rtp.dg.com)
  27     x86-64 support added by Jan Hubicka (jh@suse.cz)
  28     VIA PadLock support by Michal Ludvig (mludvig@suse.cz).  */
  29
  30 /* The main tables describing the instructions is essentially a copy
  31    of the "Opcode Map" chapter (Appendix A) of the Intel 80386
  32    Programmers Manual.  Usually, there is a capital letter, followed
  33    by a small letter.  The capital letter tell the addressing mode,
  34    and the small letter tells about the operand size.  Refer to
  35    the Intel manual for details.  */
  36
  37 #include "sysdep.h"
  38 #include "dis-asm.h"
  39 #include "opintl.h"
  40 #include "opcode/i386.h"
  41 #include "libiberty.h"
  42
  43 #include <setjmp.h>
  44
  45 static int fetch_data (struct disassemble_info *, bfd_byte *);
  46 static void ckprefix (void);
  47 static const char *prefix_name (int, int);
  48 static int print_insn (bfd_vma, disassemble_info *);
  49 static void dofloat (int);
  50 static void OP_ST (int, int);
  51 static void OP_STi (int, int);
  52 static int putop (const char *, int);
  53 static void oappend (const char *);
  54 static void append_seg (void);
  55 static void OP_indirE (int, int);
  56 static void print_operand_value (char *, int, bfd_vma);
  57 static void OP_E_register (int, int);
  58 static void OP_E_memory (int, int, int);
  59 static void OP_E_extended (int, int, int);
  60 static void print_displacement (char *, bfd_vma);
  61 static void OP_E (int, int);
  62 static void OP_G (int, int);
  63 static bfd_vma get64 (void);
  64 static bfd_signed_vma get32 (void);
  65 static bfd_signed_vma get32s (void);
  66 static int get16 (void);
  67 static void set_op (bfd_vma, int);
  68 static void OP_Skip_MODRM (int, int);
  69 static void OP_REG (int, int);
  70 static void OP_IMREG (int, int);
  71 static void OP_I (int, int);
  72 static void OP_I64 (int, int);
  73 static void OP_sI (int, int);
  74 static void OP_J (int, int);
  75 static void OP_SEG (int, int);
  76 static void OP_DIR (int, int);
  77 static void OP_OFF (int, int);
  78 static void OP_OFF64 (int, int);
  79 static void ptr_reg (int, int);
  80 static void OP_ESreg (int, int);
  81 static void OP_DSreg (int, int);
  82 static void OP_C (int, int);
  83 static void OP_D (int, int);
  84 static void OP_T (int, int);
  85 static void OP_R (int, int);
  86 static void OP_MMX (int, int);
  87 static void OP_XMM (int, int);
  88 static void OP_EM (int, int);
  89 static void OP_EX (int, int);
  90 static void OP_EMC (int,int);
  91 static void OP_MXC (int,int);
  92 static void OP_MS (int, int);
  93 static void OP_XS (int, int);
  94 static void OP_M (int, int);
  95 static void OP_VEX (int, int);
  96 static void OP_EX_Vex (int, int);
  97 static void OP_XMM_Vex (int, int);
  98 static void OP_REG_VexI4 (int, int);
  99 static void PCLMUL_Fixup (int, int);
 100 static void VZERO_Fixup (int, int);
 101 static void VCMP_Fixup (int, int);
 102 static void OP_0f07 (int, int);
 103 static void OP_Monitor (int, int);
 104 static void OP_Mwait (int, int);
 105 static void NOP_Fixup1 (int, int);
 106 static void NOP_Fixup2 (int, int);
 107 static void OP_3DNowSuffix (int, int);
 108 static void CMP_Fixup (int, int);
 109 static void BadOp (void);
 110 static void REP_Fixup (int, int);
 111 static void CMPXCHG8B_Fixup (int, int);
 112 static void XMM_Fixup (int, int);
 113 static void CRC32_Fixup (int, int);
 114 static void print_drex_arg (unsigned int, int, int);
 115 static void OP_DREX4 (int, int);
 116 static void OP_DREX3 (int, int);
 117 static void OP_DREX_ICMP (int, int);
 118 static void OP_DREX_FCMP (int, int);
 119 static void MOVBE_Fixup (int, int);
 120
 121 struct dis_private {
 122   /* Points to first byte not fetched.  */
 123   bfd_byte *max_fetched;
 124   bfd_byte the_buffer[MAX_MNEM_SIZE];
 125   bfd_vma insn_start;
 126   int orig_sizeflag;
 127   jmp_buf bailout;
 128 };
 129
 130 enum address_mode
 131 {
 132   mode_16bit,
 133   mode_32bit,
 134   mode_64bit
 135 };
 136
 137 enum address_mode address_mode;
 138
 139 /* Flags for the prefixes for the current instruction.  See below.  */
 140 static int prefixes;
 141
 142 /* REX prefix the current instruction.  See below.  */
 143 static int rex;
 144 /* Bits of REX we've already used.  */
 145 static int rex_used;
 146 /* Original REX prefix.  */
 147 static int rex_original;
 148 /* REX bits in original REX prefix ignored.  It may not be the same
 149    as rex_original since some bits may not be ignored.  */
 150 static int rex_ignored;
 151 /* Mark parts used in the REX prefix.  When we are testing for
 152    empty prefix (for 8bit register REX extension), just mask it
 153    out.  Otherwise test for REX bit is excuse for existence of REX
 154    only in case value is nonzero.  */
 155 #define USED_REX(value)                                 \
 156   {                                                     \
 157     if (value)                                          \
 158       {                                                 \
 159         if ((rex & value))                              \
 160           rex_used |= (value) | REX_OPCODE;             \
 161       }                                                 \
 162     else                                                \
 163       rex_used |= REX_OPCODE;                           \
 164   }
 165
 166 /* Special 'registers' for DREX handling */
 167 #define DREX_REG_UNKNOWN        1000    /* not initialized */
 168 #define DREX_REG_MEMORY         1001    /* use MODRM/SIB/OFFSET memory */
 169
 170 /* The DREX byte has the following fields:
 171    Bits 7-4 -- DREX.Dest, xmm destination register
 172    Bit 3    -- DREX.OC0, operand config bit defines operand order
 173    Bit 2    -- DREX.R, equivalent to REX_R bit, to extend ModRM register
 174    Bit 1    -- DREX.X, equivalent to REX_X bit, to extend SIB index field
 175    Bit 0    -- DREX.W, equivalent to REX_B bit, to extend ModRM r/m field,
 176                SIB base field, or opcode reg field.  */
 177 #define DREX_XMM(drex) ((drex >> 4) & 0xf)
 178 #define DREX_OC0(drex) ((drex >> 3) & 0x1)
 179
 180 /* Flags for prefixes which we somehow handled when printing the
 181    current instruction.  */
 182 static int used_prefixes;
 183
 184 /* Flags stored in PREFIXES.  */
 185 #define PREFIX_REPZ 1
 186 #define PREFIX_REPNZ 2
 187 #define PREFIX_LOCK 4
 188 #define PREFIX_CS 8
 189 #define PREFIX_SS 0x10
 190 #define PREFIX_DS 0x20
 191 #define PREFIX_ES 0x40
 192 #define PREFIX_FS 0x80
 193 #define PREFIX_GS 0x100
 194 #define PREFIX_DATA 0x200
 195 #define PREFIX_ADDR 0x400
 196 #define PREFIX_FWAIT 0x800
 197
 198 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
 199    to ADDR (exclusive) are valid.  Returns 1 for success, longjmps
 200    on error.  */
 201 #define FETCH_DATA(info, addr) \
 202   ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
 203    ? 1 : fetch_data ((info), (addr)))
 204
 205 static int
 206 fetch_data (struct disassemble_info *info, bfd_byte *addr)
 207 {
 208   int status;
 209   struct dis_private *priv = (struct dis_private *) info->private_data;
 210   bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer);
 211
 212   if (addr <= priv->the_buffer + MAX_MNEM_SIZE)
 213     status = (*info->read_memory_func) (start,
 214                                         priv->max_fetched,
 215                                         addr - priv->max_fetched,
 216                                         info);
 217   else
 218     status = -1;
 219   if (status != 0)
 220     {
 221       /* If we did manage to read at least one byte, then
 222          print_insn_i386 will do something sensible.  Otherwise, print
 223          an error.  We do that here because this is where we know
 224          STATUS.  */
 225       if (priv->max_fetched == priv->the_buffer)
 226         (*info->memory_error_func) (status, start, info);
 227       longjmp (priv->bailout, 1);
 228     }
 229   else
 230     priv->max_fetched = addr;
 231   return 1;
 232 }
 233
 234 #define XX { NULL, 0 }
 235
 236 #define Eb { OP_E, b_mode }
 237 #define EbS { OP_E, b_swap_mode }
 238 #define Ev { OP_E, v_mode }
 239 #define EvS { OP_E, v_swap_mode }
 240 #define Ed { OP_E, d_mode }
 241 #define Edq { OP_E, dq_mode }
 242 #define Edqw { OP_E, dqw_mode }
 243 #define Edqb { OP_E, dqb_mode }
 244 #define Edqd { OP_E, dqd_mode }
 245 #define Eq { OP_E, q_mode }
 246 #define indirEv { OP_indirE, stack_v_mode }
 247 #define indirEp { OP_indirE, f_mode }
 248 #define stackEv { OP_E, stack_v_mode }
 249 #define Em { OP_E, m_mode }
 250 #define Ew { OP_E, w_mode }
 251 #define M { OP_M, 0 }           /* lea, lgdt, etc. */
 252 #define Ma { OP_M, a_mode }
 253 #define Mb { OP_M, b_mode }
 254 #define Md { OP_M, d_mode }
 255 #define Mo { OP_M, o_mode }
 256 #define Mp { OP_M, f_mode }             /* 32 or 48 bit memory operand for LDS, LES etc */
 257 #define Mq { OP_M, q_mode }
 258 #define Mx { OP_M, x_mode }
 259 #define Mxmm { OP_M, xmm_mode }
 260 #define Gb { OP_G, b_mode }
 261 #define Gv { OP_G, v_mode }
 262 #define Gd { OP_G, d_mode }
 263 #define Gdq { OP_G, dq_mode }
 264 #define Gm { OP_G, m_mode }
 265 #define Gw { OP_G, w_mode }
 266 #define Rd { OP_R, d_mode }
 267 #define Rm { OP_R, m_mode }
 268 #define Ib { OP_I, b_mode }
 269 #define sIb { OP_sI, b_mode }   /* sign extened byte */
 270 #define Iv { OP_I, v_mode }
 271 #define Iq { OP_I, q_mode }
 272 #define Iv64 { OP_I64, v_mode }
 273 #define Iw { OP_I, w_mode }
 274 #define I1 { OP_I, const_1_mode }
 275 #define Jb { OP_J, b_mode }
 276 #define Jv { OP_J, v_mode }
 277 #define Cm { OP_C, m_mode }
 278 #define Dm { OP_D, m_mode }
 279 #define Td { OP_T, d_mode }
 280 #define Skip_MODRM { OP_Skip_MODRM, 0 }
 281
 282 #define RMeAX { OP_REG, eAX_reg }
 283 #define RMeBX { OP_REG, eBX_reg }
 284 #define RMeCX { OP_REG, eCX_reg }
 285 #define RMeDX { OP_REG, eDX_reg }
 286 #define RMeSP { OP_REG, eSP_reg }
 287 #define RMeBP { OP_REG, eBP_reg }
 288 #define RMeSI { OP_REG, eSI_reg }
 289 #define RMeDI { OP_REG, eDI_reg }
 290 #define RMrAX { OP_REG, rAX_reg }
 291 #define RMrBX { OP_REG, rBX_reg }
 292 #define RMrCX { OP_REG, rCX_reg }
 293 #define RMrDX { OP_REG, rDX_reg }
 294 #define RMrSP { OP_REG, rSP_reg }
 295 #define RMrBP { OP_REG, rBP_reg }
 296 #define RMrSI { OP_REG, rSI_reg }
 297 #define RMrDI { OP_REG, rDI_reg }
 298 #define RMAL { OP_REG, al_reg }
 299 #define RMAL { OP_REG, al_reg }
 300 #define RMCL { OP_REG, cl_reg }
 301 #define RMDL { OP_REG, dl_reg }
 302 #define RMBL { OP_REG, bl_reg }
 303 #define RMAH { OP_REG, ah_reg }
 304 #define RMCH { OP_REG, ch_reg }
 305 #define RMDH { OP_REG, dh_reg }
 306 #define RMBH { OP_REG, bh_reg }
 307 #define RMAX { OP_REG, ax_reg }
 308 #define RMDX { OP_REG, dx_reg }
 309
 310 #define eAX { OP_IMREG, eAX_reg }
 311 #define eBX { OP_IMREG, eBX_reg }
 312 #define eCX { OP_IMREG, eCX_reg }
 313 #define eDX { OP_IMREG, eDX_reg }
 314 #define eSP { OP_IMREG, eSP_reg }
 315 #define eBP { OP_IMREG, eBP_reg }
 316 #define eSI { OP_IMREG, eSI_reg }
 317 #define eDI { OP_IMREG, eDI_reg }
 318 #define AL { OP_IMREG, al_reg }
 319 #define CL { OP_IMREG, cl_reg }
 320 #define DL { OP_IMREG, dl_reg }
 321 #define BL { OP_IMREG, bl_reg }
 322 #define AH { OP_IMREG, ah_reg }
 323 #define CH { OP_IMREG, ch_reg }
 324 #define DH { OP_IMREG, dh_reg }
 325 #define BH { OP_IMREG, bh_reg }
 326 #define AX { OP_IMREG, ax_reg }
 327 #define DX { OP_IMREG, dx_reg }
 328 #define zAX { OP_IMREG, z_mode_ax_reg }
 329 #define indirDX { OP_IMREG, indir_dx_reg }
 330
 331 #define Sw { OP_SEG, w_mode }
 332 #define Sv { OP_SEG, v_mode }
 333 #define Ap { OP_DIR, 0 }
 334 #define Ob { OP_OFF64, b_mode }
 335 #define Ov { OP_OFF64, v_mode }
 336 #define Xb { OP_DSreg, eSI_reg }
 337 #define Xv { OP_DSreg, eSI_reg }
 338 #define Xz { OP_DSreg, eSI_reg }
 339 #define Yb { OP_ESreg, eDI_reg }
 340 #define Yv { OP_ESreg, eDI_reg }
 341 #define DSBX { OP_DSreg, eBX_reg }
 342
 343 #define es { OP_REG, es_reg }
 344 #define ss { OP_REG, ss_reg }
 345 #define cs { OP_REG, cs_reg }
 346 #define ds { OP_REG, ds_reg }
 347 #define fs { OP_REG, fs_reg }
 348 #define gs { OP_REG, gs_reg }
 349
 350 #define MX { OP_MMX, 0 }
 351 #define XM { OP_XMM, 0 }
 352 #define XMM { OP_XMM, xmm_mode }
 353 #define EM { OP_EM, v_mode }
 354 #define EMS { OP_EM, v_swap_mode }
 355 #define EMd { OP_EM, d_mode }
 356 #define EMx { OP_EM, x_mode }
 357 #define EXw { OP_EX, w_mode }
 358 #define EXd { OP_EX, d_mode }
 359 #define EXdS { OP_EX, d_swap_mode }
 360 #define EXq { OP_EX, q_mode }
 361 #define EXqS { OP_EX, q_swap_mode }
 362 #define EXx { OP_EX, x_mode }
 363 #define EXxS { OP_EX, x_swap_mode }
 364 #define EXxmm { OP_EX, xmm_mode }
 365 #define EXxmmq { OP_EX, xmmq_mode }
 366 #define EXymmq { OP_EX, ymmq_mode }
 367 #define EXVexWdq { OP_EX, vex_w_dq_mode }
 368 #define MS { OP_MS, v_mode }
 369 #define XS { OP_XS, v_mode }
 370 #define EMCq { OP_EMC, q_mode }
 371 #define MXC { OP_MXC, 0 }
 372 #define OPSUF { OP_3DNowSuffix, 0 }
 373 #define CMP { CMP_Fixup, 0 }
 374 #define XMM0 { XMM_Fixup, 0 }
 375
 376 #define Vex { OP_VEX, vex_mode }
 377 #define Vex128 { OP_VEX, vex128_mode }
 378 #define Vex256 { OP_VEX, vex256_mode }
 379 #define EXdVex { OP_EX_Vex, d_mode }
 380 #define EXdVexS { OP_EX_Vex, d_swap_mode }
 381 #define EXqVex { OP_EX_Vex, q_mode }
 382 #define EXqVexS { OP_EX_Vex, q_swap_mode }
 383 #define XMVex { OP_XMM_Vex, 0 }
 384 #define XMVexI4 { OP_REG_VexI4, x_mode }
 385 #define PCLMUL { PCLMUL_Fixup, 0 }
 386 #define VZERO { VZERO_Fixup, 0 }
 387 #define VCMP { VCMP_Fixup, 0 }
 388
 389 /* Used handle "rep" prefix for string instructions.  */
 390 #define Xbr { REP_Fixup, eSI_reg }
 391 #define Xvr { REP_Fixup, eSI_reg }
 392 #define Ybr { REP_Fixup, eDI_reg }
 393 #define Yvr { REP_Fixup, eDI_reg }
 394 #define Yzr { REP_Fixup, eDI_reg }
 395 #define indirDXr { REP_Fixup, indir_dx_reg }
 396 #define ALr { REP_Fixup, al_reg }
 397 #define eAXr { REP_Fixup, eAX_reg }
 398
 399 #define cond_jump_flag { NULL, cond_jump_mode }
 400 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
 401
 402 /* bits in sizeflag */
 403 #define SUFFIX_ALWAYS 4
 404 #define AFLAG 2
 405 #define DFLAG 1
 406
 407 /* byte operand */
 408 #define b_mode                  1
 409 /* byte operand with operand swapped */
 410 #define b_swap_mode             (b_mode + 1)
 411 /* operand size depends on prefixes */
 412 #define v_mode                  (b_swap_mode + 1)
 413 /* operand size depends on prefixes with operand swapped */
 414 #define v_swap_mode             (v_mode + 1)
 415 /* word operand */
 416 #define w_mode                  (v_swap_mode + 1)
 417 /* double word operand  */
 418 #define d_mode                  (w_mode + 1)
 419 /* double word operand with operand swapped */
 420 #define d_swap_mode             (d_mode + 1)
 421 /* quad word operand */
 422 #define q_mode                  (d_swap_mode + 1)
 423 /* quad word operand with operand swapped */
 424 #define q_swap_mode             (q_mode + 1)
 425 /* ten-byte operand */
 426 #define t_mode                  (q_swap_mode + 1)
 427 /* 16-byte XMM or 32-byte YMM operand */
 428 #define x_mode                  (t_mode + 1)
 429 /* 16-byte XMM or 32-byte YMM operand with operand swapped */
 430 #define x_swap_mode             (x_mode + 1)
 431 /* 16-byte XMM operand */
 432 #define xmm_mode                (x_swap_mode + 1)
 433 /* 16-byte XMM or quad word operand */
 434 #define xmmq_mode               (xmm_mode + 1)
 435 /* 32-byte YMM or quad word operand */
 436 #define ymmq_mode               (xmmq_mode + 1)
 437 /* d_mode in 32bit, q_mode in 64bit mode.  */
 438 #define m_mode                  (ymmq_mode + 1)
 439 /* pair of v_mode operands */
 440 #define a_mode                  (m_mode + 1)
 441 #define cond_jump_mode          (a_mode + 1)
 442 #define loop_jcxz_mode          (cond_jump_mode + 1)
 443 /* operand size depends on REX prefixes.  */
 444 #define dq_mode                 (loop_jcxz_mode + 1)
 445 /* registers like dq_mode, memory like w_mode.  */
 446 #define dqw_mode                (dq_mode + 1)
 447 /* 4- or 6-byte pointer operand */
 448 #define f_mode                  (dqw_mode + 1)
 449 #define const_1_mode            (f_mode + 1)
 450 /* v_mode for stack-related opcodes.  */
 451 #define stack_v_mode            (const_1_mode + 1)
 452 /* non-quad operand size depends on prefixes */
 453 #define z_mode                  (stack_v_mode + 1)
 454 /* 16-byte operand */
 455 #define o_mode                  (z_mode + 1)
 456 /* registers like dq_mode, memory like b_mode.  */
 457 #define dqb_mode                (o_mode + 1)
 458 /* registers like dq_mode, memory like d_mode.  */
 459 #define dqd_mode                (dqb_mode + 1)
 460 /* normal vex mode */
 461 #define vex_mode                (dqd_mode + 1)
 462 /* 128bit vex mode */
 463 #define vex128_mode             (vex_mode + 1)
 464 /* 256bit vex mode */
 465 #define vex256_mode             (vex128_mode + 1)
 466 /* operand size depends on the VEX.W bit.  */
 467 #define vex_w_dq_mode           (vex256_mode + 1)
 468
 469 #define es_reg                  (vex_w_dq_mode + 1)
 470 #define cs_reg                  (es_reg + 1)
 471 #define ss_reg                  (cs_reg + 1)
 472 #define ds_reg                  (ss_reg + 1)
 473 #define fs_reg                  (ds_reg + 1)
 474 #define gs_reg                  (fs_reg + 1)
 475
 476 #define eAX_reg                 (gs_reg + 1)
 477 #define eCX_reg                 (eAX_reg + 1)
 478 #define eDX_reg                 (eCX_reg + 1)
 479 #define eBX_reg                 (eDX_reg + 1)
 480 #define eSP_reg                 (eBX_reg + 1)
 481 #define eBP_reg                 (eSP_reg + 1)
 482 #define eSI_reg                 (eBP_reg + 1)
 483 #define eDI_reg                 (eSI_reg + 1)
 484
 485 #define al_reg                  (eDI_reg + 1)
 486 #define cl_reg                  (al_reg + 1)
 487 #define dl_reg                  (cl_reg + 1)
 488 #define bl_reg                  (dl_reg + 1)
 489 #define ah_reg                  (bl_reg + 1)
 490 #define ch_reg                  (ah_reg + 1)
 491 #define dh_reg                  (ch_reg + 1)
 492 #define bh_reg                  (dh_reg + 1)
 493
 494 #define ax_reg                  (bh_reg + 1)
 495 #define cx_reg                  (ax_reg + 1)
 496 #define dx_reg                  (cx_reg + 1)
 497 #define bx_reg                  (dx_reg + 1)
 498 #define sp_reg                  (bx_reg + 1)
 499 #define bp_reg                  (sp_reg + 1)
 500 #define si_reg                  (bp_reg + 1)
 501 #define di_reg                  (si_reg + 1)
 502
 503 #define rAX_reg                 (di_reg + 1)
 504 #define rCX_reg                 (rAX_reg + 1)
 505 #define rDX_reg                 (rCX_reg + 1)
 506 #define rBX_reg                 (rDX_reg + 1)
 507 #define rSP_reg                 (rBX_reg + 1)
 508 #define rBP_reg                 (rSP_reg + 1)
 509 #define rSI_reg                 (rBP_reg + 1)
 510 #define rDI_reg                 (rSI_reg + 1)
 511
 512 #define z_mode_ax_reg           (rDI_reg + 1)
 513 #define indir_dx_reg            (z_mode_ax_reg + 1)
 514
 515 #define MAX_BYTEMODE    indir_dx_reg
 516
 517 /* Flags that are OR'ed into the bytemode field to pass extra
 518    information.  */
 519 #define DREX_OC1                0x10000 /* OC1 bit set */
 520 #define DREX_NO_OC0             0x20000 /* OC0 bit not used */
 521 #define DREX_MASK               0x40000 /* mask to delete */
 522
 523 #if MAX_BYTEMODE >= DREX_OC1
 524 #error MAX_BYTEMODE must be less than DREX_OC1
 525 #endif
 526
 527 #define FLOATCODE               1
 528 #define USE_REG_TABLE           (FLOATCODE + 1)
 529 #define USE_MOD_TABLE           (USE_REG_TABLE + 1)
 530 #define USE_RM_TABLE            (USE_MOD_TABLE + 1)
 531 #define USE_PREFIX_TABLE        (USE_RM_TABLE + 1)
 532 #define USE_X86_64_TABLE        (USE_PREFIX_TABLE + 1)
 533 #define USE_3BYTE_TABLE         (USE_X86_64_TABLE + 1)
 534 #define USE_VEX_C4_TABLE        (USE_3BYTE_TABLE + 1)
 535 #define USE_VEX_C5_TABLE        (USE_VEX_C4_TABLE + 1)
 536 #define USE_VEX_LEN_TABLE       (USE_VEX_C5_TABLE + 1)
 537
 538 #define FLOAT                   NULL, { { NULL, FLOATCODE } }
 539
 540 #define DIS386(T, I)            NULL, { { NULL, (T)}, { NULL,  (I) } }
 541 #define REG_TABLE(I)            DIS386 (USE_REG_TABLE, (I))
 542 #define MOD_TABLE(I)            DIS386 (USE_MOD_TABLE, (I))
 543 #define RM_TABLE(I)             DIS386 (USE_RM_TABLE, (I))
 544 #define PREFIX_TABLE(I)         DIS386 (USE_PREFIX_TABLE, (I))
 545 #define X86_64_TABLE(I)         DIS386 (USE_X86_64_TABLE, (I))
 546 #define THREE_BYTE_TABLE(I)     DIS386 (USE_3BYTE_TABLE, (I))
 547 #define VEX_C4_TABLE(I)         DIS386 (USE_VEX_C4_TABLE, (I))
 548 #define VEX_C5_TABLE(I)         DIS386 (USE_VEX_C5_TABLE, (I))
 549 #define VEX_LEN_TABLE(I)        DIS386 (USE_VEX_LEN_TABLE, (I))
 550
 551 #define REG_80                  0
 552 #define REG_81                  (REG_80 + 1)
 553 #define REG_82                  (REG_81 + 1)
 554 #define REG_8F                  (REG_82 + 1)
 555 #define REG_C0                  (REG_8F + 1)
 556 #define REG_C1                  (REG_C0 + 1)
 557 #define REG_C6                  (REG_C1 + 1)
 558 #define REG_C7                  (REG_C6 + 1)
 559 #define REG_D0                  (REG_C7 + 1)
 560 #define REG_D1                  (REG_D0 + 1)
 561 #define REG_D2                  (REG_D1 + 1)
 562 #define REG_D3                  (REG_D2 + 1)
 563 #define REG_F6                  (REG_D3 + 1)
 564 #define REG_F7                  (REG_F6 + 1)
 565 #define REG_FE                  (REG_F7 + 1)
 566 #define REG_FF                  (REG_FE + 1)
 567 #define REG_0F00                (REG_FF + 1)
 568 #define REG_0F01                (REG_0F00 + 1)
 569 #define REG_0F0D                (REG_0F01 + 1)
 570 #define REG_0F18                (REG_0F0D + 1)
 571 #define REG_0F71                (REG_0F18 + 1)
 572 #define REG_0F72                (REG_0F71 + 1)
 573 #define REG_0F73                (REG_0F72 + 1)
 574 #define REG_0FA6                (REG_0F73 + 1)
 575 #define REG_0FA7                (REG_0FA6 + 1)
 576 #define REG_0FAE                (REG_0FA7 + 1)
 577 #define REG_0FBA                (REG_0FAE + 1)
 578 #define REG_0FC7                (REG_0FBA + 1)
 579 #define REG_VEX_71              (REG_0FC7 + 1)
 580 #define REG_VEX_72              (REG_VEX_71 + 1)
 581 #define REG_VEX_73              (REG_VEX_72 + 1)
 582 #define REG_VEX_AE              (REG_VEX_73 + 1)
 583
 584 #define MOD_8D                  0
 585 #define MOD_0F01_REG_0          (MOD_8D + 1)
 586 #define MOD_0F01_REG_1          (MOD_0F01_REG_0 + 1)
 587 #define MOD_0F01_REG_2          (MOD_0F01_REG_1 + 1)
 588 #define MOD_0F01_REG_3          (MOD_0F01_REG_2 + 1)
 589 #define MOD_0F01_REG_7          (MOD_0F01_REG_3 + 1)
 590 #define MOD_0F12_PREFIX_0       (MOD_0F01_REG_7 + 1)
 591 #define MOD_0F13                (MOD_0F12_PREFIX_0 + 1)
 592 #define MOD_0F16_PREFIX_0       (MOD_0F13 + 1)
 593 #define MOD_0F17                (MOD_0F16_PREFIX_0 + 1)
 594 #define MOD_0F18_REG_0          (MOD_0F17 + 1)
 595 #define MOD_0F18_REG_1          (MOD_0F18_REG_0 + 1)
 596 #define MOD_0F18_REG_2          (MOD_0F18_REG_1 + 1)
 597 #define MOD_0F18_REG_3          (MOD_0F18_REG_2 + 1)
 598 #define MOD_0F20                (MOD_0F18_REG_3 + 1)
 599 #define MOD_0F21                (MOD_0F20 + 1)
 600 #define MOD_0F22                (MOD_0F21 + 1)
 601 #define MOD_0F23                (MOD_0F22 + 1)
 602 #define MOD_0F24                (MOD_0F23 + 1)
 603 #define MOD_0F26                (MOD_0F24 + 1)
 604 #define MOD_0F2B_PREFIX_0       (MOD_0F26 + 1)
 605 #define MOD_0F2B_PREFIX_1       (MOD_0F2B_PREFIX_0 + 1)
 606 #define MOD_0F2B_PREFIX_2       (MOD_0F2B_PREFIX_1 + 1)
 607 #define MOD_0F2B_PREFIX_3       (MOD_0F2B_PREFIX_2 + 1)
 608 #define MOD_0F51                (MOD_0F2B_PREFIX_3 + 1)
 609 #define MOD_0F71_REG_2          (MOD_0F51 + 1)
 610 #define MOD_0F71_REG_4          (MOD_0F71_REG_2 + 1)
 611 #define MOD_0F71_REG_6          (MOD_0F71_REG_4 + 1)
 612 #define MOD_0F72_REG_2          (MOD_0F71_REG_6 + 1)
 613 #define MOD_0F72_REG_4          (MOD_0F72_REG_2 + 1)
 614 #define MOD_0F72_REG_6          (MOD_0F72_REG_4 + 1)
 615 #define MOD_0F73_REG_2          (MOD_0F72_REG_6 + 1)
 616 #define MOD_0F73_REG_3          (MOD_0F73_REG_2 + 1)
 617 #define MOD_0F73_REG_6          (MOD_0F73_REG_3 + 1)
 618 #define MOD_0F73_REG_7          (MOD_0F73_REG_6 + 1)
 619 #define MOD_0FAE_REG_0          (MOD_0F73_REG_7 + 1)
 620 #define MOD_0FAE_REG_1          (MOD_0FAE_REG_0 + 1)
 621 #define MOD_0FAE_REG_2          (MOD_0FAE_REG_1 + 1)
 622 #define MOD_0FAE_REG_3          (MOD_0FAE_REG_2 + 1)
 623 #define MOD_0FAE_REG_4          (MOD_0FAE_REG_3 + 1)
 624 #define MOD_0FAE_REG_5          (MOD_0FAE_REG_4 + 1)
 625 #define MOD_0FAE_REG_6          (MOD_0FAE_REG_5 + 1)
 626 #define MOD_0FAE_REG_7          (MOD_0FAE_REG_6 + 1)
 627 #define MOD_0FB2                (MOD_0FAE_REG_7 + 1)
 628 #define MOD_0FB4                (MOD_0FB2 + 1)
 629 #define MOD_0FB5                (MOD_0FB4 + 1)
 630 #define MOD_0FC7_REG_6          (MOD_0FB5 + 1)
 631 #define MOD_0FC7_REG_7          (MOD_0FC7_REG_6 + 1)
 632 #define MOD_0FD7                (MOD_0FC7_REG_7 + 1)
 633 #define MOD_0FE7_PREFIX_2       (MOD_0FD7 + 1)
 634 #define MOD_0FF0_PREFIX_3       (MOD_0FE7_PREFIX_2 + 1)
 635 #define MOD_0F382A_PREFIX_2     (MOD_0FF0_PREFIX_3 + 1)
 636 #define MOD_62_32BIT            (MOD_0F382A_PREFIX_2 + 1)
 637 #define MOD_C4_32BIT            (MOD_62_32BIT + 1)
 638 #define MOD_C5_32BIT            (MOD_C4_32BIT + 1)
 639 #define MOD_VEX_12_PREFIX_0     (MOD_C5_32BIT + 1)
 640 #define MOD_VEX_13              (MOD_VEX_12_PREFIX_0 + 1)
 641 #define MOD_VEX_16_PREFIX_0     (MOD_VEX_13 + 1)
 642 #define MOD_VEX_17              (MOD_VEX_16_PREFIX_0 + 1)
 643 #define MOD_VEX_2B              (MOD_VEX_17 + 1)
 644 #define MOD_VEX_51              (MOD_VEX_2B + 1)
 645 #define MOD_VEX_71_REG_2        (MOD_VEX_51 + 1)
 646 #define MOD_VEX_71_REG_4        (MOD_VEX_71_REG_2 + 1)
 647 #define MOD_VEX_71_REG_6        (MOD_VEX_71_REG_4 + 1)
 648 #define MOD_VEX_72_REG_2        (MOD_VEX_71_REG_6 + 1)
 649 #define MOD_VEX_72_REG_4        (MOD_VEX_72_REG_2 + 1)
 650 #define MOD_VEX_72_REG_6        (MOD_VEX_72_REG_4 + 1)
 651 #define MOD_VEX_73_REG_2        (MOD_VEX_72_REG_6 + 1)
 652 #define MOD_VEX_73_REG_3        (MOD_VEX_73_REG_2 + 1)
 653 #define MOD_VEX_73_REG_6        (MOD_VEX_73_REG_3 + 1)
 654 #define MOD_VEX_73_REG_7        (MOD_VEX_73_REG_6 + 1)
 655 #define MOD_VEX_AE_REG_2        (MOD_VEX_73_REG_7 + 1)
 656 #define MOD_VEX_AE_REG_3        (MOD_VEX_AE_REG_2 + 1)
 657 #define MOD_VEX_D7_PREFIX_2     (MOD_VEX_AE_REG_3 + 1)
 658 #define MOD_VEX_E7_PREFIX_2     (MOD_VEX_D7_PREFIX_2 + 1)
 659 #define MOD_VEX_F0_PREFIX_3     (MOD_VEX_E7_PREFIX_2 + 1)
 660 #define MOD_VEX_3818_PREFIX_2   (MOD_VEX_F0_PREFIX_3 + 1)
 661 #define MOD_VEX_3819_PREFIX_2   (MOD_VEX_3818_PREFIX_2 + 1)
 662 #define MOD_VEX_381A_PREFIX_2   (MOD_VEX_3819_PREFIX_2 + 1)
 663 #define MOD_VEX_382A_PREFIX_2   (MOD_VEX_381A_PREFIX_2 + 1)
 664 #define MOD_VEX_382C_PREFIX_2   (MOD_VEX_382A_PREFIX_2 + 1)
 665 #define MOD_VEX_382D_PREFIX_2   (MOD_VEX_382C_PREFIX_2 + 1)
 666 #define MOD_VEX_382E_PREFIX_2   (MOD_VEX_382D_PREFIX_2 + 1)
 667 #define MOD_VEX_382F_PREFIX_2   (MOD_VEX_382E_PREFIX_2 + 1)
 668
 669 #define RM_0F01_REG_0           0
 670 #define RM_0F01_REG_1           (RM_0F01_REG_0 + 1)
 671 #define RM_0F01_REG_2           (RM_0F01_REG_1 + 1)
 672 #define RM_0F01_REG_3           (RM_0F01_REG_2 + 1)
 673 #define RM_0F01_REG_7           (RM_0F01_REG_3 + 1)
 674 #define RM_0FAE_REG_5           (RM_0F01_REG_7 + 1)
 675 #define RM_0FAE_REG_6           (RM_0FAE_REG_5 + 1)
 676 #define RM_0FAE_REG_7           (RM_0FAE_REG_6 + 1)
 677
 678 #define PREFIX_90               0
 679 #define PREFIX_0F10             (PREFIX_90 + 1)
 680 #define PREFIX_0F11             (PREFIX_0F10 + 1)
 681 #define PREFIX_0F12             (PREFIX_0F11 + 1)
 682 #define PREFIX_0F16             (PREFIX_0F12 + 1)
 683 #define PREFIX_0F2A             (PREFIX_0F16 + 1)
 684 #define PREFIX_0F2B             (PREFIX_0F2A + 1)
 685 #define PREFIX_0F2C             (PREFIX_0F2B + 1)
 686 #define PREFIX_0F2D             (PREFIX_0F2C + 1)
 687 #define PREFIX_0F2E             (PREFIX_0F2D + 1)
 688 #define PREFIX_0F2F             (PREFIX_0F2E + 1)
 689 #define PREFIX_0F51             (PREFIX_0F2F + 1)
 690 #define PREFIX_0F52             (PREFIX_0F51 + 1)
 691 #define PREFIX_0F53             (PREFIX_0F52 + 1)
 692 #define PREFIX_0F58             (PREFIX_0F53 + 1)
 693 #define PREFIX_0F59             (PREFIX_0F58 + 1)
 694 #define PREFIX_0F5A             (PREFIX_0F59 + 1)
 695 #define PREFIX_0F5B             (PREFIX_0F5A + 1)
 696 #define PREFIX_0F5C             (PREFIX_0F5B + 1)
 697 #define PREFIX_0F5D             (PREFIX_0F5C + 1)
 698 #define PREFIX_0F5E             (PREFIX_0F5D + 1)
 699 #define PREFIX_0F5F             (PREFIX_0F5E + 1)
 700 #define PREFIX_0F60             (PREFIX_0F5F + 1)
 701 #define PREFIX_0F61             (PREFIX_0F60 + 1)
 702 #define PREFIX_0F62             (PREFIX_0F61 + 1)
 703 #define PREFIX_0F6C             (PREFIX_0F62 + 1)
 704 #define PREFIX_0F6D             (PREFIX_0F6C + 1)
 705 #define PREFIX_0F6F             (PREFIX_0F6D + 1)
 706 #define PREFIX_0F70             (PREFIX_0F6F + 1)
 707 #define PREFIX_0F73_REG_3       (PREFIX_0F70 + 1)
 708 #define PREFIX_0F73_REG_7       (PREFIX_0F73_REG_3 + 1)
 709 #define PREFIX_0F78             (PREFIX_0F73_REG_7 + 1)
 710 #define PREFIX_0F79             (PREFIX_0F78 + 1)
 711 #define PREFIX_0F7C             (PREFIX_0F79 + 1)
 712 #define PREFIX_0F7D             (PREFIX_0F7C + 1)
 713 #define PREFIX_0F7E             (PREFIX_0F7D + 1)
 714 #define PREFIX_0F7F             (PREFIX_0F7E + 1)
 715 #define PREFIX_0FB8             (PREFIX_0F7F + 1)
 716 #define PREFIX_0FBD             (PREFIX_0FB8 + 1)
 717 #define PREFIX_0FC2             (PREFIX_0FBD + 1)
 718 #define PREFIX_0FC3             (PREFIX_0FC2 + 1)
 719 #define PREFIX_0FC7_REG_6       (PREFIX_0FC3 + 1)
 720 #define PREFIX_0FD0             (PREFIX_0FC7_REG_6 + 1)
 721 #define PREFIX_0FD6             (PREFIX_0FD0 + 1)
 722 #define PREFIX_0FE6             (PREFIX_0FD6 + 1)
 723 #define PREFIX_0FE7             (PREFIX_0FE6 + 1)
 724 #define PREFIX_0FF0             (PREFIX_0FE7 + 1)
 725 #define PREFIX_0FF7             (PREFIX_0FF0 + 1)
 726 #define PREFIX_0F3810           (PREFIX_0FF7 + 1)
 727 #define PREFIX_0F3814           (PREFIX_0F3810 + 1)
 728 #define PREFIX_0F3815           (PREFIX_0F3814 + 1)
 729 #define PREFIX_0F3817           (PREFIX_0F3815 + 1)
 730 #define PREFIX_0F3820           (PREFIX_0F3817 + 1)
 731 #define PREFIX_0F3821           (PREFIX_0F3820 + 1)
 732 #define PREFIX_0F3822           (PREFIX_0F3821 + 1)
 733 #define PREFIX_0F3823           (PREFIX_0F3822 + 1)
 734 #define PREFIX_0F3824           (PREFIX_0F3823 + 1)
 735 #define PREFIX_0F3825           (PREFIX_0F3824 + 1)
 736 #define PREFIX_0F3828           (PREFIX_0F3825 + 1)
 737 #define PREFIX_0F3829           (PREFIX_0F3828 + 1)
 738 #define PREFIX_0F382A           (PREFIX_0F3829 + 1)
 739 #define PREFIX_0F382B           (PREFIX_0F382A + 1)
 740 #define PREFIX_0F3830           (PREFIX_0F382B + 1)
 741 #define PREFIX_0F3831           (PREFIX_0F3830 + 1)
 742 #define PREFIX_0F3832           (PREFIX_0F3831 + 1)
 743 #define PREFIX_0F3833           (PREFIX_0F3832 + 1)
 744 #define PREFIX_0F3834           (PREFIX_0F3833 + 1)
 745 #define PREFIX_0F3835           (PREFIX_0F3834 + 1)
 746 #define PREFIX_0F3837           (PREFIX_0F3835 + 1)
 747 #define PREFIX_0F3838           (PREFIX_0F3837 + 1)
 748 #define PREFIX_0F3839           (PREFIX_0F3838 + 1)
 749 #define PREFIX_0F383A           (PREFIX_0F3839 + 1)
 750 #define PREFIX_0F383B           (PREFIX_0F383A + 1)
 751 #define PREFIX_0F383C           (PREFIX_0F383B + 1)
 752 #define PREFIX_0F383D           (PREFIX_0F383C + 1)
 753 #define PREFIX_0F383E           (PREFIX_0F383D + 1)
 754 #define PREFIX_0F383F           (PREFIX_0F383E + 1)
 755 #define PREFIX_0F3840           (PREFIX_0F383F + 1)
 756 #define PREFIX_0F3841           (PREFIX_0F3840 + 1)
 757 #define PREFIX_0F3880           (PREFIX_0F3841 + 1)
 758 #define PREFIX_0F3881           (PREFIX_0F3880 + 1)
 759 #define PREFIX_0F38DB           (PREFIX_0F3881 + 1)
 760 #define PREFIX_0F38DC           (PREFIX_0F38DB + 1)
 761 #define PREFIX_0F38DD           (PREFIX_0F38DC + 1)
 762 #define PREFIX_0F38DE           (PREFIX_0F38DD + 1)
 763 #define PREFIX_0F38DF           (PREFIX_0F38DE + 1)
 764 #define PREFIX_0F38F0           (PREFIX_0F38DF + 1)
 765 #define PREFIX_0F38F1           (PREFIX_0F38F0 + 1)
 766 #define PREFIX_0F3A08           (PREFIX_0F38F1 + 1)
 767 #define PREFIX_0F3A09           (PREFIX_0F3A08 + 1)
 768 #define PREFIX_0F3A0A           (PREFIX_0F3A09 + 1)
 769 #define PREFIX_0F3A0B           (PREFIX_0F3A0A + 1)
 770 #define PREFIX_0F3A0C           (PREFIX_0F3A0B + 1)
 771 #define PREFIX_0F3A0D           (PREFIX_0F3A0C + 1)
 772 #define PREFIX_0F3A0E           (PREFIX_0F3A0D + 1)
 773 #define PREFIX_0F3A14           (PREFIX_0F3A0E + 1)
 774 #define PREFIX_0F3A15           (PREFIX_0F3A14 + 1)
 775 #define PREFIX_0F3A16           (PREFIX_0F3A15 + 1)
 776 #define PREFIX_0F3A17           (PREFIX_0F3A16 + 1)
 777 #define PREFIX_0F3A20           (PREFIX_0F3A17 + 1)
 778 #define PREFIX_0F3A21           (PREFIX_0F3A20 + 1)
 779 #define PREFIX_0F3A22           (PREFIX_0F3A21 + 1)
 780 #define PREFIX_0F3A40           (PREFIX_0F3A22 + 1)
 781 #define PREFIX_0F3A41           (PREFIX_0F3A40 + 1)
 782 #define PREFIX_0F3A42           (PREFIX_0F3A41 + 1)
 783 #define PREFIX_0F3A44           (PREFIX_0F3A42 + 1)
 784 #define PREFIX_0F3A60           (PREFIX_0F3A44 + 1)
 785 #define PREFIX_0F3A61           (PREFIX_0F3A60 + 1)
 786 #define PREFIX_0F3A62           (PREFIX_0F3A61 + 1)
 787 #define PREFIX_0F3A63           (PREFIX_0F3A62 + 1)
 788 #define PREFIX_0F3ADF           (PREFIX_0F3A63 + 1)
 789 #define PREFIX_VEX_10           (PREFIX_0F3ADF + 1)
 790 #define PREFIX_VEX_11           (PREFIX_VEX_10 + 1)
 791 #define PREFIX_VEX_12           (PREFIX_VEX_11 + 1)
 792 #define PREFIX_VEX_16           (PREFIX_VEX_12 + 1)
 793 #define PREFIX_VEX_2A           (PREFIX_VEX_16 + 1)
 794 #define PREFIX_VEX_2C           (PREFIX_VEX_2A + 1)
 795 #define PREFIX_VEX_2D           (PREFIX_VEX_2C + 1)
 796 #define PREFIX_VEX_2E           (PREFIX_VEX_2D + 1)
 797 #define PREFIX_VEX_2F           (PREFIX_VEX_2E + 1)
 798 #define PREFIX_VEX_51           (PREFIX_VEX_2F + 1)
 799 #define PREFIX_VEX_52           (PREFIX_VEX_51 + 1)
 800 #define PREFIX_VEX_53           (PREFIX_VEX_52 + 1)
 801 #define PREFIX_VEX_58           (PREFIX_VEX_53 + 1)
 802 #define PREFIX_VEX_59           (PREFIX_VEX_58 + 1)
 803 #define PREFIX_VEX_5A           (PREFIX_VEX_59 + 1)
 804 #define PREFIX_VEX_5B           (PREFIX_VEX_5A + 1)
 805 #define PREFIX_VEX_5C           (PREFIX_VEX_5B + 1)
 806 #define PREFIX_VEX_5D           (PREFIX_VEX_5C + 1)
 807 #define PREFIX_VEX_5E           (PREFIX_VEX_5D + 1)
 808 #define PREFIX_VEX_5F           (PREFIX_VEX_5E + 1)
 809 #define PREFIX_VEX_60           (PREFIX_VEX_5F + 1)
 810 #define PREFIX_VEX_61           (PREFIX_VEX_60 + 1)
 811 #define PREFIX_VEX_62           (PREFIX_VEX_61 + 1)
 812 #define PREFIX_VEX_63           (PREFIX_VEX_62 + 1)
 813 #define PREFIX_VEX_64           (PREFIX_VEX_63 + 1)
 814 #define PREFIX_VEX_65           (PREFIX_VEX_64 + 1)
 815 #define PREFIX_VEX_66           (PREFIX_VEX_65 + 1)
 816 #define PREFIX_VEX_67           (PREFIX_VEX_66 + 1)
 817 #define PREFIX_VEX_68           (PREFIX_VEX_67 + 1)
 818 #define PREFIX_VEX_69           (PREFIX_VEX_68 + 1)
 819 #define PREFIX_VEX_6A           (PREFIX_VEX_69 + 1)
 820 #define PREFIX_VEX_6B           (PREFIX_VEX_6A + 1)
 821 #define PREFIX_VEX_6C           (PREFIX_VEX_6B + 1)
 822 #define PREFIX_VEX_6D           (PREFIX_VEX_6C + 1)
 823 #define PREFIX_VEX_6E           (PREFIX_VEX_6D + 1)
 824 #define PREFIX_VEX_6F           (PREFIX_VEX_6E + 1)
 825 #define PREFIX_VEX_70           (PREFIX_VEX_6F + 1)
 826 #define PREFIX_VEX_71_REG_2     (PREFIX_VEX_70 + 1)
 827 #define PREFIX_VEX_71_REG_4     (PREFIX_VEX_71_REG_2 + 1)
 828 #define PREFIX_VEX_71_REG_6     (PREFIX_VEX_71_REG_4 + 1)
 829 #define PREFIX_VEX_72_REG_2     (PREFIX_VEX_71_REG_6 + 1)
 830 #define PREFIX_VEX_72_REG_4     (PREFIX_VEX_72_REG_2 + 1)
 831 #define PREFIX_VEX_72_REG_6     (PREFIX_VEX_72_REG_4 + 1)
 832 #define PREFIX_VEX_73_REG_2     (PREFIX_VEX_72_REG_6 + 1)
 833 #define PREFIX_VEX_73_REG_3     (PREFIX_VEX_73_REG_2 + 1)
 834 #define PREFIX_VEX_73_REG_6     (PREFIX_VEX_73_REG_3 + 1)
 835 #define PREFIX_VEX_73_REG_7     (PREFIX_VEX_73_REG_6 + 1)
 836 #define PREFIX_VEX_74           (PREFIX_VEX_73_REG_7 + 1)
 837 #define PREFIX_VEX_75           (PREFIX_VEX_74 + 1)
 838 #define PREFIX_VEX_76           (PREFIX_VEX_75 + 1)
 839 #define PREFIX_VEX_77           (PREFIX_VEX_76 + 1)
 840 #define PREFIX_VEX_7C           (PREFIX_VEX_77 + 1)
 841 #define PREFIX_VEX_7D           (PREFIX_VEX_7C + 1)
 842 #define PREFIX_VEX_7E           (PREFIX_VEX_7D + 1)
 843 #define PREFIX_VEX_7F           (PREFIX_VEX_7E + 1)
 844 #define PREFIX_VEX_C2           (PREFIX_VEX_7F + 1)
 845 #define PREFIX_VEX_C4           (PREFIX_VEX_C2 + 1)
 846 #define PREFIX_VEX_C5           (PREFIX_VEX_C4 + 1)
 847 #define PREFIX_VEX_D0           (PREFIX_VEX_C5 + 1)
 848 #define PREFIX_VEX_D1           (PREFIX_VEX_D0 + 1)
 849 #define PREFIX_VEX_D2           (PREFIX_VEX_D1 + 1)
 850 #define PREFIX_VEX_D3           (PREFIX_VEX_D2 + 1)
 851 #define PREFIX_VEX_D4           (PREFIX_VEX_D3 + 1)
 852 #define PREFIX_VEX_D5           (PREFIX_VEX_D4 + 1)
 853 #define PREFIX_VEX_D6           (PREFIX_VEX_D5 + 1)
 854 #define PREFIX_VEX_D7           (PREFIX_VEX_D6 + 1)
 855 #define PREFIX_VEX_D8           (PREFIX_VEX_D7 + 1)
 856 #define PREFIX_VEX_D9           (PREFIX_VEX_D8 + 1)
 857 #define PREFIX_VEX_DA           (PREFIX_VEX_D9 + 1)
 858 #define PREFIX_VEX_DB           (PREFIX_VEX_DA + 1)
 859 #define PREFIX_VEX_DC           (PREFIX_VEX_DB + 1)
 860 #define PREFIX_VEX_DD           (PREFIX_VEX_DC + 1)
 861 #define PREFIX_VEX_DE           (PREFIX_VEX_DD + 1)
 862 #define PREFIX_VEX_DF           (PREFIX_VEX_DE + 1)
 863 #define PREFIX_VEX_E0           (PREFIX_VEX_DF + 1)
 864 #define PREFIX_VEX_E1           (PREFIX_VEX_E0 + 1)
 865 #define PREFIX_VEX_E2           (PREFIX_VEX_E1 + 1)
 866 #define PREFIX_VEX_E3           (PREFIX_VEX_E2 + 1)
 867 #define PREFIX_VEX_E4           (PREFIX_VEX_E3 + 1)
 868 #define PREFIX_VEX_E5           (PREFIX_VEX_E4 + 1)
 869 #define PREFIX_VEX_E6           (PREFIX_VEX_E5 + 1)
 870 #define PREFIX_VEX_E7           (PREFIX_VEX_E6 + 1)
 871 #define PREFIX_VEX_E8           (PREFIX_VEX_E7 + 1)
 872 #define PREFIX_VEX_E9           (PREFIX_VEX_E8 + 1)
 873 #define PREFIX_VEX_EA           (PREFIX_VEX_E9 + 1)
 874 #define PREFIX_VEX_EB           (PREFIX_VEX_EA + 1)
 875 #define PREFIX_VEX_EC           (PREFIX_VEX_EB + 1)
 876 #define PREFIX_VEX_ED           (PREFIX_VEX_EC + 1)
 877 #define PREFIX_VEX_EE           (PREFIX_VEX_ED + 1)
 878 #define PREFIX_VEX_EF           (PREFIX_VEX_EE + 1)
 879 #define PREFIX_VEX_F0           (PREFIX_VEX_EF + 1)
 880 #define PREFIX_VEX_F1           (PREFIX_VEX_F0 + 1)
 881 #define PREFIX_VEX_F2           (PREFIX_VEX_F1 + 1)
 882 #define PREFIX_VEX_F3           (PREFIX_VEX_F2 + 1)
 883 #define PREFIX_VEX_F4           (PREFIX_VEX_F3 + 1)
 884 #define PREFIX_VEX_F5           (PREFIX_VEX_F4 + 1)
 885 #define PREFIX_VEX_F6           (PREFIX_VEX_F5 + 1)
 886 #define PREFIX_VEX_F7           (PREFIX_VEX_F6 + 1)
 887 #define PREFIX_VEX_F8           (PREFIX_VEX_F7 + 1)
 888 #define PREFIX_VEX_F9           (PREFIX_VEX_F8 + 1)
 889 #define PREFIX_VEX_FA           (PREFIX_VEX_F9 + 1)
 890 #define PREFIX_VEX_FB           (PREFIX_VEX_FA + 1)
 891 #define PREFIX_VEX_FC           (PREFIX_VEX_FB + 1)
 892 #define PREFIX_VEX_FD           (PREFIX_VEX_FC + 1)
 893 #define PREFIX_VEX_FE           (PREFIX_VEX_FD + 1)
 894 #define PREFIX_VEX_3800         (PREFIX_VEX_FE + 1)
 895 #define PREFIX_VEX_3801         (PREFIX_VEX_3800 + 1)
 896 #define PREFIX_VEX_3802         (PREFIX_VEX_3801 + 1)
 897 #define PREFIX_VEX_3803         (PREFIX_VEX_3802 + 1)
 898 #define PREFIX_VEX_3804         (PREFIX_VEX_3803 + 1)
 899 #define PREFIX_VEX_3805         (PREFIX_VEX_3804 + 1)
 900 #define PREFIX_VEX_3806         (PREFIX_VEX_3805 + 1)
 901 #define PREFIX_VEX_3807         (PREFIX_VEX_3806 + 1)
 902 #define PREFIX_VEX_3808         (PREFIX_VEX_3807 + 1)
 903 #define PREFIX_VEX_3809         (PREFIX_VEX_3808 + 1)
 904 #define PREFIX_VEX_380A         (PREFIX_VEX_3809 + 1)
 905 #define PREFIX_VEX_380B         (PREFIX_VEX_380A + 1)
 906 #define PREFIX_VEX_380C         (PREFIX_VEX_380B + 1)
 907 #define PREFIX_VEX_380D         (PREFIX_VEX_380C + 1)
 908 #define PREFIX_VEX_380E         (PREFIX_VEX_380D + 1)
 909 #define PREFIX_VEX_380F         (PREFIX_VEX_380E + 1)
 910 #define PREFIX_VEX_3817         (PREFIX_VEX_380F + 1)
 911 #define PREFIX_VEX_3818         (PREFIX_VEX_3817 + 1)
 912 #define PREFIX_VEX_3819         (PREFIX_VEX_3818 + 1)
 913 #define PREFIX_VEX_381A         (PREFIX_VEX_3819 + 1)
 914 #define PREFIX_VEX_381C         (PREFIX_VEX_381A + 1)
 915 #define PREFIX_VEX_381D         (PREFIX_VEX_381C + 1)
 916 #define PREFIX_VEX_381E         (PREFIX_VEX_381D + 1)
 917 #define PREFIX_VEX_3820         (PREFIX_VEX_381E + 1)
 918 #define PREFIX_VEX_3821         (PREFIX_VEX_3820 + 1)
 919 #define PREFIX_VEX_3822         (PREFIX_VEX_3821 + 1)
 920 #define PREFIX_VEX_3823         (PREFIX_VEX_3822 + 1)
 921 #define PREFIX_VEX_3824         (PREFIX_VEX_3823 + 1)
 922 #define PREFIX_VEX_3825         (PREFIX_VEX_3824 + 1)
 923 #define PREFIX_VEX_3828         (PREFIX_VEX_3825 + 1)
 924 #define PREFIX_VEX_3829         (PREFIX_VEX_3828 + 1)
 925 #define PREFIX_VEX_382A         (PREFIX_VEX_3829 + 1)
 926 #define PREFIX_VEX_382B         (PREFIX_VEX_382A + 1)
 927 #define PREFIX_VEX_382C         (PREFIX_VEX_382B + 1)
 928 #define PREFIX_VEX_382D         (PREFIX_VEX_382C + 1)
 929 #define PREFIX_VEX_382E         (PREFIX_VEX_382D + 1)
 930 #define PREFIX_VEX_382F         (PREFIX_VEX_382E + 1)
 931 #define PREFIX_VEX_3830         (PREFIX_VEX_382F + 1)
 932 #define PREFIX_VEX_3831         (PREFIX_VEX_3830 + 1)
 933 #define PREFIX_VEX_3832         (PREFIX_VEX_3831 + 1)
 934 #define PREFIX_VEX_3833         (PREFIX_VEX_3832 + 1)
 935 #define PREFIX_VEX_3834         (PREFIX_VEX_3833 + 1)
 936 #define PREFIX_VEX_3835         (PREFIX_VEX_3834 + 1)
 937 #define PREFIX_VEX_3837         (PREFIX_VEX_3835 + 1)
 938 #define PREFIX_VEX_3838         (PREFIX_VEX_3837 + 1)
 939 #define PREFIX_VEX_3839         (PREFIX_VEX_3838 + 1)
 940 #define PREFIX_VEX_383A         (PREFIX_VEX_3839 + 1)
 941 #define PREFIX_VEX_383B         (PREFIX_VEX_383A + 1)
 942 #define PREFIX_VEX_383C         (PREFIX_VEX_383B + 1)
 943 #define PREFIX_VEX_383D         (PREFIX_VEX_383C + 1)
 944 #define PREFIX_VEX_383E         (PREFIX_VEX_383D + 1)
 945 #define PREFIX_VEX_383F         (PREFIX_VEX_383E + 1)
 946 #define PREFIX_VEX_3840         (PREFIX_VEX_383F + 1)
 947 #define PREFIX_VEX_3841         (PREFIX_VEX_3840 + 1)
 948 #define PREFIX_VEX_3896         (PREFIX_VEX_3841 + 1)
 949 #define PREFIX_VEX_3897         (PREFIX_VEX_3896 + 1)
 950 #define PREFIX_VEX_3898         (PREFIX_VEX_3897 + 1)
 951 #define PREFIX_VEX_3899         (PREFIX_VEX_3898 + 1)
 952 #define PREFIX_VEX_389A         (PREFIX_VEX_3899 + 1)
 953 #define PREFIX_VEX_389B         (PREFIX_VEX_389A + 1)
 954 #define PREFIX_VEX_389C         (PREFIX_VEX_389B + 1)
 955 #define PREFIX_VEX_389D         (PREFIX_VEX_389C + 1)
 956 #define PREFIX_VEX_389E         (PREFIX_VEX_389D + 1)
 957 #define PREFIX_VEX_389F         (PREFIX_VEX_389E + 1)
 958 #define PREFIX_VEX_38A6         (PREFIX_VEX_389F + 1)
 959 #define PREFIX_VEX_38A7         (PREFIX_VEX_38A6 + 1)
 960 #define PREFIX_VEX_38A8         (PREFIX_VEX_38A7 + 1)
 961 #define PREFIX_VEX_38A9         (PREFIX_VEX_38A8 + 1)
 962 #define PREFIX_VEX_38AA         (PREFIX_VEX_38A9 + 1)
 963 #define PREFIX_VEX_38AB         (PREFIX_VEX_38AA + 1)
 964 #define PREFIX_VEX_38AC         (PREFIX_VEX_38AB + 1)
 965 #define PREFIX_VEX_38AD         (PREFIX_VEX_38AC + 1)
 966 #define PREFIX_VEX_38AE         (PREFIX_VEX_38AD + 1)
 967 #define PREFIX_VEX_38AF         (PREFIX_VEX_38AE + 1)
 968 #define PREFIX_VEX_38B6         (PREFIX_VEX_38AF + 1)
 969 #define PREFIX_VEX_38B7         (PREFIX_VEX_38B6 + 1)
 970 #define PREFIX_VEX_38B8         (PREFIX_VEX_38B7 + 1)
 971 #define PREFIX_VEX_38B9         (PREFIX_VEX_38B8 + 1)
 972 #define PREFIX_VEX_38BA         (PREFIX_VEX_38B9 + 1)
 973 #define PREFIX_VEX_38BB         (PREFIX_VEX_38BA + 1)
 974 #define PREFIX_VEX_38BC         (PREFIX_VEX_38BB + 1)
 975 #define PREFIX_VEX_38BD         (PREFIX_VEX_38BC + 1)
 976 #define PREFIX_VEX_38BE         (PREFIX_VEX_38BD + 1)
 977 #define PREFIX_VEX_38BF         (PREFIX_VEX_38BE + 1)
 978 #define PREFIX_VEX_38DB         (PREFIX_VEX_38BF + 1)
 979 #define PREFIX_VEX_38DC         (PREFIX_VEX_38DB + 1)
 980 #define PREFIX_VEX_38DD         (PREFIX_VEX_38DC + 1)
 981 #define PREFIX_VEX_38DE         (PREFIX_VEX_38DD + 1)
 982 #define PREFIX_VEX_38DF         (PREFIX_VEX_38DE + 1)
 983 #define PREFIX_VEX_3A04         (PREFIX_VEX_38DF + 1)
 984 #define PREFIX_VEX_3A05         (PREFIX_VEX_3A04 + 1)
 985 #define PREFIX_VEX_3A06         (PREFIX_VEX_3A05 + 1)
 986 #define PREFIX_VEX_3A08         (PREFIX_VEX_3A06 + 1)
 987 #define PREFIX_VEX_3A09         (PREFIX_VEX_3A08 + 1)
 988 #define PREFIX_VEX_3A0A         (PREFIX_VEX_3A09 + 1)
 989 #define PREFIX_VEX_3A0B         (PREFIX_VEX_3A0A + 1)
 990 #define PREFIX_VEX_3A0C         (PREFIX_VEX_3A0B + 1)
 991 #define PREFIX_VEX_3A0D         (PREFIX_VEX_3A0C + 1)
 992 #define PREFIX_VEX_3A0E         (PREFIX_VEX_3A0D + 1)
 993 #define PREFIX_VEX_3A0F         (PREFIX_VEX_3A0E + 1)
 994 #define PREFIX_VEX_3A14         (PREFIX_VEX_3A0F + 1)
 995 #define PREFIX_VEX_3A15         (PREFIX_VEX_3A14 + 1)
 996 #define PREFIX_VEX_3A16         (PREFIX_VEX_3A15 + 1)
 997 #define PREFIX_VEX_3A17         (PREFIX_VEX_3A16 + 1)
 998 #define PREFIX_VEX_3A18         (PREFIX_VEX_3A17 + 1)
 999 #define PREFIX_VEX_3A19         (PREFIX_VEX_3A18 + 1)
1000 #define PREFIX_VEX_3A20         (PREFIX_VEX_3A19 + 1)
1001 #define PREFIX_VEX_3A21         (PREFIX_VEX_3A20 + 1)
1002 #define PREFIX_VEX_3A22         (PREFIX_VEX_3A21 + 1)
1003 #define PREFIX_VEX_3A40         (PREFIX_VEX_3A22 + 1)
1004 #define PREFIX_VEX_3A41         (PREFIX_VEX_3A40 + 1)
1005 #define PREFIX_VEX_3A42         (PREFIX_VEX_3A41 + 1)
1006 #define PREFIX_VEX_3A44         (PREFIX_VEX_3A42 + 1)
1007 #define PREFIX_VEX_3A4A         (PREFIX_VEX_3A44 + 1)
1008 #define PREFIX_VEX_3A4B         (PREFIX_VEX_3A4A + 1)
1009 #define PREFIX_VEX_3A4C         (PREFIX_VEX_3A4B + 1)
1010 #define PREFIX_VEX_3A60         (PREFIX_VEX_3A4C + 1)
1011 #define PREFIX_VEX_3A61         (PREFIX_VEX_3A60 + 1)
1012 #define PREFIX_VEX_3A62         (PREFIX_VEX_3A61 + 1)
1013 #define PREFIX_VEX_3A63         (PREFIX_VEX_3A62 + 1)
1014 #define PREFIX_VEX_3ADF         (PREFIX_VEX_3A63 + 1)
1015
1016 #define X86_64_06               0
1017 #define X86_64_07               (X86_64_06 + 1)
1018 #define X86_64_0D               (X86_64_07 + 1)
1019 #define X86_64_16               (X86_64_0D + 1)
1020 #define X86_64_17               (X86_64_16 + 1)
1021 #define X86_64_1E               (X86_64_17 + 1)
1022 #define X86_64_1F               (X86_64_1E + 1)
1023 #define X86_64_27               (X86_64_1F + 1)
1024 #define X86_64_2F               (X86_64_27 + 1)
1025 #define X86_64_37               (X86_64_2F + 1)
1026 #define X86_64_3F               (X86_64_37 + 1)
1027 #define X86_64_60               (X86_64_3F + 1)
1028 #define X86_64_61               (X86_64_60 + 1)
1029 #define X86_64_62               (X86_64_61 + 1)
1030 #define X86_64_63               (X86_64_62 + 1)
1031 #define X86_64_6D               (X86_64_63 + 1)
1032 #define X86_64_6F               (X86_64_6D + 1)
1033 #define X86_64_9A               (X86_64_6F + 1)
1034 #define X86_64_C4               (X86_64_9A + 1)
1035 #define X86_64_C5               (X86_64_C4 + 1)
1036 #define X86_64_CE               (X86_64_C5 + 1)
1037 #define X86_64_D4               (X86_64_CE + 1)
1038 #define X86_64_D5               (X86_64_D4 + 1)
1039 #define X86_64_EA               (X86_64_D5 + 1)
1040 #define X86_64_0F01_REG_0       (X86_64_EA + 1)
1041 #define X86_64_0F01_REG_1       (X86_64_0F01_REG_0 + 1)
1042 #define X86_64_0F01_REG_2       (X86_64_0F01_REG_1 + 1)
1043 #define X86_64_0F01_REG_3       (X86_64_0F01_REG_2 + 1)
1044
1045 #define THREE_BYTE_0F24         0
1046 #define THREE_BYTE_0F25         (THREE_BYTE_0F24 + 1)
1047 #define THREE_BYTE_0F38         (THREE_BYTE_0F25 + 1)
1048 #define THREE_BYTE_0F3A         (THREE_BYTE_0F38 + 1)
1049 #define THREE_BYTE_0F7A         (THREE_BYTE_0F3A + 1)
1050 #define THREE_BYTE_0F7B         (THREE_BYTE_0F7A + 1)
1051
1052 #define VEX_0F                  0
1053 #define VEX_0F38                (VEX_0F + 1)
1054 #define VEX_0F3A                (VEX_0F38 + 1)
1055
1056 #define VEX_LEN_10_P_1  0
1057 #define VEX_LEN_10_P_3  (VEX_LEN_10_P_1 + 1)
1058 #define VEX_LEN_11_P_1  (VEX_LEN_10_P_3 + 1)
1059 #define VEX_LEN_11_P_3  (VEX_LEN_11_P_1 + 1)
1060 #define VEX_LEN_12_P_0_M_0      (VEX_LEN_11_P_3 + 1)
1061 #define VEX_LEN_12_P_0_M_1      (VEX_LEN_12_P_0_M_0 + 1)
1062 #define VEX_LEN_12_P_2  (VEX_LEN_12_P_0_M_1 + 1)
1063 #define VEX_LEN_13_M_0  (VEX_LEN_12_P_2 + 1)
1064 #define VEX_LEN_16_P_0_M_0      (VEX_LEN_13_M_0 + 1)
1065 #define VEX_LEN_16_P_0_M_1      (VEX_LEN_16_P_0_M_0 + 1)
1066 #define VEX_LEN_16_P_2  (VEX_LEN_16_P_0_M_1 + 1)
1067 #define VEX_LEN_17_M_0  (VEX_LEN_16_P_2 + 1)
1068 #define VEX_LEN_2A_P_1  (VEX_LEN_17_M_0 + 1)
1069 #define VEX_LEN_2A_P_3  (VEX_LEN_2A_P_1 + 1)
1070 #define VEX_LEN_2C_P_1  (VEX_LEN_2A_P_3 + 1)
1071 #define VEX_LEN_2C_P_3  (VEX_LEN_2C_P_1 + 1)
1072 #define VEX_LEN_2D_P_1  (VEX_LEN_2C_P_3 + 1)
1073 #define VEX_LEN_2D_P_3  (VEX_LEN_2D_P_1 + 1)
1074 #define VEX_LEN_2E_P_0  (VEX_LEN_2D_P_3 + 1)
1075 #define VEX_LEN_2E_P_2  (VEX_LEN_2E_P_0 + 1)
1076 #define VEX_LEN_2F_P_0  (VEX_LEN_2E_P_2 + 1)
1077 #define VEX_LEN_2F_P_2  (VEX_LEN_2F_P_0 + 1)
1078 #define VEX_LEN_51_P_1  (VEX_LEN_2F_P_2 + 1)
1079 #define VEX_LEN_51_P_3  (VEX_LEN_51_P_1 + 1)
1080 #define VEX_LEN_52_P_1  (VEX_LEN_51_P_3 + 1)
1081 #define VEX_LEN_53_P_1  (VEX_LEN_52_P_1 + 1)
1082 #define VEX_LEN_58_P_1  (VEX_LEN_53_P_1 + 1)
1083 #define VEX_LEN_58_P_3  (VEX_LEN_58_P_1 + 1)
1084 #define VEX_LEN_59_P_1  (VEX_LEN_58_P_3 + 1)
1085 #define VEX_LEN_59_P_3  (VEX_LEN_59_P_1 + 1)
1086 #define VEX_LEN_5A_P_1  (VEX_LEN_59_P_3 + 1)
1087 #define VEX_LEN_5A_P_3  (VEX_LEN_5A_P_1 + 1)
1088 #define VEX_LEN_5C_P_1  (VEX_LEN_5A_P_3 + 1)
1089 #define VEX_LEN_5C_P_3  (VEX_LEN_5C_P_1 + 1)
1090 #define VEX_LEN_5D_P_1  (VEX_LEN_5C_P_3 + 1)
1091 #define VEX_LEN_5D_P_3  (VEX_LEN_5D_P_1 + 1)
1092 #define VEX_LEN_5E_P_1  (VEX_LEN_5D_P_3 + 1)
1093 #define VEX_LEN_5E_P_3  (VEX_LEN_5E_P_1 + 1)
1094 #define VEX_LEN_5F_P_1  (VEX_LEN_5E_P_3 + 1)
1095 #define VEX_LEN_5F_P_3  (VEX_LEN_5F_P_1 + 1)
1096 #define VEX_LEN_60_P_2  (VEX_LEN_5F_P_3 + 1)
1097 #define VEX_LEN_61_P_2  (VEX_LEN_60_P_2 + 1)
1098 #define VEX_LEN_62_P_2  (VEX_LEN_61_P_2 + 1)
1099 #define VEX_LEN_63_P_2  (VEX_LEN_62_P_2 + 1)
1100 #define VEX_LEN_64_P_2  (VEX_LEN_63_P_2 + 1)
1101 #define VEX_LEN_65_P_2  (VEX_LEN_64_P_2 + 1)
1102 #define VEX_LEN_66_P_2  (VEX_LEN_65_P_2 + 1)
1103 #define VEX_LEN_67_P_2  (VEX_LEN_66_P_2 + 1)
1104 #define VEX_LEN_68_P_2  (VEX_LEN_67_P_2 + 1)
1105 #define VEX_LEN_69_P_2  (VEX_LEN_68_P_2 + 1)
1106 #define VEX_LEN_6A_P_2  (VEX_LEN_69_P_2 + 1)
1107 #define VEX_LEN_6B_P_2  (VEX_LEN_6A_P_2 + 1)
1108 #define VEX_LEN_6C_P_2  (VEX_LEN_6B_P_2 + 1)
1109 #define VEX_LEN_6D_P_2  (VEX_LEN_6C_P_2 + 1)
1110 #define VEX_LEN_6E_P_2  (VEX_LEN_6D_P_2 + 1)
1111 #define VEX_LEN_70_P_1  (VEX_LEN_6E_P_2 + 1)
1112 #define VEX_LEN_70_P_2  (VEX_LEN_70_P_1 + 1)
1113 #define VEX_LEN_70_P_3  (VEX_LEN_70_P_2 + 1)
1114 #define VEX_LEN_71_R_2_P_2      (VEX_LEN_70_P_3 + 1)
1115 #define VEX_LEN_71_R_4_P_2      (VEX_LEN_71_R_2_P_2 + 1)
1116 #define VEX_LEN_71_R_6_P_2      (VEX_LEN_71_R_4_P_2 + 1)
1117 #define VEX_LEN_72_R_2_P_2      (VEX_LEN_71_R_6_P_2 + 1)
1118 #define VEX_LEN_72_R_4_P_2      (VEX_LEN_72_R_2_P_2 + 1)
1119 #define VEX_LEN_72_R_6_P_2      (VEX_LEN_72_R_4_P_2 + 1)
1120 #define VEX_LEN_73_R_2_P_2      (VEX_LEN_72_R_6_P_2 + 1)
1121 #define VEX_LEN_73_R_3_P_2      (VEX_LEN_73_R_2_P_2 + 1)
1122 #define VEX_LEN_73_R_6_P_2      (VEX_LEN_73_R_3_P_2 + 1)
1123 #define VEX_LEN_73_R_7_P_2      (VEX_LEN_73_R_6_P_2 + 1)
1124 #define VEX_LEN_74_P_2  (VEX_LEN_73_R_7_P_2 + 1)
1125 #define VEX_LEN_75_P_2  (VEX_LEN_74_P_2 + 1)
1126 #define VEX_LEN_76_P_2  (VEX_LEN_75_P_2 + 1)
1127 #define VEX_LEN_7E_P_1  (VEX_LEN_76_P_2 + 1)
1128 #define VEX_LEN_7E_P_2  (VEX_LEN_7E_P_1 + 1)
1129 #define VEX_LEN_AE_R_2_M_0      (VEX_LEN_7E_P_2 + 1)
1130 #define VEX_LEN_AE_R_3_M_0      (VEX_LEN_AE_R_2_M_0 + 1)
1131 #define VEX_LEN_C2_P_1  (VEX_LEN_AE_R_3_M_0 + 1)
1132 #define VEX_LEN_C2_P_3  (VEX_LEN_C2_P_1 + 1)
1133 #define VEX_LEN_C4_P_2  (VEX_LEN_C2_P_3 + 1)
1134 #define VEX_LEN_C5_P_2  (VEX_LEN_C4_P_2 + 1)
1135 #define VEX_LEN_D1_P_2  (VEX_LEN_C5_P_2 + 1)
1136 #define VEX_LEN_D2_P_2  (VEX_LEN_D1_P_2 + 1)
1137 #define VEX_LEN_D3_P_2  (VEX_LEN_D2_P_2 + 1)
1138 #define VEX_LEN_D4_P_2  (VEX_LEN_D3_P_2 + 1)
1139 #define VEX_LEN_D5_P_2  (VEX_LEN_D4_P_2 + 1)
1140 #define VEX_LEN_D6_P_2  (VEX_LEN_D5_P_2 + 1)
1141 #define VEX_LEN_D7_P_2_M_1      (VEX_LEN_D6_P_2 + 1)
1142 #define VEX_LEN_D8_P_2  (VEX_LEN_D7_P_2_M_1 + 1)
1143 #define VEX_LEN_D9_P_2  (VEX_LEN_D8_P_2 + 1)
1144 #define VEX_LEN_DA_P_2  (VEX_LEN_D9_P_2 + 1)
1145 #define VEX_LEN_DB_P_2  (VEX_LEN_DA_P_2 + 1)
1146 #define VEX_LEN_DC_P_2  (VEX_LEN_DB_P_2 + 1)
1147 #define VEX_LEN_DD_P_2  (VEX_LEN_DC_P_2 + 1)
1148 #define VEX_LEN_DE_P_2  (VEX_LEN_DD_P_2 + 1)
1149 #define VEX_LEN_DF_P_2  (VEX_LEN_DE_P_2 + 1)
1150 #define VEX_LEN_E0_P_2  (VEX_LEN_DF_P_2 + 1)
1151 #define VEX_LEN_E1_P_2  (VEX_LEN_E0_P_2 + 1)
1152 #define VEX_LEN_E2_P_2  (VEX_LEN_E1_P_2 + 1)
1153 #define VEX_LEN_E3_P_2  (VEX_LEN_E2_P_2 + 1)
1154 #define VEX_LEN_E4_P_2  (VEX_LEN_E3_P_2 + 1)
1155 #define VEX_LEN_E5_P_2  (VEX_LEN_E4_P_2 + 1)
1156 #define VEX_LEN_E8_P_2  (VEX_LEN_E5_P_2 + 1)
1157 #define VEX_LEN_E9_P_2  (VEX_LEN_E8_P_2 + 1)
1158 #define VEX_LEN_EA_P_2  (VEX_LEN_E9_P_2 + 1)
1159 #define VEX_LEN_EB_P_2  (VEX_LEN_EA_P_2 + 1)
1160 #define VEX_LEN_EC_P_2  (VEX_LEN_EB_P_2 + 1)
1161 #define VEX_LEN_ED_P_2  (VEX_LEN_EC_P_2 + 1)
1162 #define VEX_LEN_EE_P_2  (VEX_LEN_ED_P_2 + 1)
1163 #define VEX_LEN_EF_P_2  (VEX_LEN_EE_P_2 + 1)
1164 #define VEX_LEN_F1_P_2  (VEX_LEN_EF_P_2 + 1)
1165 #define VEX_LEN_F2_P_2  (VEX_LEN_F1_P_2 + 1)
1166 #define VEX_LEN_F3_P_2  (VEX_LEN_F2_P_2 + 1)
1167 #define VEX_LEN_F4_P_2  (VEX_LEN_F3_P_2 + 1)
1168 #define VEX_LEN_F5_P_2  (VEX_LEN_F4_P_2 + 1)
1169 #define VEX_LEN_F6_P_2  (VEX_LEN_F5_P_2 + 1)
1170 #define VEX_LEN_F7_P_2  (VEX_LEN_F6_P_2 + 1)
1171 #define VEX_LEN_F8_P_2  (VEX_LEN_F7_P_2 + 1)
1172 #define VEX_LEN_F9_P_2  (VEX_LEN_F8_P_2 + 1)
1173 #define VEX_LEN_FA_P_2  (VEX_LEN_F9_P_2 + 1)
1174 #define VEX_LEN_FB_P_2  (VEX_LEN_FA_P_2 + 1)
1175 #define VEX_LEN_FC_P_2  (VEX_LEN_FB_P_2 + 1)
1176 #define VEX_LEN_FD_P_2  (VEX_LEN_FC_P_2 + 1)
1177 #define VEX_LEN_FE_P_2  (VEX_LEN_FD_P_2 + 1)
1178 #define VEX_LEN_3800_P_2        (VEX_LEN_FE_P_2 + 1)
1179 #define VEX_LEN_3801_P_2        (VEX_LEN_3800_P_2 + 1)
1180 #define VEX_LEN_3802_P_2        (VEX_LEN_3801_P_2 + 1)
1181 #define VEX_LEN_3803_P_2        (VEX_LEN_3802_P_2 + 1)
1182 #define VEX_LEN_3804_P_2        (VEX_LEN_3803_P_2 + 1)
1183 #define VEX_LEN_3805_P_2        (VEX_LEN_3804_P_2 + 1)
1184 #define VEX_LEN_3806_P_2        (VEX_LEN_3805_P_2 + 1)
1185 #define VEX_LEN_3807_P_2        (VEX_LEN_3806_P_2 + 1)
1186 #define VEX_LEN_3808_P_2        (VEX_LEN_3807_P_2 + 1)
1187 #define VEX_LEN_3809_P_2        (VEX_LEN_3808_P_2 + 1)
1188 #define VEX_LEN_380A_P_2        (VEX_LEN_3809_P_2 + 1)
1189 #define VEX_LEN_380B_P_2        (VEX_LEN_380A_P_2 + 1)
1190 #define VEX_LEN_3819_P_2_M_0    (VEX_LEN_380B_P_2 + 1)
1191 #define VEX_LEN_381A_P_2_M_0    (VEX_LEN_3819_P_2_M_0 + 1)
1192 #define VEX_LEN_381C_P_2        (VEX_LEN_381A_P_2_M_0 + 1)
1193 #define VEX_LEN_381D_P_2        (VEX_LEN_381C_P_2 + 1)
1194 #define VEX_LEN_381E_P_2        (VEX_LEN_381D_P_2 + 1)
1195 #define VEX_LEN_3820_P_2        (VEX_LEN_381E_P_2 + 1)
1196 #define VEX_LEN_3821_P_2        (VEX_LEN_3820_P_2 + 1)
1197 #define VEX_LEN_3822_P_2        (VEX_LEN_3821_P_2 + 1)
1198 #define VEX_LEN_3823_P_2        (VEX_LEN_3822_P_2 + 1)
1199 #define VEX_LEN_3824_P_2        (VEX_LEN_3823_P_2 + 1)
1200 #define VEX_LEN_3825_P_2        (VEX_LEN_3824_P_2 + 1)
1201 #define VEX_LEN_3828_P_2        (VEX_LEN_3825_P_2 + 1)
1202 #define VEX_LEN_3829_P_2        (VEX_LEN_3828_P_2 + 1)
1203 #define VEX_LEN_382A_P_2_M_0    (VEX_LEN_3829_P_2 + 1)
1204 #define VEX_LEN_382B_P_2        (VEX_LEN_382A_P_2_M_0 + 1)
1205 #define VEX_LEN_3830_P_2        (VEX_LEN_382B_P_2 + 1)
1206 #define VEX_LEN_3831_P_2        (VEX_LEN_3830_P_2 + 1)
1207 #define VEX_LEN_3832_P_2        (VEX_LEN_3831_P_2 + 1)
1208 #define VEX_LEN_3833_P_2        (VEX_LEN_3832_P_2 + 1)
1209 #define VEX_LEN_3834_P_2        (VEX_LEN_3833_P_2 + 1)
1210 #define VEX_LEN_3835_P_2        (VEX_LEN_3834_P_2 + 1)
1211 #define VEX_LEN_3837_P_2        (VEX_LEN_3835_P_2 + 1)
1212 #define VEX_LEN_3838_P_2        (VEX_LEN_3837_P_2 + 1)
1213 #define VEX_LEN_3839_P_2        (VEX_LEN_3838_P_2 + 1)
1214 #define VEX_LEN_383A_P_2        (VEX_LEN_3839_P_2 + 1)
1215 #define VEX_LEN_383B_P_2        (VEX_LEN_383A_P_2 + 1)
1216 #define VEX_LEN_383C_P_2        (VEX_LEN_383B_P_2 + 1)
1217 #define VEX_LEN_383D_P_2        (VEX_LEN_383C_P_2 + 1)
1218 #define VEX_LEN_383E_P_2        (VEX_LEN_383D_P_2 + 1)
1219 #define VEX_LEN_383F_P_2        (VEX_LEN_383E_P_2 + 1)
1220 #define VEX_LEN_3840_P_2        (VEX_LEN_383F_P_2 + 1)
1221 #define VEX_LEN_3841_P_2        (VEX_LEN_3840_P_2 + 1)
1222 #define VEX_LEN_38DB_P_2        (VEX_LEN_3841_P_2 + 1)
1223 #define VEX_LEN_38DC_P_2        (VEX_LEN_38DB_P_2 + 1)
1224 #define VEX_LEN_38DD_P_2        (VEX_LEN_38DC_P_2 + 1)
1225 #define VEX_LEN_38DE_P_2        (VEX_LEN_38DD_P_2 + 1)
1226 #define VEX_LEN_38DF_P_2        (VEX_LEN_38DE_P_2 + 1)
1227 #define VEX_LEN_3A06_P_2        (VEX_LEN_38DF_P_2 + 1)
1228 #define VEX_LEN_3A0A_P_2        (VEX_LEN_3A06_P_2 + 1)
1229 #define VEX_LEN_3A0B_P_2        (VEX_LEN_3A0A_P_2 + 1)
1230 #define VEX_LEN_3A0E_P_2        (VEX_LEN_3A0B_P_2 + 1)
1231 #define VEX_LEN_3A0F_P_2        (VEX_LEN_3A0E_P_2 + 1)
1232 #define VEX_LEN_3A14_P_2        (VEX_LEN_3A0F_P_2 + 1)
1233 #define VEX_LEN_3A15_P_2        (VEX_LEN_3A14_P_2 + 1)
1234 #define VEX_LEN_3A16_P_2        (VEX_LEN_3A15_P_2 + 1)
1235 #define VEX_LEN_3A17_P_2        (VEX_LEN_3A16_P_2 + 1)
1236 #define VEX_LEN_3A18_P_2        (VEX_LEN_3A17_P_2 + 1)
1237 #define VEX_LEN_3A19_P_2        (VEX_LEN_3A18_P_2 + 1)
1238 #define VEX_LEN_3A20_P_2        (VEX_LEN_3A19_P_2 + 1)
1239 #define VEX_LEN_3A21_P_2        (VEX_LEN_3A20_P_2 + 1)
1240 #define VEX_LEN_3A22_P_2        (VEX_LEN_3A21_P_2 + 1)
1241 #define VEX_LEN_3A41_P_2        (VEX_LEN_3A22_P_2 + 1)
1242 #define VEX_LEN_3A42_P_2        (VEX_LEN_3A41_P_2 + 1)
1243 #define VEX_LEN_3A44_P_2        (VEX_LEN_3A42_P_2 + 1)
1244 #define VEX_LEN_3A4C_P_2        (VEX_LEN_3A44_P_2 + 1)
1245 #define VEX_LEN_3A60_P_2        (VEX_LEN_3A4C_P_2 + 1)
1246 #define VEX_LEN_3A61_P_2        (VEX_LEN_3A60_P_2 + 1)
1247 #define VEX_LEN_3A62_P_2        (VEX_LEN_3A61_P_2 + 1)
1248 #define VEX_LEN_3A63_P_2        (VEX_LEN_3A62_P_2 + 1)
1249 #define VEX_LEN_3ADF_P_2        (VEX_LEN_3A63_P_2 + 1)
1250
1251 typedef void (*op_rtn) (int bytemode, int sizeflag);
1252
1253 struct dis386 {
1254   const char *name;
1255   struct
1256     {
1257       op_rtn rtn;
1258       int bytemode;
1259     } op[MAX_OPERANDS];
1260 };
1261
1262 /* Upper case letters in the instruction names here are macros.
1263    'A' => print 'b' if no register operands or suffix_always is true
1264    'B' => print 'b' if suffix_always is true
1265    'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
1266           size prefix
1267    'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
1268           suffix_always is true
1269    'E' => print 'e' if 32-bit form of jcxz
1270    'F' => print 'w' or 'l' depending on address size prefix (loop insns)
1271    'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
1272    'H' => print ",pt" or ",pn" branch hint
1273    'I' => honor following macro letter even in Intel mode (implemented only
1274           for some of the macro letters)
1275    'J' => print 'l'
1276    'K' => print 'd' or 'q' if rex prefix is present.
1277    'L' => print 'l' if suffix_always is true
1278    'M' => print 'r' if intel_mnemonic is false.
1279    'N' => print 'n' if instruction has no wait "prefix"
1280    'O' => print 'd' or 'o' (or 'q' in Intel mode)
1281    'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
1282           or suffix_always is true.  print 'q' if rex prefix is present.
1283    'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
1284           is true
1285    'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
1286    'S' => print 'w', 'l' or 'q' if suffix_always is true
1287    'T' => print 'q' in 64bit mode and behave as 'P' otherwise
1288    'U' => print 'q' in 64bit mode and behave as 'Q' otherwise
1289    'V' => print 'q' in 64bit mode and behave as 'S' otherwise
1290    'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
1291    'X' => print 's', 'd' depending on data16 prefix (for XMM)
1292    'Y' => 'q' if instruction has an REX 64bit overwrite prefix and
1293           suffix_always is true.
1294    'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
1295    '!' => change condition from true to false or from false to true.
1296    '%' => add 1 upper case letter to the macro.
1297
1298    2 upper case letter macros:
1299    "XY" => print 'x' or 'y' if no register operands or suffix_always
1300            is true.
1301    'XW' => print 's', 'd' depending on the VEX.W bit (for FMA)
1302    'LQ' => print 'l' ('d' in Intel mode) or 'q' for memory operand
1303            or suffix_always is true
1304
1305    Many of the above letters print nothing in Intel mode.  See "putop"
1306    for the details.
1307
1308    Braces '{' and '}', and vertical bars '|', indicate alternative
1309    mnemonic strings for AT&T and Intel.  */
1310
1311 static const struct dis386 dis386[] = {
1312   /* 00 */
1313   { "addB",             { Eb, Gb } },
1314   { "addS",             { Ev, Gv } },
1315   { "addB",             { Gb, EbS } },
1316   { "addS",             { Gv, EvS } },
1317   { "addB",             { AL, Ib } },
1318   { "addS",             { eAX, Iv } },
1319   { X86_64_TABLE (X86_64_06) },
1320   { X86_64_TABLE (X86_64_07) },
1321   /* 08 */
1322   { "orB",              { Eb, Gb } },
1323   { "orS",              { Ev, Gv } },
1324   { "orB",              { Gb, EbS } },
1325   { "orS",              { Gv, EvS } },
1326   { "orB",              { AL, Ib } },
1327   { "orS",              { eAX, Iv } },
1328   { X86_64_TABLE (X86_64_0D) },
1329   { "(bad)",            { XX } },       /* 0x0f extended opcode escape */
1330   /* 10 */
1331   { "adcB",             { Eb, Gb } },
1332   { "adcS",             { Ev, Gv } },
1333   { "adcB",             { Gb, EbS } },
1334   { "adcS",             { Gv, EvS } },
1335   { "adcB",             { AL, Ib } },
1336   { "adcS",             { eAX, Iv } },
1337   { X86_64_TABLE (X86_64_16) },
1338   { X86_64_TABLE (X86_64_17) },
1339   /* 18 */
1340   { "sbbB",             { Eb, Gb } },
1341   { "sbbS",             { Ev, Gv } },
1342   { "sbbB",             { Gb, EbS } },
1343   { "sbbS",             { Gv, EvS } },
1344   { "sbbB",             { AL, Ib } },
1345   { "sbbS",             { eAX, Iv } },
1346   { X86_64_TABLE (X86_64_1E) },
1347   { X86_64_TABLE (X86_64_1F) },
1348   /* 20 */
1349   { "andB",             { Eb, Gb } },
1350   { "andS",             { Ev, Gv } },
1351   { "andB",             { Gb, EbS } },
1352   { "andS",             { Gv, EvS } },
1353   { "andB",             { AL, Ib } },
1354   { "andS",             { eAX, Iv } },
1355   { "(bad)",            { XX } },       /* SEG ES prefix */
1356   { X86_64_TABLE (X86_64_27) },
1357   /* 28 */
1358   { "subB",             { Eb, Gb } },
1359   { "subS",             { Ev, Gv } },
1360   { "subB",             { Gb, EbS } },
1361   { "subS",             { Gv, EvS } },
1362   { "subB",             { AL, Ib } },
1363   { "subS",             { eAX, Iv } },
1364   { "(bad)",            { XX } },       /* SEG CS prefix */
1365   { X86_64_TABLE (X86_64_2F) },
1366   /* 30 */
1367   { "xorB",             { Eb, Gb } },
1368   { "xorS",             { Ev, Gv } },
1369   { "xorB",             { Gb, EbS } },
1370   { "xorS",             { Gv, EvS } },
1371   { "xorB",             { AL, Ib } },
1372   { "xorS",             { eAX, Iv } },
1373   { "(bad)",            { XX } },       /* SEG SS prefix */
1374   { X86_64_TABLE (X86_64_37) },
1375   /* 38 */
1376   { "cmpB",             { Eb, Gb } },
1377   { "cmpS",             { Ev, Gv } },
1378   { "cmpB",             { Gb, EbS } },
1379   { "cmpS",             { Gv, EvS } },
1380   { "cmpB",             { AL, Ib } },
1381   { "cmpS",             { eAX, Iv } },
1382   { "(bad)",            { XX } },       /* SEG DS prefix */
1383   { X86_64_TABLE (X86_64_3F) },
1384   /* 40 */
1385   { "inc{S|}",          { RMeAX } },
1386   { "inc{S|}",          { RMeCX } },
1387   { "inc{S|}",          { RMeDX } },
1388   { "inc{S|}",          { RMeBX } },
1389   { "inc{S|}",          { RMeSP } },
1390   { "inc{S|}",          { RMeBP } },
1391   { "inc{S|}",          { RMeSI } },
1392   { "inc{S|}",          { RMeDI } },
1393   /* 48 */
1394   { "dec{S|}",          { RMeAX } },
1395   { "dec{S|}",          { RMeCX } },
1396   { "dec{S|}",          { RMeDX } },
1397   { "dec{S|}",          { RMeBX } },
1398   { "dec{S|}",          { RMeSP } },
1399   { "dec{S|}",          { RMeBP } },
1400   { "dec{S|}",          { RMeSI } },
1401   { "dec{S|}",          { RMeDI } },
1402   /* 50 */
1403   { "pushV",            { RMrAX } },
1404   { "pushV",            { RMrCX } },
1405   { "pushV",            { RMrDX } },
1406   { "pushV",            { RMrBX } },
1407   { "pushV",            { RMrSP } },
1408   { "pushV",            { RMrBP } },
1409   { "pushV",            { RMrSI } },
1410   { "pushV",            { RMrDI } },
1411   /* 58 */
1412   { "popV",             { RMrAX } },
1413   { "popV",             { RMrCX } },
1414   { "popV",             { RMrDX } },
1415   { "popV",             { RMrBX } },
1416   { "popV",             { RMrSP } },
1417   { "popV",             { RMrBP } },
1418   { "popV",             { RMrSI } },
1419   { "popV",             { RMrDI } },
1420   /* 60 */
1421   { X86_64_TABLE (X86_64_60) },
1422   { X86_64_TABLE (X86_64_61) },
1423   { X86_64_TABLE (X86_64_62) },
1424   { X86_64_TABLE (X86_64_63) },
1425   { "(bad)",            { XX } },       /* seg fs */
1426   { "(bad)",            { XX } },       /* seg gs */
1427   { "(bad)",            { XX } },       /* op size prefix */
1428   { "(bad)",            { XX } },       /* adr size prefix */
1429   /* 68 */
1430   { "pushT",            { Iq } },
1431   { "imulS",            { Gv, Ev, Iv } },
1432   { "pushT",            { sIb } },
1433   { "imulS",            { Gv, Ev, sIb } },
1434   { "ins{b|}",          { Ybr, indirDX } },
1435   { X86_64_TABLE (X86_64_6D) },
1436   { "outs{b|}",         { indirDXr, Xb } },
1437   { X86_64_TABLE (X86_64_6F) },
1438   /* 70 */
1439   { "joH",              { Jb, XX, cond_jump_flag } },
1440   { "jnoH",             { Jb, XX, cond_jump_flag } },
1441   { "jbH",              { Jb, XX, cond_jump_flag } },
1442   { "jaeH",             { Jb, XX, cond_jump_flag } },
1443   { "jeH",              { Jb, XX, cond_jump_flag } },
1444   { "jneH",             { Jb, XX, cond_jump_flag } },
1445   { "jbeH",             { Jb, XX, cond_jump_flag } },
1446   { "jaH",              { Jb, XX, cond_jump_flag } },
1447   /* 78 */
1448   { "jsH",              { Jb, XX, cond_jump_flag } },
1449   { "jnsH",             { Jb, XX, cond_jump_flag } },
1450   { "jpH",              { Jb, XX, cond_jump_flag } },
1451   { "jnpH",             { Jb, XX, cond_jump_flag } },
1452   { "jlH",              { Jb, XX, cond_jump_flag } },
1453   { "jgeH",             { Jb, XX, cond_jump_flag } },
1454   { "jleH",             { Jb, XX, cond_jump_flag } },
1455   { "jgH",              { Jb, XX, cond_jump_flag } },
1456   /* 80 */
1457   { REG_TABLE (REG_80) },
1458   { REG_TABLE (REG_81) },
1459   { "(bad)",            { XX } },
1460   { REG_TABLE (REG_82) },
1461   { "testB",            { Eb, Gb } },
1462   { "testS",            { Ev, Gv } },
1463   { "xchgB",            { Eb, Gb } },
1464   { "xchgS",            { Ev, Gv } },
1465   /* 88 */
1466   { "movB",             { Eb, Gb } },
1467   { "movS",             { Ev, Gv } },
1468   { "movB",             { Gb, EbS } },
1469   { "movS",             { Gv, EvS } },
1470   { "movD",             { Sv, Sw } },
1471   { MOD_TABLE (MOD_8D) },
1472   { "movD",             { Sw, Sv } },
1473   { REG_TABLE (REG_8F) },
1474   /* 90 */
1475   { PREFIX_TABLE (PREFIX_90) },
1476   { "xchgS",            { RMeCX, eAX } },
1477   { "xchgS",            { RMeDX, eAX } },
1478   { "xchgS",            { RMeBX, eAX } },
1479   { "xchgS",            { RMeSP, eAX } },
1480   { "xchgS",            { RMeBP, eAX } },
1481   { "xchgS",            { RMeSI, eAX } },
1482   { "xchgS",            { RMeDI, eAX } },
1483   /* 98 */
1484   { "cW{t|}R",          { XX } },
1485   { "cR{t|}O",          { XX } },
1486   { X86_64_TABLE (X86_64_9A) },
1487   { "(bad)",            { XX } },       /* fwait */
1488   { "pushfT",           { XX } },
1489   { "popfT",            { XX } },
1490   { "sahf",             { XX } },
1491   { "lahf",             { XX } },
1492   /* a0 */
1493   { "movB",             { AL, Ob } },
1494   { "movS",             { eAX, Ov } },
1495   { "movB",             { Ob, AL } },
1496   { "movS",             { Ov, eAX } },
1497   { "movs{b|}",         { Ybr, Xb } },
1498   { "movs{R|}",         { Yvr, Xv } },
1499   { "cmps{b|}",         { Xb, Yb } },
1500   { "cmps{R|}",         { Xv, Yv } },
1501   /* a8 */
1502   { "testB",            { AL, Ib } },
1503   { "testS",            { eAX, Iv } },
1504   { "stosB",            { Ybr, AL } },
1505   { "stosS",            { Yvr, eAX } },
1506   { "lodsB",            { ALr, Xb } },
1507   { "lodsS",            { eAXr, Xv } },
1508   { "scasB",            { AL, Yb } },
1509   { "scasS",            { eAX, Yv } },
1510   /* b0 */
1511   { "movB",             { RMAL, Ib } },
1512   { "movB",             { RMCL, Ib } },
1513   { "movB",             { RMDL, Ib } },
1514   { "movB",             { RMBL, Ib } },
1515   { "movB",             { RMAH, Ib } },
1516   { "movB",             { RMCH, Ib } },
1517   { "movB",             { RMDH, Ib } },
1518   { "movB",             { RMBH, Ib } },
1519   /* b8 */
1520   { "movS",             { RMeAX, Iv64 } },
1521   { "movS",             { RMeCX, Iv64 } },
1522   { "movS",             { RMeDX, Iv64 } },
1523   { "movS",             { RMeBX, Iv64 } },
1524   { "movS",             { RMeSP, Iv64 } },
1525   { "movS",             { RMeBP, Iv64 } },
1526   { "movS",             { RMeSI, Iv64 } },
1527   { "movS",             { RMeDI, Iv64 } },
1528   /* c0 */
1529   { REG_TABLE (REG_C0) },
1530   { REG_TABLE (REG_C1) },
1531   { "retT",             { Iw } },
1532   { "retT",             { XX } },
1533   { X86_64_TABLE (X86_64_C4) },
1534   { X86_64_TABLE (X86_64_C5) },
1535   { REG_TABLE (REG_C6) },
1536   { REG_TABLE (REG_C7) },
1537   /* c8 */
1538   { "enterT",           { Iw, Ib } },
1539   { "leaveT",           { XX } },
1540   { "Jret{|f}P",        { Iw } },
1541   { "Jret{|f}P",        { XX } },
1542   { "int3",             { XX } },
1543   { "int",              { Ib } },
1544   { X86_64_TABLE (X86_64_CE) },
1545   { "iretP",            { XX } },
1546   /* d0 */
1547   { REG_TABLE (REG_D0) },
1548   { REG_TABLE (REG_D1) },
1549   { REG_TABLE (REG_D2) },
1550   { REG_TABLE (REG_D3) },
1551   { X86_64_TABLE (X86_64_D4) },
1552   { X86_64_TABLE (X86_64_D5) },
1553   { "(bad)",            { XX } },
1554   { "xlat",             { DSBX } },
1555   /* d8 */
1556   { FLOAT },
1557   { FLOAT },
1558   { FLOAT },
1559   { FLOAT },
1560   { FLOAT },
1561   { FLOAT },
1562   { FLOAT },
1563   { FLOAT },
1564   /* e0 */
1565   { "loopneFH",         { Jb, XX, loop_jcxz_flag } },
1566   { "loopeFH",          { Jb, XX, loop_jcxz_flag } },
1567   { "loopFH",           { Jb, XX, loop_jcxz_flag } },
1568   { "jEcxzH",           { Jb, XX, loop_jcxz_flag } },
1569   { "inB",              { AL, Ib } },
1570   { "inG",              { zAX, Ib } },
1571   { "outB",             { Ib, AL } },
1572   { "outG",             { Ib, zAX } },
1573   /* e8 */
1574   { "callT",            { Jv } },
1575   { "jmpT",             { Jv } },
1576   { X86_64_TABLE (X86_64_EA) },
1577   { "jmp",              { Jb } },
1578   { "inB",              { AL, indirDX } },
1579   { "inG",              { zAX, indirDX } },
1580   { "outB",             { indirDX, AL } },
1581   { "outG",             { indirDX, zAX } },
1582   /* f0 */
1583   { "(bad)",            { XX } },       /* lock prefix */
1584   { "icebp",            { XX } },
1585   { "(bad)",            { XX } },       /* repne */
1586   { "(bad)",            { XX } },       /* repz */
1587   { "hlt",              { XX } },
1588   { "cmc",              { XX } },
1589   { REG_TABLE (REG_F6) },
1590   { REG_TABLE (REG_F7) },
1591   /* f8 */
1592   { "clc",              { XX } },
1593   { "stc",              { XX } },
1594   { "cli",              { XX } },
1595   { "sti",              { XX } },
1596   { "cld",              { XX } },
1597   { "std",              { XX } },
1598   { REG_TABLE (REG_FE) },
1599   { REG_TABLE (REG_FF) },
1600 };
1601
1602 static const struct dis386 dis386_twobyte[] = {
1603   /* 00 */
1604   { REG_TABLE (REG_0F00 ) },
1605   { REG_TABLE (REG_0F01 ) },
1606   { "larS",             { Gv, Ew } },
1607   { "lslS",             { Gv, Ew } },
1608   { "(bad)",            { XX } },
1609   { "syscall",          { XX } },
1610   { "clts",             { XX } },
1611   { "sysretP",          { XX } },
1612   /* 08 */
1613   { "invd",             { XX } },
1614   { "wbinvd",           { XX } },
1615   { "(bad)",            { XX } },
1616   { "ud2a",             { XX } },
1617   { "(bad)",            { XX } },
1618   { REG_TABLE (REG_0F0D) },
1619   { "femms",            { XX } },
1620   { "",                 { MX, EM, OPSUF } }, /* See OP_3DNowSuffix.  */
1621   /* 10 */
1622   { PREFIX_TABLE (PREFIX_0F10) },
1623   { PREFIX_TABLE (PREFIX_0F11) },
1624   { PREFIX_TABLE (PREFIX_0F12) },
1625   { MOD_TABLE (MOD_0F13) },
1626   { "unpcklpX",         { XM, EXx } },
1627   { "unpckhpX",         { XM, EXx } },
1628   { PREFIX_TABLE (PREFIX_0F16) },
1629   { MOD_TABLE (MOD_0F17) },
1630   /* 18 */
1631   { REG_TABLE (REG_0F18) },
1632   { "nopQ",             { Ev } },
1633   { "nopQ",             { Ev } },
1634   { "nopQ",             { Ev } },
1635   { "nopQ",             { Ev } },
1636   { "nopQ",             { Ev } },
1637   { "nopQ",             { Ev } },
1638   { "nopQ",             { Ev } },
1639   /* 20 */
1640   { MOD_TABLE (MOD_0F20) },
1641   { MOD_TABLE (MOD_0F21) },
1642   { MOD_TABLE (MOD_0F22) },
1643   { MOD_TABLE (MOD_0F23) },
1644   { MOD_TABLE (MOD_0F24) },
1645   { THREE_BYTE_TABLE (THREE_BYTE_0F25) },
1646   { MOD_TABLE (MOD_0F26) },
1647   { "(bad)",            { XX } },
1648   /* 28 */
1649   { "movapX",           { XM, EXx } },
1650   { "movapX",           { EXxS, XM } },
1651   { PREFIX_TABLE (PREFIX_0F2A) },
1652   { PREFIX_TABLE (PREFIX_0F2B) },
1653   { PREFIX_TABLE (PREFIX_0F2C) },
1654   { PREFIX_TABLE (PREFIX_0F2D) },
1655   { PREFIX_TABLE (PREFIX_0F2E) },
1656   { PREFIX_TABLE (PREFIX_0F2F) },
1657   /* 30 */
1658   { "wrmsr",            { XX } },
1659   { "rdtsc",            { XX } },
1660   { "rdmsr",            { XX } },
1661   { "rdpmc",            { XX } },
1662   { "sysenter",         { XX } },
1663   { "sysexit",          { XX } },
1664   { "(bad)",            { XX } },
1665   { "getsec",           { XX } },
1666   /* 38 */
1667   { THREE_BYTE_TABLE (THREE_BYTE_0F38) },
1668   { "(bad)",            { XX } },
1669   { THREE_BYTE_TABLE (THREE_BYTE_0F3A) },
1670   { "(bad)",            { XX } },
1671   { "(bad)",            { XX } },
1672   { "(bad)",            { XX } },
1673   { "(bad)",            { XX } },
1674   { "(bad)",            { XX } },
1675   /* 40 */
1676   { "cmovoS",           { Gv, Ev } },
1677   { "cmovnoS",          { Gv, Ev } },
1678   { "cmovbS",           { Gv, Ev } },
1679   { "cmovaeS",          { Gv, Ev } },
1680   { "cmoveS",           { Gv, Ev } },
1681   { "cmovneS",          { Gv, Ev } },
1682   { "cmovbeS",          { Gv, Ev } },
1683   { "cmovaS",           { Gv, Ev } },
1684   /* 48 */
1685   { "cmovsS",           { Gv, Ev } },
1686   { "cmovnsS",          { Gv, Ev } },
1687   { "cmovpS",           { Gv, Ev } },
1688   { "cmovnpS",          { Gv, Ev } },
1689   { "cmovlS",           { Gv, Ev } },
1690   { "cmovgeS",          { Gv, Ev } },
1691   { "cmovleS",          { Gv, Ev } },
1692   { "cmovgS",           { Gv, Ev } },
1693   /* 50 */
1694   { MOD_TABLE (MOD_0F51) },
1695   { PREFIX_TABLE (PREFIX_0F51) },
1696   { PREFIX_TABLE (PREFIX_0F52) },
1697   { PREFIX_TABLE (PREFIX_0F53) },
1698   { "andpX",            { XM, EXx } },
1699   { "andnpX",           { XM, EXx } },
1700   { "orpX",             { XM, EXx } },
1701   { "xorpX",            { XM, EXx } },
1702   /* 58 */
1703   { PREFIX_TABLE (PREFIX_0F58) },
1704   { PREFIX_TABLE (PREFIX_0F59) },
1705   { PREFIX_TABLE (PREFIX_0F5A) },
1706   { PREFIX_TABLE (PREFIX_0F5B) },
1707   { PREFIX_TABLE (PREFIX_0F5C) },
1708   { PREFIX_TABLE (PREFIX_0F5D) },
1709   { PREFIX_TABLE (PREFIX_0F5E) },
1710   { PREFIX_TABLE (PREFIX_0F5F) },
1711   /* 60 */
1712   { PREFIX_TABLE (PREFIX_0F60) },
1713   { PREFIX_TABLE (PREFIX_0F61) },
1714   { PREFIX_TABLE (PREFIX_0F62) },
1715   { "packsswb",         { MX, EM } },
1716   { "pcmpgtb",          { MX, EM } },
1717   { "pcmpgtw",          { MX, EM } },
1718   { "pcmpgtd",          { MX, EM } },
1719   { "packuswb",         { MX, EM } },
1720   /* 68 */
1721   { "punpckhbw",        { MX, EM } },
1722   { "punpckhwd",        { MX, EM } },
1723   { "punpckhdq",        { MX, EM } },
1724   { "packssdw",         { MX, EM } },
1725   { PREFIX_TABLE (PREFIX_0F6C) },
1726   { PREFIX_TABLE (PREFIX_0F6D) },
1727   { "movK",             { MX, Edq } },
1728   { PREFIX_TABLE (PREFIX_0F6F) },
1729   /* 70 */
1730   { PREFIX_TABLE (PREFIX_0F70) },
1731   { REG_TABLE (REG_0F71) },
1732   { REG_TABLE (REG_0F72) },
1733   { REG_TABLE (REG_0F73) },
1734   { "pcmpeqb",          { MX, EM } },
1735   { "pcmpeqw",          { MX, EM } },
1736   { "pcmpeqd",          { MX, EM } },
1737   { "emms",             { XX } },
1738   /* 78 */
1739   { PREFIX_TABLE (PREFIX_0F78) },
1740   { PREFIX_TABLE (PREFIX_0F79) },
1741   { THREE_BYTE_TABLE (THREE_BYTE_0F7A) },
1742   { THREE_BYTE_TABLE (THREE_BYTE_0F7B) },
1743   { PREFIX_TABLE (PREFIX_0F7C) },
1744   { PREFIX_TABLE (PREFIX_0F7D) },
1745   { PREFIX_TABLE (PREFIX_0F7E) },
1746   { PREFIX_TABLE (PREFIX_0F7F) },
1747   /* 80 */
1748   { "joH",              { Jv, XX, cond_jump_flag } },
1749   { "jnoH",             { Jv, XX, cond_jump_flag } },
1750   { "jbH",              { Jv, XX, cond_jump_flag } },
1751   { "jaeH",             { Jv, XX, cond_jump_flag } },
1752   { "jeH",              { Jv, XX, cond_jump_flag } },
1753   { "jneH",             { Jv, XX, cond_jump_flag } },
1754   { "jbeH",             { Jv, XX, cond_jump_flag } },
1755   { "jaH",              { Jv, XX, cond_jump_flag } },
1756   /* 88 */
1757   { "jsH",              { Jv, XX, cond_jump_flag } },
1758   { "jnsH",             { Jv, XX, cond_jump_flag } },
1759   { "jpH",              { Jv, XX, cond_jump_flag } },
1760   { "jnpH",             { Jv, XX, cond_jump_flag } },
1761   { "jlH",              { Jv, XX, cond_jump_flag } },
1762   { "jgeH",             { Jv, XX, cond_jump_flag } },
1763   { "jleH",             { Jv, XX, cond_jump_flag } },
1764   { "jgH",              { Jv, XX, cond_jump_flag } },
1765   /* 90 */
1766   { "seto",             { Eb } },
1767   { "setno",            { Eb } },
1768   { "setb",             { Eb } },
1769   { "setae",            { Eb } },
1770   { "sete",             { Eb } },
1771   { "setne",            { Eb } },
1772   { "setbe",            { Eb } },
1773   { "seta",             { Eb } },
1774   /* 98 */
1775   { "sets",             { Eb } },
1776   { "setns",            { Eb } },
1777   { "setp",             { Eb } },
1778   { "setnp",            { Eb } },
1779   { "setl",             { Eb } },
1780   { "setge",            { Eb } },
1781   { "setle",            { Eb } },
1782   { "setg",             { Eb } },
1783   /* a0 */
1784   { "pushT",            { fs } },
1785   { "popT",             { fs } },
1786   { "cpuid",            { XX } },
1787   { "btS",              { Ev, Gv } },
1788   { "shldS",            { Ev, Gv, Ib } },
1789   { "shldS",            { Ev, Gv, CL } },
1790   { REG_TABLE (REG_0FA6) },
1791   { REG_TABLE (REG_0FA7) },
1792   /* a8 */
1793   { "pushT",            { gs } },
1794   { "popT",             { gs } },
1795   { "rsm",              { XX } },
1796   { "btsS",             { Ev, Gv } },
1797   { "shrdS",            { Ev, Gv, Ib } },
1798   { "shrdS",            { Ev, Gv, CL } },
1799   { REG_TABLE (REG_0FAE) },
1800   { "imulS",            { Gv, Ev } },
1801   /* b0 */
1802   { "cmpxchgB",         { Eb, Gb } },
1803   { "cmpxchgS",         { Ev, Gv } },
1804   { MOD_TABLE (MOD_0FB2) },
1805   { "btrS",             { Ev, Gv } },
1806   { MOD_TABLE (MOD_0FB4) },
1807   { MOD_TABLE (MOD_0FB5) },
1808   { "movz{bR|x}",       { Gv, Eb } },
1809   { "movz{wR|x}",       { Gv, Ew } }, /* yes, there really is movzww ! */
1810   /* b8 */
1811   { PREFIX_TABLE (PREFIX_0FB8) },
1812   { "ud2b",             { XX } },
1813   { REG_TABLE (REG_0FBA) },
1814   { "btcS",             { Ev, Gv } },
1815   { "bsfS",             { Gv, Ev } },
1816   { PREFIX_TABLE (PREFIX_0FBD) },
1817   { "movs{bR|x}",       { Gv, Eb } },
1818   { "movs{wR|x}",       { Gv, Ew } }, /* yes, there really is movsww ! */
1819   /* c0 */
1820   { "xaddB",            { Eb, Gb } },
1821   { "xaddS",            { Ev, Gv } },
1822   { PREFIX_TABLE (PREFIX_0FC2) },
1823   { PREFIX_TABLE (PREFIX_0FC3) },
1824   { "pinsrw",           { MX, Edqw, Ib } },
1825   { "pextrw",           { Gdq, MS, Ib } },
1826   { "shufpX",           { XM, EXx, Ib } },
1827   { REG_TABLE (REG_0FC7) },
1828   /* c8 */
1829   { "bswap",            { RMeAX } },
1830   { "bswap",            { RMeCX } },
1831   { "bswap",            { RMeDX } },
1832   { "bswap",            { RMeBX } },
1833   { "bswap",            { RMeSP } },
1834   { "bswap",            { RMeBP } },
1835   { "bswap",            { RMeSI } },
1836   { "bswap",            { RMeDI } },
1837   /* d0 */
1838   { PREFIX_TABLE (PREFIX_0FD0) },
1839   { "psrlw",            { MX, EM } },
1840   { "psrld",            { MX, EM } },
1841   { "psrlq",            { MX, EM } },
1842   { "paddq",            { MX, EM } },
1843   { "pmullw",           { MX, EM } },
1844   { PREFIX_TABLE (PREFIX_0FD6) },
1845   { MOD_TABLE (MOD_0FD7) },
1846   /* d8 */
1847   { "psubusb",          { MX, EM } },
1848   { "psubusw",          { MX, EM } },
1849   { "pminub",           { MX, EM } },
1850   { "pand",             { MX, EM } },
1851   { "paddusb",          { MX, EM } },
1852   { "paddusw",          { MX, EM } },
1853   { "pmaxub",           { MX, EM } },
1854   { "pandn",            { MX, EM } },
1855   /* e0 */
1856   { "pavgb",            { MX, EM } },
1857   { "psraw",            { MX, EM } },
1858   { "psrad",            { MX, EM } },
1859   { "pavgw",            { MX, EM } },
1860   { "pmulhuw",          { MX, EM } },
1861   { "pmulhw",           { MX, EM } },
1862   { PREFIX_TABLE (PREFIX_0FE6) },
1863   { PREFIX_TABLE (PREFIX_0FE7) },
1864   /* e8 */
1865   { "psubsb",           { MX, EM } },
1866   { "psubsw",           { MX, EM } },
1867   { "pminsw",           { MX, EM } },
1868   { "por",              { MX, EM } },
1869   { "paddsb",           { MX, EM } },
1870   { "paddsw",           { MX, EM } },
1871   { "pmaxsw",           { MX, EM } },
1872   { "pxor",             { MX, EM } },
1873   /* f0 */
1874   { PREFIX_TABLE (PREFIX_0FF0) },
1875   { "psllw",            { MX, EM } },
1876   { "pslld",            { MX, EM } },
1877   { "psllq",            { MX, EM } },
1878   { "pmuludq",          { MX, EM } },
1879   { "pmaddwd",          { MX, EM } },
1880   { "psadbw",           { MX, EM } },
1881   { PREFIX_TABLE (PREFIX_0FF7) },
1882   /* f8 */
1883   { "psubb",            { MX, EM } },
1884   { "psubw",            { MX, EM } },
1885   { "psubd",            { MX, EM } },
1886   { "psubq",            { MX, EM } },
1887   { "paddb",            { MX, EM } },
1888   { "paddw",            { MX, EM } },
1889   { "paddd",            { MX, EM } },
1890   { "(bad)",            { XX } },
1891 };
1892
1893 static const unsigned char onebyte_has_modrm[256] = {
1894   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
1895   /*       -------------------------------        */
1896   /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
1897   /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
1898   /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
1899   /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
1900   /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
1901   /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
1902   /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
1903   /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
1904   /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
1905   /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
1906   /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
1907   /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
1908   /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
1909   /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
1910   /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
1911   /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1  /* f0 */
1912   /*       -------------------------------        */
1913   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
1914 };
1915
1916 static const unsigned char twobyte_has_modrm[256] = {
1917   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
1918   /*       -------------------------------        */
1919   /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
1920   /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
1921   /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
1922   /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
1923   /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
1924   /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
1925   /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
1926   /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
1927   /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
1928   /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
1929   /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
1930   /* b0 */ 1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1, /* bf */
1931   /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
1932   /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
1933   /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
1934   /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0  /* ff */
1935   /*       -------------------------------        */
1936   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
1937 };
1938
1939 static char obuf[100];
1940 static char *obufp;
1941 static char *mnemonicendp;
1942 static char scratchbuf[100];
1943 static unsigned char *start_codep;
1944 static unsigned char *insn_codep;
1945 static unsigned char *codep;
1946 static const char *lock_prefix;
1947 static const char *data_prefix;
1948 static const char *addr_prefix;
1949 static const char *repz_prefix;
1950 static const char *repnz_prefix;
1951 static disassemble_info *the_info;
1952 static struct
1953   {
1954     int mod;
1955     int reg;
1956     int rm;
1957   }
1958 modrm;
1959 static unsigned char need_modrm;
1960 static struct
1961   {
1962     int register_specifier;
1963     int length;
1964     int prefix;
1965     int w;
1966   }
1967 vex;
1968 static unsigned char need_vex;
1969 static unsigned char need_vex_reg;
1970 static unsigned char vex_w_done;
1971
1972 struct op
1973   {
1974     const char *name;
1975     unsigned int len;
1976   };
1977
1978 /* If we are accessing mod/rm/reg without need_modrm set, then the
1979    values are stale.  Hitting this abort likely indicates that you
1980    need to update onebyte_has_modrm or twobyte_has_modrm.  */
1981 #define MODRM_CHECK  if (!need_modrm) abort ()
1982
1983 static const char **names64;
1984 static const char **names32;
1985 static const char **names16;
1986 static const char **names8;
1987 static const char **names8rex;
1988 static const char **names_seg;
1989 static const char *index64;
1990 static const char *index32;
1991 static const char **index16;
1992
1993 static const char *intel_names64[] = {
1994   "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
1995   "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
1996 };
1997 static const char *intel_names32[] = {
1998   "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
1999   "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
2000 };
2001 static const char *intel_names16[] = {
2002   "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
2003   "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
2004 };
2005 static const char *intel_names8[] = {
2006   "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
2007 };
2008 static const char *intel_names8rex[] = {
2009   "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
2010   "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
2011 };
2012 static const char *intel_names_seg[] = {
2013   "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
2014 };
2015 static const char *intel_index64 = "riz";
2016 static const char *intel_index32 = "eiz";
2017 static const char *intel_index16[] = {
2018   "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
2019 };
2020
2021 static const char *att_names64[] = {
2022   "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
2023   "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
2024 };
2025 static const char *att_names32[] = {
2026   "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
2027   "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
2028 };
2029 static const char *att_names16[] = {
2030   "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
2031   "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
2032 };
2033 static const char *att_names8[] = {
2034   "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
2035 };
2036 static const char *att_names8rex[] = {
2037   "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
2038   "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
2039 };
2040 static const char *att_names_seg[] = {
2041   "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
2042 };
2043 static const char *att_index64 = "%riz";
2044 static const char *att_index32 = "%eiz";
2045 static const char *att_index16[] = {
2046   "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
2047 };
2048
2049 static const struct dis386 reg_table[][8] = {
2050   /* REG_80 */
2051   {
2052     { "addA",   { Eb, Ib } },
2053     { "orA",    { Eb, Ib } },
2054     { "adcA",   { Eb, Ib } },
2055     { "sbbA",   { Eb, Ib } },
2056     { "andA",   { Eb, Ib } },
2057     { "subA",   { Eb, Ib } },
2058     { "xorA",   { Eb, Ib } },
2059     { "cmpA",   { Eb, Ib } },
2060   },
2061   /* REG_81 */
2062   {
2063     { "addQ",   { Ev, Iv } },
2064     { "orQ",    { Ev, Iv } },
2065     { "adcQ",   { Ev, Iv } },
2066     { "sbbQ",   { Ev, Iv } },
2067     { "andQ",   { Ev, Iv } },
2068     { "subQ",   { Ev, Iv } },
2069     { "xorQ",   { Ev, Iv } },
2070     { "cmpQ",   { Ev, Iv } },
2071   },
2072   /* REG_82 */
2073   {
2074     { "addQ",   { Ev, sIb } },
2075     { "orQ",    { Ev, sIb } },
2076     { "adcQ",   { Ev, sIb } },
2077     { "sbbQ",   { Ev, sIb } },
2078     { "andQ",   { Ev, sIb } },
2079     { "subQ",   { Ev, sIb } },
2080     { "xorQ",   { Ev, sIb } },
2081     { "cmpQ",   { Ev, sIb } },
2082   },
2083   /* REG_8F */
2084   {
2085     { "popU",   { stackEv } },
2086     { "(bad)",  { XX } },
2087     { "(bad)",  { XX } },
2088     { "(bad)",  { XX } },
2089     { "(bad)",  { XX } },
2090     { "(bad)",  { XX } },
2091     { "(bad)",  { XX } },
2092     { "(bad)",  { XX } },
2093   },
2094   /* REG_C0 */
2095   {
2096     { "rolA",   { Eb, Ib } },
2097     { "rorA",   { Eb, Ib } },
2098     { "rclA",   { Eb, Ib } },
2099     { "rcrA",   { Eb, Ib } },
2100     { "shlA",   { Eb, Ib } },
2101     { "shrA",   { Eb, Ib } },
2102     { "(bad)",  { XX } },
2103     { "sarA",   { Eb, Ib } },
2104   },
2105   /* REG_C1 */
2106   {
2107     { "rolQ",   { Ev, Ib } },
2108     { "rorQ",   { Ev, Ib } },
2109     { "rclQ",   { Ev, Ib } },
2110     { "rcrQ",   { Ev, Ib } },
2111     { "shlQ",   { Ev, Ib } },
2112     { "shrQ",   { Ev, Ib } },
2113     { "(bad)",  { XX } },
2114     { "sarQ",   { Ev, Ib } },
2115   },
2116   /* REG_C6 */
2117   {
2118     { "movA",   { Eb, Ib } },
2119     { "(bad)",  { XX } },
2120     { "(bad)",  { XX } },
2121     { "(bad)",  { XX } },
2122     { "(bad)",  { XX } },
2123     { "(bad)",  { XX } },
2124     { "(bad)",  { XX } },
2125     { "(bad)",  { XX } },
2126   },
2127   /* REG_C7 */
2128   {
2129     { "movQ",   { Ev, Iv } },
2130     { "(bad)",  { XX } },
2131     { "(bad)",  { XX } },
2132     { "(bad)",  { XX } },
2133     { "(bad)",  { XX } },
2134     { "(bad)",  { XX } },
2135     { "(bad)",  { XX } },
2136     { "(bad)",  { XX } },
2137   },
2138   /* REG_D0 */
2139   {
2140     { "rolA",   { Eb, I1 } },
2141     { "rorA",   { Eb, I1 } },
2142     { "rclA",   { Eb, I1 } },
2143     { "rcrA",   { Eb, I1 } },
2144     { "shlA",   { Eb, I1 } },
2145     { "shrA",   { Eb, I1 } },
2146     { "(bad)",  { XX } },
2147     { "sarA",   { Eb, I1 } },
2148   },
2149   /* REG_D1 */
2150   {
2151     { "rolQ",   { Ev, I1 } },
2152     { "rorQ",   { Ev, I1 } },
2153     { "rclQ",   { Ev, I1 } },
2154     { "rcrQ",   { Ev, I1 } },
2155     { "shlQ",   { Ev, I1 } },
2156     { "shrQ",   { Ev, I1 } },
2157     { "(bad)",  { XX } },
2158     { "sarQ",   { Ev, I1 } },
2159   },
2160   /* REG_D2 */
2161   {
2162     { "rolA",   { Eb, CL } },
2163     { "rorA",   { Eb, CL } },
2164     { "rclA",   { Eb, CL } },
2165     { "rcrA",   { Eb, CL } },
2166     { "shlA",   { Eb, CL } },
2167     { "shrA",   { Eb, CL } },
2168     { "(bad)",  { XX } },
2169     { "sarA",   { Eb, CL } },
2170   },
2171   /* REG_D3 */
2172   {
2173     { "rolQ",   { Ev, CL } },
2174     { "rorQ",   { Ev, CL } },
2175     { "rclQ",   { Ev, CL } },
2176     { "rcrQ",   { Ev, CL } },
2177     { "shlQ",   { Ev, CL } },
2178     { "shrQ",   { Ev, CL } },
2179     { "(bad)",  { XX } },
2180     { "sarQ",   { Ev, CL } },
2181   },
2182   /* REG_F6 */
2183   {
2184     { "testA",  { Eb, Ib } },
2185     { "(bad)",  { XX } },
2186     { "notA",   { Eb } },
2187     { "negA",   { Eb } },
2188     { "mulA",   { Eb } },       /* Don't print the implicit %al register,  */
2189     { "imulA",  { Eb } },       /* to distinguish these opcodes from other */
2190     { "divA",   { Eb } },       /* mul/imul opcodes.  Do the same for div  */
2191     { "idivA",  { Eb } },       /* and idiv for consistency.               */
2192   },
2193   /* REG_F7 */
2194   {
2195     { "testQ",  { Ev, Iv } },
2196     { "(bad)",  { XX } },
2197     { "notQ",   { Ev } },
2198     { "negQ",   { Ev } },
2199     { "mulQ",   { Ev } },       /* Don't print the implicit register.  */
2200     { "imulQ",  { Ev } },
2201     { "divQ",   { Ev } },
2202     { "idivQ",  { Ev } },
2203   },
2204   /* REG_FE */
2205   {
2206     { "incA",   { Eb } },
2207     { "decA",   { Eb } },
2208     { "(bad)",  { XX } },
2209     { "(bad)",  { XX } },
2210     { "(bad)",  { XX } },
2211     { "(bad)",  { XX } },
2212     { "(bad)",  { XX } },
2213     { "(bad)",  { XX } },
2214   },
2215   /* REG_FF */
2216   {
2217     { "incQ",   { Ev } },
2218     { "decQ",   { Ev } },
2219     { "callT",  { indirEv } },
2220     { "JcallT", { indirEp } },
2221     { "jmpT",   { indirEv } },
2222     { "JjmpT",  { indirEp } },
2223     { "pushU",  { stackEv } },
2224     { "(bad)",  { XX } },
2225   },
2226   /* REG_0F00 */
2227   {
2228     { "sldtD",  { Sv } },
2229     { "strD",   { Sv } },
2230     { "lldt",   { Ew } },
2231     { "ltr",    { Ew } },
2232     { "verr",   { Ew } },
2233     { "verw",   { Ew } },
2234     { "(bad)",  { XX } },
2235     { "(bad)",  { XX } },
2236   },
2237   /* REG_0F01 */
2238   {
2239     { MOD_TABLE (MOD_0F01_REG_0) },
2240     { MOD_TABLE (MOD_0F01_REG_1) },
2241     { MOD_TABLE (MOD_0F01_REG_2) },
2242     { MOD_TABLE (MOD_0F01_REG_3) },
2243     { "smswD",  { Sv } },
2244     { "(bad)",  { XX } },
2245     { "lmsw",   { Ew } },
2246     { MOD_TABLE (MOD_0F01_REG_7) },
2247   },
2248   /* REG_0F0D */
2249   {
2250     { "prefetch",       { Eb } },
2251     { "prefetchw",      { Eb } },
2252     { "(bad)",          { XX } },
2253     { "(bad)",          { XX } },
2254     { "(bad)",          { XX } },
2255     { "(bad)",          { XX } },
2256     { "(bad)",          { XX } },
2257     { "(bad)",          { XX } },
2258   },
2259   /* REG_0F18 */
2260   {
2261     { MOD_TABLE (MOD_0F18_REG_0) },
2262     { MOD_TABLE (MOD_0F18_REG_1) },
2263     { MOD_TABLE (MOD_0F18_REG_2) },
2264     { MOD_TABLE (MOD_0F18_REG_3) },
2265     { "(bad)",  { XX } },
2266     { "(bad)",  { XX } },
2267     { "(bad)",  { XX } },
2268     { "(bad)",  { XX } },
2269   },
2270   /* REG_0F71 */
2271   {
2272     { "(bad)",  { XX } },
2273     { "(bad)",  { XX } },
2274     { MOD_TABLE (MOD_0F71_REG_2) },
2275     { "(bad)",  { XX } },
2276     { MOD_TABLE (MOD_0F71_REG_4) },
2277     { "(bad)",  { XX } },
2278     { MOD_TABLE (MOD_0F71_REG_6) },
2279     { "(bad)",  { XX } },
2280   },
2281   /* REG_0F72 */
2282   {
2283     { "(bad)",  { XX } },
2284     { "(bad)",  { XX } },
2285     { MOD_TABLE (MOD_0F72_REG_2) },
2286     { "(bad)",  { XX } },
2287     { MOD_TABLE (MOD_0F72_REG_4) },
2288     { "(bad)",  { XX } },
2289     { MOD_TABLE (MOD_0F72_REG_6) },
2290     { "(bad)",  { XX } },
2291   },
2292   /* REG_0F73 */
2293   {
2294     { "(bad)",  { XX } },
2295     { "(bad)",  { XX } },
2296     { MOD_TABLE (MOD_0F73_REG_2) },
2297     { MOD_TABLE (MOD_0F73_REG_3) },
2298     { "(bad)",  { XX } },
2299     { "(bad)",  { XX } },
2300     { MOD_TABLE (MOD_0F73_REG_6) },
2301     { MOD_TABLE (MOD_0F73_REG_7) },
2302   },
2303   /* REG_0FA6 */
2304   {
2305     { "montmul",        { { OP_0f07, 0 } } },
2306     { "xsha1",          { { OP_0f07, 0 } } },
2307     { "xsha256",        { { OP_0f07, 0 } } },
2308     { "(bad)",          { { OP_0f07, 0 } } },
2309     { "(bad)",          { { OP_0f07, 0 } } },
2310     { "(bad)",          { { OP_0f07, 0 } } },
2311     { "(bad)",          { { OP_0f07, 0 } } },
2312     { "(bad)",          { { OP_0f07, 0 } } },
2313   },
2314   /* REG_0FA7 */
2315   {
2316     { "xstore-rng",     { { OP_0f07, 0 } } },
2317     { "xcrypt-ecb",     { { OP_0f07, 0 } } },
2318     { "xcrypt-cbc",     { { OP_0f07, 0 } } },
2319     { "xcrypt-ctr",     { { OP_0f07, 0 } } },
2320     { "xcrypt-cfb",     { { OP_0f07, 0 } } },
2321     { "xcrypt-ofb",     { { OP_0f07, 0 } } },
2322     { "(bad)",          { { OP_0f07, 0 } } },
2323     { "(bad)",          { { OP_0f07, 0 } } },
2324   },
2325   /* REG_0FAE */
2326   {
2327     { MOD_TABLE (MOD_0FAE_REG_0) },
2328     { MOD_TABLE (MOD_0FAE_REG_1) },
2329     { MOD_TABLE (MOD_0FAE_REG_2) },
2330     { MOD_TABLE (MOD_0FAE_REG_3) },
2331     { MOD_TABLE (MOD_0FAE_REG_4) },
2332     { MOD_TABLE (MOD_0FAE_REG_5) },
2333     { MOD_TABLE (MOD_0FAE_REG_6) },
2334     { MOD_TABLE (MOD_0FAE_REG_7) },
2335   },
2336   /* REG_0FBA */
2337   {
2338     { "(bad)",  { XX } },
2339     { "(bad)",  { XX } },
2340     { "(bad)",  { XX } },
2341     { "(bad)",  { XX } },
2342     { "btQ",    { Ev, Ib } },
2343     { "btsQ",   { Ev, Ib } },
2344     { "btrQ",   { Ev, Ib } },
2345     { "btcQ",   { Ev, Ib } },
2346   },
2347   /* REG_0FC7 */
2348   {
2349     { "(bad)",  { XX } },
2350     { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } } },
2351     { "(bad)",  { XX } },
2352     { "(bad)",  { XX } },
2353     { "(bad)",  { XX } },
2354     { "(bad)",  { XX } },
2355     { MOD_TABLE (MOD_0FC7_REG_6) },
2356     { MOD_TABLE (MOD_0FC7_REG_7) },
2357   },
2358   /* REG_VEX_71 */
2359   {
2360     { "(bad)",  { XX } },
2361     { "(bad)",  { XX } },
2362     { MOD_TABLE (MOD_VEX_71_REG_2) },
2363     { "(bad)",  { XX } },
2364     { MOD_TABLE (MOD_VEX_71_REG_4) },
2365     { "(bad)",  { XX } },
2366     { MOD_TABLE (MOD_VEX_71_REG_6) },
2367     { "(bad)",  { XX } },
2368   },
2369   /* REG_VEX_72 */
2370   {
2371     { "(bad)",  { XX } },
2372     { "(bad)",  { XX } },
2373     { MOD_TABLE (MOD_VEX_72_REG_2) },
2374     { "(bad)",  { XX } },
2375     { MOD_TABLE (MOD_VEX_72_REG_4) },
2376     { "(bad)",  { XX } },
2377     { MOD_TABLE (MOD_VEX_72_REG_6) },
2378     { "(bad)",  { XX } },
2379   },
2380   /* REG_VEX_73 */
2381   {
2382     { "(bad)",  { XX } },
2383     { "(bad)",  { XX } },
2384     { MOD_TABLE (MOD_VEX_73_REG_2) },
2385     { MOD_TABLE (MOD_VEX_73_REG_3) },
2386     { "(bad)",  { XX } },
2387     { "(bad)",  { XX } },
2388     { MOD_TABLE (MOD_VEX_73_REG_6) },
2389     { MOD_TABLE (MOD_VEX_73_REG_7) },
2390   },
2391   /* REG_VEX_AE */
2392   {
2393     { "(bad)",  { XX } },
2394     { "(bad)",  { XX } },
2395     { MOD_TABLE (MOD_VEX_AE_REG_2) },
2396     { MOD_TABLE (MOD_VEX_AE_REG_3) },
2397     { "(bad)",  { XX } },
2398     { "(bad)",  { XX } },
2399     { "(bad)",  { XX } },
2400     { "(bad)",  { XX } },
2401   },
2402 };
2403
2404 static const struct dis386 prefix_table[][4] = {
2405   /* PREFIX_90 */
2406   {
2407     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } } },
2408     { "pause", { XX } },
2409     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } } },
2410     { "(bad)", { XX } },
2411   },
2412
2413   /* PREFIX_0F10 */
2414   {
2415     { "movups", { XM, EXx } },
2416     { "movss",  { XM, EXd } },
2417     { "movupd", { XM, EXx } },
2418     { "movsd",  { XM, EXq } },
2419   },
2420
2421   /* PREFIX_0F11 */
2422   {
2423     { "movups", { EXxS, XM } },
2424     { "movss",  { EXdS, XM } },
2425     { "movupd", { EXxS, XM } },
2426     { "movsd",  { EXqS, XM } },
2427   },
2428
2429   /* PREFIX_0F12 */
2430   {
2431     { MOD_TABLE (MOD_0F12_PREFIX_0) },
2432     { "movsldup", { XM, EXx } },
2433     { "movlpd", { XM, EXq } },
2434     { "movddup", { XM, EXq } },
2435   },
2436
2437   /* PREFIX_0F16 */
2438   {
2439     { MOD_TABLE (MOD_0F16_PREFIX_0) },
2440     { "movshdup", { XM, EXx } },
2441     { "movhpd", { XM, EXq } },
2442     { "(bad)",  { XX } },
2443   },
2444
2445   /* PREFIX_0F2A */
2446   {
2447     { "cvtpi2ps", { XM, EMCq } },
2448     { "cvtsi2ss%LQ", { XM, Ev } },
2449     { "cvtpi2pd", { XM, EMCq } },
2450     { "cvtsi2sd%LQ", { XM, Ev } },
2451   },
2452
2453   /* PREFIX_0F2B */
2454   {
2455     { MOD_TABLE (MOD_0F2B_PREFIX_0) },
2456     { MOD_TABLE (MOD_0F2B_PREFIX_1) },
2457     { MOD_TABLE (MOD_0F2B_PREFIX_2) },
2458     { MOD_TABLE (MOD_0F2B_PREFIX_3) },
2459   },
2460
2461   /* PREFIX_0F2C */
2462   {
2463     { "cvttps2pi", { MXC, EXq } },
2464     { "cvttss2siY", { Gv, EXd } },
2465     { "cvttpd2pi", { MXC, EXx } },
2466     { "cvttsd2siY", { Gv, EXq } },
2467   },
2468
2469   /* PREFIX_0F2D */
2470   {
2471     { "cvtps2pi", { MXC, EXq } },
2472     { "cvtss2siY", { Gv, EXd } },
2473     { "cvtpd2pi", { MXC, EXx } },
2474     { "cvtsd2siY", { Gv, EXq } },
2475   },
2476
2477   /* PREFIX_0F2E */
2478   {
2479     { "ucomiss",{ XM, EXd } },
2480     { "(bad)",  { XX } },
2481     { "ucomisd",{ XM, EXq } },
2482     { "(bad)",  { XX } },
2483   },
2484
2485   /* PREFIX_0F2F */
2486   {
2487     { "comiss", { XM, EXd } },
2488     { "(bad)",  { XX } },
2489     { "comisd", { XM, EXq } },
2490     { "(bad)",  { XX } },
2491   },
2492
2493   /* PREFIX_0F51 */
2494   {
2495     { "sqrtps", { XM, EXx } },
2496     { "sqrtss", { XM, EXd } },
2497     { "sqrtpd", { XM, EXx } },
2498     { "sqrtsd", { XM, EXq } },
2499   },
2500
2501   /* PREFIX_0F52 */
2502   {
2503     { "rsqrtps",{ XM, EXx } },
2504     { "rsqrtss",{ XM, EXd } },
2505     { "(bad)",  { XX } },
2506     { "(bad)",  { XX } },
2507   },
2508
2509   /* PREFIX_0F53 */
2510   {
2511     { "rcpps",  { XM, EXx } },
2512     { "rcpss",  { XM, EXd } },
2513     { "(bad)",  { XX } },
2514     { "(bad)",  { XX } },
2515   },
2516
2517   /* PREFIX_0F58 */
2518   {
2519     { "addps", { XM, EXx } },
2520     { "addss", { XM, EXd } },
2521     { "addpd", { XM, EXx } },
2522     { "addsd", { XM, EXq } },
2523   },
2524
2525   /* PREFIX_0F59 */
2526   {
2527     { "mulps",  { XM, EXx } },
2528     { "mulss",  { XM, EXd } },
2529     { "mulpd",  { XM, EXx } },
2530     { "mulsd",  { XM, EXq } },
2531   },
2532
2533   /* PREFIX_0F5A */
2534   {
2535     { "cvtps2pd", { XM, EXq } },
2536     { "cvtss2sd", { XM, EXd } },
2537     { "cvtpd2ps", { XM, EXx } },
2538     { "cvtsd2ss", { XM, EXq } },
2539   },
2540
2541   /* PREFIX_0F5B */
2542   {
2543     { "cvtdq2ps", { XM, EXx } },
2544     { "cvttps2dq", { XM, EXx } },
2545     { "cvtps2dq", { XM, EXx } },
2546     { "(bad)",  { XX } },
2547   },
2548
2549   /* PREFIX_0F5C */
2550   {
2551     { "subps",  { XM, EXx } },
2552     { "subss",  { XM, EXd } },
2553     { "subpd",  { XM, EXx } },
2554     { "subsd",  { XM, EXq } },
2555   },
2556
2557   /* PREFIX_0F5D */
2558   {
2559     { "minps",  { XM, EXx } },
2560     { "minss",  { XM, EXd } },
2561     { "minpd",  { XM, EXx } },
2562     { "minsd",  { XM, EXq } },
2563   },
2564
2565   /* PREFIX_0F5E */
2566   {
2567     { "divps",  { XM, EXx } },
2568     { "divss",  { XM, EXd } },
2569     { "divpd",  { XM, EXx } },
2570     { "divsd",  { XM, EXq } },
2571   },
2572
2573   /* PREFIX_0F5F */
2574   {
2575     { "maxps",  { XM, EXx } },
2576     { "maxss",  { XM, EXd } },
2577     { "maxpd",  { XM, EXx } },
2578     { "maxsd",  { XM, EXq } },
2579   },
2580
2581   /* PREFIX_0F60 */
2582   {
2583     { "punpcklbw",{ MX, EMd } },
2584     { "(bad)",  { XX } },
2585     { "punpcklbw",{ MX, EMx } },
2586     { "(bad)",  { XX } },
2587   },
2588
2589   /* PREFIX_0F61 */
2590   {
2591     { "punpcklwd",{ MX, EMd } },
2592     { "(bad)",  { XX } },
2593     { "punpcklwd",{ MX, EMx } },
2594     { "(bad)",  { XX } },
2595   },
2596
2597   /* PREFIX_0F62 */
2598   {
2599     { "punpckldq",{ MX, EMd } },
2600     { "(bad)",  { XX } },
2601     { "punpckldq",{ MX, EMx } },
2602     { "(bad)",  { XX } },
2603   },
2604
2605   /* PREFIX_0F6C */
2606   {
2607     { "(bad)",  { XX } },
2608     { "(bad)",  { XX } },
2609     { "punpcklqdq", { XM, EXx } },
2610     { "(bad)",  { XX } },
2611   },
2612
2613   /* PREFIX_0F6D */
2614   {
2615     { "(bad)",  { XX } },
2616     { "(bad)",  { XX } },
2617     { "punpckhqdq", { XM, EXx } },
2618     { "(bad)",  { XX } },
2619   },
2620
2621   /* PREFIX_0F6F */
2622   {
2623     { "movq",   { MX, EM } },
2624     { "movdqu", { XM, EXx } },
2625     { "movdqa", { XM, EXx } },
2626     { "(bad)",  { XX } },
2627   },
2628
2629   /* PREFIX_0F70 */
2630   {
2631     { "pshufw", { MX, EM, Ib } },
2632     { "pshufhw",{ XM, EXx, Ib } },
2633     { "pshufd", { XM, EXx, Ib } },
2634     { "pshuflw",{ XM, EXx, Ib } },
2635   },
2636
2637   /* PREFIX_0F73_REG_3 */
2638   {
2639     { "(bad)",  { XX } },
2640     { "(bad)",  { XX } },
2641     { "psrldq", { XS, Ib } },
2642     { "(bad)",  { XX } },
2643   },
2644
2645   /* PREFIX_0F73_REG_7 */
2646   {
2647     { "(bad)",  { XX } },
2648     { "(bad)",  { XX } },
2649     { "pslldq", { XS, Ib } },
2650     { "(bad)",  { XX } },
2651   },
2652
2653   /* PREFIX_0F78 */
2654   {
2655     {"vmread",  { Em, Gm } },
2656     {"(bad)",   { XX } },
2657     {"extrq",   { XS, Ib, Ib } },
2658     {"insertq", { XM, XS, Ib, Ib } },
2659   },
2660
2661   /* PREFIX_0F79 */
2662   {
2663     {"vmwrite", { Gm, Em } },
2664     {"(bad)",   { XX } },
2665     {"extrq",   { XM, XS } },
2666     {"insertq", { XM, XS } },
2667   },
2668
2669   /* PREFIX_0F7C */
2670   {
2671     { "(bad)",  { XX } },
2672     { "(bad)",  { XX } },
2673     { "haddpd", { XM, EXx } },
2674     { "haddps", { XM, EXx } },
2675   },
2676
2677   /* PREFIX_0F7D */
2678   {
2679     { "(bad)",  { XX } },
2680     { "(bad)",  { XX } },
2681     { "hsubpd", { XM, EXx } },
2682     { "hsubps", { XM, EXx } },
2683   },
2684
2685   /* PREFIX_0F7E */
2686   {
2687     { "movK",   { Edq, MX } },
2688     { "movq",   { XM, EXq } },
2689     { "movK",   { Edq, XM } },
2690     { "(bad)",  { XX } },
2691   },
2692
2693   /* PREFIX_0F7F */
2694   {
2695     { "movq",   { EMS, MX } },
2696     { "movdqu", { EXxS, XM } },
2697     { "movdqa", { EXxS, XM } },
2698     { "(bad)",  { XX } },
2699   },
2700
2701   /* PREFIX_0FB8 */
2702   {
2703     { "(bad)", { XX } },
2704     { "popcntS", { Gv, Ev } },
2705     { "(bad)", { XX } },
2706     { "(bad)", { XX } },
2707   },
2708
2709   /* PREFIX_0FBD */
2710   {
2711     { "bsrS",   { Gv, Ev } },
2712     { "lzcntS", { Gv, Ev } },
2713     { "bsrS",   { Gv, Ev } },
2714     { "(bad)",  { XX } },
2715   },
2716
2717   /* PREFIX_0FC2 */
2718   {
2719     { "cmpps",  { XM, EXx, CMP } },
2720     { "cmpss",  { XM, EXd, CMP } },
2721     { "cmppd",  { XM, EXx, CMP } },
2722     { "cmpsd",  { XM, EXq, CMP } },
2723   },
2724
2725   /* PREFIX_0FC3 */
2726   {
2727     { "movntiS", { Ma, Gv } },
2728     { "(bad)",  { XX } },
2729     { "(bad)",  { XX } },
2730     { "(bad)",  { XX } },
2731   },
2732
2733   /* PREFIX_0FC7_REG_6 */
2734   {
2735     { "vmptrld",{ Mq } },
2736     { "vmxon",  { Mq } },
2737     { "vmclear",{ Mq } },
2738     { "(bad)",  { XX } },
2739   },
2740
2741   /* PREFIX_0FD0 */
2742   {
2743     { "(bad)",  { XX } },
2744     { "(bad)",  { XX } },
2745     { "addsubpd", { XM, EXx } },
2746     { "addsubps", { XM, EXx } },
2747   },
2748
2749   /* PREFIX_0FD6 */
2750   {
2751     { "(bad)",  { XX } },
2752     { "movq2dq",{ XM, MS } },
2753     { "movq",   { EXqS, XM } },
2754     { "movdq2q",{ MX, XS } },
2755   },
2756
2757   /* PREFIX_0FE6 */
2758   {
2759     { "(bad)",  { XX } },
2760     { "cvtdq2pd", { XM, EXq } },
2761     { "cvttpd2dq", { XM, EXx } },
2762     { "cvtpd2dq", { XM, EXx } },
2763   },
2764
2765   /* PREFIX_0FE7 */
2766   {
2767     { "movntq", { Mq, MX } },
2768     { "(bad)",  { XX } },
2769     { MOD_TABLE (MOD_0FE7_PREFIX_2) },
2770     { "(bad)",  { XX } },
2771   },
2772
2773   /* PREFIX_0FF0 */
2774   {
2775     { "(bad)",  { XX } },
2776     { "(bad)",  { XX } },
2777     { "(bad)",  { XX } },
2778     { MOD_TABLE (MOD_0FF0_PREFIX_3) },
2779   },
2780
2781   /* PREFIX_0FF7 */
2782   {
2783     { "maskmovq", { MX, MS } },
2784     { "(bad)",  { XX } },
2785     { "maskmovdqu", { XM, XS } },
2786     { "(bad)",  { XX } },
2787   },
2788
2789   /* PREFIX_0F3810 */
2790   {
2791     { "(bad)",  { XX } },
2792     { "(bad)",  { XX } },
2793     { "pblendvb", { XM, EXx, XMM0 } },
2794     { "(bad)",  { XX } },
2795   },
2796
2797   /* PREFIX_0F3814 */
2798   {
2799     { "(bad)",  { XX } },
2800     { "(bad)",  { XX } },
2801     { "blendvps", { XM, EXx, XMM0 } },
2802     { "(bad)",  { XX } },
2803   },
2804
2805   /* PREFIX_0F3815 */
2806   {
2807     { "(bad)",  { XX } },
2808     { "(bad)",  { XX } },
2809     { "blendvpd", { XM, EXx, XMM0 } },
2810     { "(bad)",  { XX } },
2811   },
2812
2813   /* PREFIX_0F3817 */
2814   {
2815     { "(bad)",  { XX } },
2816     { "(bad)",  { XX } },
2817     { "ptest",  { XM, EXx } },
2818     { "(bad)",  { XX } },
2819   },
2820
2821   /* PREFIX_0F3820 */
2822   {
2823     { "(bad)",  { XX } },
2824     { "(bad)",  { XX } },
2825     { "pmovsxbw", { XM, EXq } },
2826     { "(bad)",  { XX } },
2827   },
2828
2829   /* PREFIX_0F3821 */
2830   {
2831     { "(bad)",  { XX } },
2832     { "(bad)",  { XX } },
2833     { "pmovsxbd", { XM, EXd } },
2834     { "(bad)",  { XX } },
2835   },
2836
2837   /* PREFIX_0F3822 */
2838   {
2839     { "(bad)",  { XX } },
2840     { "(bad)",  { XX } },
2841     { "pmovsxbq", { XM, EXw } },
2842     { "(bad)",  { XX } },
2843   },
2844
2845   /* PREFIX_0F3823 */
2846   {
2847     { "(bad)",  { XX } },
2848     { "(bad)",  { XX } },
2849     { "pmovsxwd", { XM, EXq } },
2850     { "(bad)",  { XX } },
2851   },
2852
2853   /* PREFIX_0F3824 */
2854   {
2855     { "(bad)",  { XX } },
2856     { "(bad)",  { XX } },
2857     { "pmovsxwq", { XM, EXd } },
2858     { "(bad)",  { XX } },
2859   },
2860
2861   /* PREFIX_0F3825 */
2862   {
2863     { "(bad)",  { XX } },
2864     { "(bad)",  { XX } },
2865     { "pmovsxdq", { XM, EXq } },
2866     { "(bad)",  { XX } },
2867   },
2868
2869   /* PREFIX_0F3828 */
2870   {
2871     { "(bad)",  { XX } },
2872     { "(bad)",  { XX } },
2873     { "pmuldq", { XM, EXx } },
2874     { "(bad)",  { XX } },
2875   },
2876
2877   /* PREFIX_0F3829 */
2878   {
2879     { "(bad)",  { XX } },
2880     { "(bad)",  { XX } },
2881     { "pcmpeqq", { XM, EXx } },
2882     { "(bad)",  { XX } },
2883   },
2884
2885   /* PREFIX_0F382A */
2886   {
2887     { "(bad)",  { XX } },
2888     { "(bad)",  { XX } },
2889     { MOD_TABLE (MOD_0F382A_PREFIX_2) },
2890     { "(bad)",  { XX } },
2891   },
2892
2893   /* PREFIX_0F382B */
2894   {
2895     { "(bad)",  { XX } },
2896     { "(bad)",  { XX } },
2897     { "packusdw", { XM, EXx } },
2898     { "(bad)",  { XX } },
2899   },
2900
2901   /* PREFIX_0F3830 */
2902   {
2903     { "(bad)",  { XX } },
2904     { "(bad)",  { XX } },
2905     { "pmovzxbw", { XM, EXq } },
2906     { "(bad)",  { XX } },
2907   },
2908
2909   /* PREFIX_0F3831 */
2910   {
2911     { "(bad)",  { XX } },
2912     { "(bad)",  { XX } },
2913     { "pmovzxbd", { XM, EXd } },
2914     { "(bad)",  { XX } },
2915   },
2916
2917   /* PREFIX_0F3832 */
2918   {
2919     { "(bad)",  { XX } },
2920     { "(bad)",  { XX } },
2921     { "pmovzxbq", { XM, EXw } },
2922     { "(bad)",  { XX } },
2923   },
2924
2925   /* PREFIX_0F3833 */
2926   {
2927     { "(bad)",  { XX } },
2928     { "(bad)",  { XX } },
2929     { "pmovzxwd", { XM, EXq } },
2930     { "(bad)",  { XX } },
2931   },
2932
2933   /* PREFIX_0F3834 */
2934   {
2935     { "(bad)",  { XX } },
2936     { "(bad)",  { XX } },
2937     { "pmovzxwq", { XM, EXd } },
2938     { "(bad)",  { XX } },
2939   },
2940
2941   /* PREFIX_0F3835 */
2942   {
2943     { "(bad)",  { XX } },
2944     { "(bad)",  { XX } },
2945     { "pmovzxdq", { XM, EXq } },
2946     { "(bad)",  { XX } },
2947   },
2948
2949   /* PREFIX_0F3837 */
2950   {
2951     { "(bad)",  { XX } },
2952     { "(bad)",  { XX } },
2953     { "pcmpgtq", { XM, EXx } },
2954     { "(bad)",  { XX } },
2955   },
2956
2957   /* PREFIX_0F3838 */
2958   {
2959     { "(bad)",  { XX } },
2960     { "(bad)",  { XX } },
2961     { "pminsb", { XM, EXx } },
2962     { "(bad)",  { XX } },
2963   },
2964
2965   /* PREFIX_0F3839 */
2966   {
2967     { "(bad)",  { XX } },
2968     { "(bad)",  { XX } },
2969     { "pminsd", { XM, EXx } },
2970     { "(bad)",  { XX } },
2971   },
2972
2973   /* PREFIX_0F383A */
2974   {
2975     { "(bad)",  { XX } },
2976     { "(bad)",  { XX } },
2977     { "pminuw", { XM, EXx } },
2978     { "(bad)",  { XX } },
2979   },
2980
2981   /* PREFIX_0F383B */
2982   {
2983     { "(bad)",  { XX } },
2984     { "(bad)",  { XX } },
2985     { "pminud", { XM, EXx } },
2986     { "(bad)",  { XX } },
2987   },
2988
2989   /* PREFIX_0F383C */
2990   {
2991     { "(bad)",  { XX } },
2992     { "(bad)",  { XX } },
2993     { "pmaxsb", { XM, EXx } },
2994     { "(bad)",  { XX } },
2995   },
2996
2997   /* PREFIX_0F383D */
2998   {
2999     { "(bad)",  { XX } },
3000     { "(bad)",  { XX } },
3001     { "pmaxsd", { XM, EXx } },
3002     { "(bad)",  { XX } },
3003   },
3004
3005   /* PREFIX_0F383E */
3006   {
3007     { "(bad)",  { XX } },
3008     { "(bad)",  { XX } },
3009     { "pmaxuw", { XM, EXx } },
3010     { "(bad)",  { XX } },
3011   },
3012
3013   /* PREFIX_0F383F */
3014   {
3015     { "(bad)",  { XX } },
3016     { "(bad)",  { XX } },
3017     { "pmaxud", { XM, EXx } },
3018     { "(bad)",  { XX } },
3019   },
3020
3021   /* PREFIX_0F3840 */
3022   {
3023     { "(bad)",  { XX } },
3024     { "(bad)",  { XX } },
3025     { "pmulld", { XM, EXx } },
3026     { "(bad)",  { XX } },
3027   },
3028
3029   /* PREFIX_0F3841 */
3030   {
3031     { "(bad)",  { XX } },
3032     { "(bad)",  { XX } },
3033     { "phminposuw", { XM, EXx } },
3034     { "(bad)",  { XX } },
3035   },
3036
3037   /* PREFIX_0F3880 */
3038   {
3039     { "(bad)",  { XX } },
3040     { "(bad)",  { XX } },
3041     { "invept", { Gm, Mo } },
3042     { "(bad)",  { XX } },
3043   },
3044
3045   /* PREFIX_0F3881 */
3046   {
3047     { "(bad)",  { XX } },
3048     { "(bad)",  { XX } },
3049     { "invvpid", { Gm, Mo } },
3050     { "(bad)",  { XX } },
3051   },
3052
3053   /* PREFIX_0F38DB */
3054   {
3055     { "(bad)",  { XX } },
3056     { "(bad)",  { XX } },
3057     { "aesimc", { XM, EXx } },
3058     { "(bad)",  { XX } },
3059   },
3060
3061   /* PREFIX_0F38DC */
3062   {
3063     { "(bad)",  { XX } },
3064     { "(bad)",  { XX } },
3065     { "aesenc", { XM, EXx } },
3066     { "(bad)",  { XX } },
3067   },
3068
3069   /* PREFIX_0F38DD */
3070   {
3071     { "(bad)",  { XX } },
3072     { "(bad)",  { XX } },
3073     { "aesenclast", { XM, EXx } },
3074     { "(bad)",  { XX } },
3075   },
3076
3077   /* PREFIX_0F38DE */
3078   {
3079     { "(bad)",  { XX } },
3080     { "(bad)",  { XX } },
3081     { "aesdec", { XM, EXx } },
3082     { "(bad)",  { XX } },
3083   },
3084
3085   /* PREFIX_0F38DF */
3086   {
3087     { "(bad)",  { XX } },
3088     { "(bad)",  { XX } },
3089     { "aesdeclast", { XM, EXx } },
3090     { "(bad)",  { XX } },
3091   },
3092
3093   /* PREFIX_0F38F0 */
3094   {
3095     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } } },
3096     { "(bad)",  { XX } },
3097     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } } },
3098     { "crc32",  { Gdq, { CRC32_Fixup, b_mode } } },
3099   },
3100
3101   /* PREFIX_0F38F1 */
3102   {
3103     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv } },
3104     { "(bad)",  { XX } },
3105     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv } },
3106     { "crc32",  { Gdq, { CRC32_Fixup, v_mode } } },
3107   },
3108
3109   /* PREFIX_0F3A08 */
3110   {
3111     { "(bad)",  { XX } },
3112     { "(bad)",  { XX } },
3113     { "roundps", { XM, EXx, Ib } },
3114     { "(bad)",  { XX } },
3115   },
3116
3117   /* PREFIX_0F3A09 */
3118   {
3119     { "(bad)",  { XX } },
3120     { "(bad)",  { XX } },
3121     { "roundpd", { XM, EXx, Ib } },
3122     { "(bad)",  { XX } },
3123   },
3124
3125   /* PREFIX_0F3A0A */
3126   {
3127     { "(bad)",  { XX } },
3128     { "(bad)",  { XX } },
3129     { "roundss", { XM, EXd, Ib } },
3130     { "(bad)",  { XX } },
3131   },
3132
3133   /* PREFIX_0F3A0B */
3134   {
3135     { "(bad)",  { XX } },
3136     { "(bad)",  { XX } },
3137     { "roundsd", { XM, EXq, Ib } },
3138     { "(bad)",  { XX } },
3139   },
3140
3141   /* PREFIX_0F3A0C */
3142   {
3143     { "(bad)",  { XX } },
3144     { "(bad)",  { XX } },
3145     { "blendps", { XM, EXx, Ib } },
3146     { "(bad)",  { XX } },
3147   },
3148
3149   /* PREFIX_0F3A0D */
3150   {
3151     { "(bad)",  { XX } },
3152     { "(bad)",  { XX } },
3153     { "blendpd", { XM, EXx, Ib } },
3154     { "(bad)",  { XX } },
3155   },
3156
3157   /* PREFIX_0F3A0E */
3158   {
3159     { "(bad)",  { XX } },
3160     { "(bad)",  { XX } },
3161     { "pblendw", { XM, EXx, Ib } },
3162     { "(bad)",  { XX } },
3163   },
3164
3165   /* PREFIX_0F3A14 */
3166   {
3167     { "(bad)",  { XX } },
3168     { "(bad)",  { XX } },
3169     { "pextrb", { Edqb, XM, Ib } },
3170     { "(bad)",  { XX } },
3171   },
3172
3173   /* PREFIX_0F3A15 */
3174   {
3175     { "(bad)",  { XX } },
3176     { "(bad)",  { XX } },
3177     { "pextrw", { Edqw, XM, Ib } },
3178     { "(bad)",  { XX } },
3179   },
3180
3181   /* PREFIX_0F3A16 */
3182   {
3183     { "(bad)",  { XX } },
3184     { "(bad)",  { XX } },
3185     { "pextrK", { Edq, XM, Ib } },
3186     { "(bad)",  { XX } },
3187   },
3188
3189   /* PREFIX_0F3A17 */
3190   {
3191     { "(bad)",  { XX } },
3192     { "(bad)",  { XX } },
3193     { "extractps", { Edqd, XM, Ib } },
3194     { "(bad)",  { XX } },
3195   },
3196
3197   /* PREFIX_0F3A20 */
3198   {
3199     { "(bad)",  { XX } },
3200     { "(bad)",  { XX } },
3201     { "pinsrb", { XM, Edqb, Ib } },
3202     { "(bad)",  { XX } },
3203   },
3204
3205   /* PREFIX_0F3A21 */
3206   {
3207     { "(bad)",  { XX } },
3208     { "(bad)",  { XX } },
3209     { "insertps", { XM, EXd, Ib } },
3210     { "(bad)",  { XX } },
3211   },
3212
3213   /* PREFIX_0F3A22 */
3214   {
3215     { "(bad)",  { XX } },
3216     { "(bad)",  { XX } },
3217     { "pinsrK", { XM, Edq, Ib } },
3218     { "(bad)",  { XX } },
3219   },
3220
3221   /* PREFIX_0F3A40 */
3222   {
3223     { "(bad)",  { XX } },
3224     { "(bad)",  { XX } },
3225     { "dpps",   { XM, EXx, Ib } },
3226     { "(bad)",  { XX } },
3227   },
3228
3229   /* PREFIX_0F3A41 */
3230   {
3231     { "(bad)",  { XX } },
3232     { "(bad)",  { XX } },
3233     { "dppd",   { XM, EXx, Ib } },
3234     { "(bad)",  { XX } },
3235   },
3236
3237   /* PREFIX_0F3A42 */
3238   {
3239     { "(bad)",  { XX } },
3240     { "(bad)",  { XX } },
3241     { "mpsadbw", { XM, EXx, Ib } },
3242     { "(bad)",  { XX } },
3243   },
3244
3245   /* PREFIX_0F3A44 */
3246   {
3247     { "(bad)",  { XX } },
3248     { "(bad)",  { XX } },
3249     { "pclmulqdq", { XM, EXx, PCLMUL } },
3250     { "(bad)",  { XX } },
3251   },
3252
3253   /* PREFIX_0F3A60 */
3254   {
3255     { "(bad)",  { XX } },
3256     { "(bad)",  { XX } },
3257     { "pcmpestrm", { XM, EXx, Ib } },
3258     { "(bad)",  { XX } },
3259   },
3260
3261   /* PREFIX_0F3A61 */
3262   {
3263     { "(bad)",  { XX } },
3264     { "(bad)",  { XX } },
3265     { "pcmpestri", { XM, EXx, Ib } },
3266     { "(bad)",  { XX } },
3267   },
3268
3269   /* PREFIX_0F3A62 */
3270   {
3271     { "(bad)",  { XX } },
3272     { "(bad)",  { XX } },
3273     { "pcmpistrm", { XM, EXx, Ib } },
3274     { "(bad)",  { XX } },
3275   },
3276
3277   /* PREFIX_0F3A63 */
3278   {
3279     { "(bad)",  { XX } },
3280     { "(bad)",  { XX } },
3281     { "pcmpistri", { XM, EXx, Ib } },
3282     { "(bad)",  { XX } },
3283   },
3284
3285   /* PREFIX_0F3ADF */
3286   {
3287     { "(bad)",  { XX } },
3288     { "(bad)",  { XX } },
3289     { "aeskeygenassist", { XM, EXx, Ib } },
3290     { "(bad)",  { XX } },
3291   },
3292
3293   /* PREFIX_VEX_10 */
3294   {
3295     { "vmovups", { XM, EXx } },
3296     { VEX_LEN_TABLE (VEX_LEN_10_P_1) },
3297     { "vmovupd", { XM, EXx } },
3298     { VEX_LEN_TABLE (VEX_LEN_10_P_3) },
3299   },
3300
3301   /* PREFIX_VEX_11 */
3302   {
3303     { "vmovups", { EXxS, XM } },
3304     { VEX_LEN_TABLE (VEX_LEN_11_P_1) },
3305     { "vmovupd", { EXxS, XM } },
3306     { VEX_LEN_TABLE (VEX_LEN_11_P_3) },
3307   },
3308
3309   /* PREFIX_VEX_12 */
3310   {
3311     { MOD_TABLE (MOD_VEX_12_PREFIX_0) },
3312     { "vmovsldup", { XM, EXx } },
3313     { VEX_LEN_TABLE (VEX_LEN_12_P_2) },
3314     { "vmovddup", { XM, EXymmq } },
3315   },
3316
3317   /* PREFIX_VEX_16 */
3318   {
3319     { MOD_TABLE (MOD_VEX_16_PREFIX_0) },
3320     { "vmovshdup", { XM, EXx } },
3321     { VEX_LEN_TABLE (VEX_LEN_16_P_2) },
3322     { "(bad)",  { XX } },
3323   },
3324
3325   /* PREFIX_VEX_2A */
3326   {
3327     { "(bad)",  { XX } },
3328     { VEX_LEN_TABLE (VEX_LEN_2A_P_1) },
3329     { "(bad)",  { XX } },
3330     { VEX_LEN_TABLE (VEX_LEN_2A_P_3) },
3331   },
3332
3333   /* PREFIX_VEX_2C */
3334   {
3335     { "(bad)",  { XX } },
3336     { VEX_LEN_TABLE (VEX_LEN_2C_P_1) },
3337     { "(bad)",  { XX } },
3338     { VEX_LEN_TABLE (VEX_LEN_2C_P_3) },
3339   },
3340
3341   /* PREFIX_VEX_2D */
3342   {
3343     { "(bad)",  { XX } },
3344     { VEX_LEN_TABLE (VEX_LEN_2D_P_1) },
3345     { "(bad)",  { XX } },
3346     { VEX_LEN_TABLE (VEX_LEN_2D_P_3) },
3347   },
3348
3349   /* PREFIX_VEX_2E */
3350   {
3351     { VEX_LEN_TABLE (VEX_LEN_2E_P_0) },
3352     { "(bad)",  { XX } },
3353     { VEX_LEN_TABLE (VEX_LEN_2E_P_2) },
3354     { "(bad)",  { XX } },
3355   },
3356
3357   /* PREFIX_VEX_2F */
3358   {
3359     { VEX_LEN_TABLE (VEX_LEN_2F_P_0) },
3360     { "(bad)",  { XX } },
3361     { VEX_LEN_TABLE (VEX_LEN_2F_P_2) },
3362     { "(bad)",  { XX } },
3363   },
3364
3365   /* PREFIX_VEX_51 */
3366   {
3367     { "vsqrtps", { XM, EXx } },
3368     { VEX_LEN_TABLE (VEX_LEN_51_P_1) },
3369     { "vsqrtpd", { XM, EXx } },
3370     { VEX_LEN_TABLE (VEX_LEN_51_P_3) },
3371   },
3372
3373   /* PREFIX_VEX_52 */
3374   {
3375     { "vrsqrtps", { XM, EXx } },
3376     { VEX_LEN_TABLE (VEX_LEN_52_P_1) },
3377     { "(bad)",  { XX } },
3378     { "(bad)",  { XX } },
3379   },
3380
3381   /* PREFIX_VEX_53 */
3382   {
3383     { "vrcpps", { XM, EXx } },
3384     { VEX_LEN_TABLE (VEX_LEN_53_P_1) },
3385     { "(bad)",  { XX } },
3386     { "(bad)",  { XX } },
3387   },
3388
3389   /* PREFIX_VEX_58 */
3390   {
3391     { "vaddps", { XM, Vex, EXx } },
3392     { VEX_LEN_TABLE (VEX_LEN_58_P_1) },
3393     { "vaddpd", { XM, Vex, EXx } },
3394     { VEX_LEN_TABLE (VEX_LEN_58_P_3) },
3395   },
3396
3397   /* PREFIX_VEX_59 */
3398   {
3399     { "vmulps", { XM, Vex, EXx } },
3400     { VEX_LEN_TABLE (VEX_LEN_59_P_1) },
3401     { "vmulpd", { XM, Vex, EXx } },
3402     { VEX_LEN_TABLE (VEX_LEN_59_P_3) },
3403   },
3404
3405   /* PREFIX_VEX_5A */
3406   {
3407     { "vcvtps2pd", { XM, EXxmmq } },
3408     { VEX_LEN_TABLE (VEX_LEN_5A_P_1) },
3409     { "vcvtpd2ps%XY", { XMM, EXx } },
3410     { VEX_LEN_TABLE (VEX_LEN_5A_P_3) },
3411   },
3412
3413   /* PREFIX_VEX_5B */
3414   {
3415     { "vcvtdq2ps", { XM, EXx } },
3416     { "vcvttps2dq", { XM, EXx } },
3417     { "vcvtps2dq", { XM, EXx } },
3418     { "(bad)",  { XX } },
3419   },
3420
3421   /* PREFIX_VEX_5C */
3422   {
3423     { "vsubps", { XM, Vex, EXx } },
3424     { VEX_LEN_TABLE (VEX_LEN_5C_P_1) },
3425     { "vsubpd", { XM, Vex, EXx } },
3426     { VEX_LEN_TABLE (VEX_LEN_5C_P_3) },
3427   },
3428
3429   /* PREFIX_VEX_5D */
3430   {
3431     { "vminps", { XM, Vex, EXx } },
3432     { VEX_LEN_TABLE (VEX_LEN_5D_P_1) },
3433     { "vminpd", { XM, Vex, EXx } },
3434     { VEX_LEN_TABLE (VEX_LEN_5D_P_3) },
3435   },
3436
3437   /* PREFIX_VEX_5E */
3438   {
3439     { "vdivps", { XM, Vex, EXx } },
3440     { VEX_LEN_TABLE (VEX_LEN_5E_P_1) },
3441     { "vdivpd", { XM, Vex, EXx } },
3442     { VEX_LEN_TABLE (VEX_LEN_5E_P_3) },
3443   },
3444
3445   /* PREFIX_VEX_5F */
3446   {
3447     { "vmaxps", { XM, Vex, EXx } },
3448     { VEX_LEN_TABLE (VEX_LEN_5F_P_1) },
3449     { "vmaxpd", { XM, Vex, EXx } },
3450     { VEX_LEN_TABLE (VEX_LEN_5F_P_3) },
3451   },
3452
3453   /* PREFIX_VEX_60 */
3454   {
3455     { "(bad)",  { XX } },
3456     { "(bad)",  { XX } },
3457     { VEX_LEN_TABLE (VEX_LEN_60_P_2) },
3458     { "(bad)",  { XX } },
3459   },
3460
3461   /* PREFIX_VEX_61 */
3462   {
3463     { "(bad)",  { XX } },
3464     { "(bad)",  { XX } },
3465     { VEX_LEN_TABLE (VEX_LEN_61_P_2) },
3466     { "(bad)",  { XX } },
3467   },
3468
3469   /* PREFIX_VEX_62 */
3470   {
3471     { "(bad)",  { XX } },
3472     { "(bad)",  { XX } },
3473     { VEX_LEN_TABLE (VEX_LEN_62_P_2) },
3474     { "(bad)",  { XX } },
3475   },
3476
3477   /* PREFIX_VEX_63 */
3478   {
3479     { "(bad)",  { XX } },
3480     { "(bad)",  { XX } },
3481     { VEX_LEN_TABLE (VEX_LEN_63_P_2) },
3482     { "(bad)",  { XX } },
3483   },
3484
3485   /* PREFIX_VEX_64 */
3486   {
3487     { "(bad)",  { XX } },
3488     { "(bad)",  { XX } },
3489     { VEX_LEN_TABLE (VEX_LEN_64_P_2) },
3490     { "(bad)",  { XX } },
3491   },
3492
3493   /* PREFIX_VEX_65 */
3494   {
3495     { "(bad)",  { XX } },
3496     { "(bad)",  { XX } },
3497     { VEX_LEN_TABLE (VEX_LEN_65_P_2) },
3498     { "(bad)",  { XX } },
3499   },
3500
3501   /* PREFIX_VEX_66 */
3502   {
3503     { "(bad)",  { XX } },
3504     { "(bad)",  { XX } },
3505     { VEX_LEN_TABLE (VEX_LEN_66_P_2) },
3506     { "(bad)",  { XX } },
3507   },
3508
3509   /* PREFIX_VEX_67 */
3510   {
3511     { "(bad)",  { XX } },
3512     { "(bad)",  { XX } },
3513     { VEX_LEN_TABLE (VEX_LEN_67_P_2) },
3514     { "(bad)",  { XX } },
3515   },
3516
3517   /* PREFIX_VEX_68 */
3518   {
3519     { "(bad)",  { XX } },
3520     { "(bad)",  { XX } },
3521     { VEX_LEN_TABLE (VEX_LEN_68_P_2) },
3522     { "(bad)",  { XX } },
3523   },
3524
3525   /* PREFIX_VEX_69 */
3526   {
3527     { "(bad)",  { XX } },
3528     { "(bad)",  { XX } },
3529     { VEX_LEN_TABLE (VEX_LEN_69_P_2) },
3530     { "(bad)",  { XX } },
3531   },
3532
3533   /* PREFIX_VEX_6A */
3534   {
3535     { "(bad)",  { XX } },
3536     { "(bad)",  { XX } },
3537     { VEX_LEN_TABLE (VEX_LEN_6A_P_2) },
3538     { "(bad)",  { XX } },
3539   },
3540
3541   /* PREFIX_VEX_6B */
3542   {
3543     { "(bad)",  { XX } },
3544     { "(bad)",  { XX } },
3545     { VEX_LEN_TABLE (VEX_LEN_6B_P_2) },
3546     { "(bad)",  { XX } },
3547   },
3548
3549   /* PREFIX_VEX_6C */
3550   {
3551     { "(bad)",  { XX } },
3552     { "(bad)",  { XX } },
3553     { VEX_LEN_TABLE (VEX_LEN_6C_P_2) },
3554     { "(bad)",  { XX } },
3555   },
3556
3557   /* PREFIX_VEX_6D */
3558   {
3559     { "(bad)",  { XX } },
3560     { "(bad)",  { XX } },
3561     { VEX_LEN_TABLE (VEX_LEN_6D_P_2) },
3562     { "(bad)",  { XX } },
3563   },
3564
3565   /* PREFIX_VEX_6E */
3566   {
3567     { "(bad)",  { XX } },
3568     { "(bad)",  { XX } },
3569     { VEX_LEN_TABLE (VEX_LEN_6E_P_2) },
3570     { "(bad)",  { XX } },
3571   },
3572
3573   /* PREFIX_VEX_6F */
3574   {
3575     { "(bad)",  { XX } },
3576     { "vmovdqu", { XM, EXx } },
3577     { "vmovdqa", { XM, EXx } },
3578     { "(bad)",  { XX } },
3579   },
3580
3581   /* PREFIX_VEX_70 */
3582   {
3583     { "(bad)",  { XX } },
3584     { VEX_LEN_TABLE (VEX_LEN_70_P_1) },
3585     { VEX_LEN_TABLE (VEX_LEN_70_P_2) },
3586     { VEX_LEN_TABLE (VEX_LEN_70_P_3) },
3587   },
3588
3589   /* PREFIX_VEX_71_REG_2 */
3590   {
3591     { "(bad)",  { XX } },
3592     { "(bad)",  { XX } },
3593     { VEX_LEN_TABLE (VEX_LEN_71_R_2_P_2) },
3594     { "(bad)",  { XX } },
3595   },
3596
3597   /* PREFIX_VEX_71_REG_4 */
3598   {
3599     { "(bad)",  { XX } },
3600     { "(bad)",  { XX } },
3601     { VEX_LEN_TABLE (VEX_LEN_71_R_4_P_2) },
3602     { "(bad)",  { XX } },
3603   },
3604
3605   /* PREFIX_VEX_71_REG_6 */
3606   {
3607     { "(bad)",  { XX } },
3608     { "(bad)",  { XX } },
3609     { VEX_LEN_TABLE (VEX_LEN_71_R_6_P_2) },
3610     { "(bad)",  { XX } },
3611   },
3612
3613   /* PREFIX_VEX_72_REG_2 */
3614   {
3615     { "(bad)",  { XX } },
3616     { "(bad)",  { XX } },
3617     { VEX_LEN_TABLE (VEX_LEN_72_R_2_P_2) },
3618     { "(bad)",  { XX } },
3619   },
3620
3621   /* PREFIX_VEX_72_REG_4 */
3622   {
3623     { "(bad)",  { XX } },
3624     { "(bad)",  { XX } },
3625     { VEX_LEN_TABLE (VEX_LEN_72_R_4_P_2) },
3626     { "(bad)",  { XX } },
3627   },
3628
3629   /* PREFIX_VEX_72_REG_6 */
3630   {
3631     { "(bad)",  { XX } },
3632     { "(bad)",  { XX } },
3633     { VEX_LEN_TABLE (VEX_LEN_72_R_6_P_2) },
3634     { "(bad)",  { XX } },
3635   },
3636
3637   /* PREFIX_VEX_73_REG_2 */
3638   {
3639     { "(bad)",  { XX } },
3640     { "(bad)",  { XX } },
3641     { VEX_LEN_TABLE (VEX_LEN_73_R_2_P_2) },
3642     { "(bad)",  { XX } },
3643   },
3644
3645   /* PREFIX_VEX_73_REG_3 */
3646   {
3647     { "(bad)",  { XX } },
3648     { "(bad)",  { XX } },
3649     { VEX_LEN_TABLE (VEX_LEN_73_R_3_P_2) },
3650     { "(bad)",  { XX } },
3651   },
3652
3653   /* PREFIX_VEX_73_REG_6 */
3654   {
3655     { "(bad)",  { XX } },
3656     { "(bad)",  { XX } },
3657     { VEX_LEN_TABLE (VEX_LEN_73_R_6_P_2) },
3658     { "(bad)",  { XX } },
3659   },
3660
3661   /* PREFIX_VEX_73_REG_7 */
3662   {
3663     { "(bad)",  { XX } },
3664     { "(bad)",  { XX } },
3665     { VEX_LEN_TABLE (VEX_LEN_73_R_7_P_2) },
3666     { "(bad)",  { XX } },
3667   },
3668
3669   /* PREFIX_VEX_74 */
3670   {
3671     { "(bad)",  { XX } },
3672     { "(bad)",  { XX } },
3673     { VEX_LEN_TABLE (VEX_LEN_74_P_2) },
3674     { "(bad)",  { XX } },
3675   },
3676
3677   /* PREFIX_VEX_75 */
3678   {
3679     { "(bad)",  { XX } },
3680     { "(bad)",  { XX } },
3681     { VEX_LEN_TABLE (VEX_LEN_75_P_2) },
3682     { "(bad)",  { XX } },
3683   },
3684
3685   /* PREFIX_VEX_76 */
3686   {
3687     { "(bad)",  { XX } },
3688     { "(bad)",  { XX } },
3689     { VEX_LEN_TABLE (VEX_LEN_76_P_2) },
3690     { "(bad)",  { XX } },
3691   },
3692
3693   /* PREFIX_VEX_77 */
3694   {
3695     { "",       { VZERO } },
3696     { "(bad)",  { XX } },
3697     { "(bad)",  { XX } },
3698     { "(bad)",  { XX } },
3699   },
3700
3701   /* PREFIX_VEX_7C */
3702   {
3703     { "(bad)",  { XX } },
3704     { "(bad)",  { XX } },
3705     { "vhaddpd", { XM, Vex, EXx } },
3706     { "vhaddps", { XM, Vex, EXx } },
3707   },
3708
3709   /* PREFIX_VEX_7D */
3710   {
3711     { "(bad)",  { XX } },
3712     { "(bad)",  { XX } },
3713     { "vhsubpd", { XM, Vex, EXx } },
3714     { "vhsubps", { XM, Vex, EXx } },
3715   },
3716
3717   /* PREFIX_VEX_7E */
3718   {
3719     { "(bad)",  { XX } },
3720     { VEX_LEN_TABLE (VEX_LEN_7E_P_1) },
3721     { VEX_LEN_TABLE (VEX_LEN_7E_P_2) },
3722     { "(bad)",  { XX } },
3723   },
3724
3725   /* PREFIX_VEX_7F */
3726   {
3727     { "(bad)",  { XX } },
3728     { "vmovdqu", { EXxS, XM } },
3729     { "vmovdqa", { EXxS, XM } },
3730     { "(bad)",  { XX } },
3731   },
3732
3733   /* PREFIX_VEX_C2 */
3734   {
3735     { "vcmpps", { XM, Vex, EXx, VCMP } },
3736     { VEX_LEN_TABLE (VEX_LEN_C2_P_1) },
3737     { "vcmppd", { XM, Vex, EXx, VCMP } },
3738     { VEX_LEN_TABLE (VEX_LEN_C2_P_3) },
3739   },
3740
3741   /* PREFIX_VEX_C4 */
3742   {
3743     { "(bad)",  { XX } },
3744     { "(bad)",  { XX } },
3745     { VEX_LEN_TABLE (VEX_LEN_C4_P_2) },
3746     { "(bad)",  { XX } },
3747   },
3748
3749   /* PREFIX_VEX_C5 */
3750   {
3751     { "(bad)",  { XX } },
3752     { "(bad)",  { XX } },
3753     { VEX_LEN_TABLE (VEX_LEN_C5_P_2) },
3754     { "(bad)",  { XX } },
3755   },
3756
3757   /* PREFIX_VEX_D0 */
3758   {
3759     { "(bad)",  { XX } },
3760     { "(bad)",  { XX } },
3761     { "vaddsubpd", { XM, Vex, EXx } },
3762     { "vaddsubps", { XM, Vex, EXx } },
3763   },
3764
3765   /* PREFIX_VEX_D1 */
3766   {
3767     { "(bad)",  { XX } },
3768     { "(bad)",  { XX } },
3769     { VEX_LEN_TABLE (VEX_LEN_D1_P_2) },
3770     { "(bad)",  { XX } },
3771   },
3772
3773   /* PREFIX_VEX_D2 */
3774   {
3775     { "(bad)",  { XX } },
3776     { "(bad)",  { XX } },
3777     { VEX_LEN_TABLE (VEX_LEN_D2_P_2) },
3778     { "(bad)",  { XX } },
3779   },
3780
3781   /* PREFIX_VEX_D3 */
3782   {
3783     { "(bad)",  { XX } },
3784     { "(bad)",  { XX } },
3785     { VEX_LEN_TABLE (VEX_LEN_D3_P_2) },
3786     { "(bad)",  { XX } },
3787   },
3788
3789   /* PREFIX_VEX_D4 */
3790   {
3791     { "(bad)",  { XX } },
3792     { "(bad)",  { XX } },
3793     { VEX_LEN_TABLE (VEX_LEN_D4_P_2) },
3794     { "(bad)",  { XX } },
3795   },
3796
3797   /* PREFIX_VEX_D5 */
3798   {
3799     { "(bad)",  { XX } },
3800     { "(bad)",  { XX } },
3801     { VEX_LEN_TABLE (VEX_LEN_D5_P_2) },
3802     { "(bad)",  { XX } },
3803   },
3804
3805   /* PREFIX_VEX_D6 */
3806   {
3807     { "(bad)",  { XX } },
3808     { "(bad)",  { XX } },
3809     { VEX_LEN_TABLE (VEX_LEN_D6_P_2) },
3810     { "(bad)",  { XX } },
3811   },
3812
3813   /* PREFIX_VEX_D7 */
3814   {
3815     { "(bad)",  { XX } },
3816     { "(bad)",  { XX } },
3817     { MOD_TABLE (MOD_VEX_D7_PREFIX_2) },
3818     { "(bad)",  { XX } },
3819   },
3820
3821   /* PREFIX_VEX_D8 */
3822   {
3823     { "(bad)",  { XX } },
3824     { "(bad)",  { XX } },
3825     { VEX_LEN_TABLE (VEX_LEN_D8_P_2) },
3826     { "(bad)",  { XX } },
3827   },
3828
3829   /* PREFIX_VEX_D9 */
3830   {
3831     { "(bad)",  { XX } },
3832     { "(bad)",  { XX } },
3833     { VEX_LEN_TABLE (VEX_LEN_D9_P_2) },
3834     { "(bad)",  { XX } },
3835   },
3836
3837   /* PREFIX_VEX_DA */
3838   {
3839     { "(bad)",  { XX } },
3840     { "(bad)",  { XX } },
3841     { VEX_LEN_TABLE (VEX_LEN_DA_P_2) },
3842     { "(bad)",  { XX } },
3843   },
3844
3845   /* PREFIX_VEX_DB */
3846   {
3847     { "(bad)",  { XX } },
3848     { "(bad)",  { XX } },
3849     { VEX_LEN_TABLE (VEX_LEN_DB_P_2) },
3850     { "(bad)",  { XX } },
3851   },
3852
3853   /* PREFIX_VEX_DC */
3854   {
3855     { "(bad)",  { XX } },
3856     { "(bad)",  { XX } },
3857     { VEX_LEN_TABLE (VEX_LEN_DC_P_2) },
3858     { "(bad)",  { XX } },
3859   },
3860
3861   /* PREFIX_VEX_DD */
3862   {
3863     { "(bad)",  { XX } },
3864     { "(bad)",  { XX } },
3865     { VEX_LEN_TABLE (VEX_LEN_DD_P_2) },
3866     { "(bad)",  { XX } },
3867   },
3868
3869   /* PREFIX_VEX_DE */
3870   {
3871     { "(bad)",  { XX } },
3872     { "(bad)",  { XX } },
3873     { VEX_LEN_TABLE (VEX_LEN_DE_P_2) },
3874     { "(bad)",  { XX } },
3875   },
3876
3877   /* PREFIX_VEX_DF */
3878   {
3879     { "(bad)",  { XX } },
3880     { "(bad)",  { XX } },
3881     { VEX_LEN_TABLE (VEX_LEN_DF_P_2) },
3882     { "(bad)",  { XX } },
3883   },
3884
3885   /* PREFIX_VEX_E0 */
3886   {
3887     { "(bad)",  { XX } },
3888     { "(bad)",  { XX } },
3889     { VEX_LEN_TABLE (VEX_LEN_E0_P_2) },
3890     { "(bad)",  { XX } },
3891   },
3892
3893   /* PREFIX_VEX_E1 */
3894   {
3895     { "(bad)",  { XX } },
3896     { "(bad)",  { XX } },
3897     { VEX_LEN_TABLE (VEX_LEN_E1_P_2) },
3898     { "(bad)",  { XX } },
3899   },
3900
3901   /* PREFIX_VEX_E2 */
3902   {
3903     { "(bad)",  { XX } },
3904     { "(bad)",  { XX } },
3905     { VEX_LEN_TABLE (VEX_LEN_E2_P_2) },
3906     { "(bad)",  { XX } },
3907   },
3908
3909   /* PREFIX_VEX_E3 */
3910   {
3911     { "(bad)",  { XX } },
3912     { "(bad)",  { XX } },
3913     { VEX_LEN_TABLE (VEX_LEN_E3_P_2) },
3914     { "(bad)",  { XX } },
3915   },
3916
3917   /* PREFIX_VEX_E4 */
3918   {
3919     { "(bad)",  { XX } },
3920     { "(bad)",  { XX } },
3921     { VEX_LEN_TABLE (VEX_LEN_E4_P_2) },
3922     { "(bad)",  { XX } },
3923   },
3924
3925   /* PREFIX_VEX_E5 */
3926   {
3927     { "(bad)",  { XX } },
3928     { "(bad)",  { XX } },
3929     { VEX_LEN_TABLE (VEX_LEN_E5_P_2) },
3930     { "(bad)",  { XX } },
3931   },
3932
3933   /* PREFIX_VEX_E6 */
3934   {
3935     { "(bad)",  { XX } },
3936     { "vcvtdq2pd", { XM, EXxmmq } },
3937     { "vcvttpd2dq%XY", { XMM, EXx } },
3938     { "vcvtpd2dq%XY", { XMM, EXx } },
3939   },
3940
3941   /* PREFIX_VEX_E7 */
3942   {
3943     { "(bad)",  { XX } },
3944     { "(bad)",  { XX } },
3945     { MOD_TABLE (MOD_VEX_E7_PREFIX_2) },
3946     { "(bad)",  { XX } },
3947   },
3948
3949   /* PREFIX_VEX_E8 */
3950   {
3951     { "(bad)",  { XX } },
3952     { "(bad)",  { XX } },
3953     { VEX_LEN_TABLE (VEX_LEN_E8_P_2) },
3954     { "(bad)",  { XX } },
3955   },
3956
3957   /* PREFIX_VEX_E9 */
3958   {
3959     { "(bad)",  { XX } },
3960     { "(bad)",  { XX } },
3961     { VEX_LEN_TABLE (VEX_LEN_E9_P_2) },
3962     { "(bad)",  { XX } },
3963   },
3964
3965   /* PREFIX_VEX_EA */
3966   {
3967     { "(bad)",  { XX } },
3968     { "(bad)",  { XX } },
3969     { VEX_LEN_TABLE (VEX_LEN_EA_P_2) },
3970     { "(bad)",  { XX } },
3971   },
3972
3973   /* PREFIX_VEX_EB */
3974   {
3975     { "(bad)",  { XX } },
3976     { "(bad)",  { XX } },
3977     { VEX_LEN_TABLE (VEX_LEN_EB_P_2) },
3978     { "(bad)",  { XX } },
3979   },
3980
3981   /* PREFIX_VEX_EC */
3982   {
3983     { "(bad)",  { XX } },
3984     { "(bad)",  { XX } },
3985     { VEX_LEN_TABLE (VEX_LEN_EC_P_2) },
3986     { "(bad)",  { XX } },
3987   },
3988
3989   /* PREFIX_VEX_ED */
3990   {
3991     { "(bad)",  { XX } },
3992     { "(bad)",  { XX } },
3993     { VEX_LEN_TABLE (VEX_LEN_ED_P_2) },
3994     { "(bad)",  { XX } },
3995   },
3996
3997   /* PREFIX_VEX_EE */
3998   {
3999     { "(bad)",  { XX } },
4000     { "(bad)",  { XX } },
4001     { VEX_LEN_TABLE (VEX_LEN_EE_P_2) },
4002     { "(bad)",  { XX } },
4003   },
4004
4005   /* PREFIX_VEX_EF */
4006   {
4007     { "(bad)",  { XX } },
4008     { "(bad)",  { XX } },
4009     { VEX_LEN_TABLE (VEX_LEN_EF_P_2) },
4010     { "(bad)",  { XX } },
4011   },
4012
4013   /* PREFIX_VEX_F0 */
4014   {
4015     { "(bad)",  { XX } },
4016     { "(bad)",  { XX } },
4017     { "(bad)",  { XX } },
4018     { MOD_TABLE (MOD_VEX_F0_PREFIX_3) },
4019   },
4020
4021   /* PREFIX_VEX_F1 */
4022   {
4023     { "(bad)",  { XX } },
4024     { "(bad)",  { XX } },
4025     { VEX_LEN_TABLE (VEX_LEN_F1_P_2) },
4026     { "(bad)",  { XX } },
4027   },
4028
4029   /* PREFIX_VEX_F2 */
4030   {
4031     { "(bad)",  { XX } },
4032     { "(bad)",  { XX } },
4033     { VEX_LEN_TABLE (VEX_LEN_F2_P_2) },
4034     { "(bad)",  { XX } },
4035   },
4036
4037   /* PREFIX_VEX_F3 */
4038   {
4039     { "(bad)",  { XX } },
4040     { "(bad)",  { XX } },
4041     { VEX_LEN_TABLE (VEX_LEN_F3_P_2) },
4042     { "(bad)",  { XX } },
4043   },
4044
4045   /* PREFIX_VEX_F4 */
4046   {
4047     { "(bad)",  { XX } },
4048     { "(bad)",  { XX } },
4049     { VEX_LEN_TABLE (VEX_LEN_F4_P_2) },
4050     { "(bad)",  { XX } },
4051   },
4052
4053   /* PREFIX_VEX_F5 */
4054   {
4055     { "(bad)",  { XX } },
4056     { "(bad)",  { XX } },
4057     { VEX_LEN_TABLE (VEX_LEN_F5_P_2) },
4058     { "(bad)",  { XX } },
4059   },
4060
4061   /* PREFIX_VEX_F6 */
4062   {
4063     { "(bad)",  { XX } },
4064     { "(bad)",  { XX } },
4065     { VEX_LEN_TABLE (VEX_LEN_F6_P_2) },
4066     { "(bad)",  { XX } },
4067   },
4068
4069   /* PREFIX_VEX_F7 */
4070   {
4071     { "(bad)",  { XX } },
4072     { "(bad)",  { XX } },
4073     { VEX_LEN_TABLE (VEX_LEN_F7_P_2) },
4074     { "(bad)",  { XX } },
4075   },
4076
4077   /* PREFIX_VEX_F8 */
4078   {
4079     { "(bad)",  { XX } },
4080     { "(bad)",  { XX } },
4081     { VEX_LEN_TABLE (VEX_LEN_F8_P_2) },
4082     { "(bad)",  { XX } },
4083   },
4084
4085   /* PREFIX_VEX_F9 */
4086   {
4087     { "(bad)",  { XX } },
4088     { "(bad)",  { XX } },
4089     { VEX_LEN_TABLE (VEX_LEN_F9_P_2) },
4090     { "(bad)",  { XX } },
4091   },
4092
4093   /* PREFIX_VEX_FA */
4094   {
4095     { "(bad)",  { XX } },
4096     { "(bad)",  { XX } },
4097     { VEX_LEN_TABLE (VEX_LEN_FA_P_2) },
4098     { "(bad)",  { XX } },
4099   },
4100
4101   /* PREFIX_VEX_FB */
4102   {
4103     { "(bad)",  { XX } },
4104     { "(bad)",  { XX } },
4105     { VEX_LEN_TABLE (VEX_LEN_FB_P_2) },
4106     { "(bad)",  { XX } },
4107   },
4108
4109   /* PREFIX_VEX_FC */
4110   {
4111     { "(bad)",  { XX } },
4112     { "(bad)",  { XX } },
4113     { VEX_LEN_TABLE (VEX_LEN_FC_P_2) },
4114     { "(bad)",  { XX } },
4115   },
4116
4117   /* PREFIX_VEX_FD */
4118   {
4119     { "(bad)",  { XX } },
4120     { "(bad)",  { XX } },
4121     { VEX_LEN_TABLE (VEX_LEN_FD_P_2) },
4122     { "(bad)",  { XX } },
4123   },
4124
4125   /* PREFIX_VEX_FE */
4126   {
4127     { "(bad)",  { XX } },
4128     { "(bad)",  { XX } },
4129     { VEX_LEN_TABLE (VEX_LEN_FE_P_2) },
4130     { "(bad)",  { XX } },
4131   },
4132
4133   /* PREFIX_VEX_3800 */
4134   {
4135     { "(bad)",  { XX } },
4136     { "(bad)",  { XX } },
4137     { VEX_LEN_TABLE (VEX_LEN_3800_P_2) },
4138     { "(bad)",  { XX } },
4139   },
4140
4141   /* PREFIX_VEX_3801 */
4142   {
4143     { "(bad)",  { XX } },
4144     { "(bad)",  { XX } },
4145     { VEX_LEN_TABLE (VEX_LEN_3801_P_2) },
4146     { "(bad)",  { XX } },
4147   },
4148
4149   /* PREFIX_VEX_3802 */
4150   {
4151     { "(bad)",  { XX } },
4152     { "(bad)",  { XX } },
4153     { VEX_LEN_TABLE (VEX_LEN_3802_P_2) },
4154     { "(bad)",  { XX } },
4155   },
4156
4157   /* PREFIX_VEX_3803 */
4158   {
4159     { "(bad)",  { XX } },
4160     { "(bad)",  { XX } },
4161     { VEX_LEN_TABLE (VEX_LEN_3803_P_2) },
4162     { "(bad)",  { XX } },
4163   },
4164
4165   /* PREFIX_VEX_3804 */
4166   {
4167     { "(bad)",  { XX } },
4168     { "(bad)",  { XX } },
4169     { VEX_LEN_TABLE (VEX_LEN_3804_P_2) },
4170     { "(bad)",  { XX } },
4171   },
4172
4173   /* PREFIX_VEX_3805 */
4174   {
4175     { "(bad)",  { XX } },
4176     { "(bad)",  { XX } },
4177     { VEX_LEN_TABLE (VEX_LEN_3805_P_2) },
4178     { "(bad)",  { XX } },
4179   },
4180
4181   /* PREFIX_VEX_3806 */
4182   {
4183     { "(bad)",  { XX } },
4184     { "(bad)",  { XX } },
4185     { VEX_LEN_TABLE (VEX_LEN_3806_P_2) },
4186     { "(bad)",  { XX } },
4187   },
4188
4189   /* PREFIX_VEX_3807 */
4190   {
4191     { "(bad)",  { XX } },
4192     { "(bad)",  { XX } },
4193     { VEX_LEN_TABLE (VEX_LEN_3807_P_2) },
4194     { "(bad)",  { XX } },
4195   },
4196
4197   /* PREFIX_VEX_3808 */
4198   {
4199     { "(bad)",  { XX } },
4200     { "(bad)",  { XX } },
4201     { VEX_LEN_TABLE (VEX_LEN_3808_P_2) },
4202     { "(bad)",  { XX } },
4203   },
4204
4205   /* PREFIX_VEX_3809 */
4206   {
4207     { "(bad)",  { XX } },
4208     { "(bad)",  { XX } },
4209     { VEX_LEN_TABLE (VEX_LEN_3809_P_2) },
4210     { "(bad)",  { XX } },
4211   },
4212
4213   /* PREFIX_VEX_380A */
4214   {
4215     { "(bad)",  { XX } },
4216     { "(bad)",  { XX } },
4217     { VEX_LEN_TABLE (VEX_LEN_380A_P_2) },
4218     { "(bad)",  { XX } },
4219   },
4220
4221   /* PREFIX_VEX_380B */
4222   {
4223     { "(bad)",  { XX } },
4224     { "(bad)",  { XX } },
4225     { VEX_LEN_TABLE (VEX_LEN_380B_P_2) },
4226     { "(bad)",  { XX } },
4227   },
4228
4229   /* PREFIX_VEX_380C */
4230   {
4231     { "(bad)",  { XX } },
4232     { "(bad)",  { XX } },
4233     { "vpermilps", { XM, Vex, EXx } },
4234     { "(bad)",  { XX } },
4235   },
4236
4237   /* PREFIX_VEX_380D */
4238   {
4239     { "(bad)",  { XX } },
4240     { "(bad)",  { XX } },
4241     { "vpermilpd", { XM, Vex, EXx } },
4242     { "(bad)",  { XX } },
4243   },
4244
4245   /* PREFIX_VEX_380E */
4246   {
4247     { "(bad)",  { XX } },
4248     { "(bad)",  { XX } },
4249     { "vtestps", { XM, EXx } },
4250     { "(bad)",  { XX } },
4251   },
4252
4253   /* PREFIX_VEX_380F */
4254   {
4255     { "(bad)",  { XX } },
4256     { "(bad)",  { XX } },
4257     { "vtestpd", { XM, EXx } },
4258     { "(bad)",  { XX } },
4259   },
4260
4261   /* PREFIX_VEX_3817 */
4262   {
4263     { "(bad)",  { XX } },
4264     { "(bad)",  { XX } },
4265     { "vptest", { XM, EXx } },
4266     { "(bad)",  { XX } },
4267   },
4268
4269   /* PREFIX_VEX_3818 */
4270   {
4271     { "(bad)",  { XX } },
4272     { "(bad)",  { XX } },
4273     { MOD_TABLE (MOD_VEX_3818_PREFIX_2) },
4274     { "(bad)",  { XX } },
4275   },
4276
4277   /* PREFIX_VEX_3819 */
4278   {
4279     { "(bad)",  { XX } },
4280     { "(bad)",  { XX } },
4281     { MOD_TABLE (MOD_VEX_3819_PREFIX_2) },
4282     { "(bad)",  { XX } },
4283   },
4284
4285   /* PREFIX_VEX_381A */
4286   {
4287     { "(bad)",  { XX } },
4288     { "(bad)",  { XX } },
4289     { MOD_TABLE (MOD_VEX_381A_PREFIX_2) },
4290     { "(bad)",  { XX } },
4291   },
4292
4293   /* PREFIX_VEX_381C */
4294   {
4295     { "(bad)",  { XX } },
4296     { "(bad)",  { XX } },
4297     { VEX_LEN_TABLE (VEX_LEN_381C_P_2) },
4298     { "(bad)",  { XX } },
4299   },
4300
4301   /* PREFIX_VEX_381D */
4302   {
4303     { "(bad)",  { XX } },
4304     { "(bad)",  { XX } },
4305     { VEX_LEN_TABLE (VEX_LEN_381D_P_2) },
4306     { "(bad)",  { XX } },
4307   },
4308
4309   /* PREFIX_VEX_381E */
4310   {
4311     { "(bad)",  { XX } },
4312     { "(bad)",  { XX } },
4313     { VEX_LEN_TABLE (VEX_LEN_381E_P_2) },
4314     { "(bad)",  { XX } },
4315   },
4316
4317   /* PREFIX_VEX_3820 */
4318   {
4319     { "(bad)",  { XX } },
4320     { "(bad)",  { XX } },
4321     { VEX_LEN_TABLE (VEX_LEN_3820_P_2) },
4322     { "(bad)",  { XX } },
4323   },
4324
4325   /* PREFIX_VEX_3821 */
4326   {
4327     { "(bad)",  { XX } },
4328     { "(bad)",  { XX } },
4329     { VEX_LEN_TABLE (VEX_LEN_3821_P_2) },
4330     { "(bad)",  { XX } },
4331   },
4332
4333   /* PREFIX_VEX_3822 */
4334   {
4335     { "(bad)",  { XX } },
4336     { "(bad)",  { XX } },
4337     { VEX_LEN_TABLE (VEX_LEN_3822_P_2) },
4338     { "(bad)",  { XX } },
4339   },
4340
4341   /* PREFIX_VEX_3823 */
4342   {
4343     { "(bad)",  { XX } },
4344     { "(bad)",  { XX } },
4345     { VEX_LEN_TABLE (VEX_LEN_3823_P_2) },
4346     { "(bad)",  { XX } },
4347   },
4348
4349   /* PREFIX_VEX_3824 */
4350   {
4351     { "(bad)",  { XX } },
4352     { "(bad)",  { XX } },
4353     { VEX_LEN_TABLE (VEX_LEN_3824_P_2) },
4354     { "(bad)",  { XX } },
4355   },
4356
4357   /* PREFIX_VEX_3825 */
4358   {
4359     { "(bad)",  { XX } },
4360     { "(bad)",  { XX } },
4361     { VEX_LEN_TABLE (VEX_LEN_3825_P_2) },
4362     { "(bad)",  { XX } },
4363   },
4364
4365   /* PREFIX_VEX_3828 */
4366   {
4367     { "(bad)",  { XX } },
4368     { "(bad)",  { XX } },
4369     { VEX_LEN_TABLE (VEX_LEN_3828_P_2) },
4370     { "(bad)",  { XX } },
4371   },
4372
4373   /* PREFIX_VEX_3829 */
4374   {
4375     { "(bad)",  { XX } },
4376     { "(bad)",  { XX } },
4377     { VEX_LEN_TABLE (VEX_LEN_3829_P_2) },
4378     { "(bad)",  { XX } },
4379   },
4380
4381   /* PREFIX_VEX_382A */
4382   {
4383     { "(bad)",  { XX } },
4384     { "(bad)",  { XX } },
4385     { MOD_TABLE (MOD_VEX_382A_PREFIX_2) },
4386     { "(bad)",  { XX } },
4387   },
4388
4389   /* PREFIX_VEX_382B */
4390   {
4391     { "(bad)",  { XX } },
4392     { "(bad)",  { XX } },
4393     { VEX_LEN_TABLE (VEX_LEN_382B_P_2) },
4394     { "(bad)",  { XX } },
4395   },
4396
4397   /* PREFIX_VEX_382C */
4398   {
4399     { "(bad)",  { XX } },
4400     { "(bad)",  { XX } },
4401      { MOD_TABLE (MOD_VEX_382C_PREFIX_2) },
4402     { "(bad)",  { XX } },
4403   },
4404
4405   /* PREFIX_VEX_382D */
4406   {
4407     { "(bad)",  { XX } },
4408     { "(bad)",  { XX } },
4409      { MOD_TABLE (MOD_VEX_382D_PREFIX_2) },
4410     { "(bad)",  { XX } },
4411   },
4412
4413   /* PREFIX_VEX_382E */
4414   {
4415     { "(bad)",  { XX } },
4416     { "(bad)",  { XX } },
4417      { MOD_TABLE (MOD_VEX_382E_PREFIX_2) },
4418     { "(bad)",  { XX } },
4419   },
4420
4421   /* PREFIX_VEX_382F */
4422   {
4423     { "(bad)",  { XX } },
4424     { "(bad)",  { XX } },
4425      { MOD_TABLE (MOD_VEX_382F_PREFIX_2) },
4426     { "(bad)",  { XX } },
4427   },
4428
4429   /* PREFIX_VEX_3830 */
4430   {
4431     { "(bad)",  { XX } },
4432     { "(bad)",  { XX } },
4433     { VEX_LEN_TABLE (VEX_LEN_3830_P_2) },
4434     { "(bad)",  { XX } },
4435   },
4436
4437   /* PREFIX_VEX_3831 */
4438   {
4439     { "(bad)",  { XX } },
4440     { "(bad)",  { XX } },
4441     { VEX_LEN_TABLE (VEX_LEN_3831_P_2) },
4442     { "(bad)",  { XX } },
4443   },
4444
4445   /* PREFIX_VEX_3832 */
4446   {
4447     { "(bad)",  { XX } },
4448     { "(bad)",  { XX } },
4449     { VEX_LEN_TABLE (VEX_LEN_3832_P_2) },
4450     { "(bad)",  { XX } },
4451   },
4452
4453   /* PREFIX_VEX_3833 */
4454   {
4455     { "(bad)",  { XX } },
4456     { "(bad)",  { XX } },
4457     { VEX_LEN_TABLE (VEX_LEN_3833_P_2) },
4458     { "(bad)",  { XX } },
4459   },
4460
4461   /* PREFIX_VEX_3834 */
4462   {
4463     { "(bad)",  { XX } },
4464     { "(bad)",  { XX } },
4465     { VEX_LEN_TABLE (VEX_LEN_3834_P_2) },
4466     { "(bad)",  { XX } },
4467   },
4468
4469   /* PREFIX_VEX_3835 */
4470   {
4471     { "(bad)",  { XX } },
4472     { "(bad)",  { XX } },
4473     { VEX_LEN_TABLE (VEX_LEN_3835_P_2) },
4474     { "(bad)",  { XX } },
4475   },
4476
4477   /* PREFIX_VEX_3837 */
4478   {
4479     { "(bad)",  { XX } },
4480     { "(bad)",  { XX } },
4481     { VEX_LEN_TABLE (VEX_LEN_3837_P_2) },
4482     { "(bad)",  { XX } },
4483   },
4484
4485   /* PREFIX_VEX_3838 */
4486   {
4487     { "(bad)",  { XX } },
4488     { "(bad)",  { XX } },
4489     { VEX_LEN_TABLE (VEX_LEN_3838_P_2) },
4490     { "(bad)",  { XX } },
4491   },
4492
4493   /* PREFIX_VEX_3839 */
4494   {
4495     { "(bad)",  { XX } },
4496     { "(bad)",  { XX } },
4497     { VEX_LEN_TABLE (VEX_LEN_3839_P_2) },
4498     { "(bad)",  { XX } },
4499   },
4500
4501   /* PREFIX_VEX_383A */
4502   {
4503     { "(bad)",  { XX } },
4504     { "(bad)",  { XX } },
4505     { VEX_LEN_TABLE (VEX_LEN_383A_P_2) },
4506     { "(bad)",  { XX } },
4507   },
4508
4509   /* PREFIX_VEX_383B */
4510   {
4511     { "(bad)",  { XX } },
4512     { "(bad)",  { XX } },
4513     { VEX_LEN_TABLE (VEX_LEN_383B_P_2) },
4514     { "(bad)",  { XX } },
4515   },
4516
4517   /* PREFIX_VEX_383C */
4518   {
4519     { "(bad)",  { XX } },
4520     { "(bad)",  { XX } },
4521     { VEX_LEN_TABLE (VEX_LEN_383C_P_2) },
4522     { "(bad)",  { XX } },
4523   },
4524
4525   /* PREFIX_VEX_383D */
4526   {
4527     { "(bad)",  { XX } },
4528     { "(bad)",  { XX } },
4529     { VEX_LEN_TABLE (VEX_LEN_383D_P_2) },
4530     { "(bad)",  { XX } },
4531   },
4532
4533   /* PREFIX_VEX_383E */
4534   {
4535     { "(bad)",  { XX } },
4536     { "(bad)",  { XX } },
4537     { VEX_LEN_TABLE (VEX_LEN_383E_P_2) },
4538     { "(bad)",  { XX } },
4539   },
4540
4541   /* PREFIX_VEX_383F */
4542   {
4543     { "(bad)",  { XX } },
4544     { "(bad)",  { XX } },
4545     { VEX_LEN_TABLE (VEX_LEN_383F_P_2) },
4546     { "(bad)",  { XX } },
4547   },
4548
4549   /* PREFIX_VEX_3840 */
4550   {
4551     { "(bad)",  { XX } },
4552     { "(bad)",  { XX } },
4553     { VEX_LEN_TABLE (VEX_LEN_3840_P_2) },
4554     { "(bad)",  { XX } },
4555   },
4556
4557   /* PREFIX_VEX_3841 */
4558   {
4559     { "(bad)",  { XX } },
4560     { "(bad)",  { XX } },
4561     { VEX_LEN_TABLE (VEX_LEN_3841_P_2) },
4562     { "(bad)",  { XX } },
4563   },
4564
4565   /* PREFIX_VEX_3896 */
4566   {
4567     { "(bad)",  { XX } },
4568     { "(bad)",  { XX } },
4569     { "vfmaddsub132p%XW", { XM, Vex, EXx } },
4570     { "(bad)",  { XX } },
4571   },
4572
4573   /* PREFIX_VEX_3897 */
4574   {
4575     { "(bad)",  { XX } },
4576     { "(bad)",  { XX } },
4577     { "vfmsubadd132p%XW", { XM, Vex, EXx } },
4578     { "(bad)",  { XX } },
4579   },
4580
4581   /* PREFIX_VEX_3898 */
4582   {
4583     { "(bad)",  { XX } },
4584     { "(bad)",  { XX } },
4585     { "vfmadd132p%XW", { XM, Vex, EXx } },
4586     { "(bad)",  { XX } },
4587   },
4588
4589   /* PREFIX_VEX_3899 */
4590   {
4591     { "(bad)",  { XX } },
4592     { "(bad)",  { XX } },
4593     { "vfmadd132s%XW", { XM, Vex, EXVexWdq } },
4594     { "(bad)",  { XX } },
4595   },
4596
4597   /* PREFIX_VEX_389A */
4598   {
4599     { "(bad)",  { XX } },
4600     { "(bad)",  { XX } },
4601     { "vfmsub132p%XW", { XM, Vex, EXx } },
4602     { "(bad)",  { XX } },
4603   },
4604
4605   /* PREFIX_VEX_389B */
4606   {
4607     { "(bad)",  { XX } },
4608     { "(bad)",  { XX } },
4609     { "vfmsub132s%XW", { XM, Vex, EXVexWdq } },
4610     { "(bad)",  { XX } },
4611   },
4612
4613   /* PREFIX_VEX_389C */
4614   {
4615     { "(bad)",  { XX } },
4616     { "(bad)",  { XX } },
4617     { "vfnmadd132p%XW", { XM, Vex, EXx } },
4618     { "(bad)",  { XX } },
4619   },
4620
4621   /* PREFIX_VEX_389D */
4622   {
4623     { "(bad)",  { XX } },
4624     { "(bad)",  { XX } },
4625     { "vfnmadd132s%XW", { XM, Vex, EXVexWdq } },
4626     { "(bad)",  { XX } },
4627   },
4628
4629   /* PREFIX_VEX_389E */
4630   {
4631     { "(bad)",  { XX } },
4632     { "(bad)",  { XX } },
4633     { "vfnmsub132p%XW", { XM, Vex, EXx } },
4634     { "(bad)",  { XX } },
4635   },
4636
4637   /* PREFIX_VEX_389F */
4638   {
4639     { "(bad)",  { XX } },
4640     { "(bad)",  { XX } },
4641     { "vfnmsub132s%XW", { XM, Vex, EXVexWdq } },
4642     { "(bad)",  { XX } },
4643   },
4644
4645   /* PREFIX_VEX_38A6 */
4646   {
4647     { "(bad)",  { XX } },
4648     { "(bad)",  { XX } },
4649     { "vfmaddsub213p%XW", { XM, Vex, EXx } },
4650     { "(bad)",  { XX } },
4651   },
4652
4653   /* PREFIX_VEX_38A7 */
4654   {
4655     { "(bad)",  { XX } },
4656     { "(bad)",  { XX } },
4657     { "vfmsubadd213p%XW", { XM, Vex, EXx } },
4658     { "(bad)",  { XX } },
4659   },
4660
4661   /* PREFIX_VEX_38A8 */
4662   {
4663     { "(bad)",  { XX } },
4664     { "(bad)",  { XX } },
4665     { "vfmadd213p%XW", { XM, Vex, EXx } },
4666     { "(bad)",  { XX } },
4667   },
4668
4669   /* PREFIX_VEX_38A9 */
4670   {
4671     { "(bad)",  { XX } },
4672     { "(bad)",  { XX } },
4673     { "vfmadd213s%XW", { XM, Vex, EXVexWdq } },
4674     { "(bad)",  { XX } },
4675   },
4676
4677   /* PREFIX_VEX_38AA */
4678   {
4679     { "(bad)",  { XX } },
4680     { "(bad)",  { XX } },
4681     { "vfmsub213p%XW", { XM, Vex, EXx } },
4682     { "(bad)",  { XX } },
4683   },
4684
4685   /* PREFIX_VEX_38AB */
4686   {
4687     { "(bad)",  { XX } },
4688     { "(bad)",  { XX } },
4689     { "vfmsub213s%XW", { XM, Vex, EXVexWdq } },
4690     { "(bad)",  { XX } },
4691   },
4692
4693   /* PREFIX_VEX_38AC */
4694   {
4695     { "(bad)",  { XX } },
4696     { "(bad)",  { XX } },
4697     { "vfnmadd213p%XW", { XM, Vex, EXx } },
4698     { "(bad)",  { XX } },
4699   },
4700
4701   /* PREFIX_VEX_38AD */
4702   {
4703     { "(bad)",  { XX } },
4704     { "(bad)",  { XX } },
4705     { "vfnmadd213s%XW", { XM, Vex, EXVexWdq } },
4706     { "(bad)",  { XX } },
4707   },
4708
4709   /* PREFIX_VEX_38AE */
4710   {
4711     { "(bad)",  { XX } },
4712     { "(bad)",  { XX } },
4713     { "vfnmsub213p%XW", { XM, Vex, EXx } },
4714     { "(bad)",  { XX } },
4715   },
4716
4717   /* PREFIX_VEX_38AF */
4718   {
4719     { "(bad)",  { XX } },
4720     { "(bad)",  { XX } },
4721     { "vfnmsub213s%XW", { XM, Vex, EXVexWdq } },
4722     { "(bad)",  { XX } },
4723   },
4724
4725   /* PREFIX_VEX_38B6 */
4726   {
4727     { "(bad)",  { XX } },
4728     { "(bad)",  { XX } },
4729     { "vfmaddsub231p%XW", { XM, Vex, EXx } },
4730     { "(bad)",  { XX } },
4731   },
4732
4733   /* PREFIX_VEX_38B7 */
4734   {
4735     { "(bad)",  { XX } },
4736     { "(bad)",  { XX } },
4737     { "vfmsubadd231p%XW", { XM, Vex, EXx } },
4738     { "(bad)",  { XX } },
4739   },
4740
4741   /* PREFIX_VEX_38B8 */
4742   {
4743     { "(bad)",  { XX } },
4744     { "(bad)",  { XX } },
4745     { "vfmadd231p%XW", { XM, Vex, EXx } },
4746     { "(bad)",  { XX } },
4747   },
4748
4749   /* PREFIX_VEX_38B9 */
4750   {
4751     { "(bad)",  { XX } },
4752     { "(bad)",  { XX } },
4753     { "vfmadd231s%XW", { XM, Vex, EXVexWdq } },
4754     { "(bad)",  { XX } },
4755   },
4756
4757   /* PREFIX_VEX_38BA */
4758   {
4759     { "(bad)",  { XX } },
4760     { "(bad)",  { XX } },
4761     { "vfmsub231p%XW", { XM, Vex, EXx } },
4762     { "(bad)",  { XX } },
4763   },
4764
4765   /* PREFIX_VEX_38BB */
4766   {
4767     { "(bad)",  { XX } },
4768     { "(bad)",  { XX } },
4769     { "vfmsub231s%XW", { XM, Vex, EXVexWdq } },
4770     { "(bad)",  { XX } },
4771   },
4772
4773   /* PREFIX_VEX_38BC */
4774   {
4775     { "(bad)",  { XX } },
4776     { "(bad)",  { XX } },
4777     { "vfnmadd231p%XW", { XM, Vex, EXx } },
4778     { "(bad)",  { XX } },
4779   },
4780
4781   /* PREFIX_VEX_38BD */
4782   {
4783     { "(bad)",  { XX } },
4784     { "(bad)",  { XX } },
4785     { "vfnmadd231s%XW", { XM, Vex, EXVexWdq } },
4786     { "(bad)",  { XX } },
4787   },
4788
4789   /* PREFIX_VEX_38BE */
4790   {
4791     { "(bad)",  { XX } },
4792     { "(bad)",  { XX } },
4793     { "vfnmsub231p%XW", { XM, Vex, EXx } },
4794     { "(bad)",  { XX } },
4795   },
4796
4797   /* PREFIX_VEX_38BF */
4798   {
4799     { "(bad)",  { XX } },
4800     { "(bad)",  { XX } },
4801     { "vfnmsub231s%XW", { XM, Vex, EXVexWdq } },
4802     { "(bad)",  { XX } },
4803   },
4804
4805   /* PREFIX_VEX_38DB */
4806   {
4807     { "(bad)",  { XX } },
4808     { "(bad)",  { XX } },
4809     { VEX_LEN_TABLE (VEX_LEN_38DB_P_2) },
4810     { "(bad)",  { XX } },
4811   },
4812
4813   /* PREFIX_VEX_38DC */
4814   {
4815     { "(bad)",  { XX } },
4816     { "(bad)",  { XX } },
4817     { VEX_LEN_TABLE (VEX_LEN_38DC_P_2) },
4818     { "(bad)",  { XX } },
4819   },
4820
4821   /* PREFIX_VEX_38DD */
4822   {
4823     { "(bad)",  { XX } },
4824     { "(bad)",  { XX } },
4825     { VEX_LEN_TABLE (VEX_LEN_38DD_P_2) },
4826     { "(bad)",  { XX } },
4827   },
4828
4829   /* PREFIX_VEX_38DE */
4830   {
4831     { "(bad)",  { XX } },
4832     { "(bad)",  { XX } },
4833     { VEX_LEN_TABLE (VEX_LEN_38DE_P_2) },
4834     { "(bad)",  { XX } },
4835   },
4836
4837   /* PREFIX_VEX_38DF */
4838   {
4839     { "(bad)",  { XX } },
4840     { "(bad)",  { XX } },
4841     { VEX_LEN_TABLE (VEX_LEN_38DF_P_2) },
4842     { "(bad)",  { XX } },
4843   },
4844
4845   /* PREFIX_VEX_3A04 */
4846   {
4847     { "(bad)",  { XX } },
4848     { "(bad)",  { XX } },
4849     { "vpermilps", { XM, EXx, Ib } },
4850     { "(bad)",  { XX } },
4851   },
4852
4853   /* PREFIX_VEX_3A05 */
4854   {
4855     { "(bad)",  { XX } },
4856     { "(bad)",  { XX } },
4857     { "vpermilpd", { XM, EXx, Ib } },
4858     { "(bad)",  { XX } },
4859   },
4860
4861   /* PREFIX_VEX_3A06 */
4862   {
4863     { "(bad)",  { XX } },
4864     { "(bad)",  { XX } },
4865     { VEX_LEN_TABLE (VEX_LEN_3A06_P_2) },
4866     { "(bad)",  { XX } },
4867   },
4868
4869   /* PREFIX_VEX_3A08 */
4870   {
4871     { "(bad)",  { XX } },
4872     { "(bad)",  { XX } },
4873     { "vroundps", { XM, EXx, Ib } },
4874     { "(bad)",  { XX } },
4875   },
4876
4877   /* PREFIX_VEX_3A09 */
4878   {
4879     { "(bad)",  { XX } },
4880     { "(bad)",  { XX } },
4881     { "vroundpd", { XM, EXx, Ib } },
4882     { "(bad)",  { XX } },
4883   },
4884
4885   /* PREFIX_VEX_3A0A */
4886   {
4887     { "(bad)",  { XX } },
4888     { "(bad)",  { XX } },
4889     { VEX_LEN_TABLE (VEX_LEN_3A0A_P_2) },
4890     { "(bad)",  { XX } },
4891   },
4892
4893   /* PREFIX_VEX_3A0B */
4894   {
4895     { "(bad)",  { XX } },
4896     { "(bad)",  { XX } },
4897     { VEX_LEN_TABLE (VEX_LEN_3A0B_P_2) },
4898     { "(bad)",  { XX } },
4899   },
4900
4901   /* PREFIX_VEX_3A0C */
4902   {
4903     { "(bad)",  { XX } },
4904     { "(bad)",  { XX } },
4905     { "vblendps", { XM, Vex, EXx, Ib } },
4906     { "(bad)",  { XX } },
4907   },
4908
4909   /* PREFIX_VEX_3A0D */
4910   {
4911     { "(bad)",  { XX } },
4912     { "(bad)",  { XX } },
4913     { "vblendpd", { XM, Vex, EXx, Ib } },
4914     { "(bad)",  { XX } },
4915   },
4916
4917   /* PREFIX_VEX_3A0E */
4918   {
4919     { "(bad)",  { XX } },
4920     { "(bad)",  { XX } },
4921     { VEX_LEN_TABLE (VEX_LEN_3A0E_P_2) },
4922     { "(bad)",  { XX } },
4923   },
4924
4925   /* PREFIX_VEX_3A0F */
4926   {
4927     { "(bad)",  { XX } },
4928     { "(bad)",  { XX } },
4929     { VEX_LEN_TABLE (VEX_LEN_3A0F_P_2) },
4930     { "(bad)",  { XX } },
4931   },
4932
4933   /* PREFIX_VEX_3A14 */
4934   {
4935     { "(bad)",  { XX } },
4936     { "(bad)",  { XX } },
4937     { VEX_LEN_TABLE (VEX_LEN_3A14_P_2) },
4938     { "(bad)",  { XX } },
4939   },
4940
4941   /* PREFIX_VEX_3A15 */
4942   {
4943     { "(bad)",  { XX } },
4944     { "(bad)",  { XX } },
4945     { VEX_LEN_TABLE (VEX_LEN_3A15_P_2) },
4946     { "(bad)",  { XX } },
4947   },
4948
4949   /* PREFIX_VEX_3A16 */
4950   {
4951     { "(bad)",  { XX } },
4952     { "(bad)",  { XX } },
4953     { VEX_LEN_TABLE (VEX_LEN_3A16_P_2) },
4954     { "(bad)",  { XX } },
4955   },
4956
4957   /* PREFIX_VEX_3A17 */
4958   {
4959     { "(bad)",  { XX } },
4960     { "(bad)",  { XX } },
4961     { VEX_LEN_TABLE (VEX_LEN_3A17_P_2) },
4962     { "(bad)",  { XX } },
4963   },
4964
4965   /* PREFIX_VEX_3A18 */
4966   {
4967     { "(bad)",  { XX } },
4968     { "(bad)",  { XX } },
4969     { VEX_LEN_TABLE (VEX_LEN_3A18_P_2) },
4970     { "(bad)",  { XX } },
4971   },
4972
4973   /* PREFIX_VEX_3A19 */
4974   {
4975     { "(bad)",  { XX } },
4976     { "(bad)",  { XX } },
4977     { VEX_LEN_TABLE (VEX_LEN_3A19_P_2) },
4978     { "(bad)",  { XX } },
4979   },
4980
4981   /* PREFIX_VEX_3A20 */
4982   {
4983     { "(bad)",  { XX } },
4984     { "(bad)",  { XX } },
4985     { VEX_LEN_TABLE (VEX_LEN_3A20_P_2) },
4986     { "(bad)",  { XX } },
4987   },
4988
4989   /* PREFIX_VEX_3A21 */
4990   {
4991     { "(bad)",  { XX } },
4992     { "(bad)",  { XX } },
4993     { VEX_LEN_TABLE (VEX_LEN_3A21_P_2) },
4994     { "(bad)",  { XX } },
4995   },
4996
4997   /* PREFIX_VEX_3A22 */
4998   {
4999     { "(bad)",  { XX } },
5000     { "(bad)",  { XX } },
5001     { VEX_LEN_TABLE (VEX_LEN_3A22_P_2) },
5002     { "(bad)",  { XX } },
5003   },
5004
5005   /* PREFIX_VEX_3A40 */
5006   {
5007     { "(bad)",  { XX } },
5008     { "(bad)",  { XX } },
5009     { "vdpps",  { XM, Vex, EXx, Ib } },
5010     { "(bad)",  { XX } },
5011   },
5012
5013   /* PREFIX_VEX_3A41 */
5014   {
5015     { "(bad)",  { XX } },
5016     { "(bad)",  { XX } },
5017     { VEX_LEN_TABLE (VEX_LEN_3A41_P_2) },
5018     { "(bad)",  { XX } },
5019   },
5020
5021   /* PREFIX_VEX_3A42 */
5022   {
5023     { "(bad)",  { XX } },
5024     { "(bad)",  { XX } },
5025     { VEX_LEN_TABLE (VEX_LEN_3A42_P_2) },
5026     { "(bad)",  { XX } },
5027   },
5028
5029   /* PREFIX_VEX_3A44 */
5030   {
5031     { "(bad)",  { XX } },
5032     { "(bad)",  { XX } },
5033     { VEX_LEN_TABLE (VEX_LEN_3A44_P_2) },
5034     { "(bad)",  { XX } },
5035   },
5036
5037   /* PREFIX_VEX_3A4A */
5038   {
5039     { "(bad)",  { XX } },
5040     { "(bad)",  { XX } },
5041     { "vblendvps", { XM, Vex, EXx, XMVexI4 } },
5042     { "(bad)",  { XX } },
5043   },
5044
5045   /* PREFIX_VEX_3A4B */
5046   {
5047     { "(bad)",  { XX } },
5048     { "(bad)",  { XX } },
5049     { "vblendvpd", { XM, Vex, EXx, XMVexI4 } },
5050     { "(bad)",  { XX } },
5051   },
5052
5053   /* PREFIX_VEX_3A4C */
5054   {
5055     { "(bad)",  { XX } },
5056     { "(bad)",  { XX } },
5057     { VEX_LEN_TABLE (VEX_LEN_3A4C_P_2) },
5058     { "(bad)",  { XX } },
5059   },
5060
5061   /* PREFIX_VEX_3A60 */
5062   {
5063     { "(bad)",  { XX } },
5064     { "(bad)",  { XX } },
5065     { VEX_LEN_TABLE (VEX_LEN_3A60_P_2) },
5066     { "(bad)",  { XX } },
5067   },
5068
5069   /* PREFIX_VEX_3A61 */
5070   {
5071     { "(bad)",  { XX } },
5072     { "(bad)",  { XX } },
5073     { VEX_LEN_TABLE (VEX_LEN_3A61_P_2) },
5074     { "(bad)",  { XX } },
5075   },
5076
5077   /* PREFIX_VEX_3A62 */
5078   {
5079     { "(bad)",  { XX } },
5080     { "(bad)",  { XX } },
5081     { VEX_LEN_TABLE (VEX_LEN_3A62_P_2) },
5082     { "(bad)",  { XX } },
5083   },
5084
5085   /* PREFIX_VEX_3A63 */
5086   {
5087     { "(bad)",  { XX } },
5088     { "(bad)",  { XX } },
5089     { VEX_LEN_TABLE (VEX_LEN_3A63_P_2) },
5090     { "(bad)",  { XX } },
5091   },
5092
5093   /* PREFIX_VEX_3ADF */
5094   {
5095     { "(bad)",  { XX } },
5096     { "(bad)",  { XX } },
5097     { VEX_LEN_TABLE (VEX_LEN_3ADF_P_2) },
5098     { "(bad)",  { XX } },
5099   },
5100 };
5101
5102 static const struct dis386 x86_64_table[][2] = {
5103   /* X86_64_06 */
5104   {
5105     { "push{T|}", { es } },
5106     { "(bad)", { XX } },
5107   },
5108
5109   /* X86_64_07 */
5110   {
5111     { "pop{T|}", { es } },
5112     { "(bad)", { XX } },
5113   },
5114
5115   /* X86_64_0D */
5116   {
5117     { "push{T|}", { cs } },
5118     { "(bad)", { XX } },
5119   },
5120
5121   /* X86_64_16 */
5122   {
5123     { "push{T|}", { ss } },
5124     { "(bad)", { XX } },
5125   },
5126
5127   /* X86_64_17 */
5128   {
5129     { "pop{T|}", { ss } },
5130     { "(bad)", { XX } },
5131   },
5132
5133   /* X86_64_1E */
5134   {
5135     { "push{T|}", { ds } },
5136     { "(bad)", { XX } },
5137   },
5138
5139   /* X86_64_1F */
5140   {
5141     { "pop{T|}", { ds } },
5142     { "(bad)", { XX } },
5143   },
5144
5145   /* X86_64_27 */
5146   {
5147     { "daa", { XX } },
5148     { "(bad)", { XX } },
5149   },
5150
5151   /* X86_64_2F */
5152   {
5153     { "das", { XX } },
5154     { "(bad)", { XX } },
5155   },
5156
5157   /* X86_64_37 */
5158   {
5159     { "aaa", { XX } },
5160     { "(bad)", { XX } },
5161   },
5162
5163   /* X86_64_3F */
5164   {
5165     { "aas", { XX } },
5166     { "(bad)", { XX } },
5167   },
5168
5169   /* X86_64_60 */
5170   {
5171     { "pusha{P|}", { XX } },
5172     { "(bad)", { XX } },
5173   },
5174
5175   /* X86_64_61 */
5176   {
5177     { "popa{P|}", { XX } },
5178     { "(bad)", { XX } },
5179   },
5180
5181   /* X86_64_62 */
5182   {
5183     { MOD_TABLE (MOD_62_32BIT) },
5184     { "(bad)", { XX } },
5185   },
5186
5187   /* X86_64_63 */
5188   {
5189     { "arpl", { Ew, Gw } },
5190     { "movs{lq|xd}", { Gv, Ed } },
5191   },
5192
5193   /* X86_64_6D */
5194   {
5195     { "ins{R|}", { Yzr, indirDX } },
5196     { "ins{G|}", { Yzr, indirDX } },
5197   },
5198
5199   /* X86_64_6F */
5200   {
5201     { "outs{R|}", { indirDXr, Xz } },
5202     { "outs{G|}", { indirDXr, Xz } },
5203   },
5204
5205   /* X86_64_9A */
5206   {
5207     { "Jcall{T|}", { Ap } },
5208     { "(bad)", { XX } },
5209   },
5210
5211   /* X86_64_C4 */
5212   {
5213     { MOD_TABLE (MOD_C4_32BIT) },
5214     { VEX_C4_TABLE (VEX_0F) },
5215   },
5216
5217   /* X86_64_C5 */
5218   {
5219     { MOD_TABLE (MOD_C5_32BIT) },
5220     { VEX_C5_TABLE (VEX_0F) },
5221   },
5222
5223   /* X86_64_CE */
5224   {
5225     { "into", { XX } },
5226     { "(bad)", { XX } },
5227   },
5228
5229   /* X86_64_D4 */
5230   {
5231     { "aam", { sIb } },
5232     { "(bad)", { XX } },
5233   },
5234
5235   /* X86_64_D5 */
5236   {
5237     { "aad", { sIb } },
5238     { "(bad)", { XX } },
5239   },
5240
5241   /* X86_64_EA */
5242   {
5243     { "Jjmp{T|}", { Ap } },
5244     { "(bad)", { XX } },
5245   },
5246
5247   /* X86_64_0F01_REG_0 */
5248   {
5249     { "sgdt{Q|IQ}", { M } },
5250     { "sgdt", { M } },
5251   },
5252
5253   /* X86_64_0F01_REG_1 */
5254   {
5255     { "sidt{Q|IQ}", { M } },
5256     { "sidt", { M } },
5257   },
5258
5259   /* X86_64_0F01_REG_2 */
5260   {
5261     { "lgdt{Q|Q}", { M } },
5262     { "lgdt", { M } },
5263   },
5264
5265   /* X86_64_0F01_REG_3 */
5266   {
5267     { "lidt{Q|Q}", { M } },
5268     { "lidt", { M } },
5269   },
5270 };
5271
5272 static const struct dis386 three_byte_table[][256] = {
5273   /* THREE_BYTE_0F24 */
5274   {
5275     /* 00 */
5276     { "fmaddps",        { { OP_DREX4, q_mode } } },
5277     { "fmaddpd",        { { OP_DREX4, q_mode } } },
5278     { "fmaddss",        { { OP_DREX4, w_mode } } },
5279     { "fmaddsd",        { { OP_DREX4, d_mode } } },
5280     { "fmaddps",        { { OP_DREX4, DREX_OC1 + q_mode } } },
5281     { "fmaddpd",        { { OP_DREX4, DREX_OC1 + q_mode } } },
5282     { "fmaddss",        { { OP_DREX4, DREX_OC1 + w_mode } } },
5283     { "fmaddsd",        { { OP_DREX4, DREX_OC1 + d_mode } } },
5284     /* 08 */
5285     { "fmsubps",        { { OP_DREX4, q_mode } } },
5286     { "fmsubpd",        { { OP_DREX4, q_mode } } },
5287     { "fmsubss",        { { OP_DREX4, w_mode } } },
5288     { "fmsubsd",        { { OP_DREX4, d_mode } } },
5289     { "fmsubps",        { { OP_DREX4, DREX_OC1 + q_mode } } },
5290     { "fmsubpd",        { { OP_DREX4, DREX_OC1 + q_mode } } },
5291     { "fmsubss",        { { OP_DREX4, DREX_OC1 + w_mode } } },
5292     { "fmsubsd",        { { OP_DREX4, DREX_OC1 + d_mode } } },
5293     /* 10 */
5294     { "fnmaddps",       { { OP_DREX4, q_mode } } },
5295     { "fnmaddpd",       { { OP_DREX4, q_mode } } },
5296     { "fnmaddss",       { { OP_DREX4, w_mode } } },
5297     { "fnmaddsd",       { { OP_DREX4, d_mode } } },
5298     { "fnmaddps",       { { OP_DREX4, DREX_OC1 + q_mode } } },
5299     { "fnmaddpd",       { { OP_DREX4, DREX_OC1 + q_mode } } },
5300     { "fnmaddss",       { { OP_DREX4, DREX_OC1 + w_mode } } },
5301     { "fnmaddsd",       { { OP_DREX4, DREX_OC1 + d_mode } } },
5302     /* 18 */
5303     { "fnmsubps",       { { OP_DREX4, q_mode } } },
5304     { "fnmsubpd",       { { OP_DREX4, q_mode } } },
5305     { "fnmsubss",       { { OP_DREX4, w_mode } } },
5306     { "fnmsubsd",       { { OP_DREX4, d_mode } } },
5307     { "fnmsubps",       { { OP_DREX4, DREX_OC1 + q_mode } } },
5308     { "fnmsubpd",       { { OP_DREX4, DREX_OC1 + q_mode } } },
5309     { "fnmsubss",       { { OP_DREX4, DREX_OC1 + w_mode } } },
5310     { "fnmsubsd",       { { OP_DREX4, DREX_OC1 + d_mode } } },
5311     /* 20 */
5312     { "permps",         { { OP_DREX4, q_mode } } },
5313     { "permpd",         { { OP_DREX4, q_mode } } },
5314     { "pcmov",          { { OP_DREX4, q_mode } } },
5315     { "pperm",          { { OP_DREX4, q_mode } } },
5316     { "permps",         { { OP_DREX4, DREX_OC1 + q_mode } } },
5317     { "permpd",         { { OP_DREX4, DREX_OC1 + q_mode } } },
5318     { "pcmov",          { { OP_DREX4, DREX_OC1 + w_mode } } },
5319     { "pperm",          { { OP_DREX4, DREX_OC1 + d_mode } } },
5320     /* 28 */
5321     { "(bad)",          { XX } },
5322     { "(bad)",          { XX } },
5323     { "(bad)",          { XX } },
5324     { "(bad)",          { XX } },
5325     { "(bad)",          { XX } },
5326     { "(bad)",          { XX } },
5327     { "(bad)",          { XX } },
5328     { "(bad)",          { XX } },
5329     /* 30 */
5330     { "(bad)",          { XX } },
5331     { "(bad)",          { XX } },
5332     { "(bad)",          { XX } },
5333     { "(bad)",          { XX } },
5334     { "(bad)",          { XX } },
5335     { "(bad)",          { XX } },
5336     { "(bad)",          { XX } },
5337     { "(bad)",          { XX } },
5338     /* 38 */
5339     { "(bad)",          { XX } },
5340     { "(bad)",          { XX } },
5341     { "(bad)",          { XX } },
5342     { "(bad)",          { XX } },
5343     { "(bad)",          { XX } },
5344     { "(bad)",          { XX } },
5345     { "(bad)",          { XX } },
5346     { "(bad)",          { XX } },
5347     /* 40 */
5348     { "protb",          { { OP_DREX3, q_mode } } },
5349     { "protw",          { { OP_DREX3, q_mode } } },
5350     { "protd",          { { OP_DREX3, q_mode } } },
5351     { "protq",          { { OP_DREX3, q_mode } } },
5352     { "pshlb",          { { OP_DREX3, q_mode } } },
5353     { "pshlw",          { { OP_DREX3, q_mode } } },
5354     { "pshld",          { { OP_DREX3, q_mode } } },
5355     { "pshlq",          { { OP_DREX3, q_mode } } },
5356     /* 48 */
5357     { "pshab",          { { OP_DREX3, q_mode } } },
5358     { "pshaw",          { { OP_DREX3, q_mode } } },
5359     { "pshad",          { { OP_DREX3, q_mode } } },
5360     { "pshaq",          { { OP_DREX3, q_mode } } },
5361     { "(bad)",          { XX } },
5362     { "(bad)",          { XX } },
5363     { "(bad)",          { XX } },
5364     { "(bad)",          { XX } },
5365     /* 50 */
5366     { "(bad)",          { XX } },
5367     { "(bad)",          { XX } },
5368     { "(bad)",          { XX } },
5369     { "(bad)",          { XX } },
5370     { "(bad)",          { XX } },
5371     { "(bad)",          { XX } },
5372     { "(bad)",          { XX } },
5373     { "(bad)",          { XX } },
5374     /* 58 */
5375     { "(bad)",          { XX } },
5376     { "(bad)",          { XX } },
5377     { "(bad)",          { XX } },
5378     { "(bad)",          { XX } },
5379     { "(bad)",          { XX } },
5380     { "(bad)",          { XX } },
5381     { "(bad)",          { XX } },
5382     { "(bad)",          { XX } },
5383     /* 60 */
5384     { "(bad)",          { XX } },
5385     { "(bad)",          { XX } },
5386     { "(bad)",          { XX } },
5387     { "(bad)",          { XX } },
5388     { "(bad)",          { XX } },
5389     { "(bad)",          { XX } },
5390     { "(bad)",          { XX } },
5391     { "(bad)",          { XX } },
5392     /* 68 */
5393     { "(bad)",          { XX } },
5394     { "(bad)",          { XX } },
5395     { "(bad)",          { XX } },
5396     { "(bad)",          { XX } },
5397     { "(bad)",          { XX } },
5398     { "(bad)",          { XX } },
5399     { "(bad)",          { XX } },
5400     { "(bad)",          { XX } },
5401     /* 70 */
5402     { "(bad)",          { XX } },
5403     { "(bad)",          { XX } },
5404     { "(bad)",          { XX } },
5405     { "(bad)",          { XX } },
5406     { "(bad)",          { XX } },
5407     { "(bad)",          { XX } },
5408     { "(bad)",          { XX } },
5409     { "(bad)",          { XX } },
5410     /* 78 */
5411     { "(bad)",          { XX } },
5412     { "(bad)",          { XX } },
5413     { "(bad)",          { XX } },
5414     { "(bad)",          { XX } },
5415     { "(bad)",          { XX } },
5416     { "(bad)",          { XX } },
5417     { "(bad)",          { XX } },
5418     { "(bad)",          { XX } },
5419     /* 80 */
5420     { "(bad)",          { XX } },
5421     { "(bad)",          { XX } },
5422     { "(bad)",          { XX } },
5423     { "(bad)",          { XX } },
5424     { "(bad)",          { XX } },
5425     { "pmacssww",       { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
5426     { "pmacsswd",       { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
5427     { "pmacssdql",      { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
5428     /* 88 */
5429     { "(bad)",          { XX } },
5430     { "(bad)",          { XX } },
5431     { "(bad)",          { XX } },
5432     { "(bad)",          { XX } },
5433     { "(bad)",          { XX } },
5434     { "(bad)",          { XX } },
5435     { "pmacssdd",       { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
5436     { "pmacssdqh",      { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
5437     /* 90 */
5438     { "(bad)",          { XX } },
5439     { "(bad)",          { XX } },
5440     { "(bad)",          { XX } },
5441     { "(bad)",          { XX } },
5442     { "(bad)",          { XX } },
5443     { "pmacsww",        { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
5444     { "pmacswd",        { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
5445     { "pmacsdql",       { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
5446     /* 98 */
5447     { "(bad)",          { XX } },
5448     { "(bad)",          { XX } },
5449     { "(bad)",          { XX } },
5450     { "(bad)",          { XX } },
5451     { "(bad)",          { XX } },
5452     { "(bad)",          { XX } },
5453     { "pmacsdd",        { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
5454     { "pmacsdqh",       { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
5455     /* a0 */
5456     { "(bad)",          { XX } },
5457     { "(bad)",          { XX } },
5458     { "(bad)",          { XX } },
5459     { "(bad)",          { XX } },
5460     { "(bad)",          { XX } },
5461     { "(bad)",          { XX } },
5462     { "pmadcsswd",      { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
5463     { "(bad)",          { XX } },
5464     /* a8 */
5465     { "(bad)",          { XX } },
5466     { "(bad)",          { XX } },
5467     { "(bad)",          { XX } },
5468     { "(bad)",          { XX } },
5469     { "(bad)",          { XX } },
5470     { "(bad)",          { XX } },
5471     { "(bad)",          { XX } },
5472     { "(bad)",          { XX } },
5473     /* b0 */
5474     { "(bad)",          { XX } },
5475     { "(bad)",          { XX } },
5476     { "(bad)",          { XX } },
5477     { "(bad)",          { XX } },
5478     { "(bad)",          { XX } },
5479     { "(bad)",          { XX } },
5480     { "pmadcswd",       { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
5481     { "(bad)",          { XX } },
5482     /* b8 */
5483     { "(bad)",          { XX } },
5484     { "(bad)",          { XX } },
5485     { "(bad)",          { XX } },
5486     { "(bad)",          { XX } },
5487     { "(bad)",          { XX } },
5488     { "(bad)",          { XX } },
5489     { "(bad)",          { XX } },
5490     { "(bad)",          { XX } },
5491     /* c0 */
5492     { "(bad)",          { XX } },
5493     { "(bad)",          { XX } },
5494     { "(bad)",          { XX } },
5495     { "(bad)",          { XX } },
5496     { "(bad)",          { XX } },
5497     { "(bad)",          { XX } },
5498     { "(bad)",          { XX } },
5499     { "(bad)",          { XX } },
5500     /* c8 */
5501     { "(bad)",          { XX } },
5502     { "(bad)",          { XX } },
5503     { "(bad)",          { XX } },
5504     { "(bad)",          { XX } },
5505     { "(bad)",          { XX } },
5506     { "(bad)",          { XX } },
5507     { "(bad)",          { XX } },
5508     { "(bad)",          { XX } },
5509     /* d0 */
5510     { "(bad)",          { XX } },
5511     { "(bad)",          { XX } },
5512     { "(bad)",          { XX } },
5513     { "(bad)",          { XX } },
5514     { "(bad)",          { XX } },
5515     { "(bad)",          { XX } },
5516     { "(bad)",          { XX } },
5517     { "(bad)",          { XX } },
5518     /* d8 */
5519     { "(bad)",          { XX } },
5520     { "(bad)",          { XX } },
5521     { "(bad)",          { XX } },
5522     { "(bad)",          { XX } },
5523     { "(bad)",          { XX } },
5524     { "(bad)",          { XX } },
5525     { "(bad)",          { XX } },
5526     { "(bad)",          { XX } },
5527     /* e0 */
5528     { "(bad)",          { XX } },
5529     { "(bad)",          { XX } },
5530     { "(bad)",          { XX } },
5531     { "(bad)",          { XX } },
5532     { "(bad)",          { XX } },
5533     { "(bad)",          { XX } },
5534     { "(bad)",          { XX } },
5535     { "(bad)",          { XX } },
5536     /* e8 */
5537     { "(bad)",          { XX } },
5538     { "(bad)",          { XX } },
5539     { "(bad)",          { XX } },
5540     { "(bad)",          { XX } },
5541     { "(bad)",          { XX } },
5542     { "(bad)",          { XX } },
5543     { "(bad)",          { XX } },
5544     { "(bad)",          { XX } },
5545     /* f0 */
5546     { "(bad)",          { XX } },
5547     { "(bad)",          { XX } },
5548     { "(bad)",          { XX } },
5549     { "(bad)",          { XX } },
5550     { "(bad)",          { XX } },
5551     { "(bad)",          { XX } },
5552     { "(bad)",          { XX } },
5553     { "(bad)",          { XX } },
5554     /* f8 */
5555     { "(bad)",          { XX } },
5556     { "(bad)",          { XX } },
5557     { "(bad)",          { XX } },
5558     { "(bad)",          { XX } },
5559     { "(bad)",          { XX } },
5560     { "(bad)",          { XX } },
5561     { "(bad)",          { XX } },
5562     { "(bad)",          { XX } },
5563   },
5564   /* THREE_BYTE_0F25 */
5565   {
5566     /* 00 */
5567     { "(bad)",          { XX } },
5568     { "(bad)",          { XX } },
5569     { "(bad)",          { XX } },
5570     { "(bad)",          { XX } },
5571     { "(bad)",          { XX } },
5572     { "(bad)",          { XX } },
5573     { "(bad)",          { XX } },
5574     { "(bad)",          { XX } },
5575     /* 08 */
5576     { "(bad)",          { XX } },
5577     { "(bad)",          { XX } },
5578     { "(bad)",          { XX } },
5579     { "(bad)",          { XX } },
5580     { "(bad)",          { XX } },
5581     { "(bad)",          { XX } },
5582     { "(bad)",          { XX } },
5583     { "(bad)",          { XX } },
5584     /* 10 */
5585     { "(bad)",          { XX } },
5586     { "(bad)",          { XX } },
5587     { "(bad)",          { XX } },
5588     { "(bad)",          { XX } },
5589     { "(bad)",          { XX } },
5590     { "(bad)",          { XX } },
5591     { "(bad)",          { XX } },
5592     { "(bad)",          { XX } },
5593     /* 18 */
5594     { "(bad)",          { XX } },
5595     { "(bad)",          { XX } },
5596     { "(bad)",          { XX } },
5597     { "(bad)",          { XX } },
5598     { "(bad)",          { XX } },
5599     { "(bad)",          { XX } },
5600     { "(bad)",          { XX } },
5601     { "(bad)",          { XX } },
5602     /* 20 */
5603     { "(bad)",          { XX } },
5604     { "(bad)",          { XX } },
5605     { "(bad)",          { XX } },
5606     { "(bad)",          { XX } },
5607     { "(bad)",          { XX } },
5608     { "(bad)",          { XX } },
5609     { "(bad)",          { XX } },
5610     { "(bad)",          { XX } },
5611     /* 28 */
5612     { "(bad)",          { XX } },
5613     { "(bad)",          { XX } },
5614     { "(bad)",          { XX } },
5615     { "(bad)",          { XX } },
5616     { "comps",          { { OP_DREX3, q_mode }, { OP_DREX_FCMP, b_mode } } },
5617     { "compd",          { { OP_DREX3, q_mode }, { OP_DREX_FCMP, b_mode } } },
5618     { "comss",          { { OP_DREX3, w_mode }, { OP_DREX_FCMP, b_mode } } },
5619     { "comsd",          { { OP_DREX3, d_mode }, { OP_DREX_FCMP, b_mode } } },
5620     /* 30 */
5621     { "(bad)",          { XX } },
5622     { "(bad)",          { XX } },
5623     { "(bad)",          { XX } },
5624     { "(bad)",          { XX } },
5625     { "(bad)",          { XX } },
5626     { "(bad)",          { XX } },
5627     { "(bad)",          { XX } },
5628     { "(bad)",          { XX } },
5629     /* 38 */
5630     { "(bad)",          { XX } },
5631     { "(bad)",          { XX } },
5632     { "(bad)",          { XX } },
5633     { "(bad)",          { XX } },
5634     { "(bad)",          { XX } },
5635     { "(bad)",          { XX } },
5636     { "(bad)",          { XX } },
5637     { "(bad)",          { XX } },
5638     /* 40 */
5639     { "(bad)",          { XX } },
5640     { "(bad)",          { XX } },
5641     { "(bad)",          { XX } },
5642     { "(bad)",          { XX } },
5643     { "(bad)",          { XX } },
5644     { "(bad)",          { XX } },
5645     { "(bad)",          { XX } },
5646     { "(bad)",          { XX } },
5647     /* 48 */
5648     { "(bad)",          { XX } },
5649     { "(bad)",          { XX } },
5650     { "(bad)",          { XX } },
5651     { "(bad)",          { XX } },
5652     { "pcomb",          { { OP_DREX3, q_mode }, { OP_DREX_ICMP, b_mode } } },
5653     { "pcomw",          { { OP_DREX3, q_mode }, { OP_DREX_ICMP, b_mode } } },
5654     { "pcomd",          { { OP_DREX3, q_mode }, { OP_DREX_ICMP, b_mode } } },
5655     { "pcomq",          { { OP_DREX3, q_mode }, { OP_DREX_ICMP, b_mode } } },
5656     /* 50 */
5657     { "(bad)",          { XX } },
5658     { "(bad)",          { XX } },
5659     { "(bad)",          { XX } },
5660     { "(bad)",          { XX } },
5661     { "(bad)",          { XX } },
5662     { "(bad)",          { XX } },
5663     { "(bad)",          { XX } },
5664     { "(bad)",          { XX } },
5665     /* 58 */
5666     { "(bad)",          { XX } },
5667     { "(bad)",          { XX } },
5668     { "(bad)",          { XX } },
5669     { "(bad)",          { XX } },
5670     { "(bad)",          { XX } },
5671     { "(bad)",          { XX } },
5672     { "(bad)",          { XX } },
5673     { "(bad)",          { XX } },
5674     /* 60 */
5675     { "(bad)",          { XX } },
5676     { "(bad)",          { XX } },
5677     { "(bad)",          { XX } },
5678     { "(bad)",          { XX } },
5679     { "(bad)",          { XX } },
5680     { "(bad)",          { XX } },
5681     { "(bad)",          { XX } },
5682     { "(bad)",          { XX } },
5683     /* 68 */
5684     { "(bad)",          { XX } },
5685     { "(bad)",          { XX } },
5686     { "(bad)",          { XX } },
5687     { "(bad)",          { XX } },
5688     { "pcomub",         { { OP_DREX3, q_mode }, { OP_DREX_ICMP, b_mode } } },
5689     { "pcomuw",         { { OP_DREX3, q_mode }, { OP_DREX_ICMP, b_mode } } },
5690     { "pcomud",         { { OP_DREX3, q_mode }, { OP_DREX_ICMP, b_mode } } },
5691     { "pcomuq",         { { OP_DREX3, q_mode }, { OP_DREX_ICMP, b_mode } } },
5692     /* 70 */
5693     { "(bad)",          { XX } },
5694     { "(bad)",          { XX } },
5695     { "(bad)",          { XX } },
5696     { "(bad)",          { XX } },
5697     { "(bad)",          { XX } },
5698     { "(bad)",          { XX } },
5699     { "(bad)",          { XX } },
5700     { "(bad)",          { XX } },
5701     /* 78 */
5702     { "(bad)",          { XX } },
5703     { "(bad)",          { XX } },
5704     { "(bad)",          { XX } },
5705     { "(bad)",          { XX } },
5706     { "(bad)",          { XX } },
5707     { "(bad)",          { XX } },
5708     { "(bad)",          { XX } },
5709     { "(bad)",          { XX } },
5710     /* 80 */
5711     { "(bad)",          { XX } },
5712     { "(bad)",          { XX } },
5713     { "(bad)",          { XX } },
5714     { "(bad)",          { XX } },
5715     { "(bad)",          { XX } },
5716     { "(bad)",          { XX } },
5717     { "(bad)",          { XX } },
5718     { "(bad)",          { XX } },
5719     /* 88 */
5720     { "(bad)",          { XX } },
5721     { "(bad)",          { XX } },
5722     { "(bad)",          { XX } },
5723     { "(bad)",          { XX } },
5724     { "(bad)",          { XX } },
5725     { "(bad)",          { XX } },
5726     { "(bad)",          { XX } },
5727     { "(bad)",          { XX } },
5728     /* 90 */
5729     { "(bad)",          { XX } },
5730     { "(bad)",          { XX } },
5731     { "(bad)",          { XX } },
5732     { "(bad)",          { XX } },
5733     { "(bad)",          { XX } },
5734     { "(bad)",          { XX } },
5735     { "(bad)",          { XX } },
5736     { "(bad)",          { XX } },
5737     /* 98 */
5738     { "(bad)",          { XX } },
5739     { "(bad)",          { XX } },
5740     { "(bad)",          { XX } },
5741     { "(bad)",          { XX } },
5742     { "(bad)",          { XX } },
5743     { "(bad)",          { XX } },
5744     { "(bad)",          { XX } },
5745     { "(bad)",          { XX } },
5746     /* a0 */
5747     { "(bad)",          { XX } },
5748     { "(bad)",          { XX } },
5749     { "(bad)",          { XX } },
5750     { "(bad)",          { XX } },
5751     { "(bad)",          { XX } },
5752     { "(bad)",          { XX } },
5753     { "(bad)",          { XX } },
5754     { "(bad)",          { XX } },
5755     /* a8 */
5756     { "(bad)",          { XX } },
5757     { "(bad)",          { XX } },
5758     { "(bad)",          { XX } },
5759     { "(bad)",          { XX } },
5760     { "(bad)",          { XX } },
5761     { "(bad)",          { XX } },
5762     { "(bad)",          { XX } },
5763     { "(bad)",          { XX } },
5764     /* b0 */
5765     { "(bad)",          { XX } },
5766     { "(bad)",          { XX } },
5767     { "(bad)",          { XX } },
5768     { "(bad)",          { XX } },
5769     { "(bad)",          { XX } },
5770     { "(bad)",          { XX } },
5771     { "(bad)",          { XX } },
5772     { "(bad)",          { XX } },
5773     /* b8 */
5774     { "(bad)",          { XX } },
5775     { "(bad)",          { XX } },
5776     { "(bad)",          { XX } },
5777     { "(bad)",          { XX } },
5778     { "(bad)",          { XX } },
5779     { "(bad)",          { XX } },
5780     { "(bad)",          { XX } },
5781     { "(bad)",          { XX } },
5782     /* c0 */
5783     { "(bad)",          { XX } },
5784     { "(bad)",          { XX } },
5785     { "(bad)",          { XX } },
5786     { "(bad)",          { XX } },
5787     { "(bad)",          { XX } },
5788     { "(bad)",          { XX } },
5789     { "(bad)",          { XX } },
5790     { "(bad)",          { XX } },
5791     /* c8 */
5792     { "(bad)",          { XX } },
5793     { "(bad)",          { XX } },
5794     { "(bad)",          { XX } },
5795     { "(bad)",          { XX } },
5796     { "(bad)",          { XX } },
5797     { "(bad)",          { XX } },
5798     { "(bad)",          { XX } },
5799     { "(bad)",          { XX } },
5800     /* d0 */
5801     { "(bad)",          { XX } },
5802     { "(bad)",          { XX } },
5803     { "(bad)",          { XX } },
5804     { "(bad)",          { XX } },
5805     { "(bad)",          { XX } },
5806     { "(bad)",          { XX } },
5807     { "(bad)",          { XX } },
5808     { "(bad)",          { XX } },
5809     /* d8 */
5810     { "(bad)",          { XX } },
5811     { "(bad)",          { XX } },
5812     { "(bad)",          { XX } },
5813     { "(bad)",          { XX } },
5814     { "(bad)",          { XX } },
5815     { "(bad)",          { XX } },
5816     { "(bad)",          { XX } },
5817     { "(bad)",          { XX } },
5818     /* e0 */
5819     { "(bad)",          { XX } },
5820     { "(bad)",          { XX } },
5821     { "(bad)",          { XX } },
5822     { "(bad)",          { XX } },
5823     { "(bad)",          { XX } },
5824     { "(bad)",          { XX } },
5825     { "(bad)",          { XX } },
5826     { "(bad)",          { XX } },
5827     /* e8 */
5828     { "(bad)",          { XX } },
5829     { "(bad)",          { XX } },
5830     { "(bad)",          { XX } },
5831     { "(bad)",          { XX } },
5832     { "(bad)",          { XX } },
5833     { "(bad)",          { XX } },
5834     { "(bad)",          { XX } },
5835     { "(bad)",          { XX } },
5836     /* f0 */
5837     { "(bad)",          { XX } },
5838     { "(bad)",          { XX } },
5839     { "(bad)",          { XX } },
5840     { "(bad)",          { XX } },
5841     { "(bad)",          { XX } },
5842     { "(bad)",          { XX } },
5843     { "(bad)",          { XX } },
5844     { "(bad)",          { XX } },
5845     /* f8 */
5846     { "(bad)",          { XX } },
5847     { "(bad)",          { XX } },
5848     { "(bad)",          { XX } },
5849     { "(bad)",          { XX } },
5850     { "(bad)",          { XX } },
5851     { "(bad)",          { XX } },
5852     { "(bad)",          { XX } },
5853     { "(bad)",          { XX } },
5854   },
5855   /* THREE_BYTE_0F38 */
5856   {
5857     /* 00 */
5858     { "pshufb",         { MX, EM } },
5859     { "phaddw",         { MX, EM } },
5860     { "phaddd",         { MX, EM } },
5861     { "phaddsw",        { MX, EM } },
5862     { "pmaddubsw",      { MX, EM } },
5863     { "phsubw",         { MX, EM } },
5864     { "phsubd",         { MX, EM } },
5865     { "phsubsw",        { MX, EM } },
5866     /* 08 */
5867     { "psignb",         { MX, EM } },
5868     { "psignw",         { MX, EM } },
5869     { "psignd",         { MX, EM } },
5870     { "pmulhrsw",       { MX, EM } },
5871     { "(bad)",          { XX } },
5872     { "(bad)",          { XX } },
5873     { "(bad)",          { XX } },
5874     { "(bad)",          { XX } },
5875     /* 10 */
5876     { PREFIX_TABLE (PREFIX_0F3810) },
5877     { "(bad)",          { XX } },
5878     { "(bad)",          { XX } },
5879     { "(bad)",          { XX } },
5880     { PREFIX_TABLE (PREFIX_0F3814) },
5881     { PREFIX_TABLE (PREFIX_0F3815) },
5882     { "(bad)",          { XX } },
5883     { PREFIX_TABLE (PREFIX_0F3817) },
5884     /* 18 */
5885     { "(bad)",          { XX } },
5886     { "(bad)",          { XX } },
5887     { "(bad)",          { XX } },
5888     { "(bad)",          { XX } },
5889     { "pabsb",          { MX, EM } },
5890     { "pabsw",          { MX, EM } },
5891     { "pabsd",          { MX, EM } },
5892     { "(bad)",          { XX } },
5893     /* 20 */
5894     { PREFIX_TABLE (PREFIX_0F3820) },
5895     { PREFIX_TABLE (PREFIX_0F3821) },
5896     { PREFIX_TABLE (PREFIX_0F3822) },
5897     { PREFIX_TABLE (PREFIX_0F3823) },
5898     { PREFIX_TABLE (PREFIX_0F3824) },
5899     { PREFIX_TABLE (PREFIX_0F3825) },
5900     { "(bad)",          { XX } },
5901     { "(bad)",          { XX } },
5902     /* 28 */
5903     { PREFIX_TABLE (PREFIX_0F3828) },
5904     { PREFIX_TABLE (PREFIX_0F3829) },
5905     { PREFIX_TABLE (PREFIX_0F382A) },
5906     { PREFIX_TABLE (PREFIX_0F382B) },
5907     { "(bad)",          { XX } },
5908     { "(bad)",          { XX } },
5909     { "(bad)",          { XX } },
5910     { "(bad)",          { XX } },
5911     /* 30 */
5912     { PREFIX_TABLE (PREFIX_0F3830) },
5913     { PREFIX_TABLE (PREFIX_0F3831) },
5914     { PREFIX_TABLE (PREFIX_0F3832) },
5915     { PREFIX_TABLE (PREFIX_0F3833) },
5916     { PREFIX_TABLE (PREFIX_0F3834) },
5917     { PREFIX_TABLE (PREFIX_0F3835) },
5918     { "(bad)",          { XX } },
5919     { PREFIX_TABLE (PREFIX_0F3837) },
5920     /* 38 */
5921     { PREFIX_TABLE (PREFIX_0F3838) },
5922     { PREFIX_TABLE (PREFIX_0F3839) },
5923     { PREFIX_TABLE (PREFIX_0F383A) },
5924     { PREFIX_TABLE (PREFIX_0F383B) },
5925     { PREFIX_TABLE (PREFIX_0F383C) },
5926     { PREFIX_TABLE (PREFIX_0F383D) },
5927     { PREFIX_TABLE (PREFIX_0F383E) },
5928     { PREFIX_TABLE (PREFIX_0F383F) },
5929     /* 40 */
5930     { PREFIX_TABLE (PREFIX_0F3840) },
5931     { PREFIX_TABLE (PREFIX_0F3841) },
5932     { "(bad)",          { XX } },
5933     { "(bad)",          { XX } },
5934     { "(bad)",          { XX } },
5935     { "(bad)",          { XX } },
5936     { "(bad)",          { XX } },
5937     { "(bad)",          { XX } },
5938     /* 48 */
5939     { "(bad)",          { XX } },
5940     { "(bad)",          { XX } },
5941     { "(bad)",          { XX } },
5942     { "(bad)",          { XX } },
5943     { "(bad)",          { XX } },
5944     { "(bad)",          { XX } },
5945     { "(bad)",          { XX } },
5946     { "(bad)",          { XX } },
5947     /* 50 */
5948     { "(bad)",          { XX } },
5949     { "(bad)",          { XX } },
5950     { "(bad)",          { XX } },
5951     { "(bad)",          { XX } },
5952     { "(bad)",          { XX } },
5953     { "(bad)",          { XX } },
5954     { "(bad)",          { XX } },
5955     { "(bad)",          { XX } },
5956     /* 58 */
5957     { "(bad)",          { XX } },
5958     { "(bad)",          { XX } },
5959     { "(bad)",          { XX } },
5960     { "(bad)",          { XX } },
5961     { "(bad)",          { XX } },
5962     { "(bad)",          { XX } },
5963     { "(bad)",          { XX } },
5964     { "(bad)",          { XX } },
5965     /* 60 */
5966     { "(bad)",          { XX } },
5967     { "(bad)",          { XX } },
5968     { "(bad)",          { XX } },
5969     { "(bad)",          { XX } },
5970     { "(bad)",          { XX } },
5971     { "(bad)",          { XX } },
5972     { "(bad)",          { XX } },
5973     { "(bad)",          { XX } },
5974     /* 68 */
5975     { "(bad)",          { XX } },
5976     { "(bad)",          { XX } },
5977     { "(bad)",          { XX } },
5978     { "(bad)",          { XX } },
5979     { "(bad)",          { XX } },
5980     { "(bad)",          { XX } },
5981     { "(bad)",          { XX } },
5982     { "(bad)",          { XX } },
5983     /* 70 */
5984     { "(bad)",          { XX } },
5985     { "(bad)",          { XX } },
5986     { "(bad)",          { XX } },
5987     { "(bad)",          { XX } },
5988     { "(bad)",          { XX } },
5989     { "(bad)",          { XX } },
5990     { "(bad)",          { XX } },
5991     { "(bad)",          { XX } },
5992     /* 78 */
5993     { "(bad)",          { XX } },
5994     { "(bad)",          { XX } },
5995     { "(bad)",          { XX } },
5996     { "(bad)",          { XX } },
5997     { "(bad)",          { XX } },
5998     { "(bad)",          { XX } },
5999     { "(bad)",          { XX } },
6000     { "(bad)",          { XX } },
6001     /* 80 */
6002     { PREFIX_TABLE (PREFIX_0F3880) },
6003     { PREFIX_TABLE (PREFIX_0F3881) },
6004     { "(bad)",          { XX } },
6005     { "(bad)",          { XX } },
6006     { "(bad)",          { XX } },
6007     { "(bad)",          { XX } },
6008     { "(bad)",          { XX } },
6009     { "(bad)",          { XX } },
6010     /* 88 */
6011     { "(bad)",          { XX } },
6012     { "(bad)",          { XX } },
6013     { "(bad)",          { XX } },
6014     { "(bad)",          { XX } },
6015     { "(bad)",          { XX } },
6016     { "(bad)",          { XX } },
6017     { "(bad)",          { XX } },
6018     { "(bad)",          { XX } },
6019     /* 90 */
6020     { "(bad)",          { XX } },
6021     { "(bad)",          { XX } },
6022     { "(bad)",          { XX } },
6023     { "(bad)",          { XX } },
6024     { "(bad)",          { XX } },
6025     { "(bad)",          { XX } },
6026     { "(bad)",          { XX } },
6027     { "(bad)",          { XX } },
6028     /* 98 */
6029     { "(bad)",          { XX } },
6030     { "(bad)",          { XX } },
6031     { "(bad)",          { XX } },
6032     { "(bad)",          { XX } },
6033     { "(bad)",          { XX } },
6034     { "(bad)",          { XX } },
6035     { "(bad)",          { XX } },
6036     { "(bad)",          { XX } },
6037     /* a0 */
6038     { "(bad)",          { XX } },
6039     { "(bad)",          { XX } },
6040     { "(bad)",          { XX } },
6041     { "(bad)",          { XX } },
6042     { "(bad)",          { XX } },
6043     { "(bad)",          { XX } },
6044     { "(bad)",          { XX } },
6045     { "(bad)",          { XX } },
6046     /* a8 */
6047     { "(bad)",          { XX } },
6048     { "(bad)",          { XX } },
6049     { "(bad)",          { XX } },
6050     { "(bad)",          { XX } },
6051     { "(bad)",          { XX } },
6052     { "(bad)",          { XX } },
6053     { "(bad)",          { XX } },
6054     { "(bad)",          { XX } },
6055     /* b0 */
6056     { "(bad)",          { XX } },
6057     { "(bad)",          { XX } },
6058     { "(bad)",          { XX } },
6059     { "(bad)",          { XX } },
6060     { "(bad)",          { XX } },
6061     { "(bad)",          { XX } },
6062     { "(bad)",          { XX } },
6063     { "(bad)",          { XX } },
6064     /* b8 */
6065     { "(bad)",          { XX } },
6066     { "(bad)",          { XX } },
6067     { "(bad)",          { XX } },
6068     { "(bad)",          { XX } },
6069     { "(bad)",          { XX } },
6070     { "(bad)",          { XX } },
6071     { "(bad)",          { XX } },
6072     { "(bad)",          { XX } },
6073     /* c0 */
6074     { "(bad)",          { XX } },
6075     { "(bad)",          { XX } },
6076     { "(bad)",          { XX } },
6077     { "(bad)",          { XX } },
6078     { "(bad)",          { XX } },
6079     { "(bad)",          { XX } },
6080     { "(bad)",          { XX } },
6081     { "(bad)",          { XX } },
6082     /* c8 */
6083     { "(bad)",          { XX } },
6084     { "(bad)",          { XX } },
6085     { "(bad)",          { XX } },
6086     { "(bad)",          { XX } },
6087     { "(bad)",          { XX } },
6088     { "(bad)",          { XX } },
6089     { "(bad)",          { XX } },
6090     { "(bad)",          { XX } },
6091     /* d0 */
6092     { "(bad)",          { XX } },
6093     { "(bad)",          { XX } },
6094     { "(bad)",          { XX } },
6095     { "(bad)",          { XX } },
6096     { "(bad)",          { XX } },
6097     { "(bad)",          { XX } },
6098     { "(bad)",          { XX } },
6099     { "(bad)",          { XX } },
6100     /* d8 */
6101     { "(bad)",          { XX } },
6102     { "(bad)",          { XX } },
6103     { "(bad)",          { XX } },
6104     { PREFIX_TABLE (PREFIX_0F38DB) },
6105     { PREFIX_TABLE (PREFIX_0F38DC) },
6106     { PREFIX_TABLE (PREFIX_0F38DD) },
6107     { PREFIX_TABLE (PREFIX_0F38DE) },
6108     { PREFIX_TABLE (PREFIX_0F38DF) },
6109     /* e0 */
6110     { "(bad)",          { XX } },
6111     { "(bad)",          { XX } },
6112     { "(bad)",          { XX } },
6113     { "(bad)",          { XX } },
6114     { "(bad)",          { XX } },
6115     { "(bad)",          { XX } },
6116     { "(bad)",          { XX } },
6117     { "(bad)",          { XX } },
6118     /* e8 */
6119     { "(bad)",          { XX } },
6120     { "(bad)",          { XX } },
6121     { "(bad)",          { XX } },
6122     { "(bad)",          { XX } },
6123     { "(bad)",          { XX } },
6124     { "(bad)",          { XX } },
6125     { "(bad)",          { XX } },
6126     { "(bad)",          { XX } },
6127     /* f0 */
6128     { PREFIX_TABLE (PREFIX_0F38F0) },
6129     { PREFIX_TABLE (PREFIX_0F38F1) },
6130     { "(bad)",          { XX } },
6131     { "(bad)",          { XX } },
6132     { "(bad)",          { XX } },
6133     { "(bad)",          { XX } },
6134     { "(bad)",          { XX } },
6135     { "(bad)",          { XX } },
6136     /* f8 */
6137     { "(bad)",          { XX } },
6138     { "(bad)",          { XX } },
6139     { "(bad)",          { XX } },
6140     { "(bad)",          { XX } },
6141     { "(bad)",          { XX } },
6142     { "(bad)",          { XX } },
6143     { "(bad)",          { XX } },
6144     { "(bad)",          { XX } },
6145   },
6146   /* THREE_BYTE_0F3A */
6147   {
6148     /* 00 */
6149     { "(bad)",          { XX } },
6150     { "(bad)",          { XX } },
6151     { "(bad)",          { XX } },
6152     { "(bad)",          { XX } },
6153     { "(bad)",          { XX } },
6154     { "(bad)",          { XX } },
6155     { "(bad)",          { XX } },
6156     { "(bad)",          { XX } },
6157     /* 08 */
6158     { PREFIX_TABLE (PREFIX_0F3A08) },
6159     { PREFIX_TABLE (PREFIX_0F3A09) },
6160     { PREFIX_TABLE (PREFIX_0F3A0A) },
6161     { PREFIX_TABLE (PREFIX_0F3A0B) },
6162     { PREFIX_TABLE (PREFIX_0F3A0C) },
6163     { PREFIX_TABLE (PREFIX_0F3A0D) },
6164     { PREFIX_TABLE (PREFIX_0F3A0E) },
6165     { "palignr",        { MX, EM, Ib } },
6166     /* 10 */
6167     { "(bad)",          { XX } },
6168     { "(bad)",          { XX } },
6169     { "(bad)",          { XX } },
6170     { "(bad)",          { XX } },
6171     { PREFIX_TABLE (PREFIX_0F3A14) },
6172     { PREFIX_TABLE (PREFIX_0F3A15) },
6173     { PREFIX_TABLE (PREFIX_0F3A16) },
6174     { PREFIX_TABLE (PREFIX_0F3A17) },
6175     /* 18 */
6176     { "(bad)",          { XX } },
6177     { "(bad)",          { XX } },
6178     { "(bad)",          { XX } },
6179     { "(bad)",          { XX } },
6180     { "(bad)",          { XX } },
6181     { "(bad)",          { XX } },
6182     { "(bad)",          { XX } },
6183     { "(bad)",          { XX } },
6184     /* 20 */
6185     { PREFIX_TABLE (PREFIX_0F3A20) },
6186     { PREFIX_TABLE (PREFIX_0F3A21) },
6187     { PREFIX_TABLE (PREFIX_0F3A22) },
6188     { "(bad)",          { XX } },
6189     { "(bad)",          { XX } },
6190     { "(bad)",          { XX } },
6191     { "(bad)",          { XX } },
6192     { "(bad)",          { XX } },
6193     /* 28 */
6194     { "(bad)",          { XX } },
6195     { "(bad)",          { XX } },
6196     { "(bad)",          { XX } },
6197     { "(bad)",          { XX } },
6198     { "(bad)",          { XX } },
6199     { "(bad)",          { XX } },
6200     { "(bad)",          { XX } },
6201     { "(bad)",          { XX } },
6202     /* 30 */
6203     { "(bad)",          { XX } },
6204     { "(bad)",          { XX } },
6205     { "(bad)",          { XX } },
6206     { "(bad)",          { XX } },
6207     { "(bad)",          { XX } },
6208     { "(bad)",          { XX } },
6209     { "(bad)",          { XX } },
6210     { "(bad)",          { XX } },
6211     /* 38 */
6212     { "(bad)",          { XX } },
6213     { "(bad)",          { XX } },
6214     { "(bad)",          { XX } },
6215     { "(bad)",          { XX } },
6216     { "(bad)",          { XX } },
6217     { "(bad)",          { XX } },
6218     { "(bad)",          { XX } },
6219     { "(bad)",          { XX } },
6220     /* 40 */
6221     { PREFIX_TABLE (PREFIX_0F3A40) },
6222     { PREFIX_TABLE (PREFIX_0F3A41) },
6223     { PREFIX_TABLE (PREFIX_0F3A42) },
6224     { "(bad)",          { XX } },
6225     { PREFIX_TABLE (PREFIX_0F3A44) },
6226     { "(bad)",          { XX } },
6227     { "(bad)",          { XX } },
6228     { "(bad)",          { XX } },
6229     /* 48 */
6230     { "(bad)",          { XX } },
6231     { "(bad)",          { XX } },
6232     { "(bad)",          { XX } },
6233     { "(bad)",          { XX } },
6234     { "(bad)",          { XX } },
6235     { "(bad)",          { XX } },
6236     { "(bad)",          { XX } },
6237     { "(bad)",          { XX } },
6238     /* 50 */
6239     { "(bad)",          { XX } },
6240     { "(bad)",          { XX } },
6241     { "(bad)",          { XX } },
6242     { "(bad)",          { XX } },
6243     { "(bad)",          { XX } },
6244     { "(bad)",          { XX } },
6245     { "(bad)",          { XX } },
6246     { "(bad)",          { XX } },
6247     /* 58 */
6248     { "(bad)",          { XX } },
6249     { "(bad)",          { XX } },
6250     { "(bad)",          { XX } },
6251     { "(bad)",          { XX } },
6252     { "(bad)",          { XX } },
6253     { "(bad)",          { XX } },
6254     { "(bad)",          { XX } },
6255     { "(bad)",          { XX } },
6256     /* 60 */
6257     { PREFIX_TABLE (PREFIX_0F3A60) },
6258     { PREFIX_TABLE (PREFIX_0F3A61) },
6259     { PREFIX_TABLE (PREFIX_0F3A62) },
6260     { PREFIX_TABLE (PREFIX_0F3A63) },
6261     { "(bad)",          { XX } },
6262     { "(bad)",          { XX } },
6263     { "(bad)",          { XX } },
6264     { "(bad)",          { XX } },
6265     /* 68 */
6266     { "(bad)",          { XX } },
6267     { "(bad)",          { XX } },
6268     { "(bad)",          { XX } },
6269     { "(bad)",          { XX } },
6270     { "(bad)",          { XX } },
6271     { "(bad)",          { XX } },
6272     { "(bad)",          { XX } },
6273     { "(bad)",          { XX } },
6274     /* 70 */
6275     { "(bad)",          { XX } },
6276     { "(bad)",          { XX } },
6277     { "(bad)",          { XX } },
6278     { "(bad)",          { XX } },
6279     { "(bad)",          { XX } },
6280     { "(bad)",          { XX } },
6281     { "(bad)",          { XX } },
6282     { "(bad)",          { XX } },
6283     /* 78 */
6284     { "(bad)",          { XX } },
6285     { "(bad)",          { XX } },
6286     { "(bad)",          { XX } },
6287     { "(bad)",          { XX } },
6288     { "(bad)",          { XX } },
6289     { "(bad)",          { XX } },
6290     { "(bad)",          { XX } },
6291     { "(bad)",          { XX } },
6292     /* 80 */
6293     { "(bad)",          { XX } },
6294     { "(bad)",          { XX } },
6295     { "(bad)",          { XX } },
6296     { "(bad)",          { XX } },
6297     { "(bad)",          { XX } },
6298     { "(bad)",          { XX } },
6299     { "(bad)",          { XX } },
6300     { "(bad)",          { XX } },
6301     /* 88 */
6302     { "(bad)",          { XX } },
6303     { "(bad)",          { XX } },
6304     { "(bad)",          { XX } },
6305     { "(bad)",          { XX } },
6306     { "(bad)",          { XX } },
6307     { "(bad)",          { XX } },
6308     { "(bad)",          { XX } },
6309     { "(bad)",          { XX } },
6310     /* 90 */
6311     { "(bad)",          { XX } },
6312     { "(bad)",          { XX } },
6313     { "(bad)",          { XX } },
6314     { "(bad)",          { XX } },
6315     { "(bad)",          { XX } },
6316     { "(bad)",          { XX } },
6317     { "(bad)",          { XX } },
6318     { "(bad)",          { XX } },
6319     /* 98 */
6320     { "(bad)",          { XX } },
6321     { "(bad)",          { XX } },
6322     { "(bad)",          { XX } },
6323     { "(bad)",          { XX } },
6324     { "(bad)",          { XX } },
6325     { "(bad)",          { XX } },
6326     { "(bad)",          { XX } },
6327     { "(bad)",          { XX } },
6328     /* a0 */
6329     { "(bad)",          { XX } },
6330     { "(bad)",          { XX } },
6331     { "(bad)",          { XX } },
6332     { "(bad)",          { XX } },
6333     { "(bad)",          { XX } },
6334     { "(bad)",          { XX } },
6335     { "(bad)",          { XX } },
6336     { "(bad)",          { XX } },
6337     /* a8 */
6338     { "(bad)",          { XX } },
6339     { "(bad)",          { XX } },
6340     { "(bad)",          { XX } },
6341     { "(bad)",          { XX } },
6342     { "(bad)",          { XX } },
6343     { "(bad)",          { XX } },
6344     { "(bad)",          { XX } },
6345     { "(bad)",          { XX } },
6346     /* b0 */
6347     { "(bad)",          { XX } },
6348     { "(bad)",          { XX } },
6349     { "(bad)",          { XX } },
6350     { "(bad)",          { XX } },
6351     { "(bad)",          { XX } },
6352     { "(bad)",          { XX } },
6353     { "(bad)",          { XX } },
6354     { "(bad)",          { XX } },
6355     /* b8 */
6356     { "(bad)",          { XX } },
6357     { "(bad)",          { XX } },
6358     { "(bad)",          { XX } },
6359     { "(bad)",          { XX } },
6360     { "(bad)",          { XX } },
6361     { "(bad)",          { XX } },
6362     { "(bad)",          { XX } },
6363     { "(bad)",          { XX } },
6364     /* c0 */
6365     { "(bad)",          { XX } },
6366     { "(bad)",          { XX } },
6367     { "(bad)",          { XX } },
6368     { "(bad)",          { XX } },
6369     { "(bad)",          { XX } },
6370     { "(bad)",          { XX } },
6371     { "(bad)",          { XX } },
6372     { "(bad)",          { XX } },
6373     /* c8 */
6374     { "(bad)",          { XX } },
6375     { "(bad)",          { XX } },
6376     { "(bad)",          { XX } },
6377     { "(bad)",          { XX } },
6378     { "(bad)",          { XX } },
6379     { "(bad)",          { XX } },
6380     { "(bad)",          { XX } },
6381     { "(bad)",          { XX } },
6382     /* d0 */
6383     { "(bad)",          { XX } },
6384     { "(bad)",          { XX } },
6385     { "(bad)",          { XX } },
6386     { "(bad)",          { XX } },
6387     { "(bad)",          { XX } },
6388     { "(bad)",          { XX } },
6389     { "(bad)",          { XX } },
6390     { "(bad)",          { XX } },
6391     /* d8 */
6392     { "(bad)",          { XX } },
6393     { "(bad)",          { XX } },
6394     { "(bad)",          { XX } },
6395     { "(bad)",          { XX } },
6396     { "(bad)",          { XX } },
6397     { "(bad)",          { XX } },
6398     { "(bad)",          { XX } },
6399     { PREFIX_TABLE (PREFIX_0F3ADF) },
6400     /* e0 */
6401     { "(bad)",          { XX } },
6402     { "(bad)",          { XX } },
6403     { "(bad)",          { XX } },
6404     { "(bad)",          { XX } },
6405     { "(bad)",          { XX } },
6406     { "(bad)",          { XX } },
6407     { "(bad)",          { XX } },
6408     { "(bad)",          { XX } },
6409     /* e8 */
6410     { "(bad)",          { XX } },
6411     { "(bad)",          { XX } },
6412     { "(bad)",          { XX } },
6413     { "(bad)",          { XX } },
6414     { "(bad)",          { XX } },
6415     { "(bad)",          { XX } },
6416     { "(bad)",          { XX } },
6417     { "(bad)",          { XX } },
6418     /* f0 */
6419     { "(bad)",          { XX } },
6420     { "(bad)",          { XX } },
6421     { "(bad)",          { XX } },
6422     { "(bad)",          { XX } },
6423     { "(bad)",          { XX } },
6424     { "(bad)",          { XX } },
6425     { "(bad)",          { XX } },
6426     { "(bad)",          { XX } },
6427     /* f8 */
6428     { "(bad)",          { XX } },
6429     { "(bad)",          { XX } },
6430     { "(bad)",          { XX } },
6431     { "(bad)",          { XX } },
6432     { "(bad)",          { XX } },
6433     { "(bad)",          { XX } },
6434     { "(bad)",          { XX } },
6435     { "(bad)",          { XX } },
6436   },
6437   /* THREE_BYTE_0F7A */
6438   {
6439     /* 00 */
6440     { "(bad)",          { XX } },
6441     { "(bad)",          { XX } },
6442     { "(bad)",          { XX } },
6443     { "(bad)",          { XX } },
6444     { "(bad)",          { XX } },
6445     { "(bad)",          { XX } },
6446     { "(bad)",          { XX } },
6447     { "(bad)",          { XX } },
6448     /* 08 */
6449     { "(bad)",          { XX } },
6450     { "(bad)",          { XX } },
6451     { "(bad)",          { XX } },
6452     { "(bad)",          { XX } },
6453     { "(bad)",          { XX } },
6454     { "(bad)",          { XX } },
6455     { "(bad)",          { XX } },
6456     { "(bad)",          { XX } },
6457     /* 10 */
6458     { "frczps",         { XM, EXq } },
6459     { "frczpd",         { XM, EXq } },
6460     { "frczss",         { XM, EXq } },
6461     { "frczsd",         { XM, EXq } },
6462     { "(bad)",          { XX } },
6463     { "(bad)",          { XX } },
6464     { "(bad)",          { XX } },
6465     { "(bad)",          { XX } },
6466     /* 18 */
6467     { "(bad)",          { XX } },
6468     { "(bad)",          { XX } },
6469     { "(bad)",          { XX } },
6470     { "(bad)",          { XX } },
6471     { "(bad)",          { XX } },
6472     { "(bad)",          { XX } },
6473     { "(bad)",          { XX } },
6474     { "(bad)",          { XX } },
6475     /* 20 */
6476     { "ptest",          { XX } },
6477     { "(bad)",          { XX } },
6478     { "(bad)",          { XX } },
6479     { "(bad)",          { XX } },
6480     { "(bad)",          { XX } },
6481     { "(bad)",          { XX } },
6482     { "(bad)",          { XX } },
6483     { "(bad)",          { XX } },
6484     /* 28 */
6485     { "(bad)",          { XX } },
6486     { "(bad)",          { XX } },
6487     { "(bad)",          { XX } },
6488     { "(bad)",          { XX } },
6489     { "(bad)",          { XX } },
6490     { "(bad)",          { XX } },
6491     { "(bad)",          { XX } },
6492     { "(bad)",          { XX } },
6493     /* 30 */
6494     { "cvtph2ps",       { XM, EXd } },
6495     { "cvtps2ph",       { EXd, XM } },
6496     { "(bad)",          { XX } },
6497     { "(bad)",          { XX } },
6498     { "(bad)",          { XX } },
6499     { "(bad)",          { XX } },
6500     { "(bad)",          { XX } },
6501     { "(bad)",          { XX } },
6502     /* 38 */
6503     { "(bad)",          { XX } },
6504     { "(bad)",          { XX } },
6505     { "(bad)",          { XX } },
6506     { "(bad)",          { XX } },
6507     { "(bad)",          { XX } },
6508     { "(bad)",          { XX } },
6509     { "(bad)",          { XX } },
6510     { "(bad)",          { XX } },
6511     /* 40 */
6512     { "(bad)",          { XX } },
6513     { "phaddbw",        { XM, EXq } },
6514     { "phaddbd",        { XM, EXq } },
6515     { "phaddbq",        { XM, EXq } },
6516     { "(bad)",          { XX } },
6517     { "(bad)",          { XX } },
6518     { "phaddwd",        { XM, EXq } },
6519     { "phaddwq",        { XM, EXq } },
6520     /* 48 */
6521     { "(bad)",          { XX } },
6522     { "(bad)",          { XX } },
6523     { "(bad)",          { XX } },
6524     { "phadddq",        { XM, EXq } },
6525     { "(bad)",          { XX } },
6526     { "(bad)",          { XX } },
6527     { "(bad)",          { XX } },
6528     { "(bad)",          { XX } },
6529     /* 50 */
6530     { "(bad)",          { XX } },
6531     { "phaddubw",       { XM, EXq } },
6532     { "phaddubd",       { XM, EXq } },
6533     { "phaddubq",       { XM, EXq } },
6534     { "(bad)",          { XX } },
6535     { "(bad)",          { XX } },
6536     { "phadduwd",       { XM, EXq } },
6537     { "phadduwq",       { XM, EXq } },
6538     /* 58 */
6539     { "(bad)",          { XX } },
6540     { "(bad)",          { XX } },
6541     { "(bad)",          { XX } },
6542     { "phaddudq",       { XM, EXq } },
6543     { "(bad)",          { XX } },
6544     { "(bad)",          { XX } },
6545     { "(bad)",          { XX } },
6546     { "(bad)",          { XX } },
6547     /* 60 */
6548     { "(bad)",          { XX } },
6549     { "phsubbw",        { XM, EXq } },
6550     { "phsubbd",        { XM, EXq } },
6551     { "phsubbq",        { XM, EXq } },
6552     { "(bad)",          { XX } },
6553     { "(bad)",          { XX } },
6554     { "(bad)",          { XX } },
6555     { "(bad)",          { XX } },
6556     /* 68 */
6557     { "(bad)",          { XX } },
6558     { "(bad)",          { XX } },
6559     { "(bad)",          { XX } },
6560     { "(bad)",          { XX } },
6561     { "(bad)",          { XX } },
6562     { "(bad)",          { XX } },
6563     { "(bad)",          { XX } },
6564     { "(bad)",          { XX } },
6565     /* 70 */
6566     { "(bad)",          { XX } },
6567     { "(bad)",          { XX } },
6568     { "(bad)",          { XX } },
6569     { "(bad)",          { XX } },
6570     { "(bad)",          { XX } },
6571     { "(bad)",          { XX } },
6572     { "(bad)",          { XX } },
6573     { "(bad)",          { XX } },
6574     /* 78 */
6575     { "(bad)",          { XX } },
6576     { "(bad)",          { XX } },
6577     { "(bad)",          { XX } },
6578     { "(bad)",          { XX } },
6579     { "(bad)",          { XX } },
6580     { "(bad)",          { XX } },
6581     { "(bad)",          { XX } },
6582     { "(bad)",          { XX } },
6583     /* 80 */
6584     { "(bad)",          { XX } },
6585     { "(bad)",          { XX } },
6586     { "(bad)",          { XX } },
6587     { "(bad)",          { XX } },
6588     { "(bad)",          { XX } },
6589     { "(bad)",          { XX } },
6590     { "(bad)",          { XX } },
6591     { "(bad)",          { XX } },
6592     /* 88 */
6593     { "(bad)",          { XX } },
6594     { "(bad)",          { XX } },
6595     { "(bad)",          { XX } },
6596     { "(bad)",          { XX } },
6597     { "(bad)",          { XX } },
6598     { "(bad)",          { XX } },
6599     { "(bad)",          { XX } },
6600     { "(bad)",          { XX } },
6601     /* 90 */
6602     { "(bad)",          { XX } },
6603     { "(bad)",          { XX } },
6604     { "(bad)",          { XX } },
6605     { "(bad)",          { XX } },
6606     { "(bad)",          { XX } },
6607     { "(bad)",          { XX } },
6608     { "(bad)",          { XX } },
6609     { "(bad)",          { XX } },
6610     /* 98 */
6611     { "(bad)",          { XX } },
6612     { "(bad)",          { XX } },
6613     { "(bad)",          { XX } },
6614     { "(bad)",          { XX } },
6615     { "(bad)",          { XX } },
6616     { "(bad)",          { XX } },
6617     { "(bad)",          { XX } },
6618     { "(bad)",          { XX } },
6619     /* a0 */
6620     { "(bad)",          { XX } },
6621     { "(bad)",          { XX } },
6622     { "(bad)",          { XX } },
6623     { "(bad)",          { XX } },
6624     { "(bad)",          { XX } },
6625     { "(bad)",          { XX } },
6626     { "(bad)",          { XX } },
6627     { "(bad)",          { XX } },
6628     /* a8 */
6629     { "(bad)",          { XX } },
6630     { "(bad)",          { XX } },
6631     { "(bad)",          { XX } },
6632     { "(bad)",          { XX } },
6633     { "(bad)",          { XX } },
6634     { "(bad)",          { XX } },
6635     { "(bad)",          { XX } },
6636     { "(bad)",          { XX } },
6637     /* b0 */
6638     { "(bad)",          { XX } },
6639     { "(bad)",          { XX } },
6640     { "(bad)",          { XX } },
6641     { "(bad)",          { XX } },
6642     { "(bad)",          { XX } },
6643     { "(bad)",          { XX } },
6644     { "(bad)",          { XX } },
6645     { "(bad)",          { XX } },
6646     /* b8 */
6647     { "(bad)",          { XX } },
6648     { "(bad)",          { XX } },
6649     { "(bad)",          { XX } },
6650     { "(bad)",          { XX } },
6651     { "(bad)",          { XX } },
6652     { "(bad)",          { XX } },
6653     { "(bad)",          { XX } },
6654     { "(bad)",          { XX } },
6655     /* c0 */
6656     { "(bad)",          { XX } },
6657     { "(bad)",          { XX } },
6658     { "(bad)",          { XX } },
6659     { "(bad)",          { XX } },
6660     { "(bad)",          { XX } },
6661     { "(bad)",          { XX } },
6662     { "(bad)",          { XX } },
6663     { "(bad)",          { XX } },
6664     /* c8 */
6665     { "(bad)",          { XX } },
6666     { "(bad)",          { XX } },
6667     { "(bad)",          { XX } },
6668     { "(bad)",          { XX } },
6669     { "(bad)",          { XX } },
6670     { "(bad)",          { XX } },
6671     { "(bad)",          { XX } },
6672     { "(bad)",          { XX } },
6673     /* d0 */
6674     { "(bad)",          { XX } },
6675     { "(bad)",          { XX } },
6676     { "(bad)",          { XX } },
6677     { "(bad)",          { XX } },
6678     { "(bad)",          { XX } },
6679     { "(bad)",          { XX } },
6680     { "(bad)",          { XX } },
6681     { "(bad)",          { XX } },
6682     /* d8 */
6683     { "(bad)",          { XX } },
6684     { "(bad)",          { XX } },
6685     { "(bad)",          { XX } },
6686     { "(bad)",          { XX } },
6687     { "(bad)",          { XX } },
6688     { "(bad)",          { XX } },
6689     { "(bad)",          { XX } },
6690     { "(bad)",          { XX } },
6691     /* e0 */
6692     { "(bad)",          { XX } },
6693     { "(bad)",          { XX } },
6694     { "(bad)",          { XX } },
6695     { "(bad)",          { XX } },
6696     { "(bad)",          { XX } },
6697     { "(bad)",          { XX } },
6698     { "(bad)",          { XX } },
6699     { "(bad)",          { XX } },
6700     /* e8 */
6701     { "(bad)",          { XX } },
6702     { "(bad)",          { XX } },
6703     { "(bad)",          { XX } },
6704     { "(bad)",          { XX } },
6705     { "(bad)",          { XX } },
6706     { "(bad)",          { XX } },
6707     { "(bad)",          { XX } },
6708     { "(bad)",          { XX } },
6709     /* f0 */
6710     { "(bad)",          { XX } },
6711     { "(bad)",          { XX } },
6712     { "(bad)",          { XX } },
6713     { "(bad)",          { XX } },
6714     { "(bad)",          { XX } },
6715     { "(bad)",          { XX } },
6716     { "(bad)",          { XX } },
6717     { "(bad)",          { XX } },
6718     /* f8 */
6719     { "(bad)",          { XX } },
6720     { "(bad)",          { XX } },
6721     { "(bad)",          { XX } },
6722     { "(bad)",          { XX } },
6723     { "(bad)",          { XX } },
6724     { "(bad)",          { XX } },
6725     { "(bad)",          { XX } },
6726     { "(bad)",          { XX } },
6727   },
6728   /* THREE_BYTE_0F7B */
6729   {
6730     /* 00 */
6731     { "(bad)",          { XX } },
6732     { "(bad)",          { XX } },
6733     { "(bad)",          { XX } },
6734     { "(bad)",          { XX } },
6735     { "(bad)",          { XX } },
6736     { "(bad)",          { XX } },
6737     { "(bad)",          { XX } },
6738     { "(bad)",          { XX } },
6739     /* 08 */
6740     { "(bad)",          { XX } },
6741     { "(bad)",          { XX } },
6742     { "(bad)",          { XX } },
6743     { "(bad)",          { XX } },
6744     { "(bad)",          { XX } },
6745     { "(bad)",          { XX } },
6746     { "(bad)",          { XX } },
6747     { "(bad)",          { XX } },
6748     /* 10 */
6749     { "(bad)",          { XX } },
6750     { "(bad)",          { XX } },
6751     { "(bad)",          { XX } },
6752     { "(bad)",          { XX } },
6753     { "(bad)",          { XX } },
6754     { "(bad)",          { XX } },
6755     { "(bad)",          { XX } },
6756     { "(bad)",          { XX } },
6757     /* 18 */
6758     { "(bad)",          { XX } },
6759     { "(bad)",          { XX } },
6760     { "(bad)",          { XX } },
6761     { "(bad)",          { XX } },
6762     { "(bad)",          { XX } },
6763     { "(bad)",          { XX } },
6764     { "(bad)",          { XX } },
6765     { "(bad)",          { XX } },
6766     /* 20 */
6767     { "(bad)",          { XX } },
6768     { "(bad)",          { XX } },
6769     { "(bad)",          { XX } },
6770     { "(bad)",          { XX } },
6771     { "(bad)",          { XX } },
6772     { "(bad)",          { XX } },
6773     { "(bad)",          { XX } },
6774     { "(bad)",          { XX } },
6775     /* 28 */
6776     { "(bad)",          { XX } },
6777     { "(bad)",          { XX } },
6778     { "(bad)",          { XX } },
6779     { "(bad)",          { XX } },
6780     { "(bad)",          { XX } },
6781     { "(bad)",          { XX } },
6782     { "(bad)",          { XX } },
6783     { "(bad)",          { XX } },
6784     /* 30 */
6785     { "(bad)",          { XX } },
6786     { "(bad)",          { XX } },
6787     { "(bad)",          { XX } },
6788     { "(bad)",          { XX } },
6789     { "(bad)",          { XX } },
6790     { "(bad)",          { XX } },
6791     { "(bad)",          { XX } },
6792     { "(bad)",          { XX } },
6793     /* 38 */
6794     { "(bad)",          { XX } },
6795     { "(bad)",          { XX } },
6796     { "(bad)",          { XX } },
6797     { "(bad)",          { XX } },
6798     { "(bad)",          { XX } },
6799     { "(bad)",          { XX } },
6800     { "(bad)",          { XX } },
6801     { "(bad)",          { XX } },
6802     /* 40 */
6803     { "protb",          { XM, EXq, Ib } },
6804     { "protw",          { XM, EXq, Ib } },
6805     { "protd",          { XM, EXq, Ib } },
6806     { "protq",          { XM, EXq, Ib } },
6807     { "pshlb",          { XM, EXq, Ib } },
6808     { "pshlw",          { XM, EXq, Ib } },
6809     { "pshld",          { XM, EXq, Ib } },
6810     { "pshlq",          { XM, EXq, Ib } },
6811     /* 48 */
6812     { "pshab",          { XM, EXq, Ib } },
6813     { "pshaw",          { XM, EXq, Ib } },
6814     { "pshad",          { XM, EXq, Ib } },
6815     { "pshaq",          { XM, EXq, Ib } },
6816     { "(bad)",          { XX } },
6817     { "(bad)",          { XX } },
6818     { "(bad)",          { XX } },
6819     { "(bad)",          { XX } },
6820     /* 50 */
6821     { "(bad)",          { XX } },
6822     { "(bad)",          { XX } },
6823     { "(bad)",          { XX } },
6824     { "(bad)",          { XX } },
6825     { "(bad)",          { XX } },
6826     { "(bad)",          { XX } },
6827     { "(bad)",          { XX } },
6828     { "(bad)",          { XX } },
6829     /* 58 */
6830     { "(bad)",          { XX } },
6831     { "(bad)",          { XX } },
6832     { "(bad)",          { XX } },
6833     { "(bad)",          { XX } },
6834     { "(bad)",          { XX } },
6835     { "(bad)",          { XX } },
6836     { "(bad)",          { XX } },
6837     { "(bad)",          { XX } },
6838     /* 60 */
6839     { "(bad)",          { XX } },
6840     { "(bad)",          { XX } },
6841     { "(bad)",          { XX } },
6842     { "(bad)",          { XX } },
6843     { "(bad)",          { XX } },
6844     { "(bad)",          { XX } },
6845     { "(bad)",          { XX } },
6846     { "(bad)",          { XX } },
6847     /* 68 */
6848     { "(bad)",          { XX } },
6849     { "(bad)",          { XX } },
6850     { "(bad)",          { XX } },
6851     { "(bad)",          { XX } },
6852     { "(bad)",          { XX } },
6853     { "(bad)",          { XX } },
6854     { "(bad)",          { XX } },
6855     { "(bad)",          { XX } },
6856     /* 70 */
6857     { "(bad)",          { XX } },
6858     { "(bad)",          { XX } },
6859     { "(bad)",          { XX } },
6860     { "(bad)",          { XX } },
6861     { "(bad)",          { XX } },
6862     { "(bad)",          { XX } },
6863     { "(bad)",          { XX } },
6864     { "(bad)",          { XX } },
6865     /* 78 */
6866     { "(bad)",          { XX } },
6867     { "(bad)",          { XX } },
6868     { "(bad)",          { XX } },
6869     { "(bad)",          { XX } },
6870     { "(bad)",          { XX } },
6871     { "(bad)",          { XX } },
6872     { "(bad)",          { XX } },
6873     { "(bad)",          { XX } },
6874     /* 80 */
6875     { "(bad)",          { XX } },
6876     { "(bad)",          { XX } },
6877     { "(bad)",          { XX } },
6878     { "(bad)",          { XX } },
6879     { "(bad)",          { XX } },
6880     { "(bad)",          { XX } },
6881     { "(bad)",          { XX } },
6882     { "(bad)",          { XX } },
6883     /* 88 */
6884     { "(bad)",          { XX } },
6885     { "(bad)",          { XX } },
6886     { "(bad)",          { XX } },
6887     { "(bad)",          { XX } },
6888     { "(bad)",          { XX } },
6889     { "(bad)",          { XX } },
6890     { "(bad)",          { XX } },
6891     { "(bad)",          { XX } },
6892     /* 90 */
6893     { "(bad)",          { XX } },
6894     { "(bad)",          { XX } },
6895     { "(bad)",          { XX } },
6896     { "(bad)",          { XX } },
6897     { "(bad)",          { XX } },
6898     { "(bad)",          { XX } },
6899     { "(bad)",          { XX } },
6900     { "(bad)",          { XX } },
6901     /* 98 */
6902     { "(bad)",          { XX } },
6903     { "(bad)",          { XX } },
6904     { "(bad)",          { XX } },
6905     { "(bad)",          { XX } },
6906     { "(bad)",          { XX } },
6907     { "(bad)",          { XX } },
6908     { "(bad)",          { XX } },
6909     { "(bad)",          { XX } },
6910     /* a0 */
6911     { "(bad)",          { XX } },
6912     { "(bad)",          { XX } },
6913     { "(bad)",          { XX } },
6914     { "(bad)",          { XX } },
6915     { "(bad)",          { XX } },
6916     { "(bad)",          { XX } },
6917     { "(bad)",          { XX } },
6918     { "(bad)",          { XX } },
6919     /* a8 */
6920     { "(bad)",          { XX } },
6921     { "(bad)",          { XX } },
6922     { "(bad)",          { XX } },
6923     { "(bad)",          { XX } },
6924     { "(bad)",          { XX } },
6925     { "(bad)",          { XX } },
6926     { "(bad)",          { XX } },
6927     { "(bad)",          { XX } },
6928     /* b0 */
6929     { "(bad)",          { XX } },
6930     { "(bad)",          { XX } },
6931     { "(bad)",          { XX } },
6932     { "(bad)",          { XX } },
6933     { "(bad)",          { XX } },
6934     { "(bad)",          { XX } },
6935     { "(bad)",          { XX } },
6936     { "(bad)",          { XX } },
6937     /* b8 */
6938     { "(bad)",          { XX } },
6939     { "(bad)",          { XX } },
6940     { "(bad)",          { XX } },
6941     { "(bad)",          { XX } },
6942     { "(bad)",          { XX } },
6943     { "(bad)",          { XX } },
6944     { "(bad)",          { XX } },
6945     { "(bad)",          { XX } },
6946     /* c0 */
6947     { "(bad)",          { XX } },
6948     { "(bad)",          { XX } },
6949     { "(bad)",          { XX } },
6950     { "(bad)",          { XX } },
6951     { "(bad)",          { XX } },
6952     { "(bad)",          { XX } },
6953     { "(bad)",          { XX } },
6954     { "(bad)",          { XX } },
6955     /* c8 */
6956     { "(bad)",          { XX } },
6957     { "(bad)",          { XX } },
6958     { "(bad)",          { XX } },
6959     { "(bad)",          { XX } },
6960     { "(bad)",          { XX } },
6961     { "(bad)",          { XX } },
6962     { "(bad)",          { XX } },
6963     { "(bad)",          { XX } },
6964     /* d0 */
6965     { "(bad)",          { XX } },
6966     { "(bad)",          { XX } },
6967     { "(bad)",          { XX } },
6968     { "(bad)",          { XX } },
6969     { "(bad)",          { XX } },
6970     { "(bad)",          { XX } },
6971     { "(bad)",          { XX } },
6972     { "(bad)",          { XX } },
6973     /* d8 */
6974     { "(bad)",          { XX } },
6975     { "(bad)",          { XX } },
6976     { "(bad)",          { XX } },
6977     { "(bad)",          { XX } },
6978     { "(bad)",          { XX } },
6979     { "(bad)",          { XX } },
6980     { "(bad)",          { XX } },
6981     { "(bad)",          { XX } },
6982     /* e0 */
6983     { "(bad)",          { XX } },
6984     { "(bad)",          { XX } },
6985     { "(bad)",          { XX } },
6986     { "(bad)",          { XX } },
6987     { "(bad)",          { XX } },
6988     { "(bad)",          { XX } },
6989     { "(bad)",          { XX } },
6990     { "(bad)",          { XX } },
6991     /* e8 */
6992     { "(bad)",          { XX } },
6993     { "(bad)",          { XX } },
6994     { "(bad)",          { XX } },
6995     { "(bad)",          { XX } },
6996     { "(bad)",          { XX } },
6997     { "(bad)",          { XX } },
6998     { "(bad)",          { XX } },
6999     { "(bad)",          { XX } },
7000     /* f0 */
7001     { "(bad)",          { XX } },
7002     { "(bad)",          { XX } },
7003     { "(bad)",          { XX } },
7004     { "(bad)",          { XX } },
7005     { "(bad)",          { XX } },
7006     { "(bad)",          { XX } },
7007     { "(bad)",          { XX } },
7008     { "(bad)",          { XX } },
7009     /* f8 */
7010     { "(bad)",          { XX } },
7011     { "(bad)",          { XX } },
7012     { "(bad)",          { XX } },
7013     { "(bad)",          { XX } },
7014     { "(bad)",          { XX } },
7015     { "(bad)",          { XX } },
7016     { "(bad)",          { XX } },
7017     { "(bad)",          { XX } },
7018   },
7019 };
7020
7021 static const struct dis386 vex_table[][256] = {
7022   /* VEX_0F */
7023   {
7024     /* 00 */
7025     { "(bad)",          { XX } },
7026     { "(bad)",          { XX } },
7027     { "(bad)",          { XX } },
7028     { "(bad)",          { XX } },
7029     { "(bad)",          { XX } },
7030     { "(bad)",          { XX } },
7031     { "(bad)",          { XX } },
7032     { "(bad)",          { XX } },
7033     /* 08 */
7034     { "(bad)",          { XX } },
7035     { "(bad)",          { XX } },
7036     { "(bad)",          { XX } },
7037     { "(bad)",          { XX } },
7038     { "(bad)",          { XX } },
7039     { "(bad)",          { XX } },
7040     { "(bad)",          { XX } },
7041     { "(bad)",          { XX } },
7042     /* 10 */
7043     { PREFIX_TABLE (PREFIX_VEX_10) },
7044     { PREFIX_TABLE (PREFIX_VEX_11) },
7045     { PREFIX_TABLE (PREFIX_VEX_12) },
7046     { MOD_TABLE (MOD_VEX_13) },
7047     { "vunpcklpX",      { XM, Vex, EXx } },
7048     { "vunpckhpX",      { XM, Vex, EXx } },
7049     { PREFIX_TABLE (PREFIX_VEX_16) },
7050     { MOD_TABLE (MOD_VEX_17) },
7051     /* 18 */
7052     { "(bad)",          { XX } },
7053     { "(bad)",          { XX } },
7054     { "(bad)",          { XX } },
7055     { "(bad)",          { XX } },
7056     { "(bad)",          { XX } },
7057     { "(bad)",          { XX } },
7058     { "(bad)",          { XX } },
7059     { "(bad)",          { XX } },
7060     /* 20 */
7061     { "(bad)",          { XX } },
7062     { "(bad)",          { XX } },
7063     { "(bad)",          { XX } },
7064     { "(bad)",          { XX } },
7065     { "(bad)",          { XX } },
7066     { "(bad)",          { XX } },
7067     { "(bad)",          { XX } },
7068     { "(bad)",          { XX } },
7069     /* 28 */
7070     { "vmovapX",        { XM, EXx } },
7071     { "vmovapX",        { EXxS, XM } },
7072     { PREFIX_TABLE (PREFIX_VEX_2A) },
7073     { MOD_TABLE (MOD_VEX_2B) },
7074     { PREFIX_TABLE (PREFIX_VEX_2C) },
7075     { PREFIX_TABLE (PREFIX_VEX_2D) },
7076     { PREFIX_TABLE (PREFIX_VEX_2E) },
7077     { PREFIX_TABLE (PREFIX_VEX_2F) },
7078     /* 30 */
7079     { "(bad)",          { XX } },
7080     { "(bad)",          { XX } },
7081     { "(bad)",          { XX } },
7082     { "(bad)",          { XX } },
7083     { "(bad)",          { XX } },
7084     { "(bad)",          { XX } },
7085     { "(bad)",          { XX } },
7086     { "(bad)",          { XX } },
7087     /* 38 */
7088     { "(bad)",          { XX } },
7089     { "(bad)",          { XX } },
7090     { "(bad)",          { XX } },
7091     { "(bad)",          { XX } },
7092     { "(bad)",          { XX } },
7093     { "(bad)",          { XX } },
7094     { "(bad)",          { XX } },
7095     { "(bad)",          { XX } },
7096     /* 40 */
7097     { "(bad)",          { XX } },
7098     { "(bad)",          { XX } },
7099     { "(bad)",          { XX } },
7100     { "(bad)",          { XX } },
7101     { "(bad)",          { XX } },
7102     { "(bad)",          { XX } },
7103     { "(bad)",          { XX } },
7104     { "(bad)",          { XX } },
7105     /* 48 */
7106     { "(bad)",          { XX } },
7107     { "(bad)",          { XX } },
7108     { "(bad)",          { XX } },
7109     { "(bad)",          { XX } },
7110     { "(bad)",          { XX } },
7111     { "(bad)",          { XX } },
7112     { "(bad)",          { XX } },
7113     { "(bad)",          { XX } },
7114     /* 50 */
7115     { MOD_TABLE (MOD_VEX_51) },
7116     { PREFIX_TABLE (PREFIX_VEX_51) },
7117     { PREFIX_TABLE (PREFIX_VEX_52) },
7118     { PREFIX_TABLE (PREFIX_VEX_53) },
7119     { "vandpX",         { XM, Vex, EXx } },
7120     { "vandnpX",        { XM, Vex, EXx } },
7121     { "vorpX",          { XM, Vex, EXx } },
7122     { "vxorpX",         { XM, Vex, EXx } },
7123     /* 58 */
7124     { PREFIX_TABLE (PREFIX_VEX_58) },
7125     { PREFIX_TABLE (PREFIX_VEX_59) },
7126     { PREFIX_TABLE (PREFIX_VEX_5A) },
7127     { PREFIX_TABLE (PREFIX_VEX_5B) },
7128     { PREFIX_TABLE (PREFIX_VEX_5C) },
7129     { PREFIX_TABLE (PREFIX_VEX_5D) },
7130     { PREFIX_TABLE (PREFIX_VEX_5E) },
7131     { PREFIX_TABLE (PREFIX_VEX_5F) },
7132     /* 60 */
7133     { PREFIX_TABLE (PREFIX_VEX_60) },
7134     { PREFIX_TABLE (PREFIX_VEX_61) },
7135     { PREFIX_TABLE (PREFIX_VEX_62) },
7136     { PREFIX_TABLE (PREFIX_VEX_63) },
7137     { PREFIX_TABLE (PREFIX_VEX_64) },
7138     { PREFIX_TABLE (PREFIX_VEX_65) },
7139     { PREFIX_TABLE (PREFIX_VEX_66) },
7140     { PREFIX_TABLE (PREFIX_VEX_67) },
7141     /* 68 */
7142     { PREFIX_TABLE (PREFIX_VEX_68) },
7143     { PREFIX_TABLE (PREFIX_VEX_69) },
7144     { PREFIX_TABLE (PREFIX_VEX_6A) },
7145     { PREFIX_TABLE (PREFIX_VEX_6B) },
7146     { PREFIX_TABLE (PREFIX_VEX_6C) },
7147     { PREFIX_TABLE (PREFIX_VEX_6D) },
7148     { PREFIX_TABLE (PREFIX_VEX_6E) },
7149     { PREFIX_TABLE (PREFIX_VEX_6F) },
7150     /* 70 */
7151     { PREFIX_TABLE (PREFIX_VEX_70) },
7152     { REG_TABLE (REG_VEX_71) },
7153     { REG_TABLE (REG_VEX_72) },
7154     { REG_TABLE (REG_VEX_73) },
7155     { PREFIX_TABLE (PREFIX_VEX_74) },
7156     { PREFIX_TABLE (PREFIX_VEX_75) },
7157     { PREFIX_TABLE (PREFIX_VEX_76) },
7158     { PREFIX_TABLE (PREFIX_VEX_77) },
7159     /* 78 */
7160     { "(bad)",          { XX } },
7161     { "(bad)",          { XX } },
7162     { "(bad)",          { XX } },
7163     { "(bad)",          { XX } },
7164     { PREFIX_TABLE (PREFIX_VEX_7C) },
7165     { PREFIX_TABLE (PREFIX_VEX_7D) },
7166     { PREFIX_TABLE (PREFIX_VEX_7E) },
7167     { PREFIX_TABLE (PREFIX_VEX_7F) },
7168     /* 80 */
7169     { "(bad)",          { XX } },
7170     { "(bad)",          { XX } },
7171     { "(bad)",          { XX } },
7172     { "(bad)",          { XX } },
7173     { "(bad)",          { XX } },
7174     { "(bad)",          { XX } },
7175     { "(bad)",          { XX } },
7176     { "(bad)",          { XX } },
7177     /* 88 */
7178     { "(bad)",          { XX } },
7179     { "(bad)",          { XX } },
7180     { "(bad)",          { XX } },
7181     { "(bad)",          { XX } },
7182     { "(bad)",          { XX } },
7183     { "(bad)",          { XX } },
7184     { "(bad)",          { XX } },
7185     { "(bad)",          { XX } },
7186     /* 90 */
7187     { "(bad)",          { XX } },
7188     { "(bad)",          { XX } },
7189     { "(bad)",          { XX } },
7190     { "(bad)",          { XX } },
7191     { "(bad)",          { XX } },
7192     { "(bad)",          { XX } },
7193     { "(bad)",          { XX } },
7194     { "(bad)",          { XX } },
7195     /* 98 */
7196     { "(bad)",          { XX } },
7197     { "(bad)",          { XX } },
7198     { "(bad)",          { XX } },
7199     { "(bad)",          { XX } },
7200     { "(bad)",          { XX } },
7201     { "(bad)",          { XX } },
7202     { "(bad)",          { XX } },
7203     { "(bad)",          { XX } },
7204     /* a0 */
7205     { "(bad)",          { XX } },
7206     { "(bad)",          { XX } },
7207     { "(bad)",          { XX } },
7208     { "(bad)",          { XX } },
7209     { "(bad)",          { XX } },
7210     { "(bad)",          { XX } },
7211     { "(bad)",          { XX } },
7212     { "(bad)",          { XX } },
7213     /* a8 */
7214     { "(bad)",          { XX } },
7215     { "(bad)",          { XX } },
7216     { "(bad)",          { XX } },
7217     { "(bad)",          { XX } },
7218     { "(bad)",          { XX } },
7219     { "(bad)",          { XX } },
7220     { REG_TABLE (REG_VEX_AE) },
7221     { "(bad)",          { XX } },
7222     /* b0 */
7223     { "(bad)",          { XX } },
7224     { "(bad)",          { XX } },
7225     { "(bad)",          { XX } },
7226     { "(bad)",          { XX } },
7227     { "(bad)",          { XX } },
7228     { "(bad)",          { XX } },
7229     { "(bad)",          { XX } },
7230     { "(bad)",          { XX } },
7231     /* b8 */
7232     { "(bad)",          { XX } },
7233     { "(bad)",          { XX } },
7234     { "(bad)",          { XX } },
7235     { "(bad)",          { XX } },
7236     { "(bad)",          { XX } },
7237     { "(bad)",          { XX } },
7238     { "(bad)",          { XX } },
7239     { "(bad)",          { XX } },
7240     /* c0 */
7241     { "(bad)",          { XX } },
7242     { "(bad)",          { XX } },
7243     { PREFIX_TABLE (PREFIX_VEX_C2) },
7244     { "(bad)",          { XX } },
7245     { PREFIX_TABLE (PREFIX_VEX_C4) },
7246     { PREFIX_TABLE (PREFIX_VEX_C5) },
7247     { "vshufpX",        { XM, Vex, EXx, Ib } },
7248     { "(bad)",          { XX } },
7249     /* c8 */
7250     { "(bad)",          { XX } },
7251     { "(bad)",          { XX } },
7252     { "(bad)",          { XX } },
7253     { "(bad)",          { XX } },
7254     { "(bad)",          { XX } },
7255     { "(bad)",          { XX } },
7256     { "(bad)",          { XX } },
7257     { "(bad)",          { XX } },
7258     /* d0 */
7259     { PREFIX_TABLE (PREFIX_VEX_D0) },
7260     { PREFIX_TABLE (PREFIX_VEX_D1) },
7261     { PREFIX_TABLE (PREFIX_VEX_D2) },
7262     { PREFIX_TABLE (PREFIX_VEX_D3) },
7263     { PREFIX_TABLE (PREFIX_VEX_D4) },
7264     { PREFIX_TABLE (PREFIX_VEX_D5) },
7265     { PREFIX_TABLE (PREFIX_VEX_D6) },
7266     { PREFIX_TABLE (PREFIX_VEX_D7) },
7267     /* d8 */
7268     { PREFIX_TABLE (PREFIX_VEX_D8) },
7269     { PREFIX_TABLE (PREFIX_VEX_D9) },
7270     { PREFIX_TABLE (PREFIX_VEX_DA) },
7271     { PREFIX_TABLE (PREFIX_VEX_DB) },
7272     { PREFIX_TABLE (PREFIX_VEX_DC) },
7273     { PREFIX_TABLE (PREFIX_VEX_DD) },
7274     { PREFIX_TABLE (PREFIX_VEX_DE) },
7275     { PREFIX_TABLE (PREFIX_VEX_DF) },
7276     /* e0 */
7277     { PREFIX_TABLE (PREFIX_VEX_E0) },
7278     { PREFIX_TABLE (PREFIX_VEX_E1) },
7279     { PREFIX_TABLE (PREFIX_VEX_E2) },
7280     { PREFIX_TABLE (PREFIX_VEX_E3) },
7281     { PREFIX_TABLE (PREFIX_VEX_E4) },
7282     { PREFIX_TABLE (PREFIX_VEX_E5) },
7283     { PREFIX_TABLE (PREFIX_VEX_E6) },
7284     { PREFIX_TABLE (PREFIX_VEX_E7) },
7285     /* e8 */
7286     { PREFIX_TABLE (PREFIX_VEX_E8) },
7287     { PREFIX_TABLE (PREFIX_VEX_E9) },
7288     { PREFIX_TABLE (PREFIX_VEX_EA) },
7289     { PREFIX_TABLE (PREFIX_VEX_EB) },
7290     { PREFIX_TABLE (PREFIX_VEX_EC) },
7291     { PREFIX_TABLE (PREFIX_VEX_ED) },
7292     { PREFIX_TABLE (PREFIX_VEX_EE) },
7293     { PREFIX_TABLE (PREFIX_VEX_EF) },
7294     /* f0 */
7295     { PREFIX_TABLE (PREFIX_VEX_F0) },
7296     { PREFIX_TABLE (PREFIX_VEX_F1) },
7297     { PREFIX_TABLE (PREFIX_VEX_F2) },
7298     { PREFIX_TABLE (PREFIX_VEX_F3) },
7299     { PREFIX_TABLE (PREFIX_VEX_F4) },
7300     { PREFIX_TABLE (PREFIX_VEX_F5) },
7301     { PREFIX_TABLE (PREFIX_VEX_F6) },
7302     { PREFIX_TABLE (PREFIX_VEX_F7) },
7303     /* f8 */
7304     { PREFIX_TABLE (PREFIX_VEX_F8) },
7305     { PREFIX_TABLE (PREFIX_VEX_F9) },
7306     { PREFIX_TABLE (PREFIX_VEX_FA) },
7307     { PREFIX_TABLE (PREFIX_VEX_FB) },
7308     { PREFIX_TABLE (PREFIX_VEX_FC) },
7309     { PREFIX_TABLE (PREFIX_VEX_FD) },
7310     { PREFIX_TABLE (PREFIX_VEX_FE) },
7311     { "(bad)",          { XX } },
7312   },
7313   /* VEX_0F38 */
7314   {
7315     /* 00 */
7316     { PREFIX_TABLE (PREFIX_VEX_3800) },
7317     { PREFIX_TABLE (PREFIX_VEX_3801) },
7318     { PREFIX_TABLE (PREFIX_VEX_3802) },
7319     { PREFIX_TABLE (PREFIX_VEX_3803) },
7320     { PREFIX_TABLE (PREFIX_VEX_3804) },
7321     { PREFIX_TABLE (PREFIX_VEX_3805) },
7322     { PREFIX_TABLE (PREFIX_VEX_3806) },
7323     { PREFIX_TABLE (PREFIX_VEX_3807) },
7324     /* 08 */
7325     { PREFIX_TABLE (PREFIX_VEX_3808) },
7326     { PREFIX_TABLE (PREFIX_VEX_3809) },
7327     { PREFIX_TABLE (PREFIX_VEX_380A) },
7328     { PREFIX_TABLE (PREFIX_VEX_380B) },
7329     { PREFIX_TABLE (PREFIX_VEX_380C) },
7330     { PREFIX_TABLE (PREFIX_VEX_380D) },
7331     { PREFIX_TABLE (PREFIX_VEX_380E) },
7332     { PREFIX_TABLE (PREFIX_VEX_380F) },
7333     /* 10 */
7334     { "(bad)",          { XX } },
7335     { "(bad)",          { XX } },
7336     { "(bad)",          { XX } },
7337     { "(bad)",          { XX } },
7338     { "(bad)",          { XX } },
7339     { "(bad)",          { XX } },
7340     { "(bad)",          { XX } },
7341     { PREFIX_TABLE (PREFIX_VEX_3817) },
7342     /* 18 */
7343     { PREFIX_TABLE (PREFIX_VEX_3818) },
7344     { PREFIX_TABLE (PREFIX_VEX_3819) },
7345     { PREFIX_TABLE (PREFIX_VEX_381A) },
7346     { "(bad)",          { XX } },
7347     { PREFIX_TABLE (PREFIX_VEX_381C) },
7348     { PREFIX_TABLE (PREFIX_VEX_381D) },
7349     { PREFIX_TABLE (PREFIX_VEX_381E) },
7350     { "(bad)",          { XX } },
7351     /* 20 */
7352     { PREFIX_TABLE (PREFIX_VEX_3820) },
7353     { PREFIX_TABLE (PREFIX_VEX_3821) },
7354     { PREFIX_TABLE (PREFIX_VEX_3822) },
7355     { PREFIX_TABLE (PREFIX_VEX_3823) },
7356     { PREFIX_TABLE (PREFIX_VEX_3824) },
7357     { PREFIX_TABLE (PREFIX_VEX_3825) },
7358     { "(bad)",          { XX } },
7359     { "(bad)",          { XX } },
7360     /* 28 */
7361     { PREFIX_TABLE (PREFIX_VEX_3828) },
7362     { PREFIX_TABLE (PREFIX_VEX_3829) },
7363     { PREFIX_TABLE (PREFIX_VEX_382A) },
7364     { PREFIX_TABLE (PREFIX_VEX_382B) },
7365     { PREFIX_TABLE (PREFIX_VEX_382C) },
7366     { PREFIX_TABLE (PREFIX_VEX_382D) },
7367     { PREFIX_TABLE (PREFIX_VEX_382E) },
7368     { PREFIX_TABLE (PREFIX_VEX_382F) },
7369     /* 30 */
7370     { PREFIX_TABLE (PREFIX_VEX_3830) },
7371     { PREFIX_TABLE (PREFIX_VEX_3831) },
7372     { PREFIX_TABLE (PREFIX_VEX_3832) },
7373     { PREFIX_TABLE (PREFIX_VEX_3833) },
7374     { PREFIX_TABLE (PREFIX_VEX_3834) },
7375     { PREFIX_TABLE (PREFIX_VEX_3835) },
7376     { "(bad)",          { XX } },
7377     { PREFIX_TABLE (PREFIX_VEX_3837) },
7378     /* 38 */
7379     { PREFIX_TABLE (PREFIX_VEX_3838) },
7380     { PREFIX_TABLE (PREFIX_VEX_3839) },
7381     { PREFIX_TABLE (PREFIX_VEX_383A) },
7382     { PREFIX_TABLE (PREFIX_VEX_383B) },
7383     { PREFIX_TABLE (PREFIX_VEX_383C) },
7384     { PREFIX_TABLE (PREFIX_VEX_383D) },
7385     { PREFIX_TABLE (PREFIX_VEX_383E) },
7386     { PREFIX_TABLE (PREFIX_VEX_383F) },
7387     /* 40 */
7388     { PREFIX_TABLE (PREFIX_VEX_3840) },
7389     { PREFIX_TABLE (PREFIX_VEX_3841) },
7390     { "(bad)",          { XX } },
7391     { "(bad)",          { XX } },
7392     { "(bad)",          { XX } },
7393     { "(bad)",          { XX } },
7394     { "(bad)",          { XX } },
7395     { "(bad)",          { XX } },
7396     /* 48 */
7397     { "(bad)",          { XX } },
7398     { "(bad)",          { XX } },
7399     { "(bad)",          { XX } },
7400     { "(bad)",          { XX } },
7401     { "(bad)",          { XX } },
7402     { "(bad)",          { XX } },
7403     { "(bad)",          { XX } },
7404     { "(bad)",          { XX } },
7405     /* 50 */
7406     { "(bad)",          { XX } },
7407     { "(bad)",          { XX } },
7408     { "(bad)",          { XX } },
7409     { "(bad)",          { XX } },
7410     { "(bad)",          { XX } },
7411     { "(bad)",          { XX } },
7412     { "(bad)",          { XX } },
7413     { "(bad)",          { XX } },
7414     /* 58 */
7415     { "(bad)",          { XX } },
7416     { "(bad)",          { XX } },
7417     { "(bad)",          { XX } },
7418     { "(bad)",          { XX } },
7419     { "(bad)",          { XX } },
7420     { "(bad)",          { XX } },
7421     { "(bad)",          { XX } },
7422     { "(bad)",          { XX } },
7423     /* 60 */
7424     { "(bad)",          { XX } },
7425     { "(bad)",          { XX } },
7426     { "(bad)",          { XX } },
7427     { "(bad)",          { XX } },
7428     { "(bad)",          { XX } },
7429     { "(bad)",          { XX } },
7430     { "(bad)",          { XX } },
7431     { "(bad)",          { XX } },
7432     /* 68 */
7433     { "(bad)",          { XX } },
7434     { "(bad)",          { XX } },
7435     { "(bad)",          { XX } },
7436     { "(bad)",          { XX } },
7437     { "(bad)",          { XX } },
7438     { "(bad)",          { XX } },
7439     { "(bad)",          { XX } },
7440     { "(bad)",          { XX } },
7441     /* 70 */
7442     { "(bad)",          { XX } },
7443     { "(bad)",          { XX } },
7444     { "(bad)",          { XX } },
7445     { "(bad)",          { XX } },
7446     { "(bad)",          { XX } },
7447     { "(bad)",          { XX } },
7448     { "(bad)",          { XX } },
7449     { "(bad)",          { XX } },
7450     /* 78 */
7451     { "(bad)",          { XX } },
7452     { "(bad)",          { XX } },
7453     { "(bad)",          { XX } },
7454     { "(bad)",          { XX } },
7455     { "(bad)",          { XX } },
7456     { "(bad)",          { XX } },
7457     { "(bad)",          { XX } },
7458     { "(bad)",          { XX } },
7459     /* 80 */
7460     { "(bad)",          { XX } },
7461     { "(bad)",          { XX } },
7462     { "(bad)",          { XX } },
7463     { "(bad)",          { XX } },
7464     { "(bad)",          { XX } },
7465     { "(bad)",          { XX } },
7466     { "(bad)",          { XX } },
7467     { "(bad)",          { XX } },
7468     /* 88 */
7469     { "(bad)",          { XX } },
7470     { "(bad)",          { XX } },
7471     { "(bad)",          { XX } },
7472     { "(bad)",          { XX } },
7473     { "(bad)",          { XX } },
7474     { "(bad)",          { XX } },
7475     { "(bad)",          { XX } },
7476     { "(bad)",          { XX } },
7477     /* 90 */
7478     { "(bad)",          { XX } },
7479     { "(bad)",          { XX } },
7480     { "(bad)",          { XX } },
7481     { "(bad)",          { XX } },
7482     { "(bad)",          { XX } },
7483     { "(bad)",          { XX } },
7484     { PREFIX_TABLE (PREFIX_VEX_3896) },
7485     { PREFIX_TABLE (PREFIX_VEX_3897) },
7486     /* 98 */
7487     { PREFIX_TABLE (PREFIX_VEX_3898) },
7488     { PREFIX_TABLE (PREFIX_VEX_3899) },
7489     { PREFIX_TABLE (PREFIX_VEX_389A) },
7490     { PREFIX_TABLE (PREFIX_VEX_389B) },
7491     { PREFIX_TABLE (PREFIX_VEX_389C) },
7492     { PREFIX_TABLE (PREFIX_VEX_389D) },
7493     { PREFIX_TABLE (PREFIX_VEX_389E) },
7494     { PREFIX_TABLE (PREFIX_VEX_389F) },
7495     /* a0 */
7496     { "(bad)",          { XX } },
7497     { "(bad)",          { XX } },
7498     { "(bad)",          { XX } },
7499     { "(bad)",          { XX } },
7500     { "(bad)",          { XX } },
7501     { "(bad)",          { XX } },
7502     { PREFIX_TABLE (PREFIX_VEX_38A6) },
7503     { PREFIX_TABLE (PREFIX_VEX_38A7) },
7504     /* a8 */
7505     { PREFIX_TABLE (PREFIX_VEX_38A8) },
7506     { PREFIX_TABLE (PREFIX_VEX_38A9) },
7507     { PREFIX_TABLE (PREFIX_VEX_38AA) },
7508     { PREFIX_TABLE (PREFIX_VEX_38AB) },
7509     { PREFIX_TABLE (PREFIX_VEX_38AC) },
7510     { PREFIX_TABLE (PREFIX_VEX_38AD) },
7511     { PREFIX_TABLE (PREFIX_VEX_38AE) },
7512     { PREFIX_TABLE (PREFIX_VEX_38AF) },
7513     /* b0 */
7514     { "(bad)",          { XX } },
7515     { "(bad)",          { XX } },
7516     { "(bad)",          { XX } },
7517     { "(bad)",          { XX } },
7518     { "(bad)",          { XX } },
7519     { "(bad)",          { XX } },
7520     { PREFIX_TABLE (PREFIX_VEX_38B6) },
7521     { PREFIX_TABLE (PREFIX_VEX_38B7) },
7522     /* b8 */
7523     { PREFIX_TABLE (PREFIX_VEX_38B8) },
7524     { PREFIX_TABLE (PREFIX_VEX_38B9) },
7525     { PREFIX_TABLE (PREFIX_VEX_38BA) },
7526     { PREFIX_TABLE (PREFIX_VEX_38BB) },
7527     { PREFIX_TABLE (PREFIX_VEX_38BC) },
7528     { PREFIX_TABLE (PREFIX_VEX_38BD) },
7529     { PREFIX_TABLE (PREFIX_VEX_38BE) },
7530     { PREFIX_TABLE (PREFIX_VEX_38BF) },
7531     /* c0 */
7532     { "(bad)",          { XX } },
7533     { "(bad)",          { XX } },
7534     { "(bad)",          { XX } },
7535     { "(bad)",          { XX } },
7536     { "(bad)",          { XX } },
7537     { "(bad)",          { XX } },
7538     { "(bad)",          { XX } },
7539     { "(bad)",          { XX } },
7540     /* c8 */
7541     { "(bad)",          { XX } },
7542     { "(bad)",          { XX } },
7543     { "(bad)",          { XX } },
7544     { "(bad)",          { XX } },
7545     { "(bad)",          { XX } },
7546     { "(bad)",          { XX } },
7547     { "(bad)",          { XX } },
7548     { "(bad)",          { XX } },
7549     /* d0 */
7550     { "(bad)",          { XX } },
7551     { "(bad)",          { XX } },
7552     { "(bad)",          { XX } },
7553     { "(bad)",          { XX } },
7554     { "(bad)",          { XX } },
7555     { "(bad)",          { XX } },
7556     { "(bad)",          { XX } },
7557     { "(bad)",          { XX } },
7558     /* d8 */
7559     { "(bad)",          { XX } },
7560     { "(bad)",          { XX } },
7561     { "(bad)",          { XX } },
7562     { PREFIX_TABLE (PREFIX_VEX_38DB) },
7563     { PREFIX_TABLE (PREFIX_VEX_38DC) },
7564     { PREFIX_TABLE (PREFIX_VEX_38DD) },
7565     { PREFIX_TABLE (PREFIX_VEX_38DE) },
7566     { PREFIX_TABLE (PREFIX_VEX_38DF) },
7567     /* e0 */
7568     { "(bad)",          { XX } },
7569     { "(bad)",          { XX } },
7570     { "(bad)",          { XX } },
7571     { "(bad)",          { XX } },
7572     { "(bad)",          { XX } },
7573     { "(bad)",          { XX } },
7574     { "(bad)",          { XX } },
7575     { "(bad)",          { XX } },
7576     /* e8 */
7577     { "(bad)",          { XX } },
7578     { "(bad)",          { XX } },
7579     { "(bad)",          { XX } },
7580     { "(bad)",          { XX } },
7581     { "(bad)",          { XX } },
7582     { "(bad)",          { XX } },
7583     { "(bad)",          { XX } },
7584     { "(bad)",          { XX } },
7585     /* f0 */
7586     { "(bad)",          { XX } },
7587     { "(bad)",          { XX } },
7588     { "(bad)",          { XX } },
7589     { "(bad)",          { XX } },
7590     { "(bad)",          { XX } },
7591     { "(bad)",          { XX } },
7592     { "(bad)",          { XX } },
7593     { "(bad)",          { XX } },
7594     /* f8 */
7595     { "(bad)",          { XX } },
7596     { "(bad)",          { XX } },
7597     { "(bad)",          { XX } },
7598     { "(bad)",          { XX } },
7599     { "(bad)",          { XX } },
7600     { "(bad)",          { XX } },
7601     { "(bad)",          { XX } },
7602     { "(bad)",          { XX } },
7603   },
7604   /* VEX_0F3A */
7605   {
7606     /* 00 */
7607     { "(bad)",          { XX } },
7608     { "(bad)",          { XX } },
7609     { "(bad)",          { XX } },
7610     { "(bad)",          { XX } },
7611     { PREFIX_TABLE (PREFIX_VEX_3A04) },
7612     { PREFIX_TABLE (PREFIX_VEX_3A05) },
7613     { PREFIX_TABLE (PREFIX_VEX_3A06) },
7614     { "(bad)",          { XX } },
7615     /* 08 */
7616     { PREFIX_TABLE (PREFIX_VEX_3A08) },
7617     { PREFIX_TABLE (PREFIX_VEX_3A09) },
7618     { PREFIX_TABLE (PREFIX_VEX_3A0A) },
7619     { PREFIX_TABLE (PREFIX_VEX_3A0B) },
7620     { PREFIX_TABLE (PREFIX_VEX_3A0C) },
7621     { PREFIX_TABLE (PREFIX_VEX_3A0D) },
7622     { PREFIX_TABLE (PREFIX_VEX_3A0E) },
7623     { PREFIX_TABLE (PREFIX_VEX_3A0F) },
7624     /* 10 */
7625     { "(bad)",          { XX } },
7626     { "(bad)",          { XX } },
7627     { "(bad)",          { XX } },
7628     { "(bad)",          { XX } },
7629     { PREFIX_TABLE (PREFIX_VEX_3A14) },
7630     { PREFIX_TABLE (PREFIX_VEX_3A15) },
7631     { PREFIX_TABLE (PREFIX_VEX_3A16) },
7632     { PREFIX_TABLE (PREFIX_VEX_3A17) },
7633     /* 18 */
7634     { PREFIX_TABLE (PREFIX_VEX_3A18) },
7635     { PREFIX_TABLE (PREFIX_VEX_3A19) },
7636     { "(bad)",          { XX } },
7637     { "(bad)",          { XX } },
7638     { "(bad)",          { XX } },
7639     { "(bad)",          { XX } },
7640     { "(bad)",          { XX } },
7641     { "(bad)",          { XX } },
7642     /* 20 */
7643     { PREFIX_TABLE (PREFIX_VEX_3A20) },
7644     { PREFIX_TABLE (PREFIX_VEX_3A21) },
7645     { PREFIX_TABLE (PREFIX_VEX_3A22) },
7646     { "(bad)",          { XX } },
7647     { "(bad)",          { XX } },
7648     { "(bad)",          { XX } },
7649     { "(bad)",          { XX } },
7650     { "(bad)",          { XX } },
7651     /* 28 */
7652     { "(bad)",          { XX } },
7653     { "(bad)",          { XX } },
7654     { "(bad)",          { XX } },
7655     { "(bad)",          { XX } },
7656     { "(bad)",          { XX } },
7657     { "(bad)",          { XX } },
7658     { "(bad)",          { XX } },
7659     { "(bad)",          { XX } },
7660     /* 30 */
7661     { "(bad)",          { XX } },
7662     { "(bad)",          { XX } },
7663     { "(bad)",          { XX } },
7664     { "(bad)",          { XX } },
7665     { "(bad)",          { XX } },
7666     { "(bad)",          { XX } },
7667     { "(bad)",          { XX } },
7668     { "(bad)",          { XX } },
7669     /* 38 */
7670     { "(bad)",          { XX } },
7671     { "(bad)",          { XX } },
7672     { "(bad)",          { XX } },
7673     { "(bad)",          { XX } },
7674     { "(bad)",          { XX } },
7675     { "(bad)",          { XX } },
7676     { "(bad)",          { XX } },
7677     { "(bad)",          { XX } },
7678     /* 40 */
7679     { PREFIX_TABLE (PREFIX_VEX_3A40) },
7680     { PREFIX_TABLE (PREFIX_VEX_3A41) },
7681     { PREFIX_TABLE (PREFIX_VEX_3A42) },
7682     { "(bad)",          { XX } },
7683     { PREFIX_TABLE (PREFIX_VEX_3A44) },
7684     { "(bad)",          { XX } },
7685     { "(bad)",          { XX } },
7686     { "(bad)",          { XX } },
7687     /* 48 */
7688     { "(bad)",          { XX } },
7689     { "(bad)",          { XX } },
7690     { PREFIX_TABLE (PREFIX_VEX_3A4A) },
7691     { PREFIX_TABLE (PREFIX_VEX_3A4B) },
7692     { PREFIX_TABLE (PREFIX_VEX_3A4C) },
7693     { "(bad)",          { XX } },
7694     { "(bad)",          { XX } },
7695     { "(bad)",          { XX } },
7696     /* 50 */
7697     { "(bad)",          { XX } },
7698     { "(bad)",          { XX } },
7699     { "(bad)",          { XX } },
7700     { "(bad)",          { XX } },
7701     { "(bad)",          { XX } },
7702     { "(bad)",          { XX } },
7703     { "(bad)",          { XX } },
7704     { "(bad)",          { XX } },
7705     /* 58 */
7706     { "(bad)",          { XX } },
7707     { "(bad)",          { XX } },
7708     { "(bad)",          { XX } },
7709     { "(bad)",          { XX } },
7710     { "(bad)",          { XX } },
7711     { "(bad)",          { XX } },
7712     { "(bad)",          { XX } },
7713     { "(bad)",          { XX } },
7714     /* 60 */
7715     { PREFIX_TABLE (PREFIX_VEX_3A60) },
7716     { PREFIX_TABLE (PREFIX_VEX_3A61) },
7717     { PREFIX_TABLE (PREFIX_VEX_3A62) },
7718     { PREFIX_TABLE (PREFIX_VEX_3A63) },
7719     { "(bad)",          { XX } },
7720     { "(bad)",          { XX } },
7721     { "(bad)",          { XX } },
7722     { "(bad)",          { XX } },
7723     /* 68 */
7724     { "(bad)",          { XX } },
7725     { "(bad)",          { XX } },
7726     { "(bad)",          { XX } },
7727     { "(bad)",          { XX } },
7728     { "(bad)",          { XX } },
7729     { "(bad)",          { XX } },
7730     { "(bad)",          { XX } },
7731     { "(bad)",          { XX } },
7732     /* 70 */
7733     { "(bad)",          { XX } },
7734     { "(bad)",          { XX } },
7735     { "(bad)",          { XX } },
7736     { "(bad)",          { XX } },
7737     { "(bad)",          { XX } },
7738     { "(bad)",          { XX } },
7739     { "(bad)",          { XX } },
7740     { "(bad)",          { XX } },
7741     /* 78 */
7742     { "(bad)",          { XX } },
7743     { "(bad)",          { XX } },
7744     { "(bad)",          { XX } },
7745     { "(bad)",          { XX } },
7746     { "(bad)",          { XX } },
7747     { "(bad)",          { XX } },
7748     { "(bad)",          { XX } },
7749     { "(bad)",          { XX } },
7750     /* 80 */
7751     { "(bad)",          { XX } },
7752     { "(bad)",          { XX } },
7753     { "(bad)",          { XX } },
7754     { "(bad)",          { XX } },
7755     { "(bad)",          { XX } },
7756     { "(bad)",          { XX } },
7757     { "(bad)",          { XX } },
7758     { "(bad)",          { XX } },
7759     /* 88 */
7760     { "(bad)",          { XX } },
7761     { "(bad)",          { XX } },
7762     { "(bad)",          { XX } },
7763     { "(bad)",          { XX } },
7764     { "(bad)",          { XX } },
7765     { "(bad)",          { XX } },
7766     { "(bad)",          { XX } },
7767     { "(bad)",          { XX } },
7768     /* 90 */
7769     { "(bad)",          { XX } },
7770     { "(bad)",          { XX } },
7771     { "(bad)",          { XX } },
7772     { "(bad)",          { XX } },
7773     { "(bad)",          { XX } },
7774     { "(bad)",          { XX } },
7775     { "(bad)",          { XX } },
7776     { "(bad)",          { XX } },
7777     /* 98 */
7778     { "(bad)",          { XX } },
7779     { "(bad)",          { XX } },
7780     { "(bad)",          { XX } },
7781     { "(bad)",          { XX } },
7782     { "(bad)",          { XX } },
7783     { "(bad)",          { XX } },
7784     { "(bad)",          { XX } },
7785     { "(bad)",          { XX } },
7786     /* a0 */
7787     { "(bad)",          { XX } },
7788     { "(bad)",          { XX } },
7789     { "(bad)",          { XX } },
7790     { "(bad)",          { XX } },
7791     { "(bad)",          { XX } },
7792     { "(bad)",          { XX } },
7793     { "(bad)",          { XX } },
7794     { "(bad)",          { XX } },
7795     /* a8 */
7796     { "(bad)",          { XX } },
7797     { "(bad)",          { XX } },
7798     { "(bad)",          { XX } },
7799     { "(bad)",          { XX } },
7800     { "(bad)",          { XX } },
7801     { "(bad)",          { XX } },
7802     { "(bad)",          { XX } },
7803     { "(bad)",          { XX } },
7804     /* b0 */
7805     { "(bad)",          { XX } },
7806     { "(bad)",          { XX } },
7807     { "(bad)",          { XX } },
7808     { "(bad)",          { XX } },
7809     { "(bad)",          { XX } },
7810     { "(bad)",          { XX } },
7811     { "(bad)",          { XX } },
7812     { "(bad)",          { XX } },
7813     /* b8 */
7814     { "(bad)",          { XX } },
7815     { "(bad)",          { XX } },
7816     { "(bad)",          { XX } },
7817     { "(bad)",          { XX } },
7818     { "(bad)",          { XX } },
7819     { "(bad)",          { XX } },
7820     { "(bad)",          { XX } },
7821     { "(bad)",          { XX } },
7822     /* c0 */
7823     { "(bad)",          { XX } },
7824     { "(bad)",          { XX } },
7825     { "(bad)",          { XX } },
7826     { "(bad)",          { XX } },
7827     { "(bad)",          { XX } },
7828     { "(bad)",          { XX } },
7829     { "(bad)",          { XX } },
7830     { "(bad)",          { XX } },
7831     /* c8 */
7832     { "(bad)",          { XX } },
7833     { "(bad)",          { XX } },
7834     { "(bad)",          { XX } },
7835     { "(bad)",          { XX } },
7836     { "(bad)",          { XX } },
7837     { "(bad)",          { XX } },
7838     { "(bad)",          { XX } },
7839     { "(bad)",          { XX } },
7840     /* d0 */
7841     { "(bad)",          { XX } },
7842     { "(bad)",          { XX } },
7843     { "(bad)",          { XX } },
7844     { "(bad)",          { XX } },
7845     { "(bad)",          { XX } },
7846     { "(bad)",          { XX } },
7847     { "(bad)",          { XX } },
7848     { "(bad)",          { XX } },
7849     /* d8 */
7850     { "(bad)",          { XX } },
7851     { "(bad)",          { XX } },
7852     { "(bad)",          { XX } },
7853     { "(bad)",          { XX } },
7854     { "(bad)",          { XX } },
7855     { "(bad)",          { XX } },
7856     { "(bad)",          { XX } },
7857     { PREFIX_TABLE (PREFIX_VEX_3ADF) },
7858     /* e0 */
7859     { "(bad)",          { XX } },
7860     { "(bad)",          { XX } },
7861     { "(bad)",          { XX } },
7862     { "(bad)",          { XX } },
7863     { "(bad)",          { XX } },
7864     { "(bad)",          { XX } },
7865     { "(bad)",          { XX } },
7866     { "(bad)",          { XX } },
7867     /* e8 */
7868     { "(bad)",          { XX } },
7869     { "(bad)",          { XX } },
7870     { "(bad)",          { XX } },
7871     { "(bad)",          { XX } },
7872     { "(bad)",          { XX } },
7873     { "(bad)",          { XX } },
7874     { "(bad)",          { XX } },
7875     { "(bad)",          { XX } },
7876     /* f0 */
7877     { "(bad)",          { XX } },
7878     { "(bad)",          { XX } },
7879     { "(bad)",          { XX } },
7880     { "(bad)",          { XX } },
7881     { "(bad)",          { XX } },
7882     { "(bad)",          { XX } },
7883     { "(bad)",          { XX } },
7884     { "(bad)",          { XX } },
7885     /* f8 */
7886     { "(bad)",          { XX } },
7887     { "(bad)",          { XX } },
7888     { "(bad)",          { XX } },
7889     { "(bad)",          { XX } },
7890     { "(bad)",          { XX } },
7891     { "(bad)",          { XX } },
7892     { "(bad)",          { XX } },
7893     { "(bad)",          { XX } },
7894   },
7895 };
7896
7897 static const struct dis386 vex_len_table[][2] = {
7898   /* VEX_LEN_10_P_1 */
7899   {
7900     { "vmovss",         { XMVex, Vex128, EXd } },
7901     { "(bad)",          { XX } },
7902   },
7903
7904   /* VEX_LEN_10_P_3 */
7905   {
7906     { "vmovsd",         { XMVex, Vex128, EXq } },
7907     { "(bad)",          { XX } },
7908   },
7909
7910   /* VEX_LEN_11_P_1 */
7911   {
7912     { "vmovss",         { EXdVexS, Vex128, XM } },
7913     { "(bad)",          { XX } },
7914   },
7915
7916   /* VEX_LEN_11_P_3 */
7917   {
7918     { "vmovsd",         { EXqVexS, Vex128, XM } },
7919     { "(bad)",          { XX } },
7920   },
7921
7922   /* VEX_LEN_12_P_0_M_0 */
7923   {
7924     { "vmovlps",        { XM, Vex128, EXq } },
7925     { "(bad)",          { XX } },
7926   },
7927
7928   /* VEX_LEN_12_P_0_M_1 */
7929   {
7930     { "vmovhlps",       { XM, Vex128, EXq } },
7931     { "(bad)",          { XX } },
7932   },
7933
7934   /* VEX_LEN_12_P_2 */
7935   {
7936     { "vmovlpd",        { XM, Vex128, EXq } },
7937     { "(bad)",          { XX } },
7938   },
7939
7940   /* VEX_LEN_13_M_0 */
7941   {
7942     { "vmovlpX",        { EXq, XM } },
7943     { "(bad)",          { XX } },
7944   },
7945
7946   /* VEX_LEN_16_P_0_M_0 */
7947   {
7948     { "vmovhps",        { XM, Vex128, EXq } },
7949     { "(bad)",          { XX } },
7950   },
7951
7952   /* VEX_LEN_16_P_0_M_1 */
7953   {
7954     { "vmovlhps",       { XM, Vex128, EXq } },
7955     { "(bad)",          { XX } },
7956   },
7957
7958   /* VEX_LEN_16_P_2 */
7959   {
7960     { "vmovhpd",        { XM, Vex128, EXq } },
7961     { "(bad)",          { XX } },
7962   },
7963
7964   /* VEX_LEN_17_M_0 */
7965   {
7966     { "vmovhpX",        { EXq, XM } },
7967     { "(bad)",          { XX } },
7968   },
7969
7970   /* VEX_LEN_2A_P_1 */
7971   {
7972     { "vcvtsi2ss%LQ",   { XM, Vex128, Ev } },
7973     { "(bad)",          { XX } },
7974   },
7975
7976   /* VEX_LEN_2A_P_3 */
7977   {
7978     { "vcvtsi2sd%LQ",   { XM, Vex128, Ev } },
7979     { "(bad)",          { XX } },
7980   },
7981
7982   /* VEX_LEN_2C_P_1 */
7983   {
7984     { "vcvttss2siY",    { Gv, EXd } },
7985     { "(bad)",          { XX } },
7986   },
7987
7988   /* VEX_LEN_2C_P_3 */
7989   {
7990     { "vcvttsd2siY",    { Gv, EXq } },
7991     { "(bad)",          { XX } },
7992   },
7993
7994   /* VEX_LEN_2D_P_1 */
7995   {
7996     { "vcvtss2siY",     { Gv, EXd } },
7997     { "(bad)",          { XX } },
7998   },
7999
8000   /* VEX_LEN_2D_P_3 */
8001   {
8002     { "vcvtsd2siY",     { Gv, EXq } },
8003     { "(bad)",          { XX } },
8004   },
8005
8006   /* VEX_LEN_2E_P_0 */
8007   {
8008     { "vucomiss",       { XM, EXd } },
8009     { "(bad)",          { XX } },
8010   },
8011
8012   /* VEX_LEN_2E_P_2 */
8013   {
8014     { "vucomisd",       { XM, EXq } },
8015     { "(bad)",          { XX } },
8016   },
8017
8018   /* VEX_LEN_2F_P_0 */
8019   {
8020     { "vcomiss",        { XM, EXd } },
8021     { "(bad)",          { XX } },
8022   },
8023
8024   /* VEX_LEN_2F_P_2 */
8025   {
8026     { "vcomisd",        { XM, EXq } },
8027     { "(bad)",          { XX } },
8028   },
8029
8030   /* VEX_LEN_51_P_1 */
8031   {
8032     { "vsqrtss",        { XM, Vex128, EXd } },
8033     { "(bad)",          { XX } },
8034   },
8035
8036   /* VEX_LEN_51_P_3 */
8037   {
8038     { "vsqrtsd",        { XM, Vex128, EXq } },
8039     { "(bad)",          { XX } },
8040   },
8041
8042   /* VEX_LEN_52_P_1 */
8043   {
8044     { "vrsqrtss",       { XM, Vex128, EXd } },
8045     { "(bad)",          { XX } },
8046   },
8047
8048   /* VEX_LEN_53_P_1 */
8049   {
8050     { "vrcpss",         { XM, Vex128, EXd } },
8051     { "(bad)",          { XX } },
8052   },
8053
8054   /* VEX_LEN_58_P_1 */
8055   {
8056     { "vaddss",         { XM, Vex128, EXd } },
8057     { "(bad)",          { XX } },
8058   },
8059
8060   /* VEX_LEN_58_P_3 */
8061   {
8062     { "vaddsd",         { XM, Vex128, EXq } },
8063     { "(bad)",          { XX } },
8064   },
8065
8066   /* VEX_LEN_59_P_1 */
8067   {
8068     { "vmulss",         { XM, Vex128, EXd } },
8069     { "(bad)",          { XX } },
8070   },
8071
8072   /* VEX_LEN_59_P_3 */
8073   {
8074     { "vmulsd",         { XM, Vex128, EXq } },
8075     { "(bad)",          { XX } },
8076   },
8077
8078   /* VEX_LEN_5A_P_1 */
8079   {
8080     { "vcvtss2sd",      { XM, Vex128, EXd } },
8081     { "(bad)",          { XX } },
8082   },
8083
8084   /* VEX_LEN_5A_P_3 */
8085   {
8086     { "vcvtsd2ss",      { XM, Vex128, EXq } },
8087     { "(bad)",          { XX } },
8088   },
8089
8090   /* VEX_LEN_5C_P_1 */
8091   {
8092     { "vsubss",         { XM, Vex128, EXd } },
8093     { "(bad)",          { XX } },
8094   },
8095
8096   /* VEX_LEN_5C_P_3 */
8097   {
8098     { "vsubsd",         { XM, Vex128, EXq } },
8099     { "(bad)",          { XX } },
8100   },
8101
8102   /* VEX_LEN_5D_P_1 */
8103   {
8104     { "vminss",         { XM, Vex128, EXd } },
8105     { "(bad)",          { XX } },
8106   },
8107
8108   /* VEX_LEN_5D_P_3 */
8109   {
8110     { "vminsd",         { XM, Vex128, EXq } },
8111     { "(bad)",          { XX } },
8112   },
8113
8114   /* VEX_LEN_5E_P_1 */
8115   {
8116     { "vdivss",         { XM, Vex128, EXd } },
8117     { "(bad)",          { XX } },
8118   },
8119
8120   /* VEX_LEN_5E_P_3 */
8121   {
8122     { "vdivsd",         { XM, Vex128, EXq } },
8123     { "(bad)",          { XX } },
8124   },
8125
8126   /* VEX_LEN_5F_P_1 */
8127   {
8128     { "vmaxss",         { XM, Vex128, EXd } },
8129     { "(bad)",          { XX } },
8130   },
8131
8132   /* VEX_LEN_5F_P_3 */
8133   {
8134     { "vmaxsd",         { XM, Vex128, EXq } },
8135     { "(bad)",          { XX } },
8136   },
8137
8138   /* VEX_LEN_60_P_2 */
8139   {
8140     { "vpunpcklbw",     { XM, Vex128, EXx } },
8141     { "(bad)",          { XX } },
8142   },
8143
8144   /* VEX_LEN_61_P_2 */
8145   {
8146     { "vpunpcklwd",     { XM, Vex128, EXx } },
8147     { "(bad)",          { XX } },
8148   },
8149
8150   /* VEX_LEN_62_P_2 */
8151   {
8152     { "vpunpckldq",     { XM, Vex128, EXx } },
8153     { "(bad)",          { XX } },
8154   },
8155
8156   /* VEX_LEN_63_P_2 */
8157   {
8158     { "vpacksswb",      { XM, Vex128, EXx } },
8159     { "(bad)",          { XX } },
8160   },
8161
8162   /* VEX_LEN_64_P_2 */
8163   {
8164     { "vpcmpgtb",       { XM, Vex128, EXx } },
8165     { "(bad)",          { XX } },
8166   },
8167
8168   /* VEX_LEN_65_P_2 */
8169   {
8170     { "vpcmpgtw",       { XM, Vex128, EXx } },
8171     { "(bad)",          { XX } },
8172   },
8173
8174   /* VEX_LEN_66_P_2 */
8175   {
8176     { "vpcmpgtd",       { XM, Vex128, EXx } },
8177     { "(bad)",          { XX } },
8178   },
8179
8180   /* VEX_LEN_67_P_2 */
8181   {
8182     { "vpackuswb",      { XM, Vex128, EXx } },
8183     { "(bad)",          { XX } },
8184   },
8185
8186   /* VEX_LEN_68_P_2 */
8187   {
8188     { "vpunpckhbw",     { XM, Vex128, EXx } },
8189     { "(bad)",          { XX } },
8190   },
8191
8192   /* VEX_LEN_69_P_2 */
8193   {
8194     { "vpunpckhwd",     { XM, Vex128, EXx } },
8195     { "(bad)",          { XX } },
8196   },
8197
8198   /* VEX_LEN_6A_P_2 */
8199   {
8200     { "vpunpckhdq",     { XM, Vex128, EXx } },
8201     { "(bad)",          { XX } },
8202   },
8203
8204   /* VEX_LEN_6B_P_2 */
8205   {
8206     { "vpackssdw",      { XM, Vex128, EXx } },
8207     { "(bad)",          { XX } },
8208   },
8209
8210   /* VEX_LEN_6C_P_2 */
8211   {
8212     { "vpunpcklqdq",    { XM, Vex128, EXx } },
8213     { "(bad)",          { XX } },
8214   },
8215
8216   /* VEX_LEN_6D_P_2 */
8217   {
8218     { "vpunpckhqdq",    { XM, Vex128, EXx } },
8219     { "(bad)",          { XX } },
8220   },
8221
8222   /* VEX_LEN_6E_P_2 */
8223   {
8224     { "vmovK",          { XM, Edq } },
8225     { "(bad)",          { XX } },
8226   },
8227
8228   /* VEX_LEN_70_P_1 */
8229   {
8230     { "vpshufhw",       { XM, EXx, Ib } },
8231     { "(bad)",          { XX } },
8232   },
8233
8234   /* VEX_LEN_70_P_2 */
8235   {
8236     { "vpshufd",        { XM, EXx, Ib } },
8237     { "(bad)",          { XX } },
8238   },
8239
8240   /* VEX_LEN_70_P_3 */
8241   {
8242     { "vpshuflw",       { XM, EXx, Ib } },
8243     { "(bad)",          { XX } },
8244   },
8245
8246   /* VEX_LEN_71_R_2_P_2 */
8247   {
8248     { "vpsrlw",         { Vex128, XS, Ib } },
8249     { "(bad)",          { XX } },
8250   },
8251
8252   /* VEX_LEN_71_R_4_P_2 */
8253   {
8254     { "vpsraw",         { Vex128, XS, Ib } },
8255     { "(bad)",          { XX } },
8256   },
8257
8258   /* VEX_LEN_71_R_6_P_2 */
8259   {
8260     { "vpsllw",         { Vex128, XS, Ib } },
8261     { "(bad)",          { XX } },
8262   },
8263
8264   /* VEX_LEN_72_R_2_P_2 */
8265   {
8266     { "vpsrld",         { Vex128, XS, Ib } },
8267     { "(bad)",          { XX } },
8268   },
8269
8270   /* VEX_LEN_72_R_4_P_2 */
8271   {
8272     { "vpsrad",         { Vex128, XS, Ib } },
8273     { "(bad)",          { XX } },
8274   },
8275
8276   /* VEX_LEN_72_R_6_P_2 */
8277   {
8278     { "vpslld",         { Vex128, XS, Ib } },
8279     { "(bad)",          { XX } },
8280   },
8281
8282   /* VEX_LEN_73_R_2_P_2 */
8283   {
8284     { "vpsrlq",         { Vex128, XS, Ib } },
8285     { "(bad)",          { XX } },
8286   },
8287
8288   /* VEX_LEN_73_R_3_P_2 */
8289   {
8290     { "vpsrldq",        { Vex128, XS, Ib } },
8291     { "(bad)",          { XX } },
8292   },
8293
8294   /* VEX_LEN_73_R_6_P_2 */
8295   {
8296     { "vpsllq",         { Vex128, XS, Ib } },
8297     { "(bad)",          { XX } },
8298   },
8299
8300   /* VEX_LEN_73_R_7_P_2 */
8301   {
8302     { "vpslldq",        { Vex128, XS, Ib } },
8303     { "(bad)",          { XX } },
8304   },
8305
8306   /* VEX_LEN_74_P_2 */
8307   {
8308     { "vpcmpeqb",       { XM, Vex128, EXx } },
8309     { "(bad)",          { XX } },
8310   },
8311
8312   /* VEX_LEN_75_P_2 */
8313   {
8314     { "vpcmpeqw",       { XM, Vex128, EXx } },
8315     { "(bad)",          { XX } },
8316   },
8317
8318   /* VEX_LEN_76_P_2 */
8319   {
8320     { "vpcmpeqd",       { XM, Vex128, EXx } },
8321     { "(bad)",          { XX } },
8322   },
8323
8324   /* VEX_LEN_7E_P_1 */
8325   {
8326     { "vmovq",          { XM, EXq } },
8327     { "(bad)",          { XX } },
8328   },
8329
8330   /* VEX_LEN_7E_P_2 */
8331   {
8332     { "vmovK",          { Edq, XM } },
8333     { "(bad)",          { XX } },
8334   },
8335
8336   /* VEX_LEN_AE_R_2_M0 */
8337   {
8338     { "vldmxcsr",       { Md } },
8339     { "(bad)",          { XX } },
8340   },
8341
8342   /* VEX_LEN_AE_R_3_M0 */
8343   {
8344     { "vstmxcsr",       { Md } },
8345     { "(bad)",          { XX } },
8346   },
8347
8348   /* VEX_LEN_C2_P_1 */
8349   {
8350     { "vcmpss",         { XM, Vex128, EXd, VCMP } },
8351     { "(bad)",          { XX } },
8352   },
8353
8354   /* VEX_LEN_C2_P_3 */
8355   {
8356     { "vcmpsd",         { XM, Vex128, EXq, VCMP } },
8357     { "(bad)",          { XX } },
8358   },
8359
8360   /* VEX_LEN_C4_P_2 */
8361   {
8362     { "vpinsrw",        { XM, Vex128, Edqw, Ib } },
8363     { "(bad)",          { XX } },
8364   },
8365
8366   /* VEX_LEN_C5_P_2 */
8367   {
8368     { "vpextrw",        { Gdq, XS, Ib } },
8369     { "(bad)",          { XX } },
8370   },
8371
8372   /* VEX_LEN_D1_P_2 */
8373   {
8374     { "vpsrlw",         { XM, Vex128, EXx } },
8375     { "(bad)",          { XX } },
8376   },
8377
8378   /* VEX_LEN_D2_P_2 */
8379   {
8380     { "vpsrld",         { XM, Vex128, EXx } },
8381     { "(bad)",          { XX } },
8382   },
8383
8384   /* VEX_LEN_D3_P_2 */
8385   {
8386     { "vpsrlq",         { XM, Vex128, EXx } },
8387     { "(bad)",          { XX } },
8388   },
8389
8390   /* VEX_LEN_D4_P_2 */
8391   {
8392     { "vpaddq",         { XM, Vex128, EXx } },
8393     { "(bad)",          { XX } },
8394   },
8395
8396   /* VEX_LEN_D5_P_2 */
8397   {
8398     { "vpmullw",        { XM, Vex128, EXx } },
8399     { "(bad)",          { XX } },
8400   },
8401
8402   /* VEX_LEN_D6_P_2 */
8403   {
8404     { "vmovq",          { EXqS, XM } },
8405     { "(bad)",          { XX } },
8406   },
8407
8408   /* VEX_LEN_D7_P_2_M_1 */
8409   {
8410     { "vpmovmskb",      { Gdq, XS } },
8411     { "(bad)",          { XX } },
8412   },
8413
8414   /* VEX_LEN_D8_P_2 */
8415   {
8416     { "vpsubusb",       { XM, Vex128, EXx } },
8417     { "(bad)",          { XX } },
8418   },
8419
8420   /* VEX_LEN_D9_P_2 */
8421   {
8422     { "vpsubusw",       { XM, Vex128, EXx } },
8423     { "(bad)",          { XX } },
8424   },
8425
8426   /* VEX_LEN_DA_P_2 */
8427   {
8428     { "vpminub",        { XM, Vex128, EXx } },
8429     { "(bad)",          { XX } },
8430   },
8431
8432   /* VEX_LEN_DB_P_2 */
8433   {
8434     { "vpand",          { XM, Vex128, EXx } },
8435     { "(bad)",          { XX } },
8436   },
8437
8438   /* VEX_LEN_DC_P_2 */
8439   {
8440     { "vpaddusb",       { XM, Vex128, EXx } },
8441     { "(bad)",          { XX } },
8442   },
8443
8444   /* VEX_LEN_DD_P_2 */
8445   {
8446     { "vpaddusw",       { XM, Vex128, EXx } },
8447     { "(bad)",          { XX } },
8448   },
8449
8450   /* VEX_LEN_DE_P_2 */
8451   {
8452     { "vpmaxub",        { XM, Vex128, EXx } },
8453     { "(bad)",          { XX } },
8454   },
8455
8456   /* VEX_LEN_DF_P_2 */
8457   {
8458     { "vpandn",         { XM, Vex128, EXx } },
8459     { "(bad)",          { XX } },
8460   },
8461
8462   /* VEX_LEN_E0_P_2 */
8463   {
8464     { "vpavgb",         { XM, Vex128, EXx } },
8465     { "(bad)",          { XX } },
8466   },
8467
8468   /* VEX_LEN_E1_P_2 */
8469   {
8470     { "vpsraw",         { XM, Vex128, EXx } },
8471     { "(bad)",          { XX } },
8472   },
8473
8474   /* VEX_LEN_E2_P_2 */
8475   {
8476     { "vpsrad",         { XM, Vex128, EXx } },
8477     { "(bad)",          { XX } },
8478   },
8479
8480   /* VEX_LEN_E3_P_2 */
8481   {
8482     { "vpavgw",         { XM, Vex128, EXx } },
8483     { "(bad)",          { XX } },
8484   },
8485
8486   /* VEX_LEN_E4_P_2 */
8487   {
8488     { "vpmulhuw",       { XM, Vex128, EXx } },
8489     { "(bad)",          { XX } },
8490   },
8491
8492   /* VEX_LEN_E5_P_2 */
8493   {
8494     { "vpmulhw",        { XM, Vex128, EXx } },
8495     { "(bad)",          { XX } },
8496   },
8497
8498   /* VEX_LEN_E8_P_2 */
8499   {
8500     { "vpsubsb",        { XM, Vex128, EXx } },
8501     { "(bad)",          { XX } },
8502   },
8503
8504   /* VEX_LEN_E9_P_2 */
8505   {
8506     { "vpsubsw",        { XM, Vex128, EXx } },
8507     { "(bad)",          { XX } },
8508   },
8509
8510   /* VEX_LEN_EA_P_2 */
8511   {
8512     { "vpminsw",        { XM, Vex128, EXx } },
8513     { "(bad)",          { XX } },
8514   },
8515
8516   /* VEX_LEN_EB_P_2 */
8517   {
8518     { "vpor",           { XM, Vex128, EXx } },
8519     { "(bad)",          { XX } },
8520   },
8521
8522   /* VEX_LEN_EC_P_2 */
8523   {
8524     { "vpaddsb",        { XM, Vex128, EXx } },
8525     { "(bad)",          { XX } },
8526   },
8527
8528   /* VEX_LEN_ED_P_2 */
8529   {
8530     { "vpaddsw",        { XM, Vex128, EXx } },
8531     { "(bad)",          { XX } },
8532   },
8533
8534   /* VEX_LEN_EE_P_2 */
8535   {
8536     { "vpmaxsw",        { XM, Vex128, EXx } },
8537     { "(bad)",          { XX } },
8538   },
8539
8540   /* VEX_LEN_EF_P_2 */
8541   {
8542     { "vpxor",          { XM, Vex128, EXx } },
8543     { "(bad)",          { XX } },
8544   },
8545
8546   /* VEX_LEN_F1_P_2 */
8547   {
8548     { "vpsllw",         { XM, Vex128, EXx } },
8549     { "(bad)",          { XX } },
8550   },
8551
8552   /* VEX_LEN_F2_P_2 */
8553   {
8554     { "vpslld",         { XM, Vex128, EXx } },
8555     { "(bad)",          { XX } },
8556   },
8557
8558   /* VEX_LEN_F3_P_2 */
8559   {
8560     { "vpsllq",         { XM, Vex128, EXx } },
8561     { "(bad)",          { XX } },
8562   },
8563
8564   /* VEX_LEN_F4_P_2 */
8565   {
8566     { "vpmuludq",       { XM, Vex128, EXx } },
8567     { "(bad)",          { XX } },
8568   },
8569
8570   /* VEX_LEN_F5_P_2 */
8571   {
8572     { "vpmaddwd",       { XM, Vex128, EXx } },
8573     { "(bad)",          { XX } },
8574   },
8575
8576   /* VEX_LEN_F6_P_2 */
8577   {
8578     { "vpsadbw",        { XM, Vex128, EXx } },
8579     { "(bad)",          { XX } },
8580   },
8581
8582   /* VEX_LEN_F7_P_2 */
8583   {
8584     { "vmaskmovdqu",    { XM, XS } },
8585     { "(bad)",          { XX } },
8586   },
8587
8588   /* VEX_LEN_F8_P_2 */
8589   {
8590     { "vpsubb",         { XM, Vex128, EXx } },
8591     { "(bad)",          { XX } },
8592   },
8593
8594   /* VEX_LEN_F9_P_2 */
8595   {
8596     { "vpsubw",         { XM, Vex128, EXx } },
8597     { "(bad)",          { XX } },
8598   },
8599
8600   /* VEX_LEN_FA_P_2 */
8601   {
8602     { "vpsubd",         { XM, Vex128, EXx } },
8603     { "(bad)",          { XX } },
8604   },
8605
8606   /* VEX_LEN_FB_P_2 */
8607   {
8608     { "vpsubq",         { XM, Vex128, EXx } },
8609     { "(bad)",          { XX } },
8610   },
8611
8612   /* VEX_LEN_FC_P_2 */
8613   {
8614     { "vpaddb",         { XM, Vex128, EXx } },
8615     { "(bad)",          { XX } },
8616   },
8617
8618   /* VEX_LEN_FD_P_2 */
8619   {
8620     { "vpaddw",         { XM, Vex128, EXx } },
8621     { "(bad)",          { XX } },
8622   },
8623
8624   /* VEX_LEN_FE_P_2 */
8625   {
8626     { "vpaddd",         { XM, Vex128, EXx } },
8627     { "(bad)",          { XX } },
8628   },
8629
8630   /* VEX_LEN_3800_P_2 */
8631   {
8632     { "vpshufb",        { XM, Vex128, EXx } },
8633     { "(bad)",          { XX } },
8634   },
8635
8636   /* VEX_LEN_3801_P_2 */
8637   {
8638     { "vphaddw",        { XM, Vex128, EXx } },
8639     { "(bad)",          { XX } },
8640   },
8641
8642   /* VEX_LEN_3802_P_2 */
8643   {
8644     { "vphaddd",        { XM, Vex128, EXx } },
8645     { "(bad)",          { XX } },
8646   },
8647
8648   /* VEX_LEN_3803_P_2 */
8649   {
8650     { "vphaddsw",       { XM, Vex128, EXx } },
8651     { "(bad)",          { XX } },
8652   },
8653
8654   /* VEX_LEN_3804_P_2 */
8655   {
8656     { "vpmaddubsw",     { XM, Vex128, EXx } },
8657     { "(bad)",          { XX } },
8658   },
8659
8660   /* VEX_LEN_3805_P_2 */
8661   {
8662     { "vphsubw",        { XM, Vex128, EXx } },
8663     { "(bad)",          { XX } },
8664   },
8665
8666   /* VEX_LEN_3806_P_2 */
8667   {
8668     { "vphsubd",        { XM, Vex128, EXx } },
8669     { "(bad)",          { XX } },
8670   },
8671
8672   /* VEX_LEN_3807_P_2 */
8673   {
8674     { "vphsubsw",       { XM, Vex128, EXx } },
8675     { "(bad)",          { XX } },
8676   },
8677
8678   /* VEX_LEN_3808_P_2 */
8679   {
8680     { "vpsignb",        { XM, Vex128, EXx } },
8681     { "(bad)",          { XX } },
8682   },
8683
8684   /* VEX_LEN_3809_P_2 */
8685   {
8686     { "vpsignw",        { XM, Vex128, EXx } },
8687     { "(bad)",          { XX } },
8688   },
8689
8690   /* VEX_LEN_380A_P_2 */
8691   {
8692     { "vpsignd",        { XM, Vex128, EXx } },
8693     { "(bad)",          { XX } },
8694   },
8695
8696   /* VEX_LEN_380B_P_2 */
8697   {
8698     { "vpmulhrsw",      { XM, Vex128, EXx } },
8699     { "(bad)",          { XX } },
8700   },
8701
8702   /* VEX_LEN_3819_P_2_M_0 */
8703   {
8704     { "(bad)",          { XX } },
8705     { "vbroadcastsd",   { XM, Mq } },
8706   },
8707
8708   /* VEX_LEN_381A_P_2_M_0 */
8709   {
8710     { "(bad)",          { XX } },
8711     { "vbroadcastf128", { XM, Mxmm } },
8712   },
8713
8714   /* VEX_LEN_381C_P_2 */
8715   {
8716     { "vpabsb",         { XM, EXx } },
8717     { "(bad)",          { XX } },
8718   },
8719
8720   /* VEX_LEN_381D_P_2 */
8721   {
8722     { "vpabsw",         { XM, EXx } },
8723     { "(bad)",          { XX } },
8724   },
8725
8726   /* VEX_LEN_381E_P_2 */
8727   {
8728     { "vpabsd",         { XM, EXx } },
8729     { "(bad)",          { XX } },
8730   },
8731
8732   /* VEX_LEN_3820_P_2 */
8733   {
8734     { "vpmovsxbw",      { XM, EXq } },
8735     { "(bad)",          { XX } },
8736   },
8737
8738   /* VEX_LEN_3821_P_2 */
8739   {
8740     { "vpmovsxbd",      { XM, EXd } },
8741     { "(bad)",          { XX } },
8742   },
8743
8744   /* VEX_LEN_3822_P_2 */
8745   {
8746     { "vpmovsxbq",      { XM, EXw } },
8747     { "(bad)",          { XX } },
8748   },
8749
8750   /* VEX_LEN_3823_P_2 */
8751   {
8752     { "vpmovsxwd",      { XM, EXq } },
8753     { "(bad)",          { XX } },
8754   },
8755
8756   /* VEX_LEN_3824_P_2 */
8757   {
8758     { "vpmovsxwq",      { XM, EXd } },
8759     { "(bad)",          { XX } },
8760   },
8761
8762   /* VEX_LEN_3825_P_2 */
8763   {
8764     { "vpmovsxdq",      { XM, EXq } },
8765     { "(bad)",          { XX } },
8766   },
8767
8768   /* VEX_LEN_3828_P_2 */
8769   {
8770     { "vpmuldq",        { XM, Vex128, EXx } },
8771     { "(bad)",          { XX } },
8772   },
8773
8774   /* VEX_LEN_3829_P_2 */
8775   {
8776     { "vpcmpeqq",       { XM, Vex128, EXx } },
8777     { "(bad)",          { XX } },
8778   },
8779
8780   /* VEX_LEN_382A_P_2_M_0 */
8781   {
8782     { "vmovntdqa",      { XM, Mx } },
8783     { "(bad)",          { XX } },
8784   },
8785
8786   /* VEX_LEN_382B_P_2 */
8787   {
8788     { "vpackusdw",      { XM, Vex128, EXx } },
8789     { "(bad)",          { XX } },
8790   },
8791
8792   /* VEX_LEN_3830_P_2 */
8793   {
8794     { "vpmovzxbw",      { XM, EXq } },
8795     { "(bad)",          { XX } },
8796   },
8797
8798   /* VEX_LEN_3831_P_2 */
8799   {
8800     { "vpmovzxbd",      { XM, EXd } },
8801     { "(bad)",          { XX } },
8802   },
8803
8804   /* VEX_LEN_3832_P_2 */
8805   {
8806     { "vpmovzxbq",      { XM, EXw } },
8807     { "(bad)",          { XX } },
8808   },
8809
8810   /* VEX_LEN_3833_P_2 */
8811   {
8812     { "vpmovzxwd",      { XM, EXq } },
8813     { "(bad)",          { XX } },
8814   },
8815
8816   /* VEX_LEN_3834_P_2 */
8817   {
8818     { "vpmovzxwq",      { XM, EXd } },
8819     { "(bad)",          { XX } },
8820   },
8821
8822   /* VEX_LEN_3835_P_2 */
8823   {
8824     { "vpmovzxdq",      { XM, EXq } },
8825     { "(bad)",          { XX } },
8826   },
8827
8828   /* VEX_LEN_3837_P_2 */
8829   {
8830     { "vpcmpgtq",       { XM, Vex128, EXx } },
8831     { "(bad)",          { XX } },
8832   },
8833
8834   /* VEX_LEN_3838_P_2 */
8835   {
8836     { "vpminsb",        { XM, Vex128, EXx } },
8837     { "(bad)",          { XX } },
8838   },
8839
8840   /* VEX_LEN_3839_P_2 */
8841   {
8842     { "vpminsd",        { XM, Vex128, EXx } },
8843     { "(bad)",          { XX } },
8844   },
8845
8846   /* VEX_LEN_383A_P_2 */
8847   {
8848     { "vpminuw",        { XM, Vex128, EXx } },
8849     { "(bad)",          { XX } },
8850   },
8851
8852   /* VEX_LEN_383B_P_2 */
8853   {
8854     { "vpminud",        { XM, Vex128, EXx } },
8855     { "(bad)",          { XX } },
8856   },
8857
8858   /* VEX_LEN_383C_P_2 */
8859   {
8860     { "vpmaxsb",        { XM, Vex128, EXx } },
8861     { "(bad)",          { XX } },
8862   },
8863
8864   /* VEX_LEN_383D_P_2 */
8865   {
8866     { "vpmaxsd",        { XM, Vex128, EXx } },
8867     { "(bad)",          { XX } },
8868   },
8869
8870   /* VEX_LEN_383E_P_2 */
8871   {
8872     { "vpmaxuw",        { XM, Vex128, EXx } },
8873     { "(bad)",          { XX } },
8874   },
8875
8876   /* VEX_LEN_383F_P_2 */
8877   {
8878     { "vpmaxud",        { XM, Vex128, EXx } },
8879     { "(bad)",          { XX } },
8880   },
8881
8882   /* VEX_LEN_3840_P_2 */
8883   {
8884     { "vpmulld",        { XM, Vex128, EXx } },
8885     { "(bad)",          { XX } },
8886   },
8887
8888   /* VEX_LEN_3841_P_2 */
8889   {
8890     { "vphminposuw",    { XM, EXx } },
8891     { "(bad)",          { XX } },
8892   },
8893
8894   /* VEX_LEN_38DB_P_2 */
8895   {
8896     { "vaesimc",        { XM, EXx } },
8897     { "(bad)",          { XX } },
8898   },
8899
8900   /* VEX_LEN_38DC_P_2 */
8901   {
8902     { "vaesenc",        { XM, Vex128, EXx } },
8903     { "(bad)",          { XX } },
8904   },
8905
8906   /* VEX_LEN_38DD_P_2 */
8907   {
8908     { "vaesenclast",    { XM, Vex128, EXx } },
8909     { "(bad)",          { XX } },
8910   },
8911
8912   /* VEX_LEN_38DE_P_2 */
8913   {
8914     { "vaesdec",        { XM, Vex128, EXx } },
8915     { "(bad)",          { XX } },
8916   },
8917
8918   /* VEX_LEN_38DF_P_2 */
8919   {
8920     { "vaesdeclast",    { XM, Vex128, EXx } },
8921     { "(bad)",          { XX } },
8922   },
8923
8924   /* VEX_LEN_3A06_P_2 */
8925   {
8926     { "(bad)",          { XX } },
8927     { "vperm2f128",     { XM, Vex256, EXx, Ib } },
8928   },
8929
8930   /* VEX_LEN_3A0A_P_2 */
8931   {
8932     { "vroundss",       { XM, Vex128, EXd, Ib } },
8933     { "(bad)",          { XX } },
8934   },
8935
8936   /* VEX_LEN_3A0B_P_2 */
8937   {
8938     { "vroundsd",       { XM, Vex128, EXq, Ib } },
8939     { "(bad)",          { XX } },
8940   },
8941
8942   /* VEX_LEN_3A0E_P_2 */
8943   {
8944     { "vpblendw",       { XM, Vex128, EXx, Ib } },
8945     { "(bad)",          { XX } },
8946   },
8947
8948   /* VEX_LEN_3A0F_P_2 */
8949   {
8950     { "vpalignr",       { XM, Vex128, EXx, Ib } },
8951     { "(bad)",          { XX } },
8952   },
8953
8954   /* VEX_LEN_3A14_P_2 */
8955   {
8956     { "vpextrb",        { Edqb, XM, Ib } },
8957     { "(bad)",          { XX } },
8958   },
8959
8960   /* VEX_LEN_3A15_P_2 */
8961   {
8962     { "vpextrw",        { Edqw, XM, Ib } },
8963     { "(bad)",          { XX } },
8964   },
8965
8966   /* VEX_LEN_3A16_P_2  */
8967   {
8968     { "vpextrK",        { Edq, XM, Ib } },
8969     { "(bad)",          { XX } },
8970   },
8971
8972   /* VEX_LEN_3A17_P_2 */
8973   {
8974     { "vextractps",     { Edqd, XM, Ib } },
8975     { "(bad)",          { XX } },
8976   },
8977
8978   /* VEX_LEN_3A18_P_2 */
8979   {
8980     { "(bad)",          { XX } },
8981     { "vinsertf128",    { XM, Vex256, EXxmm, Ib } },
8982   },
8983
8984   /* VEX_LEN_3A19_P_2 */
8985   {
8986     { "(bad)",          { XX } },
8987     { "vextractf128",   { EXxmm, XM, Ib } },
8988   },
8989
8990   /* VEX_LEN_3A20_P_2 */
8991   {
8992     { "vpinsrb",        { XM, Vex128, Edqb, Ib } },
8993     { "(bad)",          { XX } },
8994   },
8995
8996   /* VEX_LEN_3A21_P_2 */
8997   {
8998     { "vinsertps",      { XM, Vex128, EXd, Ib } },
8999     { "(bad)",          { XX } },
9000   },
9001
9002   /* VEX_LEN_3A22_P_2 */
9003   {
9004     { "vpinsrK",        { XM, Vex128, Edq, Ib } },
9005     { "(bad)",          { XX } },
9006   },
9007
9008   /* VEX_LEN_3A41_P_2 */
9009   {
9010     { "vdppd",          { XM, Vex128, EXx, Ib } },
9011     { "(bad)",          { XX } },
9012   },
9013
9014   /* VEX_LEN_3A42_P_2 */
9015   {
9016     { "vmpsadbw",       { XM, Vex128, EXx, Ib } },
9017     { "(bad)",          { XX } },
9018   },
9019
9020   /* VEX_LEN_3A44_P_2 */
9021   {
9022     { "vpclmulqdq",     { XM, Vex128, EXx, PCLMUL } },
9023     { "(bad)",          { XX } },
9024   },
9025
9026   /* VEX_LEN_3A4C_P_2 */
9027   {
9028     { "vpblendvb",      { XM, Vex128, EXx, XMVexI4 } },
9029     { "(bad)",          { XX } },
9030   },
9031
9032   /* VEX_LEN_3A60_P_2 */
9033   {
9034     { "vpcmpestrm",     { XM, EXx, Ib } },
9035     { "(bad)",          { XX } },
9036   },
9037
9038   /* VEX_LEN_3A61_P_2 */
9039   {
9040     { "vpcmpestri",     { XM, EXx, Ib } },
9041     { "(bad)",          { XX } },
9042   },
9043
9044   /* VEX_LEN_3A62_P_2 */
9045   {
9046     { "vpcmpistrm",     { XM, EXx, Ib } },
9047     { "(bad)",          { XX } },
9048   },
9049
9050   /* VEX_LEN_3A63_P_2 */
9051   {
9052     { "vpcmpistri",     { XM, EXx, Ib } },
9053     { "(bad)",          { XX } },
9054   },
9055
9056   /* VEX_LEN_3ADF_P_2 */
9057   {
9058     { "vaeskeygenassist", { XM, EXx, Ib } },
9059     { "(bad)",          { XX } },
9060   },
9061 };
9062
9063 static const struct dis386 mod_table[][2] = {
9064   {
9065     /* MOD_8D */
9066     { "leaS",           { Gv, M } },
9067     { "(bad)",          { XX } },
9068   },
9069   {
9070     /* MOD_0F01_REG_0 */
9071     { X86_64_TABLE (X86_64_0F01_REG_0) },
9072     { RM_TABLE (RM_0F01_REG_0) },
9073   },
9074   {
9075     /* MOD_0F01_REG_1 */
9076     { X86_64_TABLE (X86_64_0F01_REG_1) },
9077     { RM_TABLE (RM_0F01_REG_1) },
9078   },
9079   {
9080     /* MOD_0F01_REG_2 */
9081     { X86_64_TABLE (X86_64_0F01_REG_2) },
9082     { RM_TABLE (RM_0F01_REG_2) },
9083   },
9084   {
9085     /* MOD_0F01_REG_3 */
9086     { X86_64_TABLE (X86_64_0F01_REG_3) },
9087     { RM_TABLE (RM_0F01_REG_3) },
9088   },
9089   {
9090     /* MOD_0F01_REG_7 */
9091     { "invlpg",         { Mb } },
9092     { RM_TABLE (RM_0F01_REG_7) },
9093   },
9094   {
9095     /* MOD_0F12_PREFIX_0 */
9096     { "movlps",         { XM, EXq } },
9097     { "movhlps",        { XM, EXq } },
9098   },
9099   {
9100     /* MOD_0F13 */
9101     { "movlpX",         { EXq, XM } },
9102     { "(bad)",          { XX } },
9103   },
9104   {
9105     /* MOD_0F16_PREFIX_0 */
9106     { "movhps",         { XM, EXq } },
9107     { "movlhps",        { XM, EXq } },
9108   },
9109   {
9110     /* MOD_0F17 */
9111     { "movhpX",         { EXq, XM } },
9112     { "(bad)",          { XX } },
9113   },
9114   {
9115     /* MOD_0F18_REG_0 */
9116     { "prefetchnta",    { Mb } },
9117     { "(bad)",          { XX } },
9118   },
9119   {
9120     /* MOD_0F18_REG_1 */
9121     { "prefetcht0",     { Mb } },
9122     { "(bad)",          { XX } },
9123   },
9124   {
9125     /* MOD_0F18_REG_2 */
9126     { "prefetcht1",     { Mb } },
9127     { "(bad)",          { XX } },
9128   },
9129   {
9130     /* MOD_0F18_REG_3 */
9131     { "prefetcht2",     { Mb } },
9132     { "(bad)",          { XX } },
9133   },
9134   {
9135     /* MOD_0F20 */
9136     { "(bad)",          { XX } },
9137     { "movZ",           { Rm, Cm } },
9138   },
9139   {
9140     /* MOD_0F21 */
9141     { "(bad)",          { XX } },
9142     { "movZ",           { Rm, Dm } },
9143   },
9144   {
9145     /* MOD_0F22 */
9146     { "(bad)",          { XX } },
9147     { "movZ",           { Cm, Rm } },
9148   },
9149   {
9150     /* MOD_0F23 */
9151     { "(bad)",          { XX } },
9152     { "movZ",           { Dm, Rm } },
9153   },
9154   {
9155     /* MOD_0F24 */
9156     { THREE_BYTE_TABLE (THREE_BYTE_0F24) },
9157     { "movL",           { Rd, Td } },
9158   },
9159   {
9160     /* MOD_0F26 */
9161     { "(bad)",          { XX } },
9162     { "movL",           { Td, Rd } },
9163   },
9164   {
9165     /* MOD_0F2B_PREFIX_0 */
9166     {"movntps",         { Mx, XM } },
9167     { "(bad)",          { XX } },
9168   },
9169   {
9170     /* MOD_0F2B_PREFIX_1 */
9171     {"movntss",         { Md, XM } },
9172     { "(bad)",          { XX } },
9173   },
9174   {
9175     /* MOD_0F2B_PREFIX_2 */
9176     {"movntpd",         { Mx, XM } },
9177     { "(bad)",          { XX } },
9178   },
9179   {
9180     /* MOD_0F2B_PREFIX_3 */
9181     {"movntsd",         { Mq, XM } },
9182     { "(bad)",          { XX } },
9183   },
9184   {
9185     /* MOD_0F51 */
9186     { "(bad)",          { XX } },
9187     { "movmskpX",       { Gdq, XS } },
9188   },
9189   {
9190     /* MOD_0F71_REG_2 */
9191     { "(bad)",          { XX } },
9192     { "psrlw",          { MS, Ib } },
9193   },
9194   {
9195     /* MOD_0F71_REG_4 */
9196     { "(bad)",          { XX } },
9197     { "psraw",          { MS, Ib } },
9198   },
9199   {
9200     /* MOD_0F71_REG_6 */
9201     { "(bad)",          { XX } },
9202     { "psllw",          { MS, Ib } },
9203   },
9204   {
9205     /* MOD_0F72_REG_2 */
9206     { "(bad)",          { XX } },
9207     { "psrld",          { MS, Ib } },
9208   },
9209   {
9210     /* MOD_0F72_REG_4 */
9211     { "(bad)",          { XX } },
9212     { "psrad",          { MS, Ib } },
9213   },
9214   {
9215     /* MOD_0F72_REG_6 */
9216     { "(bad)",          { XX } },
9217     { "pslld",          { MS, Ib } },
9218   },
9219   {
9220     /* MOD_0F73_REG_2 */
9221     { "(bad)",          { XX } },
9222     { "psrlq",          { MS, Ib } },
9223   },
9224   {
9225     /* MOD_0F73_REG_3 */
9226     { "(bad)",          { XX } },
9227     { PREFIX_TABLE (PREFIX_0F73_REG_3) },
9228   },
9229   {
9230     /* MOD_0F73_REG_6 */
9231     { "(bad)",          { XX } },
9232     { "psllq",          { MS, Ib } },
9233   },
9234   {
9235     /* MOD_0F73_REG_7 */
9236     { "(bad)",          { XX } },
9237     { PREFIX_TABLE (PREFIX_0F73_REG_7) },
9238   },
9239   {
9240     /* MOD_0FAE_REG_0 */
9241     { "fxsave",         { M } },
9242     { "(bad)",          { XX } },
9243   },
9244   {
9245     /* MOD_0FAE_REG_1 */
9246     { "fxrstor",        { M } },
9247     { "(bad)",          { XX } },
9248   },
9249   {
9250     /* MOD_0FAE_REG_2 */
9251     { "ldmxcsr",        { Md } },
9252     { "(bad)",          { XX } },
9253   },
9254   {
9255     /* MOD_0FAE_REG_3 */
9256     { "stmxcsr",        { Md } },
9257     { "(bad)",          { XX } },
9258   },
9259   {
9260     /* MOD_0FAE_REG_4 */
9261     { "xsave",          { M } },
9262     { "(bad)",          { XX } },
9263   },
9264   {
9265     /* MOD_0FAE_REG_5 */
9266     { "xrstor",         { M } },
9267     { RM_TABLE (RM_0FAE_REG_5) },
9268   },
9269   {
9270     /* MOD_0FAE_REG_6 */
9271     { "xsaveopt",       { M } },
9272     { RM_TABLE (RM_0FAE_REG_6) },
9273   },
9274   {
9275     /* MOD_0FAE_REG_7 */
9276     { "clflush",        { Mb } },
9277     { RM_TABLE (RM_0FAE_REG_7) },
9278   },
9279   {
9280     /* MOD_0FB2 */
9281     { "lssS",           { Gv, Mp } },
9282     { "(bad)",          { XX } },
9283   },
9284   {
9285     /* MOD_0FB4 */
9286     { "lfsS",           { Gv, Mp } },
9287     { "(bad)",          { XX } },
9288   },
9289   {
9290     /* MOD_0FB5 */
9291     { "lgsS",           { Gv, Mp } },
9292     { "(bad)",          { XX } },
9293   },
9294   {
9295     /* MOD_0FC7_REG_6 */
9296     { PREFIX_TABLE (PREFIX_0FC7_REG_6) },
9297     { "(bad)",          { XX } },
9298   },
9299   {
9300     /* MOD_0FC7_REG_7 */
9301     { "vmptrst",        { Mq } },
9302     { "(bad)",          { XX } },
9303   },
9304   {
9305     /* MOD_0FD7 */
9306     { "(bad)",          { XX } },
9307     { "pmovmskb",       { Gdq, MS } },
9308   },
9309   {
9310     /* MOD_0FE7_PREFIX_2 */
9311     { "movntdq",        { Mx, XM } },
9312     { "(bad)",          { XX } },
9313   },
9314   {
9315     /* MOD_0FF0_PREFIX_3 */
9316     { "lddqu",          { XM, M } },
9317     { "(bad)",          { XX } },
9318   },
9319   {
9320     /* MOD_0F382A_PREFIX_2 */
9321     { "movntdqa",       { XM, Mx } },
9322     { "(bad)",          { XX } },
9323   },
9324   {
9325     /* MOD_62_32BIT */
9326     { "bound{S|}",      { Gv, Ma } },
9327     { "(bad)",          { XX } },
9328   },
9329   {
9330     /* MOD_C4_32BIT */
9331     { "lesS",           { Gv, Mp } },
9332     { VEX_C4_TABLE (VEX_0F) },
9333   },
9334   {
9335     /* MOD_C5_32BIT */
9336     { "ldsS",           { Gv, Mp } },
9337     { VEX_C5_TABLE (VEX_0F) },
9338   },
9339   {
9340     /* MOD_VEX_12_PREFIX_0 */
9341     { VEX_LEN_TABLE (VEX_LEN_12_P_0_M_0) },
9342     { VEX_LEN_TABLE (VEX_LEN_12_P_0_M_1) },
9343   },
9344   {
9345     /* MOD_VEX_13 */
9346     { VEX_LEN_TABLE (VEX_LEN_13_M_0) },
9347     { "(bad)",          { XX } },
9348   },
9349   {
9350     /* MOD_VEX_16_PREFIX_0 */
9351     { VEX_LEN_TABLE (VEX_LEN_16_P_0_M_0) },
9352     { VEX_LEN_TABLE (VEX_LEN_16_P_0_M_1) },
9353   },
9354   {
9355     /* MOD_VEX_17 */
9356     { VEX_LEN_TABLE (VEX_LEN_17_M_0) },
9357     { "(bad)",          { XX } },
9358   },
9359   {
9360     /* MOD_VEX_2B */
9361     { "vmovntpX",       { Mx, XM } },
9362     { "(bad)",          { XX } },
9363   },
9364   {
9365     /* MOD_VEX_51 */
9366     { "(bad)",          { XX } },
9367     { "vmovmskpX",      { Gdq, XS } },
9368   },
9369   {
9370     /* MOD_VEX_71_REG_2 */
9371     { "(bad)",          { XX } },
9372     { PREFIX_TABLE (PREFIX_VEX_71_REG_2) },
9373   },
9374   {
9375     /* MOD_VEX_71_REG_4 */
9376     { "(bad)",          { XX } },
9377     { PREFIX_TABLE (PREFIX_VEX_71_REG_4) },
9378   },
9379   {
9380     /* MOD_VEX_71_REG_6 */
9381     { "(bad)",          { XX } },
9382     { PREFIX_TABLE (PREFIX_VEX_71_REG_6) },
9383   },
9384   {
9385     /* MOD_VEX_72_REG_2 */
9386     { "(bad)",          { XX } },
9387     { PREFIX_TABLE (PREFIX_VEX_72_REG_2) },
9388   },
9389   {
9390     /* MOD_VEX_72_REG_4 */
9391     { "(bad)",          { XX } },
9392     { PREFIX_TABLE (PREFIX_VEX_72_REG_4) },
9393   },
9394   {
9395     /* MOD_VEX_72_REG_6 */
9396     { "(bad)",          { XX } },
9397     { PREFIX_TABLE (PREFIX_VEX_72_REG_6) },
9398   },
9399   {
9400     /* MOD_VEX_73_REG_2 */
9401     { "(bad)",          { XX } },
9402     { PREFIX_TABLE (PREFIX_VEX_73_REG_2) },
9403   },
9404   {
9405     /* MOD_VEX_73_REG_3 */
9406     { "(bad)",          { XX } },
9407     { PREFIX_TABLE (PREFIX_VEX_73_REG_3) },
9408   },
9409   {
9410     /* MOD_VEX_73_REG_6 */
9411     { "(bad)",          { XX } },
9412     { PREFIX_TABLE (PREFIX_VEX_73_REG_6) },
9413   },
9414   {
9415     /* MOD_VEX_73_REG_7 */
9416     { "(bad)",          { XX } },
9417     { PREFIX_TABLE (PREFIX_VEX_73_REG_7) },
9418   },
9419   {
9420     /* MOD_VEX_AE_REG_2 */
9421     { VEX_LEN_TABLE (VEX_LEN_AE_R_2_M_0) },
9422     { "(bad)",          { XX } },
9423   },
9424   {
9425     /* MOD_VEX_AE_REG_3 */
9426     { VEX_LEN_TABLE (VEX_LEN_AE_R_3_M_0) },
9427     { "(bad)",          { XX } },
9428   },
9429   {
9430     /* MOD_VEX_D7_PREFIX_2 */
9431     { "(bad)",          { XX } },
9432     { VEX_LEN_TABLE (VEX_LEN_D7_P_2_M_1) },
9433   },
9434   {
9435     /* MOD_VEX_E7_PREFIX_2 */
9436     { "vmovntdq",       { Mx, XM } },
9437     { "(bad)",          { XX } },
9438   },
9439   {
9440     /* MOD_VEX_F0_PREFIX_3 */
9441     { "vlddqu",         { XM, M } },
9442     { "(bad)",          { XX } },
9443   },
9444   {
9445     /* MOD_VEX_3818_PREFIX_2 */
9446     { "vbroadcastss",   { XM, Md } },
9447     { "(bad)",          { XX } },
9448   },
9449   {
9450     /* MOD_VEX_3819_PREFIX_2 */
9451     { VEX_LEN_TABLE (VEX_LEN_3819_P_2_M_0) },
9452     { "(bad)",          { XX } },
9453   },
9454   {
9455     /* MOD_VEX_381A_PREFIX_2 */
9456     { VEX_LEN_TABLE (VEX_LEN_381A_P_2_M_0) },
9457     { "(bad)",          { XX } },
9458   },
9459   {
9460     /* MOD_VEX_382A_PREFIX_2 */
9461     { VEX_LEN_TABLE (VEX_LEN_382A_P_2_M_0) },
9462     { "(bad)",          { XX } },
9463   },
9464   {
9465     /* MOD_VEX_382C_PREFIX_2 */
9466     { "vmaskmovps",     { XM, Vex, Mx } },
9467     { "(bad)",          { XX } },
9468   },
9469   {
9470     /* MOD_VEX_382D_PREFIX_2 */
9471     { "vmaskmovpd",     { XM, Vex, Mx } },
9472     { "(bad)",          { XX } },
9473   },
9474   {
9475     /* MOD_VEX_382E_PREFIX_2 */
9476     { "vmaskmovps",     { Mx, Vex, XM } },
9477     { "(bad)",          { XX } },
9478   },
9479   {
9480     /* MOD_VEX_382F_PREFIX_2 */
9481     { "vmaskmovpd",     { Mx, Vex, XM } },
9482     { "(bad)",          { XX } },
9483   },
9484 };
9485
9486 static const struct dis386 rm_table[][8] = {
9487   {
9488     /* RM_0F01_REG_0 */
9489     { "(bad)",          { XX } },
9490     { "vmcall",         { Skip_MODRM } },
9491     { "vmlaunch",       { Skip_MODRM } },
9492     { "vmresume",       { Skip_MODRM } },
9493     { "vmxoff",         { Skip_MODRM } },
9494     { "(bad)",          { XX } },
9495     { "(bad)",          { XX } },
9496     { "(bad)",          { XX } },
9497   },
9498   {
9499     /* RM_0F01_REG_1 */
9500     { "monitor",        { { OP_Monitor, 0 } } },
9501     { "mwait",          { { OP_Mwait, 0 } } },
9502     { "(bad)",          { XX } },
9503     { "(bad)",          { XX } },
9504     { "(bad)",          { XX } },
9505     { "(bad)",          { XX } },
9506     { "(bad)",          { XX } },
9507     { "(bad)",          { XX } },
9508   },
9509   {
9510     /* RM_0F01_REG_2 */
9511     { "xgetbv",         { Skip_MODRM } },
9512     { "xsetbv",         { Skip_MODRM } },
9513     { "(bad)",          { XX } },
9514     { "(bad)",          { XX } },
9515     { "(bad)",          { XX } },
9516     { "(bad)",          { XX } },
9517     { "(bad)",          { XX } },
9518     { "(bad)",          { XX } },
9519   },
9520   {
9521     /* RM_0F01_REG_3 */
9522     { "vmrun",          { Skip_MODRM } },
9523     { "vmmcall",        { Skip_MODRM } },
9524     { "vmload",         { Skip_MODRM } },
9525     { "vmsave",         { Skip_MODRM } },
9526     { "stgi",           { Skip_MODRM } },
9527     { "clgi",           { Skip_MODRM } },
9528     { "skinit",         { Skip_MODRM } },
9529     { "invlpga",        { Skip_MODRM } },
9530   },
9531   {
9532     /* RM_0F01_REG_7 */
9533     { "swapgs",         { Skip_MODRM } },
9534     { "rdtscp",         { Skip_MODRM } },
9535     { "(bad)",          { XX } },
9536     { "(bad)",          { XX } },
9537     { "(bad)",          { XX } },
9538     { "(bad)",          { XX } },
9539     { "(bad)",          { XX } },
9540     { "(bad)",          { XX } },
9541   },
9542   {
9543     /* RM_0FAE_REG_5 */
9544     { "lfence",         { Skip_MODRM } },
9545     { "(bad)",          { XX } },
9546     { "(bad)",          { XX } },
9547     { "(bad)",          { XX } },
9548     { "(bad)",          { XX } },
9549     { "(bad)",          { XX } },
9550     { "(bad)",          { XX } },
9551     { "(bad)",          { XX } },
9552   },
9553   {
9554     /* RM_0FAE_REG_6 */
9555     { "mfence",         { Skip_MODRM } },
9556     { "(bad)",          { XX } },
9557     { "(bad)",          { XX } },
9558     { "(bad)",          { XX } },
9559     { "(bad)",          { XX } },
9560     { "(bad)",          { XX } },
9561     { "(bad)",          { XX } },
9562     { "(bad)",          { XX } },
9563   },
9564   {
9565     /* RM_0FAE_REG_7 */
9566     { "sfence",         { Skip_MODRM } },
9567     { "(bad)",          { XX } },
9568     { "(bad)",          { XX } },
9569     { "(bad)",          { XX } },
9570     { "(bad)",          { XX } },
9571     { "(bad)",          { XX } },
9572     { "(bad)",          { XX } },
9573     { "(bad)",          { XX } },
9574   },
9575 };
9576
9577 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
9578
9579 static void
9580 ckprefix (void)
9581 {
9582   int newrex;
9583   rex = 0;
9584   rex_original = 0;
9585   rex_ignored = 0;
9586   prefixes = 0;
9587   used_prefixes = 0;
9588   rex_used = 0;
9589   while (1)
9590     {
9591       FETCH_DATA (the_info, codep + 1);
9592       newrex = 0;
9593       switch (*codep)
9594         {
9595         /* REX prefixes family.  */
9596         case 0x40:
9597         case 0x41:
9598         case 0x42:
9599         case 0x43:
9600         case 0x44:
9601         case 0x45:
9602         case 0x46:
9603         case 0x47:
9604         case 0x48:
9605         case 0x49:
9606         case 0x4a:
9607         case 0x4b:
9608         case 0x4c:
9609         case 0x4d:
9610         case 0x4e:
9611         case 0x4f:
9612             if (address_mode == mode_64bit)
9613               newrex = *codep;
9614             else
9615               return;
9616           break;
9617         case 0xf3:
9618           prefixes |= PREFIX_REPZ;
9619           break;
9620         case 0xf2:
9621           prefixes |= PREFIX_REPNZ;
9622           break;
9623         case 0xf0:
9624           prefixes |= PREFIX_LOCK;
9625           break;
9626         case 0x2e:
9627           prefixes |= PREFIX_CS;
9628           break;
9629         case 0x36:
9630           prefixes |= PREFIX_SS;
9631           break;
9632         case 0x3e:
9633           prefixes |= PREFIX_DS;
9634           break;
9635         case 0x26:
9636           prefixes |= PREFIX_ES;
9637           break;
9638         case 0x64:
9639           prefixes |= PREFIX_FS;
9640           break;
9641         case 0x65:
9642           prefixes |= PREFIX_GS;
9643           break;
9644         case 0x66:
9645           prefixes |= PREFIX_DATA;
9646           break;
9647         case 0x67:
9648           prefixes |= PREFIX_ADDR;
9649           break;
9650         case FWAIT_OPCODE:
9651           /* fwait is really an instruction.  If there are prefixes
9652              before the fwait, they belong to the fwait, *not* to the
9653              following instruction.  */
9654           if (prefixes || rex)
9655             {
9656               prefixes |= PREFIX_FWAIT;
9657               codep++;
9658               return;
9659             }
9660           prefixes = PREFIX_FWAIT;
9661           break;
9662         default:
9663           return;
9664         }
9665       /* Rex is ignored when followed by another prefix.  */
9666       if (rex)
9667         {
9668           rex_used = rex;
9669           return;
9670         }
9671       rex = newrex;
9672       rex_original = rex;
9673       codep++;
9674     }
9675 }
9676
9677 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
9678    prefix byte.  */
9679
9680 static const char *
9681 prefix_name (int pref, int sizeflag)
9682 {
9683   static const char *rexes [16] =
9684     {
9685       "rex",            /* 0x40 */
9686       "rex.B",          /* 0x41 */
9687       "rex.X",          /* 0x42 */
9688       "rex.XB",         /* 0x43 */
9689       "rex.R",          /* 0x44 */
9690       "rex.RB",         /* 0x45 */
9691       "rex.RX",         /* 0x46 */
9692       "rex.RXB",        /* 0x47 */
9693       "rex.W",          /* 0x48 */
9694       "rex.WB",         /* 0x49 */
9695       "rex.WX",         /* 0x4a */
9696       "rex.WXB",        /* 0x4b */
9697       "rex.WR",         /* 0x4c */
9698       "rex.WRB",        /* 0x4d */
9699       "rex.WRX",        /* 0x4e */
9700       "rex.WRXB",       /* 0x4f */
9701     };
9702
9703   switch (pref)
9704     {
9705     /* REX prefixes family.  */
9706     case 0x40:
9707     case 0x41:
9708     case 0x42:
9709     case 0x43:
9710     case 0x44:
9711     case 0x45:
9712     case 0x46:
9713     case 0x47:
9714     case 0x48:
9715     case 0x49:
9716     case 0x4a:
9717     case 0x4b:
9718     case 0x4c:
9719     case 0x4d:
9720     case 0x4e:
9721     case 0x4f:
9722       return rexes [pref - 0x40];
9723     case 0xf3:
9724       return "repz";
9725     case 0xf2:
9726       return "repnz";
9727     case 0xf0:
9728       return "lock";
9729     case 0x2e:
9730       return "cs";
9731     case 0x36:
9732       return "ss";
9733     case 0x3e:
9734       return "ds";
9735     case 0x26:
9736       return "es";
9737     case 0x64:
9738       return "fs";
9739     case 0x65:
9740       return "gs";
9741     case 0x66:
9742       return (sizeflag & DFLAG) ? "data16" : "data32";
9743     case 0x67:
9744       if (address_mode == mode_64bit)
9745         return (sizeflag & AFLAG) ? "addr32" : "addr64";
9746       else
9747         return (sizeflag & AFLAG) ? "addr16" : "addr32";
9748     case FWAIT_OPCODE:
9749       return "fwait";
9750     default:
9751       return NULL;
9752     }
9753 }
9754
9755 static char op_out[MAX_OPERANDS][100];
9756 static int op_ad, op_index[MAX_OPERANDS];
9757 static int two_source_ops;
9758 static bfd_vma op_address[MAX_OPERANDS];
9759 static bfd_vma op_riprel[MAX_OPERANDS];
9760 static bfd_vma start_pc;
9761
9762 /*
9763  *   On the 386's of 1988, the maximum length of an instruction is 15 bytes.
9764  *   (see topic "Redundant prefixes" in the "Differences from 8086"
9765  *   section of the "Virtual 8086 Mode" chapter.)
9766  * 'pc' should be the address of this instruction, it will
9767  *   be used to print the target address if this is a relative jump or call
9768  * The function returns the length of this instruction in bytes.
9769  */
9770
9771 static char intel_syntax;
9772 static char intel_mnemonic = !SYSV386_COMPAT;
9773 static char open_char;
9774 static char close_char;
9775 static char separator_char;
9776 static char scale_char;
9777
9778 /* Here for backwards compatibility.  When gdb stops using
9779    print_insn_i386_att and print_insn_i386_intel these functions can
9780    disappear, and print_insn_i386 be merged into print_insn.  */
9781 int
9782 print_insn_i386_att (bfd_vma pc, disassemble_info *info)
9783 {
9784   intel_syntax = 0;
9785
9786   return print_insn (pc, info);
9787 }
9788
9789 int
9790 print_insn_i386_intel (bfd_vma pc, disassemble_info *info)
9791 {
9792   intel_syntax = 1;
9793
9794   return print_insn (pc, info);
9795 }
9796
9797 int
9798 print_insn_i386 (bfd_vma pc, disassemble_info *info)
9799 {
9800   intel_syntax = -1;
9801
9802   return print_insn (pc, info);
9803 }
9804
9805 void
9806 print_i386_disassembler_options (FILE *stream)
9807 {
9808   fprintf (stream, _("\n\
9809 The following i386/x86-64 specific disassembler options are supported for use\n\
9810 with the -M switch (multiple options should be separated by commas):\n"));
9811
9812   fprintf (stream, _("  x86-64      Disassemble in 64bit mode\n"));
9813   fprintf (stream, _("  i386        Disassemble in 32bit mode\n"));
9814   fprintf (stream, _("  i8086       Disassemble in 16bit mode\n"));
9815   fprintf (stream, _("  att         Display instruction in AT&T syntax\n"));
9816   fprintf (stream, _("  intel       Display instruction in Intel syntax\n"));
9817   fprintf (stream, _("  att-mnemonic\n"
9818                      "              Display instruction in AT&T mnemonic\n"));
9819   fprintf (stream, _("  intel-mnemonic\n"
9820                      "              Display instruction in Intel mnemonic\n"));
9821   fprintf (stream, _("  addr64      Assume 64bit address size\n"));
9822   fprintf (stream, _("  addr32      Assume 32bit address size\n"));
9823   fprintf (stream, _("  addr16      Assume 16bit address size\n"));
9824   fprintf (stream, _("  data32      Assume 32bit data size\n"));
9825   fprintf (stream, _("  data16      Assume 16bit data size\n"));
9826   fprintf (stream, _("  suffix      Always display instruction suffix in AT&T syntax\n"));
9827 }
9828
9829 /* Get a pointer to struct dis386 with a valid name.  */
9830
9831 static const struct dis386 *
9832 get_valid_dis386 (const struct dis386 *dp, disassemble_info *info)
9833 {
9834   int index, vex_table_index;
9835
9836   if (dp->name != NULL)
9837     return dp;
9838
9839   switch (dp->op[0].bytemode)
9840     {
9841     case USE_REG_TABLE:
9842       dp = &reg_table[dp->op[1].bytemode][modrm.reg];
9843       break;
9844
9845     case USE_MOD_TABLE:
9846       index = modrm.mod == 0x3 ? 1 : 0;
9847       dp = &mod_table[dp->op[1].bytemode][index];
9848       break;
9849
9850     case USE_RM_TABLE:
9851       dp = &rm_table[dp->op[1].bytemode][modrm.rm];
9852       break;
9853
9854     case USE_PREFIX_TABLE:
9855       if (need_vex)
9856         {
9857           /* The prefix in VEX is implicit.  */
9858           switch (vex.prefix)
9859             {
9860             case 0:
9861               index = 0;
9862               break;
9863             case REPE_PREFIX_OPCODE:
9864               index = 1;
9865               break;
9866             case DATA_PREFIX_OPCODE:
9867               index = 2;
9868               break;
9869             case REPNE_PREFIX_OPCODE:
9870               index = 3;
9871               break;
9872             default:
9873               abort ();
9874               break;
9875             }
9876         }
9877       else
9878         {
9879           index = 0;
9880           used_prefixes |= (prefixes & PREFIX_REPZ);
9881           if (prefixes & PREFIX_REPZ)
9882             {
9883               index = 1;
9884               repz_prefix = NULL;
9885             }
9886           else
9887             {
9888               /* We should check PREFIX_REPNZ and PREFIX_REPZ before
9889                  PREFIX_DATA.  */
9890               used_prefixes |= (prefixes & PREFIX_REPNZ);
9891               if (prefixes & PREFIX_REPNZ)
9892                 {
9893                   index = 3;
9894                   repnz_prefix = NULL;
9895                 }
9896               else
9897                 {
9898                   used_prefixes |= (prefixes & PREFIX_DATA);
9899                   if (prefixes & PREFIX_DATA)
9900                     {
9901                       index = 2;
9902                       data_prefix = NULL;
9903                     }
9904                 }
9905             }
9906         }
9907       dp = &prefix_table[dp->op[1].bytemode][index];
9908       break;
9909
9910     case USE_X86_64_TABLE:
9911       index = address_mode == mode_64bit ? 1 : 0;
9912       dp = &x86_64_table[dp->op[1].bytemode][index];
9913       break;
9914
9915     case USE_3BYTE_TABLE:
9916       FETCH_DATA (info, codep + 2);
9917       index = *codep++;
9918       dp = &three_byte_table[dp->op[1].bytemode][index];
9919       modrm.mod = (*codep >> 6) & 3;
9920       modrm.reg = (*codep >> 3) & 7;
9921       modrm.rm = *codep & 7;
9922       break;
9923
9924     case USE_VEX_LEN_TABLE:
9925       if (!need_vex)
9926         abort ();
9927
9928       switch (vex.length)
9929         {
9930         case 128:
9931           index = 0;
9932           break;
9933         case 256:
9934           index = 1;
9935           break;
9936         default:
9937           abort ();
9938           break;
9939         }
9940
9941       dp = &vex_len_table[dp->op[1].bytemode][index];
9942       break;
9943
9944     case USE_VEX_C4_TABLE:
9945       FETCH_DATA (info, codep + 3);
9946       /* All bits in the REX prefix are ignored.  */
9947       rex_ignored = rex;
9948       rex = ~(*codep >> 5) & 0x7;
9949       switch ((*codep & 0x1f))
9950         {
9951         default:
9952           BadOp ();
9953         case 0x1:
9954           vex_table_index = 0;
9955           break;
9956         case 0x2:
9957           vex_table_index = 1;
9958           break;
9959         case 0x3:
9960           vex_table_index = 2;
9961           break;
9962         }
9963       codep++;
9964       vex.w = *codep & 0x80;
9965       if (vex.w && address_mode == mode_64bit)
9966         rex |= REX_W;
9967
9968       vex.register_specifier = (~(*codep >> 3)) & 0xf;
9969       if (address_mode != mode_64bit
9970           && vex.register_specifier > 0x7)
9971         BadOp ();
9972
9973       vex.length = (*codep & 0x4) ? 256 : 128;
9974       switch ((*codep & 0x3))
9975         {
9976         case 0:
9977           vex.prefix = 0;
9978           break;
9979         case 1:
9980           vex.prefix = DATA_PREFIX_OPCODE;
9981           break;
9982         case 2:
9983           vex.prefix = REPE_PREFIX_OPCODE;
9984           break;
9985         case 3:
9986           vex.prefix = REPNE_PREFIX_OPCODE;
9987           break;
9988         }
9989       need_vex = 1;
9990       need_vex_reg = 1;
9991       codep++;
9992       index = *codep++;
9993       dp = &vex_table[vex_table_index][index];
9994       /* There is no MODRM byte for VEX [82|77].  */
9995       if (index != 0x77 && index != 0x82)
9996         {
9997           FETCH_DATA (info, codep + 1);
9998           modrm.mod = (*codep >> 6) & 3;
9999           modrm.reg = (*codep >> 3) & 7;
10000           modrm.rm = *codep & 7;
10001         }
10002       break;
10003
10004     case USE_VEX_C5_TABLE:
10005       FETCH_DATA (info, codep + 2);
10006       /* All bits in the REX prefix are ignored.  */
10007       rex_ignored = rex;
10008       rex = (*codep & 0x80) ? 0 : REX_R;
10009
10010       vex.register_specifier = (~(*codep >> 3)) & 0xf;
10011       if (address_mode != mode_64bit
10012           && vex.register_specifier > 0x7)
10013         BadOp ();
10014
10015       vex.length = (*codep & 0x4) ? 256 : 128;
10016       switch ((*codep & 0x3))
10017         {
10018         case 0:
10019           vex.prefix = 0;
10020           break;
10021         case 1:
10022           vex.prefix = DATA_PREFIX_OPCODE;
10023           break;
10024         case 2:
10025           vex.prefix = REPE_PREFIX_OPCODE;
10026           break;
10027         case 3:
10028           vex.prefix = REPNE_PREFIX_OPCODE;
10029           break;
10030         }
10031       need_vex = 1;
10032       need_vex_reg = 1;
10033       codep++;
10034       index = *codep++;
10035       dp = &vex_table[dp->op[1].bytemode][index];
10036       /* There is no MODRM byte for VEX [82|77].  */
10037       if (index != 0x77 && index != 0x82)
10038         {
10039           FETCH_DATA (info, codep + 1);
10040           modrm.mod = (*codep >> 6) & 3;
10041           modrm.reg = (*codep >> 3) & 7;
10042           modrm.rm = *codep & 7;
10043         }
10044       break;
10045
10046     default:
10047       oappend (INTERNAL_DISASSEMBLER_ERROR);
10048       return NULL;
10049     }
10050
10051   if (dp->name != NULL)
10052     return dp;
10053   else
10054     return get_valid_dis386 (dp, info);
10055 }
10056
10057 static int
10058 print_insn (bfd_vma pc, disassemble_info *info)
10059 {
10060   const struct dis386 *dp;
10061   int i;
10062   char *op_txt[MAX_OPERANDS];
10063   int needcomma;
10064   int sizeflag;
10065   const char *p;
10066   struct dis_private priv;
10067   unsigned char op;
10068   char prefix_obuf[32];
10069   char *prefix_obufp;
10070
10071   if (info->mach == bfd_mach_x86_64_intel_syntax
10072       || info->mach == bfd_mach_x86_64)
10073     address_mode = mode_64bit;
10074   else
10075     address_mode = mode_32bit;
10076
10077   if (intel_syntax == (char) -1)
10078     intel_syntax = (info->mach == bfd_mach_i386_i386_intel_syntax
10079                     || info->mach == bfd_mach_x86_64_intel_syntax);
10080
10081   if (info->mach == bfd_mach_i386_i386
10082       || info->mach == bfd_mach_x86_64
10083       || info->mach == bfd_mach_i386_i386_intel_syntax
10084       || info->mach == bfd_mach_x86_64_intel_syntax)
10085     priv.orig_sizeflag = AFLAG | DFLAG;
10086   else if (info->mach == bfd_mach_i386_i8086)
10087     priv.orig_sizeflag = 0;
10088   else
10089     abort ();
10090
10091   for (p = info->disassembler_options; p != NULL; )
10092     {
10093       if (CONST_STRNEQ (p, "x86-64"))
10094         {
10095           address_mode = mode_64bit;
10096           priv.orig_sizeflag = AFLAG | DFLAG;
10097         }
10098       else if (CONST_STRNEQ (p, "i386"))
10099         {
10100           address_mode = mode_32bit;
10101           priv.orig_sizeflag = AFLAG | DFLAG;
10102         }
10103       else if (CONST_STRNEQ (p, "i8086"))
10104         {
10105           address_mode = mode_16bit;
10106           priv.orig_sizeflag = 0;
10107         }
10108       else if (CONST_STRNEQ (p, "intel"))
10109         {
10110           intel_syntax = 1;
10111           if (CONST_STRNEQ (p + 5, "-mnemonic"))
10112             intel_mnemonic = 1;
10113         }
10114       else if (CONST_STRNEQ (p, "att"))
10115         {
10116           intel_syntax = 0;
10117           if (CONST_STRNEQ (p + 3, "-mnemonic"))
10118             intel_mnemonic = 0;
10119         }
10120       else if (CONST_STRNEQ (p, "addr"))
10121         {
10122           if (address_mode == mode_64bit)
10123             {
10124               if (p[4] == '3' && p[5] == '2')
10125                 priv.orig_sizeflag &= ~AFLAG;
10126               else if (p[4] == '6' && p[5] == '4')
10127                 priv.orig_sizeflag |= AFLAG;
10128             }
10129           else
10130             {
10131               if (p[4] == '1' && p[5] == '6')
10132                 priv.orig_sizeflag &= ~AFLAG;
10133               else if (p[4] == '3' && p[5] == '2')
10134                 priv.orig_sizeflag |= AFLAG;
10135             }
10136         }
10137       else if (CONST_STRNEQ (p, "data"))
10138         {
10139           if (p[4] == '1' && p[5] == '6')
10140             priv.orig_sizeflag &= ~DFLAG;
10141           else if (p[4] == '3' && p[5] == '2')
10142             priv.orig_sizeflag |= DFLAG;
10143         }
10144       else if (CONST_STRNEQ (p, "suffix"))
10145         priv.orig_sizeflag |= SUFFIX_ALWAYS;
10146
10147       p = strchr (p, ',');
10148       if (p != NULL)
10149         p++;
10150     }
10151
10152   if (intel_syntax)
10153     {
10154       names64 = intel_names64;
10155       names32 = intel_names32;
10156       names16 = intel_names16;
10157       names8 = intel_names8;
10158       names8rex = intel_names8rex;
10159       names_seg = intel_names_seg;
10160       index64 = intel_index64;
10161       index32 = intel_index32;
10162       index16 = intel_index16;
10163       open_char = '[';
10164       close_char = ']';
10165       separator_char = '+';
10166       scale_char = '*';
10167     }
10168   else
10169     {
10170       names64 = att_names64;
10171       names32 = att_names32;
10172       names16 = att_names16;
10173       names8 = att_names8;
10174       names8rex = att_names8rex;
10175       names_seg = att_names_seg;
10176       index64 = att_index64;
10177       index32 = att_index32;
10178       index16 = att_index16;
10179       open_char = '(';
10180       close_char =  ')';
10181       separator_char = ',';
10182       scale_char = ',';
10183     }
10184
10185   /* The output looks better if we put 7 bytes on a line, since that
10186      puts most long word instructions on a single line.  */
10187   info->bytes_per_line = 7;
10188
10189   info->private_data = &priv;
10190   priv.max_fetched = priv.the_buffer;
10191   priv.insn_start = pc;
10192
10193   obuf[0] = 0;
10194   for (i = 0; i < MAX_OPERANDS; ++i)
10195     {
10196       op_out[i][0] = 0;
10197       op_index[i] = -1;
10198     }
10199
10200   the_info = info;
10201   start_pc = pc;
10202   start_codep = priv.the_buffer;
10203   codep = priv.the_buffer;
10204
10205   if (setjmp (priv.bailout) != 0)
10206     {
10207       const char *name;
10208
10209       /* Getting here means we tried for data but didn't get it.  That
10210          means we have an incomplete instruction of some sort.  Just
10211          print the first byte as a prefix or a .byte pseudo-op.  */
10212       if (codep > priv.the_buffer)
10213         {
10214           name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
10215           if (name != NULL)
10216             (*info->fprintf_func) (info->stream, "%s", name);
10217           else
10218             {
10219               /* Just print the first byte as a .byte instruction.  */
10220               (*info->fprintf_func) (info->stream, ".byte 0x%x",
10221                                      (unsigned int) priv.the_buffer[0]);
10222             }
10223
10224           return 1;
10225         }
10226
10227       return -1;
10228     }
10229
10230   obufp = obuf;
10231   ckprefix ();
10232
10233   insn_codep = codep;
10234   sizeflag = priv.orig_sizeflag;
10235
10236   FETCH_DATA (info, codep + 1);
10237   two_source_ops = (*codep == 0x62) || (*codep == 0xc8);
10238
10239   if (((prefixes & PREFIX_FWAIT)
10240        && ((*codep < 0xd8) || (*codep > 0xdf)))
10241       || (rex && rex_used))
10242     {
10243       const char *name;
10244
10245       /* fwait not followed by floating point instruction, or rex followed
10246          by other prefixes.  Print the first prefix.  */
10247       name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
10248       if (name == NULL)
10249         name = INTERNAL_DISASSEMBLER_ERROR;
10250       (*info->fprintf_func) (info->stream, "%s", name);
10251       return 1;
10252     }
10253
10254   op = 0;
10255   if (*codep == 0x0f)
10256     {
10257       unsigned char threebyte;
10258       FETCH_DATA (info, codep + 2);
10259       threebyte = *++codep;
10260       dp = &dis386_twobyte[threebyte];
10261       need_modrm = twobyte_has_modrm[*codep];
10262       codep++;
10263     }
10264   else
10265     {
10266       dp = &dis386[*codep];
10267       need_modrm = onebyte_has_modrm[*codep];
10268       codep++;
10269     }
10270
10271   if ((prefixes & PREFIX_REPZ))
10272     {
10273       repz_prefix = "repz ";
10274       used_prefixes |= PREFIX_REPZ;
10275     }
10276   else
10277     repz_prefix = NULL;
10278
10279   if ((prefixes & PREFIX_REPNZ))
10280     {
10281       repnz_prefix = "repnz ";
10282       used_prefixes |= PREFIX_REPNZ;
10283     }
10284   else
10285     repnz_prefix = NULL;
10286
10287   if ((prefixes & PREFIX_LOCK))
10288     {
10289       lock_prefix = "lock ";
10290       used_prefixes |= PREFIX_LOCK;
10291     }
10292   else
10293     lock_prefix = NULL;
10294
10295   addr_prefix = NULL;
10296   if (prefixes & PREFIX_ADDR)
10297     {
10298       sizeflag ^= AFLAG;
10299       if (dp->op[2].bytemode != loop_jcxz_mode || intel_syntax)
10300         {
10301           if ((sizeflag & AFLAG) || address_mode == mode_64bit)
10302             addr_prefix = "addr32 ";
10303           else
10304             addr_prefix = "addr16 ";
10305           used_prefixes |= PREFIX_ADDR;
10306         }
10307     }
10308
10309   data_prefix = NULL;
10310   if ((prefixes & PREFIX_DATA))
10311     {
10312       sizeflag ^= DFLAG;
10313       if (dp->op[2].bytemode == cond_jump_mode
10314           && dp->op[0].bytemode == v_mode
10315           && !intel_syntax)
10316         {
10317           if (sizeflag & DFLAG)
10318             data_prefix = "data32 ";
10319           else
10320             data_prefix = "data16 ";
10321           used_prefixes |= PREFIX_DATA;
10322         }
10323     }
10324
10325   if (need_modrm)
10326     {
10327       FETCH_DATA (info, codep + 1);
10328       modrm.mod = (*codep >> 6) & 3;
10329       modrm.reg = (*codep >> 3) & 7;
10330       modrm.rm = *codep & 7;
10331     }
10332
10333   if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
10334     {
10335       dofloat (sizeflag);
10336     }
10337   else
10338     {
10339       need_vex = 0;
10340       need_vex_reg = 0;
10341       vex_w_done = 0;
10342       dp = get_valid_dis386 (dp, info);
10343       if (dp != NULL && putop (dp->name, sizeflag) == 0)
10344         {
10345           for (i = 0; i < MAX_OPERANDS; ++i)
10346             {
10347               obufp = op_out[i];
10348               op_ad = MAX_OPERANDS - 1 - i;
10349               if (dp->op[i].rtn)
10350                 (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag);
10351             }
10352         }
10353     }
10354
10355   /* See if any prefixes were not used.  If so, print the first one
10356      separately.  If we don't do this, we'll wind up printing an
10357      instruction stream which does not precisely correspond to the
10358      bytes we are disassembling.  */
10359   if ((prefixes & ~used_prefixes) != 0)
10360     {
10361       const char *name;
10362
10363       name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
10364       if (name == NULL)
10365         name = INTERNAL_DISASSEMBLER_ERROR;
10366       (*info->fprintf_func) (info->stream, "%s", name);
10367       return 1;
10368     }
10369   if ((rex_original & ~rex_used) || rex_ignored)
10370     {
10371       const char *name;
10372       name = prefix_name (rex_original, priv.orig_sizeflag);
10373       if (name == NULL)
10374         name = INTERNAL_DISASSEMBLER_ERROR;
10375       (*info->fprintf_func) (info->stream, "%s ", name);
10376     }
10377
10378   prefix_obuf[0] = 0;
10379   prefix_obufp = prefix_obuf;
10380   if (lock_prefix)
10381     prefix_obufp = stpcpy (prefix_obufp, lock_prefix);
10382   if (repz_prefix)
10383     prefix_obufp = stpcpy (prefix_obufp, repz_prefix);
10384   if (repnz_prefix)
10385     prefix_obufp = stpcpy (prefix_obufp, repnz_prefix);
10386   if (addr_prefix)
10387     prefix_obufp = stpcpy (prefix_obufp, addr_prefix);
10388   if (data_prefix)
10389     prefix_obufp = stpcpy (prefix_obufp, data_prefix);
10390
10391   if (prefix_obuf[0] != 0)
10392     (*info->fprintf_func) (info->stream, "%s", prefix_obuf);
10393
10394   obufp = mnemonicendp;
10395   for (i = strlen (obuf) + strlen (prefix_obuf); i < 6; i++)
10396     oappend (" ");
10397   oappend (" ");
10398   (*info->fprintf_func) (info->stream, "%s", obuf);
10399
10400   /* The enter and bound instructions are printed with operands in the same
10401      order as the intel book; everything else is printed in reverse order.  */
10402   if (intel_syntax || two_source_ops)
10403     {
10404       bfd_vma riprel;
10405
10406       for (i = 0; i < MAX_OPERANDS; ++i)
10407         op_txt[i] = op_out[i];
10408
10409       for (i = 0; i < (MAX_OPERANDS >> 1); ++i)
10410         {
10411           op_ad = op_index[i];
10412           op_index[i] = op_index[MAX_OPERANDS - 1 - i];
10413           op_index[MAX_OPERANDS - 1 - i] = op_ad;
10414           riprel = op_riprel[i];
10415           op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i];
10416           op_riprel[MAX_OPERANDS - 1 - i] = riprel;
10417         }
10418     }
10419   else
10420     {
10421       for (i = 0; i < MAX_OPERANDS; ++i)
10422         op_txt[MAX_OPERANDS - 1 - i] = op_out[i];
10423     }
10424
10425   needcomma = 0;
10426   for (i = 0; i < MAX_OPERANDS; ++i)
10427     if (*op_txt[i])
10428       {
10429         if (needcomma)
10430           (*info->fprintf_func) (info->stream, ",");
10431         if (op_index[i] != -1 && !op_riprel[i])
10432           (*info->print_address_func) ((bfd_vma) op_address[op_index[i]], info);
10433         else
10434           (*info->fprintf_func) (info->stream, "%s", op_txt[i]);
10435         needcomma = 1;
10436       }
10437
10438   for (i = 0; i < MAX_OPERANDS; i++)
10439     if (op_index[i] != -1 && op_riprel[i])
10440       {
10441         (*info->fprintf_func) (info->stream, "        # ");
10442         (*info->print_address_func) ((bfd_vma) (start_pc + codep - start_codep
10443                                                 + op_address[op_index[i]]), info);
10444         break;
10445       }
10446   return codep - priv.the_buffer;
10447 }
10448
10449 static const char *float_mem[] = {
10450   /* d8 */
10451   "fadd{s|}",
10452   "fmul{s|}",
10453   "fcom{s|}",
10454   "fcomp{s|}",
10455   "fsub{s|}",
10456   "fsubr{s|}",
10457   "fdiv{s|}",
10458   "fdivr{s|}",
10459   /* d9 */
10460   "fld{s|}",
10461   "(bad)",
10462   "fst{s|}",
10463   "fstp{s|}",
10464   "fldenvIC",
10465   "fldcw",
10466   "fNstenvIC",
10467   "fNstcw",
10468   /* da */
10469   "fiadd{l|}",
10470   "fimul{l|}",
10471   "ficom{l|}",
10472   "ficomp{l|}",
10473   "fisub{l|}",
10474   "fisubr{l|}",
10475   "fidiv{l|}",
10476   "fidivr{l|}",
10477   /* db */
10478   "fild{l|}",
10479   "fisttp{l|}",
10480   "fist{l|}",
10481   "fistp{l|}",
10482   "(bad)",
10483   "fld{t||t|}",
10484   "(bad)",
10485   "fstp{t||t|}",
10486   /* dc */
10487   "fadd{l|}",
10488   "fmul{l|}",
10489   "fcom{l|}",
10490   "fcomp{l|}",
10491   "fsub{l|}",
10492   "fsubr{l|}",
10493   "fdiv{l|}",
10494   "fdivr{l|}",
10495   /* dd */
10496   "fld{l|}",
10497   "fisttp{ll|}",
10498   "fst{l||}",
10499   "fstp{l|}",
10500   "frstorIC",
10501   "(bad)",
10502   "fNsaveIC",
10503   "fNstsw",
10504   /* de */
10505   "fiadd",
10506   "fimul",
10507   "ficom",
10508   "ficomp",
10509   "fisub",
10510   "fisubr",
10511   "fidiv",
10512   "fidivr",
10513   /* df */
10514   "fild",
10515   "fisttp",
10516   "fist",
10517   "fistp",
10518   "fbld",
10519   "fild{ll|}",
10520   "fbstp",
10521   "fistp{ll|}",
10522 };
10523
10524 static const unsigned char float_mem_mode[] = {
10525   /* d8 */
10526   d_mode,
10527   d_mode,
10528   d_mode,
10529   d_mode,
10530   d_mode,
10531   d_mode,
10532   d_mode,
10533   d_mode,
10534   /* d9 */
10535   d_mode,
10536   0,
10537   d_mode,
10538   d_mode,
10539   0,
10540   w_mode,
10541   0,
10542   w_mode,
10543   /* da */
10544   d_mode,
10545   d_mode,
10546   d_mode,
10547   d_mode,
10548   d_mode,
10549   d_mode,
10550   d_mode,
10551   d_mode,
10552   /* db */
10553   d_mode,
10554   d_mode,
10555   d_mode,
10556   d_mode,
10557   0,
10558   t_mode,
10559   0,
10560   t_mode,
10561   /* dc */
10562   q_mode,
10563   q_mode,
10564   q_mode,
10565   q_mode,
10566   q_mode,
10567   q_mode,
10568   q_mode,
10569   q_mode,
10570   /* dd */
10571   q_mode,
10572   q_mode,
10573   q_mode,
10574   q_mode,
10575   0,
10576   0,
10577   0,
10578   w_mode,
10579   /* de */
10580   w_mode,
10581   w_mode,
10582   w_mode,
10583   w_mode,
10584   w_mode,
10585   w_mode,
10586   w_mode,
10587   w_mode,
10588   /* df */
10589   w_mode,
10590   w_mode,
10591   w_mode,
10592   w_mode,
10593   t_mode,
10594   q_mode,
10595   t_mode,
10596   q_mode
10597 };
10598
10599 #define ST { OP_ST, 0 }
10600 #define STi { OP_STi, 0 }
10601
10602 #define FGRPd9_2 NULL, { { NULL, 0 } }
10603 #define FGRPd9_4 NULL, { { NULL, 1 } }
10604 #define FGRPd9_5 NULL, { { NULL, 2 } }
10605 #define FGRPd9_6 NULL, { { NULL, 3 } }
10606 #define FGRPd9_7 NULL, { { NULL, 4 } }
10607 #define FGRPda_5 NULL, { { NULL, 5 } }
10608 #define FGRPdb_4 NULL, { { NULL, 6 } }
10609 #define FGRPde_3 NULL, { { NULL, 7 } }
10610 #define FGRPdf_4 NULL, { { NULL, 8 } }
10611
10612 static const struct dis386 float_reg[][8] = {
10613   /* d8 */
10614   {
10615     { "fadd",   { ST, STi } },
10616     { "fmul",   { ST, STi } },
10617     { "fcom",   { STi } },
10618     { "fcomp",  { STi } },
10619     { "fsub",   { ST, STi } },
10620     { "fsubr",  { ST, STi } },
10621     { "fdiv",   { ST, STi } },
10622     { "fdivr",  { ST, STi } },
10623   },
10624   /* d9 */
10625   {
10626     { "fld",    { STi } },
10627     { "fxch",   { STi } },
10628     { FGRPd9_2 },
10629     { "(bad)",  { XX } },
10630     { FGRPd9_4 },
10631     { FGRPd9_5 },
10632     { FGRPd9_6 },
10633     { FGRPd9_7 },
10634   },
10635   /* da */
10636   {
10637     { "fcmovb", { ST, STi } },
10638     { "fcmove", { ST, STi } },
10639     { "fcmovbe",{ ST, STi } },
10640     { "fcmovu", { ST, STi } },
10641     { "(bad)",  { XX } },
10642     { FGRPda_5 },
10643     { "(bad)",  { XX } },
10644     { "(bad)",  { XX } },
10645   },
10646   /* db */
10647   {
10648     { "fcmovnb",{ ST, STi } },
10649     { "fcmovne",{ ST, STi } },
10650     { "fcmovnbe",{ ST, STi } },
10651     { "fcmovnu",{ ST, STi } },
10652     { FGRPdb_4 },
10653     { "fucomi", { ST, STi } },
10654     { "fcomi",  { ST, STi } },
10655     { "(bad)",  { XX } },
10656   },
10657   /* dc */
10658   {
10659     { "fadd",   { STi, ST } },
10660     { "fmul",   { STi, ST } },
10661     { "(bad)",  { XX } },
10662     { "(bad)",  { XX } },
10663     { "fsub!M", { STi, ST } },
10664     { "fsubM",  { STi, ST } },
10665     { "fdiv!M", { STi, ST } },
10666     { "fdivM",  { STi, ST } },
10667   },
10668   /* dd */
10669   {
10670     { "ffree",  { STi } },
10671     { "(bad)",  { XX } },
10672     { "fst",    { STi } },
10673     { "fstp",   { STi } },
10674     { "fucom",  { STi } },
10675     { "fucomp", { STi } },
10676     { "(bad)",  { XX } },
10677     { "(bad)",  { XX } },
10678   },
10679   /* de */
10680   {
10681     { "faddp",  { STi, ST } },
10682     { "fmulp",  { STi, ST } },
10683     { "(bad)",  { XX } },
10684     { FGRPde_3 },
10685     { "fsub!Mp", { STi, ST } },
10686     { "fsubMp", { STi, ST } },
10687     { "fdiv!Mp", { STi, ST } },
10688     { "fdivMp", { STi, ST } },
10689   },
10690   /* df */
10691   {
10692     { "ffreep", { STi } },
10693     { "(bad)",  { XX } },
10694     { "(bad)",  { XX } },
10695     { "(bad)",  { XX } },
10696     { FGRPdf_4 },
10697     { "fucomip", { ST, STi } },
10698     { "fcomip", { ST, STi } },
10699     { "(bad)",  { XX } },
10700   },
10701 };
10702
10703 static char *fgrps[][8] = {
10704   /* d9_2  0 */
10705   {
10706     "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10707   },
10708
10709   /* d9_4  1 */
10710   {
10711     "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
10712   },
10713
10714   /* d9_5  2 */
10715   {
10716     "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
10717   },
10718
10719   /* d9_6  3 */
10720   {
10721     "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
10722   },
10723
10724   /* d9_7  4 */
10725   {
10726     "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
10727   },
10728
10729   /* da_5  5 */
10730   {
10731     "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10732   },
10733
10734   /* db_4  6 */
10735   {
10736     "feni(287 only)","fdisi(287 only)","fNclex","fNinit",
10737     "fNsetpm(287 only)","(bad)","(bad)","(bad)",
10738   },
10739
10740   /* de_3  7 */
10741   {
10742     "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10743   },
10744
10745   /* df_4  8 */
10746   {
10747     "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10748   },
10749 };
10750
10751 static void
10752 swap_operand (void)
10753 {
10754   mnemonicendp[0] = '.';
10755   mnemonicendp[1] = 's';
10756   mnemonicendp += 2;
10757 }
10758
10759 static void
10760 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED,
10761                int sizeflag ATTRIBUTE_UNUSED)
10762 {
10763   /* Skip mod/rm byte.  */
10764   MODRM_CHECK;
10765   codep++;
10766 }
10767
10768 static void
10769 dofloat (int sizeflag)
10770 {
10771   const struct dis386 *dp;
10772   unsigned char floatop;
10773
10774   floatop = codep[-1];
10775
10776   if (modrm.mod != 3)
10777     {
10778       int fp_indx = (floatop - 0xd8) * 8 + modrm.reg;
10779
10780       putop (float_mem[fp_indx], sizeflag);
10781       obufp = op_out[0];
10782       op_ad = 2;
10783       OP_E (float_mem_mode[fp_indx], sizeflag);
10784       return;
10785     }
10786   /* Skip mod/rm byte.  */
10787   MODRM_CHECK;
10788   codep++;
10789
10790   dp = &float_reg[floatop - 0xd8][modrm.reg];
10791   if (dp->name == NULL)
10792     {
10793       putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag);
10794
10795       /* Instruction fnstsw is only one with strange arg.  */
10796       if (floatop == 0xdf && codep[-1] == 0xe0)
10797         strcpy (op_out[0], names16[0]);
10798     }
10799   else
10800     {
10801       putop (dp->name, sizeflag);
10802
10803       obufp = op_out[0];
10804       op_ad = 2;
10805       if (dp->op[0].rtn)
10806         (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag);
10807
10808       obufp = op_out[1];
10809       op_ad = 1;
10810       if (dp->op[1].rtn)
10811         (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag);
10812     }
10813 }
10814
10815 static void
10816 OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
10817 {
10818   oappend ("%st" + intel_syntax);
10819 }
10820
10821 static void
10822 OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
10823 {
10824   sprintf (scratchbuf, "%%st(%d)", modrm.rm);
10825   oappend (scratchbuf + intel_syntax);
10826 }
10827
10828 /* Capital letters in template are macros.  */
10829 static int
10830 putop (const char *template, int sizeflag)
10831 {
10832   const char *p;
10833   int alt = 0;
10834   int cond = 1;
10835   unsigned int l = 0, len = 1;
10836   char last[4];
10837
10838 #define SAVE_LAST(c)                    \
10839   if (l < len && l < sizeof (last))     \
10840     last[l++] = c;                      \
10841   else                                  \
10842     abort ();
10843
10844   for (p = template; *p; p++)
10845     {
10846       switch (*p)
10847         {
10848         default:
10849           *obufp++ = *p;
10850           break;
10851         case '%':
10852           len++;
10853           break;
10854         case '!':
10855           cond = 0;
10856           break;
10857         case '{':
10858           alt = 0;
10859           if (intel_syntax)
10860             {
10861               while (*++p != '|')
10862                 if (*p == '}' || *p == '\0')
10863                   abort ();
10864             }
10865           /* Fall through.  */
10866         case 'I':
10867           alt = 1;
10868           continue;
10869         case '|':
10870           while (*++p != '}')
10871             {
10872               if (*p == '\0')
10873                 abort ();
10874             }
10875           break;
10876         case '}':
10877           break;
10878         case 'A':
10879           if (intel_syntax)
10880             break;
10881           if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
10882             *obufp++ = 'b';
10883           break;
10884         case 'B':
10885           if (intel_syntax)
10886             break;
10887           if (sizeflag & SUFFIX_ALWAYS)
10888             *obufp++ = 'b';
10889           break;
10890         case 'C':
10891           if (intel_syntax && !alt)
10892             break;
10893           if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
10894             {
10895               if (sizeflag & DFLAG)
10896                 *obufp++ = intel_syntax ? 'd' : 'l';
10897               else
10898                 *obufp++ = intel_syntax ? 'w' : 's';
10899               used_prefixes |= (prefixes & PREFIX_DATA);
10900             }
10901           break;
10902         case 'D':
10903           if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
10904             break;
10905           USED_REX (REX_W);
10906           if (modrm.mod == 3)
10907             {
10908               if (rex & REX_W)
10909                 *obufp++ = 'q';
10910               else if (sizeflag & DFLAG)
10911                 *obufp++ = intel_syntax ? 'd' : 'l';
10912               else
10913                 *obufp++ = 'w';
10914               used_prefixes |= (prefixes & PREFIX_DATA);
10915             }
10916           else
10917             *obufp++ = 'w';
10918           break;
10919         case 'E':               /* For jcxz/jecxz */
10920           if (address_mode == mode_64bit)
10921             {
10922               if (sizeflag & AFLAG)
10923                 *obufp++ = 'r';
10924               else
10925                 *obufp++ = 'e';
10926             }
10927           else
10928             if (sizeflag & AFLAG)
10929               *obufp++ = 'e';
10930           used_prefixes |= (prefixes & PREFIX_ADDR);
10931           break;
10932         case 'F':
10933           if (intel_syntax)
10934             break;
10935           if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
10936             {
10937               if (sizeflag & AFLAG)
10938                 *obufp++ = address_mode == mode_64bit ? 'q' : 'l';
10939               else
10940                 *obufp++ = address_mode == mode_64bit ? 'l' : 'w';
10941               used_prefixes |= (prefixes & PREFIX_ADDR);
10942             }
10943           break;
10944         case 'G':
10945           if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS)))
10946             break;
10947           if ((rex & REX_W) || (sizeflag & DFLAG))
10948             *obufp++ = 'l';
10949           else
10950             *obufp++ = 'w';
10951           if (!(rex & REX_W))
10952             used_prefixes |= (prefixes & PREFIX_DATA);
10953           break;
10954         case 'H':
10955           if (intel_syntax)
10956             break;
10957           if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS
10958               || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS)
10959             {
10960               used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS);
10961               *obufp++ = ',';
10962               *obufp++ = 'p';
10963               if (prefixes & PREFIX_DS)
10964                 *obufp++ = 't';
10965               else
10966                 *obufp++ = 'n';
10967             }
10968           break;
10969         case 'J':
10970           if (intel_syntax)
10971             break;
10972           *obufp++ = 'l';
10973           break;
10974         case 'K':
10975           USED_REX (REX_W);
10976           if (rex & REX_W)
10977             *obufp++ = 'q';
10978           else
10979             *obufp++ = 'd';
10980           break;
10981         case 'Z':
10982           if (intel_syntax)
10983             break;
10984           if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS))
10985             {
10986               *obufp++ = 'q';
10987               break;
10988             }
10989           /* Fall through.  */
10990           goto case_L;
10991         case 'L':
10992           if (l != 0 || len != 1)
10993             {
10994               SAVE_LAST (*p);
10995               break;
10996             }
10997 case_L:
10998           if (intel_syntax)
10999             break;
11000           if (sizeflag & SUFFIX_ALWAYS)
11001             *obufp++ = 'l';
11002           break;
11003         case 'M':
11004           if (intel_mnemonic != cond)
11005             *obufp++ = 'r';
11006           break;
11007         case 'N':
11008           if ((prefixes & PREFIX_FWAIT) == 0)
11009             *obufp++ = 'n';
11010           else
11011             used_prefixes |= PREFIX_FWAIT;
11012           break;
11013         case 'O':
11014           USED_REX (REX_W);
11015           if (rex & REX_W)
11016             *obufp++ = 'o';
11017           else if (intel_syntax && (sizeflag & DFLAG))
11018             *obufp++ = 'q';
11019           else
11020             *obufp++ = 'd';
11021           if (!(rex & REX_W))
11022             used_prefixes |= (prefixes & PREFIX_DATA);
11023           break;
11024         case 'T':
11025           if (intel_syntax)
11026             break;
11027           if (address_mode == mode_64bit && (sizeflag & DFLAG))
11028             {
11029               *obufp++ = 'q';
11030               break;
11031             }
11032           /* Fall through.  */
11033         case 'P':
11034           if (intel_syntax)
11035             break;
11036           if ((prefixes & PREFIX_DATA)
11037               || (rex & REX_W)
11038               || (sizeflag & SUFFIX_ALWAYS))
11039             {
11040               USED_REX (REX_W);
11041               if (rex & REX_W)
11042                 *obufp++ = 'q';
11043               else
11044                 {
11045                    if (sizeflag & DFLAG)
11046                       *obufp++ = 'l';
11047                    else
11048                      *obufp++ = 'w';
11049                 }
11050               used_prefixes |= (prefixes & PREFIX_DATA);
11051             }
11052           break;
11053         case 'U':
11054           if (intel_syntax)
11055             break;
11056           if (address_mode == mode_64bit && (sizeflag & DFLAG))
11057             {
11058               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
11059                 *obufp++ = 'q';
11060               break;
11061             }
11062           /* Fall through.  */
11063           goto case_Q;
11064         case 'Q':
11065           if (l == 0 && len == 1)
11066             {
11067 case_Q:
11068               if (intel_syntax && !alt)
11069                 break;
11070               USED_REX (REX_W);
11071               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
11072                 {
11073                   if (rex & REX_W)
11074                     *obufp++ = 'q';
11075                   else
11076                     {
11077                       if (sizeflag & DFLAG)
11078                         *obufp++ = intel_syntax ? 'd' : 'l';
11079                       else
11080                         *obufp++ = 'w';
11081                     }
11082                   used_prefixes |= (prefixes & PREFIX_DATA);
11083                 }
11084             }
11085           else
11086             {
11087               if (l != 1 || len != 2 || last[0] != 'L')
11088                 {
11089                   SAVE_LAST (*p);
11090                   break;
11091                 }
11092               if (intel_syntax
11093                   || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
11094                 break;
11095               if ((rex & REX_W))
11096                 {
11097                   USED_REX (REX_W);
11098                   *obufp++ = 'q';
11099                 }
11100               else
11101                 *obufp++ = 'l';
11102             }
11103           break;
11104         case 'R':
11105           USED_REX (REX_W);
11106           if (rex & REX_W)
11107             *obufp++ = 'q';
11108           else if (sizeflag & DFLAG)
11109             {
11110               if (intel_syntax)
11111                   *obufp++ = 'd';
11112               else
11113                   *obufp++ = 'l';
11114             }
11115           else
11116             *obufp++ = 'w';
11117           if (intel_syntax && !p[1]
11118               && ((rex & REX_W) || (sizeflag & DFLAG)))
11119             *obufp++ = 'e';
11120           if (!(rex & REX_W))
11121             used_prefixes |= (prefixes & PREFIX_DATA);
11122           break;
11123         case 'V':
11124           if (intel_syntax)
11125             break;
11126           if (address_mode == mode_64bit && (sizeflag & DFLAG))
11127             {
11128               if (sizeflag & SUFFIX_ALWAYS)
11129                 *obufp++ = 'q';
11130               break;
11131             }
11132           /* Fall through.  */
11133         case 'S':
11134           if (intel_syntax)
11135             break;
11136           if (sizeflag & SUFFIX_ALWAYS)
11137             {
11138               if (rex & REX_W)
11139                 *obufp++ = 'q';
11140               else
11141                 {
11142                   if (sizeflag & DFLAG)
11143                     *obufp++ = 'l';
11144                   else
11145                     *obufp++ = 'w';
11146                   used_prefixes |= (prefixes & PREFIX_DATA);
11147                 }
11148             }
11149           break;
11150         case 'X':
11151           if (l != 0 || len != 1)
11152             {
11153               SAVE_LAST (*p);
11154               break;
11155             }
11156           if (need_vex && vex.prefix)
11157             {
11158               if (vex.prefix == DATA_PREFIX_OPCODE)
11159                 *obufp++ = 'd';
11160               else
11161                 *obufp++ = 's';
11162             }
11163           else if (prefixes & PREFIX_DATA)
11164             *obufp++ = 'd';
11165           else
11166             *obufp++ = 's';
11167           used_prefixes |= (prefixes & PREFIX_DATA);
11168           break;
11169         case 'Y':
11170           if (l == 0 && len == 1)
11171             {
11172               if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
11173                 break;
11174               if (rex & REX_W)
11175                 {
11176                   USED_REX (REX_W);
11177                   *obufp++ = 'q';
11178                 }
11179               break;
11180             }
11181           else
11182             {
11183               if (l != 1 || len != 2 || last[0] != 'X')
11184                 {
11185                   SAVE_LAST (*p);
11186                   break;
11187                 }
11188               if (!need_vex)
11189                 abort ();
11190               if (intel_syntax
11191                   || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
11192                 break;
11193               switch (vex.length)
11194                 {
11195                 case 128:
11196                   *obufp++ = 'x';
11197                   break;
11198                 case 256:
11199                   *obufp++ = 'y';
11200                   break;
11201                 default:
11202                   abort ();
11203                 }
11204             }
11205           break;
11206         case 'W':
11207           if (l == 0 && len == 1)
11208             {
11209               /* operand size flag for cwtl, cbtw */
11210               USED_REX (REX_W);
11211               if (rex & REX_W)
11212                 {
11213                   if (intel_syntax)
11214                     *obufp++ = 'd';
11215                   else
11216                     *obufp++ = 'l';
11217                 }
11218               else if (sizeflag & DFLAG)
11219                 *obufp++ = 'w';
11220               else
11221                 *obufp++ = 'b';
11222               if (!(rex & REX_W))
11223                 used_prefixes |= (prefixes & PREFIX_DATA);
11224             }
11225           else
11226             {
11227               if (l != 1 || len != 2 || last[0] != 'X')
11228                 {
11229                   SAVE_LAST (*p);
11230                   break;
11231                 }
11232               if (!need_vex)
11233                 abort ();
11234               *obufp++ = vex.w ? 'd': 's';
11235             }
11236           break;
11237         }
11238       alt = 0;
11239     }
11240   *obufp = 0;
11241   mnemonicendp = obufp;
11242   return 0;
11243 }
11244
11245 static void
11246 oappend (const char *s)
11247 {
11248   obufp = stpcpy (obufp, s);
11249 }
11250
11251 static void
11252 append_seg (void)
11253 {
11254   if (prefixes & PREFIX_CS)
11255     {
11256       used_prefixes |= PREFIX_CS;
11257       oappend ("%cs:" + intel_syntax);
11258     }
11259   if (prefixes & PREFIX_DS)
11260     {
11261       used_prefixes |= PREFIX_DS;
11262       oappend ("%ds:" + intel_syntax);
11263     }
11264   if (prefixes & PREFIX_SS)
11265     {
11266       used_prefixes |= PREFIX_SS;
11267       oappend ("%ss:" + intel_syntax);
11268     }
11269   if (prefixes & PREFIX_ES)
11270     {
11271       used_prefixes |= PREFIX_ES;
11272       oappend ("%es:" + intel_syntax);
11273     }
11274   if (prefixes & PREFIX_FS)
11275     {
11276       used_prefixes |= PREFIX_FS;
11277       oappend ("%fs:" + intel_syntax);
11278     }
11279   if (prefixes & PREFIX_GS)
11280     {
11281       used_prefixes |= PREFIX_GS;
11282       oappend ("%gs:" + intel_syntax);
11283     }
11284 }
11285
11286 static void
11287 OP_indirE (int bytemode, int sizeflag)
11288 {
11289   if (!intel_syntax)
11290     oappend ("*");
11291   OP_E (bytemode, sizeflag);
11292 }
11293
11294 static void
11295 print_operand_value (char *buf, int hex, bfd_vma disp)
11296 {
11297   if (address_mode == mode_64bit)
11298     {
11299       if (hex)
11300         {
11301           char tmp[30];
11302           int i;
11303           buf[0] = '0';
11304           buf[1] = 'x';
11305           sprintf_vma (tmp, disp);
11306           for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++);
11307           strcpy (buf + 2, tmp + i);
11308         }
11309       else
11310         {
11311           bfd_signed_vma v = disp;
11312           char tmp[30];
11313           int i;
11314           if (v < 0)
11315             {
11316               *(buf++) = '-';
11317               v = -disp;
11318               /* Check for possible overflow on 0x8000000000000000.  */
11319               if (v < 0)
11320                 {
11321                   strcpy (buf, "9223372036854775808");
11322                   return;
11323                 }
11324             }
11325           if (!v)
11326             {
11327               strcpy (buf, "0");
11328               return;
11329             }
11330
11331           i = 0;
11332           tmp[29] = 0;
11333           while (v)
11334             {
11335               tmp[28 - i] = (v % 10) + '0';
11336               v /= 10;
11337               i++;
11338             }
11339           strcpy (buf, tmp + 29 - i);
11340         }
11341     }
11342   else
11343     {
11344       if (hex)
11345         sprintf (buf, "0x%x", (unsigned int) disp);
11346       else
11347         sprintf (buf, "%d", (int) disp);
11348     }
11349 }
11350
11351 /* Put DISP in BUF as signed hex number.  */
11352
11353 static void
11354 print_displacement (char *buf, bfd_vma disp)
11355 {
11356   bfd_signed_vma val = disp;
11357   char tmp[30];
11358   int i, j = 0;
11359
11360   if (val < 0)
11361     {
11362       buf[j++] = '-';
11363       val = -disp;
11364
11365       /* Check for possible overflow.  */
11366       if (val < 0)
11367         {
11368           switch (address_mode)
11369             {
11370             case mode_64bit:
11371               strcpy (buf + j, "0x8000000000000000");
11372               break;
11373             case mode_32bit:
11374               strcpy (buf + j, "0x80000000");
11375               break;
11376             case mode_16bit:
11377               strcpy (buf + j, "0x8000");
11378               break;
11379             }
11380           return;
11381         }
11382     }
11383
11384   buf[j++] = '0';
11385   buf[j++] = 'x';
11386
11387   sprintf_vma (tmp, (bfd_vma) val);
11388   for (i = 0; tmp[i] == '0'; i++)
11389     continue;
11390   if (tmp[i] == '\0')
11391     i--;
11392   strcpy (buf + j, tmp + i);
11393 }
11394
11395 static void
11396 intel_operand_size (int bytemode, int sizeflag)
11397 {
11398   switch (bytemode)
11399     {
11400     case b_mode:
11401     case b_swap_mode:
11402     case dqb_mode:
11403       oappend ("BYTE PTR ");
11404       break;
11405     case w_mode:
11406     case dqw_mode:
11407       oappend ("WORD PTR ");
11408       break;
11409     case stack_v_mode:
11410       if (address_mode == mode_64bit && (sizeflag & DFLAG))
11411         {
11412           oappend ("QWORD PTR ");
11413           used_prefixes |= (prefixes & PREFIX_DATA);
11414           break;
11415         }
11416       /* FALLTHRU */
11417     case v_mode:
11418     case v_swap_mode:
11419     case dq_mode:
11420       USED_REX (REX_W);
11421       if (rex & REX_W)
11422         oappend ("QWORD PTR ");
11423       else if ((sizeflag & DFLAG) || bytemode == dq_mode)
11424         oappend ("DWORD PTR ");
11425       else
11426         oappend ("WORD PTR ");
11427       used_prefixes |= (prefixes & PREFIX_DATA);
11428       break;
11429     case z_mode:
11430       if ((rex & REX_W) || (sizeflag & DFLAG))
11431         *obufp++ = 'D';
11432       oappend ("WORD PTR ");
11433       if (!(rex & REX_W))
11434         used_prefixes |= (prefixes & PREFIX_DATA);
11435       break;
11436     case a_mode:
11437       if (sizeflag & DFLAG)
11438         oappend ("QWORD PTR ");
11439       else
11440         oappend ("DWORD PTR ");
11441       used_prefixes |= (prefixes & PREFIX_DATA);
11442       break;
11443     case d_mode:
11444     case d_swap_mode:
11445     case dqd_mode:
11446       oappend ("DWORD PTR ");
11447       break;
11448     case q_mode:
11449     case q_swap_mode:
11450       oappend ("QWORD PTR ");
11451       break;
11452     case m_mode:
11453       if (address_mode == mode_64bit)
11454         oappend ("QWORD PTR ");
11455       else
11456         oappend ("DWORD PTR ");
11457       break;
11458     case f_mode:
11459       if (sizeflag & DFLAG)
11460         oappend ("FWORD PTR ");
11461       else
11462         oappend ("DWORD PTR ");
11463       used_prefixes |= (prefixes & PREFIX_DATA);
11464       break;
11465     case t_mode:
11466       oappend ("TBYTE PTR ");
11467       break;
11468     case x_mode:
11469     case x_swap_mode:
11470       if (need_vex)
11471         {
11472           switch (vex.length)
11473             {
11474             case 128:
11475               oappend ("XMMWORD PTR ");
11476               break;
11477             case 256:
11478               oappend ("YMMWORD PTR ");
11479               break;
11480             default:
11481               abort ();
11482             }
11483         }
11484       else
11485         oappend ("XMMWORD PTR ");
11486       break;
11487     case xmm_mode:
11488       oappend ("XMMWORD PTR ");
11489       break;
11490     case xmmq_mode:
11491       if (!need_vex)
11492         abort ();
11493
11494       switch (vex.length)
11495         {
11496         case 128:
11497           oappend ("QWORD PTR ");
11498           break;
11499         case 256:
11500           oappend ("XMMWORD PTR ");
11501           break;
11502         default:
11503           abort ();
11504         }
11505       break;
11506     case ymmq_mode:
11507       if (!need_vex)
11508         abort ();
11509
11510       switch (vex.length)
11511         {
11512         case 128:
11513           oappend ("QWORD PTR ");
11514           break;
11515         case 256:
11516           oappend ("YMMWORD PTR ");
11517           break;
11518         default:
11519           abort ();
11520         }
11521       break;
11522     case o_mode:
11523       oappend ("OWORD PTR ");
11524       break;
11525     case vex_w_dq_mode:
11526       if (!need_vex)
11527         abort ();
11528
11529       if (vex.w)
11530         oappend ("QWORD PTR ");
11531       else
11532         oappend ("DWORD PTR ");
11533       break;
11534     default:
11535       break;
11536     }
11537 }
11538
11539 static void
11540 OP_E_register (int bytemode, int sizeflag)
11541 {
11542   int reg = modrm.rm;
11543   const char **names;
11544
11545   USED_REX (REX_B);
11546   if ((rex & REX_B))
11547     reg += 8;
11548
11549   if ((sizeflag & SUFFIX_ALWAYS)
11550       && (bytemode == b_swap_mode || bytemode == v_swap_mode))
11551     swap_operand ();
11552
11553   switch (bytemode)
11554     {
11555     case b_mode:
11556     case b_swap_mode:
11557       USED_REX (0);
11558       if (rex)
11559         names = names8rex;
11560       else
11561         names = names8;
11562       break;
11563     case w_mode:
11564       names = names16;
11565       break;
11566     case d_mode:
11567       names = names32;
11568       break;
11569     case q_mode:
11570       names = names64;
11571       break;
11572     case m_mode:
11573       names = address_mode == mode_64bit ? names64 : names32;
11574       break;
11575     case stack_v_mode:
11576       if (address_mode == mode_64bit && (sizeflag & DFLAG))
11577         {
11578           names = names64;
11579           used_prefixes |= (prefixes & PREFIX_DATA);
11580           break;
11581         }
11582       bytemode = v_mode;
11583       /* FALLTHRU */
11584     case v_mode:
11585     case v_swap_mode:
11586     case dq_mode:
11587     case dqb_mode:
11588     case dqd_mode:
11589     case dqw_mode:
11590       USED_REX (REX_W);
11591       if (rex & REX_W)
11592         names = names64;
11593       else if ((sizeflag & DFLAG)
11594                || (bytemode != v_mode
11595                    && bytemode != v_swap_mode))
11596         names = names32;
11597       else
11598         names = names16;
11599       used_prefixes |= (prefixes & PREFIX_DATA);
11600       break;
11601     case 0:
11602       return;
11603     default:
11604       oappend (INTERNAL_DISASSEMBLER_ERROR);
11605       return;
11606     }
11607   oappend (names[reg]);
11608 }
11609
11610 static void
11611 OP_E_memory (int bytemode, int sizeflag, int has_drex)
11612 {
11613   bfd_vma disp = 0;
11614   int add = (rex & REX_B) ? 8 : 0;
11615   int riprel = 0;
11616
11617   USED_REX (REX_B);
11618   if (intel_syntax)
11619     intel_operand_size (bytemode, sizeflag);
11620   append_seg ();
11621
11622   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
11623     {
11624       /* 32/64 bit address mode */
11625       int havedisp;
11626       int havesib;
11627       int havebase;
11628       int haveindex;
11629       int needindex;
11630       int base, rbase;
11631       int index = 0;
11632       int scale = 0;
11633
11634       havesib = 0;
11635       havebase = 1;
11636       haveindex = 0;
11637       base = modrm.rm;
11638
11639       if (base == 4)
11640         {
11641           havesib = 1;
11642           FETCH_DATA (the_info, codep + 1);
11643           index = (*codep >> 3) & 7;
11644           scale = (*codep >> 6) & 3;
11645           base = *codep & 7;
11646           USED_REX (REX_X);
11647           if (rex & REX_X)
11648             index += 8;
11649           haveindex = index != 4;
11650           codep++;
11651         }
11652       rbase = base + add;
11653
11654       /* If we have a DREX byte, skip it now
11655          (it has already been handled) */
11656       if (has_drex)
11657         {
11658           FETCH_DATA (the_info, codep + 1);
11659           codep++;
11660         }
11661
11662       switch (modrm.mod)
11663         {
11664         case 0:
11665           if (base == 5)
11666             {
11667               havebase = 0;
11668               if (address_mode == mode_64bit && !havesib)
11669                 riprel = 1;
11670               disp = get32s ();
11671             }
11672           break;
11673         case 1:
11674           FETCH_DATA (the_info, codep + 1);
11675           disp = *codep++;
11676           if ((disp & 0x80) != 0)
11677             disp -= 0x100;
11678           break;
11679         case 2:
11680           disp = get32s ();
11681           break;
11682         }
11683
11684       /* In 32bit mode, we need index register to tell [offset] from
11685          [eiz*1 + offset].  */
11686       needindex = (havesib
11687                    && !havebase
11688                    && !haveindex
11689                    && address_mode == mode_32bit);
11690       havedisp = (havebase
11691                   || needindex
11692                   || (havesib && (haveindex || scale != 0)));
11693
11694       if (!intel_syntax)
11695         if (modrm.mod != 0 || base == 5)
11696           {
11697             if (havedisp || riprel)
11698               print_displacement (scratchbuf, disp);
11699             else
11700               print_operand_value (scratchbuf, 1, disp);
11701             oappend (scratchbuf);
11702             if (riprel)
11703               {
11704                 set_op (disp, 1);
11705                 oappend (sizeflag & AFLAG ? "(%rip)" : "(%eip)");
11706               }
11707           }
11708
11709       if (havebase || haveindex || riprel)
11710         used_prefixes |= PREFIX_ADDR;
11711
11712       if (havedisp || (intel_syntax && riprel))
11713         {
11714           *obufp++ = open_char;
11715           if (intel_syntax && riprel)
11716             {
11717               set_op (disp, 1);
11718               oappend (sizeflag & AFLAG ? "rip" : "eip");
11719             }
11720           *obufp = '\0';
11721           if (havebase)
11722             oappend (address_mode == mode_64bit && (sizeflag & AFLAG)
11723                      ? names64[rbase] : names32[rbase]);
11724           if (havesib)
11725             {
11726               /* ESP/RSP won't allow index.  If base isn't ESP/RSP,
11727                  print index to tell base + index from base.  */
11728               if (scale != 0
11729                   || needindex
11730                   || haveindex
11731                   || (havebase && base != ESP_REG_NUM))
11732                 {
11733                   if (!intel_syntax || havebase)
11734                     {
11735                       *obufp++ = separator_char;
11736                       *obufp = '\0';
11737                     }
11738                   if (haveindex)
11739                     oappend (address_mode == mode_64bit
11740                              && (sizeflag & AFLAG)
11741                              ? names64[index] : names32[index]);
11742                   else
11743                     oappend (address_mode == mode_64bit
11744                              && (sizeflag & AFLAG)
11745                              ? index64 : index32);
11746
11747                   *obufp++ = scale_char;
11748                   *obufp = '\0';
11749                   sprintf (scratchbuf, "%d", 1 << scale);
11750                   oappend (scratchbuf);
11751                 }
11752             }
11753           if (intel_syntax
11754               && (disp || modrm.mod != 0 || base == 5))
11755             {
11756               if (!havedisp || (bfd_signed_vma) disp >= 0)
11757                 {
11758                   *obufp++ = '+';
11759                   *obufp = '\0';
11760                 }
11761               else if (modrm.mod != 1)
11762                 {
11763                   *obufp++ = '-';
11764                   *obufp = '\0';
11765                   disp = - (bfd_signed_vma) disp;
11766                 }
11767
11768               if (havedisp)
11769                 print_displacement (scratchbuf, disp);
11770               else
11771                 print_operand_value (scratchbuf, 1, disp);
11772               oappend (scratchbuf);
11773             }
11774
11775           *obufp++ = close_char;
11776           *obufp = '\0';
11777         }
11778       else if (intel_syntax)
11779         {
11780           if (modrm.mod != 0 || base == 5)
11781             {
11782               if (prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
11783                               | PREFIX_ES | PREFIX_FS | PREFIX_GS))
11784                 ;
11785               else
11786                 {
11787                   oappend (names_seg[ds_reg - es_reg]);
11788                   oappend (":");
11789                 }
11790               print_operand_value (scratchbuf, 1, disp);
11791               oappend (scratchbuf);
11792             }
11793         }
11794     }
11795   else
11796     { /* 16 bit address mode */
11797       switch (modrm.mod)
11798         {
11799         case 0:
11800           if (modrm.rm == 6)
11801             {
11802               disp = get16 ();
11803               if ((disp & 0x8000) != 0)
11804                 disp -= 0x10000;
11805             }
11806           break;
11807         case 1:
11808           FETCH_DATA (the_info, codep + 1);
11809           disp = *codep++;
11810           if ((disp & 0x80) != 0)
11811             disp -= 0x100;
11812           break;
11813         case 2:
11814           disp = get16 ();
11815           if ((disp & 0x8000) != 0)
11816             disp -= 0x10000;
11817           break;
11818         }
11819
11820       if (!intel_syntax)
11821         if (modrm.mod != 0 || modrm.rm == 6)
11822           {
11823             print_displacement (scratchbuf, disp);
11824             oappend (scratchbuf);
11825           }
11826
11827       if (modrm.mod != 0 || modrm.rm != 6)
11828         {
11829           *obufp++ = open_char;
11830           *obufp = '\0';
11831           oappend (index16[modrm.rm]);
11832           if (intel_syntax
11833               && (disp || modrm.mod != 0 || modrm.rm == 6))
11834             {
11835               if ((bfd_signed_vma) disp >= 0)
11836                 {
11837                   *obufp++ = '+';
11838                   *obufp = '\0';
11839                 }
11840               else if (modrm.mod != 1)
11841                 {
11842                   *obufp++ = '-';
11843                   *obufp = '\0';
11844                   disp = - (bfd_signed_vma) disp;
11845                 }
11846
11847               print_displacement (scratchbuf, disp);
11848               oappend (scratchbuf);
11849             }
11850
11851           *obufp++ = close_char;
11852           *obufp = '\0';
11853         }
11854       else if (intel_syntax)
11855         {
11856           if (prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
11857                           | PREFIX_ES | PREFIX_FS | PREFIX_GS))
11858             ;
11859           else
11860             {
11861               oappend (names_seg[ds_reg - es_reg]);
11862               oappend (":");
11863             }
11864           print_operand_value (scratchbuf, 1, disp & 0xffff);
11865           oappend (scratchbuf);
11866         }
11867     }
11868 }
11869
11870 static void
11871 OP_E_extended (int bytemode, int sizeflag, int has_drex)
11872 {
11873   /* Skip mod/rm byte.  */
11874   MODRM_CHECK;
11875   codep++;
11876
11877   if (modrm.mod == 3)
11878     OP_E_register (bytemode, sizeflag);
11879   else
11880     OP_E_memory (bytemode, sizeflag, has_drex);
11881 }
11882
11883 static void
11884 OP_E (int bytemode, int sizeflag)
11885 {
11886   OP_E_extended (bytemode, sizeflag, 0);
11887 }
11888
11889
11890 static void
11891 OP_G (int bytemode, int sizeflag)
11892 {
11893   int add = 0;
11894   USED_REX (REX_R);
11895   if (rex & REX_R)
11896     add += 8;
11897   switch (bytemode)
11898     {
11899     case b_mode:
11900       USED_REX (0);
11901       if (rex)
11902         oappend (names8rex[modrm.reg + add]);
11903       else
11904         oappend (names8[modrm.reg + add]);
11905       break;
11906     case w_mode:
11907       oappend (names16[modrm.reg + add]);
11908       break;
11909     case d_mode:
11910       oappend (names32[modrm.reg + add]);
11911       break;
11912     case q_mode:
11913       oappend (names64[modrm.reg + add]);
11914       break;
11915     case v_mode:
11916     case dq_mode:
11917     case dqb_mode:
11918     case dqd_mode:
11919     case dqw_mode:
11920       USED_REX (REX_W);
11921       if (rex & REX_W)
11922         oappend (names64[modrm.reg + add]);
11923       else if ((sizeflag & DFLAG) || bytemode != v_mode)
11924         oappend (names32[modrm.reg + add]);
11925       else
11926         oappend (names16[modrm.reg + add]);
11927       used_prefixes |= (prefixes & PREFIX_DATA);
11928       break;
11929     case m_mode:
11930       if (address_mode == mode_64bit)
11931         oappend (names64[modrm.reg + add]);
11932       else
11933         oappend (names32[modrm.reg + add]);
11934       break;
11935     default:
11936       oappend (INTERNAL_DISASSEMBLER_ERROR);
11937       break;
11938     }
11939 }
11940
11941 static bfd_vma
11942 get64 (void)
11943 {
11944   bfd_vma x;
11945 #ifdef BFD64
11946   unsigned int a;
11947   unsigned int b;
11948
11949   FETCH_DATA (the_info, codep + 8);
11950   a = *codep++ & 0xff;
11951   a |= (*codep++ & 0xff) << 8;
11952   a |= (*codep++ & 0xff) << 16;
11953   a |= (*codep++ & 0xff) << 24;
11954   b = *codep++ & 0xff;
11955   b |= (*codep++ & 0xff) << 8;
11956   b |= (*codep++ & 0xff) << 16;
11957   b |= (*codep++ & 0xff) << 24;
11958   x = a + ((bfd_vma) b << 32);
11959 #else
11960   abort ();
11961   x = 0;
11962 #endif
11963   return x;
11964 }
11965
11966 static bfd_signed_vma
11967 get32 (void)
11968 {
11969   bfd_signed_vma x = 0;
11970
11971   FETCH_DATA (the_info, codep + 4);
11972   x = *codep++ & (bfd_signed_vma) 0xff;
11973   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
11974   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
11975   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
11976   return x;
11977 }
11978
11979 static bfd_signed_vma
11980 get32s (void)
11981 {
11982   bfd_signed_vma x = 0;
11983
11984   FETCH_DATA (the_info, codep + 4);
11985   x = *codep++ & (bfd_signed_vma) 0xff;
11986   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
11987   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
11988   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
11989
11990   x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31);
11991
11992   return x;
11993 }
11994
11995 static int
11996 get16 (void)
11997 {
11998   int x = 0;
11999
12000   FETCH_DATA (the_info, codep + 2);
12001   x = *codep++ & 0xff;
12002   x |= (*codep++ & 0xff) << 8;
12003   return x;
12004 }
12005
12006 static void
12007 set_op (bfd_vma op, int riprel)
12008 {
12009   op_index[op_ad] = op_ad;
12010   if (address_mode == mode_64bit)
12011     {
12012       op_address[op_ad] = op;
12013       op_riprel[op_ad] = riprel;
12014     }
12015   else
12016     {
12017       /* Mask to get a 32-bit address.  */
12018       op_address[op_ad] = op & 0xffffffff;
12019       op_riprel[op_ad] = riprel & 0xffffffff;
12020     }
12021 }
12022
12023 static void
12024 OP_REG (int code, int sizeflag)
12025 {
12026   const char *s;
12027   int add;
12028   USED_REX (REX_B);
12029   if (rex & REX_B)
12030     add = 8;
12031   else
12032     add = 0;
12033
12034   switch (code)
12035     {
12036     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
12037     case sp_reg: case bp_reg: case si_reg: case di_reg:
12038       s = names16[code - ax_reg + add];
12039       break;
12040     case es_reg: case ss_reg: case cs_reg:
12041     case ds_reg: case fs_reg: case gs_reg:
12042       s = names_seg[code - es_reg + add];
12043       break;
12044     case al_reg: case ah_reg: case cl_reg: case ch_reg:
12045     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
12046       USED_REX (0);
12047       if (rex)
12048         s = names8rex[code - al_reg + add];
12049       else
12050         s = names8[code - al_reg];
12051       break;
12052     case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
12053     case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
12054       if (address_mode == mode_64bit && (sizeflag & DFLAG))
12055         {
12056           s = names64[code - rAX_reg + add];
12057           break;
12058         }
12059       code += eAX_reg - rAX_reg;
12060       /* Fall through.  */
12061     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
12062     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
12063       USED_REX (REX_W);
12064       if (rex & REX_W)
12065         s = names64[code - eAX_reg + add];
12066       else if (sizeflag & DFLAG)
12067         s = names32[code - eAX_reg + add];
12068       else
12069         s = names16[code - eAX_reg + add];
12070       used_prefixes |= (prefixes & PREFIX_DATA);
12071       break;
12072     default:
12073       s = INTERNAL_DISASSEMBLER_ERROR;
12074       break;
12075     }
12076   oappend (s);
12077 }
12078
12079 static void
12080 OP_IMREG (int code, int sizeflag)
12081 {
12082   const char *s;
12083
12084   switch (code)
12085     {
12086     case indir_dx_reg:
12087       if (intel_syntax)
12088         s = "dx";
12089       else
12090         s = "(%dx)";
12091       break;
12092     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
12093     case sp_reg: case bp_reg: case si_reg: case di_reg:
12094       s = names16[code - ax_reg];
12095       break;
12096     case es_reg: case ss_reg: case cs_reg:
12097     case ds_reg: case fs_reg: case gs_reg:
12098       s = names_seg[code - es_reg];
12099       break;
12100     case al_reg: case ah_reg: case cl_reg: case ch_reg:
12101     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
12102       USED_REX (0);
12103       if (rex)
12104         s = names8rex[code - al_reg];
12105       else
12106         s = names8[code - al_reg];
12107       break;
12108     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
12109     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
12110       USED_REX (REX_W);
12111       if (rex & REX_W)
12112         s = names64[code - eAX_reg];
12113       else if (sizeflag & DFLAG)
12114         s = names32[code - eAX_reg];
12115       else
12116         s = names16[code - eAX_reg];
12117       used_prefixes |= (prefixes & PREFIX_DATA);
12118       break;
12119     case z_mode_ax_reg:
12120       if ((rex & REX_W) || (sizeflag & DFLAG))
12121         s = *names32;
12122       else
12123         s = *names16;
12124       if (!(rex & REX_W))
12125         used_prefixes |= (prefixes & PREFIX_DATA);
12126       break;
12127     default:
12128       s = INTERNAL_DISASSEMBLER_ERROR;
12129       break;
12130     }
12131   oappend (s);
12132 }
12133
12134 static void
12135 OP_I (int bytemode, int sizeflag)
12136 {
12137   bfd_signed_vma op;
12138   bfd_signed_vma mask = -1;
12139
12140   switch (bytemode)
12141     {
12142     case b_mode:
12143       FETCH_DATA (the_info, codep + 1);
12144       op = *codep++;
12145       mask = 0xff;
12146       break;
12147     case q_mode:
12148       if (address_mode == mode_64bit)
12149         {
12150           op = get32s ();
12151           break;
12152         }
12153       /* Fall through.  */
12154     case v_mode:
12155       USED_REX (REX_W);
12156       if (rex & REX_W)
12157         op = get32s ();
12158       else if (sizeflag & DFLAG)
12159         {
12160           op = get32 ();
12161           mask = 0xffffffff;
12162         }
12163       else
12164         {
12165           op = get16 ();
12166           mask = 0xfffff;
12167         }
12168       used_prefixes |= (prefixes & PREFIX_DATA);
12169       break;
12170     case w_mode:
12171       mask = 0xfffff;
12172       op = get16 ();
12173       break;
12174     case const_1_mode:
12175       if (intel_syntax)
12176         oappend ("1");
12177       return;
12178     default:
12179       oappend (INTERNAL_DISASSEMBLER_ERROR);
12180       return;
12181     }
12182
12183   op &= mask;
12184   scratchbuf[0] = '$';
12185   print_operand_value (scratchbuf + 1, 1, op);
12186   oappend (scratchbuf + intel_syntax);
12187   scratchbuf[0] = '\0';
12188 }
12189
12190 static void
12191 OP_I64 (int bytemode, int sizeflag)
12192 {
12193   bfd_signed_vma op;
12194   bfd_signed_vma mask = -1;
12195
12196   if (address_mode != mode_64bit)
12197     {
12198       OP_I (bytemode, sizeflag);
12199       return;
12200     }
12201
12202   switch (bytemode)
12203     {
12204     case b_mode:
12205       FETCH_DATA (the_info, codep + 1);
12206       op = *codep++;
12207       mask = 0xff;
12208       break;
12209     case v_mode:
12210       USED_REX (REX_W);
12211       if (rex & REX_W)
12212         op = get64 ();
12213       else if (sizeflag & DFLAG)
12214         {
12215           op = get32 ();
12216           mask = 0xffffffff;
12217         }
12218       else
12219         {
12220           op = get16 ();
12221           mask = 0xfffff;
12222         }
12223       used_prefixes |= (prefixes & PREFIX_DATA);
12224       break;
12225     case w_mode:
12226       mask = 0xfffff;
12227       op = get16 ();
12228       break;
12229     default:
12230       oappend (INTERNAL_DISASSEMBLER_ERROR);
12231       return;
12232     }
12233
12234   op &= mask;
12235   scratchbuf[0] = '$';
12236   print_operand_value (scratchbuf + 1, 1, op);
12237   oappend (scratchbuf + intel_syntax);
12238   scratchbuf[0] = '\0';
12239 }
12240
12241 static void
12242 OP_sI (int bytemode, int sizeflag)
12243 {
12244   bfd_signed_vma op;
12245   bfd_signed_vma mask = -1;
12246
12247   switch (bytemode)
12248     {
12249     case b_mode:
12250       FETCH_DATA (the_info, codep + 1);
12251       op = *codep++;
12252       if ((op & 0x80) != 0)
12253         op -= 0x100;
12254       mask = 0xffffffff;
12255       break;
12256     case v_mode:
12257       USED_REX (REX_W);
12258       if (rex & REX_W)
12259         op = get32s ();
12260       else if (sizeflag & DFLAG)
12261         {
12262           op = get32s ();
12263           mask = 0xffffffff;
12264         }
12265       else
12266         {
12267           mask = 0xffffffff;
12268           op = get16 ();
12269           if ((op & 0x8000) != 0)
12270             op -= 0x10000;
12271         }
12272       used_prefixes |= (prefixes & PREFIX_DATA);
12273       break;
12274     case w_mode:
12275       op = get16 ();
12276       mask = 0xffffffff;
12277       if ((op & 0x8000) != 0)
12278         op -= 0x10000;
12279       break;
12280     default:
12281       oappend (INTERNAL_DISASSEMBLER_ERROR);
12282       return;
12283     }
12284
12285   scratchbuf[0] = '$';
12286   print_operand_value (scratchbuf + 1, 1, op);
12287   oappend (scratchbuf + intel_syntax);
12288 }
12289
12290 static void
12291 OP_J (int bytemode, int sizeflag)
12292 {
12293   bfd_vma disp;
12294   bfd_vma mask = -1;
12295   bfd_vma segment = 0;
12296
12297   switch (bytemode)
12298     {
12299     case b_mode:
12300       FETCH_DATA (the_info, codep + 1);
12301       disp = *codep++;
12302       if ((disp & 0x80) != 0)
12303         disp -= 0x100;
12304       break;
12305     case v_mode:
12306       if ((sizeflag & DFLAG) || (rex & REX_W))
12307         disp = get32s ();
12308       else
12309         {
12310           disp = get16 ();
12311           if ((disp & 0x8000) != 0)
12312             disp -= 0x10000;
12313           /* In 16bit mode, address is wrapped around at 64k within
12314              the same segment.  Otherwise, a data16 prefix on a jump
12315              instruction means that the pc is masked to 16 bits after
12316              the displacement is added!  */
12317           mask = 0xffff;
12318           if ((prefixes & PREFIX_DATA) == 0)
12319             segment = ((start_pc + codep - start_codep)
12320                        & ~((bfd_vma) 0xffff));
12321         }
12322       used_prefixes |= (prefixes & PREFIX_DATA);
12323       break;
12324     default:
12325       oappend (INTERNAL_DISASSEMBLER_ERROR);
12326       return;
12327     }
12328   disp = ((start_pc + codep - start_codep + disp) & mask) | segment;
12329   set_op (disp, 0);
12330   print_operand_value (scratchbuf, 1, disp);
12331   oappend (scratchbuf);
12332 }
12333
12334 static void
12335 OP_SEG (int bytemode, int sizeflag)
12336 {
12337   if (bytemode == w_mode)
12338     oappend (names_seg[modrm.reg]);
12339   else
12340     OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag);
12341 }
12342
12343 static void
12344 OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag)
12345 {
12346   int seg, offset;
12347
12348   if (sizeflag & DFLAG)
12349     {
12350       offset = get32 ();
12351       seg = get16 ();
12352     }
12353   else
12354     {
12355       offset = get16 ();
12356       seg = get16 ();
12357     }
12358   used_prefixes |= (prefixes & PREFIX_DATA);
12359   if (intel_syntax)
12360     sprintf (scratchbuf, "0x%x:0x%x", seg, offset);
12361   else
12362     sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset);
12363   oappend (scratchbuf);
12364 }
12365
12366 static void
12367 OP_OFF (int bytemode, int sizeflag)
12368 {
12369   bfd_vma off;
12370
12371   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
12372     intel_operand_size (bytemode, sizeflag);
12373   append_seg ();
12374
12375   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
12376     off = get32 ();
12377   else
12378     off = get16 ();
12379
12380   if (intel_syntax)
12381     {
12382       if (!(prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
12383                         | PREFIX_ES | PREFIX_FS | PREFIX_GS)))
12384         {
12385           oappend (names_seg[ds_reg - es_reg]);
12386           oappend (":");
12387         }
12388     }
12389   print_operand_value (scratchbuf, 1, off);
12390   oappend (scratchbuf);
12391 }
12392
12393 static void
12394 OP_OFF64 (int bytemode, int sizeflag)
12395 {
12396   bfd_vma off;
12397
12398   if (address_mode != mode_64bit
12399       || (prefixes & PREFIX_ADDR))
12400     {
12401       OP_OFF (bytemode, sizeflag);
12402       return;
12403     }
12404
12405   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
12406     intel_operand_size (bytemode, sizeflag);
12407   append_seg ();
12408
12409   off = get64 ();
12410
12411   if (intel_syntax)
12412     {
12413       if (!(prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
12414                         | PREFIX_ES | PREFIX_FS | PREFIX_GS)))
12415         {
12416           oappend (names_seg[ds_reg - es_reg]);
12417           oappend (":");
12418         }
12419     }
12420   print_operand_value (scratchbuf, 1, off);
12421   oappend (scratchbuf);
12422 }
12423
12424 static void
12425 ptr_reg (int code, int sizeflag)
12426 {
12427   const char *s;
12428
12429   *obufp++ = open_char;
12430   used_prefixes |= (prefixes & PREFIX_ADDR);
12431   if (address_mode == mode_64bit)
12432     {
12433       if (!(sizeflag & AFLAG))
12434         s = names32[code - eAX_reg];
12435       else
12436         s = names64[code - eAX_reg];
12437     }
12438   else if (sizeflag & AFLAG)
12439     s = names32[code - eAX_reg];
12440   else
12441     s = names16[code - eAX_reg];
12442   oappend (s);
12443   *obufp++ = close_char;
12444   *obufp = 0;
12445 }
12446
12447 static void
12448 OP_ESreg (int code, int sizeflag)
12449 {
12450   if (intel_syntax)
12451     {
12452       switch (codep[-1])
12453         {
12454         case 0x6d:      /* insw/insl */
12455           intel_operand_size (z_mode, sizeflag);
12456           break;
12457         case 0xa5:      /* movsw/movsl/movsq */
12458         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
12459         case 0xab:      /* stosw/stosl */
12460         case 0xaf:      /* scasw/scasl */
12461           intel_operand_size (v_mode, sizeflag);
12462           break;
12463         default:
12464           intel_operand_size (b_mode, sizeflag);
12465         }
12466     }
12467   oappend ("%es:" + intel_syntax);
12468   ptr_reg (code, sizeflag);
12469 }
12470
12471 static void
12472 OP_DSreg (int code, int sizeflag)
12473 {
12474   if (intel_syntax)
12475     {
12476       switch (codep[-1])
12477         {
12478         case 0x6f:      /* outsw/outsl */
12479           intel_operand_size (z_mode, sizeflag);
12480           break;
12481         case 0xa5:      /* movsw/movsl/movsq */
12482         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
12483         case 0xad:      /* lodsw/lodsl/lodsq */
12484           intel_operand_size (v_mode, sizeflag);
12485           break;
12486         default:
12487           intel_operand_size (b_mode, sizeflag);
12488         }
12489     }
12490   if ((prefixes
12491        & (PREFIX_CS
12492           | PREFIX_DS
12493           | PREFIX_SS
12494           | PREFIX_ES
12495           | PREFIX_FS
12496           | PREFIX_GS)) == 0)
12497     prefixes |= PREFIX_DS;
12498   append_seg ();
12499   ptr_reg (code, sizeflag);
12500 }
12501
12502 static void
12503 OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12504 {
12505   int add;
12506   if (rex & REX_R)
12507     {
12508       USED_REX (REX_R);
12509       add = 8;
12510     }
12511   else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK))
12512     {
12513       lock_prefix = NULL;
12514       used_prefixes |= PREFIX_LOCK;
12515       add = 8;
12516     }
12517   else
12518     add = 0;
12519   sprintf (scratchbuf, "%%cr%d", modrm.reg + add);
12520   oappend (scratchbuf + intel_syntax);
12521 }
12522
12523 static void
12524 OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12525 {
12526   int add;
12527   USED_REX (REX_R);
12528   if (rex & REX_R)
12529     add = 8;
12530   else
12531     add = 0;
12532   if (intel_syntax)
12533     sprintf (scratchbuf, "db%d", modrm.reg + add);
12534   else
12535     sprintf (scratchbuf, "%%db%d", modrm.reg + add);
12536   oappend (scratchbuf);
12537 }
12538
12539 static void
12540 OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12541 {
12542   sprintf (scratchbuf, "%%tr%d", modrm.reg);
12543   oappend (scratchbuf + intel_syntax);
12544 }
12545
12546 static void
12547 OP_R (int bytemode, int sizeflag)
12548 {
12549   if (modrm.mod == 3)
12550     OP_E (bytemode, sizeflag);
12551   else
12552     BadOp ();
12553 }
12554
12555 static void
12556 OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12557 {
12558   used_prefixes |= (prefixes & PREFIX_DATA);
12559   if (prefixes & PREFIX_DATA)
12560     {
12561       int add;
12562       USED_REX (REX_R);
12563       if (rex & REX_R)
12564         add = 8;
12565       else
12566         add = 0;
12567       sprintf (scratchbuf, "%%xmm%d", modrm.reg + add);
12568     }
12569   else
12570     sprintf (scratchbuf, "%%mm%d", modrm.reg);
12571   oappend (scratchbuf + intel_syntax);
12572 }
12573
12574 static void
12575 OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
12576 {
12577   int add;
12578   USED_REX (REX_R);
12579   if (rex & REX_R)
12580     add = 8;
12581   else
12582     add = 0;
12583   if (need_vex && bytemode != xmm_mode)
12584     {
12585       switch (vex.length)
12586         {
12587         case 128:
12588           sprintf (scratchbuf, "%%xmm%d", modrm.reg + add);
12589           break;
12590         case 256:
12591           sprintf (scratchbuf, "%%ymm%d", modrm.reg + add);
12592           break;
12593         default:
12594           abort ();
12595         }
12596     }
12597   else
12598     sprintf (scratchbuf, "%%xmm%d", modrm.reg + add);
12599   oappend (scratchbuf + intel_syntax);
12600 }
12601
12602 static void
12603 OP_EM (int bytemode, int sizeflag)
12604 {
12605   if (modrm.mod != 3)
12606     {
12607       if (intel_syntax
12608           && (bytemode == v_mode || bytemode == v_swap_mode))
12609         {
12610           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
12611           used_prefixes |= (prefixes & PREFIX_DATA);
12612         }
12613       OP_E (bytemode, sizeflag);
12614       return;
12615     }
12616
12617   if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode)
12618     swap_operand ();
12619
12620   /* Skip mod/rm byte.  */
12621   MODRM_CHECK;
12622   codep++;
12623   used_prefixes |= (prefixes & PREFIX_DATA);
12624   if (prefixes & PREFIX_DATA)
12625     {
12626       int add;
12627
12628       USED_REX (REX_B);
12629       if (rex & REX_B)
12630         add = 8;
12631       else
12632         add = 0;
12633       sprintf (scratchbuf, "%%xmm%d", modrm.rm + add);
12634     }
12635   else
12636     sprintf (scratchbuf, "%%mm%d", modrm.rm);
12637   oappend (scratchbuf + intel_syntax);
12638 }
12639
12640 /* cvt* are the only instructions in sse2 which have
12641    both SSE and MMX operands and also have 0x66 prefix
12642    in their opcode. 0x66 was originally used to differentiate
12643    between SSE and MMX instruction(operands). So we have to handle the
12644    cvt* separately using OP_EMC and OP_MXC */
12645 static void
12646 OP_EMC (int bytemode, int sizeflag)
12647 {
12648   if (modrm.mod != 3)
12649     {
12650       if (intel_syntax && bytemode == v_mode)
12651         {
12652           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
12653           used_prefixes |= (prefixes & PREFIX_DATA);
12654         }
12655       OP_E (bytemode, sizeflag);
12656       return;
12657     }
12658
12659   /* Skip mod/rm byte.  */
12660   MODRM_CHECK;
12661   codep++;
12662   used_prefixes |= (prefixes & PREFIX_DATA);
12663   sprintf (scratchbuf, "%%mm%d", modrm.rm);
12664   oappend (scratchbuf + intel_syntax);
12665 }
12666
12667 static void
12668 OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12669 {
12670   used_prefixes |= (prefixes & PREFIX_DATA);
12671   sprintf (scratchbuf, "%%mm%d", modrm.reg);
12672   oappend (scratchbuf + intel_syntax);
12673 }
12674
12675 static void
12676 OP_EX (int bytemode, int sizeflag)
12677 {
12678   int add;
12679   if (modrm.mod != 3)
12680     {
12681       OP_E (bytemode, sizeflag);
12682       return;
12683     }
12684   USED_REX (REX_B);
12685   if (rex & REX_B)
12686     add = 8;
12687   else
12688     add = 0;
12689
12690   if ((sizeflag & SUFFIX_ALWAYS)
12691       && (bytemode == x_swap_mode
12692           || bytemode == d_swap_mode
12693           || bytemode == q_swap_mode))
12694     swap_operand ();
12695
12696   /* Skip mod/rm byte.  */
12697   MODRM_CHECK;
12698   codep++;
12699   if (need_vex
12700       && bytemode != xmm_mode
12701       && bytemode != xmmq_mode)
12702     {
12703       switch (vex.length)
12704         {
12705         case 128:
12706           sprintf (scratchbuf, "%%xmm%d", modrm.rm + add);
12707           break;
12708         case 256:
12709           sprintf (scratchbuf, "%%ymm%d", modrm.rm + add);
12710           break;
12711         default:
12712           abort ();
12713         }
12714     }
12715   else
12716     sprintf (scratchbuf, "%%xmm%d", modrm.rm + add);
12717   oappend (scratchbuf + intel_syntax);
12718 }
12719
12720 static void
12721 OP_MS (int bytemode, int sizeflag)
12722 {
12723   if (modrm.mod == 3)
12724     OP_EM (bytemode, sizeflag);
12725   else
12726     BadOp ();
12727 }
12728
12729 static void
12730 OP_XS (int bytemode, int sizeflag)
12731 {
12732   if (modrm.mod == 3)
12733     OP_EX (bytemode, sizeflag);
12734   else
12735     BadOp ();
12736 }
12737
12738 static void
12739 OP_M (int bytemode, int sizeflag)
12740 {
12741   if (modrm.mod == 3)
12742     /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
12743     BadOp ();
12744   else
12745     OP_E (bytemode, sizeflag);
12746 }
12747
12748 static void
12749 OP_0f07 (int bytemode, int sizeflag)
12750 {
12751   if (modrm.mod != 3 || modrm.rm != 0)
12752     BadOp ();
12753   else
12754     OP_E (bytemode, sizeflag);
12755 }
12756
12757 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
12758    32bit mode and "xchg %rax,%rax" in 64bit mode.  */
12759
12760 static void
12761 NOP_Fixup1 (int bytemode, int sizeflag)
12762 {
12763   if ((prefixes & PREFIX_DATA) != 0
12764       || (rex != 0
12765           && rex != 0x48
12766           && address_mode == mode_64bit))
12767     OP_REG (bytemode, sizeflag);
12768   else
12769     strcpy (obuf, "nop");
12770 }
12771
12772 static void
12773 NOP_Fixup2 (int bytemode, int sizeflag)
12774 {
12775   if ((prefixes & PREFIX_DATA) != 0
12776       || (rex != 0
12777           && rex != 0x48
12778           && address_mode == mode_64bit))
12779     OP_IMREG (bytemode, sizeflag);
12780 }
12781
12782 static const char *const Suffix3DNow[] = {
12783 /* 00 */        NULL,           NULL,           NULL,           NULL,
12784 /* 04 */        NULL,           NULL,           NULL,           NULL,
12785 /* 08 */        NULL,           NULL,           NULL,           NULL,
12786 /* 0C */        "pi2fw",        "pi2fd",        NULL,           NULL,
12787 /* 10 */        NULL,           NULL,           NULL,           NULL,
12788 /* 14 */        NULL,           NULL,           NULL,           NULL,
12789 /* 18 */        NULL,           NULL,           NULL,           NULL,
12790 /* 1C */        "pf2iw",        "pf2id",        NULL,           NULL,
12791 /* 20 */        NULL,           NULL,           NULL,           NULL,
12792 /* 24 */        NULL,           NULL,           NULL,           NULL,
12793 /* 28 */        NULL,           NULL,           NULL,           NULL,
12794 /* 2C */        NULL,           NULL,           NULL,           NULL,
12795 /* 30 */        NULL,           NULL,           NULL,           NULL,
12796 /* 34 */        NULL,           NULL,           NULL,           NULL,
12797 /* 38 */        NULL,           NULL,           NULL,           NULL,
12798 /* 3C */        NULL,           NULL,           NULL,           NULL,
12799 /* 40 */        NULL,           NULL,           NULL,           NULL,
12800 /* 44 */        NULL,           NULL,           NULL,           NULL,
12801 /* 48 */        NULL,           NULL,           NULL,           NULL,
12802 /* 4C */        NULL,           NULL,           NULL,           NULL,
12803 /* 50 */        NULL,           NULL,           NULL,           NULL,
12804 /* 54 */        NULL,           NULL,           NULL,           NULL,
12805 /* 58 */        NULL,           NULL,           NULL,           NULL,
12806 /* 5C */        NULL,           NULL,           NULL,           NULL,
12807 /* 60 */        NULL,           NULL,           NULL,           NULL,
12808 /* 64 */        NULL,           NULL,           NULL,           NULL,
12809 /* 68 */        NULL,           NULL,           NULL,           NULL,
12810 /* 6C */        NULL,           NULL,           NULL,           NULL,
12811 /* 70 */        NULL,           NULL,           NULL,           NULL,
12812 /* 74 */        NULL,           NULL,           NULL,           NULL,
12813 /* 78 */        NULL,           NULL,           NULL,           NULL,
12814 /* 7C */        NULL,           NULL,           NULL,           NULL,
12815 /* 80 */        NULL,           NULL,           NULL,           NULL,
12816 /* 84 */        NULL,           NULL,           NULL,           NULL,
12817 /* 88 */        NULL,           NULL,           "pfnacc",       NULL,
12818 /* 8C */        NULL,           NULL,           "pfpnacc",      NULL,
12819 /* 90 */        "pfcmpge",      NULL,           NULL,           NULL,
12820 /* 94 */        "pfmin",        NULL,           "pfrcp",        "pfrsqrt",
12821 /* 98 */        NULL,           NULL,           "pfsub",        NULL,
12822 /* 9C */        NULL,           NULL,           "pfadd",        NULL,
12823 /* A0 */        "pfcmpgt",      NULL,           NULL,           NULL,
12824 /* A4 */        "pfmax",        NULL,           "pfrcpit1",     "pfrsqit1",
12825 /* A8 */        NULL,           NULL,           "pfsubr",       NULL,
12826 /* AC */        NULL,           NULL,           "pfacc",        NULL,
12827 /* B0 */        "pfcmpeq",      NULL,           NULL,           NULL,
12828 /* B4 */        "pfmul",        NULL,           "pfrcpit2",     "pmulhrw",
12829 /* B8 */        NULL,           NULL,           NULL,           "pswapd",
12830 /* BC */        NULL,           NULL,           NULL,           "pavgusb",
12831 /* C0 */        NULL,           NULL,           NULL,           NULL,
12832 /* C4 */        NULL,           NULL,           NULL,           NULL,
12833 /* C8 */        NULL,           NULL,           NULL,           NULL,
12834 /* CC */        NULL,           NULL,           NULL,           NULL,
12835 /* D0 */        NULL,           NULL,           NULL,           NULL,
12836 /* D4 */        NULL,           NULL,           NULL,           NULL,
12837 /* D8 */        NULL,           NULL,           NULL,           NULL,
12838 /* DC */        NULL,           NULL,           NULL,           NULL,
12839 /* E0 */        NULL,           NULL,           NULL,           NULL,
12840 /* E4 */        NULL,           NULL,           NULL,           NULL,
12841 /* E8 */        NULL,           NULL,           NULL,           NULL,
12842 /* EC */        NULL,           NULL,           NULL,           NULL,
12843 /* F0 */        NULL,           NULL,           NULL,           NULL,
12844 /* F4 */        NULL,           NULL,           NULL,           NULL,
12845 /* F8 */        NULL,           NULL,           NULL,           NULL,
12846 /* FC */        NULL,           NULL,           NULL,           NULL,
12847 };
12848
12849 static void
12850 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12851 {
12852   const char *mnemonic;
12853
12854   FETCH_DATA (the_info, codep + 1);
12855   /* AMD 3DNow! instructions are specified by an opcode suffix in the
12856      place where an 8-bit immediate would normally go.  ie. the last
12857      byte of the instruction.  */
12858   obufp = mnemonicendp;
12859   mnemonic = Suffix3DNow[*codep++ & 0xff];
12860   if (mnemonic)
12861     oappend (mnemonic);
12862   else
12863     {
12864       /* Since a variable sized modrm/sib chunk is between the start
12865          of the opcode (0x0f0f) and the opcode suffix, we need to do
12866          all the modrm processing first, and don't know until now that
12867          we have a bad opcode.  This necessitates some cleaning up.  */
12868       op_out[0][0] = '\0';
12869       op_out[1][0] = '\0';
12870       BadOp ();
12871     }
12872   mnemonicendp = obufp;
12873 }
12874
12875 static struct op simd_cmp_op[] =
12876 {
12877   { STRING_COMMA_LEN ("eq") },
12878   { STRING_COMMA_LEN ("lt") },
12879   { STRING_COMMA_LEN ("le") },
12880   { STRING_COMMA_LEN ("unord") },
12881   { STRING_COMMA_LEN ("neq") },
12882   { STRING_COMMA_LEN ("nlt") },
12883   { STRING_COMMA_LEN ("nle") },
12884   { STRING_COMMA_LEN ("ord") }
12885 };
12886
12887 static void
12888 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12889 {
12890   unsigned int cmp_type;
12891
12892   FETCH_DATA (the_info, codep + 1);
12893   cmp_type = *codep++ & 0xff;
12894   if (cmp_type < ARRAY_SIZE (simd_cmp_op))
12895     {
12896       char suffix [3];
12897       char *p = mnemonicendp - 2;
12898       suffix[0] = p[0];
12899       suffix[1] = p[1];
12900       suffix[2] = '\0';
12901       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
12902       mnemonicendp += simd_cmp_op[cmp_type].len;
12903     }
12904   else
12905     {
12906       /* We have a reserved extension byte.  Output it directly.  */
12907       scratchbuf[0] = '$';
12908       print_operand_value (scratchbuf + 1, 1, cmp_type);
12909       oappend (scratchbuf + intel_syntax);
12910       scratchbuf[0] = '\0';
12911     }
12912 }
12913
12914 static void
12915 OP_Mwait (int bytemode ATTRIBUTE_UNUSED,
12916           int sizeflag ATTRIBUTE_UNUSED)
12917 {
12918   /* mwait %eax,%ecx  */
12919   if (!intel_syntax)
12920     {
12921       const char **names = (address_mode == mode_64bit
12922                             ? names64 : names32);
12923       strcpy (op_out[0], names[0]);
12924       strcpy (op_out[1], names[1]);
12925       two_source_ops = 1;
12926     }
12927   /* Skip mod/rm byte.  */
12928   MODRM_CHECK;
12929   codep++;
12930 }
12931
12932 static void
12933 OP_Monitor (int bytemode ATTRIBUTE_UNUSED,
12934             int sizeflag ATTRIBUTE_UNUSED)
12935 {
12936   /* monitor %eax,%ecx,%edx"  */
12937   if (!intel_syntax)
12938     {
12939       const char **op1_names;
12940       const char **names = (address_mode == mode_64bit
12941                             ? names64 : names32);
12942
12943       if (!(prefixes & PREFIX_ADDR))
12944         op1_names = (address_mode == mode_16bit
12945                      ? names16 : names);
12946       else
12947         {
12948           /* Remove "addr16/addr32".  */
12949           addr_prefix = NULL;
12950           op1_names = (address_mode != mode_32bit
12951                        ? names32 : names16);
12952           used_prefixes |= PREFIX_ADDR;
12953         }
12954       strcpy (op_out[0], op1_names[0]);
12955       strcpy (op_out[1], names[1]);
12956       strcpy (op_out[2], names[2]);
12957       two_source_ops = 1;
12958     }
12959   /* Skip mod/rm byte.  */
12960   MODRM_CHECK;
12961   codep++;
12962 }
12963
12964 static void
12965 BadOp (void)
12966 {
12967   /* Throw away prefixes and 1st. opcode byte.  */
12968   codep = insn_codep + 1;
12969   oappend ("(bad)");
12970 }
12971
12972 static void
12973 REP_Fixup (int bytemode, int sizeflag)
12974 {
12975   /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
12976      lods and stos.  */
12977   if (prefixes & PREFIX_REPZ)
12978     repz_prefix = "rep ";
12979
12980   switch (bytemode)
12981     {
12982     case al_reg:
12983     case eAX_reg:
12984     case indir_dx_reg:
12985       OP_IMREG (bytemode, sizeflag);
12986       break;
12987     case eDI_reg:
12988       OP_ESreg (bytemode, sizeflag);
12989       break;
12990     case eSI_reg:
12991       OP_DSreg (bytemode, sizeflag);
12992       break;
12993     default:
12994       abort ();
12995       break;
12996     }
12997 }
12998
12999 static void
13000 CMPXCHG8B_Fixup (int bytemode, int sizeflag)
13001 {
13002   USED_REX (REX_W);
13003   if (rex & REX_W)
13004     {
13005       /* Change cmpxchg8b to cmpxchg16b.  */
13006       char *p = mnemonicendp - 2;
13007       mnemonicendp = stpcpy (p, "16b");
13008       bytemode = o_mode;
13009     }
13010   OP_M (bytemode, sizeflag);
13011 }
13012
13013 static void
13014 XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED)
13015 {
13016   if (need_vex)
13017     {
13018       switch (vex.length)
13019         {
13020         case 128:
13021           sprintf (scratchbuf, "%%xmm%d", reg);
13022           break;
13023         case 256:
13024           sprintf (scratchbuf, "%%ymm%d", reg);
13025           break;
13026         default:
13027           abort ();
13028         }
13029     }
13030   else
13031     sprintf (scratchbuf, "%%xmm%d", reg);
13032   oappend (scratchbuf + intel_syntax);
13033 }
13034
13035 static void
13036 CRC32_Fixup (int bytemode, int sizeflag)
13037 {
13038   /* Add proper suffix to "crc32".  */
13039   char *p = mnemonicendp;
13040
13041   switch (bytemode)
13042     {
13043     case b_mode:
13044       if (intel_syntax)
13045         goto skip;
13046
13047       *p++ = 'b';
13048       break;
13049     case v_mode:
13050       if (intel_syntax)
13051         goto skip;
13052
13053       USED_REX (REX_W);
13054       if (rex & REX_W)
13055         *p++ = 'q';
13056       else if (sizeflag & DFLAG)
13057         *p++ = 'l';
13058       else
13059         *p++ = 'w';
13060       used_prefixes |= (prefixes & PREFIX_DATA);
13061       break;
13062     default:
13063       oappend (INTERNAL_DISASSEMBLER_ERROR);
13064       break;
13065     }
13066   mnemonicendp = p;
13067   *p = '\0';
13068
13069 skip:
13070   if (modrm.mod == 3)
13071     {
13072       int add;
13073
13074       /* Skip mod/rm byte.  */
13075       MODRM_CHECK;
13076       codep++;
13077
13078       USED_REX (REX_B);
13079       add = (rex & REX_B) ? 8 : 0;
13080       if (bytemode == b_mode)
13081         {
13082           USED_REX (0);
13083           if (rex)
13084             oappend (names8rex[modrm.rm + add]);
13085           else
13086             oappend (names8[modrm.rm + add]);
13087         }
13088       else
13089         {
13090           USED_REX (REX_W);
13091           if (rex & REX_W)
13092             oappend (names64[modrm.rm + add]);
13093           else if ((prefixes & PREFIX_DATA))
13094             oappend (names16[modrm.rm + add]);
13095           else
13096             oappend (names32[modrm.rm + add]);
13097         }
13098     }
13099   else
13100     OP_E (bytemode, sizeflag);
13101 }
13102
13103 /* Print a DREX argument as either a register or memory operation.  */
13104 static void
13105 print_drex_arg (unsigned int reg, int bytemode, int sizeflag)
13106 {
13107   if (reg == DREX_REG_UNKNOWN)
13108     BadOp ();
13109
13110   else if (reg != DREX_REG_MEMORY)
13111     {
13112       sprintf (scratchbuf, "%%xmm%d", reg);
13113       oappend (scratchbuf + intel_syntax);
13114     }
13115
13116   else
13117     OP_E_extended (bytemode, sizeflag, 1);
13118 }
13119
13120 /* SSE5 instructions that have 4 arguments are encoded as:
13121    0f 24 <sub-opcode> <modrm> <optional-sib> <drex> <offset>.
13122
13123    The <sub-opcode> byte has 1 bit (0x4) that is combined with 1 bit in
13124    the DREX field (0x8) to determine how the arguments are laid out.
13125    The destination register must be the same register as one of the
13126    inputs, and it is encoded in the DREX byte.  No REX prefix is used
13127    for these instructions, since the DREX field contains the 3 extension
13128    bits provided by the REX prefix.
13129
13130    The bytemode argument adds 2 extra bits for passing extra information:
13131         DREX_OC1        -- Set the OC1 bit to indicate dest == 1st arg
13132         DREX_NO_OC0     -- OC0 in DREX is invalid
13133         (but pretend it is set).  */
13134
13135 static void
13136 OP_DREX4 (int flag_bytemode, int sizeflag)
13137 {
13138   unsigned int drex_byte;
13139   unsigned int regs[4];
13140   unsigned int modrm_regmem;
13141   unsigned int modrm_reg;
13142   unsigned int drex_reg;
13143   int bytemode;
13144   int rex_save = rex;
13145   int rex_used_save = rex_used;
13146   int has_sib = 0;
13147   int oc1 = (flag_bytemode & DREX_OC1) ? 2 : 0;
13148   int oc0;
13149   int i;
13150
13151   bytemode = flag_bytemode & ~ DREX_MASK;
13152
13153   for (i = 0; i < 4; i++)
13154     regs[i] = DREX_REG_UNKNOWN;
13155
13156   /* Determine if we have a SIB byte in addition to MODRM before the
13157      DREX byte.  */
13158   if (((sizeflag & AFLAG) || address_mode == mode_64bit)
13159       && (modrm.mod != 3)
13160       && (modrm.rm == 4))
13161     has_sib = 1;
13162
13163   /* Get the DREX byte.  */
13164   FETCH_DATA (the_info, codep + 2 + has_sib);
13165   drex_byte = codep[has_sib+1];
13166   drex_reg = DREX_XMM (drex_byte);
13167   modrm_reg = modrm.reg + ((drex_byte & REX_R) ? 8 : 0);
13168
13169   /* Is OC0 legal?  If not, hardwire oc0 == 1.  */
13170   if (flag_bytemode & DREX_NO_OC0)
13171     {
13172       oc0 = 1;
13173       if (DREX_OC0 (drex_byte))
13174         BadOp ();
13175     }
13176   else
13177     oc0 = DREX_OC0 (drex_byte);
13178
13179   if (modrm.mod == 3)
13180     {
13181       /* regmem == register  */
13182       modrm_regmem = modrm.rm + ((drex_byte & REX_B) ? 8 : 0);
13183       rex = rex_used = 0;
13184       /* skip modrm/drex since we don't call OP_E_extended  */
13185       codep += 2;
13186     }
13187   else
13188     {
13189       /* regmem == memory, fill in appropriate REX bits  */
13190       modrm_regmem = DREX_REG_MEMORY;
13191       rex = drex_byte & (REX_B | REX_X | REX_R);
13192       if (rex)
13193         rex |= REX_OPCODE;
13194       rex_used = rex;
13195     }
13196
13197   /* Based on the OC1/OC0 bits, lay out the arguments in the correct
13198      order.  */
13199   switch (oc0 + oc1)
13200     {
13201     default:
13202       BadOp ();
13203       return;
13204
13205     case 0:
13206       regs[0] = modrm_regmem;
13207       regs[1] = modrm_reg;
13208       regs[2] = drex_reg;
13209       regs[3] = drex_reg;
13210       break;
13211
13212     case 1:
13213       regs[0] = modrm_reg;
13214       regs[1] = modrm_regmem;
13215       regs[2] = drex_reg;
13216       regs[3] = drex_reg;
13217       break;
13218
13219     case 2:
13220       regs[0] = drex_reg;
13221       regs[1] = modrm_regmem;
13222       regs[2] = modrm_reg;
13223       regs[3] = drex_reg;
13224       break;
13225
13226     case 3:
13227       regs[0] = drex_reg;
13228       regs[1] = modrm_reg;
13229       regs[2] = modrm_regmem;
13230       regs[3] = drex_reg;
13231       break;
13232     }
13233
13234   /* Print out the arguments.  */
13235   for (i = 0; i < 4; i++)
13236     {
13237       int j = (intel_syntax) ? 3 - i : i;
13238       if (i > 0)
13239         {
13240           *obufp++ = ',';
13241           *obufp = '\0';
13242         }
13243
13244       print_drex_arg (regs[j], bytemode, sizeflag);
13245     }
13246
13247   rex = rex_save;
13248   rex_used = rex_used_save;
13249 }
13250
13251 /* SSE5 instructions that have 3 arguments, and are encoded as:
13252    0f 24 <sub-opcode> <modrm> <optional-sib> <drex> <offset>    (or)
13253    0f 25 <sub-opcode> <modrm> <optional-sib> <drex> <offset> <cmp-byte>
13254
13255    The DREX field has 1 bit (0x8) to determine how the arguments are
13256    laid out. The destination register is encoded in the DREX byte.
13257    No REX prefix is used for these instructions, since the DREX field
13258    contains the 3 extension bits provided by the REX prefix.  */
13259
13260 static void
13261 OP_DREX3 (int flag_bytemode, int sizeflag)
13262 {
13263   unsigned int drex_byte;
13264   unsigned int regs[3];
13265   unsigned int modrm_regmem;
13266   unsigned int modrm_reg;
13267   unsigned int drex_reg;
13268   int bytemode;
13269   int rex_save = rex;
13270   int rex_used_save = rex_used;
13271   int has_sib = 0;
13272   int oc0;
13273   int i;
13274
13275   bytemode = flag_bytemode & ~ DREX_MASK;
13276
13277   for (i = 0; i < 3; i++)
13278     regs[i] = DREX_REG_UNKNOWN;
13279
13280   /* Determine if we have a SIB byte in addition to MODRM before the
13281      DREX byte.  */
13282   if (((sizeflag & AFLAG) || address_mode == mode_64bit)
13283       && (modrm.mod != 3)
13284       && (modrm.rm == 4))
13285     has_sib = 1;
13286
13287   /* Get the DREX byte.  */
13288   FETCH_DATA (the_info, codep + 2 + has_sib);
13289   drex_byte = codep[has_sib+1];
13290   drex_reg = DREX_XMM (drex_byte);
13291   modrm_reg = modrm.reg + ((drex_byte & REX_R) ? 8 : 0);
13292
13293   /* Is OC0 legal?  If not, hardwire oc0 == 0 */
13294   oc0 = DREX_OC0 (drex_byte);
13295   if ((flag_bytemode & DREX_NO_OC0) && oc0)
13296     BadOp ();
13297
13298   if (modrm.mod == 3)
13299     {
13300       /* regmem == register */
13301       modrm_regmem = modrm.rm + ((drex_byte & REX_B) ? 8 : 0);
13302       rex = rex_used = 0;
13303       /* skip modrm/drex since we don't call OP_E_extended.  */
13304       codep += 2;
13305     }
13306   else
13307     {
13308       /* regmem == memory, fill in appropriate REX bits.  */
13309       modrm_regmem = DREX_REG_MEMORY;
13310       rex = drex_byte & (REX_B | REX_X | REX_R);
13311       if (rex)
13312         rex |= REX_OPCODE;
13313       rex_used = rex;
13314     }
13315
13316   /* Based on the OC1/OC0 bits, lay out the arguments in the correct
13317      order.  */
13318   switch (oc0)
13319     {
13320     default:
13321       BadOp ();
13322       return;
13323
13324     case 0:
13325       regs[0] = modrm_regmem;
13326       regs[1] = modrm_reg;
13327       regs[2] = drex_reg;
13328       break;
13329
13330     case 1:
13331       regs[0] = modrm_reg;
13332       regs[1] = modrm_regmem;
13333       regs[2] = drex_reg;
13334       break;
13335     }
13336
13337   /* Print out the arguments.  */
13338   for (i = 0; i < 3; i++)
13339     {
13340       int j = (intel_syntax) ? 2 - i : i;
13341       if (i > 0)
13342         {
13343           *obufp++ = ',';
13344           *obufp = '\0';
13345         }
13346
13347       print_drex_arg (regs[j], bytemode, sizeflag);
13348     }
13349
13350   rex = rex_save;
13351   rex_used = rex_used_save;
13352 }
13353
13354 /* Emit a floating point comparison for comp<xx> instructions.  */
13355
13356 static void
13357 OP_DREX_FCMP (int bytemode ATTRIBUTE_UNUSED,
13358               int sizeflag ATTRIBUTE_UNUSED)
13359 {
13360   unsigned char byte;
13361
13362   static const char *const cmp_test[] = {
13363     "eq",
13364     "lt",
13365     "le",
13366     "unord",
13367     "ne",
13368     "nlt",
13369     "nle",
13370     "ord",
13371     "ueq",
13372     "ult",
13373     "ule",
13374     "false",
13375     "une",
13376     "unlt",
13377     "unle",
13378     "true"
13379   };
13380
13381   FETCH_DATA (the_info, codep + 1);
13382   byte = *codep & 0xff;
13383
13384   if (byte >= ARRAY_SIZE (cmp_test)
13385       || obuf[0] != 'c'
13386       || obuf[1] != 'o'
13387       || obuf[2] != 'm')
13388     {
13389       /* The instruction isn't one we know about, so just append the
13390          extension byte as a numeric value.  */
13391       OP_I (b_mode, 0);
13392     }
13393
13394   else
13395     {
13396       sprintf (scratchbuf, "com%s%s", cmp_test[byte], obuf+3);
13397       mnemonicendp = stpcpy (obuf, scratchbuf);
13398       codep++;
13399     }
13400 }
13401
13402 /* Emit an integer point comparison for pcom<xx> instructions,
13403    rewriting the instruction to have the test inside of it.  */
13404
13405 static void
13406 OP_DREX_ICMP (int bytemode ATTRIBUTE_UNUSED,
13407               int sizeflag ATTRIBUTE_UNUSED)
13408 {
13409   unsigned char byte;
13410
13411   static const char *const cmp_test[] = {
13412     "lt",
13413     "le",
13414     "gt",
13415     "ge",
13416     "eq",
13417     "ne",
13418     "false",
13419     "true"
13420   };
13421
13422   FETCH_DATA (the_info, codep + 1);
13423   byte = *codep & 0xff;
13424
13425   if (byte >= ARRAY_SIZE (cmp_test)
13426       || obuf[0] != 'p'
13427       || obuf[1] != 'c'
13428       || obuf[2] != 'o'
13429       || obuf[3] != 'm')
13430     {
13431       /* The instruction isn't one we know about, so just print the
13432          comparison test byte as a numeric value.  */
13433       OP_I (b_mode, 0);
13434     }
13435
13436   else
13437     {
13438       sprintf (scratchbuf, "pcom%s%s", cmp_test[byte], obuf+4);
13439       mnemonicendp = stpcpy (obuf, scratchbuf);
13440       codep++;
13441     }
13442 }
13443
13444 /* Display the destination register operand for instructions with
13445    VEX. */
13446
13447 static void
13448 OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
13449 {
13450   if (!need_vex)
13451     abort ();
13452
13453   if (!need_vex_reg)
13454     return;
13455
13456   switch (vex.length)
13457     {
13458     case 128:
13459       switch (bytemode)
13460         {
13461         case vex_mode:
13462         case vex128_mode:
13463           break;
13464         default:
13465           abort ();
13466           return;
13467         }
13468
13469       sprintf (scratchbuf, "%%xmm%d", vex.register_specifier);
13470       break;
13471     case 256:
13472       switch (bytemode)
13473         {
13474         case vex_mode:
13475         case vex256_mode:
13476           break;
13477         default:
13478           abort ();
13479           return;
13480         }
13481
13482       sprintf (scratchbuf, "%%ymm%d", vex.register_specifier);
13483       break;
13484     default:
13485       abort ();
13486       break;
13487     }
13488   oappend (scratchbuf + intel_syntax);
13489 }
13490
13491 static void
13492 OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
13493 {
13494   int reg;
13495   FETCH_DATA (the_info, codep + 1);
13496   reg = *codep++;
13497
13498   if (bytemode != x_mode)
13499     abort ();
13500
13501   if (reg & 0xf)
13502       BadOp ();
13503
13504   reg >>= 4;
13505   if (reg > 7 && address_mode != mode_64bit)
13506     BadOp ();
13507
13508   switch (vex.length)
13509     {
13510     case 128:
13511       sprintf (scratchbuf, "%%xmm%d", reg);
13512       break;
13513     case 256:
13514       sprintf (scratchbuf, "%%ymm%d", reg);
13515       break;
13516     default:
13517       abort ();
13518     }
13519   oappend (scratchbuf + intel_syntax);
13520 }
13521
13522 static void
13523 OP_EX_Vex (int bytemode, int sizeflag)
13524 {
13525   if (modrm.mod != 3)
13526     {
13527       if (vex.register_specifier != 0)
13528         BadOp ();
13529       need_vex_reg = 0;
13530     }
13531   OP_EX (bytemode, sizeflag);
13532 }
13533
13534 static void
13535 OP_XMM_Vex (int bytemode, int sizeflag)
13536 {
13537   if (modrm.mod != 3)
13538     {
13539       if (vex.register_specifier != 0)
13540         BadOp ();
13541       need_vex_reg = 0;
13542     }
13543   OP_XMM (bytemode, sizeflag);
13544 }
13545
13546 static void
13547 VZERO_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13548 {
13549   switch (vex.length)
13550     {
13551     case 128:
13552       mnemonicendp = stpcpy (obuf, "vzeroupper");
13553       break;
13554     case 256:
13555       mnemonicendp = stpcpy (obuf, "vzeroall");
13556       break;
13557     default:
13558       abort ();
13559     }
13560 }
13561
13562 static struct op vex_cmp_op[] =
13563 {
13564   { STRING_COMMA_LEN ("eq") },
13565   { STRING_COMMA_LEN ("lt") },
13566   { STRING_COMMA_LEN ("le") },
13567   { STRING_COMMA_LEN ("unord") },
13568   { STRING_COMMA_LEN ("neq") },
13569   { STRING_COMMA_LEN ("nlt") },
13570   { STRING_COMMA_LEN ("nle") },
13571   { STRING_COMMA_LEN ("ord") },
13572   { STRING_COMMA_LEN ("eq_uq") },
13573   { STRING_COMMA_LEN ("nge") },
13574   { STRING_COMMA_LEN ("ngt") },
13575   { STRING_COMMA_LEN ("false") },
13576   { STRING_COMMA_LEN ("neq_oq") },
13577   { STRING_COMMA_LEN ("ge") },
13578   { STRING_COMMA_LEN ("gt") },
13579   { STRING_COMMA_LEN ("true") },
13580   { STRING_COMMA_LEN ("eq_os") },
13581   { STRING_COMMA_LEN ("lt_oq") },
13582   { STRING_COMMA_LEN ("le_oq") },
13583   { STRING_COMMA_LEN ("unord_s") },
13584   { STRING_COMMA_LEN ("neq_us") },
13585   { STRING_COMMA_LEN ("nlt_uq") },
13586   { STRING_COMMA_LEN ("nle_uq") },
13587   { STRING_COMMA_LEN ("ord_s") },
13588   { STRING_COMMA_LEN ("eq_us") },
13589   { STRING_COMMA_LEN ("nge_uq") },
13590   { STRING_COMMA_LEN ("ngt_uq") },
13591   { STRING_COMMA_LEN ("false_os") },
13592   { STRING_COMMA_LEN ("neq_os") },
13593   { STRING_COMMA_LEN ("ge_oq") },
13594   { STRING_COMMA_LEN ("gt_oq") },
13595   { STRING_COMMA_LEN ("true_us") },
13596 };
13597
13598 static void
13599 VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13600 {
13601   unsigned int cmp_type;
13602
13603   FETCH_DATA (the_info, codep + 1);
13604   cmp_type = *codep++ & 0xff;
13605   if (cmp_type < ARRAY_SIZE (vex_cmp_op))
13606     {
13607       char suffix [3];
13608       char *p = mnemonicendp - 2;
13609       suffix[0] = p[0];
13610       suffix[1] = p[1];
13611       suffix[2] = '\0';
13612       sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix);
13613       mnemonicendp += vex_cmp_op[cmp_type].len;
13614     }
13615   else
13616     {
13617       /* We have a reserved extension byte.  Output it directly.  */
13618       scratchbuf[0] = '$';
13619       print_operand_value (scratchbuf + 1, 1, cmp_type);
13620       oappend (scratchbuf + intel_syntax);
13621       scratchbuf[0] = '\0';
13622     }
13623 }
13624
13625 static const struct op pclmul_op[] =
13626 {
13627   { STRING_COMMA_LEN ("lql") },
13628   { STRING_COMMA_LEN ("hql") },
13629   { STRING_COMMA_LEN ("lqh") },
13630   { STRING_COMMA_LEN ("hqh") }
13631 };
13632
13633 static void
13634 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED,
13635               int sizeflag ATTRIBUTE_UNUSED)
13636 {
13637   unsigned int pclmul_type;
13638
13639   FETCH_DATA (the_info, codep + 1);
13640   pclmul_type = *codep++ & 0xff;
13641   switch (pclmul_type)
13642     {
13643     case 0x10:
13644       pclmul_type = 2;
13645       break;
13646     case 0x11:
13647       pclmul_type = 3;
13648       break;
13649     default:
13650       break;
13651     }
13652   if (pclmul_type < ARRAY_SIZE (pclmul_op))
13653     {
13654       char suffix [4];
13655       char *p = mnemonicendp - 3;
13656       suffix[0] = p[0];
13657       suffix[1] = p[1];
13658       suffix[2] = p[2];
13659       suffix[3] = '\0';
13660       sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix);
13661       mnemonicendp += pclmul_op[pclmul_type].len;
13662     }
13663   else
13664     {
13665       /* We have a reserved extension byte.  Output it directly.  */
13666       scratchbuf[0] = '$';
13667       print_operand_value (scratchbuf + 1, 1, pclmul_type);
13668       oappend (scratchbuf + intel_syntax);
13669       scratchbuf[0] = '\0';
13670     }
13671 }
13672
13673 static void
13674 MOVBE_Fixup (int bytemode, int sizeflag)
13675 {
13676   /* Add proper suffix to "movbe".  */
13677   char *p = mnemonicendp;
13678
13679   switch (bytemode)
13680     {
13681     case v_mode:
13682       if (intel_syntax)
13683         goto skip;
13684
13685       USED_REX (REX_W);
13686       if (sizeflag & SUFFIX_ALWAYS)
13687         {
13688           if (rex & REX_W)
13689             *p++ = 'q';
13690           else if (sizeflag & DFLAG)
13691             *p++ = 'l';
13692           else
13693             *p++ = 'w';
13694         }
13695       used_prefixes |= (prefixes & PREFIX_DATA);
13696       break;
13697     default:
13698       oappend (INTERNAL_DISASSEMBLER_ERROR);
13699       break;
13700     }
13701   mnemonicendp = p;
13702   *p = '\0';
13703
13704 skip:
13705   OP_M (bytemode, sizeflag);
13706 }