include/opcode/ia64.h

   1 /* ia64.h -- Header file for ia64 opcode table
   2    Copyright (C) 1998, 1999, 2000, 2002 Free Software Foundation, Inc.
   3         Contributed by David Mosberger-Tang <davidm@hpl.hp.com> */
   4
   5 #ifndef opcode_ia64_h
   6 #define opcode_ia64_h
   7
   8 #include <sys/types.h>
   9
  10 #include "bfd.h"
  11
  12
  13 typedef BFD_HOST_U_64_BIT ia64_insn;
  14
  15 enum ia64_insn_type
  16   {
  17     IA64_TYPE_NIL = 0,  /* illegal type */
  18     IA64_TYPE_A,        /* integer alu (I- or M-unit) */
  19     IA64_TYPE_I,        /* non-alu integer (I-unit) */
  20     IA64_TYPE_M,        /* memory (M-unit) */
  21     IA64_TYPE_B,        /* branch (B-unit) */
  22     IA64_TYPE_F,        /* floating-point (F-unit) */
  23     IA64_TYPE_X,        /* long encoding (X-unit) */
  24     IA64_TYPE_DYN,      /* Dynamic opcode */
  25     IA64_NUM_TYPES
  26   };
  27
  28 enum ia64_unit
  29   {
  30     IA64_UNIT_NIL = 0,  /* illegal unit */
  31     IA64_UNIT_I,        /* integer unit */
  32     IA64_UNIT_M,        /* memory unit */
  33     IA64_UNIT_B,        /* branching unit */
  34     IA64_UNIT_F,        /* floating-point unit */
  35     IA64_UNIT_L,        /* long "unit" */
  36     IA64_UNIT_X,        /* may be integer or branch unit */
  37     IA64_NUM_UNITS
  38   };
  39
  40 /* Changes to this enumeration must be propagated to the operand table in
  41    bfd/cpu-ia64-opc.c
  42  */
  43 enum ia64_opnd
  44   {
  45     IA64_OPND_NIL,      /* no operand---MUST BE FIRST!*/
  46
  47     /* constants */
  48     IA64_OPND_AR_CSD,   /* application register csd (ar.csd) */
  49     IA64_OPND_AR_CCV,   /* application register ccv (ar.ccv) */
  50     IA64_OPND_AR_PFS,   /* application register pfs (ar.pfs) */
  51     IA64_OPND_C1,       /* the constant 1 */
  52     IA64_OPND_C8,       /* the constant 8 */
  53     IA64_OPND_C16,      /* the constant 16 */
  54     IA64_OPND_GR0,      /* gr0 */
  55     IA64_OPND_IP,       /* instruction pointer (ip) */
  56     IA64_OPND_PR,       /* predicate register (pr) */
  57     IA64_OPND_PR_ROT,   /* rotating predicate register (pr.rot) */
  58     IA64_OPND_PSR,      /* processor status register (psr) */
  59     IA64_OPND_PSR_L,    /* processor status register L (psr.l) */
  60     IA64_OPND_PSR_UM,   /* processor status register UM (psr.um) */
  61
  62     /* register operands: */
  63     IA64_OPND_AR3,      /* third application register # (bits 20-26) */
  64     IA64_OPND_B1,       /* branch register # (bits 6-8) */
  65     IA64_OPND_B2,       /* branch register # (bits 13-15) */
  66     IA64_OPND_CR3,      /* third control register # (bits 20-26) */
  67     IA64_OPND_F1,       /* first floating-point register # */
  68     IA64_OPND_F2,       /* second floating-point register # */
  69     IA64_OPND_F3,       /* third floating-point register # */
  70     IA64_OPND_F4,       /* fourth floating-point register # */
  71     IA64_OPND_P1,       /* first predicate # */
  72     IA64_OPND_P2,       /* second predicate # */
  73     IA64_OPND_R1,       /* first register # */
  74     IA64_OPND_R2,       /* second register # */
  75     IA64_OPND_R3,       /* third register # */
  76     IA64_OPND_R3_2,     /* third register # (limited to gr0-gr3) */
  77
  78     /* memory operands: */
  79     IA64_OPND_MR3,      /* memory at addr of third register # */
  80
  81     /* indirect operands: */
  82     IA64_OPND_CPUID_R3, /* cpuid[reg] */
  83     IA64_OPND_DBR_R3,   /* dbr[reg] */
  84     IA64_OPND_DTR_R3,   /* dtr[reg] */
  85     IA64_OPND_ITR_R3,   /* itr[reg] */
  86     IA64_OPND_IBR_R3,   /* ibr[reg] */
  87     IA64_OPND_MSR_R3,   /* msr[reg] */
  88     IA64_OPND_PKR_R3,   /* pkr[reg] */
  89     IA64_OPND_PMC_R3,   /* pmc[reg] */
  90     IA64_OPND_PMD_R3,   /* pmd[reg] */
  91     IA64_OPND_RR_R3,    /* rr[reg] */
  92
  93     /* immediate operands: */
  94     IA64_OPND_CCNT5,    /* 5-bit count (31 - bits 20-24) */
  95     IA64_OPND_CNT2a,    /* 2-bit count (1 + bits 27-28) */
  96     IA64_OPND_CNT2b,    /* 2-bit count (bits 27-28): 1, 2, 3 */
  97     IA64_OPND_CNT2c,    /* 2-bit count (bits 30-31): 0, 7, 15, or 16 */
  98     IA64_OPND_CNT5,     /* 5-bit count (bits 14-18) */
  99     IA64_OPND_CNT6,     /* 6-bit count (bits 27-32) */
 100     IA64_OPND_CPOS6a,   /* 6-bit count (63 - bits 20-25) */
 101     IA64_OPND_CPOS6b,   /* 6-bit count (63 - bits 14-19) */
 102     IA64_OPND_CPOS6c,   /* 6-bit count (63 - bits 31-36) */
 103     IA64_OPND_IMM1,     /* signed 1-bit immediate (bit 36) */
 104     IA64_OPND_IMMU2,    /* unsigned 2-bit immediate (bits 13-14) */
 105     IA64_OPND_IMMU7a,   /* unsigned 7-bit immediate (bits 13-19) */
 106     IA64_OPND_IMMU7b,   /* unsigned 7-bit immediate (bits 20-26) */
 107     IA64_OPND_SOF,      /* 8-bit stack frame size */
 108     IA64_OPND_SOL,      /* 8-bit size of locals */
 109     IA64_OPND_SOR,      /* 6-bit number of rotating registers (scaled by 8) */
 110     IA64_OPND_IMM8,     /* signed 8-bit immediate (bits 13-19 & 36) */
 111     IA64_OPND_IMM8U4,   /* cmp4*u signed 8-bit immediate (bits 13-19 & 36) */
 112     IA64_OPND_IMM8M1,   /* signed 8-bit immediate -1 (bits 13-19 & 36) */
 113     IA64_OPND_IMM8M1U4, /* cmp4*u signed 8-bit immediate -1 (bits 13-19 & 36)*/
 114     IA64_OPND_IMM8M1U8, /* cmp*u signed 8-bit immediate -1 (bits 13-19 & 36) */
 115     IA64_OPND_IMMU9,    /* unsigned 9-bit immediate (bits 33-34, 20-26) */
 116     IA64_OPND_IMM9a,    /* signed 9-bit immediate (bits 6-12, 27, 36) */
 117     IA64_OPND_IMM9b,    /* signed 9-bit immediate (bits 13-19, 27, 36) */
 118     IA64_OPND_IMM14,    /* signed 14-bit immediate (bits 13-19, 27-32, 36) */
 119     IA64_OPND_IMM17,    /* signed 17-bit immediate (2*bits 6-12, 24-31, 36) */
 120     IA64_OPND_IMMU21,   /* unsigned 21-bit immediate (bits 6-25, 36) */
 121     IA64_OPND_IMM22,    /* signed 22-bit immediate (bits 13-19, 22-36) */
 122     IA64_OPND_IMMU24,   /* unsigned 24-bit immediate (bits 6-26, 31-32, 36) */
 123     IA64_OPND_IMM44,    /* signed 44-bit immediate (2^16*bits 6-32, 36) */
 124     IA64_OPND_IMMU62,   /* unsigned 62-bit immediate */
 125     IA64_OPND_IMMU64,   /* unsigned 64-bit immediate (lotsa bits...) */
 126     IA64_OPND_INC3,     /* signed 3-bit (bits 13-15): +/-1, 4, 8, 16 */
 127     IA64_OPND_LEN4,     /* 4-bit count (bits 27-30 + 1) */
 128     IA64_OPND_LEN6,     /* 6-bit count (bits 27-32 + 1) */
 129     IA64_OPND_MBTYPE4,  /* 4-bit mux type (bits 20-23) */
 130     IA64_OPND_MHTYPE8,  /* 8-bit mux type (bits 20-27) */
 131     IA64_OPND_POS6,     /* 6-bit count (bits 14-19) */
 132     IA64_OPND_TAG13,    /* signed 13-bit tag (ip + 16*bits 6-12, 33-34) */
 133     IA64_OPND_TAG13b,   /* signed 13-bit tag (ip + 16*bits 24-32) */
 134     IA64_OPND_TGT25,    /* signed 25-bit (ip + 16*bits 6-25, 36) */
 135     IA64_OPND_TGT25b,   /* signed 25-bit (ip + 16*bits 6-12, 20-32, 36) */
 136     IA64_OPND_TGT25c,   /* signed 25-bit (ip + 16*bits 13-32, 36) */
 137     IA64_OPND_TGT64,    /* 64-bit (ip + 16*bits 13-32, 36, 2-40(L)) */
 138     IA64_OPND_LDXMOV,   /* any symbol, generates R_IA64_LDXMOV.  */
 139
 140     IA64_OPND_COUNT     /* # of operand types (MUST BE LAST!) */
 141   };
 142
 143 enum ia64_dependency_mode
 144 {
 145   IA64_DV_RAW,
 146   IA64_DV_WAW,
 147   IA64_DV_WAR,
 148 };
 149
 150 enum ia64_dependency_semantics
 151 {
 152   IA64_DVS_NONE,
 153   IA64_DVS_IMPLIED,
 154   IA64_DVS_IMPLIEDF,
 155   IA64_DVS_DATA,
 156   IA64_DVS_INSTR,
 157   IA64_DVS_SPECIFIC,
 158   IA64_DVS_STOP,
 159   IA64_DVS_OTHER,
 160 };
 161
 162 enum ia64_resource_specifier
 163 {
 164   IA64_RS_ANY,
 165   IA64_RS_AR_K,
 166   IA64_RS_AR_UNAT,
 167   IA64_RS_AR, /* 8-15, 20, 22-23, 31, 33-35, 37-39, 41-43, 45-47, 67-111 */
 168   IA64_RS_ARb, /* 48-63, 112-127 */
 169   IA64_RS_BR,
 170   IA64_RS_CFM,
 171   IA64_RS_CPUID,
 172   IA64_RS_CR_IRR,
 173   IA64_RS_CR_LRR,
 174   IA64_RS_CR, /* 3-7,10-15,18,26-63,75-79,82-127 */
 175   IA64_RS_DBR,
 176   IA64_RS_FR,
 177   IA64_RS_FRb,
 178   IA64_RS_GR0,
 179   IA64_RS_GR,
 180   IA64_RS_IBR,
 181   IA64_RS_INSERVICE, /* CR[EOI] or CR[IVR] */
 182   IA64_RS_MSR,
 183   IA64_RS_PKR,
 184   IA64_RS_PMC,
 185   IA64_RS_PMD,
 186   IA64_RS_PR,  /* non-rotating, 1-15 */
 187   IA64_RS_PRr, /* rotating, 16-62 */
 188   IA64_RS_PR63,
 189   IA64_RS_RR,
 190
 191   IA64_RS_ARX, /* ARs not in RS_AR or RS_ARb */
 192   IA64_RS_CRX, /* CRs not in RS_CR */
 193   IA64_RS_PSR, /* PSR bits */
 194   IA64_RS_RSE, /* implementation-specific RSE resources */
 195   IA64_RS_AR_FPSR,
 196 };
 197
 198 enum ia64_rse_resource
 199 {
 200   IA64_RSE_N_STACKED_PHYS,
 201   IA64_RSE_BOF,
 202   IA64_RSE_STORE_REG,
 203   IA64_RSE_LOAD_REG,
 204   IA64_RSE_BSPLOAD,
 205   IA64_RSE_RNATBITINDEX,
 206   IA64_RSE_CFLE,
 207   IA64_RSE_NDIRTY,
 208 };
 209
 210 /* Information about a given resource dependency */
 211 struct ia64_dependency
 212 {
 213   /* Name of the resource */
 214   const char *name;
 215   /* Does this dependency need further specification? */
 216   enum ia64_resource_specifier specifier;
 217   /* Mode of dependency */
 218   enum ia64_dependency_mode mode;
 219   /* Dependency semantics */
 220   enum ia64_dependency_semantics semantics;
 221   /* Register index, if applicable (distinguishes AR, CR, and PSR deps) */
 222 #define REG_NONE (-1)
 223   int regindex;
 224   /* Special info on semantics */
 225   const char *info;
 226 };
 227
 228 /* Two arrays of indexes into the ia64_dependency table.
 229    chks are dependencies to check for conflicts when an opcode is
 230    encountered; regs are dependencies to register (mark as used) when an
 231    opcode is used.  chks correspond to readers (RAW) or writers (WAW or
 232    WAR) of a resource, while regs correspond to writers (RAW or WAW) and
 233    readers (WAR) of a resource.  */
 234 struct ia64_opcode_dependency
 235 {
 236   int nchks;
 237   const unsigned short *chks;
 238   int nregs;
 239   const unsigned short *regs;
 240 };
 241
 242 /* encode/extract the note/index for a dependency */
 243 #define RDEP(N,X) (((N)<<11)|(X))
 244 #define NOTE(X) (((X)>>11)&0x1F)
 245 #define DEP(X) ((X)&0x7FF)
 246
 247 /* A template descriptor describes the execution units that are active
 248    for each of the three slots.  It also specifies the location of
 249    instruction group boundaries that may be present between two slots.  */
 250 struct ia64_templ_desc
 251   {
 252     int group_boundary; /* 0=no boundary, 1=between slot 0 & 1, etc. */
 253     enum ia64_unit exec_unit[3];
 254     const char *name;
 255   };
 256
 257 /* The opcode table is an array of struct ia64_opcode.  */
 258
 259 struct ia64_opcode
 260   {
 261     /* The opcode name.  */
 262     const char *name;
 263
 264     /* The type of the instruction: */
 265     enum ia64_insn_type type;
 266
 267     /* Number of output operands: */
 268     int num_outputs;
 269
 270     /* The opcode itself.  Those bits which will be filled in with
 271        operands are zeroes.  */
 272     ia64_insn opcode;
 273
 274     /* The opcode mask.  This is used by the disassembler.  This is a
 275        mask containing ones indicating those bits which must match the
 276        opcode field, and zeroes indicating those bits which need not
 277        match (and are presumably filled in by operands).  */
 278     ia64_insn mask;
 279
 280     /* An array of operand codes.  Each code is an index into the
 281        operand table.  They appear in the order which the operands must
 282        appear in assembly code, and are terminated by a zero.  */
 283     enum ia64_opnd operands[5];
 284
 285     /* One bit flags for the opcode.  These are primarily used to
 286        indicate specific processors and environments support the
 287        instructions.  The defined values are listed below. */
 288     unsigned int flags;
 289
 290     /* Used by ia64_find_next_opcode (). */
 291     short ent_index;
 292
 293     /* Opcode dependencies. */
 294     const struct ia64_opcode_dependency *dependencies;
 295   };
 296
 297 /* Values defined for the flags field of a struct ia64_opcode.  */
 298
 299 #define IA64_OPCODE_FIRST       (1<<0)  /* must be first in an insn group */
 300 #define IA64_OPCODE_X_IN_MLX    (1<<1)  /* insn is allowed in X slot of MLX */
 301 #define IA64_OPCODE_LAST        (1<<2)  /* must be last in an insn group */
 302 #define IA64_OPCODE_PRIV        (1<<3)  /* privileged instruct */
 303 #define IA64_OPCODE_SLOT2       (1<<4)  /* insn allowed in slot 2 only */
 304 #define IA64_OPCODE_NO_PRED     (1<<5)  /* insn cannot be predicated */
 305 #define IA64_OPCODE_PSEUDO      (1<<6)  /* insn is a pseudo-op */
 306 #define IA64_OPCODE_F2_EQ_F3    (1<<7)  /* constraint: F2 == F3 */
 307 #define IA64_OPCODE_LEN_EQ_64MCNT       (1<<8)  /* constraint: LEN == 64-CNT */
 308 #define IA64_OPCODE_MOD_RRBS    (1<<9)  /* modifies all rrbs in CFM */
 309 #define IA64_OPCODE_POSTINC     (1<<10) /* postincrement MR3 operand */
 310
 311 /* A macro to extract the major opcode from an instruction.  */
 312 #define IA64_OP(i)      (((i) >> 37) & 0xf)
 313
 314 enum ia64_operand_class
 315   {
 316     IA64_OPND_CLASS_CST,        /* constant */
 317     IA64_OPND_CLASS_REG,        /* register */
 318     IA64_OPND_CLASS_IND,        /* indirect register */
 319     IA64_OPND_CLASS_ABS,        /* absolute value */
 320     IA64_OPND_CLASS_REL,        /* IP-relative value */
 321   };
 322
 323 /* The operands table is an array of struct ia64_operand.  */
 324
 325 struct ia64_operand
 326 {
 327   enum ia64_operand_class class;
 328
 329   /* Set VALUE as the operand bits for the operand of type SELF in the
 330      instruction pointed to by CODE.  If an error occurs, *CODE is not
 331      modified and the returned string describes the cause of the
 332      error.  If no error occurs, NULL is returned.  */
 333   const char *(*insert) (const struct ia64_operand *self, ia64_insn value,
 334                          ia64_insn *code);
 335
 336   /* Extract the operand bits for an operand of type SELF from
 337      instruction CODE store them in *VALUE.  If an error occurs, the
 338      cause of the error is described by the string returned.  If no
 339      error occurs, NULL is returned.  */
 340   const char *(*extract) (const struct ia64_operand *self, ia64_insn code,
 341                           ia64_insn *value);
 342
 343   /* A string whose meaning depends on the operand class.  */
 344
 345   const char *str;
 346
 347   struct bit_field
 348     {
 349       /* The number of bits in the operand.  */
 350       int bits;
 351
 352       /* How far the operand is left shifted in the instruction.  */
 353       int shift;
 354     }
 355   field[4];             /* no operand has more than this many bit-fields */
 356
 357   unsigned int flags;
 358
 359   const char *desc;     /* brief description */
 360 };
 361
 362 /* Values defined for the flags field of a struct ia64_operand.  */
 363
 364 /* Disassemble as signed decimal (instead of hex): */
 365 #define IA64_OPND_FLAG_DECIMAL_SIGNED   (1<<0)
 366 /* Disassemble as unsigned decimal (instead of hex): */
 367 #define IA64_OPND_FLAG_DECIMAL_UNSIGNED (1<<1)
 368
 369 extern const struct ia64_templ_desc ia64_templ_desc[16];
 370
 371 /* The tables are sorted by major opcode number and are otherwise in
 372    the order in which the disassembler should consider instructions.  */
 373 extern struct ia64_opcode ia64_opcodes_a[];
 374 extern struct ia64_opcode ia64_opcodes_i[];
 375 extern struct ia64_opcode ia64_opcodes_m[];
 376 extern struct ia64_opcode ia64_opcodes_b[];
 377 extern struct ia64_opcode ia64_opcodes_f[];
 378 extern struct ia64_opcode ia64_opcodes_d[];
 379
 380
 381 extern struct ia64_opcode *ia64_find_opcode (const char *name);
 382 extern struct ia64_opcode *ia64_find_next_opcode (struct ia64_opcode *ent);
 383
 384 extern struct ia64_opcode *ia64_dis_opcode (ia64_insn insn,
 385                                             enum ia64_insn_type type);
 386
 387 extern void ia64_free_opcode (struct ia64_opcode *ent);
 388 extern const struct ia64_dependency *ia64_find_dependency (int index);
 389
 390 /* To avoid circular library dependencies, this array is implemented
 391    in bfd/cpu-ia64-opc.c: */
 392 extern const struct ia64_operand elf64_ia64_operands[IA64_OPND_COUNT];
 393
 394 #endif /* opcode_ia64_h */