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merge from gcc
[binutils.git] / ld / testsuite / ld-frv / tls-relax-initial-shared-2.d
blob791189034dfec00775df380b0ab65882975ee2c5
1 #name: FRV TLS relocs with addends, shared linking with static TLS, relaxing
2 #source: tls-2.s
3 #as: --defsym static_tls=1
4 #objdump: -DR -j .text -j .got -j .plt
5 #ld: -shared tmpdir/tls-1-dep.so --version-script tls-1-shared.lds --relax
6
7 .*: file format elf.*frv.*
8
9 Disassembly of section \.text:
10
11 00000454 <_start>:
12 454: 92 c8 f0 34 ldi @\(gr15,52\),gr9
13 458: 92 c8 f0 44 ldi @\(gr15,68\),gr9
14 45c: 92 c8 f0 5c ldi @\(gr15,92\),gr9
15 460: 00 88 00 00 nop\.p
16 464: 80 88 00 00 nop
17 468: 92 c8 f0 7c ldi @\(gr15,124\),gr9
18 46c: 80 88 00 00 nop
19 470: 00 88 00 00 nop\.p
20 474: 80 88 00 00 nop
21 478: 92 c8 f0 84 ldi @\(gr15,132\),gr9
22 47c: 80 88 00 00 nop
23 480: 00 88 00 00 nop\.p
24 484: 80 88 00 00 nop
25 488: 92 c8 f0 94 ldi @\(gr15,148\),gr9
26 48c: 80 88 00 00 nop
27 490: 12 c8 f0 38 ldi\.p @\(gr15,56\),gr9
28 494: 80 88 00 00 nop
29 498: 80 88 00 00 nop
30 49c: 12 c8 f0 48 ldi\.p @\(gr15,72\),gr9
31 4a0: 80 88 00 00 nop
32 4a4: 80 88 00 00 nop
33 4a8: 12 c8 f0 60 ldi\.p @\(gr15,96\),gr9
34 4ac: 80 88 00 00 nop
35 4b0: 80 88 00 00 nop
36 4b4: 80 88 00 00 nop
37 4b8: 92 fc f8 14 setlos 0xf*fffff814,gr9
38 4bc: 80 88 00 00 nop
39 4c0: 92 fc 08 14 setlos 0x814,gr9
40 4c4: 92 f8 00 00 sethi hi\(0x0\),gr9
41 4c8: 92 f4 f8 14 setlo 0xf814,gr9
42 4cc: 92 c8 f0 64 ldi @\(gr15,100\),gr9
43 4d0: 92 c8 f0 0c ldi @\(gr15,12\),gr9
44 4d4: 92 c8 f0 1c ldi @\(gr15,28\),gr9
45 4d8: 00 88 00 00 nop\.p
46 4dc: 80 88 00 00 nop
47 4e0: 92 c8 f0 98 ldi @\(gr15,152\),gr9
48 4e4: 80 88 00 00 nop
49 4e8: 00 88 00 00 nop\.p
50 4ec: 80 88 00 00 nop
51 4f0: 92 c8 f0 6c ldi @\(gr15,108\),gr9
52 4f4: 80 88 00 00 nop
53 4f8: 00 88 00 00 nop\.p
54 4fc: 80 88 00 00 nop
55 500: 92 c8 f0 70 ldi @\(gr15,112\),gr9
56 504: 80 88 00 00 nop
57 508: 12 c8 f0 68 ldi\.p @\(gr15,104\),gr9
58 50c: 80 88 00 00 nop
59 510: 80 88 00 00 nop
60 514: 12 c8 f0 10 ldi\.p @\(gr15,16\),gr9
61 518: 80 88 00 00 nop
62 51c: 80 88 00 00 nop
63 520: 12 c8 f0 20 ldi\.p @\(gr15,32\),gr9
64 524: 80 88 00 00 nop
65 528: 80 88 00 00 nop
66 52c: 80 88 00 00 nop
67 530: 92 fc f8 24 setlos 0xf*fffff824,gr9
68 534: 80 88 00 00 nop
69 538: 92 fc 08 24 setlos 0x824,gr9
70 53c: 92 f8 00 00 sethi hi\(0x0\),gr9
71 540: 92 f4 f8 24 setlo 0xf824,gr9
72 544: 92 c8 f0 28 ldi @\(gr15,40\),gr9
73 548: 92 c8 f0 4c ldi @\(gr15,76\),gr9
74 54c: 92 c8 f0 50 ldi @\(gr15,80\),gr9
75 550: 00 88 00 00 nop\.p
76 554: 80 88 00 00 nop
77 558: 92 c8 f0 74 ldi @\(gr15,116\),gr9
78 55c: 80 88 00 00 nop
79 560: 00 88 00 00 nop\.p
80 564: 80 88 00 00 nop
81 568: 92 c8 f0 88 ldi @\(gr15,136\),gr9
82 56c: 80 88 00 00 nop
83 570: 00 88 00 00 nop\.p
84 574: 80 88 00 00 nop
85 578: 92 c8 f0 8c ldi @\(gr15,140\),gr9
86 57c: 80 88 00 00 nop
87 580: 12 c8 f0 2c ldi\.p @\(gr15,44\),gr9
88 584: 80 88 00 00 nop
89 588: 80 88 00 00 nop
90 58c: 12 c8 f0 3c ldi\.p @\(gr15,60\),gr9
91 590: 80 88 00 00 nop
92 594: 80 88 00 00 nop
93 598: 12 c8 f0 54 ldi\.p @\(gr15,84\),gr9
94 59c: 80 88 00 00 nop
95 5a0: 80 88 00 00 nop
96 5a4: 80 88 00 00 nop
97 5a8: 92 fc 00 04 setlos 0x4,gr9
98 5ac: 80 88 00 00 nop
99 5b0: 92 fc 10 04 setlos 0x1004,gr9
100 5b4: 92 f8 00 01 sethi 0x1,gr9
101 5b8: 92 f4 00 04 setlo 0x4,gr9
102 5bc: 92 c8 f0 30 ldi @\(gr15,48\),gr9
103 5c0: 92 c8 f0 40 ldi @\(gr15,64\),gr9
104 5c4: 92 c8 f0 58 ldi @\(gr15,88\),gr9
105 5c8: 00 88 00 00 nop\.p
106 5cc: 80 88 00 00 nop
107 5d0: 92 c8 f0 78 ldi @\(gr15,120\),gr9
108 5d4: 80 88 00 00 nop
109 5d8: 00 88 00 00 nop\.p
110 5dc: 80 88 00 00 nop
111 5e0: 92 c8 f0 80 ldi @\(gr15,128\),gr9
112 5e4: 80 88 00 00 nop
113 5e8: 00 88 00 00 nop\.p
114 5ec: 80 88 00 00 nop
115 5f0: 92 c8 f0 90 ldi @\(gr15,144\),gr9
116 5f4: 80 88 00 00 nop
117 5f8: 12 c8 f0 14 ldi\.p @\(gr15,20\),gr9
118 5fc: 80 88 00 00 nop
119 600: 80 88 00 00 nop
120 604: 12 c8 f0 18 ldi\.p @\(gr15,24\),gr9
121 608: 80 88 00 00 nop
122 60c: 80 88 00 00 nop
123 610: 12 c8 f0 24 ldi\.p @\(gr15,36\),gr9
124 614: 80 88 00 00 nop
125 618: 80 88 00 00 nop
126 61c: 92 c8 f0 34 ldi @\(gr15,52\),gr9
127 620: 92 c8 f0 5c ldi @\(gr15,92\),gr9
128 624: 92 c8 f0 64 ldi @\(gr15,100\),gr9
129 628: 92 c8 f0 1c ldi @\(gr15,28\),gr9
130 62c: 92 c8 f0 28 ldi @\(gr15,40\),gr9
131 630: 92 c8 f0 50 ldi @\(gr15,80\),gr9
132 634: 92 c8 f0 30 ldi @\(gr15,48\),gr9
133 638: 92 c8 f0 58 ldi @\(gr15,88\),gr9
134 63c: 80 88 00 00 nop
135 640: 92 c8 f0 44 ldi @\(gr15,68\),gr9
136 644: 80 88 00 00 nop
137 648: 80 88 00 00 nop
138 64c: 92 c8 f0 0c ldi @\(gr15,12\),gr9
139 Disassembly of section \.got:
140
141 000046e8 <_GLOBAL_OFFSET_TABLE_>:
142 \.\.\.
143 46f4: 00 00 10 11 add\.p sp,gr17,gr0
144 46f4: R_FRV_TLSOFF \.tbss
145 46f8: 00 00 10 13 add\.p sp,gr19,gr0
146 46f8: R_FRV_TLSOFF \.tbss
147 46fc: 00 00 00 03 add\.p gr0,gr3,gr0
148 46fc: R_FRV_TLSOFF x
149 4700: 00 00 10 03 add\.p sp,gr3,gr0
150 4700: R_FRV_TLSOFF x
151 4704: 00 01 00 11 add\.p gr16,gr17,gr0
152 4704: R_FRV_TLSOFF \.tbss
153 4708: 00 01 00 13 add\.p gr16,gr19,gr0
154 4708: R_FRV_TLSOFF \.tbss
155 470c: 00 01 00 03 add\.p gr16,gr3,gr0
156 470c: R_FRV_TLSOFF x
157 4710: 00 00 07 f1 \*unknown\*
158 4710: R_FRV_TLSOFF \.tbss
159 4714: 00 00 07 f3 \*unknown\*
160 4714: R_FRV_TLSOFF \.tbss
161 4718: 00 00 00 01 add\.p gr0,sp,gr0
162 4718: R_FRV_TLSOFF x
163 471c: 00 00 00 01 add\.p gr0,sp,gr0
164 471c: R_FRV_TLSOFF \.tbss
165 4720: 00 00 00 03 add\.p gr0,gr3,gr0
166 4720: R_FRV_TLSOFF \.tbss
167 4724: 00 00 17 f3 \*unknown\*
168 4724: R_FRV_TLSOFF \.tbss
169 4728: 00 00 10 01 add\.p sp,sp,gr0
170 4728: R_FRV_TLSOFF x
171 472c: 00 00 10 01 add\.p sp,sp,gr0
172 472c: R_FRV_TLSOFF \.tbss
173 4730: 00 00 10 03 add\.p sp,gr3,gr0
174 4730: R_FRV_TLSOFF \.tbss
175 4734: 00 00 17 f1 \*unknown\*
176 4734: R_FRV_TLSOFF \.tbss
177 4738: 00 01 07 f1 \*unknown\*
178 4738: R_FRV_TLSOFF \.tbss
179 473c: 00 01 07 f3 \*unknown\*
180 473c: R_FRV_TLSOFF \.tbss
181 4740: 00 01 00 01 add\.p gr16,sp,gr0
182 4740: R_FRV_TLSOFF x
183 4744: 00 01 00 01 add\.p gr16,sp,gr0
184 4744: R_FRV_TLSOFF \.tbss
185 4748: 00 01 00 03 add\.p gr16,gr3,gr0
186 4748: R_FRV_TLSOFF \.tbss
187 474c: 00 00 00 11 add\.p gr0,gr17,gr0
188 474c: R_FRV_TLSOFF \.tbss
189 4750: 00 00 00 13 add\.p gr0,gr19,gr0
190 4750: R_FRV_TLSOFF \.tbss
191 4754: 00 00 10 12 add\.p sp,gr18,gr0
192 4754: R_FRV_TLSOFF \.tbss
193 4758: 00 01 00 12 add\.p gr16,gr18,gr0
194 4758: R_FRV_TLSOFF \.tbss
195 475c: 00 00 07 f2 \*unknown\*
196 475c: R_FRV_TLSOFF \.tbss
197 4760: 00 00 00 02 add\.p gr0,fp,gr0
198 4760: R_FRV_TLSOFF x
199 4764: 00 00 00 02 add\.p gr0,fp,gr0
200 4764: R_FRV_TLSOFF \.tbss
201 4768: 00 00 10 02 add\.p sp,fp,gr0
202 4768: R_FRV_TLSOFF x
203 476c: 00 00 10 02 add\.p sp,fp,gr0
204 476c: R_FRV_TLSOFF \.tbss
205 4770: 00 00 17 f2 \*unknown\*
206 4770: R_FRV_TLSOFF \.tbss
207 4774: 00 01 07 f2 \*unknown\*
208 4774: R_FRV_TLSOFF \.tbss
209 4778: 00 01 00 02 add\.p gr16,fp,gr0
210 4778: R_FRV_TLSOFF x
211 477c: 00 01 00 02 add\.p gr16,fp,gr0
212 477c: R_FRV_TLSOFF \.tbss
213 4780: 00 00 00 12 add\.p gr0,gr18,gr0
214 4780: R_FRV_TLSOFF \.tbss
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