ld/testsuite/ld-spu/ovl.d

   1 #source: ovl.s
   2 #ld: -N -T ovl.lnk
   3 #objdump: -D
   4
   5 .*elf32-spu
   6
   7 Disassembly of section \.text:
   8
   9 00000100 <_start>:
  10  100:   1c f8 00 81     ai      \$1,\$1,-32
  11  104:   48 20 00 00     xor     \$0,\$0,\$0
  12  108:   24 00 00 80     stqd    \$0,0\(\$1\)
  13  10c:   24 00 40 80     stqd    \$0,16\(\$1\)
  14  110:   33 00 04 00     brsl    \$0,130 <f0\+0x4>       # 130
  15  114:   33 00 04 80     brsl    \$0,138 <f0\+0xc>       # 138
  16  118:   33 00 07 00     brsl    \$0,150 <f0\+0x24>      # 150
  17  11c:   42 00 ac 09     ila     \$9,344 # 158
  18  120:   35 20 04 80     bisl    \$0,\$9
  19  124:   1c 08 00 81     ai      \$1,\$1,32      # 20
  20  128:   32 7f fb 00     br      100 <_start>    # 100
  21
  22 0000012c <f0>:
  23  12c:   35 00 00 00     bi      \$0
  24  130:   42 02 00 4f     ila     \$79,1024       # 400
  25  134:   32 00 02 80     br      148 <f0\+0x1c>  # 148
  26  138:   42 02 02 4f     ila     \$79,1028       # 404
  27  13c:   32 00 01 80     br      148 <f0\+0x1c>  # 148
  28  140:   42 02 08 4f     ila     \$79,1040       # 410
  29  144:   40 20 00 00     nop     \$0
  30  148:   42 00 00 ce     ila     \$78,1
  31  14c:   32 00 0a 80     br      1a0 <__ovly_load>       # 1a0
  32  150:   42 02 00 4f     ila     \$79,1024       # 400
  33  154:   32 00 02 80     br      168 <f0\+0x3c>  # 168
  34  158:   42 02 12 4f     ila     \$79,1060       # 424
  35  15c:   32 00 01 80     br      168 <f0\+0x3c>  # 168
  36  160:   42 02 1a 4f     ila     \$79,1076       # 434
  37  164:   40 20 00 00     nop     \$0
  38  168:   42 00 01 4e     ila     \$78,2
  39  16c:   32 00 06 80     br      1a0 <__ovly_load>       # 1a0
  40 #...
  41 [0-9a-f]+ <__ovly_return>:
  42 [0-9a-f ]+:     3f e1 00 4e     shlqbyi \$78,\$0,4
  43 [0-9a-f ]+:     3f e2 00 4f     shlqbyi \$79,\$0,8
  44 [0-9a-f ]+:     25 00 27 ce     biz     \$78,\$79
  45
  46 [0-9a-f]+ <__ovly_load>:
  47 #...
  48 [0-9a-f]+ <_ovly_debug_event>:
  49 #...
  50 Disassembly of section \.ov_a1:
  51
  52 00000400 <f1_a1>:
  53  400:   32 00 01 80     br      40c <f3_a1>     # 40c
  54
  55 00000404 <f2_a1>:
  56  404:   42 00 a0 03     ila     \$3,320 # 140
  57  408:   35 00 00 00     bi      \$0
  58
  59 0000040c <f3_a1>:
  60  40c:   35 00 00 00     bi      \$0
  61
  62 00000410 <f4_a1>:
  63  410:   35 00 00 00     bi      \$0
  64         \.\.\.
  65 Disassembly of section \.ov_a2:
  66
  67 00000400 <f1_a2>:
  68  400:   24 00 40 80     stqd    \$0,16\(\$1\)
  69  404:   24 ff 80 81     stqd    \$1,-32\(\$1\)
  70  408:   1c f8 00 81     ai      \$1,\$1,-32
  71  40c:   33 7f a4 00     brsl    \$0,12c <f0>    # 12c
  72  410:   33 7f a4 00     brsl    \$0,130 <f0\+0x4>       # 130
  73  414:   33 00 03 80     brsl    \$0,430 <f3_a2> # 430
  74  418:   34 00 c0 80     lqd     \$0,48\(\$1\)   # 30
  75  41c:   1c 08 00 81     ai      \$1,\$1,32      # 20
  76  420:   35 00 00 00     bi      \$0
  77
  78 00000424 <f2_a2>:
  79  424:   41 00 00 03     ilhu    \$3,0
  80  428:   60 80 b0 03     iohl    \$3,352 # 160
  81  42c:   35 00 00 00     bi      \$0
  82
  83 00000430 <f3_a2>:
  84  430:   35 00 00 00     bi      \$0
  85
  86 00000434 <f4_a2>:
  87  434:   35 00 00 00     bi      \$0
  88         \.\.\.
  89 Disassembly of section .data:
  90
  91 00000440 <_ovly_table>:
  92  440:   00 00 04 00 .*
  93  444:   00 00 00 20 .*
  94  448:   00 00 02 e0 .*
  95  44c:   00 00 00 01 .*
  96  450:   00 00 04 00 .*
  97  454:   00 00 00 40 .*
  98  458:   00 00 03 00 .*
  99  45c:   00 00 00 01 .*
 100
 101 00000460 <_ovly_buf_table>:
 102  460:   00 00 00 00 .*
 103 Disassembly of section \.toe:
 104
 105 00000470 <_EAR_>:
 106         \.\.\.
 107 Disassembly of section \.note\.spu_name:
 108
 109 .* <\.note\.spu_name>:
 110 .*:     00 00 00 08 .*
 111 .*:     00 00 00 0c .*
 112 .*:     00 00 00 01 .*
 113 .*:     53 50 55 4e .*
 114 .*:     41 4d 45 00 .*
 115 .*:     74 6d 70 64 .*
 116 .*:     69 72 2f 64 .*
 117 .*:     75 6d 70 00 .*