ld/testsuite/ld-frv/fdpic-pie-6.d

   1 #name: FRV uClinux PIC relocs to weak undefined symbols, pie linking
   2 #source: fdpic6.s
   3 #objdump: -DR -j .text -j .data -j .got -j .plt
   4 #ld: -pie --defsym WD1=D6
   5
   6 .*:     file format elf.*frv.*
   7
   8 Disassembly of section \.plt:
   9
  10 [0-9a-f ]+<\.plt>:
  11 [0-9a-f ]+:     00 00 00 08     add\.p gr0,gr8,gr0
  12 [0-9a-f ]+:     c0 1a 00 06     bra [0-9a-f]+ <F6-0x10>
  13 [0-9a-f ]+:     00 00 00 00     add\.p gr0,gr0,gr0
  14 [0-9a-f ]+:     c0 1a 00 04     bra [0-9a-f]+ <F6-0x10>
  15 [0-9a-f ]+:     00 00 00 10     add\.p gr0,gr16,gr0
  16 [0-9a-f ]+:     c0 1a 00 02     bra [0-9a-f]+ <F6-0x10>
  17 [0-9a-f ]+:     00 00 00 18     add\.p gr0,gr24,gr0
  18 [0-9a-f ]+:     88 08 f1 40     ldd @\(gr15,gr0\),gr4
  19 [0-9a-f ]+:     80 30 40 00     jmpl @\(gr4,gr0\)
  20 [0-9a-f ]+:     9c cc ff f0     lddi @\(gr15,-16\),gr14
  21 [0-9a-f ]+:     80 30 e0 00     jmpl @\(gr14,gr0\)
  22 Disassembly of section \.text:
  23
  24 [0-9a-f ]+<F6>:
  25 [0-9a-f ]+:     fe 3f ff fe     call [0-9a-f]+ <F6-0x8>
  26 [0-9a-f ]+:     80 40 f0 0c     addi gr15,12,gr0
  27 [0-9a-f ]+:     80 fc 00 24     setlos 0x24,gr0
  28 [0-9a-f ]+:     80 f4 00 20     setlo 0x20,gr0
  29 [0-9a-f ]+:     80 f8 00 00     sethi hi\(0x0\),gr0
  30 [0-9a-f ]+:     80 40 f0 10     addi gr15,16,gr0
  31 [0-9a-f ]+:     80 fc 00 18     setlos 0x18,gr0
  32 [0-9a-f ]+:     80 f4 00 1c     setlo 0x1c,gr0
  33 [0-9a-f ]+:     80 f8 00 00     sethi hi\(0x0\),gr0
  34 [0-9a-f ]+:     80 40 ff f8     addi gr15,-8,gr0
  35 [0-9a-f ]+:     80 fc ff e8     setlos 0xf*ffffffe8,gr0
  36 [0-9a-f ]+:     80 f4 ff e0     setlo 0xffe0,gr0
  37 [0-9a-f ]+:     80 f8 ff ff     sethi 0xffff,gr0
  38 [0-9a-f ]+:     80 f4 ff d0     setlo 0xffd0,gr0
  39 [0-9a-f ]+:     80 f8 ff ff     sethi 0xffff,gr0
  40 [0-9a-f ]+:     80 f4 00 14     setlo 0x14,gr0
  41 [0-9a-f ]+:     80 f8 00 00     sethi hi\(0x0\),gr0
  42 Disassembly of section \.dat[0-9a-f ]+:
  43
  44 [0-9a-f ]+<D6>:
  45         \.\.\.
  46 [0-9a-f  ]+: R_FRV_32   WD0
  47 [0-9a-f  ]+: R_FRV_FUNCDESC     WFb
  48 [0-9a-f  ]+: R_FRV_32   WFb
  49 Disassembly of section \.got:
  50
  51 [0-9a-f ]+<_GLOBAL_OFFSET_TABLE_-0x20>:
  52 [0-9a-f ]+:     00 00 04 b8     .*
  53 [0-9a-f  ]+: R_FRV_FUNCDESC_VALUE       WF9
  54 [0-9a-f ]+:     00 00 00 02     .*
  55 [0-9a-f ]+:     00 00 04 b0     .*
  56 [0-9a-f  ]+: R_FRV_FUNCDESC_VALUE       WF8
  57 [0-9a-f ]+:     00 00 00 02     .*
  58 [0-9a-f ]+:     00 00 04 a8     .*
  59 [0-9a-f  ]+: R_FRV_FUNCDESC_VALUE       WF0
  60 [0-9a-f ]+:     00 00 00 02     .*
  61 [0-9a-f ]+:     00 00 04 a0     .*
  62 [0-9a-f  ]+: R_FRV_FUNCDESC_VALUE       WF7
  63 [0-9a-f ]+:     00 00 00 02     .*
  64
  65 [0-9a-f ]+<_GLOBAL_OFFSET_TABLE_>:
  66         \.\.\.
  67 [0-9a-f  ]+: R_FRV_32   WF1
  68 [0-9a-f  ]+: R_FRV_FUNCDESC     WF4
  69 [0-9a-f  ]+: R_FRV_32   WD2
  70 [0-9a-f  ]+: R_FRV_FUNCDESC     WF5
  71 [0-9a-f  ]+: R_FRV_FUNCDESC     WF6
  72 [0-9a-f  ]+: R_FRV_32   WF3
  73 [0-9a-f  ]+: R_FRV_32   WF2