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* configure.in (TOPLEVEL_CONFIGURE_ARGUMENTS, baseargs): Fix
[binutils.git] / gas / config / tc-m68k.c
blob5ad330691e14f25fe0bcd9a3bdf1d8a43951264d
1 /* tc-m68k.c -- Assemble for the m68k family
2 Copyright 1987, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005, 2006 Free Software Foundation, Inc.
4
5 This file is part of GAS, the GNU Assembler.
6
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
10 any later version.
11
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to the Free
19 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
20 02110-1301, USA. */
21
22 #include "as.h"
23 #include "safe-ctype.h"
24 #include "obstack.h"
25 #include "subsegs.h"
26 #include "dwarf2dbg.h"
27 #include "dw2gencfi.h"
28
29 #include "opcode/m68k.h"
30 #include "m68k-parse.h"
31
32 #if defined (OBJ_ELF)
33 #include "elf/m68k.h"
34 #endif
35
36 #ifdef M68KCOFF
37 #include "obj-coff.h"
38 #endif
39
40 /* This string holds the chars that always start a comment. If the
41 pre-processor is disabled, these aren't very useful. The macro
42 tc_comment_chars points to this. We use this, rather than the
43 usual comment_chars, so that the --bitwise-or option will work. */
44 #if defined (TE_SVR4) || defined (TE_DELTA)
45 const char *m68k_comment_chars = "|#";
46 #else
47 const char *m68k_comment_chars = "|";
48 #endif
49
50 /* This array holds the chars that only start a comment at the beginning of
51 a line. If the line seems to have the form '# 123 filename'
52 .line and .file directives will appear in the pre-processed output */
53 /* Note that input_file.c hand checks for '#' at the beginning of the
54 first line of the input file. This is because the compiler outputs
55 #NO_APP at the beginning of its output. */
56 /* Also note that comments like this one will always work. */
57 const char line_comment_chars[] = "#*";
58
59 const char line_separator_chars[] = ";";
60
61 /* Chars that can be used to separate mant from exp in floating point nums. */
62 const char EXP_CHARS[] = "eE";
63
64 /* Chars that mean this number is a floating point constant, as
65 in "0f12.456" or "0d1.2345e12". */
66
67 const char FLT_CHARS[] = "rRsSfFdDxXeEpP";
68
69 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
70 changed in read.c . Ideally it shouldn't have to know about it at all,
71 but nothing is ideal around here. */
72
73 /* Are we trying to generate PIC code? If so, absolute references
74 ought to be made into linkage table references or pc-relative
75 references. Not implemented. For ELF there are other means
76 to denote pic relocations. */
77 int flag_want_pic;
78
79 static int flag_short_refs; /* -l option. */
80 static int flag_long_jumps; /* -S option. */
81 static int flag_keep_pcrel; /* --pcrel option. */
82
83 #ifdef REGISTER_PREFIX_OPTIONAL
84 int flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
85 #else
86 int flag_reg_prefix_optional;
87 #endif
88
89 /* Whether --register-prefix-optional was used on the command line. */
90 static int reg_prefix_optional_seen;
91
92 /* The floating point coprocessor to use by default. */
93 static enum m68k_register m68k_float_copnum = COP1;
94
95 /* If this is non-zero, then references to number(%pc) will be taken
96 to refer to number, rather than to %pc + number. */
97 static int m68k_abspcadd;
98
99 /* If this is non-zero, then the quick forms of the move, add, and sub
100 instructions are used when possible. */
101 static int m68k_quick = 1;
102
103 /* If this is non-zero, then if the size is not specified for a base
104 or outer displacement, the assembler assumes that the size should
105 be 32 bits. */
106 static int m68k_rel32 = 1;
107
108 /* This is non-zero if m68k_rel32 was set from the command line. */
109 static int m68k_rel32_from_cmdline;
110
111 /* The default width to use for an index register when using a base
112 displacement. */
113 static enum m68k_size m68k_index_width_default = SIZE_LONG;
114
115 /* We want to warn if any text labels are misaligned. In order to get
116 the right line number, we need to record the line number for each
117 label. */
118 struct label_line
119 {
120 struct label_line *next;
121 symbolS *label;
122 char *file;
123 unsigned int line;
124 int text;
125 };
126
127 /* The list of labels. */
128
129 static struct label_line *labels;
130
131 /* The current label. */
132
133 static struct label_line *current_label;
134
135 /* Pointer to list holding the opcodes sorted by name. */
136 static struct m68k_opcode const ** m68k_sorted_opcodes;
137
138 /* Its an arbitrary name: This means I don't approve of it.
139 See flames below. */
140 static struct obstack robyn;
141
142 struct m68k_incant
143 {
144 const char *m_operands;
145 unsigned long m_opcode;
146 short m_opnum;
147 short m_codenum;
148 int m_arch;
149 struct m68k_incant *m_next;
150 };
151
152 #define getone(x) ((((x)->m_opcode)>>16)&0xffff)
153 #define gettwo(x) (((x)->m_opcode)&0xffff)
154
155 static const enum m68k_register m68000_ctrl[] = { 0 };
156 static const enum m68k_register m68010_ctrl[] = {
157 SFC, DFC, USP, VBR,
158 0
159 };
160 static const enum m68k_register m68020_ctrl[] = {
161 SFC, DFC, USP, VBR, CACR, CAAR, MSP, ISP,
162 0
163 };
164 static const enum m68k_register m68040_ctrl[] = {
165 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1,
166 USP, VBR, MSP, ISP, MMUSR, URP, SRP,
167 0
168 };
169 static const enum m68k_register m68060_ctrl[] = {
170 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1, BUSCR,
171 USP, VBR, URP, SRP, PCR,
172 0
173 };
174 static const enum m68k_register mcf_ctrl[] = {
175 CACR, TC, ACR0, ACR1, ACR2, ACR3, VBR, ROMBAR,
176 RAMBAR0, RAMBAR1, MBAR,
177 0
178 };
179 static const enum m68k_register mcf5208_ctrl[] = {
180 CACR, ACR0, ACR1, VBR, RAMBAR1,
181 0
182 };
183 static const enum m68k_register mcf5213_ctrl[] = {
184 VBR, RAMBAR, FLASHBAR,
185 0
186 };
187 static const enum m68k_register mcf5216_ctrl[] = {
188 VBR, CACR, ACR0, ACR1, FLASHBAR, RAMBAR,
189 0
190 };
191 static const enum m68k_register mcf52235_ctrl[] = {
192 VBR, FLASHBAR, RAMBAR,
193 0
194 };
195 static const enum m68k_register mcf5225_ctrl[] = {
196 VBR, CACR, ACR0, ACR1, FLASHBAR, RAMBAR, MBAR,
197 0
198 };
199 static const enum m68k_register mcf5235_ctrl[] = {
200 VBR, CACR, ACR0, ACR1, RAMBAR,
201 0
202 };
203 static const enum m68k_register mcf5249_ctrl[] = {
204 VBR, CACR, ACR0, ACR1, RAMBAR0, RAMBAR1, MBAR, MBAR2,
205 0
206 };
207 static const enum m68k_register mcf5250_ctrl[] = {
208 VBR,
209 0
210 };
211 static const enum m68k_register mcf5271_ctrl[] = {
212 VBR, CACR, ACR0, ACR1, RAMBAR,
213 0
214 };
215 static const enum m68k_register mcf5272_ctrl[] = {
216 VBR, CACR, ACR0, ACR1, ROMBAR, RAMBAR, MBAR,
217 0
218 };
219 static const enum m68k_register mcf5275_ctrl[] = {
220 VBR, CACR, ACR0, ACR1, RAMBAR,
221 0
222 };
223 static const enum m68k_register mcf5282_ctrl[] = {
224 VBR, CACR, ACR0, ACR1, FLASHBAR, RAMBAR,
225 0
226 };
227 static const enum m68k_register mcf5329_ctrl[] = {
228 VBR, CACR, ACR0, ACR1, RAMBAR,
229 0
230 };
231 static const enum m68k_register mcf5373_ctrl[] = {
232 VBR, CACR, ACR0, ACR1, RAMBAR,
233 0
234 };
235 static const enum m68k_register mcfv4e_ctrl[] = {
236 CACR, TC, ITT0, ITT1, DTT0, DTT1, BUSCR, VBR, PC, ROMBAR,
237 ROMBAR1, RAMBAR0, RAMBAR1, MPCR, EDRAMBAR, SECMBAR, MBAR, MBAR0, MBAR1,
238 PCR1U0, PCR1L0, PCR1U1, PCR1L1, PCR2U0, PCR2L0, PCR2U1, PCR2L1,
239 PCR3U0, PCR3L0, PCR3U1, PCR3L1,
240 0
241 };
242 #define cpu32_ctrl m68010_ctrl
243
244 static const enum m68k_register *control_regs;
245
246 /* Internal form of a 68020 instruction. */
247 struct m68k_it
248 {
249 const char *error;
250 const char *args; /* List of opcode info. */
251 int numargs;
252
253 int numo; /* Number of shorts in opcode. */
254 short opcode[11];
255
256 struct m68k_op operands[6];
257
258 int nexp; /* Number of exprs in use. */
259 struct m68k_exp exprs[4];
260
261 int nfrag; /* Number of frags we have to produce. */
262 struct
263 {
264 int fragoff; /* Where in the current opcode the frag ends. */
265 symbolS *fadd;
266 offsetT foff;
267 int fragty;
268 }
269 fragb[4];
270
271 int nrel; /* Num of reloc strucs in use. */
272 struct
273 {
274 int n;
275 expressionS exp;
276 char wid;
277 char pcrel;
278 /* In a pc relative address the difference between the address
279 of the offset and the address that the offset is relative
280 to. This depends on the addressing mode. Basically this
281 is the value to put in the offset field to address the
282 first byte of the offset, without regarding the special
283 significance of some values (in the branch instruction, for
284 example). */
285 int pcrel_fix;
286 #ifdef OBJ_ELF
287 /* Whether this expression needs special pic relocation, and if
288 so, which. */
289 enum pic_relocation pic_reloc;
290 #endif
291 }
292 reloc[5]; /* Five is enough??? */
293 };
294
295 #define cpu_of_arch(x) ((x) & (m68000up | mcfisa_a))
296 #define float_of_arch(x) ((x) & mfloat)
297 #define mmu_of_arch(x) ((x) & mmmu)
298 #define arch_coldfire_p(x) ((x) & mcfisa_a)
299 #define arch_coldfire_fpu(x) ((x) & cfloat)
300
301 /* Macros for determining if cpu supports a specific addressing mode. */
302 #define HAVE_LONG_BRANCH(x) ((x) & (m68020|m68030|m68040|m68060|cpu32|mcfisa_b))
303
304 static struct m68k_it the_ins; /* The instruction being assembled. */
305
306 #define op(ex) ((ex)->exp.X_op)
307 #define adds(ex) ((ex)->exp.X_add_symbol)
308 #define subs(ex) ((ex)->exp.X_op_symbol)
309 #define offs(ex) ((ex)->exp.X_add_number)
310
311 /* Macros for adding things to the m68k_it struct. */
312 #define addword(w) (the_ins.opcode[the_ins.numo++] = (w))
313
314 /* Like addword, but goes BEFORE general operands. */
315
316 static void
317 insop (int w, const struct m68k_incant *opcode)
318 {
319 int z;
320 for (z = the_ins.numo; z > opcode->m_codenum; --z)
321 the_ins.opcode[z] = the_ins.opcode[z - 1];
322 for (z = 0; z < the_ins.nrel; z++)
323 the_ins.reloc[z].n += 2;
324 for (z = 0; z < the_ins.nfrag; z++)
325 the_ins.fragb[z].fragoff++;
326 the_ins.opcode[opcode->m_codenum] = w;
327 the_ins.numo++;
328 }
329
330 /* The numo+1 kludge is so we can hit the low order byte of the prev word.
331 Blecch. */
332 static void
333 add_fix (int width, struct m68k_exp *exp, int pc_rel, int pc_fix)
334 {
335 the_ins.reloc[the_ins.nrel].n = (width == 'B' || width == '3'
336 ? the_ins.numo * 2 - 1
337 : (width == 'b'
338 ? the_ins.numo * 2 + 1
339 : the_ins.numo * 2));
340 the_ins.reloc[the_ins.nrel].exp = exp->exp;
341 the_ins.reloc[the_ins.nrel].wid = width;
342 the_ins.reloc[the_ins.nrel].pcrel_fix = pc_fix;
343 #ifdef OBJ_ELF
344 the_ins.reloc[the_ins.nrel].pic_reloc = exp->pic_reloc;
345 #endif
346 the_ins.reloc[the_ins.nrel++].pcrel = pc_rel;
347 }
348
349 /* Cause an extra frag to be generated here, inserting up to 10 bytes
350 (that value is chosen in the frag_var call in md_assemble). TYPE
351 is the subtype of the frag to be generated; its primary type is
352 rs_machine_dependent.
353
354 The TYPE parameter is also used by md_convert_frag_1 and
355 md_estimate_size_before_relax. The appropriate type of fixup will
356 be emitted by md_convert_frag_1.
357
358 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
359 static void
360 add_frag (symbolS *add, offsetT off, int type)
361 {
362 the_ins.fragb[the_ins.nfrag].fragoff = the_ins.numo;
363 the_ins.fragb[the_ins.nfrag].fadd = add;
364 the_ins.fragb[the_ins.nfrag].foff = off;
365 the_ins.fragb[the_ins.nfrag++].fragty = type;
366 }
367
368 #define isvar(ex) \
369 (op (ex) != O_constant && op (ex) != O_big)
370
371 static char *crack_operand (char *str, struct m68k_op *opP);
372 static int get_num (struct m68k_exp *exp, int ok);
373 static int reverse_16_bits (int in);
374 static int reverse_8_bits (int in);
375 static void install_gen_operand (int mode, int val);
376 static void install_operand (int mode, int val);
377 static void s_bss (int);
378 static void s_data1 (int);
379 static void s_data2 (int);
380 static void s_even (int);
381 static void s_proc (int);
382 static void s_chip (int);
383 static void s_fopt (int);
384 static void s_opt (int);
385 static void s_reg (int);
386 static void s_restore (int);
387 static void s_save (int);
388 static void s_mri_if (int);
389 static void s_mri_else (int);
390 static void s_mri_endi (int);
391 static void s_mri_break (int);
392 static void s_mri_next (int);
393 static void s_mri_for (int);
394 static void s_mri_endf (int);
395 static void s_mri_repeat (int);
396 static void s_mri_until (int);
397 static void s_mri_while (int);
398 static void s_mri_endw (int);
399 static void s_m68k_cpu (int);
400 static void s_m68k_arch (int);
401
402 struct m68k_cpu
403 {
404 unsigned long arch; /* Architecture features. */
405 const enum m68k_register *control_regs; /* Control regs on chip */
406 const char *name; /* Name */
407 int alias; /* Alias for a cannonical name. If 1, then
408 succeeds canonical name, if -1 then
409 succeeds canonical name, if <-1 ||>1 this is a
410 deprecated name, and the next/previous name
411 should be used. */
412 };
413
414 /* We hold flags for features explicitly enabled and explicitly
415 disabled. */
416 static int current_architecture;
417 static int not_current_architecture;
418 static const struct m68k_cpu *selected_arch;
419 static const struct m68k_cpu *selected_cpu;
420 static int initialized;
421
422 /* Architecture models. */
423 static const struct m68k_cpu m68k_archs[] =
424 {
425 {m68000, m68000_ctrl, "68000", 0},
426 {m68010, m68010_ctrl, "68010", 0},
427 {m68020|m68881|m68851, m68020_ctrl, "68020", 0},
428 {m68030|m68881|m68851, m68020_ctrl, "68030", 0},
429 {m68040, m68040_ctrl, "68040", 0},
430 {m68060, m68060_ctrl, "68060", 0},
431 {cpu32|m68881, cpu32_ctrl, "cpu32", 0},
432 {mcfisa_a|mcfhwdiv, NULL, "isaa", 0},
433 {mcfisa_a|mcfhwdiv|mcfisa_aa|mcfusp, NULL, "isaaplus", 0},
434 {mcfisa_a|mcfhwdiv|mcfisa_b|mcfusp, NULL, "isab", 0},
435 {mcfisa_a|mcfhwdiv|mcfisa_b|mcfmac|mcfusp, mcf_ctrl, "cfv4", 0},
436 {mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcfv4e_ctrl, "cfv4e", 0},
437 {0,0,NULL, 0}
438 };
439
440 /* Architecture extensions, here 'alias' -1 for m68k, +1 for cf and 0
441 for either. */
442 static const struct m68k_cpu m68k_extensions[] =
443 {
444 {m68851, NULL, "68851", -1},
445 {m68881, NULL, "68881", -1},
446 {m68881, NULL, "68882", -1},
447
448 {cfloat|m68881, NULL, "float", 0},
449
450 {mcfhwdiv, NULL, "div", 1},
451 {mcfusp, NULL, "usp", 1},
452 {mcfmac, NULL, "mac", 1},
453 {mcfemac, NULL, "emac", 1},
454
455 {0,NULL,NULL, 0}
456 };
457
458 /* Processor list */
459 static const struct m68k_cpu m68k_cpus[] =
460 {
461 {m68000, m68000_ctrl, "68000", 0},
462 {m68000, m68000_ctrl, "68ec000", 1},
463 {m68000, m68000_ctrl, "68hc000", 1},
464 {m68000, m68000_ctrl, "68hc001", 1},
465 {m68000, m68000_ctrl, "68008", 1},
466 {m68000, m68000_ctrl, "68302", 1},
467 {m68000, m68000_ctrl, "68306", 1},
468 {m68000, m68000_ctrl, "68307", 1},
469 {m68000, m68000_ctrl, "68322", 1},
470 {m68000, m68000_ctrl, "68356", 1},
471 {m68010, m68010_ctrl, "68010", 0},
472 {m68020|m68881|m68851, m68020_ctrl, "68020", 0},
473 {m68020|m68881|m68851, m68020_ctrl, "68k", 1},
474 {m68020|m68881|m68851, m68020_ctrl, "68ec020", 1},
475 {m68030|m68881|m68851, m68020_ctrl, "68030", 0},
476 {m68030|m68881|m68851, m68020_ctrl, "68ec030", 1},
477 {m68040, m68040_ctrl, "68040", 0},
478 {m68040, m68040_ctrl, "68ec040", 1},
479 {m68060, m68060_ctrl, "68060", 0},
480 {m68060, m68060_ctrl, "68ec060", 1},
481
482 {cpu32|m68881, cpu32_ctrl, "cpu32", 0},
483 {cpu32|m68881, cpu32_ctrl, "68330", 1},
484 {cpu32|m68881, cpu32_ctrl, "68331", 1},
485 {cpu32|m68881, cpu32_ctrl, "68332", 1},
486 {cpu32|m68881, cpu32_ctrl, "68333", 1},
487 {cpu32|m68881, cpu32_ctrl, "68334", 1},
488 {cpu32|m68881, cpu32_ctrl, "68336", 1},
489 {cpu32|m68881, cpu32_ctrl, "68340", 1},
490 {cpu32|m68881, cpu32_ctrl, "68341", 1},
491 {cpu32|m68881, cpu32_ctrl, "68349", 1},
492 {cpu32|m68881, cpu32_ctrl, "68360", 1},
493
494 {mcfisa_a, mcf_ctrl, "5200", 0},
495 {mcfisa_a, mcf_ctrl, "5202", 1},
496 {mcfisa_a, mcf_ctrl, "5204", 1},
497 {mcfisa_a, mcf_ctrl, "5206", 1},
498
499 {mcfisa_a|mcfhwdiv|mcfmac, mcf_ctrl, "5206e", 0},
500
501 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5208_ctrl, "5207", -1},
502 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5208_ctrl, "5208", 0},
503
504 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5213_ctrl, "5211", -1},
505 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5213_ctrl, "5212", -1},
506 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5213_ctrl, "5213", 0},
507
508 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5216_ctrl, "5214", -1},
509 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5216_ctrl, "5216", 0},
510 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5216_ctrl, "521x", 2},
511
512 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52235_ctrl, "52230", -1},
513 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52235_ctrl, "52233", -1},
514 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52235_ctrl, "52234", -1},
515 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52235_ctrl, "52235", 0},
516
517 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5225_ctrl, "5224", -1},
518 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5225_ctrl, "5225", 0},
519
520 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "5232", -1},
521 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "5233", -1},
522 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "5234", -1},
523 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "5235", -1},
524 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "523x", 0},
525
526 {mcfisa_a|mcfhwdiv|mcfemac, mcf5249_ctrl, "5249", 0},
527 {mcfisa_a|mcfhwdiv|mcfemac, mcf5250_ctrl, "5250", 0},
528
529 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5271_ctrl, "5270", -1},
530 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5271_ctrl, "5271", 0},
531
532 {mcfisa_a|mcfhwdiv|mcfmac, mcf5272_ctrl, "5272", 0},
533
534 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5275_ctrl, "5274", -1},
535 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5275_ctrl, "5275", 0},
536
537 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5282_ctrl, "5280", -1},
538 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5282_ctrl, "5281", -1},
539 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5282_ctrl, "5282", -1},
540 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5282_ctrl, "528x", 0},
541
542 {mcfisa_a|mcfhwdiv|mcfmac, mcf_ctrl, "5307", 0},
543
544 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5329_ctrl, "5327", -1},
545 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5329_ctrl, "5328", -1},
546 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5329_ctrl, "5329", -1},
547 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5329_ctrl, "532x", 0},
548
549 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5373_ctrl, "5372", -1},
550 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5373_ctrl, "5373", -1},
551 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5373_ctrl, "537x", 0},
552
553 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfmac, mcf_ctrl, "5407",0},
554
555 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcfv4e_ctrl, "5470", -1},
556 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcfv4e_ctrl, "5471", -1},
557 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcfv4e_ctrl, "5472", -1},
558 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcfv4e_ctrl, "5473", -1},
559 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcfv4e_ctrl, "5474", -1},
560 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcfv4e_ctrl, "5475", -1},
561 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcfv4e_ctrl, "547x", 0},
562
563 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcfv4e_ctrl, "5480", -1},
564 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcfv4e_ctrl, "5481", -1},
565 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcfv4e_ctrl, "5482", -1},
566 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcfv4e_ctrl, "5483", -1},
567 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcfv4e_ctrl, "5484", -1},
568 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcfv4e_ctrl, "5485", -1},
569 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcfv4e_ctrl, "548x", 0},
570
571 {0,NULL,NULL, 0}
572 };
573
574 static const struct m68k_cpu *m68k_lookup_cpu
575 (const char *, const struct m68k_cpu *, int, int *);
576 static int m68k_set_arch (const char *, int, int);
577 static int m68k_set_cpu (const char *, int, int);
578 static int m68k_set_extension (const char *, int, int);
579 static void m68k_init_arch (void);
580
581 /* This is the assembler relaxation table for m68k. m68k is a rich CISC
582 architecture and we have a lot of relaxation modes. */
583
584 /* Macros used in the relaxation code. */
585 #define TAB(x,y) (((x) << 2) + (y))
586 #define TABTYPE(x) ((x) >> 2)
587
588 /* Relaxation states. */
589 #define BYTE 0
590 #define SHORT 1
591 #define LONG 2
592 #define SZ_UNDEF 3
593
594 /* Here are all the relaxation modes we support. First we can relax ordinary
595 branches. On 68020 and higher and on CPU32 all branch instructions take
596 three forms, so on these CPUs all branches always remain as such. When we
597 have to expand to the LONG form on a 68000, though, we substitute an
598 absolute jump instead. This is a direct replacement for unconditional
599 branches and a branch over a jump for conditional branches. However, if the
600 user requires PIC and disables this with --pcrel, we can only relax between
601 BYTE and SHORT forms, punting if that isn't enough. This gives us four
602 different relaxation modes for branches: */
603
604 #define BRANCHBWL 0 /* Branch byte, word, or long. */
605 #define BRABSJUNC 1 /* Absolute jump for LONG, unconditional. */
606 #define BRABSJCOND 2 /* Absolute jump for LONG, conditional. */
607 #define BRANCHBW 3 /* Branch byte or word. */
608
609 /* We also relax coprocessor branches and DBcc's. All CPUs that support
610 coprocessor branches support them in word and long forms, so we have only
611 one relaxation mode for them. DBcc's are word only on all CPUs. We can
612 relax them to the LONG form with a branch-around sequence. This sequence
613 can use a long branch (if available) or an absolute jump (if acceptable).
614 This gives us two relaxation modes. If long branches are not available and
615 absolute jumps are not acceptable, we don't relax DBcc's. */
616
617 #define FBRANCH 4 /* Coprocessor branch. */
618 #define DBCCLBR 5 /* DBcc relaxable with a long branch. */
619 #define DBCCABSJ 6 /* DBcc relaxable with an absolute jump. */
620
621 /* That's all for instruction relaxation. However, we also relax PC-relative
622 operands. Specifically, we have three operand relaxation modes. On the
623 68000 PC-relative operands can only be 16-bit, but on 68020 and higher and
624 on CPU32 they may be 16-bit or 32-bit. For the latter we relax between the
625 two. Also PC+displacement+index operands in their simple form (with a non-
626 suppressed index without memory indirection) are supported on all CPUs, but
627 on the 68000 the displacement can be 8-bit only, whereas on 68020 and higher
628 and on CPU32 we relax it to SHORT and LONG forms as well using the extended
629 form of the PC+displacement+index operand. Finally, some absolute operands
630 can be relaxed down to 16-bit PC-relative. */
631
632 #define PCREL1632 7 /* 16-bit or 32-bit PC-relative. */
633 #define PCINDEX 8 /* PC + displacement + index. */
634 #define ABSTOPCREL 9 /* Absolute relax down to 16-bit PC-relative. */
635
636 /* Note that calls to frag_var need to specify the maximum expansion
637 needed; this is currently 10 bytes for DBCC. */
638
639 /* The fields are:
640 How far Forward this mode will reach:
641 How far Backward this mode will reach:
642 How many bytes this mode will add to the size of the frag
643 Which mode to go to if the offset won't fit in this one
644
645 Please check tc-m68k.h:md_prepare_relax_scan if changing this table. */
646 relax_typeS md_relax_table[] =
647 {
648 { 127, -128, 0, TAB (BRANCHBWL, SHORT) },
649 { 32767, -32768, 2, TAB (BRANCHBWL, LONG) },
650 { 0, 0, 4, 0 },
651 { 1, 1, 0, 0 },
652
653 { 127, -128, 0, TAB (BRABSJUNC, SHORT) },
654 { 32767, -32768, 2, TAB (BRABSJUNC, LONG) },
655 { 0, 0, 4, 0 },
656 { 1, 1, 0, 0 },
657
658 { 127, -128, 0, TAB (BRABSJCOND, SHORT) },
659 { 32767, -32768, 2, TAB (BRABSJCOND, LONG) },
660 { 0, 0, 6, 0 },
661 { 1, 1, 0, 0 },
662
663 { 127, -128, 0, TAB (BRANCHBW, SHORT) },
664 { 0, 0, 2, 0 },
665 { 1, 1, 0, 0 },
666 { 1, 1, 0, 0 },
667
668 { 1, 1, 0, 0 }, /* FBRANCH doesn't come BYTE. */
669 { 32767, -32768, 2, TAB (FBRANCH, LONG) },
670 { 0, 0, 4, 0 },
671 { 1, 1, 0, 0 },
672
673 { 1, 1, 0, 0 }, /* DBCC doesn't come BYTE. */
674 { 32767, -32768, 2, TAB (DBCCLBR, LONG) },
675 { 0, 0, 10, 0 },
676 { 1, 1, 0, 0 },
677
678 { 1, 1, 0, 0 }, /* DBCC doesn't come BYTE. */
679 { 32767, -32768, 2, TAB (DBCCABSJ, LONG) },
680 { 0, 0, 10, 0 },
681 { 1, 1, 0, 0 },
682
683 { 1, 1, 0, 0 }, /* PCREL1632 doesn't come BYTE. */
684 { 32767, -32768, 2, TAB (PCREL1632, LONG) },
685 { 0, 0, 6, 0 },
686 { 1, 1, 0, 0 },
687
688 { 125, -130, 0, TAB (PCINDEX, SHORT) },
689 { 32765, -32770, 2, TAB (PCINDEX, LONG) },
690 { 0, 0, 4, 0 },
691 { 1, 1, 0, 0 },
692
693 { 1, 1, 0, 0 }, /* ABSTOPCREL doesn't come BYTE. */
694 { 32767, -32768, 2, TAB (ABSTOPCREL, LONG) },
695 { 0, 0, 4, 0 },
696 { 1, 1, 0, 0 },
697 };
698
699 /* These are the machine dependent pseudo-ops. These are included so
700 the assembler can work on the output from the SUN C compiler, which
701 generates these. */
702
703 /* This table describes all the machine specific pseudo-ops the assembler
704 has to support. The fields are:
705 pseudo-op name without dot
706 function to call to execute this pseudo-op
707 Integer arg to pass to the function. */
708 const pseudo_typeS md_pseudo_table[] =
709 {
710 {"data1", s_data1, 0},
711 {"data2", s_data2, 0},
712 {"bss", s_bss, 0},
713 {"even", s_even, 0},
714 {"skip", s_space, 0},
715 {"proc", s_proc, 0},
716 #if defined (TE_SUN3) || defined (OBJ_ELF)
717 {"align", s_align_bytes, 0},
718 #endif
719 #ifdef OBJ_ELF
720 {"swbeg", s_ignore, 0},
721 #endif
722 {"extend", float_cons, 'x'},
723 {"ldouble", float_cons, 'x'},
724
725 {"arch", s_m68k_arch, 0},
726 {"cpu", s_m68k_cpu, 0},
727
728 /* The following pseudo-ops are supported for MRI compatibility. */
729 {"chip", s_chip, 0},
730 {"comline", s_space, 1},
731 {"fopt", s_fopt, 0},
732 {"mask2", s_ignore, 0},
733 {"opt", s_opt, 0},
734 {"reg", s_reg, 0},
735 {"restore", s_restore, 0},
736 {"save", s_save, 0},
737
738 {"if", s_mri_if, 0},
739 {"if.b", s_mri_if, 'b'},
740 {"if.w", s_mri_if, 'w'},
741 {"if.l", s_mri_if, 'l'},
742 {"else", s_mri_else, 0},
743 {"else.s", s_mri_else, 's'},
744 {"else.l", s_mri_else, 'l'},
745 {"endi", s_mri_endi, 0},
746 {"break", s_mri_break, 0},
747 {"break.s", s_mri_break, 's'},
748 {"break.l", s_mri_break, 'l'},
749 {"next", s_mri_next, 0},
750 {"next.s", s_mri_next, 's'},
751 {"next.l", s_mri_next, 'l'},
752 {"for", s_mri_for, 0},
753 {"for.b", s_mri_for, 'b'},
754 {"for.w", s_mri_for, 'w'},
755 {"for.l", s_mri_for, 'l'},
756 {"endf", s_mri_endf, 0},
757 {"repeat", s_mri_repeat, 0},
758 {"until", s_mri_until, 0},
759 {"until.b", s_mri_until, 'b'},
760 {"until.w", s_mri_until, 'w'},
761 {"until.l", s_mri_until, 'l'},
762 {"while", s_mri_while, 0},
763 {"while.b", s_mri_while, 'b'},
764 {"while.w", s_mri_while, 'w'},
765 {"while.l", s_mri_while, 'l'},
766 {"endw", s_mri_endw, 0},
767
768 {0, 0, 0}
769 };
770
771 /* The mote pseudo ops are put into the opcode table, since they
772 don't start with a . they look like opcodes to gas. */
773
774 const pseudo_typeS mote_pseudo_table[] =
775 {
776
777 {"dcl", cons, 4},
778 {"dc", cons, 2},
779 {"dcw", cons, 2},
780 {"dcb", cons, 1},
781
782 {"dsl", s_space, 4},
783 {"ds", s_space, 2},
784 {"dsw", s_space, 2},
785 {"dsb", s_space, 1},
786
787 {"xdef", s_globl, 0},
788 #ifdef OBJ_ELF
789 {"align", s_align_bytes, 0},
790 #else
791 {"align", s_align_ptwo, 0},
792 #endif
793 #ifdef M68KCOFF
794 {"sect", obj_coff_section, 0},
795 {"section", obj_coff_section, 0},
796 #endif
797 {0, 0, 0}
798 };
799
800 /* Truncate and sign-extend at 32 bits, so that building on a 64-bit host
801 gives identical results to a 32-bit host. */
802 #define TRUNC(X) ((valueT) (X) & 0xffffffff)
803 #define SEXT(X) ((TRUNC (X) ^ 0x80000000) - 0x80000000)
804
805 #define issbyte(x) ((valueT) SEXT (x) + 0x80 < 0x100)
806 #define isubyte(x) ((valueT) TRUNC (x) < 0x100)
807 #define issword(x) ((valueT) SEXT (x) + 0x8000 < 0x10000)
808 #define isuword(x) ((valueT) TRUNC (x) < 0x10000)
809
810 #define isbyte(x) ((valueT) SEXT (x) + 0xff < 0x1ff)
811 #define isword(x) ((valueT) SEXT (x) + 0xffff < 0x1ffff)
812 #define islong(x) (1)
813
814 static char notend_table[256];
815 static char alt_notend_table[256];
816 #define notend(s) \
817 (! (notend_table[(unsigned char) *s] \
818 || (*s == ':' \
819 && alt_notend_table[(unsigned char) s[1]])))
820
821 #ifdef OBJ_ELF
822
823 /* Return zero if the reference to SYMBOL from within the same segment may
824 be relaxed. */
825
826 /* On an ELF system, we can't relax an externally visible symbol,
827 because it may be overridden by a shared library. However, if
828 TARGET_OS is "elf", then we presume that we are assembling for an
829 embedded system, in which case we don't have to worry about shared
830 libraries, and we can relax any external sym. */
831
832 #define relaxable_symbol(symbol) \
833 (!((S_IS_EXTERNAL (symbol) && EXTERN_FORCE_RELOC) \
834 || S_IS_WEAK (symbol)))
835
836 /* Compute the relocation code for a fixup of SIZE bytes, using pc
837 relative relocation if PCREL is non-zero. PIC says whether a special
838 pic relocation was requested. */
839
840 static bfd_reloc_code_real_type
841 get_reloc_code (int size, int pcrel, enum pic_relocation pic)
842 {
843 switch (pic)
844 {
845 case pic_got_pcrel:
846 switch (size)
847 {
848 case 1:
849 return BFD_RELOC_8_GOT_PCREL;
850 case 2:
851 return BFD_RELOC_16_GOT_PCREL;
852 case 4:
853 return BFD_RELOC_32_GOT_PCREL;
854 }
855 break;
856
857 case pic_got_off:
858 switch (size)
859 {
860 case 1:
861 return BFD_RELOC_8_GOTOFF;
862 case 2:
863 return BFD_RELOC_16_GOTOFF;
864 case 4:
865 return BFD_RELOC_32_GOTOFF;
866 }
867 break;
868
869 case pic_plt_pcrel:
870 switch (size)
871 {
872 case 1:
873 return BFD_RELOC_8_PLT_PCREL;
874 case 2:
875 return BFD_RELOC_16_PLT_PCREL;
876 case 4:
877 return BFD_RELOC_32_PLT_PCREL;
878 }
879 break;
880
881 case pic_plt_off:
882 switch (size)
883 {
884 case 1:
885 return BFD_RELOC_8_PLTOFF;
886 case 2:
887 return BFD_RELOC_16_PLTOFF;
888 case 4:
889 return BFD_RELOC_32_PLTOFF;
890 }
891 break;
892
893 case pic_none:
894 if (pcrel)
895 {
896 switch (size)
897 {
898 case 1:
899 return BFD_RELOC_8_PCREL;
900 case 2:
901 return BFD_RELOC_16_PCREL;
902 case 4:
903 return BFD_RELOC_32_PCREL;
904 }
905 }
906 else
907 {
908 switch (size)
909 {
910 case 1:
911 return BFD_RELOC_8;
912 case 2:
913 return BFD_RELOC_16;
914 case 4:
915 return BFD_RELOC_32;
916 }
917 }
918 }
919
920 if (pcrel)
921 {
922 if (pic == pic_none)
923 as_bad (_("Can not do %d byte pc-relative relocation"), size);
924 else
925 as_bad (_("Can not do %d byte pc-relative pic relocation"), size);
926 }
927 else
928 {
929 if (pic == pic_none)
930 as_bad (_("Can not do %d byte relocation"), size);
931 else
932 as_bad (_("Can not do %d byte pic relocation"), size);
933 }
934
935 return BFD_RELOC_NONE;
936 }
937
938 /* Here we decide which fixups can be adjusted to make them relative
939 to the beginning of the section instead of the symbol. Basically
940 we need to make sure that the dynamic relocations are done
941 correctly, so in some cases we force the original symbol to be
942 used. */
943 int
944 tc_m68k_fix_adjustable (fixS *fixP)
945 {
946 /* Adjust_reloc_syms doesn't know about the GOT. */
947 switch (fixP->fx_r_type)
948 {
949 case BFD_RELOC_8_GOT_PCREL:
950 case BFD_RELOC_16_GOT_PCREL:
951 case BFD_RELOC_32_GOT_PCREL:
952 case BFD_RELOC_8_GOTOFF:
953 case BFD_RELOC_16_GOTOFF:
954 case BFD_RELOC_32_GOTOFF:
955 case BFD_RELOC_8_PLT_PCREL:
956 case BFD_RELOC_16_PLT_PCREL:
957 case BFD_RELOC_32_PLT_PCREL:
958 case BFD_RELOC_8_PLTOFF:
959 case BFD_RELOC_16_PLTOFF:
960 case BFD_RELOC_32_PLTOFF:
961 return 0;
962
963 case BFD_RELOC_VTABLE_INHERIT:
964 case BFD_RELOC_VTABLE_ENTRY:
965 return 0;
966
967 default:
968 return 1;
969 }
970 }
971
972 #else /* !OBJ_ELF */
973
974 #define get_reloc_code(SIZE,PCREL,OTHER) NO_RELOC
975
976 #define relaxable_symbol(symbol) 1
977
978 #endif /* OBJ_ELF */
979
980 arelent *
981 tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
982 {
983 arelent *reloc;
984 bfd_reloc_code_real_type code;
985
986 /* If the tcbit is set, then this was a fixup of a negative value
987 that was never resolved. We do not have a reloc to handle this,
988 so just return. We assume that other code will have detected this
989 situation and produced a helpful error message, so we just tell the
990 user that the reloc cannot be produced. */
991 if (fixp->fx_tcbit)
992 {
993 if (fixp->fx_addsy)
994 as_bad_where (fixp->fx_file, fixp->fx_line,
995 _("Unable to produce reloc against symbol '%s'"),
996 S_GET_NAME (fixp->fx_addsy));
997 return NULL;
998 }
999
1000 if (fixp->fx_r_type != BFD_RELOC_NONE)
1001 {
1002 code = fixp->fx_r_type;
1003
1004 /* Since DIFF_EXPR_OK is defined in tc-m68k.h, it is possible
1005 that fixup_segment converted a non-PC relative reloc into a
1006 PC relative reloc. In such a case, we need to convert the
1007 reloc code. */
1008 if (fixp->fx_pcrel)
1009 {
1010 switch (code)
1011 {
1012 case BFD_RELOC_8:
1013 code = BFD_RELOC_8_PCREL;
1014 break;
1015 case BFD_RELOC_16:
1016 code = BFD_RELOC_16_PCREL;
1017 break;
1018 case BFD_RELOC_32:
1019 code = BFD_RELOC_32_PCREL;
1020 break;
1021 case BFD_RELOC_8_PCREL:
1022 case BFD_RELOC_16_PCREL:
1023 case BFD_RELOC_32_PCREL:
1024 case BFD_RELOC_8_GOT_PCREL:
1025 case BFD_RELOC_16_GOT_PCREL:
1026 case BFD_RELOC_32_GOT_PCREL:
1027 case BFD_RELOC_8_GOTOFF:
1028 case BFD_RELOC_16_GOTOFF:
1029 case BFD_RELOC_32_GOTOFF:
1030 case BFD_RELOC_8_PLT_PCREL:
1031 case BFD_RELOC_16_PLT_PCREL:
1032 case BFD_RELOC_32_PLT_PCREL:
1033 case BFD_RELOC_8_PLTOFF:
1034 case BFD_RELOC_16_PLTOFF:
1035 case BFD_RELOC_32_PLTOFF:
1036 break;
1037 default:
1038 as_bad_where (fixp->fx_file, fixp->fx_line,
1039 _("Cannot make %s relocation PC relative"),
1040 bfd_get_reloc_code_name (code));
1041 }
1042 }
1043 }
1044 else
1045 {
1046 #define F(SZ,PCREL) (((SZ) << 1) + (PCREL))
1047 switch (F (fixp->fx_size, fixp->fx_pcrel))
1048 {
1049 #define MAP(SZ,PCREL,TYPE) case F(SZ,PCREL): code = (TYPE); break
1050 MAP (1, 0, BFD_RELOC_8);
1051 MAP (2, 0, BFD_RELOC_16);
1052 MAP (4, 0, BFD_RELOC_32);
1053 MAP (1, 1, BFD_RELOC_8_PCREL);
1054 MAP (2, 1, BFD_RELOC_16_PCREL);
1055 MAP (4, 1, BFD_RELOC_32_PCREL);
1056 default:
1057 abort ();
1058 }
1059 }
1060 #undef F
1061 #undef MAP
1062
1063 reloc = (arelent *) xmalloc (sizeof (arelent));
1064 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
1065 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
1066 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
1067 #ifndef OBJ_ELF
1068 if (fixp->fx_pcrel)
1069 reloc->addend = fixp->fx_addnumber;
1070 else
1071 reloc->addend = 0;
1072 #else
1073 if (!fixp->fx_pcrel)
1074 reloc->addend = fixp->fx_addnumber;
1075 else
1076 reloc->addend = (section->vma
1077 /* Explicit sign extension in case char is
1078 unsigned. */
1079 + ((fixp->fx_pcrel_adjust & 0xff) ^ 0x80) - 0x80
1080 + fixp->fx_addnumber
1081 + md_pcrel_from (fixp));
1082 #endif
1083
1084 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
1085 assert (reloc->howto != 0);
1086
1087 return reloc;
1088 }
1089
1090 /* Handle of the OPCODE hash table. NULL means any use before
1091 m68k_ip_begin() will crash. */
1092 static struct hash_control *op_hash;
1093 \f
1094 /* Assemble an m68k instruction. */
1095
1096 static void
1097 m68k_ip (char *instring)
1098 {
1099 register char *p;
1100 register struct m68k_op *opP;
1101 register const struct m68k_incant *opcode;
1102 register const char *s;
1103 register int tmpreg = 0, baseo = 0, outro = 0, nextword;
1104 char *pdot, *pdotmove;
1105 enum m68k_size siz1, siz2;
1106 char c;
1107 int losing;
1108 int opsfound;
1109 struct m68k_op operands_backup[6];
1110 LITTLENUM_TYPE words[6];
1111 LITTLENUM_TYPE *wordp;
1112 unsigned long ok_arch = 0;
1113
1114 if (*instring == ' ')
1115 instring++; /* Skip leading whitespace. */
1116
1117 /* Scan up to end of operation-code, which MUST end in end-of-string
1118 or exactly 1 space. */
1119 pdot = 0;
1120 for (p = instring; *p != '\0'; p++)
1121 {
1122 if (*p == ' ')
1123 break;
1124 if (*p == '.')
1125 pdot = p;
1126 }
1127
1128 if (p == instring)
1129 {
1130 the_ins.error = _("No operator");
1131 return;
1132 }
1133
1134 /* p now points to the end of the opcode name, probably whitespace.
1135 Make sure the name is null terminated by clobbering the
1136 whitespace, look it up in the hash table, then fix it back.
1137 Remove a dot, first, since the opcode tables have none. */
1138 if (pdot != NULL)
1139 {
1140 for (pdotmove = pdot; pdotmove < p; pdotmove++)
1141 *pdotmove = pdotmove[1];
1142 p--;
1143 }
1144
1145 c = *p;
1146 *p = '\0';
1147 opcode = (const struct m68k_incant *) hash_find (op_hash, instring);
1148 *p = c;
1149
1150 if (pdot != NULL)
1151 {
1152 for (pdotmove = p; pdotmove > pdot; pdotmove--)
1153 *pdotmove = pdotmove[-1];
1154 *pdot = '.';
1155 ++p;
1156 }
1157
1158 if (opcode == NULL)
1159 {
1160 the_ins.error = _("Unknown operator");
1161 return;
1162 }
1163
1164 /* Found a legitimate opcode, start matching operands. */
1165 while (*p == ' ')
1166 ++p;
1167
1168 if (opcode->m_operands == 0)
1169 {
1170 char *old = input_line_pointer;
1171 *old = '\n';
1172 input_line_pointer = p;
1173 /* Ahh - it's a motorola style psuedo op. */
1174 mote_pseudo_table[opcode->m_opnum].poc_handler
1175 (mote_pseudo_table[opcode->m_opnum].poc_val);
1176 input_line_pointer = old;
1177 *old = 0;
1178
1179 return;
1180 }
1181
1182 if (flag_mri && opcode->m_opnum == 0)
1183 {
1184 /* In MRI mode, random garbage is allowed after an instruction
1185 which accepts no operands. */
1186 the_ins.args = opcode->m_operands;
1187 the_ins.numargs = opcode->m_opnum;
1188 the_ins.numo = opcode->m_codenum;
1189 the_ins.opcode[0] = getone (opcode);
1190 the_ins.opcode[1] = gettwo (opcode);
1191 return;
1192 }
1193
1194 for (opP = &the_ins.operands[0]; *p; opP++)
1195 {
1196 p = crack_operand (p, opP);
1197
1198 if (opP->error)
1199 {
1200 the_ins.error = opP->error;
1201 return;
1202 }
1203 }
1204
1205 opsfound = opP - &the_ins.operands[0];
1206
1207 /* This ugly hack is to support the floating pt opcodes in their
1208 standard form. Essentially, we fake a first enty of type COP#1 */
1209 if (opcode->m_operands[0] == 'I')
1210 {
1211 int n;
1212
1213 for (n = opsfound; n > 0; --n)
1214 the_ins.operands[n] = the_ins.operands[n - 1];
1215
1216 memset (&the_ins.operands[0], '\0', sizeof (the_ins.operands[0]));
1217 the_ins.operands[0].mode = CONTROL;
1218 the_ins.operands[0].reg = m68k_float_copnum;
1219 opsfound++;
1220 }
1221
1222 /* We've got the operands. Find an opcode that'll accept them. */
1223 for (losing = 0;;)
1224 {
1225 /* If we didn't get the right number of ops, or we have no
1226 common model with this pattern then reject this pattern. */
1227
1228 ok_arch |= opcode->m_arch;
1229 if (opsfound != opcode->m_opnum
1230 || ((opcode->m_arch & current_architecture) == 0))
1231 ++losing;
1232 else
1233 {
1234 int i;
1235
1236 /* Make a copy of the operands of this insn so that
1237 we can modify them safely, should we want to. */
1238 assert (opsfound <= (int) ARRAY_SIZE (operands_backup));
1239 for (i = 0; i < opsfound; i++)
1240 operands_backup[i] = the_ins.operands[i];
1241
1242 for (s = opcode->m_operands, opP = &operands_backup[0];
1243 *s && !losing;
1244 s += 2, opP++)
1245 {
1246 /* Warning: this switch is huge! */
1247 /* I've tried to organize the cases into this order:
1248 non-alpha first, then alpha by letter. Lower-case
1249 goes directly before uppercase counterpart. */
1250 /* Code with multiple case ...: gets sorted by the lowest
1251 case ... it belongs to. I hope this makes sense. */
1252 switch (*s)
1253 {
1254 case '!':
1255 switch (opP->mode)
1256 {
1257 case IMMED:
1258 case DREG:
1259 case AREG:
1260 case FPREG:
1261 case CONTROL:
1262 case AINC:
1263 case ADEC:
1264 case REGLST:
1265 losing++;
1266 break;
1267 default:
1268 break;
1269 }
1270 break;
1271
1272 case '<':
1273 switch (opP->mode)
1274 {
1275 case DREG:
1276 case AREG:
1277 case FPREG:
1278 case CONTROL:
1279 case IMMED:
1280 case ADEC:
1281 case REGLST:
1282 losing++;
1283 break;
1284 default:
1285 break;
1286 }
1287 break;
1288
1289 case '>':
1290 switch (opP->mode)
1291 {
1292 case DREG:
1293 case AREG:
1294 case FPREG:
1295 case CONTROL:
1296 case IMMED:
1297 case AINC:
1298 case REGLST:
1299 losing++;
1300 break;
1301 case ABSL:
1302 break;
1303 default:
1304 if (opP->reg == PC
1305 || opP->reg == ZPC)
1306 losing++;
1307 break;
1308 }
1309 break;
1310
1311 case 'm':
1312 switch (opP->mode)
1313 {
1314 case DREG:
1315 case AREG:
1316 case AINDR:
1317 case AINC:
1318 case ADEC:
1319 break;
1320 default:
1321 losing++;
1322 }
1323 break;
1324
1325 case 'n':
1326 switch (opP->mode)
1327 {
1328 case DISP:
1329 break;
1330 default:
1331 losing++;
1332 }
1333 break;
1334
1335 case 'o':
1336 switch (opP->mode)
1337 {
1338 case BASE:
1339 case ABSL:
1340 case IMMED:
1341 break;
1342 default:
1343 losing++;
1344 }
1345 break;
1346
1347 case 'p':
1348 switch (opP->mode)
1349 {
1350 case DREG:
1351 case AREG:
1352 case AINDR:
1353 case AINC:
1354 case ADEC:
1355 break;
1356 case DISP:
1357 if (opP->reg == PC || opP->reg == ZPC)
1358 losing++;
1359 break;
1360 default:
1361 losing++;
1362 }
1363 break;
1364
1365 case 'q':
1366 switch (opP->mode)
1367 {
1368 case DREG:
1369 case AINDR:
1370 case AINC:
1371 case ADEC:
1372 break;
1373 case DISP:
1374 if (opP->reg == PC || opP->reg == ZPC)
1375 losing++;
1376 break;
1377 default:
1378 losing++;
1379 break;
1380 }
1381 break;
1382
1383 case 'v':
1384 switch (opP->mode)
1385 {
1386 case DREG:
1387 case AINDR:
1388 case AINC:
1389 case ADEC:
1390 case ABSL:
1391 break;
1392 case DISP:
1393 if (opP->reg == PC || opP->reg == ZPC)
1394 losing++;
1395 break;
1396 default:
1397 losing++;
1398 break;
1399 }
1400 break;
1401
1402 case '#':
1403 if (opP->mode != IMMED)
1404 losing++;
1405 else if (s[1] == 'b'
1406 && ! isvar (&opP->disp)
1407 && (opP->disp.exp.X_op != O_constant
1408 || ! isbyte (opP->disp.exp.X_add_number)))
1409 losing++;
1410 else if (s[1] == 'B'
1411 && ! isvar (&opP->disp)
1412 && (opP->disp.exp.X_op != O_constant
1413 || ! issbyte (opP->disp.exp.X_add_number)))
1414 losing++;
1415 else if (s[1] == 'w'
1416 && ! isvar (&opP->disp)
1417 && (opP->disp.exp.X_op != O_constant
1418 || ! isword (opP->disp.exp.X_add_number)))
1419 losing++;
1420 else if (s[1] == 'W'
1421 && ! isvar (&opP->disp)
1422 && (opP->disp.exp.X_op != O_constant
1423 || ! issword (opP->disp.exp.X_add_number)))
1424 losing++;
1425 break;
1426
1427 case '^':
1428 case 'T':
1429 if (opP->mode != IMMED)
1430 losing++;
1431 break;
1432
1433 case '$':
1434 if (opP->mode == AREG
1435 || opP->mode == CONTROL
1436 || opP->mode == FPREG
1437 || opP->mode == IMMED
1438 || opP->mode == REGLST
1439 || (opP->mode != ABSL
1440 && (opP->reg == PC
1441 || opP->reg == ZPC)))
1442 losing++;
1443 break;
1444
1445 case '%':
1446 if (opP->mode == CONTROL
1447 || opP->mode == FPREG
1448 || opP->mode == REGLST
1449 || opP->mode == IMMED
1450 || (opP->mode != ABSL
1451 && (opP->reg == PC
1452 || opP->reg == ZPC)))
1453 losing++;
1454 break;
1455
1456 case '&':
1457 switch (opP->mode)
1458 {
1459 case DREG:
1460 case AREG:
1461 case FPREG:
1462 case CONTROL:
1463 case IMMED:
1464 case AINC:
1465 case ADEC:
1466 case REGLST:
1467 losing++;
1468 break;
1469 case ABSL:
1470 break;
1471 default:
1472 if (opP->reg == PC
1473 || opP->reg == ZPC)
1474 losing++;
1475 break;
1476 }
1477 break;
1478
1479 case '*':
1480 if (opP->mode == CONTROL
1481 || opP->mode == FPREG
1482 || opP->mode == REGLST)
1483 losing++;
1484 break;
1485
1486 case '+':
1487 if (opP->mode != AINC)
1488 losing++;
1489 break;
1490
1491 case '-':
1492 if (opP->mode != ADEC)
1493 losing++;
1494 break;
1495
1496 case '/':
1497 switch (opP->mode)
1498 {
1499 case AREG:
1500 case CONTROL:
1501 case FPREG:
1502 case AINC:
1503 case ADEC:
1504 case IMMED:
1505 case REGLST:
1506 losing++;
1507 break;
1508 default:
1509 break;
1510 }
1511 break;
1512
1513 case ';':
1514 switch (opP->mode)
1515 {
1516 case AREG:
1517 case CONTROL:
1518 case FPREG:
1519 case REGLST:
1520 losing++;
1521 break;
1522 default:
1523 break;
1524 }
1525 break;
1526
1527 case '?':
1528 switch (opP->mode)
1529 {
1530 case AREG:
1531 case CONTROL:
1532 case FPREG:
1533 case AINC:
1534 case ADEC:
1535 case IMMED:
1536 case REGLST:
1537 losing++;
1538 break;
1539 case ABSL:
1540 break;
1541 default:
1542 if (opP->reg == PC || opP->reg == ZPC)
1543 losing++;
1544 break;
1545 }
1546 break;
1547
1548 case '@':
1549 switch (opP->mode)
1550 {
1551 case AREG:
1552 case CONTROL:
1553 case FPREG:
1554 case IMMED:
1555 case REGLST:
1556 losing++;
1557 break;
1558 default:
1559 break;
1560 }
1561 break;
1562
1563 case '~': /* For now! (JF FOO is this right?) */
1564 switch (opP->mode)
1565 {
1566 case DREG:
1567 case AREG:
1568 case CONTROL:
1569 case FPREG:
1570 case IMMED:
1571 case REGLST:
1572 losing++;
1573 break;
1574 case ABSL:
1575 break;
1576 default:
1577 if (opP->reg == PC
1578 || opP->reg == ZPC)
1579 losing++;
1580 break;
1581 }
1582 break;
1583
1584 case '3':
1585 if (opP->mode != CONTROL
1586 || (opP->reg != TT0 && opP->reg != TT1))
1587 losing++;
1588 break;
1589
1590 case 'A':
1591 if (opP->mode != AREG)
1592 losing++;
1593 break;
1594
1595 case 'a':
1596 if (opP->mode != AINDR)
1597 ++losing;
1598 break;
1599
1600 case '4':
1601 if (opP->mode != AINDR && opP->mode != AINC && opP->mode != ADEC
1602 && (opP->mode != DISP
1603 || opP->reg < ADDR0
1604 || opP->reg > ADDR7))
1605 ++losing;
1606 break;
1607
1608 case 'B': /* FOO */
1609 if (opP->mode != ABSL
1610 || (flag_long_jumps
1611 && strncmp (instring, "jbsr", 4) == 0))
1612 losing++;
1613 break;
1614
1615 case 'b':
1616 switch (opP->mode)
1617 {
1618 case IMMED:
1619 case ABSL:
1620 case AREG:
1621 case FPREG:
1622 case CONTROL:
1623 case POST:
1624 case PRE:
1625 case REGLST:
1626 losing++;
1627 break;
1628 default:
1629 break;
1630 }
1631 break;
1632
1633 case 'C':
1634 if (opP->mode != CONTROL || opP->reg != CCR)
1635 losing++;
1636 break;
1637
1638 case 'd':
1639 if (opP->mode != DISP
1640 || opP->reg < ADDR0
1641 || opP->reg > ADDR7)
1642 losing++;
1643 break;
1644
1645 case 'D':
1646 if (opP->mode != DREG)
1647 losing++;
1648 break;
1649
1650 case 'E':
1651 if (opP->reg != ACC)
1652 losing++;
1653 break;
1654
1655 case 'e':
1656 if (opP->reg != ACC && opP->reg != ACC1
1657 && opP->reg != ACC2 && opP->reg != ACC3)
1658 losing++;
1659 break;
1660
1661 case 'F':
1662 if (opP->mode != FPREG)
1663 losing++;
1664 break;
1665
1666 case 'G':
1667 if (opP->reg != MACSR)
1668 losing++;
1669 break;
1670
1671 case 'g':
1672 if (opP->reg != ACCEXT01 && opP->reg != ACCEXT23)
1673 losing++;
1674 break;
1675
1676 case 'H':
1677 if (opP->reg != MASK)
1678 losing++;
1679 break;
1680
1681 case 'I':
1682 if (opP->mode != CONTROL
1683 || opP->reg < COP0
1684 || opP->reg > COP7)
1685 losing++;
1686 break;
1687
1688 case 'i':
1689 if (opP->mode != LSH && opP->mode != RSH)
1690 losing++;
1691 break;
1692
1693 case 'J':
1694 if (opP->mode != CONTROL
1695 || opP->reg < USP
1696 || opP->reg > last_movec_reg
1697 || !control_regs)
1698 losing++;
1699 else
1700 {
1701 const enum m68k_register *rp;
1702
1703 for (rp = control_regs; *rp; rp++)
1704 if (*rp == opP->reg)
1705 break;
1706 if (*rp == 0)
1707 losing++;
1708 }
1709 break;
1710
1711 case 'k':
1712 if (opP->mode != IMMED)
1713 losing++;
1714 break;
1715
1716 case 'l':
1717 case 'L':
1718 if (opP->mode == DREG
1719 || opP->mode == AREG
1720 || opP->mode == FPREG)
1721 {
1722 if (s[1] == '8')
1723 losing++;
1724 else
1725 {
1726 switch (opP->mode)
1727 {
1728 case DREG:
1729 opP->mask = 1 << (opP->reg - DATA0);
1730 break;
1731 case AREG:
1732 opP->mask = 1 << (opP->reg - ADDR0 + 8);
1733 break;
1734 case FPREG:
1735 opP->mask = 1 << (opP->reg - FP0 + 16);
1736 break;
1737 default:
1738 abort ();
1739 }
1740 opP->mode = REGLST;
1741 }
1742 }
1743 else if (opP->mode == CONTROL)
1744 {
1745 if (s[1] != '8')
1746 losing++;
1747 else
1748 {
1749 switch (opP->reg)
1750 {
1751 case FPI:
1752 opP->mask = 1 << 24;
1753 break;
1754 case FPS:
1755 opP->mask = 1 << 25;
1756 break;
1757 case FPC:
1758 opP->mask = 1 << 26;
1759 break;
1760 default:
1761 losing++;
1762 break;
1763 }
1764 opP->mode = REGLST;
1765 }
1766 }
1767 else if (opP->mode != REGLST)
1768 losing++;
1769 else if (s[1] == '8' && (opP->mask & 0x0ffffff) != 0)
1770 losing++;
1771 else if (s[1] == '3' && (opP->mask & 0x7000000) != 0)
1772 losing++;
1773 break;
1774
1775 case 'M':
1776 if (opP->mode != IMMED)
1777 losing++;
1778 else if (opP->disp.exp.X_op != O_constant
1779 || ! issbyte (opP->disp.exp.X_add_number))
1780 losing++;
1781 else if (! m68k_quick
1782 && instring[3] != 'q'
1783 && instring[4] != 'q')
1784 losing++;
1785 break;
1786
1787 case 'O':
1788 if (opP->mode != DREG
1789 && opP->mode != IMMED
1790 && opP->mode != ABSL)
1791 losing++;
1792 break;
1793
1794 case 'Q':
1795 if (opP->mode != IMMED)
1796 losing++;
1797 else if (opP->disp.exp.X_op != O_constant
1798 || TRUNC (opP->disp.exp.X_add_number) - 1 > 7)
1799 losing++;
1800 else if (! m68k_quick
1801 && (strncmp (instring, "add", 3) == 0
1802 || strncmp (instring, "sub", 3) == 0)
1803 && instring[3] != 'q')
1804 losing++;
1805 break;
1806
1807 case 'R':
1808 if (opP->mode != DREG && opP->mode != AREG)
1809 losing++;
1810 break;
1811
1812 case 'r':
1813 if (opP->mode != AINDR
1814 && (opP->mode != BASE
1815 || (opP->reg != 0
1816 && opP->reg != ZADDR0)
1817 || opP->disp.exp.X_op != O_absent
1818 || ((opP->index.reg < DATA0
1819 || opP->index.reg > DATA7)
1820 && (opP->index.reg < ADDR0
1821 || opP->index.reg > ADDR7))
1822 || opP->index.size != SIZE_UNSPEC
1823 || opP->index.scale != 1))
1824 losing++;
1825 break;
1826
1827 case 's':
1828 if (opP->mode != CONTROL
1829 || ! (opP->reg == FPI
1830 || opP->reg == FPS
1831 || opP->reg == FPC))
1832 losing++;
1833 break;
1834
1835 case 'S':
1836 if (opP->mode != CONTROL || opP->reg != SR)
1837 losing++;
1838 break;
1839
1840 case 't':
1841 if (opP->mode != IMMED)
1842 losing++;
1843 else if (opP->disp.exp.X_op != O_constant
1844 || TRUNC (opP->disp.exp.X_add_number) > 7)
1845 losing++;
1846 break;
1847
1848 case 'U':
1849 if (opP->mode != CONTROL || opP->reg != USP)
1850 losing++;
1851 break;
1852
1853 case 'x':
1854 if (opP->mode != IMMED)
1855 losing++;
1856 else if (opP->disp.exp.X_op != O_constant
1857 || (TRUNC (opP->disp.exp.X_add_number) != 0xffffffff
1858 && TRUNC (opP->disp.exp.X_add_number) - 1 > 6))
1859 losing++;
1860 break;
1861
1862 /* JF these are out of order. We could put them
1863 in order if we were willing to put up with
1864 bunches of #ifdef m68851s in the code.
1865
1866 Don't forget that you need these operands
1867 to use 68030 MMU instructions. */
1868 #ifndef NO_68851
1869 /* Memory addressing mode used by pflushr. */
1870 case '|':
1871 if (opP->mode == CONTROL
1872 || opP->mode == FPREG
1873 || opP->mode == DREG
1874 || opP->mode == AREG
1875 || opP->mode == REGLST)
1876 losing++;
1877 /* We should accept immediate operands, but they
1878 supposedly have to be quad word, and we don't
1879 handle that. I would like to see what a Motorola
1880 assembler does before doing something here. */
1881 if (opP->mode == IMMED)
1882 losing++;
1883 break;
1884
1885 case 'f':
1886 if (opP->mode != CONTROL
1887 || (opP->reg != SFC && opP->reg != DFC))
1888 losing++;
1889 break;
1890
1891 case '0':
1892 if (opP->mode != CONTROL || opP->reg != TC)
1893 losing++;
1894 break;
1895
1896 case '1':
1897 if (opP->mode != CONTROL || opP->reg != AC)
1898 losing++;
1899 break;
1900
1901 case '2':
1902 if (opP->mode != CONTROL
1903 || (opP->reg != CAL
1904 && opP->reg != VAL
1905 && opP->reg != SCC))
1906 losing++;
1907 break;
1908
1909 case 'V':
1910 if (opP->mode != CONTROL
1911 || opP->reg != VAL)
1912 losing++;
1913 break;
1914
1915 case 'W':
1916 if (opP->mode != CONTROL
1917 || (opP->reg != DRP
1918 && opP->reg != SRP
1919 && opP->reg != CRP))
1920 losing++;
1921 break;
1922
1923 case 'w':
1924 switch (opP->mode)
1925 {
1926 case IMMED:
1927 case ABSL:
1928 case AREG:
1929 case DREG:
1930 case FPREG:
1931 case CONTROL:
1932 case POST:
1933 case PRE:
1934 case REGLST:
1935 losing++;
1936 break;
1937 default:
1938 break;
1939 }
1940 break;
1941
1942 case 'X':
1943 if (opP->mode != CONTROL
1944 || (!(opP->reg >= BAD && opP->reg <= BAD + 7)
1945 && !(opP->reg >= BAC && opP->reg <= BAC + 7)))
1946 losing++;
1947 break;
1948
1949 case 'Y':
1950 if (opP->mode != CONTROL || opP->reg != PSR)
1951 losing++;
1952 break;
1953
1954 case 'Z':
1955 if (opP->mode != CONTROL || opP->reg != PCSR)
1956 losing++;
1957 break;
1958 #endif
1959 case 'c':
1960 if (opP->mode != CONTROL
1961 || (opP->reg != NC
1962 && opP->reg != IC
1963 && opP->reg != DC
1964 && opP->reg != BC))
1965 losing++;
1966 break;
1967
1968 case '_':
1969 if (opP->mode != ABSL)
1970 ++losing;
1971 break;
1972
1973 case 'u':
1974 if (opP->reg < DATA0L || opP->reg > ADDR7U)
1975 losing++;
1976 /* FIXME: kludge instead of fixing parser:
1977 upper/lower registers are *not* CONTROL
1978 registers, but ordinary ones. */
1979 if ((opP->reg >= DATA0L && opP->reg <= DATA7L)
1980 || (opP->reg >= DATA0U && opP->reg <= DATA7U))
1981 opP->mode = DREG;
1982 else
1983 opP->mode = AREG;
1984 break;
1985
1986 case 'y':
1987 if (!(opP->mode == AINDR
1988 || (opP->mode == DISP
1989 && !(opP->reg == PC || opP->reg == ZPC))))
1990 losing++;
1991 break;
1992
1993 case 'z':
1994 if (!(opP->mode == AINDR || opP->mode == DISP))
1995 losing++;
1996 break;
1997
1998 default:
1999 abort ();
2000 }
2001
2002 if (losing)
2003 break;
2004 }
2005
2006 /* Since we have found the correct instruction, copy
2007 in the modifications that we may have made. */
2008 if (!losing)
2009 for (i = 0; i < opsfound; i++)
2010 the_ins.operands[i] = operands_backup[i];
2011 }
2012
2013 if (!losing)
2014 break;
2015
2016 opcode = opcode->m_next;
2017
2018 if (!opcode)
2019 {
2020 if (ok_arch
2021 && !(ok_arch & current_architecture))
2022 {
2023 const struct m68k_cpu *cpu;
2024 int any = 0;
2025 size_t space = 400;
2026 char *buf = xmalloc (space + 1);
2027 size_t len;
2028 int paren = 1;
2029
2030 the_ins.error = buf;
2031 /* Make sure there's a NUL at the end of the buffer -- strncpy
2032 won't write one when it runs out of buffer */
2033 buf[space] = 0;
2034 #define APPEND(STRING) \
2035 (strncpy (buf, STRING, space), len = strlen (buf), buf += len, space -= len)
2036
2037 APPEND (_("invalid instruction for this architecture; needs "));
2038 switch (ok_arch)
2039 {
2040 case mcfisa_a:
2041 APPEND (_("ColdFire ISA_A"));
2042 break;
2043 case mcfhwdiv:
2044 APPEND (_("ColdFire hardware divide"));
2045 break;
2046 case mcfisa_aa:
2047 APPEND (_("ColdFire ISA_A+"));
2048 break;
2049 case mcfisa_b:
2050 APPEND (_("ColdFire ISA_B"));
2051 break;
2052 case cfloat:
2053 APPEND (_("ColdFire fpu"));
2054 break;
2055 case mfloat:
2056 APPEND (_("M68K fpu"));
2057 break;
2058 case mmmu:
2059 APPEND (_("M68K mmu"));
2060 break;
2061 case m68020up:
2062 APPEND (_("68020 or higher"));
2063 break;
2064 case m68000up:
2065 APPEND (_("68000 or higher"));
2066 break;
2067 case m68010up:
2068 APPEND (_("68010 or higher"));
2069 break;
2070 default:
2071 paren = 0;
2072 }
2073 if (paren)
2074 APPEND (" (");
2075
2076 for (cpu = m68k_cpus; cpu->name; cpu++)
2077 if (!cpu->alias && (cpu->arch & ok_arch))
2078 {
2079 const struct m68k_cpu *alias;
2080
2081 if (any)
2082 APPEND (", ");
2083 any = 0;
2084 APPEND (cpu->name);
2085 APPEND (" [");
2086 if (cpu != m68k_cpus)
2087 for (alias = cpu - 1; alias->alias; alias--)
2088 {
2089 if (any)
2090 APPEND (", ");
2091 APPEND (alias->name);
2092 any = 1;
2093 }
2094 for (alias = cpu + 1; alias->alias; alias++)
2095 {
2096 if (any)
2097 APPEND (", ");
2098 APPEND (alias->name);
2099 any = 1;
2100 }
2101
2102 APPEND ("]");
2103 any = 1;
2104 }
2105 if (paren)
2106 APPEND (")");
2107 #undef APPEND
2108 if (!space)
2109 {
2110 /* we ran out of space, so replace the end of the list
2111 with ellipsis. */
2112 buf -= 4;
2113 while (*buf != ' ')
2114 buf--;
2115 strcpy (buf, " ...");
2116 }
2117 }
2118 else
2119 the_ins.error = _("operands mismatch");
2120 return;
2121 }
2122
2123 losing = 0;
2124 }
2125
2126 /* Now assemble it. */
2127 the_ins.args = opcode->m_operands;
2128 the_ins.numargs = opcode->m_opnum;
2129 the_ins.numo = opcode->m_codenum;
2130 the_ins.opcode[0] = getone (opcode);
2131 the_ins.opcode[1] = gettwo (opcode);
2132
2133 for (s = the_ins.args, opP = &the_ins.operands[0]; *s; s += 2, opP++)
2134 {
2135 /* This switch is a doozy.
2136 Watch the first step; its a big one! */
2137 switch (s[0])
2138 {
2139
2140 case '*':
2141 case '~':
2142 case '%':
2143 case ';':
2144 case '@':
2145 case '!':
2146 case '&':
2147 case '$':
2148 case '?':
2149 case '/':
2150 case '<':
2151 case '>':
2152 case 'b':
2153 case 'm':
2154 case 'n':
2155 case 'o':
2156 case 'p':
2157 case 'q':
2158 case 'v':
2159 case 'w':
2160 case 'y':
2161 case 'z':
2162 case '4':
2163 #ifndef NO_68851
2164 case '|':
2165 #endif
2166 switch (opP->mode)
2167 {
2168 case IMMED:
2169 tmpreg = 0x3c; /* 7.4 */
2170 if (strchr ("bwl", s[1]))
2171 nextword = get_num (&opP->disp, 90);
2172 else
2173 nextword = get_num (&opP->disp, 0);
2174 if (isvar (&opP->disp))
2175 add_fix (s[1], &opP->disp, 0, 0);
2176 switch (s[1])
2177 {
2178 case 'b':
2179 if (!isbyte (nextword))
2180 opP->error = _("operand out of range");
2181 addword (nextword);
2182 baseo = 0;
2183 break;
2184 case 'w':
2185 if (!isword (nextword))
2186 opP->error = _("operand out of range");
2187 addword (nextword);
2188 baseo = 0;
2189 break;
2190 case 'W':
2191 if (!issword (nextword))
2192 opP->error = _("operand out of range");
2193 addword (nextword);
2194 baseo = 0;
2195 break;
2196 case 'l':
2197 addword (nextword >> 16);
2198 addword (nextword);
2199 baseo = 0;
2200 break;
2201
2202 case 'f':
2203 baseo = 2;
2204 outro = 8;
2205 break;
2206 case 'F':
2207 baseo = 4;
2208 outro = 11;
2209 break;
2210 case 'x':
2211 baseo = 6;
2212 outro = 15;
2213 break;
2214 case 'p':
2215 baseo = 6;
2216 outro = -1;
2217 break;
2218 default:
2219 abort ();
2220 }
2221 if (!baseo)
2222 break;
2223
2224 /* We gotta put out some float. */
2225 if (op (&opP->disp) != O_big)
2226 {
2227 valueT val;
2228 int gencnt;
2229
2230 /* Can other cases happen here? */
2231 if (op (&opP->disp) != O_constant)
2232 abort ();
2233
2234 val = (valueT) offs (&opP->disp);
2235 gencnt = 0;
2236 do
2237 {
2238 generic_bignum[gencnt] = (LITTLENUM_TYPE) val;
2239 val >>= LITTLENUM_NUMBER_OF_BITS;
2240 ++gencnt;
2241 }
2242 while (val != 0);
2243 offs (&opP->disp) = gencnt;
2244 }
2245 if (offs (&opP->disp) > 0)
2246 {
2247 if (offs (&opP->disp) > baseo)
2248 {
2249 as_warn (_("Bignum too big for %c format; truncated"),
2250 s[1]);
2251 offs (&opP->disp) = baseo;
2252 }
2253 baseo -= offs (&opP->disp);
2254 while (baseo--)
2255 addword (0);
2256 for (wordp = generic_bignum + offs (&opP->disp) - 1;
2257 offs (&opP->disp)--;
2258 --wordp)
2259 addword (*wordp);
2260 break;
2261 }
2262 gen_to_words (words, baseo, (long) outro);
2263 for (wordp = words; baseo--; wordp++)
2264 addword (*wordp);
2265 break;
2266 case DREG:
2267 tmpreg = opP->reg - DATA; /* 0.dreg */
2268 break;
2269 case AREG:
2270 tmpreg = 0x08 + opP->reg - ADDR; /* 1.areg */
2271 break;
2272 case AINDR:
2273 tmpreg = 0x10 + opP->reg - ADDR; /* 2.areg */
2274 break;
2275 case ADEC:
2276 tmpreg = 0x20 + opP->reg - ADDR; /* 4.areg */
2277 break;
2278 case AINC:
2279 tmpreg = 0x18 + opP->reg - ADDR; /* 3.areg */
2280 break;
2281 case DISP:
2282
2283 nextword = get_num (&opP->disp, 90);
2284
2285 /* Convert mode 5 addressing with a zero offset into
2286 mode 2 addressing to reduce the instruction size by a
2287 word. */
2288 if (! isvar (&opP->disp)
2289 && (nextword == 0)
2290 && (opP->disp.size == SIZE_UNSPEC)
2291 && (opP->reg >= ADDR0)
2292 && (opP->reg <= ADDR7))
2293 {
2294 tmpreg = 0x10 + opP->reg - ADDR; /* 2.areg */
2295 break;
2296 }
2297
2298 if (opP->reg == PC
2299 && ! isvar (&opP->disp)
2300 && m68k_abspcadd)
2301 {
2302 opP->disp.exp.X_op = O_symbol;
2303 opP->disp.exp.X_add_symbol =
2304 section_symbol (absolute_section);
2305 }
2306
2307 /* Force into index mode. Hope this works. */
2308
2309 /* We do the first bit for 32-bit displacements, and the
2310 second bit for 16 bit ones. It is possible that we
2311 should make the default be WORD instead of LONG, but
2312 I think that'd break GCC, so we put up with a little
2313 inefficiency for the sake of working output. */
2314
2315 if (!issword (nextword)
2316 || (isvar (&opP->disp)
2317 && ((opP->disp.size == SIZE_UNSPEC
2318 && flag_short_refs == 0
2319 && cpu_of_arch (current_architecture) >= m68020
2320 && ! arch_coldfire_p (current_architecture))
2321 || opP->disp.size == SIZE_LONG)))
2322 {
2323 if (cpu_of_arch (current_architecture) < m68020
2324 || arch_coldfire_p (current_architecture))
2325 opP->error =
2326 _("displacement too large for this architecture; needs 68020 or higher");
2327 if (opP->reg == PC)
2328 tmpreg = 0x3B; /* 7.3 */
2329 else
2330 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
2331 if (isvar (&opP->disp))
2332 {
2333 if (opP->reg == PC)
2334 {
2335 if (opP->disp.size == SIZE_LONG
2336 #ifdef OBJ_ELF
2337 /* If the displacement needs pic
2338 relocation it cannot be relaxed. */
2339 || opP->disp.pic_reloc != pic_none
2340 #endif
2341 )
2342 {
2343 addword (0x0170);
2344 add_fix ('l', &opP->disp, 1, 2);
2345 }
2346 else
2347 {
2348 add_frag (adds (&opP->disp),
2349 SEXT (offs (&opP->disp)),
2350 TAB (PCREL1632, SZ_UNDEF));
2351 break;
2352 }
2353 }
2354 else
2355 {
2356 addword (0x0170);
2357 add_fix ('l', &opP->disp, 0, 0);
2358 }
2359 }
2360 else
2361 addword (0x0170);
2362 addword (nextword >> 16);
2363 }
2364 else
2365 {
2366 if (opP->reg == PC)
2367 tmpreg = 0x3A; /* 7.2 */
2368 else
2369 tmpreg = 0x28 + opP->reg - ADDR; /* 5.areg */
2370
2371 if (isvar (&opP->disp))
2372 {
2373 if (opP->reg == PC)
2374 {
2375 add_fix ('w', &opP->disp, 1, 0);
2376 }
2377 else
2378 add_fix ('w', &opP->disp, 0, 0);
2379 }
2380 }
2381 addword (nextword);
2382 break;
2383
2384 case POST:
2385 case PRE:
2386 case BASE:
2387 nextword = 0;
2388 baseo = get_num (&opP->disp, 90);
2389 if (opP->mode == POST || opP->mode == PRE)
2390 outro = get_num (&opP->odisp, 90);
2391 /* Figure out the `addressing mode'.
2392 Also turn on the BASE_DISABLE bit, if needed. */
2393 if (opP->reg == PC || opP->reg == ZPC)
2394 {
2395 tmpreg = 0x3b; /* 7.3 */
2396 if (opP->reg == ZPC)
2397 nextword |= 0x80;
2398 }
2399 else if (opP->reg == 0)
2400 {
2401 nextword |= 0x80;
2402 tmpreg = 0x30; /* 6.garbage */
2403 }
2404 else if (opP->reg >= ZADDR0 && opP->reg <= ZADDR7)
2405 {
2406 nextword |= 0x80;
2407 tmpreg = 0x30 + opP->reg - ZADDR0;
2408 }
2409 else
2410 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
2411
2412 siz1 = opP->disp.size;
2413 if (opP->mode == POST || opP->mode == PRE)
2414 siz2 = opP->odisp.size;
2415 else
2416 siz2 = SIZE_UNSPEC;
2417
2418 /* Index register stuff. */
2419 if (opP->index.reg != 0
2420 && opP->index.reg >= DATA
2421 && opP->index.reg <= ADDR7)
2422 {
2423 nextword |= (opP->index.reg - DATA) << 12;
2424
2425 if (opP->index.size == SIZE_LONG
2426 || (opP->index.size == SIZE_UNSPEC
2427 && m68k_index_width_default == SIZE_LONG))
2428 nextword |= 0x800;
2429
2430 if ((opP->index.scale != 1
2431 && cpu_of_arch (current_architecture) < m68020)
2432 || (opP->index.scale == 8
2433 && (arch_coldfire_p (current_architecture)
2434 && !arch_coldfire_fpu (current_architecture))))
2435 {
2436 opP->error =
2437 _("scale factor invalid on this architecture; needs cpu32 or 68020 or higher");
2438 }
2439
2440 if (arch_coldfire_p (current_architecture)
2441 && opP->index.size == SIZE_WORD)
2442 opP->error = _("invalid index size for coldfire");
2443
2444 switch (opP->index.scale)
2445 {
2446 case 1:
2447 break;
2448 case 2:
2449 nextword |= 0x200;
2450 break;
2451 case 4:
2452 nextword |= 0x400;
2453 break;
2454 case 8:
2455 nextword |= 0x600;
2456 break;
2457 default:
2458 abort ();
2459 }
2460 /* IF its simple,
2461 GET US OUT OF HERE! */
2462
2463 /* Must be INDEX, with an index register. Address
2464 register cannot be ZERO-PC, and either :b was
2465 forced, or we know it will fit. For a 68000 or
2466 68010, force this mode anyways, because the
2467 larger modes aren't supported. */
2468 if (opP->mode == BASE
2469 && ((opP->reg >= ADDR0
2470 && opP->reg <= ADDR7)
2471 || opP->reg == PC))
2472 {
2473 if (siz1 == SIZE_BYTE
2474 || cpu_of_arch (current_architecture) < m68020
2475 || arch_coldfire_p (current_architecture)
2476 || (siz1 == SIZE_UNSPEC
2477 && ! isvar (&opP->disp)
2478 && issbyte (baseo)))
2479 {
2480 nextword += baseo & 0xff;
2481 addword (nextword);
2482 if (isvar (&opP->disp))
2483 {
2484 /* Do a byte relocation. If it doesn't
2485 fit (possible on m68000) let the
2486 fixup processing complain later. */
2487 if (opP->reg == PC)
2488 add_fix ('B', &opP->disp, 1, 1);
2489 else
2490 add_fix ('B', &opP->disp, 0, 0);
2491 }
2492 else if (siz1 != SIZE_BYTE)
2493 {
2494 if (siz1 != SIZE_UNSPEC)
2495 as_warn (_("Forcing byte displacement"));
2496 if (! issbyte (baseo))
2497 opP->error = _("byte displacement out of range");
2498 }
2499
2500 break;
2501 }
2502 else if (siz1 == SIZE_UNSPEC
2503 && opP->reg == PC
2504 && isvar (&opP->disp)
2505 && subs (&opP->disp) == NULL
2506 #ifdef OBJ_ELF
2507 /* If the displacement needs pic
2508 relocation it cannot be relaxed. */
2509 && opP->disp.pic_reloc == pic_none
2510 #endif
2511 )
2512 {
2513 /* The code in md_convert_frag_1 needs to be
2514 able to adjust nextword. Call frag_grow
2515 to ensure that we have enough space in
2516 the frag obstack to make all the bytes
2517 contiguous. */
2518 frag_grow (14);
2519 nextword += baseo & 0xff;
2520 addword (nextword);
2521 add_frag (adds (&opP->disp),
2522 SEXT (offs (&opP->disp)),
2523 TAB (PCINDEX, SZ_UNDEF));
2524
2525 break;
2526 }
2527 }
2528 }
2529 else
2530 {
2531 nextword |= 0x40; /* No index reg. */
2532 if (opP->index.reg >= ZDATA0
2533 && opP->index.reg <= ZDATA7)
2534 nextword |= (opP->index.reg - ZDATA0) << 12;
2535 else if (opP->index.reg >= ZADDR0
2536 || opP->index.reg <= ZADDR7)
2537 nextword |= (opP->index.reg - ZADDR0 + 8) << 12;
2538 }
2539
2540 /* It isn't simple. */
2541
2542 if (cpu_of_arch (current_architecture) < m68020
2543 || arch_coldfire_p (current_architecture))
2544 opP->error =
2545 _("invalid operand mode for this architecture; needs 68020 or higher");
2546
2547 nextword |= 0x100;
2548 /* If the guy specified a width, we assume that it is
2549 wide enough. Maybe it isn't. If so, we lose. */
2550 switch (siz1)
2551 {
2552 case SIZE_UNSPEC:
2553 if (isvar (&opP->disp)
2554 ? m68k_rel32
2555 : ! issword (baseo))
2556 {
2557 siz1 = SIZE_LONG;
2558 nextword |= 0x30;
2559 }
2560 else if (! isvar (&opP->disp) && baseo == 0)
2561 nextword |= 0x10;
2562 else
2563 {
2564 nextword |= 0x20;
2565 siz1 = SIZE_WORD;
2566 }
2567 break;
2568 case SIZE_BYTE:
2569 as_warn (_(":b not permitted; defaulting to :w"));
2570 /* Fall through. */
2571 case SIZE_WORD:
2572 nextword |= 0x20;
2573 break;
2574 case SIZE_LONG:
2575 nextword |= 0x30;
2576 break;
2577 }
2578
2579 /* Figure out inner displacement stuff. */
2580 if (opP->mode == POST || opP->mode == PRE)
2581 {
2582 if (cpu_of_arch (current_architecture) & cpu32)
2583 opP->error = _("invalid operand mode for this architecture; needs 68020 or higher");
2584 switch (siz2)
2585 {
2586 case SIZE_UNSPEC:
2587 if (isvar (&opP->odisp)
2588 ? m68k_rel32
2589 : ! issword (outro))
2590 {
2591 siz2 = SIZE_LONG;
2592 nextword |= 0x3;
2593 }
2594 else if (! isvar (&opP->odisp) && outro == 0)
2595 nextword |= 0x1;
2596 else
2597 {
2598 nextword |= 0x2;
2599 siz2 = SIZE_WORD;
2600 }
2601 break;
2602 case 1:
2603 as_warn (_(":b not permitted; defaulting to :w"));
2604 /* Fall through. */
2605 case 2:
2606 nextword |= 0x2;
2607 break;
2608 case 3:
2609 nextword |= 0x3;
2610 break;
2611 }
2612 if (opP->mode == POST
2613 && (nextword & 0x40) == 0)
2614 nextword |= 0x04;
2615 }
2616 addword (nextword);
2617
2618 if (siz1 != SIZE_UNSPEC && isvar (&opP->disp))
2619 {
2620 if (opP->reg == PC || opP->reg == ZPC)
2621 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 1, 2);
2622 else
2623 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 0, 0);
2624 }
2625 if (siz1 == SIZE_LONG)
2626 addword (baseo >> 16);
2627 if (siz1 != SIZE_UNSPEC)
2628 addword (baseo);
2629
2630 if (siz2 != SIZE_UNSPEC && isvar (&opP->odisp))
2631 add_fix (siz2 == SIZE_LONG ? 'l' : 'w', &opP->odisp, 0, 0);
2632 if (siz2 == SIZE_LONG)
2633 addword (outro >> 16);
2634 if (siz2 != SIZE_UNSPEC)
2635 addword (outro);
2636
2637 break;
2638
2639 case ABSL:
2640 nextword = get_num (&opP->disp, 90);
2641 switch (opP->disp.size)
2642 {
2643 default:
2644 abort ();
2645 case SIZE_UNSPEC:
2646 if (!isvar (&opP->disp) && issword (offs (&opP->disp)))
2647 {
2648 tmpreg = 0x38; /* 7.0 */
2649 addword (nextword);
2650 break;
2651 }
2652 if (isvar (&opP->disp)
2653 && !subs (&opP->disp)
2654 && adds (&opP->disp)
2655 #ifdef OBJ_ELF
2656 /* If the displacement needs pic relocation it
2657 cannot be relaxed. */
2658 && opP->disp.pic_reloc == pic_none
2659 #endif
2660 && !flag_long_jumps
2661 && !strchr ("~%&$?", s[0]))
2662 {
2663 tmpreg = 0x3A; /* 7.2 */
2664 add_frag (adds (&opP->disp),
2665 SEXT (offs (&opP->disp)),
2666 TAB (ABSTOPCREL, SZ_UNDEF));
2667 break;
2668 }
2669 /* Fall through into long. */
2670 case SIZE_LONG:
2671 if (isvar (&opP->disp))
2672 add_fix ('l', &opP->disp, 0, 0);
2673
2674 tmpreg = 0x39;/* 7.1 mode */
2675 addword (nextword >> 16);
2676 addword (nextword);
2677 break;
2678
2679 case SIZE_BYTE:
2680 as_bad (_("unsupported byte value; use a different suffix"));
2681 /* Fall through. */
2682
2683 case SIZE_WORD:
2684 if (isvar (&opP->disp))
2685 add_fix ('w', &opP->disp, 0, 0);
2686
2687 tmpreg = 0x38;/* 7.0 mode */
2688 addword (nextword);
2689 break;
2690 }
2691 break;
2692 case CONTROL:
2693 case FPREG:
2694 default:
2695 as_bad (_("unknown/incorrect operand"));
2696 /* abort (); */
2697 }
2698
2699 /* If s[0] is '4', then this is for the mac instructions
2700 that can have a trailing_ampersand set. If so, set 0x100
2701 bit on tmpreg so install_gen_operand can check for it and
2702 set the appropriate bit (word2, bit 5). */
2703 if (s[0] == '4')
2704 {
2705 if (opP->trailing_ampersand)
2706 tmpreg |= 0x100;
2707 }
2708 install_gen_operand (s[1], tmpreg);
2709 break;
2710
2711 case '#':
2712 case '^':
2713 switch (s[1])
2714 { /* JF: I hate floating point! */
2715 case 'j':
2716 tmpreg = 70;
2717 break;
2718 case '8':
2719 tmpreg = 20;
2720 break;
2721 case 'C':
2722 tmpreg = 50;
2723 break;
2724 case '3':
2725 default:
2726 tmpreg = 90;
2727 break;
2728 }
2729 tmpreg = get_num (&opP->disp, tmpreg);
2730 if (isvar (&opP->disp))
2731 add_fix (s[1], &opP->disp, 0, 0);
2732 switch (s[1])
2733 {
2734 case 'b': /* Danger: These do no check for
2735 certain types of overflow.
2736 user beware! */
2737 if (!isbyte (tmpreg))
2738 opP->error = _("out of range");
2739 insop (tmpreg, opcode);
2740 if (isvar (&opP->disp))
2741 the_ins.reloc[the_ins.nrel - 1].n =
2742 (opcode->m_codenum) * 2 + 1;
2743 break;
2744 case 'B':
2745 if (!issbyte (tmpreg))
2746 opP->error = _("out of range");
2747 the_ins.opcode[the_ins.numo - 1] |= tmpreg & 0xff;
2748 if (isvar (&opP->disp))
2749 the_ins.reloc[the_ins.nrel - 1].n = opcode->m_codenum * 2 - 1;
2750 break;
2751 case 'w':
2752 if (!isword (tmpreg))
2753 opP->error = _("out of range");
2754 insop (tmpreg, opcode);
2755 if (isvar (&opP->disp))
2756 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2757 break;
2758 case 'W':
2759 if (!issword (tmpreg))
2760 opP->error = _("out of range");
2761 insop (tmpreg, opcode);
2762 if (isvar (&opP->disp))
2763 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2764 break;
2765 case 'l':
2766 /* Because of the way insop works, we put these two out
2767 backwards. */
2768 insop (tmpreg, opcode);
2769 insop (tmpreg >> 16, opcode);
2770 if (isvar (&opP->disp))
2771 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2772 break;
2773 case '3':
2774 tmpreg &= 0xFF;
2775 case '8':
2776 case 'C':
2777 case 'j':
2778 install_operand (s[1], tmpreg);
2779 break;
2780 default:
2781 abort ();
2782 }
2783 break;
2784
2785 case '+':
2786 case '-':
2787 case 'A':
2788 case 'a':
2789 install_operand (s[1], opP->reg - ADDR);
2790 break;
2791
2792 case 'B':
2793 tmpreg = get_num (&opP->disp, 90);
2794 switch (s[1])
2795 {
2796 case 'B':
2797 add_fix ('B', &opP->disp, 1, -1);
2798 break;
2799 case 'W':
2800 add_fix ('w', &opP->disp, 1, 0);
2801 addword (0);
2802 break;
2803 case 'L':
2804 long_branch:
2805 if (! HAVE_LONG_BRANCH (current_architecture))
2806 as_warn (_("Can't use long branches on 68000/68010/5200"));
2807 the_ins.opcode[0] |= 0xff;
2808 add_fix ('l', &opP->disp, 1, 0);
2809 addword (0);
2810 addword (0);
2811 break;
2812 case 'g':
2813 if (subs (&opP->disp)) /* We can't relax it. */
2814 goto long_branch;
2815
2816 #ifdef OBJ_ELF
2817 /* If the displacement needs pic relocation it cannot be
2818 relaxed. */
2819 if (opP->disp.pic_reloc != pic_none)
2820 goto long_branch;
2821 #endif
2822 /* This could either be a symbol, or an absolute
2823 address. If it's an absolute address, turn it into
2824 an absolute jump right here and keep it out of the
2825 relaxer. */
2826 if (adds (&opP->disp) == 0)
2827 {
2828 if (the_ins.opcode[0] == 0x6000) /* jbra */
2829 the_ins.opcode[0] = 0x4EF9;
2830 else if (the_ins.opcode[0] == 0x6100) /* jbsr */
2831 the_ins.opcode[0] = 0x4EB9;
2832 else /* jCC */
2833 {
2834 the_ins.opcode[0] ^= 0x0100;
2835 the_ins.opcode[0] |= 0x0006;
2836 addword (0x4EF9);
2837 }
2838 add_fix ('l', &opP->disp, 0, 0);
2839 addword (0);
2840 addword (0);
2841 break;
2842 }
2843
2844 /* Now we know it's going into the relaxer. Now figure
2845 out which mode. We try in this order of preference:
2846 long branch, absolute jump, byte/word branches only. */
2847 if (HAVE_LONG_BRANCH (current_architecture))
2848 add_frag (adds (&opP->disp),
2849 SEXT (offs (&opP->disp)),
2850 TAB (BRANCHBWL, SZ_UNDEF));
2851 else if (! flag_keep_pcrel)
2852 {
2853 if ((the_ins.opcode[0] == 0x6000)
2854 || (the_ins.opcode[0] == 0x6100))
2855 add_frag (adds (&opP->disp),
2856 SEXT (offs (&opP->disp)),
2857 TAB (BRABSJUNC, SZ_UNDEF));
2858 else
2859 add_frag (adds (&opP->disp),
2860 SEXT (offs (&opP->disp)),
2861 TAB (BRABSJCOND, SZ_UNDEF));
2862 }
2863 else
2864 add_frag (adds (&opP->disp),
2865 SEXT (offs (&opP->disp)),
2866 TAB (BRANCHBW, SZ_UNDEF));
2867 break;
2868 case 'w':
2869 if (isvar (&opP->disp))
2870 {
2871 /* Check for DBcc instructions. We can relax them,
2872 but only if we have long branches and/or absolute
2873 jumps. */
2874 if (((the_ins.opcode[0] & 0xf0f8) == 0x50c8)
2875 && (HAVE_LONG_BRANCH (current_architecture)
2876 || (! flag_keep_pcrel)))
2877 {
2878 if (HAVE_LONG_BRANCH (current_architecture))
2879 add_frag (adds (&opP->disp),
2880 SEXT (offs (&opP->disp)),
2881 TAB (DBCCLBR, SZ_UNDEF));
2882 else
2883 add_frag (adds (&opP->disp),
2884 SEXT (offs (&opP->disp)),
2885 TAB (DBCCABSJ, SZ_UNDEF));
2886 break;
2887 }
2888 add_fix ('w', &opP->disp, 1, 0);
2889 }
2890 addword (0);
2891 break;
2892 case 'C': /* Fixed size LONG coproc branches. */
2893 add_fix ('l', &opP->disp, 1, 0);
2894 addword (0);
2895 addword (0);
2896 break;
2897 case 'c': /* Var size Coprocesssor branches. */
2898 if (subs (&opP->disp) || (adds (&opP->disp) == 0))
2899 {
2900 the_ins.opcode[the_ins.numo - 1] |= 0x40;
2901 add_fix ('l', &opP->disp, 1, 0);
2902 addword (0);
2903 addword (0);
2904 }
2905 else
2906 add_frag (adds (&opP->disp),
2907 SEXT (offs (&opP->disp)),
2908 TAB (FBRANCH, SZ_UNDEF));
2909 break;
2910 default:
2911 abort ();
2912 }
2913 break;
2914
2915 case 'C': /* Ignore it. */
2916 break;
2917
2918 case 'd': /* JF this is a kludge. */
2919 install_operand ('s', opP->reg - ADDR);
2920 tmpreg = get_num (&opP->disp, 90);
2921 if (!issword (tmpreg))
2922 {
2923 as_warn (_("Expression out of range, using 0"));
2924 tmpreg = 0;
2925 }
2926 addword (tmpreg);
2927 break;
2928
2929 case 'D':
2930 install_operand (s[1], opP->reg - DATA);
2931 break;
2932
2933 case 'e': /* EMAC ACCx, reg/reg. */
2934 install_operand (s[1], opP->reg - ACC);
2935 break;
2936
2937 case 'E': /* Ignore it. */
2938 break;
2939
2940 case 'F':
2941 install_operand (s[1], opP->reg - FP0);
2942 break;
2943
2944 case 'g': /* EMAC ACCEXTx. */
2945 install_operand (s[1], opP->reg - ACCEXT01);
2946 break;
2947
2948 case 'G': /* Ignore it. */
2949 case 'H':
2950 break;
2951
2952 case 'I':
2953 tmpreg = opP->reg - COP0;
2954 install_operand (s[1], tmpreg);
2955 break;
2956
2957 case 'i': /* MAC/EMAC scale factor. */
2958 install_operand (s[1], opP->mode == LSH ? 0x1 : 0x3);
2959 break;
2960
2961 case 'J': /* JF foo. */
2962 switch (opP->reg)
2963 {
2964 case SFC:
2965 tmpreg = 0x000;
2966 break;
2967 case DFC:
2968 tmpreg = 0x001;
2969 break;
2970 case CACR:
2971 tmpreg = 0x002;
2972 break;
2973 case TC:
2974 tmpreg = 0x003;
2975 break;
2976 case ACR0:
2977 case ITT0:
2978 tmpreg = 0x004;
2979 break;
2980 case ACR1:
2981 case ITT1:
2982 tmpreg = 0x005;
2983 break;
2984 case ACR2:
2985 case DTT0:
2986 tmpreg = 0x006;
2987 break;
2988 case ACR3:
2989 case DTT1:
2990 tmpreg = 0x007;
2991 break;
2992 case BUSCR:
2993 tmpreg = 0x008;
2994 break;
2995
2996 case USP:
2997 tmpreg = 0x800;
2998 break;
2999 case VBR:
3000 tmpreg = 0x801;
3001 break;
3002 case CAAR:
3003 tmpreg = 0x802;
3004 break;
3005 case MSP:
3006 tmpreg = 0x803;
3007 break;
3008 case ISP:
3009 tmpreg = 0x804;
3010 break;
3011 case MMUSR:
3012 tmpreg = 0x805;
3013 break;
3014 case URP:
3015 tmpreg = 0x806;
3016 break;
3017 case SRP:
3018 tmpreg = 0x807;
3019 break;
3020 case PCR:
3021 tmpreg = 0x808;
3022 break;
3023 case ROMBAR:
3024 tmpreg = 0xC00;
3025 break;
3026 case ROMBAR1:
3027 tmpreg = 0xC01;
3028 break;
3029 case FLASHBAR:
3030 case RAMBAR0:
3031 tmpreg = 0xC04;
3032 break;
3033 case RAMBAR:
3034 case RAMBAR1:
3035 tmpreg = 0xC05;
3036 break;
3037 case MPCR:
3038 tmpreg = 0xC0C;
3039 break;
3040 case EDRAMBAR:
3041 tmpreg = 0xC0D;
3042 break;
3043 case MBAR0:
3044 case MBAR2:
3045 case SECMBAR:
3046 tmpreg = 0xC0E;
3047 break;
3048 case MBAR1:
3049 case MBAR:
3050 tmpreg = 0xC0F;
3051 break;
3052 case PCR1U0:
3053 tmpreg = 0xD02;
3054 break;
3055 case PCR1L0:
3056 tmpreg = 0xD03;
3057 break;
3058 case PCR2U0:
3059 tmpreg = 0xD04;
3060 break;
3061 case PCR2L0:
3062 tmpreg = 0xD05;
3063 break;
3064 case PCR3U0:
3065 tmpreg = 0xD06;
3066 break;
3067 case PCR3L0:
3068 tmpreg = 0xD07;
3069 break;
3070 case PCR1L1:
3071 tmpreg = 0xD0A;
3072 break;
3073 case PCR1U1:
3074 tmpreg = 0xD0B;
3075 break;
3076 case PCR2L1:
3077 tmpreg = 0xD0C;
3078 break;
3079 case PCR2U1:
3080 tmpreg = 0xD0D;
3081 break;
3082 case PCR3L1:
3083 tmpreg = 0xD0E;
3084 break;
3085 case PCR3U1:
3086 tmpreg = 0xD0F;
3087 break;
3088 default:
3089 abort ();
3090 }
3091 install_operand (s[1], tmpreg);
3092 break;
3093
3094 case 'k':
3095 tmpreg = get_num (&opP->disp, 55);
3096 install_operand (s[1], tmpreg & 0x7f);
3097 break;
3098
3099 case 'l':
3100 tmpreg = opP->mask;
3101 if (s[1] == 'w')
3102 {
3103 if (tmpreg & 0x7FF0000)
3104 as_bad (_("Floating point register in register list"));
3105 insop (reverse_16_bits (tmpreg), opcode);
3106 }
3107 else
3108 {
3109 if (tmpreg & 0x700FFFF)
3110 as_bad (_("Wrong register in floating-point reglist"));
3111 install_operand (s[1], reverse_8_bits (tmpreg >> 16));
3112 }
3113 break;
3114
3115 case 'L':
3116 tmpreg = opP->mask;
3117 if (s[1] == 'w')
3118 {
3119 if (tmpreg & 0x7FF0000)
3120 as_bad (_("Floating point register in register list"));
3121 insop (tmpreg, opcode);
3122 }
3123 else if (s[1] == '8')
3124 {
3125 if (tmpreg & 0x0FFFFFF)
3126 as_bad (_("incorrect register in reglist"));
3127 install_operand (s[1], tmpreg >> 24);
3128 }
3129 else
3130 {
3131 if (tmpreg & 0x700FFFF)
3132 as_bad (_("wrong register in floating-point reglist"));
3133 else
3134 install_operand (s[1], tmpreg >> 16);
3135 }
3136 break;
3137
3138 case 'M':
3139 install_operand (s[1], get_num (&opP->disp, 60));
3140 break;
3141
3142 case 'O':
3143 tmpreg = ((opP->mode == DREG)
3144 ? 0x20 + (int) (opP->reg - DATA)
3145 : (get_num (&opP->disp, 40) & 0x1F));
3146 install_operand (s[1], tmpreg);
3147 break;
3148
3149 case 'Q':
3150 tmpreg = get_num (&opP->disp, 10);
3151 if (tmpreg == 8)
3152 tmpreg = 0;
3153 install_operand (s[1], tmpreg);
3154 break;
3155
3156 case 'R':
3157 /* This depends on the fact that ADDR registers are eight
3158 more than their corresponding DATA regs, so the result
3159 will have the ADDR_REG bit set. */
3160 install_operand (s[1], opP->reg - DATA);
3161 break;
3162
3163 case 'r':
3164 if (opP->mode == AINDR)
3165 install_operand (s[1], opP->reg - DATA);
3166 else
3167 install_operand (s[1], opP->index.reg - DATA);
3168 break;
3169
3170 case 's':
3171 if (opP->reg == FPI)
3172 tmpreg = 0x1;
3173 else if (opP->reg == FPS)
3174 tmpreg = 0x2;
3175 else if (opP->reg == FPC)
3176 tmpreg = 0x4;
3177 else
3178 abort ();
3179 install_operand (s[1], tmpreg);
3180 break;
3181
3182 case 'S': /* Ignore it. */
3183 break;
3184
3185 case 'T':
3186 install_operand (s[1], get_num (&opP->disp, 30));
3187 break;
3188
3189 case 'U': /* Ignore it. */
3190 break;
3191
3192 case 'c':
3193 switch (opP->reg)
3194 {
3195 case NC:
3196 tmpreg = 0;
3197 break;
3198 case DC:
3199 tmpreg = 1;
3200 break;
3201 case IC:
3202 tmpreg = 2;
3203 break;
3204 case BC:
3205 tmpreg = 3;
3206 break;
3207 default:
3208 as_fatal (_("failed sanity check"));
3209 } /* switch on cache token. */
3210 install_operand (s[1], tmpreg);
3211 break;
3212 #ifndef NO_68851
3213 /* JF: These are out of order, I fear. */
3214 case 'f':
3215 switch (opP->reg)
3216 {
3217 case SFC:
3218 tmpreg = 0;
3219 break;
3220 case DFC:
3221 tmpreg = 1;
3222 break;
3223 default:
3224 abort ();
3225 }
3226 install_operand (s[1], tmpreg);
3227 break;
3228
3229 case '0':
3230 case '1':
3231 case '2':
3232 switch (opP->reg)
3233 {
3234 case TC:
3235 tmpreg = 0;
3236 break;
3237 case CAL:
3238 tmpreg = 4;
3239 break;
3240 case VAL:
3241 tmpreg = 5;
3242 break;
3243 case SCC:
3244 tmpreg = 6;
3245 break;
3246 case AC:
3247 tmpreg = 7;
3248 break;
3249 default:
3250 abort ();
3251 }
3252 install_operand (s[1], tmpreg);
3253 break;
3254
3255 case 'V':
3256 if (opP->reg == VAL)
3257 break;
3258 abort ();
3259
3260 case 'W':
3261 switch (opP->reg)
3262 {
3263 case DRP:
3264 tmpreg = 1;
3265 break;
3266 case SRP:
3267 tmpreg = 2;
3268 break;
3269 case CRP:
3270 tmpreg = 3;
3271 break;
3272 default:
3273 abort ();
3274 }
3275 install_operand (s[1], tmpreg);
3276 break;
3277
3278 case 'X':
3279 switch (opP->reg)
3280 {
3281 case BAD:
3282 case BAD + 1:
3283 case BAD + 2:
3284 case BAD + 3:
3285 case BAD + 4:
3286 case BAD + 5:
3287 case BAD + 6:
3288 case BAD + 7:
3289 tmpreg = (4 << 10) | ((opP->reg - BAD) << 2);
3290 break;
3291
3292 case BAC:
3293 case BAC + 1:
3294 case BAC + 2:
3295 case BAC + 3:
3296 case BAC + 4:
3297 case BAC + 5:
3298 case BAC + 6:
3299 case BAC + 7:
3300 tmpreg = (5 << 10) | ((opP->reg - BAC) << 2);
3301 break;
3302
3303 default:
3304 abort ();
3305 }
3306 install_operand (s[1], tmpreg);
3307 break;
3308 case 'Y':
3309 know (opP->reg == PSR);
3310 break;
3311 case 'Z':
3312 know (opP->reg == PCSR);
3313 break;
3314 #endif /* m68851 */
3315 case '3':
3316 switch (opP->reg)
3317 {
3318 case TT0:
3319 tmpreg = 2;
3320 break;
3321 case TT1:
3322 tmpreg = 3;
3323 break;
3324 default:
3325 abort ();
3326 }
3327 install_operand (s[1], tmpreg);
3328 break;
3329 case 't':
3330 tmpreg = get_num (&opP->disp, 20);
3331 install_operand (s[1], tmpreg);
3332 break;
3333 case '_': /* used only for move16 absolute 32-bit address. */
3334 if (isvar (&opP->disp))
3335 add_fix ('l', &opP->disp, 0, 0);
3336 tmpreg = get_num (&opP->disp, 90);
3337 addword (tmpreg >> 16);
3338 addword (tmpreg & 0xFFFF);
3339 break;
3340 case 'u':
3341 install_operand (s[1], opP->reg - DATA0L);
3342 opP->reg -= (DATA0L);
3343 opP->reg &= 0x0F; /* remove upper/lower bit. */
3344 break;
3345 case 'x':
3346 tmpreg = get_num (&opP->disp, 80);
3347 if (tmpreg == -1)
3348 tmpreg = 0;
3349 install_operand (s[1], tmpreg);
3350 break;
3351 default:
3352 abort ();
3353 }
3354 }
3355
3356 /* By the time whe get here (FINALLY) the_ins contains the complete
3357 instruction, ready to be emitted. . . */
3358 }
3359
3360 static int
3361 reverse_16_bits (int in)
3362 {
3363 int out = 0;
3364 int n;
3365
3366 static int mask[16] =
3367 {
3368 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
3369 0x0100, 0x0200, 0x0400, 0x0800, 0x1000, 0x2000, 0x4000, 0x8000
3370 };
3371 for (n = 0; n < 16; n++)
3372 {
3373 if (in & mask[n])
3374 out |= mask[15 - n];
3375 }
3376 return out;
3377 } /* reverse_16_bits() */
3378
3379 static int
3380 reverse_8_bits (int in)
3381 {
3382 int out = 0;
3383 int n;
3384
3385 static int mask[8] =
3386 {
3387 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
3388 };
3389
3390 for (n = 0; n < 8; n++)
3391 {
3392 if (in & mask[n])
3393 out |= mask[7 - n];
3394 }
3395 return out;
3396 } /* reverse_8_bits() */
3397
3398 /* Cause an extra frag to be generated here, inserting up to 10 bytes
3399 (that value is chosen in the frag_var call in md_assemble). TYPE
3400 is the subtype of the frag to be generated; its primary type is
3401 rs_machine_dependent.
3402
3403 The TYPE parameter is also used by md_convert_frag_1 and
3404 md_estimate_size_before_relax. The appropriate type of fixup will
3405 be emitted by md_convert_frag_1.
3406
3407 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
3408 static void
3409 install_operand (int mode, int val)
3410 {
3411 switch (mode)
3412 {
3413 case 's':
3414 the_ins.opcode[0] |= val & 0xFF; /* JF FF is for M kludge. */
3415 break;
3416 case 'd':
3417 the_ins.opcode[0] |= val << 9;
3418 break;
3419 case '1':
3420 the_ins.opcode[1] |= val << 12;
3421 break;
3422 case '2':
3423 the_ins.opcode[1] |= val << 6;
3424 break;
3425 case '3':
3426 the_ins.opcode[1] |= val;
3427 break;
3428 case '4':
3429 the_ins.opcode[2] |= val << 12;
3430 break;
3431 case '5':
3432 the_ins.opcode[2] |= val << 6;
3433 break;
3434 case '6':
3435 /* DANGER! This is a hack to force cas2l and cas2w cmds to be
3436 three words long! */
3437 the_ins.numo++;
3438 the_ins.opcode[2] |= val;
3439 break;
3440 case '7':
3441 the_ins.opcode[1] |= val << 7;
3442 break;
3443 case '8':
3444 the_ins.opcode[1] |= val << 10;
3445 break;
3446 #ifndef NO_68851
3447 case '9':
3448 the_ins.opcode[1] |= val << 5;
3449 break;
3450 #endif
3451
3452 case 't':
3453 the_ins.opcode[1] |= (val << 10) | (val << 7);
3454 break;
3455 case 'D':
3456 the_ins.opcode[1] |= (val << 12) | val;
3457 break;
3458 case 'g':
3459 the_ins.opcode[0] |= val = 0xff;
3460 break;
3461 case 'i':
3462 the_ins.opcode[0] |= val << 9;
3463 break;
3464 case 'C':
3465 the_ins.opcode[1] |= val;
3466 break;
3467 case 'j':
3468 the_ins.opcode[1] |= val;
3469 the_ins.numo++; /* What a hack. */
3470 break;
3471 case 'k':
3472 the_ins.opcode[1] |= val << 4;
3473 break;
3474 case 'b':
3475 case 'w':
3476 case 'W':
3477 case 'l':
3478 break;
3479 case 'e':
3480 the_ins.opcode[0] |= (val << 6);
3481 break;
3482 case 'L':
3483 the_ins.opcode[1] = (val >> 16);
3484 the_ins.opcode[2] = val & 0xffff;
3485 break;
3486 case 'm':
3487 the_ins.opcode[0] |= ((val & 0x8) << (6 - 3));
3488 the_ins.opcode[0] |= ((val & 0x7) << 9);
3489 the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
3490 break;
3491 case 'n': /* MAC/EMAC Rx on !load. */
3492 the_ins.opcode[0] |= ((val & 0x8) << (6 - 3));
3493 the_ins.opcode[0] |= ((val & 0x7) << 9);
3494 the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
3495 break;
3496 case 'o': /* MAC/EMAC Rx on load. */
3497 the_ins.opcode[1] |= val << 12;
3498 the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
3499 break;
3500 case 'M': /* MAC/EMAC Ry on !load. */
3501 the_ins.opcode[0] |= (val & 0xF);
3502 the_ins.opcode[1] |= ((val & 0x10) << (6 - 4));
3503 break;
3504 case 'N': /* MAC/EMAC Ry on load. */
3505 the_ins.opcode[1] |= (val & 0xF);
3506 the_ins.opcode[1] |= ((val & 0x10) << (6 - 4));
3507 break;
3508 case 'h':
3509 the_ins.opcode[1] |= ((val != 1) << 10);
3510 break;
3511 case 'F':
3512 the_ins.opcode[0] |= ((val & 0x3) << 9);
3513 break;
3514 case 'f':
3515 the_ins.opcode[0] |= ((val & 0x3) << 0);
3516 break;
3517 case 'G': /* EMAC accumulator in a EMAC load instruction. */
3518 the_ins.opcode[0] |= ((~val & 0x1) << 7);
3519 the_ins.opcode[1] |= ((val & 0x2) << (4 - 1));
3520 break;
3521 case 'H': /* EMAC accumulator in a EMAC non-load instruction. */
3522 the_ins.opcode[0] |= ((val & 0x1) << 7);
3523 the_ins.opcode[1] |= ((val & 0x2) << (4 - 1));
3524 break;
3525 case 'I':
3526 the_ins.opcode[1] |= ((val & 0x3) << 9);
3527 break;
3528 case ']':
3529 the_ins.opcode[0] |= (val & 0x1) <<10;
3530 break;
3531 case 'c':
3532 default:
3533 as_fatal (_("failed sanity check."));
3534 }
3535 }
3536
3537 static void
3538 install_gen_operand (int mode, int val)
3539 {
3540 switch (mode)
3541 {
3542 case '/': /* Special for mask loads for mac/msac insns with
3543 possible mask; trailing_ampersend set in bit 8. */
3544 the_ins.opcode[0] |= (val & 0x3f);
3545 the_ins.opcode[1] |= (((val & 0x100) >> 8) << 5);
3546 break;
3547 case 's':
3548 the_ins.opcode[0] |= val;
3549 break;
3550 case 'd':
3551 /* This is a kludge!!! */
3552 the_ins.opcode[0] |= (val & 0x07) << 9 | (val & 0x38) << 3;
3553 break;
3554 case 'b':
3555 case 'w':
3556 case 'l':
3557 case 'f':
3558 case 'F':
3559 case 'x':
3560 case 'p':
3561 the_ins.opcode[0] |= val;
3562 break;
3563 /* more stuff goes here. */
3564 default:
3565 as_fatal (_("failed sanity check."));
3566 }
3567 }
3568
3569 /* Verify that we have some number of paren pairs, do m68k_ip_op(), and
3570 then deal with the bitfield hack. */
3571
3572 static char *
3573 crack_operand (char *str, struct m68k_op *opP)
3574 {
3575 register int parens;
3576 register int c;
3577 register char *beg_str;
3578 int inquote = 0;
3579
3580 if (!str)
3581 {
3582 return str;
3583 }
3584 beg_str = str;
3585 for (parens = 0; *str && (parens > 0 || inquote || notend (str)); str++)
3586 {
3587 if (! inquote)
3588 {
3589 if (*str == '(')
3590 parens++;
3591 else if (*str == ')')
3592 {
3593 if (!parens)
3594 { /* ERROR. */
3595 opP->error = _("Extra )");
3596 return str;
3597 }
3598 --parens;
3599 }
3600 }
3601 if (flag_mri && *str == '\'')
3602 inquote = ! inquote;
3603 }
3604 if (!*str && parens)
3605 { /* ERROR. */
3606 opP->error = _("Missing )");
3607 return str;
3608 }
3609 c = *str;
3610 *str = '\0';
3611 if (m68k_ip_op (beg_str, opP) != 0)
3612 {
3613 *str = c;
3614 return str;
3615 }
3616 *str = c;
3617 if (c == '}')
3618 c = *++str; /* JF bitfield hack. */
3619 if (c)
3620 {
3621 c = *++str;
3622 if (!c)
3623 as_bad (_("Missing operand"));
3624 }
3625
3626 /* Detect MRI REG symbols and convert them to REGLSTs. */
3627 if (opP->mode == CONTROL && (int)opP->reg < 0)
3628 {
3629 opP->mode = REGLST;
3630 opP->mask = ~(int)opP->reg;
3631 opP->reg = 0;
3632 }
3633
3634 return str;
3635 }
3636
3637 /* This is the guts of the machine-dependent assembler. STR points to a
3638 machine dependent instruction. This function is supposed to emit
3639 the frags/bytes it assembles to.
3640 */
3641
3642 static void
3643 insert_reg (const char *regname, int regnum)
3644 {
3645 char buf[100];
3646 int i;
3647
3648 #ifdef REGISTER_PREFIX
3649 if (!flag_reg_prefix_optional)
3650 {
3651 buf[0] = REGISTER_PREFIX;
3652 strcpy (buf + 1, regname);
3653 regname = buf;
3654 }
3655 #endif
3656
3657 symbol_table_insert (symbol_new (regname, reg_section, regnum,
3658 &zero_address_frag));
3659
3660 for (i = 0; regname[i]; i++)
3661 buf[i] = TOUPPER (regname[i]);
3662 buf[i] = '\0';
3663
3664 symbol_table_insert (symbol_new (buf, reg_section, regnum,
3665 &zero_address_frag));
3666 }
3667
3668 struct init_entry
3669 {
3670 const char *name;
3671 int number;
3672 };
3673
3674 static const struct init_entry init_table[] =
3675 {
3676 { "d0", DATA0 },
3677 { "d1", DATA1 },
3678 { "d2", DATA2 },
3679 { "d3", DATA3 },
3680 { "d4", DATA4 },
3681 { "d5", DATA5 },
3682 { "d6", DATA6 },
3683 { "d7", DATA7 },
3684 { "a0", ADDR0 },
3685 { "a1", ADDR1 },
3686 { "a2", ADDR2 },
3687 { "a3", ADDR3 },
3688 { "a4", ADDR4 },
3689 { "a5", ADDR5 },
3690 { "a6", ADDR6 },
3691 { "fp", ADDR6 },
3692 { "a7", ADDR7 },
3693 { "sp", ADDR7 },
3694 { "ssp", ADDR7 },
3695 { "fp0", FP0 },
3696 { "fp1", FP1 },
3697 { "fp2", FP2 },
3698 { "fp3", FP3 },
3699 { "fp4", FP4 },
3700 { "fp5", FP5 },
3701 { "fp6", FP6 },
3702 { "fp7", FP7 },
3703 { "fpi", FPI },
3704 { "fpiar", FPI },
3705 { "fpc", FPI },
3706 { "fps", FPS },
3707 { "fpsr", FPS },
3708 { "fpc", FPC },
3709 { "fpcr", FPC },
3710 { "control", FPC },
3711 { "status", FPS },
3712 { "iaddr", FPI },
3713
3714 { "cop0", COP0 },
3715 { "cop1", COP1 },
3716 { "cop2", COP2 },
3717 { "cop3", COP3 },
3718 { "cop4", COP4 },
3719 { "cop5", COP5 },
3720 { "cop6", COP6 },
3721 { "cop7", COP7 },
3722 { "pc", PC },
3723 { "zpc", ZPC },
3724 { "sr", SR },
3725
3726 { "ccr", CCR },
3727 { "cc", CCR },
3728
3729 { "acc", ACC },
3730 { "acc0", ACC },
3731 { "acc1", ACC1 },
3732 { "acc2", ACC2 },
3733 { "acc3", ACC3 },
3734 { "accext01", ACCEXT01 },
3735 { "accext23", ACCEXT23 },
3736 { "macsr", MACSR },
3737 { "mask", MASK },
3738
3739 /* Control registers. */
3740 { "sfc", SFC }, /* Source Function Code. */
3741 { "sfcr", SFC },
3742 { "dfc", DFC }, /* Destination Function Code. */
3743 { "dfcr", DFC },
3744 { "cacr", CACR }, /* Cache Control Register. */
3745 { "caar", CAAR }, /* Cache Address Register. */
3746
3747 { "usp", USP }, /* User Stack Pointer. */
3748 { "vbr", VBR }, /* Vector Base Register. */
3749 { "msp", MSP }, /* Master Stack Pointer. */
3750 { "isp", ISP }, /* Interrupt Stack Pointer. */
3751
3752 { "itt0", ITT0 }, /* Instruction Transparent Translation Reg 0. */
3753 { "itt1", ITT1 }, /* Instruction Transparent Translation Reg 1. */
3754 { "dtt0", DTT0 }, /* Data Transparent Translation Register 0. */
3755 { "dtt1", DTT1 }, /* Data Transparent Translation Register 1. */
3756
3757 /* 68ec040 versions of same */
3758 { "iacr0", ITT0 }, /* Instruction Access Control Register 0. */
3759 { "iacr1", ITT1 }, /* Instruction Access Control Register 0. */
3760 { "dacr0", DTT0 }, /* Data Access Control Register 0. */
3761 { "dacr1", DTT1 }, /* Data Access Control Register 0. */
3762
3763 /* mcf5200 versions of same. The ColdFire programmer's reference
3764 manual indicated that the order is 2,3,0,1, but Ken Rose
3765 <rose@netcom.com> says that 0,1,2,3 is the correct order. */
3766 { "acr0", ACR0 }, /* Access Control Unit 0. */
3767 { "acr1", ACR1 }, /* Access Control Unit 1. */
3768 { "acr2", ACR2 }, /* Access Control Unit 2. */
3769 { "acr3", ACR3 }, /* Access Control Unit 3. */
3770
3771 { "tc", TC }, /* MMU Translation Control Register. */
3772 { "tcr", TC },
3773
3774 { "mmusr", MMUSR }, /* MMU Status Register. */
3775 { "srp", SRP }, /* User Root Pointer. */
3776 { "urp", URP }, /* Supervisor Root Pointer. */
3777
3778 { "buscr", BUSCR },
3779 { "pcr", PCR },
3780
3781 { "rombar", ROMBAR }, /* ROM Base Address Register. */
3782 { "rambar0", RAMBAR0 }, /* ROM Base Address Register. */
3783 { "rambar1", RAMBAR1 }, /* ROM Base Address Register. */
3784 { "mbar", MBAR }, /* Module Base Address Register. */
3785
3786 { "mbar0", MBAR0 }, /* mcfv4e registers. */
3787 { "mbar1", MBAR1 }, /* mcfv4e registers. */
3788 { "rombar0", ROMBAR }, /* mcfv4e registers. */
3789 { "rombar1", ROMBAR1 }, /* mcfv4e registers. */
3790 { "mpcr", MPCR }, /* mcfv4e registers. */
3791 { "edrambar", EDRAMBAR }, /* mcfv4e registers. */
3792 { "secmbar", SECMBAR }, /* mcfv4e registers. */
3793 { "asid", TC }, /* mcfv4e registers. */
3794 { "mmubar", BUSCR }, /* mcfv4e registers. */
3795 { "pcr1u0", PCR1U0 }, /* mcfv4e registers. */
3796 { "pcr1l0", PCR1L0 }, /* mcfv4e registers. */
3797 { "pcr2u0", PCR2U0 }, /* mcfv4e registers. */
3798 { "pcr2l0", PCR2L0 }, /* mcfv4e registers. */
3799 { "pcr3u0", PCR3U0 }, /* mcfv4e registers. */
3800 { "pcr3l0", PCR3L0 }, /* mcfv4e registers. */
3801 { "pcr1u1", PCR1U1 }, /* mcfv4e registers. */
3802 { "pcr1l1", PCR1L1 }, /* mcfv4e registers. */
3803 { "pcr2u1", PCR2U1 }, /* mcfv4e registers. */
3804 { "pcr2l1", PCR2L1 }, /* mcfv4e registers. */
3805 { "pcr3u1", PCR3U1 }, /* mcfv4e registers. */
3806 { "pcr3l1", PCR3L1 }, /* mcfv4e registers. */
3807
3808 { "flashbar", FLASHBAR }, /* mcf528x registers. */
3809 { "rambar", RAMBAR }, /* mcf528x registers. */
3810
3811 { "mbar2", MBAR2 }, /* mcf5249 registers. */
3812 /* End of control registers. */
3813
3814 { "ac", AC },
3815 { "bc", BC },
3816 { "cal", CAL },
3817 { "crp", CRP },
3818 { "drp", DRP },
3819 { "pcsr", PCSR },
3820 { "psr", PSR },
3821 { "scc", SCC },
3822 { "val", VAL },
3823 { "bad0", BAD0 },
3824 { "bad1", BAD1 },
3825 { "bad2", BAD2 },
3826 { "bad3", BAD3 },
3827 { "bad4", BAD4 },
3828 { "bad5", BAD5 },
3829 { "bad6", BAD6 },
3830 { "bad7", BAD7 },
3831 { "bac0", BAC0 },
3832 { "bac1", BAC1 },
3833 { "bac2", BAC2 },
3834 { "bac3", BAC3 },
3835 { "bac4", BAC4 },
3836 { "bac5", BAC5 },
3837 { "bac6", BAC6 },
3838 { "bac7", BAC7 },
3839
3840 { "ic", IC },
3841 { "dc", DC },
3842 { "nc", NC },
3843
3844 { "tt0", TT0 },
3845 { "tt1", TT1 },
3846 /* 68ec030 versions of same. */
3847 { "ac0", TT0 },
3848 { "ac1", TT1 },
3849 /* 68ec030 access control unit, identical to 030 MMU status reg. */
3850 { "acusr", PSR },
3851
3852 /* Suppressed data and address registers. */
3853 { "zd0", ZDATA0 },
3854 { "zd1", ZDATA1 },
3855 { "zd2", ZDATA2 },
3856 { "zd3", ZDATA3 },
3857 { "zd4", ZDATA4 },
3858 { "zd5", ZDATA5 },
3859 { "zd6", ZDATA6 },
3860 { "zd7", ZDATA7 },
3861 { "za0", ZADDR0 },
3862 { "za1", ZADDR1 },
3863 { "za2", ZADDR2 },
3864 { "za3", ZADDR3 },
3865 { "za4", ZADDR4 },
3866 { "za5", ZADDR5 },
3867 { "za6", ZADDR6 },
3868 { "za7", ZADDR7 },
3869
3870 /* Upper and lower data and address registers, used by macw and msacw. */
3871 { "d0l", DATA0L },
3872 { "d1l", DATA1L },
3873 { "d2l", DATA2L },
3874 { "d3l", DATA3L },
3875 { "d4l", DATA4L },
3876 { "d5l", DATA5L },
3877 { "d6l", DATA6L },
3878 { "d7l", DATA7L },
3879
3880 { "a0l", ADDR0L },
3881 { "a1l", ADDR1L },
3882 { "a2l", ADDR2L },
3883 { "a3l", ADDR3L },
3884 { "a4l", ADDR4L },
3885 { "a5l", ADDR5L },
3886 { "a6l", ADDR6L },
3887 { "a7l", ADDR7L },
3888
3889 { "d0u", DATA0U },
3890 { "d1u", DATA1U },
3891 { "d2u", DATA2U },
3892 { "d3u", DATA3U },
3893 { "d4u", DATA4U },
3894 { "d5u", DATA5U },
3895 { "d6u", DATA6U },
3896 { "d7u", DATA7U },
3897
3898 { "a0u", ADDR0U },
3899 { "a1u", ADDR1U },
3900 { "a2u", ADDR2U },
3901 { "a3u", ADDR3U },
3902 { "a4u", ADDR4U },
3903 { "a5u", ADDR5U },
3904 { "a6u", ADDR6U },
3905 { "a7u", ADDR7U },
3906
3907 { 0, 0 }
3908 };
3909
3910 static void
3911 init_regtable (void)
3912 {
3913 int i;
3914 for (i = 0; init_table[i].name; i++)
3915 insert_reg (init_table[i].name, init_table[i].number);
3916 }
3917
3918 void
3919 md_assemble (char *str)
3920 {
3921 const char *er;
3922 short *fromP;
3923 char *toP = NULL;
3924 int m, n = 0;
3925 char *to_beg_P;
3926 int shorts_this_frag;
3927 fixS *fixP;
3928
3929 if (!selected_cpu && !selected_arch)
3930 {
3931 /* We've not selected an architecture yet. Set the default
3932 now. We do this lazily so that an initial .cpu or .arch directive
3933 can specify. */
3934 if (!m68k_set_cpu (TARGET_CPU, 1, 1))
3935 as_bad (_("unrecognized default cpu `%s'"), TARGET_CPU);
3936 }
3937 if (!initialized)
3938 m68k_init_arch ();
3939
3940 /* In MRI mode, the instruction and operands are separated by a
3941 space. Anything following the operands is a comment. The label
3942 has already been removed. */
3943 if (flag_mri)
3944 {
3945 char *s;
3946 int fields = 0;
3947 int infield = 0;
3948 int inquote = 0;
3949
3950 for (s = str; *s != '\0'; s++)
3951 {
3952 if ((*s == ' ' || *s == '\t') && ! inquote)
3953 {
3954 if (infield)
3955 {
3956 ++fields;
3957 if (fields >= 2)
3958 {
3959 *s = '\0';
3960 break;
3961 }
3962 infield = 0;
3963 }
3964 }
3965 else
3966 {
3967 if (! infield)
3968 infield = 1;
3969 if (*s == '\'')
3970 inquote = ! inquote;
3971 }
3972 }
3973 }
3974
3975 memset (&the_ins, '\0', sizeof (the_ins));
3976 m68k_ip (str);
3977 er = the_ins.error;
3978 if (!er)
3979 {
3980 for (n = 0; n < the_ins.numargs; n++)
3981 if (the_ins.operands[n].error)
3982 {
3983 er = the_ins.operands[n].error;
3984 break;
3985 }
3986 }
3987 if (er)
3988 {
3989 as_bad (_("%s -- statement `%s' ignored"), er, str);
3990 return;
3991 }
3992
3993 /* If there is a current label, record that it marks an instruction. */
3994 if (current_label != NULL)
3995 {
3996 current_label->text = 1;
3997 current_label = NULL;
3998 }
3999
4000 #ifdef OBJ_ELF
4001 /* Tie dwarf2 debug info to the address at the start of the insn. */
4002 dwarf2_emit_insn (0);
4003 #endif
4004
4005 if (the_ins.nfrag == 0)
4006 {
4007 /* No frag hacking involved; just put it out. */
4008 toP = frag_more (2 * the_ins.numo);
4009 fromP = &the_ins.opcode[0];
4010 for (m = the_ins.numo; m; --m)
4011 {
4012 md_number_to_chars (toP, (long) (*fromP), 2);
4013 toP += 2;
4014 fromP++;
4015 }
4016 /* Put out symbol-dependent info. */
4017 for (m = 0; m < the_ins.nrel; m++)
4018 {
4019 switch (the_ins.reloc[m].wid)
4020 {
4021 case 'B':
4022 n = 1;
4023 break;
4024 case 'b':
4025 n = 1;
4026 break;
4027 case '3':
4028 n = 1;
4029 break;
4030 case 'w':
4031 case 'W':
4032 n = 2;
4033 break;
4034 case 'l':
4035 n = 4;
4036 break;
4037 default:
4038 as_fatal (_("Don't know how to figure width of %c in md_assemble()"),
4039 the_ins.reloc[m].wid);
4040 }
4041
4042 fixP = fix_new_exp (frag_now,
4043 ((toP - frag_now->fr_literal)
4044 - the_ins.numo * 2 + the_ins.reloc[m].n),
4045 n,
4046 &the_ins.reloc[m].exp,
4047 the_ins.reloc[m].pcrel,
4048 get_reloc_code (n, the_ins.reloc[m].pcrel,
4049 the_ins.reloc[m].pic_reloc));
4050 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
4051 if (the_ins.reloc[m].wid == 'B')
4052 fixP->fx_signed = 1;
4053 }
4054 return;
4055 }
4056
4057 /* There's some frag hacking. */
4058 {
4059 /* Calculate the max frag size. */
4060 int wid;
4061
4062 wid = 2 * the_ins.fragb[0].fragoff;
4063 for (n = 1; n < the_ins.nfrag; n++)
4064 wid += 2 * (the_ins.numo - the_ins.fragb[n - 1].fragoff);
4065 /* frag_var part. */
4066 wid += 10;
4067 /* Make sure the whole insn fits in one chunk, in particular that
4068 the var part is attached, as we access one byte before the
4069 variable frag for byte branches. */
4070 frag_grow (wid);
4071 }
4072
4073 for (n = 0, fromP = &the_ins.opcode[0]; n < the_ins.nfrag; n++)
4074 {
4075 int wid;
4076
4077 if (n == 0)
4078 wid = 2 * the_ins.fragb[n].fragoff;
4079 else
4080 wid = 2 * (the_ins.numo - the_ins.fragb[n - 1].fragoff);
4081 toP = frag_more (wid);
4082 to_beg_P = toP;
4083 shorts_this_frag = 0;
4084 for (m = wid / 2; m; --m)
4085 {
4086 md_number_to_chars (toP, (long) (*fromP), 2);
4087 toP += 2;
4088 fromP++;
4089 shorts_this_frag++;
4090 }
4091 for (m = 0; m < the_ins.nrel; m++)
4092 {
4093 if ((the_ins.reloc[m].n) >= 2 * shorts_this_frag)
4094 {
4095 the_ins.reloc[m].n -= 2 * shorts_this_frag;
4096 break;
4097 }
4098 wid = the_ins.reloc[m].wid;
4099 if (wid == 0)
4100 continue;
4101 the_ins.reloc[m].wid = 0;
4102 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
4103
4104 fixP = fix_new_exp (frag_now,
4105 ((toP - frag_now->fr_literal)
4106 - the_ins.numo * 2 + the_ins.reloc[m].n),
4107 wid,
4108 &the_ins.reloc[m].exp,
4109 the_ins.reloc[m].pcrel,
4110 get_reloc_code (wid, the_ins.reloc[m].pcrel,
4111 the_ins.reloc[m].pic_reloc));
4112 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
4113 }
4114 (void) frag_var (rs_machine_dependent, 10, 0,
4115 (relax_substateT) (the_ins.fragb[n].fragty),
4116 the_ins.fragb[n].fadd, the_ins.fragb[n].foff, to_beg_P);
4117 }
4118 n = (the_ins.numo - the_ins.fragb[n - 1].fragoff);
4119 shorts_this_frag = 0;
4120 if (n)
4121 {
4122 toP = frag_more (n * 2);
4123 while (n--)
4124 {
4125 md_number_to_chars (toP, (long) (*fromP), 2);
4126 toP += 2;
4127 fromP++;
4128 shorts_this_frag++;
4129 }
4130 }
4131 for (m = 0; m < the_ins.nrel; m++)
4132 {
4133 int wid;
4134
4135 wid = the_ins.reloc[m].wid;
4136 if (wid == 0)
4137 continue;
4138 the_ins.reloc[m].wid = 0;
4139 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
4140
4141 fixP = fix_new_exp (frag_now,
4142 ((the_ins.reloc[m].n + toP - frag_now->fr_literal)
4143 - shorts_this_frag * 2),
4144 wid,
4145 &the_ins.reloc[m].exp,
4146 the_ins.reloc[m].pcrel,
4147 get_reloc_code (wid, the_ins.reloc[m].pcrel,
4148 the_ins.reloc[m].pic_reloc));
4149 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
4150 }
4151 }
4152
4153 /* Comparison function used by qsort to rank the opcode entries by name. */
4154
4155 static int
4156 m68k_compare_opcode (const void * v1, const void * v2)
4157 {
4158 struct m68k_opcode * op1, * op2;
4159 int ret;
4160
4161 if (v1 == v2)
4162 return 0;
4163
4164 op1 = *(struct m68k_opcode **) v1;
4165 op2 = *(struct m68k_opcode **) v2;
4166
4167 /* Compare the two names. If different, return the comparison.
4168 If the same, return the order they are in the opcode table. */
4169 ret = strcmp (op1->name, op2->name);
4170 if (ret)
4171 return ret;
4172 if (op1 < op2)
4173 return -1;
4174 return 1;
4175 }
4176
4177 void
4178 md_begin (void)
4179 {
4180 const struct m68k_opcode *ins;
4181 struct m68k_incant *hack, *slak;
4182 const char *retval = 0; /* Empty string, or error msg text. */
4183 int i;
4184
4185 /* Set up hash tables with 68000 instructions.
4186 similar to what the vax assembler does. */
4187 /* RMS claims the thing to do is take the m68k-opcode.h table, and make
4188 a copy of it at runtime, adding in the information we want but isn't
4189 there. I think it'd be better to have an awk script hack the table
4190 at compile time. Or even just xstr the table and use it as-is. But
4191 my lord ghod hath spoken, so we do it this way. Excuse the ugly var
4192 names. */
4193
4194 if (flag_mri)
4195 {
4196 flag_reg_prefix_optional = 1;
4197 m68k_abspcadd = 1;
4198 if (! m68k_rel32_from_cmdline)
4199 m68k_rel32 = 0;
4200 }
4201
4202 /* First sort the opcode table into alphabetical order to seperate
4203 the order that the assembler wants to see the opcodes from the
4204 order that the disassembler wants to see them. */
4205 m68k_sorted_opcodes = xmalloc (m68k_numopcodes * sizeof (* m68k_sorted_opcodes));
4206 if (!m68k_sorted_opcodes)
4207 as_fatal (_("Internal Error: Can't allocate m68k_sorted_opcodes of size %d"),
4208 m68k_numopcodes * ((int) sizeof (* m68k_sorted_opcodes)));
4209
4210 for (i = m68k_numopcodes; i--;)
4211 m68k_sorted_opcodes[i] = m68k_opcodes + i;
4212
4213 qsort (m68k_sorted_opcodes, m68k_numopcodes,
4214 sizeof (m68k_sorted_opcodes[0]), m68k_compare_opcode);
4215
4216 op_hash = hash_new ();
4217
4218 obstack_begin (&robyn, 4000);
4219 for (i = 0; i < m68k_numopcodes; i++)
4220 {
4221 hack = slak = (struct m68k_incant *) obstack_alloc (&robyn, sizeof (struct m68k_incant));
4222 do
4223 {
4224 ins = m68k_sorted_opcodes[i];
4225
4226 /* We *could* ignore insns that don't match our
4227 arch here by just leaving them out of the hash. */
4228 slak->m_operands = ins->args;
4229 slak->m_opnum = strlen (slak->m_operands) / 2;
4230 slak->m_arch = ins->arch;
4231 slak->m_opcode = ins->opcode;
4232 /* This is kludgey. */
4233 slak->m_codenum = ((ins->match) & 0xffffL) ? 2 : 1;
4234 if (i + 1 != m68k_numopcodes
4235 && !strcmp (ins->name, m68k_sorted_opcodes[i + 1]->name))
4236 {
4237 slak->m_next = obstack_alloc (&robyn, sizeof (struct m68k_incant));
4238 i++;
4239 }
4240 else
4241 slak->m_next = 0;
4242 slak = slak->m_next;
4243 }
4244 while (slak);
4245
4246 retval = hash_insert (op_hash, ins->name, (char *) hack);
4247 if (retval)
4248 as_fatal (_("Internal Error: Can't hash %s: %s"), ins->name, retval);
4249 }
4250
4251 for (i = 0; i < m68k_numaliases; i++)
4252 {
4253 const char *name = m68k_opcode_aliases[i].primary;
4254 const char *alias = m68k_opcode_aliases[i].alias;
4255 PTR val = hash_find (op_hash, name);
4256
4257 if (!val)
4258 as_fatal (_("Internal Error: Can't find %s in hash table"), name);
4259 retval = hash_insert (op_hash, alias, val);
4260 if (retval)
4261 as_fatal (_("Internal Error: Can't hash %s: %s"), alias, retval);
4262 }
4263
4264 /* In MRI mode, all unsized branches are variable sized. Normally,
4265 they are word sized. */
4266 if (flag_mri)
4267 {
4268 static struct m68k_opcode_alias mri_aliases[] =
4269 {
4270 { "bhi", "jhi", },
4271 { "bls", "jls", },
4272 { "bcc", "jcc", },
4273 { "bcs", "jcs", },
4274 { "bne", "jne", },
4275 { "beq", "jeq", },
4276 { "bvc", "jvc", },
4277 { "bvs", "jvs", },
4278 { "bpl", "jpl", },
4279 { "bmi", "jmi", },
4280 { "bge", "jge", },
4281 { "blt", "jlt", },
4282 { "bgt", "jgt", },
4283 { "ble", "jle", },
4284 { "bra", "jra", },
4285 { "bsr", "jbsr", },
4286 };
4287
4288 for (i = 0;
4289 i < (int) (sizeof mri_aliases / sizeof mri_aliases[0]);
4290 i++)
4291 {
4292 const char *name = mri_aliases[i].primary;
4293 const char *alias = mri_aliases[i].alias;
4294 PTR val = hash_find (op_hash, name);
4295
4296 if (!val)
4297 as_fatal (_("Internal Error: Can't find %s in hash table"), name);
4298 retval = hash_jam (op_hash, alias, val);
4299 if (retval)
4300 as_fatal (_("Internal Error: Can't hash %s: %s"), alias, retval);
4301 }
4302 }
4303
4304 for (i = 0; i < (int) sizeof (notend_table); i++)
4305 {
4306 notend_table[i] = 0;
4307 alt_notend_table[i] = 0;
4308 }
4309
4310 notend_table[','] = 1;
4311 notend_table['{'] = 1;
4312 notend_table['}'] = 1;
4313 alt_notend_table['a'] = 1;
4314 alt_notend_table['A'] = 1;
4315 alt_notend_table['d'] = 1;
4316 alt_notend_table['D'] = 1;
4317 alt_notend_table['#'] = 1;
4318 alt_notend_table['&'] = 1;
4319 alt_notend_table['f'] = 1;
4320 alt_notend_table['F'] = 1;
4321 #ifdef REGISTER_PREFIX
4322 alt_notend_table[REGISTER_PREFIX] = 1;
4323 #endif
4324
4325 /* We need to put '(' in alt_notend_table to handle
4326 cas2 %d0:%d2,%d3:%d4,(%a0):(%a1) */
4327 alt_notend_table['('] = 1;
4328
4329 /* We need to put '@' in alt_notend_table to handle
4330 cas2 %d0:%d2,%d3:%d4,@(%d0):@(%d1) */
4331 alt_notend_table['@'] = 1;
4332
4333 /* We need to put digits in alt_notend_table to handle
4334 bfextu %d0{24:1},%d0 */
4335 alt_notend_table['0'] = 1;
4336 alt_notend_table['1'] = 1;
4337 alt_notend_table['2'] = 1;
4338 alt_notend_table['3'] = 1;
4339 alt_notend_table['4'] = 1;
4340 alt_notend_table['5'] = 1;
4341 alt_notend_table['6'] = 1;
4342 alt_notend_table['7'] = 1;
4343 alt_notend_table['8'] = 1;
4344 alt_notend_table['9'] = 1;
4345
4346 #ifndef MIT_SYNTAX_ONLY
4347 /* Insert pseudo ops, these have to go into the opcode table since
4348 gas expects pseudo ops to start with a dot. */
4349 {
4350 int n = 0;
4351
4352 while (mote_pseudo_table[n].poc_name)
4353 {
4354 hack = obstack_alloc (&robyn, sizeof (struct m68k_incant));
4355 hash_insert (op_hash,
4356 mote_pseudo_table[n].poc_name, (char *) hack);
4357 hack->m_operands = 0;
4358 hack->m_opnum = n;
4359 n++;
4360 }
4361 }
4362 #endif
4363
4364 init_regtable ();
4365
4366 #ifdef OBJ_ELF
4367 record_alignment (text_section, 2);
4368 record_alignment (data_section, 2);
4369 record_alignment (bss_section, 2);
4370 #endif
4371 }
4372
4373 \f
4374 /* This is called when a label is defined. */
4375
4376 void
4377 m68k_frob_label (symbolS *sym)
4378 {
4379 struct label_line *n;
4380
4381 n = (struct label_line *) xmalloc (sizeof *n);
4382 n->next = labels;
4383 n->label = sym;
4384 as_where (&n->file, &n->line);
4385 n->text = 0;
4386 labels = n;
4387 current_label = n;
4388
4389 #ifdef OBJ_ELF
4390 dwarf2_emit_label (sym);
4391 #endif
4392 }
4393
4394 /* This is called when a value that is not an instruction is emitted. */
4395
4396 void
4397 m68k_flush_pending_output (void)
4398 {
4399 current_label = NULL;
4400 }
4401
4402 /* This is called at the end of the assembly, when the final value of
4403 the label is known. We warn if this is a text symbol aligned at an
4404 odd location. */
4405
4406 void
4407 m68k_frob_symbol (symbolS *sym)
4408 {
4409 if (S_GET_SEGMENT (sym) == reg_section
4410 && (int) S_GET_VALUE (sym) < 0)
4411 {
4412 S_SET_SEGMENT (sym, absolute_section);
4413 S_SET_VALUE (sym, ~(int)S_GET_VALUE (sym));
4414 }
4415 else if ((S_GET_VALUE (sym) & 1) != 0)
4416 {
4417 struct label_line *l;
4418
4419 for (l = labels; l != NULL; l = l->next)
4420 {
4421 if (l->label == sym)
4422 {
4423 if (l->text)
4424 as_warn_where (l->file, l->line,
4425 _("text label `%s' aligned to odd boundary"),
4426 S_GET_NAME (sym));
4427 break;
4428 }
4429 }
4430 }
4431 }
4432 \f
4433 /* This is called if we go in or out of MRI mode because of the .mri
4434 pseudo-op. */
4435
4436 void
4437 m68k_mri_mode_change (int on)
4438 {
4439 if (on)
4440 {
4441 if (! flag_reg_prefix_optional)
4442 {
4443 flag_reg_prefix_optional = 1;
4444 #ifdef REGISTER_PREFIX
4445 init_regtable ();
4446 #endif
4447 }
4448 m68k_abspcadd = 1;
4449 if (! m68k_rel32_from_cmdline)
4450 m68k_rel32 = 0;
4451 }
4452 else
4453 {
4454 if (! reg_prefix_optional_seen)
4455 {
4456 #ifdef REGISTER_PREFIX_OPTIONAL
4457 flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
4458 #else
4459 flag_reg_prefix_optional = 0;
4460 #endif
4461 #ifdef REGISTER_PREFIX
4462 init_regtable ();
4463 #endif
4464 }
4465 m68k_abspcadd = 0;
4466 if (! m68k_rel32_from_cmdline)
4467 m68k_rel32 = 1;
4468 }
4469 }
4470
4471 /* Equal to MAX_PRECISION in atof-ieee.c. */
4472 #define MAX_LITTLENUMS 6
4473
4474 /* Turn a string in input_line_pointer into a floating point constant
4475 of type TYPE, and store the appropriate bytes in *LITP. The number
4476 of LITTLENUMS emitted is stored in *SIZEP. An error message is
4477 returned, or NULL on OK. */
4478
4479 char *
4480 md_atof (int type, char *litP, int *sizeP)
4481 {
4482 int prec;
4483 LITTLENUM_TYPE words[MAX_LITTLENUMS];
4484 LITTLENUM_TYPE *wordP;
4485 char *t;
4486
4487 switch (type)
4488 {
4489 case 'f':
4490 case 'F':
4491 case 's':
4492 case 'S':
4493 prec = 2;
4494 break;
4495
4496 case 'd':
4497 case 'D':
4498 case 'r':
4499 case 'R':
4500 prec = 4;
4501 break;
4502
4503 case 'x':
4504 case 'X':
4505 prec = 6;
4506 break;
4507
4508 case 'p':
4509 case 'P':
4510 prec = 6;
4511 break;
4512
4513 default:
4514 *sizeP = 0;
4515 return _("Bad call to MD_ATOF()");
4516 }
4517 t = atof_ieee (input_line_pointer, type, words);
4518 if (t)
4519 input_line_pointer = t;
4520
4521 *sizeP = prec * sizeof (LITTLENUM_TYPE);
4522 for (wordP = words; prec--;)
4523 {
4524 md_number_to_chars (litP, (long) (*wordP++), sizeof (LITTLENUM_TYPE));
4525 litP += sizeof (LITTLENUM_TYPE);
4526 }
4527 return 0;
4528 }
4529
4530 void
4531 md_number_to_chars (char *buf, valueT val, int n)
4532 {
4533 number_to_chars_bigendian (buf, val, n);
4534 }
4535
4536 void
4537 md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
4538 {
4539 offsetT val = *valP;
4540 addressT upper_limit;
4541 offsetT lower_limit;
4542
4543 /* This is unnecessary but it convinces the native rs6000 compiler
4544 to generate the code we want. */
4545 char *buf = fixP->fx_frag->fr_literal;
4546 buf += fixP->fx_where;
4547 /* End ibm compiler workaround. */
4548
4549 val = SEXT (val);
4550
4551 if (fixP->fx_addsy == NULL && fixP->fx_pcrel == 0)
4552 fixP->fx_done = 1;
4553
4554 #ifdef OBJ_ELF
4555 if (fixP->fx_addsy)
4556 {
4557 memset (buf, 0, fixP->fx_size);
4558 fixP->fx_addnumber = val; /* Remember value for emit_reloc. */
4559
4560 if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
4561 && !S_IS_DEFINED (fixP->fx_addsy)
4562 && !S_IS_WEAK (fixP->fx_addsy))
4563 S_SET_WEAK (fixP->fx_addsy);
4564 return;
4565 }
4566 #endif
4567
4568 if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
4569 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
4570 return;
4571
4572 switch (fixP->fx_size)
4573 {
4574 /* The cast to offsetT below are necessary to make code
4575 correct for machines where ints are smaller than offsetT. */
4576 case 1:
4577 *buf++ = val;
4578 upper_limit = 0x7f;
4579 lower_limit = - (offsetT) 0x80;
4580 break;
4581 case 2:
4582 *buf++ = (val >> 8);
4583 *buf++ = val;
4584 upper_limit = 0x7fff;
4585 lower_limit = - (offsetT) 0x8000;
4586 break;
4587 case 4:
4588 *buf++ = (val >> 24);
4589 *buf++ = (val >> 16);
4590 *buf++ = (val >> 8);
4591 *buf++ = val;
4592 upper_limit = 0x7fffffff;
4593 lower_limit = - (offsetT) 0x7fffffff - 1; /* Avoid constant overflow. */
4594 break;
4595 default:
4596 BAD_CASE (fixP->fx_size);
4597 }
4598
4599 /* Fix up a negative reloc. */
4600 if (fixP->fx_addsy == NULL && fixP->fx_subsy != NULL)
4601 {
4602 fixP->fx_addsy = fixP->fx_subsy;
4603 fixP->fx_subsy = NULL;
4604 fixP->fx_tcbit = 1;
4605 }
4606
4607 /* For non-pc-relative values, it's conceivable we might get something
4608 like "0xff" for a byte field. So extend the upper part of the range
4609 to accept such numbers. We arbitrarily disallow "-0xff" or "0xff+0xff",
4610 so that we can do any range checking at all. */
4611 if (! fixP->fx_pcrel && ! fixP->fx_signed)
4612 upper_limit = upper_limit * 2 + 1;
4613
4614 if ((addressT) val > upper_limit
4615 && (val > 0 || val < lower_limit))
4616 as_bad_where (fixP->fx_file, fixP->fx_line, _("value out of range"));
4617
4618 /* A one byte PC-relative reloc means a short branch. We can't use
4619 a short branch with a value of 0 or -1, because those indicate
4620 different opcodes (branches with longer offsets). fixup_segment
4621 in write.c may have clobbered fx_pcrel, so we need to examine the
4622 reloc type. */
4623 if ((fixP->fx_pcrel
4624 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
4625 && fixP->fx_size == 1
4626 && (fixP->fx_addsy == NULL
4627 || S_IS_DEFINED (fixP->fx_addsy))
4628 && (val == 0 || val == -1))
4629 as_bad_where (fixP->fx_file, fixP->fx_line, _("invalid byte branch offset"));
4630 }
4631
4632 /* *fragP has been relaxed to its final size, and now needs to have
4633 the bytes inside it modified to conform to the new size There is UGLY
4634 MAGIC here. ..
4635 */
4636 static void
4637 md_convert_frag_1 (fragS *fragP)
4638 {
4639 long disp;
4640 fixS *fixP;
4641
4642 /* Address in object code of the displacement. */
4643 register int object_address = fragP->fr_fix + fragP->fr_address;
4644
4645 /* Address in gas core of the place to store the displacement. */
4646 /* This convinces the native rs6000 compiler to generate the code we
4647 want. */
4648 register char *buffer_address = fragP->fr_literal;
4649 buffer_address += fragP->fr_fix;
4650 /* End ibm compiler workaround. */
4651
4652 /* The displacement of the address, from current location. */
4653 disp = fragP->fr_symbol ? S_GET_VALUE (fragP->fr_symbol) : 0;
4654 disp = (disp + fragP->fr_offset) - object_address;
4655
4656 switch (fragP->fr_subtype)
4657 {
4658 case TAB (BRANCHBWL, BYTE):
4659 case TAB (BRABSJUNC, BYTE):
4660 case TAB (BRABSJCOND, BYTE):
4661 case TAB (BRANCHBW, BYTE):
4662 know (issbyte (disp));
4663 if (disp == 0)
4664 as_bad_where (fragP->fr_file, fragP->fr_line,
4665 _("short branch with zero offset: use :w"));
4666 fixP = fix_new (fragP, fragP->fr_fix - 1, 1, fragP->fr_symbol,
4667 fragP->fr_offset, 1, RELAX_RELOC_PC8);
4668 fixP->fx_pcrel_adjust = -1;
4669 break;
4670 case TAB (BRANCHBWL, SHORT):
4671 case TAB (BRABSJUNC, SHORT):
4672 case TAB (BRABSJCOND, SHORT):
4673 case TAB (BRANCHBW, SHORT):
4674 fragP->fr_opcode[1] = 0x00;
4675 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, fragP->fr_offset,
4676 1, RELAX_RELOC_PC16);
4677 fragP->fr_fix += 2;
4678 break;
4679 case TAB (BRANCHBWL, LONG):
4680 fragP->fr_opcode[1] = (char) 0xFF;
4681 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
4682 1, RELAX_RELOC_PC32);
4683 fragP->fr_fix += 4;
4684 break;
4685 case TAB (BRABSJUNC, LONG):
4686 if (fragP->fr_opcode[0] == 0x61) /* jbsr */
4687 {
4688 if (flag_keep_pcrel)
4689 as_fatal (_("Tried to convert PC relative BSR to absolute JSR"));
4690 fragP->fr_opcode[0] = 0x4E;
4691 fragP->fr_opcode[1] = (char) 0xB9; /* JSR with ABSL LONG operand. */
4692 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
4693 0, RELAX_RELOC_ABS32);
4694 fragP->fr_fix += 4;
4695 }
4696 else if (fragP->fr_opcode[0] == 0x60) /* jbra */
4697 {
4698 if (flag_keep_pcrel)
4699 as_fatal (_("Tried to convert PC relative branch to absolute jump"));
4700 fragP->fr_opcode[0] = 0x4E;
4701 fragP->fr_opcode[1] = (char) 0xF9; /* JMP with ABSL LONG operand. */
4702 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
4703 0, RELAX_RELOC_ABS32);
4704 fragP->fr_fix += 4;
4705 }
4706 else
4707 {
4708 /* This cannot happen, because jbsr and jbra are the only two
4709 unconditional branches. */
4710 abort ();
4711 }
4712 break;
4713 case TAB (BRABSJCOND, LONG):
4714 if (flag_keep_pcrel)
4715 as_fatal (_("Tried to convert PC relative conditional branch to absolute jump"));
4716
4717 /* Only Bcc 68000 instructions can come here
4718 Change bcc into b!cc/jmp absl long. */
4719 fragP->fr_opcode[0] ^= 0x01; /* Invert bcc. */
4720 fragP->fr_opcode[1] = 0x06; /* Branch offset = 6. */
4721
4722 /* JF: these used to be fr_opcode[2,3], but they may be in a
4723 different frag, in which case referring to them is a no-no.
4724 Only fr_opcode[0,1] are guaranteed to work. */
4725 *buffer_address++ = 0x4e; /* put in jmp long (0x4ef9) */
4726 *buffer_address++ = (char) 0xf9;
4727 fragP->fr_fix += 2; /* Account for jmp instruction. */
4728 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4729 fragP->fr_offset, 0, RELAX_RELOC_ABS32);
4730 fragP->fr_fix += 4;
4731 break;
4732 case TAB (FBRANCH, SHORT):
4733 know ((fragP->fr_opcode[1] & 0x40) == 0);
4734 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, fragP->fr_offset,
4735 1, RELAX_RELOC_PC16);
4736 fragP->fr_fix += 2;
4737 break;
4738 case TAB (FBRANCH, LONG):
4739 fragP->fr_opcode[1] |= 0x40; /* Turn on LONG bit. */
4740 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
4741 1, RELAX_RELOC_PC32);
4742 fragP->fr_fix += 4;
4743 break;
4744 case TAB (DBCCLBR, SHORT):
4745 case TAB (DBCCABSJ, SHORT):
4746 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, fragP->fr_offset,
4747 1, RELAX_RELOC_PC16);
4748 fragP->fr_fix += 2;
4749 break;
4750 case TAB (DBCCLBR, LONG):
4751 /* Only DBcc instructions can come here.
4752 Change dbcc into dbcc/bral.
4753 JF: these used to be fr_opcode[2-7], but that's wrong. */
4754 if (flag_keep_pcrel)
4755 as_fatal (_("Tried to convert DBcc to absolute jump"));
4756
4757 *buffer_address++ = 0x00; /* Branch offset = 4. */
4758 *buffer_address++ = 0x04;
4759 *buffer_address++ = 0x60; /* Put in bra pc+6. */
4760 *buffer_address++ = 0x06;
4761 *buffer_address++ = 0x60; /* Put in bral (0x60ff). */
4762 *buffer_address++ = (char) 0xff;
4763
4764 fragP->fr_fix += 6; /* Account for bra/jmp instructions. */
4765 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset, 1,
4766 RELAX_RELOC_PC32);
4767 fragP->fr_fix += 4;
4768 break;
4769 case TAB (DBCCABSJ, LONG):
4770 /* Only DBcc instructions can come here.
4771 Change dbcc into dbcc/jmp.
4772 JF: these used to be fr_opcode[2-7], but that's wrong. */
4773 if (flag_keep_pcrel)
4774 as_fatal (_("Tried to convert PC relative conditional branch to absolute jump"));
4775
4776 *buffer_address++ = 0x00; /* Branch offset = 4. */
4777 *buffer_address++ = 0x04;
4778 *buffer_address++ = 0x60; /* Put in bra pc + 6. */
4779 *buffer_address++ = 0x06;
4780 *buffer_address++ = 0x4e; /* Put in jmp long (0x4ef9). */
4781 *buffer_address++ = (char) 0xf9;
4782
4783 fragP->fr_fix += 6; /* Account for bra/jmp instructions. */
4784 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset, 0,
4785 RELAX_RELOC_ABS32);
4786 fragP->fr_fix += 4;
4787 break;
4788 case TAB (PCREL1632, SHORT):
4789 fragP->fr_opcode[1] &= ~0x3F;
4790 fragP->fr_opcode[1] |= 0x3A; /* 072 - mode 7.2 */
4791 fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
4792 fragP->fr_offset, 1, RELAX_RELOC_PC16);
4793 fragP->fr_fix += 2;
4794 break;
4795 case TAB (PCREL1632, LONG):
4796 /* Already set to mode 7.3; this indicates: PC indirect with
4797 suppressed index, 32-bit displacement. */
4798 *buffer_address++ = 0x01;
4799 *buffer_address++ = 0x70;
4800 fragP->fr_fix += 2;
4801 fixP = fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
4802 fragP->fr_offset, 1, RELAX_RELOC_PC32);
4803 fixP->fx_pcrel_adjust = 2;
4804 fragP->fr_fix += 4;
4805 break;
4806 case TAB (PCINDEX, BYTE):
4807 assert (fragP->fr_fix >= 2);
4808 buffer_address[-2] &= ~1;
4809 fixP = fix_new (fragP, fragP->fr_fix - 1, 1, fragP->fr_symbol,
4810 fragP->fr_offset, 1, RELAX_RELOC_PC8);
4811 fixP->fx_pcrel_adjust = 1;
4812 break;
4813 case TAB (PCINDEX, SHORT):
4814 assert (fragP->fr_fix >= 2);
4815 buffer_address[-2] |= 0x1;
4816 buffer_address[-1] = 0x20;
4817 fixP = fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
4818 fragP->fr_offset, 1, RELAX_RELOC_PC16);
4819 fixP->fx_pcrel_adjust = 2;
4820 fragP->fr_fix += 2;
4821 break;
4822 case TAB (PCINDEX, LONG):
4823 assert (fragP->fr_fix >= 2);
4824 buffer_address[-2] |= 0x1;
4825 buffer_address[-1] = 0x30;
4826 fixP = fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
4827 fragP->fr_offset, 1, RELAX_RELOC_PC32);
4828 fixP->fx_pcrel_adjust = 2;
4829 fragP->fr_fix += 4;
4830 break;
4831 case TAB (ABSTOPCREL, SHORT):
4832 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, fragP->fr_offset,
4833 1, RELAX_RELOC_PC16);
4834 fragP->fr_fix += 2;
4835 break;
4836 case TAB (ABSTOPCREL, LONG):
4837 if (flag_keep_pcrel)
4838 as_fatal (_("Tried to convert PC relative conditional branch to absolute jump"));
4839 /* The thing to do here is force it to ABSOLUTE LONG, since
4840 ABSTOPCREL is really trying to shorten an ABSOLUTE address anyway. */
4841 if ((fragP->fr_opcode[1] & 0x3F) != 0x3A)
4842 abort ();
4843 fragP->fr_opcode[1] &= ~0x3F;
4844 fragP->fr_opcode[1] |= 0x39; /* Mode 7.1 */
4845 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
4846 0, RELAX_RELOC_ABS32);
4847 fragP->fr_fix += 4;
4848 break;
4849 }
4850 }
4851
4852 void
4853 md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED,
4854 segT sec ATTRIBUTE_UNUSED,
4855 fragS *fragP)
4856 {
4857 md_convert_frag_1 (fragP);
4858 }
4859
4860 /* Force truly undefined symbols to their maximum size, and generally set up
4861 the frag list to be relaxed
4862 */
4863 int
4864 md_estimate_size_before_relax (fragS *fragP, segT segment)
4865 {
4866 /* Handle SZ_UNDEF first, it can be changed to BYTE or SHORT. */
4867 switch (fragP->fr_subtype)
4868 {
4869 case TAB (BRANCHBWL, SZ_UNDEF):
4870 case TAB (BRABSJUNC, SZ_UNDEF):
4871 case TAB (BRABSJCOND, SZ_UNDEF):
4872 {
4873 if (S_GET_SEGMENT (fragP->fr_symbol) == segment
4874 && relaxable_symbol (fragP->fr_symbol))
4875 {
4876 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE);
4877 }
4878 else if (flag_short_refs)
4879 {
4880 /* Symbol is undefined and we want short ref. */
4881 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
4882 }
4883 else
4884 {
4885 /* Symbol is still undefined. Make it LONG. */
4886 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), LONG);
4887 }
4888 break;
4889 }
4890
4891 case TAB (BRANCHBW, SZ_UNDEF):
4892 {
4893 if (S_GET_SEGMENT (fragP->fr_symbol) == segment
4894 && relaxable_symbol (fragP->fr_symbol))
4895 {
4896 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE);
4897 }
4898 else
4899 {
4900 /* Symbol is undefined and we don't have long branches. */
4901 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
4902 }
4903 break;
4904 }
4905
4906 case TAB (FBRANCH, SZ_UNDEF):
4907 case TAB (DBCCLBR, SZ_UNDEF):
4908 case TAB (DBCCABSJ, SZ_UNDEF):
4909 case TAB (PCREL1632, SZ_UNDEF):
4910 {
4911 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
4912 && relaxable_symbol (fragP->fr_symbol))
4913 || flag_short_refs)
4914 {
4915 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
4916 }
4917 else
4918 {
4919 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), LONG);
4920 }
4921 break;
4922 }
4923
4924 case TAB (PCINDEX, SZ_UNDEF):
4925 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
4926 && relaxable_symbol (fragP->fr_symbol)))
4927 {
4928 fragP->fr_subtype = TAB (PCINDEX, BYTE);
4929 }
4930 else
4931 {
4932 fragP->fr_subtype = TAB (PCINDEX, LONG);
4933 }
4934 break;
4935
4936 case TAB (ABSTOPCREL, SZ_UNDEF):
4937 {
4938 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
4939 && relaxable_symbol (fragP->fr_symbol)))
4940 {
4941 fragP->fr_subtype = TAB (ABSTOPCREL, SHORT);
4942 }
4943 else
4944 {
4945 fragP->fr_subtype = TAB (ABSTOPCREL, LONG);
4946 }
4947 break;
4948 }
4949
4950 default:
4951 break;
4952 }
4953
4954 /* Now that SZ_UNDEF are taken care of, check others. */
4955 switch (fragP->fr_subtype)
4956 {
4957 case TAB (BRANCHBWL, BYTE):
4958 case TAB (BRABSJUNC, BYTE):
4959 case TAB (BRABSJCOND, BYTE):
4960 case TAB (BRANCHBW, BYTE):
4961 /* We can't do a short jump to the next instruction, so in that
4962 case we force word mode. If the symbol is at the start of a
4963 frag, and it is the next frag with any data in it (usually
4964 this is just the next frag, but assembler listings may
4965 introduce empty frags), we must use word mode. */
4966 if (fragP->fr_symbol)
4967 {
4968 fragS *sym_frag;
4969
4970 sym_frag = symbol_get_frag (fragP->fr_symbol);
4971 if (S_GET_VALUE (fragP->fr_symbol) == sym_frag->fr_address)
4972 {
4973 fragS *l;
4974
4975 for (l = fragP->fr_next; l && l != sym_frag; l = l->fr_next)
4976 if (l->fr_fix != 0)
4977 break;
4978 if (l == sym_frag)
4979 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
4980 }
4981 }
4982 break;
4983 default:
4984 break;
4985 }
4986 return md_relax_table[fragP->fr_subtype].rlx_length;
4987 }
4988
4989 #if defined(OBJ_AOUT) | defined(OBJ_BOUT)
4990 /* the bit-field entries in the relocation_info struct plays hell
4991 with the byte-order problems of cross-assembly. So as a hack,
4992 I added this mach. dependent ri twiddler. Ugly, but it gets
4993 you there. -KWK */
4994 /* on m68k: first 4 bytes are normal unsigned long, next three bytes
4995 are symbolnum, most sig. byte first. Last byte is broken up with
4996 bit 7 as pcrel, bits 6 & 5 as length, bit 4 as pcrel, and the lower
4997 nibble as nuthin. (on Sun 3 at least) */
4998 /* Translate the internal relocation information into target-specific
4999 format. */
5000 #ifdef comment
5001 void
5002 md_ri_to_chars (char *the_bytes, struct reloc_info_generic *ri)
5003 {
5004 /* This is easy. */
5005 md_number_to_chars (the_bytes, ri->r_address, 4);
5006 /* Now the fun stuff. */
5007 the_bytes[4] = (ri->r_symbolnum >> 16) & 0x0ff;
5008 the_bytes[5] = (ri->r_symbolnum >> 8) & 0x0ff;
5009 the_bytes[6] = ri->r_symbolnum & 0x0ff;
5010 the_bytes[7] = (((ri->r_pcrel << 7) & 0x80)
5011 | ((ri->r_length << 5) & 0x60)
5012 | ((ri->r_extern << 4) & 0x10));
5013 }
5014
5015 #endif
5016
5017 #endif /* OBJ_AOUT or OBJ_BOUT */
5018
5019 #ifndef WORKING_DOT_WORD
5020 int md_short_jump_size = 4;
5021 int md_long_jump_size = 6;
5022
5023 void
5024 md_create_short_jump (char *ptr, addressT from_addr, addressT to_addr,
5025 fragS *frag ATTRIBUTE_UNUSED,
5026 symbolS *to_symbol ATTRIBUTE_UNUSED)
5027 {
5028 valueT offset;
5029
5030 offset = to_addr - (from_addr + 2);
5031
5032 md_number_to_chars (ptr, (valueT) 0x6000, 2);
5033 md_number_to_chars (ptr + 2, (valueT) offset, 2);
5034 }
5035
5036 void
5037 md_create_long_jump (char *ptr, addressT from_addr, addressT to_addr,
5038 fragS *frag, symbolS *to_symbol)
5039 {
5040 valueT offset;
5041
5042 if (!HAVE_LONG_BRANCH (current_architecture))
5043 {
5044 if (flag_keep_pcrel)
5045 as_fatal (_("Tried to convert PC relative branch to absolute jump"));
5046 offset = to_addr - S_GET_VALUE (to_symbol);
5047 md_number_to_chars (ptr, (valueT) 0x4EF9, 2);
5048 md_number_to_chars (ptr + 2, (valueT) offset, 4);
5049 fix_new (frag, (ptr + 2) - frag->fr_literal, 4, to_symbol, (offsetT) 0,
5050 0, NO_RELOC);
5051 }
5052 else
5053 {
5054 offset = to_addr - (from_addr + 2);
5055 md_number_to_chars (ptr, (valueT) 0x60ff, 2);
5056 md_number_to_chars (ptr + 2, (valueT) offset, 4);
5057 }
5058 }
5059
5060 #endif
5061
5062 /* Different values of OK tell what its OK to return. Things that
5063 aren't OK are an error (what a shock, no?)
5064
5065 0: Everything is OK
5066 10: Absolute 1:8 only
5067 20: Absolute 0:7 only
5068 30: absolute 0:15 only
5069 40: Absolute 0:31 only
5070 50: absolute 0:127 only
5071 55: absolute -64:63 only
5072 60: absolute -128:127 only
5073 70: absolute 0:4095 only
5074 80: absolute -1, 1:7 only
5075 90: No bignums. */
5076
5077 static int
5078 get_num (struct m68k_exp *exp, int ok)
5079 {
5080 if (exp->exp.X_op == O_absent)
5081 {
5082 /* Do the same thing the VAX asm does. */
5083 op (exp) = O_constant;
5084 adds (exp) = 0;
5085 subs (exp) = 0;
5086 offs (exp) = 0;
5087 if (ok == 10)
5088 {
5089 as_warn (_("expression out of range: defaulting to 1"));
5090 offs (exp) = 1;
5091 }
5092 }
5093 else if (exp->exp.X_op == O_constant)
5094 {
5095 switch (ok)
5096 {
5097 case 10:
5098 if ((valueT) TRUNC (offs (exp)) - 1 > 7)
5099 {
5100 as_warn (_("expression out of range: defaulting to 1"));
5101 offs (exp) = 1;
5102 }
5103 break;
5104 case 20:
5105 if ((valueT) TRUNC (offs (exp)) > 7)
5106 goto outrange;
5107 break;
5108 case 30:
5109 if ((valueT) TRUNC (offs (exp)) > 15)
5110 goto outrange;
5111 break;
5112 case 40:
5113 if ((valueT) TRUNC (offs (exp)) > 32)
5114 goto outrange;
5115 break;
5116 case 50:
5117 if ((valueT) TRUNC (offs (exp)) > 127)
5118 goto outrange;
5119 break;
5120 case 55:
5121 if ((valueT) SEXT (offs (exp)) + 64 > 127)
5122 goto outrange;
5123 break;
5124 case 60:
5125 if ((valueT) SEXT (offs (exp)) + 128 > 255)
5126 goto outrange;
5127 break;
5128 case 70:
5129 if ((valueT) TRUNC (offs (exp)) > 4095)
5130 {
5131 outrange:
5132 as_warn (_("expression out of range: defaulting to 0"));
5133 offs (exp) = 0;
5134 }
5135 break;
5136 case 80:
5137 if ((valueT) TRUNC (offs (exp)) != 0xffffffff
5138 && (valueT) TRUNC (offs (exp)) - 1 > 6)
5139 {
5140 as_warn (_("expression out of range: defaulting to 1"));
5141 offs (exp) = 1;
5142 }
5143 break;
5144 default:
5145 break;
5146 }
5147 }
5148 else if (exp->exp.X_op == O_big)
5149 {
5150 if (offs (exp) <= 0 /* flonum. */
5151 && (ok == 90 /* no bignums */
5152 || (ok > 10 /* Small-int ranges including 0 ok. */
5153 /* If we have a flonum zero, a zero integer should
5154 do as well (e.g., in moveq). */
5155 && generic_floating_point_number.exponent == 0
5156 && generic_floating_point_number.low[0] == 0)))
5157 {
5158 /* HACK! Turn it into a long. */
5159 LITTLENUM_TYPE words[6];
5160
5161 gen_to_words (words, 2, 8L); /* These numbers are magic! */
5162 op (exp) = O_constant;
5163 adds (exp) = 0;
5164 subs (exp) = 0;
5165 offs (exp) = words[1] | (words[0] << 16);
5166 }
5167 else if (ok != 0)
5168 {
5169 op (exp) = O_constant;
5170 adds (exp) = 0;
5171 subs (exp) = 0;
5172 offs (exp) = (ok == 10) ? 1 : 0;
5173 as_warn (_("Can't deal with expression; defaulting to %ld"),
5174 (long) offs (exp));
5175 }
5176 }
5177 else
5178 {
5179 if (ok >= 10 && ok <= 80)
5180 {
5181 op (exp) = O_constant;
5182 adds (exp) = 0;
5183 subs (exp) = 0;
5184 offs (exp) = (ok == 10) ? 1 : 0;
5185 as_warn (_("Can't deal with expression; defaulting to %ld"),
5186 (long) offs (exp));
5187 }
5188 }
5189
5190 if (exp->size != SIZE_UNSPEC)
5191 {
5192 switch (exp->size)
5193 {
5194 case SIZE_UNSPEC:
5195 case SIZE_LONG:
5196 break;
5197 case SIZE_BYTE:
5198 if (!isbyte (offs (exp)))
5199 as_warn (_("expression doesn't fit in BYTE"));
5200 break;
5201 case SIZE_WORD:
5202 if (!isword (offs (exp)))
5203 as_warn (_("expression doesn't fit in WORD"));
5204 break;
5205 }
5206 }
5207
5208 return offs (exp);
5209 }
5210
5211 /* These are the back-ends for the various machine dependent pseudo-ops. */
5212
5213 static void
5214 s_data1 (int ignore ATTRIBUTE_UNUSED)
5215 {
5216 subseg_set (data_section, 1);
5217 demand_empty_rest_of_line ();
5218 }
5219
5220 static void
5221 s_data2 (int ignore ATTRIBUTE_UNUSED)
5222 {
5223 subseg_set (data_section, 2);
5224 demand_empty_rest_of_line ();
5225 }
5226
5227 static void
5228 s_bss (int ignore ATTRIBUTE_UNUSED)
5229 {
5230 /* We don't support putting frags in the BSS segment, we fake it
5231 by marking in_bss, then looking at s_skip for clues. */
5232
5233 subseg_set (bss_section, 0);
5234 demand_empty_rest_of_line ();
5235 }
5236
5237 static void
5238 s_even (int ignore ATTRIBUTE_UNUSED)
5239 {
5240 register int temp;
5241 register long temp_fill;
5242
5243 temp = 1; /* JF should be 2? */
5244 temp_fill = get_absolute_expression ();
5245 if (!need_pass_2) /* Never make frag if expect extra pass. */
5246 frag_align (temp, (int) temp_fill, 0);
5247 demand_empty_rest_of_line ();
5248 record_alignment (now_seg, temp);
5249 }
5250
5251 static void
5252 s_proc (int ignore ATTRIBUTE_UNUSED)
5253 {
5254 demand_empty_rest_of_line ();
5255 }
5256 \f
5257 /* Pseudo-ops handled for MRI compatibility. */
5258
5259 /* This function returns non-zero if the argument is a conditional
5260 pseudo-op. This is called when checking whether a pending
5261 alignment is needed. */
5262
5263 int
5264 m68k_conditional_pseudoop (pseudo_typeS *pop)
5265 {
5266 return (pop->poc_handler == s_mri_if
5267 || pop->poc_handler == s_mri_else);
5268 }
5269
5270 /* Handle an MRI style chip specification. */
5271
5272 static void
5273 mri_chip (void)
5274 {
5275 char *s;
5276 char c;
5277 int i;
5278
5279 s = input_line_pointer;
5280 /* We can't use get_symbol_end since the processor names are not proper
5281 symbols. */
5282 while (is_part_of_name (c = *input_line_pointer++))
5283 ;
5284 *--input_line_pointer = 0;
5285 for (i = 0; m68k_cpus[i].name; i++)
5286 if (strcasecmp (s, m68k_cpus[i].name) == 0)
5287 break;
5288 if (!m68k_cpus[i].name)
5289 {
5290 as_bad (_("%s: unrecognized processor name"), s);
5291 *input_line_pointer = c;
5292 ignore_rest_of_line ();
5293 return;
5294 }
5295 *input_line_pointer = c;
5296
5297 if (*input_line_pointer == '/')
5298 current_architecture = 0;
5299 else
5300 current_architecture &= m68881 | m68851;
5301 current_architecture |= m68k_cpus[i].arch & ~(m68881 | m68851);
5302 control_regs = m68k_cpus[i].control_regs;
5303
5304 while (*input_line_pointer == '/')
5305 {
5306 ++input_line_pointer;
5307 s = input_line_pointer;
5308 /* We can't use get_symbol_end since the processor names are not
5309 proper symbols. */
5310 while (is_part_of_name (c = *input_line_pointer++))
5311 ;
5312 *--input_line_pointer = 0;
5313 if (strcmp (s, "68881") == 0)
5314 current_architecture |= m68881;
5315 else if (strcmp (s, "68851") == 0)
5316 current_architecture |= m68851;
5317 *input_line_pointer = c;
5318 }
5319 }
5320
5321 /* The MRI CHIP pseudo-op. */
5322
5323 static void
5324 s_chip (int ignore ATTRIBUTE_UNUSED)
5325 {
5326 char *stop = NULL;
5327 char stopc;
5328
5329 if (flag_mri)
5330 stop = mri_comment_field (&stopc);
5331 mri_chip ();
5332 if (flag_mri)
5333 mri_comment_end (stop, stopc);
5334 demand_empty_rest_of_line ();
5335 }
5336
5337 /* The MRI FOPT pseudo-op. */
5338
5339 static void
5340 s_fopt (int ignore ATTRIBUTE_UNUSED)
5341 {
5342 SKIP_WHITESPACE ();
5343
5344 if (strncasecmp (input_line_pointer, "ID=", 3) == 0)
5345 {
5346 int temp;
5347
5348 input_line_pointer += 3;
5349 temp = get_absolute_expression ();
5350 if (temp < 0 || temp > 7)
5351 as_bad (_("bad coprocessor id"));
5352 else
5353 m68k_float_copnum = COP0 + temp;
5354 }
5355 else
5356 {
5357 as_bad (_("unrecognized fopt option"));
5358 ignore_rest_of_line ();
5359 return;
5360 }
5361
5362 demand_empty_rest_of_line ();
5363 }
5364
5365 /* The structure used to handle the MRI OPT pseudo-op. */
5366
5367 struct opt_action
5368 {
5369 /* The name of the option. */
5370 const char *name;
5371
5372 /* If this is not NULL, just call this function. The first argument
5373 is the ARG field of this structure, the second argument is
5374 whether the option was negated. */
5375 void (*pfn) (int arg, int on);
5376
5377 /* If this is not NULL, and the PFN field is NULL, set the variable
5378 this points to. Set it to the ARG field if the option was not
5379 negated, and the NOTARG field otherwise. */
5380 int *pvar;
5381
5382 /* The value to pass to PFN or to assign to *PVAR. */
5383 int arg;
5384
5385 /* The value to assign to *PVAR if the option is negated. If PFN is
5386 NULL, and PVAR is not NULL, and ARG and NOTARG are the same, then
5387 the option may not be negated. */
5388 int notarg;
5389 };
5390
5391 /* The table used to handle the MRI OPT pseudo-op. */
5392
5393 static void skip_to_comma (int, int);
5394 static void opt_nest (int, int);
5395 static void opt_chip (int, int);
5396 static void opt_list (int, int);
5397 static void opt_list_symbols (int, int);
5398
5399 static const struct opt_action opt_table[] =
5400 {
5401 { "abspcadd", 0, &m68k_abspcadd, 1, 0 },
5402
5403 /* We do relaxing, so there is little use for these options. */
5404 { "b", 0, 0, 0, 0 },
5405 { "brs", 0, 0, 0, 0 },
5406 { "brb", 0, 0, 0, 0 },
5407 { "brl", 0, 0, 0, 0 },
5408 { "brw", 0, 0, 0, 0 },
5409
5410 { "c", 0, 0, 0, 0 },
5411 { "cex", 0, 0, 0, 0 },
5412 { "case", 0, &symbols_case_sensitive, 1, 0 },
5413 { "cl", 0, 0, 0, 0 },
5414 { "cre", 0, 0, 0, 0 },
5415 { "d", 0, &flag_keep_locals, 1, 0 },
5416 { "e", 0, 0, 0, 0 },
5417 { "f", 0, &flag_short_refs, 1, 0 },
5418 { "frs", 0, &flag_short_refs, 1, 0 },
5419 { "frl", 0, &flag_short_refs, 0, 1 },
5420 { "g", 0, 0, 0, 0 },
5421 { "i", 0, 0, 0, 0 },
5422 { "m", 0, 0, 0, 0 },
5423 { "mex", 0, 0, 0, 0 },
5424 { "mc", 0, 0, 0, 0 },
5425 { "md", 0, 0, 0, 0 },
5426 { "nest", opt_nest, 0, 0, 0 },
5427 { "next", skip_to_comma, 0, 0, 0 },
5428 { "o", 0, 0, 0, 0 },
5429 { "old", 0, 0, 0, 0 },
5430 { "op", skip_to_comma, 0, 0, 0 },
5431 { "pco", 0, 0, 0, 0 },
5432 { "p", opt_chip, 0, 0, 0 },
5433 { "pcr", 0, 0, 0, 0 },
5434 { "pcs", 0, 0, 0, 0 },
5435 { "r", 0, 0, 0, 0 },
5436 { "quick", 0, &m68k_quick, 1, 0 },
5437 { "rel32", 0, &m68k_rel32, 1, 0 },
5438 { "s", opt_list, 0, 0, 0 },
5439 { "t", opt_list_symbols, 0, 0, 0 },
5440 { "w", 0, &flag_no_warnings, 0, 1 },
5441 { "x", 0, 0, 0, 0 }
5442 };
5443
5444 #define OPTCOUNT ((int) (sizeof opt_table / sizeof opt_table[0]))
5445
5446 /* The MRI OPT pseudo-op. */
5447
5448 static void
5449 s_opt (int ignore ATTRIBUTE_UNUSED)
5450 {
5451 do
5452 {
5453 int t;
5454 char *s;
5455 char c;
5456 int i;
5457 const struct opt_action *o;
5458
5459 SKIP_WHITESPACE ();
5460
5461 t = 1;
5462 if (*input_line_pointer == '-')
5463 {
5464 ++input_line_pointer;
5465 t = 0;
5466 }
5467 else if (strncasecmp (input_line_pointer, "NO", 2) == 0)
5468 {
5469 input_line_pointer += 2;
5470 t = 0;
5471 }
5472
5473 s = input_line_pointer;
5474 c = get_symbol_end ();
5475
5476 for (i = 0, o = opt_table; i < OPTCOUNT; i++, o++)
5477 {
5478 if (strcasecmp (s, o->name) == 0)
5479 {
5480 if (o->pfn)
5481 {
5482 /* Restore input_line_pointer now in case the option
5483 takes arguments. */
5484 *input_line_pointer = c;
5485 (*o->pfn) (o->arg, t);
5486 }
5487 else if (o->pvar != NULL)
5488 {
5489 if (! t && o->arg == o->notarg)
5490 as_bad (_("option `%s' may not be negated"), s);
5491 *input_line_pointer = c;
5492 *o->pvar = t ? o->arg : o->notarg;
5493 }
5494 else
5495 *input_line_pointer = c;
5496 break;
5497 }
5498 }
5499 if (i >= OPTCOUNT)
5500 {
5501 as_bad (_("option `%s' not recognized"), s);
5502 *input_line_pointer = c;
5503 }
5504 }
5505 while (*input_line_pointer++ == ',');
5506
5507 /* Move back to terminating character. */
5508 --input_line_pointer;
5509 demand_empty_rest_of_line ();
5510 }
5511
5512 /* Skip ahead to a comma. This is used for OPT options which we do
5513 not support and which take arguments. */
5514
5515 static void
5516 skip_to_comma (int arg ATTRIBUTE_UNUSED, int on ATTRIBUTE_UNUSED)
5517 {
5518 while (*input_line_pointer != ','
5519 && ! is_end_of_line[(unsigned char) *input_line_pointer])
5520 ++input_line_pointer;
5521 }
5522
5523 /* Handle the OPT NEST=depth option. */
5524
5525 static void
5526 opt_nest (int arg ATTRIBUTE_UNUSED, int on ATTRIBUTE_UNUSED)
5527 {
5528 if (*input_line_pointer != '=')
5529 {
5530 as_bad (_("bad format of OPT NEST=depth"));
5531 return;
5532 }
5533
5534 ++input_line_pointer;
5535 max_macro_nest = get_absolute_expression ();
5536 }
5537
5538 /* Handle the OPT P=chip option. */
5539
5540 static void
5541 opt_chip (int arg ATTRIBUTE_UNUSED, int on ATTRIBUTE_UNUSED)
5542 {
5543 if (*input_line_pointer != '=')
5544 {
5545 /* This is just OPT P, which we do not support. */
5546 return;
5547 }
5548
5549 ++input_line_pointer;
5550 mri_chip ();
5551 }
5552
5553 /* Handle the OPT S option. */
5554
5555 static void
5556 opt_list (int arg ATTRIBUTE_UNUSED, int on)
5557 {
5558 listing_list (on);
5559 }
5560
5561 /* Handle the OPT T option. */
5562
5563 static void
5564 opt_list_symbols (int arg ATTRIBUTE_UNUSED, int on)
5565 {
5566 if (on)
5567 listing |= LISTING_SYMBOLS;
5568 else
5569 listing &= ~LISTING_SYMBOLS;
5570 }
5571
5572 /* Handle the MRI REG pseudo-op. */
5573
5574 static void
5575 s_reg (int ignore ATTRIBUTE_UNUSED)
5576 {
5577 char *s;
5578 int c;
5579 struct m68k_op rop;
5580 int mask;
5581 char *stop = NULL;
5582 char stopc;
5583
5584 if (line_label == NULL)
5585 {
5586 as_bad (_("missing label"));
5587 ignore_rest_of_line ();
5588 return;
5589 }
5590
5591 if (flag_mri)
5592 stop = mri_comment_field (&stopc);
5593
5594 SKIP_WHITESPACE ();
5595
5596 s = input_line_pointer;
5597 while (ISALNUM (*input_line_pointer)
5598 #ifdef REGISTER_PREFIX
5599 || *input_line_pointer == REGISTER_PREFIX
5600 #endif
5601 || *input_line_pointer == '/'
5602 || *input_line_pointer == '-')
5603 ++input_line_pointer;
5604 c = *input_line_pointer;
5605 *input_line_pointer = '\0';
5606
5607 if (m68k_ip_op (s, &rop) != 0)
5608 {
5609 if (rop.error == NULL)
5610 as_bad (_("bad register list"));
5611 else
5612 as_bad (_("bad register list: %s"), rop.error);
5613 *input_line_pointer = c;
5614 ignore_rest_of_line ();
5615 return;
5616 }
5617
5618 *input_line_pointer = c;
5619
5620 if (rop.mode == REGLST)
5621 mask = rop.mask;
5622 else if (rop.mode == DREG)
5623 mask = 1 << (rop.reg - DATA0);
5624 else if (rop.mode == AREG)
5625 mask = 1 << (rop.reg - ADDR0 + 8);
5626 else if (rop.mode == FPREG)
5627 mask = 1 << (rop.reg - FP0 + 16);
5628 else if (rop.mode == CONTROL
5629 && rop.reg == FPI)
5630 mask = 1 << 24;
5631 else if (rop.mode == CONTROL
5632 && rop.reg == FPS)
5633 mask = 1 << 25;
5634 else if (rop.mode == CONTROL
5635 && rop.reg == FPC)
5636 mask = 1 << 26;
5637 else
5638 {
5639 as_bad (_("bad register list"));
5640 ignore_rest_of_line ();
5641 return;
5642 }
5643
5644 S_SET_SEGMENT (line_label, reg_section);
5645 S_SET_VALUE (line_label, ~mask);
5646 symbol_set_frag (line_label, &zero_address_frag);
5647
5648 if (flag_mri)
5649 mri_comment_end (stop, stopc);
5650
5651 demand_empty_rest_of_line ();
5652 }
5653
5654 /* This structure is used for the MRI SAVE and RESTORE pseudo-ops. */
5655
5656 struct save_opts
5657 {
5658 struct save_opts *next;
5659 int abspcadd;
5660 int symbols_case_sensitive;
5661 int keep_locals;
5662 int short_refs;
5663 int architecture;
5664 const enum m68k_register *control_regs;
5665 int quick;
5666 int rel32;
5667 int listing;
5668 int no_warnings;
5669 /* FIXME: We don't save OPT S. */
5670 };
5671
5672 /* This variable holds the stack of saved options. */
5673
5674 static struct save_opts *save_stack;
5675
5676 /* The MRI SAVE pseudo-op. */
5677
5678 static void
5679 s_save (int ignore ATTRIBUTE_UNUSED)
5680 {
5681 struct save_opts *s;
5682
5683 s = (struct save_opts *) xmalloc (sizeof (struct save_opts));
5684 s->abspcadd = m68k_abspcadd;
5685 s->symbols_case_sensitive = symbols_case_sensitive;
5686 s->keep_locals = flag_keep_locals;
5687 s->short_refs = flag_short_refs;
5688 s->architecture = current_architecture;
5689 s->control_regs = control_regs;
5690 s->quick = m68k_quick;
5691 s->rel32 = m68k_rel32;
5692 s->listing = listing;
5693 s->no_warnings = flag_no_warnings;
5694
5695 s->next = save_stack;
5696 save_stack = s;
5697
5698 demand_empty_rest_of_line ();
5699 }
5700
5701 /* The MRI RESTORE pseudo-op. */
5702
5703 static void
5704 s_restore (int ignore ATTRIBUTE_UNUSED)
5705 {
5706 struct save_opts *s;
5707
5708 if (save_stack == NULL)
5709 {
5710 as_bad (_("restore without save"));
5711 ignore_rest_of_line ();
5712 return;
5713 }
5714
5715 s = save_stack;
5716 save_stack = s->next;
5717
5718 m68k_abspcadd = s->abspcadd;
5719 symbols_case_sensitive = s->symbols_case_sensitive;
5720 flag_keep_locals = s->keep_locals;
5721 flag_short_refs = s->short_refs;
5722 current_architecture = s->architecture;
5723 control_regs = s->control_regs;
5724 m68k_quick = s->quick;
5725 m68k_rel32 = s->rel32;
5726 listing = s->listing;
5727 flag_no_warnings = s->no_warnings;
5728
5729 free (s);
5730
5731 demand_empty_rest_of_line ();
5732 }
5733
5734 /* Types of MRI structured control directives. */
5735
5736 enum mri_control_type
5737 {
5738 mri_for,
5739 mri_if,
5740 mri_repeat,
5741 mri_while
5742 };
5743
5744 /* This structure is used to stack the MRI structured control
5745 directives. */
5746
5747 struct mri_control_info
5748 {
5749 /* The directive within which this one is enclosed. */
5750 struct mri_control_info *outer;
5751
5752 /* The type of directive. */
5753 enum mri_control_type type;
5754
5755 /* Whether an ELSE has been in an IF. */
5756 int else_seen;
5757
5758 /* The add or sub statement at the end of a FOR. */
5759 char *incr;
5760
5761 /* The label of the top of a FOR or REPEAT loop. */
5762 char *top;
5763
5764 /* The label to jump to for the next iteration, or the else
5765 expression of a conditional. */
5766 char *next;
5767
5768 /* The label to jump to to break out of the loop, or the label past
5769 the end of a conditional. */
5770 char *bottom;
5771 };
5772
5773 /* The stack of MRI structured control directives. */
5774
5775 static struct mri_control_info *mri_control_stack;
5776
5777 /* The current MRI structured control directive index number, used to
5778 generate label names. */
5779
5780 static int mri_control_index;
5781
5782 /* Assemble an instruction for an MRI structured control directive. */
5783
5784 static void
5785 mri_assemble (char *str)
5786 {
5787 char *s;
5788
5789 /* md_assemble expects the opcode to be in lower case. */
5790 for (s = str; *s != ' ' && *s != '\0'; s++)
5791 *s = TOLOWER (*s);
5792
5793 md_assemble (str);
5794 }
5795
5796 /* Generate a new MRI label structured control directive label name. */
5797
5798 static char *
5799 mri_control_label (void)
5800 {
5801 char *n;
5802
5803 n = (char *) xmalloc (20);
5804 sprintf (n, "%smc%d", FAKE_LABEL_NAME, mri_control_index);
5805 ++mri_control_index;
5806 return n;
5807 }
5808
5809 /* Create a new MRI structured control directive. */
5810
5811 static struct mri_control_info *
5812 push_mri_control (enum mri_control_type type)
5813 {
5814 struct mri_control_info *n;
5815
5816 n = (struct mri_control_info *) xmalloc (sizeof (struct mri_control_info));
5817
5818 n->type = type;
5819 n->else_seen = 0;
5820 if (type == mri_if || type == mri_while)
5821 n->top = NULL;
5822 else
5823 n->top = mri_control_label ();
5824 n->next = mri_control_label ();
5825 n->bottom = mri_control_label ();
5826
5827 n->outer = mri_control_stack;
5828 mri_control_stack = n;
5829
5830 return n;
5831 }
5832
5833 /* Pop off the stack of MRI structured control directives. */
5834
5835 static void
5836 pop_mri_control (void)
5837 {
5838 struct mri_control_info *n;
5839
5840 n = mri_control_stack;
5841 mri_control_stack = n->outer;
5842 if (n->top != NULL)
5843 free (n->top);
5844 free (n->next);
5845 free (n->bottom);
5846 free (n);
5847 }
5848
5849 /* Recognize a condition code in an MRI structured control expression. */
5850
5851 static int
5852 parse_mri_condition (int *pcc)
5853 {
5854 char c1, c2;
5855
5856 know (*input_line_pointer == '<');
5857
5858 ++input_line_pointer;
5859 c1 = *input_line_pointer++;
5860 c2 = *input_line_pointer++;
5861
5862 if (*input_line_pointer != '>')
5863 {
5864 as_bad (_("syntax error in structured control directive"));
5865 return 0;
5866 }
5867
5868 ++input_line_pointer;
5869 SKIP_WHITESPACE ();
5870
5871 c1 = TOLOWER (c1);
5872 c2 = TOLOWER (c2);
5873
5874 *pcc = (c1 << 8) | c2;
5875
5876 return 1;
5877 }
5878
5879 /* Parse a single operand in an MRI structured control expression. */
5880
5881 static int
5882 parse_mri_control_operand (int *pcc, char **leftstart, char **leftstop,
5883 char **rightstart, char **rightstop)
5884 {
5885 char *s;
5886
5887 SKIP_WHITESPACE ();
5888
5889 *pcc = -1;
5890 *leftstart = NULL;
5891 *leftstop = NULL;
5892 *rightstart = NULL;
5893 *rightstop = NULL;
5894
5895 if (*input_line_pointer == '<')
5896 {
5897 /* It's just a condition code. */
5898 return parse_mri_condition (pcc);
5899 }
5900
5901 /* Look ahead for the condition code. */
5902 for (s = input_line_pointer; *s != '\0'; ++s)
5903 {
5904 if (*s == '<' && s[1] != '\0' && s[2] != '\0' && s[3] == '>')
5905 break;
5906 }
5907 if (*s == '\0')
5908 {
5909 as_bad (_("missing condition code in structured control directive"));
5910 return 0;
5911 }
5912
5913 *leftstart = input_line_pointer;
5914 *leftstop = s;
5915 if (*leftstop > *leftstart
5916 && ((*leftstop)[-1] == ' ' || (*leftstop)[-1] == '\t'))
5917 --*leftstop;
5918
5919 input_line_pointer = s;
5920 if (! parse_mri_condition (pcc))
5921 return 0;
5922
5923 /* Look ahead for AND or OR or end of line. */
5924 for (s = input_line_pointer; *s != '\0'; ++s)
5925 {
5926 /* We must make sure we don't misinterpret AND/OR at the end of labels!
5927 if d0 <eq> #FOOAND and d1 <ne> #BAROR then
5928 ^^^ ^^ */
5929 if ((s == input_line_pointer
5930 || *(s-1) == ' '
5931 || *(s-1) == '\t')
5932 && ((strncasecmp (s, "AND", 3) == 0
5933 && (s[3] == '.' || ! is_part_of_name (s[3])))
5934 || (strncasecmp (s, "OR", 2) == 0
5935 && (s[2] == '.' || ! is_part_of_name (s[2])))))
5936 break;
5937 }
5938
5939 *rightstart = input_line_pointer;
5940 *rightstop = s;
5941 if (*rightstop > *rightstart
5942 && ((*rightstop)[-1] == ' ' || (*rightstop)[-1] == '\t'))
5943 --*rightstop;
5944
5945 input_line_pointer = s;
5946
5947 return 1;
5948 }
5949
5950 #define MCC(b1, b2) (((b1) << 8) | (b2))
5951
5952 /* Swap the sense of a condition. This changes the condition so that
5953 it generates the same result when the operands are swapped. */
5954
5955 static int
5956 swap_mri_condition (int cc)
5957 {
5958 switch (cc)
5959 {
5960 case MCC ('h', 'i'): return MCC ('c', 's');
5961 case MCC ('l', 's'): return MCC ('c', 'c');
5962 /* <HS> is an alias for <CC>. */
5963 case MCC ('h', 's'):
5964 case MCC ('c', 'c'): return MCC ('l', 's');
5965 /* <LO> is an alias for <CS>. */
5966 case MCC ('l', 'o'):
5967 case MCC ('c', 's'): return MCC ('h', 'i');
5968 case MCC ('p', 'l'): return MCC ('m', 'i');
5969 case MCC ('m', 'i'): return MCC ('p', 'l');
5970 case MCC ('g', 'e'): return MCC ('l', 'e');
5971 case MCC ('l', 't'): return MCC ('g', 't');
5972 case MCC ('g', 't'): return MCC ('l', 't');
5973 case MCC ('l', 'e'): return MCC ('g', 'e');
5974 /* Issue a warning for conditions we can not swap. */
5975 case MCC ('n', 'e'): return MCC ('n', 'e'); // no problem here
5976 case MCC ('e', 'q'): return MCC ('e', 'q'); // also no problem
5977 case MCC ('v', 'c'):
5978 case MCC ('v', 's'):
5979 default :
5980 as_warn (_("Condition <%c%c> in structured control directive can not be encoded correctly"),
5981 (char) (cc >> 8), (char) (cc));
5982 break;
5983 }
5984 return cc;
5985 }
5986
5987 /* Reverse the sense of a condition. */
5988
5989 static int
5990 reverse_mri_condition (int cc)
5991 {
5992 switch (cc)
5993 {
5994 case MCC ('h', 'i'): return MCC ('l', 's');
5995 case MCC ('l', 's'): return MCC ('h', 'i');
5996 /* <HS> is an alias for <CC> */
5997 case MCC ('h', 's'): return MCC ('l', 'o');
5998 case MCC ('c', 'c'): return MCC ('c', 's');
5999 /* <LO> is an alias for <CS> */
6000 case MCC ('l', 'o'): return MCC ('h', 's');
6001 case MCC ('c', 's'): return MCC ('c', 'c');
6002 case MCC ('n', 'e'): return MCC ('e', 'q');
6003 case MCC ('e', 'q'): return MCC ('n', 'e');
6004 case MCC ('v', 'c'): return MCC ('v', 's');
6005 case MCC ('v', 's'): return MCC ('v', 'c');
6006 case MCC ('p', 'l'): return MCC ('m', 'i');
6007 case MCC ('m', 'i'): return MCC ('p', 'l');
6008 case MCC ('g', 'e'): return MCC ('l', 't');
6009 case MCC ('l', 't'): return MCC ('g', 'e');
6010 case MCC ('g', 't'): return MCC ('l', 'e');
6011 case MCC ('l', 'e'): return MCC ('g', 't');
6012 }
6013 return cc;
6014 }
6015
6016 /* Build an MRI structured control expression. This generates test
6017 and branch instructions. It goes to TRUELAB if the condition is
6018 true, and to FALSELAB if the condition is false. Exactly one of
6019 TRUELAB and FALSELAB will be NULL, meaning to fall through. QUAL
6020 is the size qualifier for the expression. EXTENT is the size to
6021 use for the branch. */
6022
6023 static void
6024 build_mri_control_operand (int qual, int cc, char *leftstart, char *leftstop,
6025 char *rightstart, char *rightstop,
6026 const char *truelab, const char *falselab,
6027 int extent)
6028 {
6029 char *buf;
6030 char *s;
6031
6032 if (leftstart != NULL)
6033 {
6034 struct m68k_op leftop, rightop;
6035 char c;
6036
6037 /* Swap the compare operands, if necessary, to produce a legal
6038 m68k compare instruction. Comparing a register operand with
6039 a non-register operand requires the register to be on the
6040 right (cmp, cmpa). Comparing an immediate value with
6041 anything requires the immediate value to be on the left
6042 (cmpi). */
6043
6044 c = *leftstop;
6045 *leftstop = '\0';
6046 (void) m68k_ip_op (leftstart, &leftop);
6047 *leftstop = c;
6048
6049 c = *rightstop;
6050 *rightstop = '\0';
6051 (void) m68k_ip_op (rightstart, &rightop);
6052 *rightstop = c;
6053
6054 if (rightop.mode == IMMED
6055 || ((leftop.mode == DREG || leftop.mode == AREG)
6056 && (rightop.mode != DREG && rightop.mode != AREG)))
6057 {
6058 char *temp;
6059
6060 /* Correct conditional handling:
6061 if #1 <lt> d0 then ;means if (1 < d0)
6062 ...
6063 endi
6064
6065 should assemble to:
6066
6067 cmp #1,d0 if we do *not* swap the operands
6068 bgt true we need the swapped condition!
6069 ble false
6070 true:
6071 ...
6072 false:
6073 */
6074 temp = leftstart;
6075 leftstart = rightstart;
6076 rightstart = temp;
6077 temp = leftstop;
6078 leftstop = rightstop;
6079 rightstop = temp;
6080 }
6081 else
6082 {
6083 cc = swap_mri_condition (cc);
6084 }
6085 }
6086
6087 if (truelab == NULL)
6088 {
6089 cc = reverse_mri_condition (cc);
6090 truelab = falselab;
6091 }
6092
6093 if (leftstart != NULL)
6094 {
6095 buf = (char *) xmalloc (20
6096 + (leftstop - leftstart)
6097 + (rightstop - rightstart));
6098 s = buf;
6099 *s++ = 'c';
6100 *s++ = 'm';
6101 *s++ = 'p';
6102 if (qual != '\0')
6103 *s++ = TOLOWER (qual);
6104 *s++ = ' ';
6105 memcpy (s, leftstart, leftstop - leftstart);
6106 s += leftstop - leftstart;
6107 *s++ = ',';
6108 memcpy (s, rightstart, rightstop - rightstart);
6109 s += rightstop - rightstart;
6110 *s = '\0';
6111 mri_assemble (buf);
6112 free (buf);
6113 }
6114
6115 buf = (char *) xmalloc (20 + strlen (truelab));
6116 s = buf;
6117 *s++ = 'b';
6118 *s++ = cc >> 8;
6119 *s++ = cc & 0xff;
6120 if (extent != '\0')
6121 *s++ = TOLOWER (extent);
6122 *s++ = ' ';
6123 strcpy (s, truelab);
6124 mri_assemble (buf);
6125 free (buf);
6126 }
6127
6128 /* Parse an MRI structured control expression. This generates test
6129 and branch instructions. STOP is where the expression ends. It
6130 goes to TRUELAB if the condition is true, and to FALSELAB if the
6131 condition is false. Exactly one of TRUELAB and FALSELAB will be
6132 NULL, meaning to fall through. QUAL is the size qualifier for the
6133 expression. EXTENT is the size to use for the branch. */
6134
6135 static void
6136 parse_mri_control_expression (char *stop, int qual, const char *truelab,
6137 const char *falselab, int extent)
6138 {
6139 int c;
6140 int cc;
6141 char *leftstart;
6142 char *leftstop;
6143 char *rightstart;
6144 char *rightstop;
6145
6146 c = *stop;
6147 *stop = '\0';
6148
6149 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
6150 &rightstart, &rightstop))
6151 {
6152 *stop = c;
6153 return;
6154 }
6155
6156 if (strncasecmp (input_line_pointer, "AND", 3) == 0)
6157 {
6158 const char *flab;
6159
6160 if (falselab != NULL)
6161 flab = falselab;
6162 else
6163 flab = mri_control_label ();
6164
6165 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6166 rightstop, (const char *) NULL, flab, extent);
6167
6168 input_line_pointer += 3;
6169 if (*input_line_pointer != '.'
6170 || input_line_pointer[1] == '\0')
6171 qual = '\0';
6172 else
6173 {
6174 qual = input_line_pointer[1];
6175 input_line_pointer += 2;
6176 }
6177
6178 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
6179 &rightstart, &rightstop))
6180 {
6181 *stop = c;
6182 return;
6183 }
6184
6185 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6186 rightstop, truelab, falselab, extent);
6187
6188 if (falselab == NULL)
6189 colon (flab);
6190 }
6191 else if (strncasecmp (input_line_pointer, "OR", 2) == 0)
6192 {
6193 const char *tlab;
6194
6195 if (truelab != NULL)
6196 tlab = truelab;
6197 else
6198 tlab = mri_control_label ();
6199
6200 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6201 rightstop, tlab, (const char *) NULL, extent);
6202
6203 input_line_pointer += 2;
6204 if (*input_line_pointer != '.'
6205 || input_line_pointer[1] == '\0')
6206 qual = '\0';
6207 else
6208 {
6209 qual = input_line_pointer[1];
6210 input_line_pointer += 2;
6211 }
6212
6213 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
6214 &rightstart, &rightstop))
6215 {
6216 *stop = c;
6217 return;
6218 }
6219
6220 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6221 rightstop, truelab, falselab, extent);
6222
6223 if (truelab == NULL)
6224 colon (tlab);
6225 }
6226 else
6227 {
6228 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6229 rightstop, truelab, falselab, extent);
6230 }
6231
6232 *stop = c;
6233 if (input_line_pointer != stop)
6234 as_bad (_("syntax error in structured control directive"));
6235 }
6236
6237 /* Handle the MRI IF pseudo-op. This may be a structured control
6238 directive, or it may be a regular assembler conditional, depending
6239 on its operands. */
6240
6241 static void
6242 s_mri_if (int qual)
6243 {
6244 char *s;
6245 int c;
6246 struct mri_control_info *n;
6247
6248 /* A structured control directive must end with THEN with an
6249 optional qualifier. */
6250 s = input_line_pointer;
6251 /* We only accept '*' as introduction of comments if preceded by white space
6252 or at first column of a line (I think this can't actually happen here?)
6253 This is important when assembling:
6254 if d0 <ne> 12(a0,d0*2) then
6255 if d0 <ne> #CONST*20 then. */
6256 while (! (is_end_of_line[(unsigned char) *s]
6257 || (flag_mri
6258 && *s == '*'
6259 && (s == input_line_pointer
6260 || *(s-1) == ' '
6261 || *(s-1) == '\t'))))
6262 ++s;
6263 --s;
6264 while (s > input_line_pointer && (*s == ' ' || *s == '\t'))
6265 --s;
6266
6267 if (s - input_line_pointer > 1
6268 && s[-1] == '.')
6269 s -= 2;
6270
6271 if (s - input_line_pointer < 3
6272 || strncasecmp (s - 3, "THEN", 4) != 0)
6273 {
6274 if (qual != '\0')
6275 {
6276 as_bad (_("missing then"));
6277 ignore_rest_of_line ();
6278 return;
6279 }
6280
6281 /* It's a conditional. */
6282 s_if (O_ne);
6283 return;
6284 }
6285
6286 /* Since this might be a conditional if, this pseudo-op will be
6287 called even if we are supported to be ignoring input. Double
6288 check now. Clobber *input_line_pointer so that ignore_input
6289 thinks that this is not a special pseudo-op. */
6290 c = *input_line_pointer;
6291 *input_line_pointer = 0;
6292 if (ignore_input ())
6293 {
6294 *input_line_pointer = c;
6295 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6296 ++input_line_pointer;
6297 demand_empty_rest_of_line ();
6298 return;
6299 }
6300 *input_line_pointer = c;
6301
6302 n = push_mri_control (mri_if);
6303
6304 parse_mri_control_expression (s - 3, qual, (const char *) NULL,
6305 n->next, s[1] == '.' ? s[2] : '\0');
6306
6307 if (s[1] == '.')
6308 input_line_pointer = s + 3;
6309 else
6310 input_line_pointer = s + 1;
6311
6312 if (flag_mri)
6313 {
6314 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6315 ++input_line_pointer;
6316 }
6317
6318 demand_empty_rest_of_line ();
6319 }
6320
6321 /* Handle the MRI else pseudo-op. If we are currently doing an MRI
6322 structured IF, associate the ELSE with the IF. Otherwise, assume
6323 it is a conditional else. */
6324
6325 static void
6326 s_mri_else (int qual)
6327 {
6328 int c;
6329 char *buf;
6330 char q[2];
6331
6332 if (qual == '\0'
6333 && (mri_control_stack == NULL
6334 || mri_control_stack->type != mri_if
6335 || mri_control_stack->else_seen))
6336 {
6337 s_else (0);
6338 return;
6339 }
6340
6341 c = *input_line_pointer;
6342 *input_line_pointer = 0;
6343 if (ignore_input ())
6344 {
6345 *input_line_pointer = c;
6346 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6347 ++input_line_pointer;
6348 demand_empty_rest_of_line ();
6349 return;
6350 }
6351 *input_line_pointer = c;
6352
6353 if (mri_control_stack == NULL
6354 || mri_control_stack->type != mri_if
6355 || mri_control_stack->else_seen)
6356 {
6357 as_bad (_("else without matching if"));
6358 ignore_rest_of_line ();
6359 return;
6360 }
6361
6362 mri_control_stack->else_seen = 1;
6363
6364 buf = (char *) xmalloc (20 + strlen (mri_control_stack->bottom));
6365 q[0] = TOLOWER (qual);
6366 q[1] = '\0';
6367 sprintf (buf, "bra%s %s", q, mri_control_stack->bottom);
6368 mri_assemble (buf);
6369 free (buf);
6370
6371 colon (mri_control_stack->next);
6372
6373 if (flag_mri)
6374 {
6375 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6376 ++input_line_pointer;
6377 }
6378
6379 demand_empty_rest_of_line ();
6380 }
6381
6382 /* Handle the MRI ENDI pseudo-op. */
6383
6384 static void
6385 s_mri_endi (int ignore ATTRIBUTE_UNUSED)
6386 {
6387 if (mri_control_stack == NULL
6388 || mri_control_stack->type != mri_if)
6389 {
6390 as_bad (_("endi without matching if"));
6391 ignore_rest_of_line ();
6392 return;
6393 }
6394
6395 /* ignore_input will not return true for ENDI, so we don't need to
6396 worry about checking it again here. */
6397
6398 if (! mri_control_stack->else_seen)
6399 colon (mri_control_stack->next);
6400 colon (mri_control_stack->bottom);
6401
6402 pop_mri_control ();
6403
6404 if (flag_mri)
6405 {
6406 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6407 ++input_line_pointer;
6408 }
6409
6410 demand_empty_rest_of_line ();
6411 }
6412
6413 /* Handle the MRI BREAK pseudo-op. */
6414
6415 static void
6416 s_mri_break (int extent)
6417 {
6418 struct mri_control_info *n;
6419 char *buf;
6420 char ex[2];
6421
6422 n = mri_control_stack;
6423 while (n != NULL
6424 && n->type != mri_for
6425 && n->type != mri_repeat
6426 && n->type != mri_while)
6427 n = n->outer;
6428 if (n == NULL)
6429 {
6430 as_bad (_("break outside of structured loop"));
6431 ignore_rest_of_line ();
6432 return;
6433 }
6434
6435 buf = (char *) xmalloc (20 + strlen (n->bottom));
6436 ex[0] = TOLOWER (extent);
6437 ex[1] = '\0';
6438 sprintf (buf, "bra%s %s", ex, n->bottom);
6439 mri_assemble (buf);
6440 free (buf);
6441
6442 if (flag_mri)
6443 {
6444 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6445 ++input_line_pointer;
6446 }
6447
6448 demand_empty_rest_of_line ();
6449 }
6450
6451 /* Handle the MRI NEXT pseudo-op. */
6452
6453 static void
6454 s_mri_next (int extent)
6455 {
6456 struct mri_control_info *n;
6457 char *buf;
6458 char ex[2];
6459
6460 n = mri_control_stack;
6461 while (n != NULL
6462 && n->type != mri_for
6463 && n->type != mri_repeat
6464 && n->type != mri_while)
6465 n = n->outer;
6466 if (n == NULL)
6467 {
6468 as_bad (_("next outside of structured loop"));
6469 ignore_rest_of_line ();
6470 return;
6471 }
6472
6473 buf = (char *) xmalloc (20 + strlen (n->next));
6474 ex[0] = TOLOWER (extent);
6475 ex[1] = '\0';
6476 sprintf (buf, "bra%s %s", ex, n->next);
6477 mri_assemble (buf);
6478 free (buf);
6479
6480 if (flag_mri)
6481 {
6482 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6483 ++input_line_pointer;
6484 }
6485
6486 demand_empty_rest_of_line ();
6487 }
6488
6489 /* Handle the MRI FOR pseudo-op. */
6490
6491 static void
6492 s_mri_for (int qual)
6493 {
6494 const char *varstart, *varstop;
6495 const char *initstart, *initstop;
6496 const char *endstart, *endstop;
6497 const char *bystart, *bystop;
6498 int up;
6499 int by;
6500 int extent;
6501 struct mri_control_info *n;
6502 char *buf;
6503 char *s;
6504 char ex[2];
6505
6506 /* The syntax is
6507 FOR.q var = init { TO | DOWNTO } end [ BY by ] DO.e
6508 */
6509
6510 SKIP_WHITESPACE ();
6511 varstart = input_line_pointer;
6512
6513 /* Look for the '='. */
6514 while (! is_end_of_line[(unsigned char) *input_line_pointer]
6515 && *input_line_pointer != '=')
6516 ++input_line_pointer;
6517 if (*input_line_pointer != '=')
6518 {
6519 as_bad (_("missing ="));
6520 ignore_rest_of_line ();
6521 return;
6522 }
6523
6524 varstop = input_line_pointer;
6525 if (varstop > varstart
6526 && (varstop[-1] == ' ' || varstop[-1] == '\t'))
6527 --varstop;
6528
6529 ++input_line_pointer;
6530
6531 initstart = input_line_pointer;
6532
6533 /* Look for TO or DOWNTO. */
6534 up = 1;
6535 initstop = NULL;
6536 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6537 {
6538 if (strncasecmp (input_line_pointer, "TO", 2) == 0
6539 && ! is_part_of_name (input_line_pointer[2]))
6540 {
6541 initstop = input_line_pointer;
6542 input_line_pointer += 2;
6543 break;
6544 }
6545 if (strncasecmp (input_line_pointer, "DOWNTO", 6) == 0
6546 && ! is_part_of_name (input_line_pointer[6]))
6547 {
6548 initstop = input_line_pointer;
6549 up = 0;
6550 input_line_pointer += 6;
6551 break;
6552 }
6553 ++input_line_pointer;
6554 }
6555 if (initstop == NULL)
6556 {
6557 as_bad (_("missing to or downto"));
6558 ignore_rest_of_line ();
6559 return;
6560 }
6561 if (initstop > initstart
6562 && (initstop[-1] == ' ' || initstop[-1] == '\t'))
6563 --initstop;
6564
6565 SKIP_WHITESPACE ();
6566 endstart = input_line_pointer;
6567
6568 /* Look for BY or DO. */
6569 by = 0;
6570 endstop = NULL;
6571 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6572 {
6573 if (strncasecmp (input_line_pointer, "BY", 2) == 0
6574 && ! is_part_of_name (input_line_pointer[2]))
6575 {
6576 endstop = input_line_pointer;
6577 by = 1;
6578 input_line_pointer += 2;
6579 break;
6580 }
6581 if (strncasecmp (input_line_pointer, "DO", 2) == 0
6582 && (input_line_pointer[2] == '.'
6583 || ! is_part_of_name (input_line_pointer[2])))
6584 {
6585 endstop = input_line_pointer;
6586 input_line_pointer += 2;
6587 break;
6588 }
6589 ++input_line_pointer;
6590 }
6591 if (endstop == NULL)
6592 {
6593 as_bad (_("missing do"));
6594 ignore_rest_of_line ();
6595 return;
6596 }
6597 if (endstop > endstart
6598 && (endstop[-1] == ' ' || endstop[-1] == '\t'))
6599 --endstop;
6600
6601 if (! by)
6602 {
6603 bystart = "#1";
6604 bystop = bystart + 2;
6605 }
6606 else
6607 {
6608 SKIP_WHITESPACE ();
6609 bystart = input_line_pointer;
6610
6611 /* Look for DO. */
6612 bystop = NULL;
6613 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6614 {
6615 if (strncasecmp (input_line_pointer, "DO", 2) == 0
6616 && (input_line_pointer[2] == '.'
6617 || ! is_part_of_name (input_line_pointer[2])))
6618 {
6619 bystop = input_line_pointer;
6620 input_line_pointer += 2;
6621 break;
6622 }
6623 ++input_line_pointer;
6624 }
6625 if (bystop == NULL)
6626 {
6627 as_bad (_("missing do"));
6628 ignore_rest_of_line ();
6629 return;
6630 }
6631 if (bystop > bystart
6632 && (bystop[-1] == ' ' || bystop[-1] == '\t'))
6633 --bystop;
6634 }
6635
6636 if (*input_line_pointer != '.')
6637 extent = '\0';
6638 else
6639 {
6640 extent = input_line_pointer[1];
6641 input_line_pointer += 2;
6642 }
6643
6644 /* We have fully parsed the FOR operands. Now build the loop. */
6645 n = push_mri_control (mri_for);
6646
6647 buf = (char *) xmalloc (50 + (input_line_pointer - varstart));
6648
6649 /* Move init,var. */
6650 s = buf;
6651 *s++ = 'm';
6652 *s++ = 'o';
6653 *s++ = 'v';
6654 *s++ = 'e';
6655 if (qual != '\0')
6656 *s++ = TOLOWER (qual);
6657 *s++ = ' ';
6658 memcpy (s, initstart, initstop - initstart);
6659 s += initstop - initstart;
6660 *s++ = ',';
6661 memcpy (s, varstart, varstop - varstart);
6662 s += varstop - varstart;
6663 *s = '\0';
6664 mri_assemble (buf);
6665
6666 colon (n->top);
6667
6668 /* cmp end,var. */
6669 s = buf;
6670 *s++ = 'c';
6671 *s++ = 'm';
6672 *s++ = 'p';
6673 if (qual != '\0')
6674 *s++ = TOLOWER (qual);
6675 *s++ = ' ';
6676 memcpy (s, endstart, endstop - endstart);
6677 s += endstop - endstart;
6678 *s++ = ',';
6679 memcpy (s, varstart, varstop - varstart);
6680 s += varstop - varstart;
6681 *s = '\0';
6682 mri_assemble (buf);
6683
6684 /* bcc bottom. */
6685 ex[0] = TOLOWER (extent);
6686 ex[1] = '\0';
6687 if (up)
6688 sprintf (buf, "blt%s %s", ex, n->bottom);
6689 else
6690 sprintf (buf, "bgt%s %s", ex, n->bottom);
6691 mri_assemble (buf);
6692
6693 /* Put together the add or sub instruction used by ENDF. */
6694 s = buf;
6695 if (up)
6696 strcpy (s, "add");
6697 else
6698 strcpy (s, "sub");
6699 s += 3;
6700 if (qual != '\0')
6701 *s++ = TOLOWER (qual);
6702 *s++ = ' ';
6703 memcpy (s, bystart, bystop - bystart);
6704 s += bystop - bystart;
6705 *s++ = ',';
6706 memcpy (s, varstart, varstop - varstart);
6707 s += varstop - varstart;
6708 *s = '\0';
6709 n->incr = buf;
6710
6711 if (flag_mri)
6712 {
6713 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6714 ++input_line_pointer;
6715 }
6716
6717 demand_empty_rest_of_line ();
6718 }
6719
6720 /* Handle the MRI ENDF pseudo-op. */
6721
6722 static void
6723 s_mri_endf (int ignore ATTRIBUTE_UNUSED)
6724 {
6725 if (mri_control_stack == NULL
6726 || mri_control_stack->type != mri_for)
6727 {
6728 as_bad (_("endf without for"));
6729 ignore_rest_of_line ();
6730 return;
6731 }
6732
6733 colon (mri_control_stack->next);
6734
6735 mri_assemble (mri_control_stack->incr);
6736
6737 sprintf (mri_control_stack->incr, "bra %s", mri_control_stack->top);
6738 mri_assemble (mri_control_stack->incr);
6739
6740 free (mri_control_stack->incr);
6741
6742 colon (mri_control_stack->bottom);
6743
6744 pop_mri_control ();
6745
6746 if (flag_mri)
6747 {
6748 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6749 ++input_line_pointer;
6750 }
6751
6752 demand_empty_rest_of_line ();
6753 }
6754
6755 /* Handle the MRI REPEAT pseudo-op. */
6756
6757 static void
6758 s_mri_repeat (int ignore ATTRIBUTE_UNUSED)
6759 {
6760 struct mri_control_info *n;
6761
6762 n = push_mri_control (mri_repeat);
6763 colon (n->top);
6764 if (flag_mri)
6765 {
6766 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6767 ++input_line_pointer;
6768 }
6769 demand_empty_rest_of_line ();
6770 }
6771
6772 /* Handle the MRI UNTIL pseudo-op. */
6773
6774 static void
6775 s_mri_until (int qual)
6776 {
6777 char *s;
6778
6779 if (mri_control_stack == NULL
6780 || mri_control_stack->type != mri_repeat)
6781 {
6782 as_bad (_("until without repeat"));
6783 ignore_rest_of_line ();
6784 return;
6785 }
6786
6787 colon (mri_control_stack->next);
6788
6789 for (s = input_line_pointer; ! is_end_of_line[(unsigned char) *s]; s++)
6790 ;
6791
6792 parse_mri_control_expression (s, qual, (const char *) NULL,
6793 mri_control_stack->top, '\0');
6794
6795 colon (mri_control_stack->bottom);
6796
6797 input_line_pointer = s;
6798
6799 pop_mri_control ();
6800
6801 if (flag_mri)
6802 {
6803 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6804 ++input_line_pointer;
6805 }
6806
6807 demand_empty_rest_of_line ();
6808 }
6809
6810 /* Handle the MRI WHILE pseudo-op. */
6811
6812 static void
6813 s_mri_while (int qual)
6814 {
6815 char *s;
6816
6817 struct mri_control_info *n;
6818
6819 s = input_line_pointer;
6820 /* We only accept '*' as introduction of comments if preceded by white space
6821 or at first column of a line (I think this can't actually happen here?)
6822 This is important when assembling:
6823 while d0 <ne> 12(a0,d0*2) do
6824 while d0 <ne> #CONST*20 do. */
6825 while (! (is_end_of_line[(unsigned char) *s]
6826 || (flag_mri
6827 && *s == '*'
6828 && (s == input_line_pointer
6829 || *(s-1) == ' '
6830 || *(s-1) == '\t'))))
6831 s++;
6832 --s;
6833 while (*s == ' ' || *s == '\t')
6834 --s;
6835 if (s - input_line_pointer > 1
6836 && s[-1] == '.')
6837 s -= 2;
6838 if (s - input_line_pointer < 2
6839 || strncasecmp (s - 1, "DO", 2) != 0)
6840 {
6841 as_bad (_("missing do"));
6842 ignore_rest_of_line ();
6843 return;
6844 }
6845
6846 n = push_mri_control (mri_while);
6847
6848 colon (n->next);
6849
6850 parse_mri_control_expression (s - 1, qual, (const char *) NULL, n->bottom,
6851 s[1] == '.' ? s[2] : '\0');
6852
6853 input_line_pointer = s + 1;
6854 if (*input_line_pointer == '.')
6855 input_line_pointer += 2;
6856
6857 if (flag_mri)
6858 {
6859 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6860 ++input_line_pointer;
6861 }
6862
6863 demand_empty_rest_of_line ();
6864 }
6865
6866 /* Handle the MRI ENDW pseudo-op. */
6867
6868 static void
6869 s_mri_endw (int ignore ATTRIBUTE_UNUSED)
6870 {
6871 char *buf;
6872
6873 if (mri_control_stack == NULL
6874 || mri_control_stack->type != mri_while)
6875 {
6876 as_bad (_("endw without while"));
6877 ignore_rest_of_line ();
6878 return;
6879 }
6880
6881 buf = (char *) xmalloc (20 + strlen (mri_control_stack->next));
6882 sprintf (buf, "bra %s", mri_control_stack->next);
6883 mri_assemble (buf);
6884 free (buf);
6885
6886 colon (mri_control_stack->bottom);
6887
6888 pop_mri_control ();
6889
6890 if (flag_mri)
6891 {
6892 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6893 ++input_line_pointer;
6894 }
6895
6896 demand_empty_rest_of_line ();
6897 }
6898 \f
6899 /* Parse a .cpu directive. */
6900
6901 static void
6902 s_m68k_cpu (int ignored ATTRIBUTE_UNUSED)
6903 {
6904 char saved_char;
6905 char *name;
6906
6907 if (initialized)
6908 {
6909 as_bad (_("already assembled instructions"));
6910 ignore_rest_of_line ();
6911 return;
6912 }
6913
6914 name = input_line_pointer;
6915 while (*input_line_pointer && !ISSPACE(*input_line_pointer))
6916 input_line_pointer++;
6917 saved_char = *input_line_pointer;
6918 *input_line_pointer = 0;
6919
6920 m68k_set_cpu (name, 1, 0);
6921
6922 *input_line_pointer = saved_char;
6923 demand_empty_rest_of_line ();
6924 return;
6925 }
6926
6927 /* Parse a .arch directive. */
6928
6929 static void
6930 s_m68k_arch (int ignored ATTRIBUTE_UNUSED)
6931 {
6932 char saved_char;
6933 char *name;
6934
6935 if (initialized)
6936 {
6937 as_bad (_("already assembled instructions"));
6938 ignore_rest_of_line ();
6939 return;
6940 }
6941
6942 name = input_line_pointer;
6943 while (*input_line_pointer && *input_line_pointer != ','
6944 && !ISSPACE (*input_line_pointer))
6945 input_line_pointer++;
6946 saved_char = *input_line_pointer;
6947 *input_line_pointer = 0;
6948
6949 if (m68k_set_arch (name, 1, 0))
6950 {
6951 /* Scan extensions. */
6952 do
6953 {
6954 *input_line_pointer++ = saved_char;
6955 if (!*input_line_pointer || ISSPACE (*input_line_pointer))
6956 break;
6957 name = input_line_pointer;
6958 while (*input_line_pointer && *input_line_pointer != ','
6959 && !ISSPACE (*input_line_pointer))
6960 input_line_pointer++;
6961 saved_char = *input_line_pointer;
6962 *input_line_pointer = 0;
6963 }
6964 while (m68k_set_extension (name, 1, 0));
6965 }
6966
6967 *input_line_pointer = saved_char;
6968 demand_empty_rest_of_line ();
6969 return;
6970 }
6971 \f
6972 /* Lookup a cpu name in TABLE and return the slot found. Return NULL
6973 if none is found, the caller is responsible for emitting an error
6974 message. If ALLOW_M is non-zero, we allow an initial 'm' on the
6975 cpu name, if it begins with a '6' (possibly skipping an intervening
6976 'c'. We also allow a 'c' in the same place. if NEGATED is
6977 non-zero, we accept a leading 'no-' and *NEGATED is set to true, if
6978 the option is indeed negated. */
6979
6980 static const struct m68k_cpu *
6981 m68k_lookup_cpu (const char *arg, const struct m68k_cpu *table,
6982 int allow_m, int *negated)
6983 {
6984 /* allow negated value? */
6985 if (negated)
6986 {
6987 *negated = 0;
6988
6989 if (arg[0] == 'n' && arg[1] == 'o' && arg[2] == '-')
6990 {
6991 arg += 3;
6992 *negated = 1;
6993 }
6994 }
6995
6996 /* Remove 'm' or 'mc' prefix from 68k variants. */
6997 if (allow_m)
6998 {
6999 if (arg[0] == 'm')
7000 {
7001 if (arg[1] == '6')
7002 arg += 1;
7003 else if (arg[1] == 'c' && arg[2] == '6')
7004 arg += 2;
7005 }
7006 }
7007 else if (arg[0] == 'c' && arg[1] == '6')
7008 arg += 1;
7009
7010 for (; table->name; table++)
7011 if (!strcmp (arg, table->name))
7012 {
7013 if (table->alias < -1 || table->alias > 1)
7014 as_bad (_("`%s' is deprecated, use `%s'"),
7015 table->name, table[table->alias < 0 ? 1 : -1].name);
7016 return table;
7017 }
7018 return 0;
7019 }
7020
7021 /* Set the cpu, issuing errors if it is unrecognized, or invalid */
7022
7023 static int
7024 m68k_set_cpu (char const *name, int allow_m, int silent)
7025 {
7026 const struct m68k_cpu *cpu;
7027
7028 cpu = m68k_lookup_cpu (name, m68k_cpus, allow_m, NULL);
7029
7030 if (!cpu)
7031 {
7032 if (!silent)
7033 as_bad (_("cpu `%s' unrecognized"), name);
7034 return 0;
7035 }
7036
7037 if (selected_cpu && selected_cpu != cpu)
7038 {
7039 as_bad (_("already selected `%s' processor"),
7040 selected_cpu->name);
7041 return 0;
7042 }
7043 selected_cpu = cpu;
7044 return 1;
7045 }
7046
7047 /* Set the architecture, issuing errors if it is unrecognized, or invalid */
7048
7049 static int
7050 m68k_set_arch (char const *name, int allow_m, int silent)
7051 {
7052 const struct m68k_cpu *arch;
7053
7054 arch = m68k_lookup_cpu (name, m68k_archs, allow_m, NULL);
7055
7056 if (!arch)
7057 {
7058 if (!silent)
7059 as_bad (_("architecture `%s' unrecognized"), name);
7060 return 0;
7061 }
7062
7063 if (selected_arch && selected_arch != arch)
7064 {
7065 as_bad (_("already selected `%s' architecture"),
7066 selected_arch->name);
7067 return 0;
7068 }
7069
7070 selected_arch = arch;
7071 return 1;
7072 }
7073
7074 /* Set the architecture extension, issuing errors if it is
7075 unrecognized, or invalid */
7076
7077 static int
7078 m68k_set_extension (char const *name, int allow_m, int silent)
7079 {
7080 int negated;
7081 const struct m68k_cpu *ext;
7082
7083 ext = m68k_lookup_cpu (name, m68k_extensions, allow_m, &negated);
7084
7085 if (!ext)
7086 {
7087 if (!silent)
7088 as_bad (_("extension `%s' unrecognized"), name);
7089 return 0;
7090 }
7091
7092 if (negated)
7093 not_current_architecture |= ext->arch;
7094 else
7095 current_architecture |= ext->arch;
7096 return 1;
7097 }
7098
7099 /* md_parse_option
7100 Invocation line includes a switch not recognized by the base assembler.
7101 */
7102
7103 #ifdef OBJ_ELF
7104 const char *md_shortopts = "lSA:m:kQ:V";
7105 #else
7106 const char *md_shortopts = "lSA:m:k";
7107 #endif
7108
7109 struct option md_longopts[] = {
7110 #define OPTION_PIC (OPTION_MD_BASE)
7111 {"pic", no_argument, NULL, OPTION_PIC},
7112 #define OPTION_REGISTER_PREFIX_OPTIONAL (OPTION_MD_BASE + 1)
7113 {"register-prefix-optional", no_argument, NULL,
7114 OPTION_REGISTER_PREFIX_OPTIONAL},
7115 #define OPTION_BITWISE_OR (OPTION_MD_BASE + 2)
7116 {"bitwise-or", no_argument, NULL, OPTION_BITWISE_OR},
7117 #define OPTION_BASE_SIZE_DEFAULT_16 (OPTION_MD_BASE + 3)
7118 {"base-size-default-16", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_16},
7119 #define OPTION_BASE_SIZE_DEFAULT_32 (OPTION_MD_BASE + 4)
7120 {"base-size-default-32", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_32},
7121 #define OPTION_DISP_SIZE_DEFAULT_16 (OPTION_MD_BASE + 5)
7122 {"disp-size-default-16", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_16},
7123 #define OPTION_DISP_SIZE_DEFAULT_32 (OPTION_MD_BASE + 6)
7124 {"disp-size-default-32", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_32},
7125 #define OPTION_PCREL (OPTION_MD_BASE + 7)
7126 {"pcrel", no_argument, NULL, OPTION_PCREL},
7127 {NULL, no_argument, NULL, 0}
7128 };
7129 size_t md_longopts_size = sizeof (md_longopts);
7130
7131 int
7132 md_parse_option (int c, char *arg)
7133 {
7134 switch (c)
7135 {
7136 case 'l': /* -l means keep external to 2 bit offset
7137 rather than 16 bit one. */
7138 flag_short_refs = 1;
7139 break;
7140
7141 case 'S': /* -S means that jbsr's always turn into
7142 jsr's. */
7143 flag_long_jumps = 1;
7144 break;
7145
7146 case OPTION_PCREL: /* --pcrel means never turn PC-relative
7147 branches into absolute jumps. */
7148 flag_keep_pcrel = 1;
7149 break;
7150
7151 case OPTION_PIC:
7152 case 'k':
7153 flag_want_pic = 1;
7154 break; /* -pic, Position Independent Code. */
7155
7156 case OPTION_REGISTER_PREFIX_OPTIONAL:
7157 flag_reg_prefix_optional = 1;
7158 reg_prefix_optional_seen = 1;
7159 break;
7160
7161 /* -V: SVR4 argument to print version ID. */
7162 case 'V':
7163 print_version_id ();
7164 break;
7165
7166 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
7167 should be emitted or not. FIXME: Not implemented. */
7168 case 'Q':
7169 break;
7170
7171 case OPTION_BITWISE_OR:
7172 {
7173 char *n, *t;
7174 const char *s;
7175
7176 n = (char *) xmalloc (strlen (m68k_comment_chars) + 1);
7177 t = n;
7178 for (s = m68k_comment_chars; *s != '\0'; s++)
7179 if (*s != '|')
7180 *t++ = *s;
7181 *t = '\0';
7182 m68k_comment_chars = n;
7183 }
7184 break;
7185
7186 case OPTION_BASE_SIZE_DEFAULT_16:
7187 m68k_index_width_default = SIZE_WORD;
7188 break;
7189
7190 case OPTION_BASE_SIZE_DEFAULT_32:
7191 m68k_index_width_default = SIZE_LONG;
7192 break;
7193
7194 case OPTION_DISP_SIZE_DEFAULT_16:
7195 m68k_rel32 = 0;
7196 m68k_rel32_from_cmdline = 1;
7197 break;
7198
7199 case OPTION_DISP_SIZE_DEFAULT_32:
7200 m68k_rel32 = 1;
7201 m68k_rel32_from_cmdline = 1;
7202 break;
7203
7204 case 'A':
7205 #if WARN_DEPRECATED
7206 as_tsktsk (_ ("option `-A%s' is deprecated: use `-%s'",
7207 arg, arg));
7208 #endif
7209 /* Intentional fall-through. */
7210 case 'm':
7211 if (!strncmp (arg, "arch=", 5))
7212 m68k_set_arch (arg + 5, 1, 0);
7213 else if (!strncmp (arg, "cpu=", 4))
7214 m68k_set_cpu (arg + 4, 1, 0);
7215 else if (m68k_set_extension (arg, 0, 1))
7216 ;
7217 else if (m68k_set_arch (arg, 0, 1))
7218 ;
7219 else if (m68k_set_cpu (arg, 0, 1))
7220 ;
7221 else
7222 return 0;
7223 break;
7224
7225 default:
7226 return 0;
7227 }
7228
7229 return 1;
7230 }
7231
7232 /* Setup tables from the selected arch and/or cpu */
7233
7234 static void
7235 m68k_init_arch (void)
7236 {
7237 if (not_current_architecture & current_architecture)
7238 {
7239 as_bad (_("architecture features both enabled and disabled"));
7240 not_current_architecture &= ~current_architecture;
7241 }
7242 if (selected_arch)
7243 {
7244 current_architecture |= selected_arch->arch;
7245 control_regs = selected_arch->control_regs;
7246 }
7247 else
7248 current_architecture |= selected_cpu->arch;
7249
7250 current_architecture &= ~not_current_architecture;
7251
7252 if ((current_architecture & (cfloat | m68881)) == (cfloat | m68881))
7253 {
7254 /* Determine which float is really meant. */
7255 if (current_architecture & (m68k_mask & ~m68881))
7256 current_architecture ^= cfloat;
7257 else
7258 current_architecture ^= m68881;
7259 }
7260
7261 if (selected_cpu)
7262 {
7263 control_regs = selected_cpu->control_regs;
7264 if (current_architecture & ~selected_cpu->arch)
7265 {
7266 as_bad (_("selected processor does not have all features of selected architecture"));
7267 current_architecture
7268 = selected_cpu->arch & ~not_current_architecture;
7269 }
7270 }
7271
7272 if ((current_architecture & m68k_mask)
7273 && (current_architecture & ~m68k_mask))
7274 {
7275 as_bad (_ ("m68k and cf features both selected"));
7276 if (current_architecture & m68k_mask)
7277 current_architecture &= m68k_mask;
7278 else
7279 current_architecture &= ~m68k_mask;
7280 }
7281
7282 /* Permit m68881 specification with all cpus; those that can't work
7283 with a coprocessor could be doing emulation. */
7284 if (current_architecture & m68851)
7285 {
7286 if (current_architecture & m68040)
7287 as_warn (_("68040 and 68851 specified; mmu instructions may assemble incorrectly"));
7288 }
7289 /* What other incompatibilities could we check for? */
7290
7291 if (cpu_of_arch (current_architecture) < m68020
7292 || arch_coldfire_p (current_architecture))
7293 md_relax_table[TAB (PCINDEX, BYTE)].rlx_more = 0;
7294
7295 initialized = 1;
7296 }
7297
7298 void
7299 md_show_usage (FILE *stream)
7300 {
7301 const char *default_cpu = TARGET_CPU;
7302 int i;
7303 unsigned int default_arch;
7304
7305 /* Get the canonical name for the default target CPU. */
7306 if (*default_cpu == 'm')
7307 default_cpu++;
7308 for (i = 0; m68k_cpus[i].name; i++)
7309 {
7310 if (strcasecmp (default_cpu, m68k_cpus[i].name) == 0)
7311 {
7312 default_arch = m68k_cpus[i].arch;
7313 while (m68k_cpus[i].alias > 0)
7314 i--;
7315 while (m68k_cpus[i].alias < 0)
7316 i++;
7317 default_cpu = m68k_cpus[i].name;
7318 }
7319 }
7320
7321 fprintf (stream, _("\
7322 -march=<arch> set architecture\n\
7323 -mcpu=<cpu> set cpu [default %s]\n\
7324 "), default_cpu);
7325 for (i = 0; m68k_extensions[i].name; i++)
7326 fprintf (stream, _("\
7327 -m[no-]%-16s enable/disable%s architecture extension\n\
7328 "), m68k_extensions[i].name,
7329 m68k_extensions[i].alias > 0 ? " ColdFire"
7330 : m68k_extensions[i].alias < 0 ? " m68k" : "");
7331
7332 fprintf (stream, _("\
7333 -l use 1 word for refs to undefined symbols [default 2]\n\
7334 -pic, -k generate position independent code\n\
7335 -S turn jbsr into jsr\n\
7336 --pcrel never turn PC-relative branches into absolute jumps\n\
7337 --register-prefix-optional\n\
7338 recognize register names without prefix character\n\
7339 --bitwise-or do not treat `|' as a comment character\n\
7340 --base-size-default-16 base reg without size is 16 bits\n\
7341 --base-size-default-32 base reg without size is 32 bits (default)\n\
7342 --disp-size-default-16 displacement with unknown size is 16 bits\n\
7343 --disp-size-default-32 displacement with unknown size is 32 bits (default)\n\
7344 "));
7345
7346 fprintf (stream, _("Architecture variants are: "));
7347 for (i = 0; m68k_archs[i].name; i++)
7348 {
7349 if (i)
7350 fprintf (stream, " | ");
7351 fprintf (stream, m68k_archs[i].name);
7352 }
7353 fprintf (stream, "\n");
7354
7355 fprintf (stream, _("Processor variants are: "));
7356 for (i = 0; m68k_cpus[i].name; i++)
7357 {
7358 if (i)
7359 fprintf (stream, " | ");
7360 fprintf (stream, m68k_cpus[i].name);
7361 }
7362 fprintf (stream, _("\n"));
7363 }
7364 \f
7365 #ifdef TEST2
7366
7367 /* TEST2: Test md_assemble() */
7368 /* Warning, this routine probably doesn't work anymore. */
7369 int
7370 main (void)
7371 {
7372 struct m68k_it the_ins;
7373 char buf[120];
7374 char *cp;
7375 int n;
7376
7377 m68k_ip_begin ();
7378 for (;;)
7379 {
7380 if (!gets (buf) || !*buf)
7381 break;
7382 if (buf[0] == '|' || buf[1] == '.')
7383 continue;
7384 for (cp = buf; *cp; cp++)
7385 if (*cp == '\t')
7386 *cp = ' ';
7387 if (is_label (buf))
7388 continue;
7389 memset (&the_ins, '\0', sizeof (the_ins));
7390 m68k_ip (&the_ins, buf);
7391 if (the_ins.error)
7392 {
7393 printf (_("Error %s in %s\n"), the_ins.error, buf);
7394 }
7395 else
7396 {
7397 printf (_("Opcode(%d.%s): "), the_ins.numo, the_ins.args);
7398 for (n = 0; n < the_ins.numo; n++)
7399 printf (" 0x%x", the_ins.opcode[n] & 0xffff);
7400 printf (" ");
7401 print_the_insn (&the_ins.opcode[0], stdout);
7402 (void) putchar ('\n');
7403 }
7404 for (n = 0; n < strlen (the_ins.args) / 2; n++)
7405 {
7406 if (the_ins.operands[n].error)
7407 {
7408 printf ("op%d Error %s in %s\n", n, the_ins.operands[n].error, buf);
7409 continue;
7410 }
7411 printf ("mode %d, reg %d, ", the_ins.operands[n].mode,
7412 the_ins.operands[n].reg);
7413 if (the_ins.operands[n].b_const)
7414 printf ("Constant: '%.*s', ",
7415 1 + the_ins.operands[n].e_const - the_ins.operands[n].b_const,
7416 the_ins.operands[n].b_const);
7417 printf ("ireg %d, isiz %d, imul %d, ", the_ins.operands[n].ireg,
7418 the_ins.operands[n].isiz, the_ins.operands[n].imul);
7419 if (the_ins.operands[n].b_iadd)
7420 printf ("Iadd: '%.*s',",
7421 1 + the_ins.operands[n].e_iadd - the_ins.operands[n].b_iadd,
7422 the_ins.operands[n].b_iadd);
7423 putchar ('\n');
7424 }
7425 }
7426 m68k_ip_end ();
7427 return 0;
7428 }
7429
7430 int
7431 is_label (char *str)
7432 {
7433 while (*str == ' ')
7434 str++;
7435 while (*str && *str != ' ')
7436 str++;
7437 if (str[-1] == ':' || str[1] == '=')
7438 return 1;
7439 return 0;
7440 }
7441
7442 #endif
7443
7444 /* Possible states for relaxation:
7445
7446 0 0 branch offset byte (bra, etc)
7447 0 1 word
7448 0 2 long
7449
7450 1 0 indexed offsets byte a0@(32,d4:w:1) etc
7451 1 1 word
7452 1 2 long
7453
7454 2 0 two-offset index word-word a0@(32,d4)@(45) etc
7455 2 1 word-long
7456 2 2 long-word
7457 2 3 long-long
7458
7459 */
7460
7461 /* We have no need to default values of symbols. */
7462
7463 symbolS *
7464 md_undefined_symbol (char *name ATTRIBUTE_UNUSED)
7465 {
7466 return 0;
7467 }
7468
7469 /* Round up a section size to the appropriate boundary. */
7470 valueT
7471 md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size)
7472 {
7473 #ifdef OBJ_AOUT
7474 /* For a.out, force the section size to be aligned. If we don't do
7475 this, BFD will align it for us, but it will not write out the
7476 final bytes of the section. This may be a bug in BFD, but it is
7477 easier to fix it here since that is how the other a.out targets
7478 work. */
7479 int align;
7480
7481 align = bfd_get_section_alignment (stdoutput, segment);
7482 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
7483 #endif
7484
7485 return size;
7486 }
7487
7488 /* Exactly what point is a PC-relative offset relative TO?
7489 On the 68k, it is relative to the address of the first extension
7490 word. The difference between the addresses of the offset and the
7491 first extension word is stored in fx_pcrel_adjust. */
7492 long
7493 md_pcrel_from (fixS *fixP)
7494 {
7495 int adjust;
7496
7497 /* Because fx_pcrel_adjust is a char, and may be unsigned, we explicitly
7498 sign extend the value here. */
7499 adjust = ((fixP->fx_pcrel_adjust & 0xff) ^ 0x80) - 0x80;
7500 if (adjust == 64)
7501 adjust = -1;
7502 return fixP->fx_where + fixP->fx_frag->fr_address - adjust;
7503 }
7504
7505 #ifdef OBJ_ELF
7506 void
7507 m68k_elf_final_processing (void)
7508 {
7509 unsigned flags = 0;
7510
7511 if (arch_coldfire_fpu (current_architecture))
7512 flags |= EF_M68K_CFV4E;
7513 /* Set file-specific flags if this is a cpu32 processor. */
7514 if (cpu_of_arch (current_architecture) & cpu32)
7515 flags |= EF_M68K_CPU32;
7516 else if ((cpu_of_arch (current_architecture) & m68000up)
7517 && !(cpu_of_arch (current_architecture) & m68020up))
7518 flags |= EF_M68K_M68000;
7519
7520 if (current_architecture & mcfisa_a)
7521 {
7522 static const unsigned isa_features[][2] =
7523 {
7524 {EF_M68K_ISA_A_NODIV, mcfisa_a},
7525 {EF_M68K_ISA_A, mcfisa_a|mcfhwdiv},
7526 {EF_M68K_ISA_A_PLUS,mcfisa_a|mcfisa_aa|mcfhwdiv|mcfusp},
7527 {EF_M68K_ISA_B_NOUSP,mcfisa_a|mcfisa_b|mcfhwdiv},
7528 {EF_M68K_ISA_B, mcfisa_a|mcfisa_b|mcfhwdiv|mcfusp},
7529 {0,0},
7530 };
7531 static const unsigned mac_features[][2] =
7532 {
7533 {EF_M68K_MAC, mcfmac},
7534 {EF_M68K_EMAC, mcfemac},
7535 {0,0},
7536 };
7537 unsigned ix;
7538 unsigned pattern;
7539
7540 pattern = (current_architecture
7541 & (mcfisa_a|mcfisa_aa|mcfisa_b|mcfhwdiv|mcfusp));
7542 for (ix = 0; isa_features[ix][1]; ix++)
7543 {
7544 if (pattern == isa_features[ix][1])
7545 {
7546 flags |= isa_features[ix][0];
7547 break;
7548 }
7549 }
7550 if (!isa_features[ix][1])
7551 {
7552 cf_bad:
7553 as_warn (_("Not a defined coldfire architecture"));
7554 }
7555 else
7556 {
7557 if (current_architecture & cfloat)
7558 flags |= EF_M68K_FLOAT | EF_M68K_CFV4E;
7559
7560 pattern = current_architecture & (mcfmac|mcfemac);
7561 if (pattern)
7562 {
7563 for (ix = 0; mac_features[ix][1]; ix++)
7564 {
7565 if (pattern == mac_features[ix][1])
7566 {
7567 flags |= mac_features[ix][0];
7568 break;
7569 }
7570 }
7571 if (!mac_features[ix][1])
7572 goto cf_bad;
7573 }
7574 }
7575 }
7576 elf_elfheader (stdoutput)->e_flags |= flags;
7577 }
7578 #endif
7579
7580 int
7581 tc_m68k_regname_to_dw2regnum (const char *regname)
7582 {
7583 unsigned int regnum;
7584 static const char *const regnames[] =
7585 {
7586 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
7587 "a0", "a1", "a2", "a3", "a4", "a5", "a6", "sp",
7588 "fp0", "fp1", "fp2", "fp3", "fp4", "fp5", "fp6", "fp7",
7589 "pc"
7590 };
7591
7592 for (regnum = 0; regnum < ARRAY_SIZE (regnames); regnum++)
7593 if (strcmp (regname, regnames[regnum]) == 0)
7594 return regnum;
7595
7596 return -1;
7597 }
7598
7599 void
7600 tc_m68k_frame_initial_instructions (void)
7601 {
7602 static int sp_regno = -1;
7603
7604 if (sp_regno < 0)
7605 sp_regno = tc_m68k_regname_to_dw2regnum ("sp");
7606
7607 cfi_add_CFA_def_cfa (sp_regno, -DWARF2_CIE_DATA_ALIGNMENT);
7608 cfi_add_CFA_offset (DWARF2_DEFAULT_RETURN_COLUMN, DWARF2_CIE_DATA_ALIGNMENT);
7609 }
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