include/opcode/m88k.h

   1 /* Table of opcodes for the motorola 88k family.
   2    Copyright 1989, 1990, 1991, 1992, 1993 Free Software Foundation, Inc.
   3
   4 This file is part of GDB and GAS.
   5
   6 This program is free software; you can redistribute it and/or modify
   7 it under the terms of the GNU General Public License as published by
   8 the Free Software Foundation; either version 2 of the License, or
   9 (at your option) any later version.
  10
  11 This program is distributed in the hope that it will be useful,
  12 but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14 GNU General Public License for more details.
  15
  16 You should have received a copy of the GNU General Public License
  17 along with this program; if not, write to the Free Software
  18 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
  19
  20 /*
  21  *                      Disassembler Instruction Table
  22  *
  23  *      The first field of the table is the opcode field. If an opcode
  24  *      is specified which has any non-opcode bits on, a system error
  25  *      will occur when the system attempts the install it into the
  26  *      instruction table.  The second parameter is a pointer to the
  27  *      instruction mnemonic. Each operand is specified by offset, width,
  28  *      and type. The offset is the bit number of the least significant
  29  *      bit of the operand with bit 0 being the least significant bit of
  30  *      the instruction. The width is the number of bits used to specify
  31  *      the operand. The type specifies the output format to be used for
  32  *      the operand. The valid formats are: register, register indirect,
  33  *      hex constant, and bit field specification.  The last field is a
  34  *      pointer to the next instruction in the linked list.  These pointers
  35  *      are initialized by init_disasm().
  36  *
  37  *                              Structure Format
  38  *
  39  *       struct INSTAB {
  40  *          UPINT opcode;
  41  *          char *mnemonic;
  42  *          struct OPSPEC op1,op2,op3;
  43  *          struct SIM_FLAGS flgs;
  44  *          struct INSTAB *next;
  45  *       }
  46  *
  47  *       struct OPSPEC {
  48  *          UPINT offset:5;
  49  *          UPINT width:6;
  50  *          UPINT type:5;
  51  *       }
  52  *
  53  *                              Revision History
  54  *
  55  *      Revision 1.0    11/08/85        Creation date
  56  *               1.1    02/05/86        Updated instruction mnemonic table MD
  57  *               1.2    06/16/86        Updated SIM_FLAGS for floating point
  58  *               1.3    09/20/86        Updated for new encoding
  59  *                      05/11/89        R. Trawick adapted from Motorola disassembler
  60  */
  61
  62 #include <stdio.h>
  63
  64
  65 /*
  66  * This file contains the structures and constants needed to build the M88000
  67  * simulator.  It is the main include file, containing all the
  68  * structures, macros and definitions except for the floating point
  69  * instruction set.
  70  */
  71
  72 /*
  73  * The following flag informs the Simulator as to what type of byte ordering
  74  * will be used. For instance, a BOFLAG = 1 indicates a DEC VAX and IBM type
  75  * of ordering shall be used.
  76 */
  77
  78 /* # define     BOFLAG   1 */                       /* BYTE ORDERING FLAG */
  79
  80 /* define the number of bits in the primary opcode field of the instruction,
  81  * the destination field, the source 1 and source 2 fields.
  82  */
  83 # define    OP       8                        /* size of opcode field */
  84 # define    DEST     6                        /* size of destination  */
  85 # define    SOURCE1  6                        /* size of source1      */
  86 # define    SOURCE2  6                        /* size of source2      */
  87
  88 # define    REGs    32                        /* number of registers  */
  89
  90 # define    WORD    long
  91 # define    FLAG    unsigned
  92 # define    STATE   short
  93
  94 # define    TRUE     1
  95 # define    FALSE    0
  96
  97 # define    READ     0
  98 # define    WRITE    1
  99
 100 /* The next four equates define the priorities that the various classes
 101  * of instructions have regarding writing results back into registers and
 102  * signalling exceptions.
 103  */
 104 /* PMEM is also defined in <sys/param.h> on Delta 88's.  Sigh!  */
 105 #undef PMEM
 106
 107 # define    PINT  0   /* Integer Priority */
 108 # define    PFLT  1   /* Floating Point Priority */
 109 # define    PMEM  2   /* Memory Priority */
 110 # define    NA    3   /* Not Applicable, instruction doesnt write to regs */
 111 # define    HIPRI 3   /* highest of these priorities */
 112
 113 /* The instruction registers are an artificial mechanism to speed up
 114  * simulator execution.  In the real processor, an instruction register
 115  * is 32 bits wide.  In the simulator, the 32 bit instruction is kept in
 116  * a structure field called rawop, and the instruction is partially decoded,
 117  * and split into various fields and flags which make up the other fields
 118  * of the structure.
 119  * The partial decode is done when the instructions are initially loaded
 120  * into simulator memory.  The simulator code memory is not an array of
 121  * 32 bit words, but is an array of instruction register structures.
 122  * Yes this wastes memory, but it executes much quicker.
 123  */
 124
 125 struct IR_FIELDS {
 126                     unsigned        op:OP,
 127                                     dest: DEST,
 128                                     src1: SOURCE1,
 129                                     src2: SOURCE2;
 130                               int   ltncy,
 131                                     extime,
 132                                     wb_pri;     /* writeback priority     */
 133                     unsigned        imm_flags:2,/* immediate size         */
 134                                     rs1_used:1, /* register source 1 used */
 135                                     rs2_used:1, /* register source 2 used */
 136                                     rsd_used:1, /* register source/dest. used */
 137                                     c_flag:1,   /* complement      */
 138                                     u_flag:1,   /* upper half word */
 139                                     n_flag:1,   /* execute next    */
 140                                     wb_flag:1,  /* uses writeback slot */
 141                                     dest_64:1,  /* dest size       */
 142                                     s1_64:1,    /* source 1 size   */
 143                                     s2_64:1,    /* source 2 size   */
 144                                     scale_flag:1, /* scaled register */
 145                                     brk_flg:1;
 146                  };
 147
 148 struct  mem_segs {
 149         struct mem_wrd *seg;                    /* pointer (returned by calloc) to segment */
 150         unsigned long baseaddr;                 /* base load address from file headers */
 151         unsigned long endaddr;                  /* Ending address of segment */
 152         int           flags;                    /* segment control flags (none defined 12/5/86) */
 153 };
 154
 155 #define MAXSEGS         (10)                    /* max number of segment allowed */
 156 #define MEMSEGSIZE      (sizeof(struct mem_segs))/* size of mem_segs structure */
 157
 158
 159 #define BRK_RD          (0x01)                  /* break on memory read */
 160 #define BRK_WR          (0x02)                  /* break on memory write */
 161 #define BRK_EXEC        (0x04)                  /* break on execution */
 162 #define BRK_CNT         (0x08)                  /* break on terminal count */
 163
 164
 165 struct  mem_wrd {
 166         struct IR_FIELDS opcode;                /* simulator instruction break down */
 167         union {
 168                 unsigned long  l;               /* memory element break down */
 169                 unsigned short s[2];
 170                 unsigned char  c[4];
 171         } mem;
 172 };
 173
 174 #define MEMWRDSIZE      (sizeof(struct mem_wrd))        /* size of each 32 bit memory model */
 175
 176 /* External declarations */
 177
 178 extern  struct mem_segs memory[];
 179 extern  struct PROCESSOR m78000;
 180
 181 struct  PROCESSOR   {
 182              unsigned WORD
 183                             ip,          /* execute instruction pointer */
 184                             vbr,         /* vector base register */
 185                             psr;         /* processor status register */
 186
 187                     WORD    S1bus, /* source 1 */
 188                             S2bus, /* source 2 */
 189                             Dbus,  /* destination */
 190                             DAbus, /* data address bus */
 191                             ALU,
 192                             Regs[REGs],       /* data registers */
 193                             time_left[REGs],  /* max clocks before reg is available */
 194                             wb_pri[REGs],     /* writeback priority of reg */
 195                             SFU0_regs[REGs],  /* integer unit control regs */
 196                             SFU1_regs[REGs],  /* floating point control regs */
 197                             Scoreboard[REGs],
 198                             Vbr;
 199             unsigned WORD   scoreboard,
 200                             Psw,
 201                             Tpsw;
 202                     FLAG   jump_pending:1;   /* waiting for a jump instr. */
 203                     };
 204
 205 # define    i26bit      1    /* size of immediate field */
 206 # define    i16bit      2
 207 # define    i10bit      3
 208
 209 /* Definitions for fields in psr */
 210
 211 # define mode  31
 212 # define rbo   30
 213 # define ser   29
 214 # define carry 28
 215 # define sf7m  11
 216 # define sf6m  10
 217 # define sf5m   9
 218 # define sf4m   8
 219 # define sf3m   7
 220 # define sf2m   6
 221 # define sf1m   5
 222 # define mam    4
 223 # define inm    3
 224 # define exm    2
 225 # define trm    1
 226 # define ovfm   0
 227
 228 #define     MODEMASK   (1<<(mode-1))
 229 # define    SILENT     0   /* simulate without output to crt */
 230 # define    VERBOSE    1   /* simulate in verbose mode */
 231 # define    PR_INSTR   2   /* only print instructions */
 232
 233 # define    RESET      16 /* reset phase */
 234
 235 # define    PHASE1     0  /* data path phases */
 236 # define    PHASE2     1
 237
 238 /* the 1 clock operations */
 239
 240 # define    ADDU        1
 241 # define    ADDC        2
 242 # define    ADDUC       3
 243 # define    ADD         4
 244
 245 # define    SUBU    ADD+1
 246 # define    SUBB    ADD+2
 247 # define    SUBUB   ADD+3
 248 # define    SUB     ADD+4
 249
 250 # define    AND_    ADD+5
 251 # define    OR      ADD+6
 252 # define    XOR     ADD+7
 253 # define    CMP     ADD+8
 254
 255 /* the LOADS */
 256
 257 # define    LDAB    CMP+1
 258 # define    LDAH    CMP+2
 259 # define    LDA     CMP+3
 260 # define    LDAD    CMP+4
 261
 262 # define    LDB   LDAD+1
 263 # define    LDH   LDAD+2
 264 # define    LD    LDAD+3
 265 # define    LDD   LDAD+4
 266 # define    LDBU  LDAD+5
 267 # define    LDHU  LDAD+6
 268
 269 /* the STORES */
 270
 271 # define    STB    LDHU+1
 272 # define    STH    LDHU+2
 273 # define    ST     LDHU+3
 274 # define    STD    LDHU+4
 275
 276 /* the exchange */
 277
 278 # define    XMEMBU LDHU+5
 279 # define    XMEM   LDHU+6
 280
 281 /* the branches */
 282 # define    JSR    STD+1
 283 # define    BSR    STD+2
 284 # define    BR     STD+3
 285 # define    JMP    STD+4
 286 # define    BB1    STD+5
 287 # define    BB0    STD+6
 288 # define    RTN    STD+7
 289 # define    BCND   STD+8
 290
 291 /* the TRAPS */
 292 # define    TB1    BCND+1
 293 # define    TB0    BCND+2
 294 # define    TCND   BCND+3
 295 # define    RTE    BCND+4
 296 # define    TBND   BCND+5
 297
 298 /* the MISC instructions */
 299 # define    MUL     TBND + 1
 300 # define    DIV     MUL  +2
 301 # define    DIVU    MUL  +3
 302 # define    MASK    MUL  +4
 303 # define    FF0     MUL  +5
 304 # define    FF1     MUL  +6
 305 # define    CLR     MUL  +7
 306 # define    SET     MUL  +8
 307 # define    EXT     MUL  +9
 308 # define    EXTU    MUL  +10
 309 # define    MAK     MUL  +11
 310 # define    ROT     MUL  +12
 311
 312 /* control register manipulations */
 313
 314 # define    LDCR    ROT  +1
 315 # define    STCR    ROT  +2
 316 # define    XCR     ROT  +3
 317
 318 # define    FLDCR    ROT  +4
 319 # define    FSTCR    ROT  +5
 320 # define    FXCR     ROT  +6
 321
 322
 323 # define    NOP     XCR +1
 324
 325 /* floating point instructions */
 326
 327 # define    FADD    NOP +1
 328 # define    FSUB    NOP +2
 329 # define    FMUL    NOP +3
 330 # define    FDIV    NOP +4
 331 # define    FSQRT   NOP +5
 332 # define    FCMP    NOP +6
 333 # define    FIP     NOP +7
 334 # define    FLT     NOP +8
 335 # define    INT     NOP +9
 336 # define    NINT    NOP +10
 337 # define    TRNC    NOP +11
 338 # define    FLDC   NOP +12
 339 # define    FSTC   NOP +13
 340 # define    FXC    NOP +14
 341
 342 # define UEXT(src,off,wid) ((((unsigned int)(src))>>(off)) & ((1<<(wid)) - 1))
 343 # define SEXT(src,off,wid) (((((int)(src))<<(32-((off)+(wid)))) >>(32-(wid))) )
 344 # define MAKE(src,off,wid) \
 345   ((((unsigned int)(src)) & ((1<<(wid)) - 1)) << (off))
 346
 347 # define opword(n) (unsigned long) (memaddr->mem.l)
 348
 349 /*  Constants and Masks */
 350
 351 #define SFU0       0x80000000
 352 #define SFU1       0x84000000
 353 #define SFU7       0x9c000000
 354 #define RRI10      0xf0000000
 355 #define RRR        0xf4000000
 356 #define SFUMASK    0xfc00ffe0
 357 #define RRRMASK    0xfc00ffe0
 358 #define RRI10MASK  0xfc00fc00
 359 #define DEFMASK    0xfc000000
 360 #define CTRL       0x0000f000
 361 #define CTRLMASK   0xfc00f800
 362
 363 /* Operands types */
 364
 365 enum operand_type {
 366   HEX = 1,
 367   REG = 2,
 368   CONT = 3,
 369   IND = 3,
 370   BF = 4,
 371   REGSC = 5    /* scaled register */,
 372   CRREG = 6    /* control register */,
 373   FCRREG = 7    /* floating point control register */,
 374   PCREL = 8,
 375   CONDMASK = 9,
 376   XREG = 10, /* extended register */
 377   DEC = 11, /* decimal */
 378 };
 379
 380 /* Hashing Specification */
 381
 382 #define HASHVAL     79
 383
 384 /* Type definitions */
 385
 386 typedef unsigned int UINT;
 387
 388 /* Structure templates */
 389
 390 #if never
 391 typedef struct {
 392    unsigned int offset:5;
 393    unsigned int width:6;
 394    unsigned int type:5;
 395 } OPSPEC;
 396 #endif
 397
 398 typedef struct {
 399    unsigned int offset;
 400    unsigned int width;
 401    enum operand_type type;
 402 } OPSPEC;
 403
 404         struct SIM_FLAGS {
 405               int  ltncy,   /* latency (max number of clocks needed to execute) */
 406                   extime,   /* execution time (min number of clocks needed to execute) */
 407                   wb_pri;   /* writeback slot priority */
 408    unsigned         op:OP,   /* simulator version of opcode */
 409              imm_flags:2,   /* 10,16 or 26 bit immediate flags */
 410               rs1_used:1,   /* register source 1 used */
 411               rs2_used:1,   /* register source 2 used */
 412               rsd_used:1,   /* register source/dest used */
 413                 c_flag:1,   /* complement */
 414                 u_flag:1,   /* upper half word */
 415                 n_flag:1,   /* execute next */
 416                wb_flag:1,   /* uses writeback slot */
 417                dest_64:1,   /* double precision dest */
 418                  s1_64:1,   /* double precision source 1 */
 419                  s2_64:1,   /* double precision source 2 */
 420             scale_flag:1;   /* register is scaled */
 421 };
 422
 423 typedef struct INSTRUCTAB {
 424    unsigned int  opcode;
 425    char          *mnemonic;
 426    OPSPEC        op1,op2,op3;
 427    struct SIM_FLAGS flgs;
 428    struct INSTRUCTAB    *next;
 429 } INSTAB;
 430 \f
 431
 432 #define NO_OPERAND {0,0,0}
 433
 434 /* Opcode     Mnemonic       Op 1 Spec     Op 2 Spec    Op 3 Spec         Simflags             Next  */
 435
 436 static INSTAB  instructions[] = {
 437   {0xf400c800,"jsr         ",{0,5,REG}   ,NO_OPERAND      ,NO_OPERAND   , {2,2,NA,JSR ,          0,0,1,0,0,0,0,1,0,0,0,0}, NULL },
 438   {0xf400cc00,"jsr.n       ",{0,5,REG}   ,NO_OPERAND      ,NO_OPERAND   , {1,1,NA,JSR ,          0,0,1,0,0,0,1,1,0,0,0,0}, NULL },
 439   {0xf400c000,"jmp         ",{0,5,REG}   ,NO_OPERAND      ,NO_OPERAND   , {2,2,NA,JMP ,          0,0,1,0,0,0,0,1,0,0,0,0}, NULL },
 440   {0xf400c400,"jmp.n       ",{0,5,REG}   ,NO_OPERAND      ,NO_OPERAND   , {1,1,NA,JMP ,          0,0,1,0,0,0,1,1,0,0,0,0}, NULL },
 441   {0xc8000000,"bsr         ",{0,26,PCREL},NO_OPERAND      ,NO_OPERAND   , {2,2,NA,BSR ,     i26bit,0,0,0,0,0,0,1,0,0,0,0}, NULL },
 442   {0xcc000000,"bsr.n       ",{0,26,PCREL},NO_OPERAND      ,NO_OPERAND   , {1,1,NA,BSR ,     i26bit,0,0,0,0,0,1,1,0,0,0,0}, NULL },
 443   {0xc0000000,"br          ",{0,26,PCREL},NO_OPERAND      ,NO_OPERAND   , {2,2,NA,BR  ,     i26bit,0,0,0,0,0,0,1,0,0,0,0}, NULL },
 444   {0xc4000000,"br.n        ",{0,26,PCREL},NO_OPERAND      ,NO_OPERAND   , {1,1,NA,BR  ,     i26bit,0,0,0,0,0,1,1,0,0,0,0}, NULL },
 445   {0xd0000000,"bb0         ",{21,5,HEX}  ,{16,5,REG}   ,{0,16,PCREL},{2,2,NA,BB0,     i16bit,0,1,0,0,0,0,1,0,0,0,0}, NULL },
 446   {0xd4000000,"bb0.n       ",{21,5,HEX}  ,{16,5,REG}   ,{0,16,PCREL},{1,1,NA,BB0,     i16bit,0,1,0,0,0,1,1,0,0,0,0}, NULL },
 447   {0xd8000000,"bb1         ",{21,5,HEX},{16,5,REG}     ,{0,16,PCREL},{2,2,NA,BB1,     i16bit,0,1,0,0,0,0,1,0,0,0,0}, NULL },
 448   {0xdc000000,"bb1.n       ",{21,5,HEX},{16,5,REG}     ,{0,16,PCREL},{1,1,NA,BB1,     i16bit,0,1,0,0,0,1,1,0,0,0,0}, NULL },
 449   {0xf000d000,"tb0         ",{21,5,HEX}  ,{16,5,REG}   ,{0,10,HEX}, {2,2,NA,TB0 ,     i10bit,0,1,0,0,0,0,1,0,0,0,0}, NULL },
 450   {0xf000d800,"tb1         ",{21,5,HEX}  ,{16,5,REG}   ,{0,10,HEX}, {2,2,NA,TB1 ,     i10bit,0,1,0,0,0,0,1,0,0,0,0}, NULL },
 451   {0xe8000000,"bcnd        ",{21,5,CONDMASK},{16,5,REG},{0,16,PCREL},{2,2,NA,BCND,    i16bit,0,1,0,0,0,0,1,0,0,0,0}, NULL },
 452   {0xec000000,"bcnd.n      ",{21,5,CONDMASK},{16,5,REG},{0,16,PCREL},{1,1,NA,BCND,    i16bit,0,1,0,0,0,1,1,0,0,0,0}, NULL },
 453   {0xf000e800,"tcnd        ",{21,5,CONDMASK},{16,5,REG},{0,10,HEX}, {2,2,NA,TCND,     i10bit,0,1,0,0,0,0,1,0,0,0,0}, NULL },
 454   {0xf8000000,"tbnd        ",{16,5,REG}  ,{0,16,HEX}   ,NO_OPERAND   , {2,2,NA,TBND,     i10bit,1,0,0,0,0,0,1,0,0,0,0}, NULL },
 455   {0xf400f800,"tbnd        ",{16,5,REG}  ,{0,5,REG}    ,NO_OPERAND   , {2,2,NA,TBND,          0,1,1,0,0,0,0,1,0,0,0,0}, NULL },
 456   {0xf400fc00,"rte         ",NO_OPERAND     ,NO_OPERAND      ,NO_OPERAND   , {2,2,NA,RTE ,          0,0,0,0,0,0,0,1,0,0,0,0}, NULL },
 457   {0x1c000000,"ld.b        ",{21,5,REG}  ,{16,5,REG}   ,{0,16,HEX}, {3,1,PMEM,LDB    ,i16bit,1,0,1,0,0,0,1,0,0,0,0}, NULL },
 458   {0xf4001c00,"ld.b        ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {3,1,PMEM,LDB     ,    0,1,1,1,0,0,0,1,0,0,0,0}, NULL },
 459   {0x0c000000,"ld.bu       ",{21,5,REG}  ,{16,5,REG}   ,{0,16,HEX}, {3,1,PMEM,LDBU,   i16bit,1,0,1,0,0,0,1,0,0,0,0}, NULL },
 460   {0xf4000c00,"ld.bu       ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {3,1,PMEM,LDBU        ,0,1,1,1,0,0,0,1,0,0,0,0}, NULL },
 461   {0x18000000,"ld.h        ",{21,5,REG}  ,{16,5,REG}   ,{0,16,HEX}, {3,1,PMEM,LDH    ,i16bit,1,0,1,0,0,0,1,0,0,0,0}, NULL },
 462   {0xf4001800,"ld.h        ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {3,1,PMEM,LDH         ,0,1,1,1,0,0,0,1,0,0,0,0}, NULL },
 463   {0xf4001a00,"ld.h        ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REGSC},{3,1,PMEM,LDH         ,0,1,1,1,0,0,0,1,0,0,0,1}, NULL },
 464   {0x08000000,"ld.hu       ",{21,5,REG}  ,{16,5,REG}   ,{0,16,HEX}, {3,1,PMEM,LDHU,   i16bit,1,0,1,0,0,0,1,0,0,0,0}, NULL },
 465   {0xf4000800,"ld.hu       ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {3,1,PMEM,LDHU        ,0,1,1,1,0,0,0,1,0,0,0,0}, NULL },
 466   {0xf4000a00,"ld.hu       ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REGSC},{3,1,PMEM,LDHU        ,0,1,1,1,0,0,0,1,0,0,0,1}, NULL },
 467   {0x14000000,"ld          ",{21,5,REG}  ,{16,5,REG}   ,{0,16,HEX}, {3,1,PMEM,LD     ,i16bit,1,0,1,0,0,0,1,0,0,0,0}, NULL },
 468   {0xf4001400,"ld          ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {3,1,PMEM,LD          ,0,1,1,1,0,0,0,1,0,0,0,0}, NULL },
 469   {0xf4001600,"ld          ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REGSC},{3,1,PMEM,LD          ,0,1,1,1,0,0,0,1,0,0,0,1}, NULL },
 470   {0x10000000,"ld.d        ",{21,5,REG}  ,{16,5,REG}   ,{0,16,HEX}, {3,1,PMEM,LDD    ,i16bit,1,0,1,0,0,0,1,0,0,0,0}, NULL },
 471   {0xf4001000,"ld.d        ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {3,1,PMEM,LDD         ,0,1,1,1,0,0,0,1,0,0,0,0}, NULL },
 472   {0xf4001200,"ld.d        ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REGSC},{3,1,PMEM,LDD         ,0,1,1,1,0,0,0,1,0,0,0,1}, NULL },
 473   {0xf4001500,"ld.usr      ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {3,1,PMEM,LD          ,0,1,1,1,0,0,0,1,0,0,0,0}, NULL },
 474   {0xf4001700,"ld.usr      ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REGSC},{3,1,PMEM,LD          ,0,1,1,1,0,0,0,1,0,0,0,1}, NULL },
 475   {0x2c000000,"st.b        ",{21,5,REG}  ,{16,5,REG}   ,{0,16,HEX}, {1,1,NA,STB      ,i16bit,1,0,1,0,0,0,1,0,0,0,0}, NULL },
 476   {0xf4002c00,"st.b        ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {1,1,NA,STB           ,0,1,1,1,0,0,0,1,0,0,0,0}, NULL },
 477   {0x28000000,"st.h        ",{21,5,REG}  ,{16,5,REG}   ,{0,16,HEX}, {1,1,NA,STH      ,i16bit,1,0,1,0,0,0,1,0,0,0,0}, NULL },
 478   {0xf4002800,"st.h        ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {1,1,NA,STH           ,0,1,1,1,0,0,0,1,0,0,0,0}, NULL },
 479   {0xf4002a00,"st.h        ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REGSC},{1,1,NA,STH           ,0,1,1,1,0,0,0,1,0,0,0,1}, NULL },
 480   {0x24000000,"st          ",{21,5,REG}  ,{16,5,REG}   ,{0,16,HEX}, {1,1,NA,ST       ,i16bit,1,0,1,0,0,0,1,0,0,0,0}, NULL },
 481   {0xf4002400,"st          ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {1,1,NA,ST            ,0,1,1,1,0,0,0,1,0,0,0,0}   ,NULL },
 482   {0xf4002600,"st          ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REGSC},{1,1,NA,ST            ,0,1,1,1,0,0,0,1,0,0,0,1}   ,NULL },
 483   {0x20000000,"st.d        ",{21,5,REG}  ,{16,5,REG}   ,{0,16,HEX}, {1,1,NA,STD      ,i16bit,0,1,0,0,0,0,1,0,0,0,0}   ,NULL },
 484   {0xf4002000,"st.d        ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {1,1,NA,STD           ,0,1,1,1,0,0,0,1,0,0,0,0}   ,NULL },
 485   {0xf4002200,"st.d        ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REGSC},{1,1,NA,STD           ,0,1,1,1,0,0,0,1,0,0,0,1}   ,NULL },
 486   {0xf4002500,"st.usr      ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {1,1,NA,ST            ,0,1,1,1,0,0,0,1,0,0,0,0}   ,NULL },
 487   {0xf4002700,"st.usr      ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REGSC},{1,1,NA,ST            ,0,1,1,1,0,0,0,1,0,0,0,1}   ,NULL },
 488 /*  m88100 only:
 489   {0x00000000,"xmem.bu     ",{21,5,REG}  ,{16,5,REG}   ,{0,16,HEX}, {3,1,PMEM,XMEMBU ,i16bit,1,1,1,0,0,0,1,0,0,0,0}   ,NULL },
 490  */
 491   {0xf4000000,"xmem.bu     ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {3,1,PMEM,XMEM        ,0,1,1,1,0,0,0,1,0,0,0,0}   ,NULL },
 492 /*  m88100 only:
 493   {0x04000000,"xmem        ",{21,5,REG}  ,{16,5,REG}   ,{0,16,HEX}, {3,1,PMEM,XMEM   ,i16bit,1,1,1,0,0,0,1,0,0,0,0}   ,NULL },
 494  */
 495   {0xf4000400,"xmem        ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {3,1,PMEM,XMEM        ,0,1,1,1,0,0,0,1,0,0,0,0}   ,NULL },
 496   {0xf4000600,"xmem        ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REGSC},{3,1,PMEM,XMEM        ,0,1,1,1,0,0,0,1,0,0,0,1}   ,NULL },
 497   {0xf4000500,"xmem.usr    ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {3,1,PMEM,XMEM        ,0,1,1,1,0,0,0,1,0,0,0,0}   ,NULL },
 498   {0xf4000700,"xmem.usr    ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REGSC},{3,1,PMEM,XMEM        ,0,1,1,1,0,0,0,1,0,0,0,1}   ,NULL },
 499 /* m88100 only:
 500   {0xf4003e00,"lda.b       ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REGSC},{1,1,PINT,LDAH,        0,1,1,1,0,0,0,0,0,0,0,1}   ,NULL },
 501  */
 502   {0xf4003e00,"lda.x       ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REGSC},{1,1,PINT,LDAH,        0,1,1,1,0,0,0,0,0,0,0,1}   ,NULL },
 503   {0xf4003a00,"lda.h       ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REGSC},{1,1,PINT,LDAH,        0,1,1,1,0,0,0,0,0,0,0,1}   ,NULL },
 504   {0xf4003600,"lda         ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REGSC},{1,1,PINT,LDA ,        0,1,1,1,0,0,0,0,0,0,0,1}   ,NULL },
 505   {0xf4003200,"lda.d       ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REGSC},{1,1,PINT,LDAD,        0,1,1,1,0,0,0,0,0,0,0,1}   ,NULL },
 506
 507   {0x80004000,"ldcr        ",{21,5,REG}  ,{5,6,CRREG}  ,NO_OPERAND    ,{1,1,PINT,LDCR,        0,1,1,1,0,0,0,0,0,0,0,0}   ,NULL },
 508   {0x80008000,"stcr        ",{16,5,REG}  ,{5,6,CRREG}  ,NO_OPERAND    ,{1,1,PINT,STCR,        0,1,1,1,0,0,0,0,0,0,0,0}   ,NULL },
 509   {0x8000c000,"xcr         ",{21,5,REG}  ,{16,5,REG}   ,{5,6,CRREG},{1,1,PINT,XCR,         0,1,1,1,0,0,0,0,0,0,0,0}   ,NULL },
 510
 511   {0xf4006000,"addu        ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {1,1,PINT,ADDU,        0,1,1,1,0,0,0,0,0,0,0,0}   ,NULL },
 512   {0xf4006200,"addu.ci     ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {1,1,PINT,ADDU,        0,1,1,1,0,0,0,0,0,0,0,0}   ,NULL },
 513   {0xf4006100,"addu.co     ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {1,1,PINT,ADDU,        0,1,1,1,0,0,0,0,0,0,0,0}   ,NULL },
 514   {0xf4006300,"addu.cio    ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {1,1,PINT,ADDU,        0,1,1,1,0,0,0,0,0,0,0,0}   ,NULL },
 515   {0xf4006400,"subu        ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {1,1,PINT,SUBU,        0,1,1,1,0,0,0,0,0,0,0,0}   ,NULL },
 516   {0xf4006600,"subu.ci     ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {1,1,PINT,SUBU,        0,1,1,1,0,0,0,0,0,0,0,0}   ,NULL },
 517   {0xf4006500,"subu.co     ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {1,1,PINT,SUBU,        0,1,1,1,0,0,0,0,0,0,0,0}   ,NULL },
 518   {0xf4006700,"subu.cio    ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {1,1,PINT,SUBU,        0,1,1,1,0,0,0,0,0,0,0,0}   ,NULL },
 519   {0xf4006800,"divu        ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {32,32,PINT,DIVU,        0,1,1,1,0,0,0,0,0,0,0,0}   ,NULL },
 520   {0xf4006900,"divu.d      ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,}, NULL },
 521   {0xf4006e00,"muls        ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,}, NULL },
 522   {0xf4006c00,"mulu        ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {1,4,PINT,MUL,      0,1,1,1,0,0,0,0,0,0,0,0}   ,NULL },
 523   {0xf4007000,"add         ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {1,1,PINT,ADD ,        0,1,1,1,0,0,0,0,0,0,0,0}   ,NULL },
 524   {0xf4007200,"add.ci      ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {1,1,PINT,ADD ,        0,1,1,1,0,0,0,0,0,0,0,0}   ,NULL },
 525   {0xf4007100,"add.co      ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {1,1,PINT,ADD ,        0,1,1,1,0,0,0,0,0,0,0,0}   ,NULL },
 526   {0xf4007300,"add.cio     ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {1,1,PINT,ADD ,        0,1,1,1,0,0,0,0,0,0,0,0}   ,NULL },
 527   {0xf4007400,"sub         ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {1,1,PINT,SUB ,        0,1,1,1,0,0,0,0,0,0,0,0}   ,NULL },
 528   {0xf4007600,"sub.ci      ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {1,1,PINT,SUB ,        0,1,1,1,0,0,0,0,0,0,0,0}   ,NULL },
 529   {0xf4007500,"sub.co      ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {1,1,PINT,SUB ,        0,1,1,1,0,0,0,0,0,0,0,0}   ,NULL },
 530   {0xf4007700,"sub.cio     ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {1,1,PINT,SUB ,        0,1,1,1,0,0,0,0,0,0,0,0}   ,NULL },
 531   {0xf4007800,"divs        ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {32,32,PINT,DIV ,      0,1,1,1,0,0,0,0,0,0,0,0}   ,NULL },
 532   {0xf4007c00,"cmp         ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {1,1,PINT,CMP,         0,1,1,1,0,0,0,0,0,0,0,0}   ,NULL },
 533
 534   {0x60000000,"addu        ",{21,5,REG}  ,{16,5,REG}   ,{0,16,HEX}, {1,1,PINT,ADDU,   i16bit,1,0,1,0,0,0,0,0,0,0,0}   ,NULL },
 535   {0x64000000,"subu        ",{21,5,REG}  ,{16,5,REG}   ,{0,16,HEX}, {1,1,PINT,SUBU,   i16bit,1,0,1,0,0,0,0,0,0,0,0}   ,NULL },
 536
 537   {0x68000000,"divu        ",{21,5,REG}  ,{16,5,REG}   ,{0,16,HEX}, {32,32,PINT,DIVU, i16bit,1,0,1,0,0,0,0,0,0,0,0}   ,NULL },
 538   {0x6c000000,"mulu        ",{21,5,REG}  ,{16,5,REG}   ,{0,16,HEX}, {4,1,PINT,MUL,    i16bit,1,0,1,0,0,0,0,0,0,0,0}   ,NULL },
 539   {0x70000000,"add         ",{21,5,REG}  ,{16,5,REG}   ,{0,16,HEX}, {1,1,PINT,ADD,    i16bit,1,0,1,0,0,0,0,0,0,0,0}   ,NULL },
 540   {0x74000000,"sub         ",{21,5,REG}  ,{16,5,REG}   ,{0,16,HEX}, {1,1,PINT,SUB,    i16bit,1,0,1,0,0,0,0,0,0,0,0}   ,NULL },
 541   {0x78000000,"divs        ",{21,5,REG}  ,{16,5,REG}   ,{0,16,HEX}, {32,32,PINT,DIV,  i16bit,1,0,1,0,0,0,0,0,0,0,0}   ,NULL },
 542   {0x7c000000,"cmp         ",{21,5,REG}  ,{16,5,REG}   ,{0,16,HEX}, {1,1,PINT,CMP,    i16bit,1,0,1,0,0,0,0,0,0,0,0}   ,NULL },
 543
 544   {0xf4004000,"and         ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {1,1,PINT,AND_        ,0,1,1,1,0,0,0,0,0,0,0,0}   ,NULL },
 545   {0xf4004400,"and.c       ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {1,1,PINT,AND_        ,0,1,1,1,1,0,0,0,0,0,0,0}   ,NULL },
 546   {0xf4005800,"or          ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {1,1,PINT,OR          ,0,1,1,1,0,0,0,0,0,0,0,0}   ,NULL },
 547   {0xf4005c00,"or.c        ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {1,1,PINT,OR          ,0,1,1,1,1,0,0,0,0,0,0,0}   ,NULL },
 548   {0xf4005000,"xor         ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {1,1,PINT,XOR         ,0,1,1,1,0,0,0,0,0,0,0,0}   ,NULL },
 549   {0xf4005400,"xor.c       ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {1,1,PINT,XOR         ,0,1,1,1,1,0,0,0,0,0,0,0}   ,NULL },
 550   {0x40000000,"and         ",{21,5,REG}  ,{16,5,REG}   ,{0,16,HEX}, {1,1,PINT,AND_   ,i16bit,1,0,1,0,0,0,0,0,0,0,0}   ,NULL },
 551   {0x44000000,"and.u       ",{21,5,REG}  ,{16,5,REG}   ,{0,16,HEX}, {1,1,PINT,AND_   ,i16bit,1,0,1,0,1,0,0,0,0,0,0}   ,NULL },
 552   {0x58000000,"or          ",{21,5,REG}  ,{16,5,REG}   ,{0,16,HEX}, {1,1,PINT,OR     ,i16bit,1,0,1,0,0,0,0,0,0,0,0}   ,NULL },
 553   {0x5c000000,"or.u        ",{21,5,REG}  ,{16,5,REG}   ,{0,16,HEX}, {1,1,PINT,OR     ,i16bit,1,0,1,0,1,0,0,0,0,0,0}   ,NULL },
 554   {0x50000000,"xor         ",{21,5,REG}  ,{16,5,REG}   ,{0,16,HEX}, {1,1,PINT,XOR    ,i16bit,1,0,1,0,0,0,0,0,0,0,0}   ,NULL },
 555   {0x54000000,"xor.u       ",{21,5,REG}  ,{16,5,REG}   ,{0,16,HEX}, {1,1,PINT,XOR    ,i16bit,1,0,1,0,1,0,0,0,0,0,0}   ,NULL },
 556   {0x48000000,"mask        ",{21,5,REG}  ,{16,5,REG}   ,{0,16,HEX}, {1,1,PINT,MASK   ,i16bit,1,0,1,0,0,0,0,0,0,0,0}   ,NULL },
 557   {0x4c000000,"mask.u      ",{21,5,REG}  ,{16,5,REG}   ,{0,16,HEX}, {1,1,PINT,MASK   ,i16bit,1,0,1,0,1,0,0,0,0,0,0}   ,NULL },
 558   {0xf400ec00,"ff0         ",{21,5,REG}  ,{0,5,REG}    ,NO_OPERAND   , {1,1,PINT,FF0         ,0,0,1,1,0,0,0,0,0,0,0,0}   ,NULL },
 559   {0xf400e800,"ff1         ",{21,5,REG}  ,{0,5,REG}    ,NO_OPERAND   , {1,1,PINT,FF1         ,0,0,1,1,0,0,0,0,0,0,0,0}   ,NULL },
 560   {0xf0008000,"clr         ",{21,5,REG}  ,{16,5,REG}   ,{0,10,BF} , {1,1,PINT,CLR    ,i10bit,1,0,1,0,0,0,0,0,0,0,0}   ,NULL },
 561   {0xf0008800,"set         ",{21,5,REG}  ,{16,5,REG}   ,{0,10,BF} , {1,1,PINT,SET    ,i10bit,1,0,1,0,0,0,0,0,0,0,0}   ,NULL },
 562   {0xf0009000,"ext         ",{21,5,REG}  ,{16,5,REG}   ,{0,10,BF} , {1,1,PINT,EXT    ,i10bit,1,0,1,0,0,0,0,0,0,0,0}   ,NULL },
 563   {0xf0009800,"extu        ",{21,5,REG}  ,{16,5,REG}   ,{0,10,BF} , {1,1,PINT,EXTU   ,i10bit,1,0,1,0,0,0,0,0,0,0,0}   ,NULL },
 564   {0xf000a000,"mak         ",{21,5,REG}  ,{16,5,REG}   ,{0,10,BF} , {1,1,PINT,MAK    ,i10bit,1,0,1,0,0,0,0,0,0,0,0}   ,NULL },
 565   {0xf000a800,"rot         ",{21,5,REG}  ,{16,5,REG}   ,{0,10,BF} , {1,1,PINT,ROT    ,i10bit,1,0,1,0,0,0,0,0,0,0,0}   ,NULL },
 566   {0xf4008000,"clr         ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {1,1,PINT,CLR         ,0,1,1,1,0,0,0,0,0,0,0,0}   ,NULL },
 567   {0xf4008800,"set         ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {1,1,PINT,SET         ,0,1,1,1,0,0,0,0,0,0,0,0}   ,NULL },
 568   {0xf4009000,"ext         ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {1,1,PINT,EXT         ,0,1,1,1,0,0,0,0,0,0,0,0}   ,NULL },
 569   {0xf4009800,"extu        ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {1,1,PINT,EXTU        ,0,1,1,1,0,0,0,0,0,0,0,0}   ,NULL },
 570   {0xf400a000,"mak         ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {1,1,PINT,MAK         ,0,1,1,1,0,0,0,0,0,0,0,0}   ,NULL },
 571   {0xf400a800,"rot         ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {1,1,PINT,ROT         ,0,1,1,1,0,0,0,0,0,0,0,0}   ,NULL },
 572
 573   {0x84002800,"fadd.sss    ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {5,1,PFLT,FADD        ,0,1,1,1,0,0,0,1,0,0,0,0}   ,NULL },
 574   {0x84002880,"fadd.ssd    ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {6,2,PFLT,FADD        ,0,1,1,1,0,0,0,1,0,0,1,0}   ,NULL },
 575   {0x84002a00,"fadd.sds    ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {6,2,PFLT,FADD        ,0,1,1,1,0,0,0,1,0,1,0,0}   ,NULL },
 576   {0x84002a80,"fadd.sdd    ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {6,2,PFLT,FADD        ,0,1,1,1,0,0,0,1,0,1,1,0}   ,NULL },
 577   {0x84002820,"fadd.dss    ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {6,2,PFLT,FADD        ,0,1,1,1,0,0,0,1,1,0,0,0}   ,NULL },
 578   {0x840028a0,"fadd.dsd    ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {6,2,PFLT,FADD        ,0,1,1,1,0,0,0,1,1,0,1,0}   ,NULL },
 579   {0x84002a20,"fadd.dds    ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {6,2,PFLT,FADD        ,0,1,1,1,0,0,0,1,1,1,0,0}   ,NULL },
 580   {0x84002aa0,"fadd.ddd    ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {6,2,PFLT,FADD        ,0,1,1,1,0,0,0,1,1,1,1,0}   ,NULL },
 581   {0x84003000,"fsub.sss    ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {5,1,PFLT,FSUB        ,0,1,1,1,0,0,0,1,0,0,0,0}   ,NULL },
 582   {0x84003080,"fsub.ssd    ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {6,2,PFLT,FSUB        ,0,1,1,1,0,0,0,1,0,0,1,0}   ,NULL },
 583   {0x84003200,"fsub.sds    ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {6,2,PFLT,FSUB        ,0,1,1,1,0,0,0,1,0,1,0,0}   ,NULL },
 584   {0x84003280,"fsub.sdd    ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {6,2,PFLT,FSUB        ,0,1,1,1,0,0,0,1,0,1,1,0}   ,NULL },
 585   {0x84003020,"fsub.dss    ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {6,2,PFLT,FSUB        ,0,1,1,1,0,0,0,1,1,0,0,0}   ,NULL },
 586   {0x840030a0,"fsub.dsd    ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {6,2,PFLT,FSUB        ,0,1,1,1,0,0,0,1,1,0,1,0}   ,NULL },
 587   {0x84003220,"fsub.dds    ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {6,2,PFLT,FSUB        ,0,1,1,1,0,0,0,1,1,1,0,0}   ,NULL },
 588   {0x840032a0,"fsub.ddd    ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {6,2,PFLT,FSUB        ,0,1,1,1,0,0,0,1,1,1,1,0}   ,NULL },
 589   {0x84000000,"fmul.sss    ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {6,1,PFLT,FMUL        ,0,1,1,1,0,0,0,1,0,0,0,0}   ,NULL },
 590   {0x84000080,"fmul.ssd    ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {9,2,PFLT,FMUL        ,0,1,1,1,0,0,0,1,0,0,1,0}   ,NULL },
 591   {0x84000200,"fmul.sds    ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {9,2,PFLT,FMUL        ,0,1,1,1,0,0,0,1,0,1,0,0}   ,NULL },
 592   {0x84000280,"fmul.sdd    ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {9,2,PFLT,FMUL        ,0,1,1,1,0,0,0,1,0,1,1,0}   ,NULL },
 593   {0x84000020,"fmul.dss    ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {9,2,PFLT,FMUL        ,0,1,1,1,0,0,0,1,1,0,0,0}   ,NULL },
 594   {0x840000a0,"fmul.dsd    ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {9,2,PFLT,FMUL        ,0,1,1,1,0,0,0,1,1,0,1,0}   ,NULL },
 595   {0x84000220,"fmul.dds    ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {9,2,PFLT,FMUL        ,0,1,1,1,0,0,0,1,1,1,0,0}   ,NULL },
 596   {0x840002a0,"fmul.ddd    ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {9,2,PFLT,FMUL        ,0,1,1,1,0,0,0,1,1,1,1,0}   ,NULL },
 597   {0x84007000,"fdiv.sss    ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {30,30,PFLT,FDIV      ,0,1,1,1,0,0,0,1,0,0,0,0}   ,NULL },
 598   {0x84007080,"fdiv.ssd    ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {60,60,PFLT,FDIV      ,0,1,1,1,0,0,0,1,0,0,1,0}   ,NULL },
 599   {0x84007200,"fdiv.sds    ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {60,60,PFLT,FDIV      ,0,1,1,1,0,0,0,1,0,1,0,0}   ,NULL },
 600   {0x84007280,"fdiv.sdd    ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {60,60,PFLT,FDIV      ,0,1,1,1,0,0,0,1,0,1,1,0}   ,NULL },
 601   {0x84007020,"fdiv.dss    ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {60,60,PFLT,FDIV      ,0,1,1,1,0,0,0,1,1,0,0,0}   ,NULL },
 602   {0x840070a0,"fdiv.dsd    ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {60,60,PFLT,FDIV      ,0,1,1,1,0,0,0,1,1,0,1,0}   ,NULL },
 603   {0x84007220,"fdiv.dds    ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {60,60,PFLT,FDIV      ,0,1,1,1,0,0,0,1,1,1,0,0}   ,NULL },
 604   {0x840072a0,"fdiv.ddd    ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {60,60,PFLT,FDIV      ,0,1,1,1,0,0,0,1,1,1,1,0}   ,NULL },
 605   {0x84007800,"fsqrt.ss    ",{21,5,REG}  ,{0,5,REG}    ,NO_OPERAND   , {5,1,PFLT,FLT         ,0,0,1,1,0,0,0,1,0,0,0,0}   ,NULL },
 606   {0x84007820,"fsqrt.sd    ",{21,5,REG}  ,{0,5,REG}    ,NO_OPERAND   , {5,1,PFLT,FLT         ,0,0,1,1,0,0,0,1,0,0,0,0}   ,NULL },
 607   {0x84007880,"fsqrt.ds    ",{21,5,REG}  ,{0,5,REG}    ,NO_OPERAND   , {5,1,PFLT,FLT         ,0,0,1,1,0,0,0,1,0,0,0,0}   ,NULL },
 608   {0x840078a0,"fsqrt.dd    ",{21,5,REG}  ,{0,5,REG}    ,NO_OPERAND   , {6,1,PFLT,FLT         ,0,0,1,1,0,0,0,1,1,0,0,0}   ,NULL },
 609   {0x84003800,"fcmp.ss     ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {5,1,PFLT,FCMP        ,0,1,1,1,0,0,0,1,0,0,0,0}   ,NULL },
 610   {0x84003880,"fcmp.sd     ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {6,1,PFLT,FCMP        ,0,1,1,1,0,0,0,1,0,1,0,0}   ,NULL },
 611   {0x84003a00,"fcmp.ds     ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {6,1,PFLT,FCMP        ,0,1,1,1,0,0,0,1,1,0,0,0}   ,NULL },
 612   {0x84003a80,"fcmp.dd     ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {6,1,PFLT,FCMP        ,0,1,1,1,0,0,0,1,1,1,0,0}   ,NULL },
 613   {0x84002000,"flt.s       ",{21,5,REG}  ,{0,5,REG}    ,NO_OPERAND   , {5,1,PFLT,FLT         ,0,0,1,1,0,0,0,1,0,0,0,0}   ,NULL },
 614   {0x84002020,"flt.d       ",{21,5,REG}  ,{0,5,REG}    ,NO_OPERAND   , {6,1,PFLT,FLT         ,0,0,1,1,0,0,0,1,1,0,0,0}   ,NULL },
 615   {0x84004800,"int.s       ",{21,5,REG}  ,{0,5,REG}    ,NO_OPERAND   , {5,1,PFLT,INT         ,0,0,1,1,0,0,0,1,0,0,0,0}   ,NULL },
 616   {0x84004880,"int.d       ",{21,5,REG}  ,{0,5,REG}    ,NO_OPERAND   , {6,1,PFLT,INT         ,0,0,1,1,0,0,0,1,1,0,0,0}   ,NULL },
 617   {0x84005000,"nint.s      ",{21,5,REG}  ,{0,5,REG}    ,NO_OPERAND   , {5,1,PFLT,INT         ,0,0,1,1,0,0,0,1,0,0,0,0}   ,NULL },
 618   {0x84005080,"nint.d      ",{21,5,REG}  ,{0,5,REG}    ,NO_OPERAND   , {6,1,PFLT,INT         ,0,0,1,1,0,0,0,1,1,0,0,0}   ,NULL },
 619   {0x84005800,"trnc.s      ",{21,5,REG}  ,{0,5,REG}    ,NO_OPERAND   , {5,1,PFLT,TRNC        ,0,0,1,1,0,0,0,1,0,0,0,0}   ,NULL },
 620   {0x84005880,"trnc.d      ",{21,5,REG}  ,{0,5,REG}    ,NO_OPERAND   , {6,1,PFLT,TRNC        ,0,0,1,1,0,0,0,1,1,0,0,0}   ,NULL },
 621
 622   {0x80004800,"fldcr       ",{21,5,REG}  ,{5,6,FCRREG} ,NO_OPERAND   , {1,1,PFLT,FLDC        ,0,0,1,1,0,0,0,1,0,0,0,0}   ,NULL },
 623   {0x80008800,"fstcr       ",{16,5,REG}  ,{5,6,FCRREG} ,NO_OPERAND   , {1,1,PFLT,FSTC        ,0,0,1,1,0,0,0,1,0,0,0,0}   ,NULL },
 624   {0x8000c800,"fxcr        ",{21,5,REG}  ,{16,5,REG}   ,{5,6,FCRREG} , {1,1,PFLT,FXC         ,0,0,1,1,0,0,0,1,0,0,0,0}   ,NULL },
 625
 626 /* The following are new for the 88110. */
 627
 628   {0x8400aaa0,"fadd.ddd    ",{21,5,XREG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 629   {0x8400aa80,"fadd.dds    ",{21,5,XREG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 630   {0x8400aac0,"fadd.ddx    ",{21,5,XREG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 631   {0x8400aa20,"fadd.dsd    ",{21,5,XREG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 632   {0x8400aa00,"fadd.dss    ",{21,5,XREG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 633   {0x8400aa40,"fadd.dsx    ",{21,5,XREG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 634   {0x8400ab20,"fadd.dxd    ",{21,5,XREG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 635   {0x8400ab00,"fadd.dxs    ",{21,5,XREG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 636   {0x8400ab40,"fadd.dxx    ",{21,5,XREG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 637   {0x8400a8a0,"fadd.sdd    ",{21,5,XREG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 638   {0x8400a880,"fadd.sds    ",{21,5,XREG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 639   {0x8400a8c0,"fadd.sdx    ",{21,5,XREG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 640   {0x8400a820,"fadd.ssd    ",{21,5,XREG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 641   {0x8400a800,"fadd.sss    ",{21,5,XREG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 642   {0x8400a840,"fadd.ssx    ",{21,5,XREG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 643   {0x8400a920,"fadd.sxd    ",{21,5,XREG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 644   {0x8400a900,"fadd.sxs    ",{21,5,XREG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 645   {0x8400a940,"fadd.sxx    ",{21,5,XREG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 646   {0x8400aca0,"fadd.xdd    ",{21,5,XREG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 647   {0x8400ac80,"fadd.xds    ",{21,5,XREG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 648   {0x8400acc0,"fadd.xdx    ",{21,5,XREG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 649   {0x8400ac20,"fadd.xsd    ",{21,5,XREG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 650   {0x8400ac00,"fadd.xss    ",{21,5,XREG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 651   {0x8400ac40,"fadd.xsx    ",{21,5,XREG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 652   {0x8400ad20,"fadd.xxd    ",{21,5,XREG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 653   {0x8400ad00,"fadd.xxs    ",{21,5,XREG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 654   {0x8400ad40,"fadd.xxx    ",{21,5,XREG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 655
 656   {0x8400ba80,"fcmp.sdd    ",{21,5,REG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 657   {0x8400ba00,"fcmp.sds    ",{21,5,REG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 658   {0x8400bb00,"fcmp.sdx    ",{21,5,REG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 659   {0x8400b880,"fcmp.ssd    ",{21,5,REG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 660   {0x8400b800,"fcmp.sss    ",{21,5,REG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 661   {0x8400b900,"fcmp.ssx    ",{21,5,REG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 662   {0x8400bc80,"fcmp.sxd    ",{21,5,REG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 663   {0x8400bc00,"fcmp.sxs    ",{21,5,REG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 664   {0x8400bd00,"fcmp.sxx    ",{21,5,REG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 665
 666   {0x8400baa0,"fcmpu.sdd   ",{21,5,REG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 667   {0x8400ba20,"fcmpu.sds   ",{21,5,REG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 668   {0x8400bb20,"fcmpu.sdx   ",{21,5,REG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 669   {0x8400b8a0,"fcmpu.ssd   ",{21,5,REG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 670   {0x8400b820,"fcmpu.sss   ",{21,5,REG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 671   {0x8400b920,"fcmpu.ssx   ",{21,5,REG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 672   {0x8400bca0,"fcmpu.sxd   ",{21,5,REG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 673   {0x8400bc20,"fcmpu.sxs   ",{21,5,REG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 674   {0x8400bd20,"fcmpu.sxx   ",{21,5,REG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 675
 676   {0x84000820,"fcvt.sd     ",{21,5,REG} ,{0,5,REG}  ,NO_OPERAND, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 677   {0x84000880,"fcvt.ds     ",{21,5,REG} ,{0,5,REG}  ,NO_OPERAND, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 678
 679   {0x84008880,"fcvt.ds     ",{21,5,XREG} ,{0,5,XREG}  ,NO_OPERAND, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 680   {0x840088c0,"fcvt.dx     ",{21,5,XREG} ,{0,5,XREG}  ,NO_OPERAND, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 681   {0x84008820,"fcvt.sd     ",{21,5,XREG} ,{0,5,XREG}  ,NO_OPERAND, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 682   {0x84008840,"fcvt.sx     ",{21,5,XREG} ,{0,5,XREG}  ,NO_OPERAND, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 683   {0x84008920,"fcvt.xd     ",{21,5,XREG} ,{0,5,XREG}  ,NO_OPERAND, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 684   {0x84008900,"fcvt.xs     ",{21,5,XREG} ,{0,5,XREG}  ,NO_OPERAND, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 685
 686   {0x8400f2a0,"fdiv.ddd    ",{21,5,XREG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 687   {0x8400f280,"fdiv.dds    ",{21,5,XREG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 688   {0x8400f2c0,"fdiv.ddx    ",{21,5,XREG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 689   {0x8400f220,"fdiv.dsd    ",{21,5,XREG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 690   {0x8400f200,"fdiv.dss    ",{21,5,XREG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 691   {0x8400f240,"fdiv.dsx    ",{21,5,XREG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 692   {0x8400f320,"fdiv.dxd    ",{21,5,XREG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 693   {0x8400f300,"fdiv.dxs    ",{21,5,XREG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 694   {0x8400f340,"fdiv.dxx    ",{21,5,XREG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 695   {0x8400f0a0,"fdiv.sdd    ",{21,5,XREG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 696   {0x8400f080,"fdiv.sds    ",{21,5,XREG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 697   {0x8400f0c0,"fdiv.sdx    ",{21,5,XREG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 698   {0x8400f020,"fdiv.ssd    ",{21,5,XREG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 699   {0x8400f000,"fdiv.sss    ",{21,5,XREG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 700   {0x8400f040,"fdiv.ssx    ",{21,5,XREG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 701   {0x8400f120,"fdiv.sxd    ",{21,5,XREG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 702   {0x8400f100,"fdiv.sxs    ",{21,5,XREG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 703   {0x8400f140,"fdiv.sxx    ",{21,5,XREG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 704   {0x8400f4a0,"fdiv.xdd    ",{21,5,XREG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 705   {0x8400f480,"fdiv.xds    ",{21,5,XREG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 706   {0x8400f4c0,"fdiv.xdx    ",{21,5,XREG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 707   {0x8400f420,"fdiv.xsd    ",{21,5,XREG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 708   {0x8400f400,"fdiv.xss    ",{21,5,XREG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 709   {0x8400f440,"fdiv.xsx    ",{21,5,XREG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 710   {0x8400f520,"fdiv.xxd    ",{21,5,XREG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 711   {0x8400f500,"fdiv.xxs    ",{21,5,XREG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 712   {0x8400f540,"fdiv.xxx    ",{21,5,XREG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 713
 714   {0x84002220,"flt.ds      ",{21,5,XREG} ,{0,5,REG}  ,NO_OPERAND, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 715   {0x84002200,"flt.ss      ",{21,5,XREG} ,{0,5,REG}  ,NO_OPERAND, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 716   {0x84002240,"flt.xs      ",{21,5,XREG} ,{0,5,REG}  ,NO_OPERAND, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 717
 718   {0x840082a0,"fmul.ddd    ",{21,5,XREG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 719   {0x84008280,"fmul.dds    ",{21,5,XREG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 720   {0x840082c0,"fmul.ddx    ",{21,5,XREG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 721   {0x84008220,"fmul.dsd    ",{21,5,XREG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 722   {0x84008200,"fmul.dss    ",{21,5,XREG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 723   {0x84008240,"fmul.dsx    ",{21,5,XREG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 724   {0x84008320,"fmul.dxd    ",{21,5,XREG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 725   {0x84008300,"fmul.dxs    ",{21,5,XREG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 726   {0x84008340,"fmul.dxx    ",{21,5,XREG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 727   {0x840080a0,"fmul.sdd    ",{21,5,XREG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 728   {0x84008080,"fmul.sds    ",{21,5,XREG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 729   {0x840080c0,"fmul.sdx    ",{21,5,XREG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 730   {0x84008020,"fmul.ssd    ",{21,5,XREG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 731   {0x84008000,"fmul.sss    ",{21,5,XREG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 732   {0x84008040,"fmul.ssx    ",{21,5,XREG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 733   {0x84008120,"fmul.sxd    ",{21,5,XREG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 734   {0x84008100,"fmul.sxs    ",{21,5,XREG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 735   {0x84008140,"fmul.sxx    ",{21,5,XREG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 736   {0x840084a0,"fmul.xdd    ",{21,5,XREG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 737   {0x84008480,"fmul.xds    ",{21,5,XREG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 738   {0x840084c0,"fmul.xdx    ",{21,5,XREG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 739   {0x84008420,"fmul.xsd    ",{21,5,XREG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 740   {0x84008400,"fmul.xss    ",{21,5,XREG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 741   {0x84008440,"fmul.xsx    ",{21,5,XREG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 742   {0x84008520,"fmul.xxd    ",{21,5,XREG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 743   {0x84008500,"fmul.xxs    ",{21,5,XREG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 744   {0x84008540,"fmul.xxx    ",{21,5,XREG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 745
 746   {0x8400f8a0,"fsqrt.dd    ",{21,5,XREG}, {0,5,XREG}, NO_OPERAND, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 747   {0x8400f880,"fsqrt.ds    ",{21,5,XREG}, {0,5,XREG}, NO_OPERAND, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 748   {0x8400f8c0,"fsqrt.dx    ",{21,5,XREG}, {0,5,XREG}, NO_OPERAND, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 749   {0x8400f820,"fsqrt.sd    ",{21,5,XREG}, {0,5,XREG}, NO_OPERAND, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 750   {0x8400f800,"fsqrt.ss    ",{21,5,XREG}, {0,5,XREG}, NO_OPERAND, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 751   {0x8400f840,"fsqrt.sx    ",{21,5,XREG}, {0,5,XREG}, NO_OPERAND, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 752   {0x8400f920,"fsqrt.xd    ",{21,5,XREG}, {0,5,XREG}, NO_OPERAND, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 753   {0x8400f900,"fsqrt.xs    ",{21,5,XREG}, {0,5,XREG}, NO_OPERAND, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 754   {0x8400f940,"fsqrt.xx    ",{21,5,XREG}, {0,5,XREG}, NO_OPERAND, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 755
 756   {0x8400b2a0,"fsub.ddd    ",{21,5,XREG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 757   {0x8400b280,"fsub.dds    ",{21,5,XREG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 758   {0x8400b2c0,"fsub.ddx    ",{21,5,XREG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 759   {0x8400b220,"fsub.dsd    ",{21,5,XREG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 760   {0x8400b200,"fsub.dss    ",{21,5,XREG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 761   {0x8400b240,"fsub.dsx    ",{21,5,XREG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 762   {0x8400b320,"fsub.dxd    ",{21,5,XREG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 763   {0x8400b300,"fsub.dxs    ",{21,5,XREG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 764   {0x8400b340,"fsub.dxx    ",{21,5,XREG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 765   {0x8400b0a0,"fsub.sdd    ",{21,5,XREG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 766   {0x8400b080,"fsub.sds    ",{21,5,XREG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 767   {0x8400b0c0,"fsub.sdx    ",{21,5,XREG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 768   {0x8400b020,"fsub.ssd    ",{21,5,XREG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 769   {0x8400b000,"fsub.sss    ",{21,5,XREG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 770   {0x8400b040,"fsub.ssx    ",{21,5,XREG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 771   {0x8400b120,"fsub.sxd    ",{21,5,XREG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 772   {0x8400b100,"fsub.sxs    ",{21,5,XREG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 773   {0x8400b140,"fsub.sxx    ",{21,5,XREG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 774   {0x8400b4a0,"fsub.xdd    ",{21,5,XREG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 775   {0x8400b480,"fsub.xds    ",{21,5,XREG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 776   {0x8400b4c0,"fsub.xdx    ",{21,5,XREG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 777   {0x8400b420,"fsub.xsd    ",{21,5,XREG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 778   {0x8400b400,"fsub.xss    ",{21,5,XREG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 779   {0x8400b440,"fsub.xsx    ",{21,5,XREG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 780   {0x8400b520,"fsub.xxd    ",{21,5,XREG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 781   {0x8400b500,"fsub.xxs    ",{21,5,XREG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 782   {0x8400b540,"fsub.xxx    ",{21,5,XREG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 783
 784   {0x8400fc00,"illop", {0,2,DEC}, NO_OPERAND, NO_OPERAND, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 785
 786   {0x8400c800,"int.ss      ", {21,5,REG}, {0,5,XREG}, NO_OPERAND, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 787   {0x8400c880,"int.sd      ", {21,5,REG}, {0,5,XREG}, NO_OPERAND, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 788   {0x8400c900,"int.sx      ", {21,5,REG}, {0,5,XREG}, NO_OPERAND, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 789
 790   {0x04000000,"ld          ", {21,5,XREG}, {16,5,REG}, {0,16,HEX}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 791   {0x00000000,"ld.d        ", {21,5,XREG}, {16,5,REG}, {0,16,HEX}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 792   {0x3c000000,"ld.x        ", {21,5,XREG}, {16,5,REG}, {0,16,HEX}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 793
 794   {0xf0001400,"ld          ", {21,5,XREG}, {16,5,REG}, {0,5,REG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 795   {0xf0001000,"ld.d        ", {21,5,XREG}, {16,5,REG}, {0,5,REG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 796   {0xf0001800,"ld.x        ", {21,5,XREG}, {16,5,REG}, {0,5,REG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 797   {0xf0001500,"ld.usr      ", {21,5,XREG}, {16,5,REG}, {0,5,REG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 798   {0xf0001100,"ld.d.usr    ", {21,5,XREG}, {16,5,REG}, {0,5,REG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 799   {0xf0001900,"ld.x.usr    ", {21,5,XREG}, {16,5,REG}, {0,5,REG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 800
 801   {0xf0001600,"ld          ", {21,5,XREG}, {16,5,REG}, {0,5,REGSC}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 802   {0xf0001200,"ld.d        ", {21,5,XREG}, {16,5,REG}, {0,5,REGSC}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 803   {0xf0001a00,"ld.x        ", {21,5,XREG}, {16,5,REG}, {0,5,REGSC}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 804   {0xf0001700,"ld.usr      ", {21,5,XREG}, {16,5,REG}, {0,5,REGSC}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 805   {0xf0001300,"ld.d.usr    ", {21,5,XREG}, {16,5,REG}, {0,5,REGSC}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 806   {0xf0001b00,"ld.x.usr    ", {21,5,XREG}, {16,5,REG}, {0,5,REGSC}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 807
 808   {0x8400c000,"mov.s       ", {21,5,REG}, {0,5,XREG}, NO_OPERAND, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 809   {0x8400c080,"mov.d       ", {21,5,REG}, {0,5,XREG}, NO_OPERAND, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 810   {0x84004200,"mov.s       ", {21,5,XREG}, {0,5,REG}, NO_OPERAND, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 811   {0x84004280,"mov.d       ", {21,5,XREG}, {0,5,REG}, NO_OPERAND, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 812   {0x8400c300,"mov         ", {21,5,XREG}, {0,5,XREG}, NO_OPERAND, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 813
 814   {0xf4006d00,"mulu.d      ", {21,5,REG}, {16,5,REG}, {0,5,REG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 815
 816   {0x8400d080,"nint.sd     ", {21,5,REG}, {0,5,XREG}, NO_OPERAND, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 817   {0x8400d000,"nint.ss     ", {21,5,REG}, {0,5,XREG}, NO_OPERAND, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 818   {0x8400d100,"nint.sx     ", {21,5,REG}, {0,5,XREG}, NO_OPERAND, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 819
 820   {0x88002020,"padd.b      ", {21,5,REG}, {16,5,REG}, {0,5,REG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 821   {0x88002040,"padd.h      ", {21,5,REG}, {16,5,REG}, {0,5,REG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 822   {0x88002060,"padd        ", {21,5,REG}, {16,5,REG}, {0,5,REG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 823
 824   {0x880021e0,"padds.s     ", {21,5,REG}, {16,5,REG}, {0,5,REG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 825   {0x880021a0,"padds.s.b   ", {21,5,REG}, {16,5,REG}, {0,5,REG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 826   {0x880021c0,"padds.s.h   ", {21,5,REG}, {16,5,REG}, {0,5,REG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 827   {0x880020e0,"padds.u     ", {21,5,REG}, {16,5,REG}, {0,5,REG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 828   {0x880020a0,"padds.u.b   ", {21,5,REG}, {16,5,REG}, {0,5,REG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 829   {0x880020c0,"padds.u.h   ", {21,5,REG}, {16,5,REG}, {0,5,REG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 830   {0x88002160,"padds.us    ", {21,5,REG}, {16,5,REG}, {0,5,REG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 831   {0x88002120,"padds.us.b  ", {21,5,REG}, {16,5,REG}, {0,5,REG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 832   {0x88002140,"padds.us.h  ", {21,5,REG}, {16,5,REG}, {0,5,REG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 833
 834   {0x88003860,"pcmp        ", {21,5,REG}, {16,5,REG}, {0,5,REG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 835
 836   {0x88000000,"pmul        ", {21,5,REG}, {16,5,REG}, {0,5,REG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 837
 838   {0x88006260,"ppack.16    ", {21,5,REG}, {16,5,REG}, {0,5,REG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 839   {0x88006240,"ppack.16.h  ", {21,5,REG}, {16,5,REG}, {0,5,REG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 840   {0x88006460,"ppack.32    ", {21,5,REG}, {16,5,REG}, {0,5,REG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 841   {0x88006420,"ppack.32.b  ", {21,5,REG}, {16,5,REG}, {0,5,REG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 842   {0x88006440,"ppack.32.h  ", {21,5,REG}, {16,5,REG}, {0,5,REG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 843   {0x88006160,"ppack.8     ", {21,5,REG}, {16,5,REG}, {0,5,REG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 844
 845   {0x88007200,"prot        ", {21,5,REG}, {16,5,REG}, {5,6,HEX}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 846   {0x88007800,"prot        ", {21,5,REG}, {16,5,REG}, {0,5,REG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 847
 848   {0x88003020,"psub.b      ", {21,5,REG}, {16,5,REG}, {0,5,REG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 849   {0x88003040,"psub.h      ", {21,5,REG}, {16,5,REG}, {0,5,REG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 850   {0x88003060,"psub        ", {21,5,REG}, {16,5,REG}, {0,5,REG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 851
 852   {0x880031e0,"psubs.s     ", {21,5,REG}, {16,5,REG}, {0,5,REG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 853   {0x880031a0,"psubs.s.b   ", {21,5,REG}, {16,5,REG}, {0,5,REG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 854   {0x880031c0,"psubs.s.h   ", {21,5,REG}, {16,5,REG}, {0,5,REG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 855   {0x880030e0,"psubs.u     ", {21,5,REG}, {16,5,REG}, {0,5,REG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 856   {0x880030a0,"psubs.u.b   ", {21,5,REG}, {16,5,REG}, {0,5,REG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 857   {0x880030c0,"psubs.u.h   ", {21,5,REG}, {16,5,REG}, {0,5,REG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 858   {0x88003160,"psubs.us    ", {21,5,REG}, {16,5,REG}, {0,5,REG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 859   {0x88003120,"psubs.us.b  ", {21,5,REG}, {16,5,REG}, {0,5,REG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 860   {0x88003140,"psubs.us.h  ", {21,5,REG}, {16,5,REG}, {0,5,REG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 861
 862   {0x88006800,"punpk.n     ", {21,5,REG}, {16,5,REG}, NO_OPERAND, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 863   {0x88006820,"punpk.b     ", {21,5,REG}, {16,5,REG}, NO_OPERAND, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 864
 865   {0x34000000,"st          ", {21,5,XREG}, {16,5,REG}, {0,16,HEX}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 866   {0x30000000,"st.d        ", {21,5,XREG}, {16,5,REG}, {0,16,HEX}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 867   {0x38000000,"st.x        ", {21,5,XREG}, {16,5,REG}, {0,16,HEX}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 868
 869   {0xf4002c80,"st.b.wt     ", {21,5,REG}, {16,5,REG}, {0,5,REG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 870   {0xf4002880,"st.h.wt     ", {21,5,REG}, {16,5,REG}, {0,5,REG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 871   {0xf4002480,"st.wt       ", {21,5,REG}, {16,5,REG}, {0,5,REG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 872   {0xf4002080,"st.d.wt     ", {21,5,REG}, {16,5,REG}, {0,5,REG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 873   {0xf4002d80,"st.b.usr.wt ", {21,5,REG}, {16,5,REG}, {0,5,REG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 874   {0xf4002980,"st.h.usr.wt ", {21,5,REG}, {16,5,REG}, {0,5,REG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 875   {0xf4002580,"st.usr.wt   ", {21,5,REG}, {16,5,REG}, {0,5,REG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 876   {0xf4002180,"st.d.usr.wt ", {21,5,REG}, {16,5,REG}, {0,5,REG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 877
 878   {0xf0002400,"st          ", {21,5,XREG}, {16,5,REG}, {0,5,REG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 879   {0xf0002000,"st.d        ", {21,5,XREG}, {16,5,REG}, {0,5,REG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 880   {0xf0002100,"st.d.usr    ", {21,5,XREG}, {16,5,REG}, {0,5,REG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 881   {0xf0002180,"st.d.usr.wt ", {21,5,XREG}, {16,5,REG}, {0,5,REG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 882   {0xf0002080,"st.d.wt     ", {21,5,XREG}, {16,5,REG}, {0,5,REG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 883   {0xf0002500,"st.usr      ", {21,5,XREG}, {16,5,REG}, {0,5,REG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 884   {0xf0002580,"st.usr.wt   ", {21,5,XREG}, {16,5,REG}, {0,5,REG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 885   {0xf0002480,"st.wt       ", {21,5,XREG}, {16,5,REG}, {0,5,REG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 886   {0xf0002800,"st.x        ", {21,5,XREG}, {16,5,REG}, {0,5,REG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 887   {0xf0002900,"st.x.usr    ", {21,5,XREG}, {16,5,REG}, {0,5,REG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 888   {0xf0002980,"st.x.usr.wt ", {21,5,XREG}, {16,5,REG}, {0,5,REG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 889   {0xf0002880,"st.x.wt     ", {21,5,XREG}, {16,5,REG}, {0,5,REG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 890
 891   {0xf4002f80,"st.b.usr.wt ", {21,5,REG}, {16,5,REG}, {0,5,REGSC}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 892   {0xf4002e80,"st.b.wt     ", {21,5,REG}, {16,5,REG}, {0,5,REGSC}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 893   {0xf4002380,"st.d.usr.wt ", {21,5,REG}, {16,5,REG}, {0,5,REGSC}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 894   {0xf4002280,"st.d.wt     ", {21,5,REG}, {16,5,REG}, {0,5,REGSC}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 895   {0xf4002b80,"st.h.usr.wt ", {21,5,REG}, {16,5,REG}, {0,5,REGSC}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 896   {0xf4002a80,"st.h.wt     ", {21,5,REG}, {16,5,REG}, {0,5,REGSC}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 897   {0xf4002780,"st.usr.wt   ", {21,5,REG}, {16,5,REG}, {0,5,REGSC}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 898   {0xf4002680,"st.wt       ", {21,5,REG}, {16,5,REG}, {0,5,REGSC}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 899
 900   {0xf0002600,"st          ", {21,5,XREG}, {16,5,REG}, {0,5,REGSC}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 901   {0xf0002200,"st.d        ", {21,5,XREG}, {16,5,REG}, {0,5,REGSC}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 902   {0xf0002300,"st.d.usr    ", {21,5,XREG}, {16,5,REG}, {0,5,REGSC}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 903   {0xf0002380,"st.d.usr.wt ", {21,5,XREG}, {16,5,REG}, {0,5,REGSC}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 904   {0xf0002280,"st.d.wt     ", {21,5,XREG}, {16,5,REG}, {0,5,REGSC}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 905   {0xf0002700,"st.usr      ", {21,5,XREG}, {16,5,REG}, {0,5,REGSC}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 906   {0xf0002780,"st.usr.wt   ", {21,5,XREG}, {16,5,REG}, {0,5,REGSC}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 907   {0xf0002680,"st.wt       ", {21,5,XREG}, {16,5,REG}, {0,5,REGSC}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 908   {0xf0002a00,"st.x        ", {21,5,XREG}, {16,5,REG}, {0,5,REGSC}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 909   {0xf0002b00,"st.x.usr    ", {21,5,XREG}, {16,5,REG}, {0,5,REGSC}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 910   {0xf0002b80,"st.x.usr.wt ", {21,5,XREG}, {16,5,REG}, {0,5,REGSC}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 911   {0xf0002a80,"st.x.wt     ", {21,5,XREG}, {16,5,REG}, {0,5,REGSC}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 912
 913   {0x8400d880,"trnc.sd     ", {21,5,REG}, {0,5,XREG}, NO_OPERAND, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 914   {0x8400d800,"trnc.ss     ", {21,5,REG}, {0,5,XREG}, NO_OPERAND, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 915   {0x8400d900,"trnc.sx     ", {21,5,REG}, {0,5,XREG}, NO_OPERAND, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
 916
 917 };
 918
 919 /*
 920  * Local Variables:
 921  * fill-column: 131
 922  * End:
 923  */