include/opcode/ppc.h

   1 /* ppc.h -- Header file for PowerPC opcode table
   2    Copyright 1994, 1995 Free Software Foundation, Inc.
   3    Written by Ian Lance Taylor, Cygnus Support
   4
   5 This file is part of GDB, GAS, and the GNU binutils.
   6
   7 GDB, GAS, and the GNU binutils are free software; you can redistribute
   8 them and/or modify them under the terms of the GNU General Public
   9 License as published by the Free Software Foundation; either version
  10 1, or (at your option) any later version.
  11
  12 GDB, GAS, and the GNU binutils are distributed in the hope that they
  13 will be useful, but WITHOUT ANY WARRANTY; without even the implied
  14 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
  15 the GNU General Public License for more details.
  16
  17 You should have received a copy of the GNU General Public License
  18 along with this file; see the file COPYING.  If not, write to the Free
  19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
  20
  21 #ifndef PPC_H
  22 #define PPC_H
  23
  24 /* The opcode table is an array of struct powerpc_opcode.  */
  25
  26 struct powerpc_opcode
  27 {
  28   /* The opcode name.  */
  29   const char *name;
  30
  31   /* The opcode itself.  Those bits which will be filled in with
  32      operands are zeroes.  */
  33   unsigned long opcode;
  34
  35   /* The opcode mask.  This is used by the disassembler.  This is a
  36      mask containing ones indicating those bits which must match the
  37      opcode field, and zeroes indicating those bits which need not
  38      match (and are presumably filled in by operands).  */
  39   unsigned long mask;
  40
  41   /* One bit flags for the opcode.  These are used to indicate which
  42      specific processors support the instructions.  The defined values
  43      are listed below.  */
  44   unsigned long flags;
  45
  46   /* An array of operand codes.  Each code is an index into the
  47      operand table.  They appear in the order which the operands must
  48      appear in assembly code, and are terminated by a zero.  */
  49   unsigned char operands[8];
  50 };
  51
  52 /* The table itself is sorted by major opcode number, and is otherwise
  53    in the order in which the disassembler should consider
  54    instructions.  */
  55 extern const struct powerpc_opcode powerpc_opcodes[];
  56 extern const int powerpc_num_opcodes;
  57
  58 /* Values defined for the flags field of a struct powerpc_opcode.  */
  59
  60 /* Opcode is defined for the PowerPC architecture.  */
  61 #define PPC_OPCODE_PPC (01)
  62
  63 /* Opcode is defined for the POWER (RS/6000) architecture.  */
  64 #define PPC_OPCODE_POWER (02)
  65
  66 /* Opcode is defined for the POWER2 (Rios 2) architecture.  */
  67 #define PPC_OPCODE_POWER2 (04)
  68
  69 /* Opcode is only defined on 32 bit architectures.  */
  70 #define PPC_OPCODE_32 (010)
  71
  72 /* Opcode is only defined on 64 bit architectures.  */
  73 #define PPC_OPCODE_64 (020)
  74
  75 /* Opcode is supported by the Motorola PowerPC 601 processor.  The 601
  76    is assumed to support all PowerPC (PPC_OPCODE_PPC) instructions,
  77    but it also supports many additional POWER instructions.  */
  78 #define PPC_OPCODE_601 (040)
  79
  80 /* Opcode is supported in both the Power and PowerPC architectures
  81    (ie, compiler's -mcpu=common or assembler's -mcom).  */
  82 #define PPC_OPCODE_COMMON (0100)
  83
  84 /* Opcode is supported for any Power or PowerPC platform (this is
  85    for the assembler's -many option, and it eliminates duplicates).  */
  86 #define PPC_OPCODE_ANY (0200)
  87
  88 /* Opcode is supported as part of the 64-bit bridge.  */
  89 #define PPC_OPCODE_64_BRIDGE (0400)
  90
  91 /* Opcode is supported by Altivec Vector Unit */
  92 #define PPC_OPCODE_ALTIVEC   (01000)
  93
  94 /* A macro to extract the major opcode from an instruction.  */
  95 #define PPC_OP(i) (((i) >> 26) & 0x3f)
  96 \f
  97 /* The operands table is an array of struct powerpc_operand.  */
  98
  99 struct powerpc_operand
 100 {
 101   /* The number of bits in the operand.  */
 102   int bits;
 103
 104   /* How far the operand is left shifted in the instruction.  */
 105   int shift;
 106
 107   /* Insertion function.  This is used by the assembler.  To insert an
 108      operand value into an instruction, check this field.
 109
 110      If it is NULL, execute
 111          i |= (op & ((1 << o->bits) - 1)) << o->shift;
 112      (i is the instruction which we are filling in, o is a pointer to
 113      this structure, and op is the opcode value; this assumes twos
 114      complement arithmetic).
 115
 116      If this field is not NULL, then simply call it with the
 117      instruction and the operand value.  It will return the new value
 118      of the instruction.  If the ERRMSG argument is not NULL, then if
 119      the operand value is illegal, *ERRMSG will be set to a warning
 120      string (the operand will be inserted in any case).  If the
 121      operand value is legal, *ERRMSG will be unchanged (most operands
 122      can accept any value).  */
 123   unsigned long (*insert) PARAMS ((unsigned long instruction, long op,
 124                                    const char **errmsg));
 125
 126   /* Extraction function.  This is used by the disassembler.  To
 127      extract this operand type from an instruction, check this field.
 128
 129      If it is NULL, compute
 130          op = ((i) >> o->shift) & ((1 << o->bits) - 1);
 131          if ((o->flags & PPC_OPERAND_SIGNED) != 0
 132              && (op & (1 << (o->bits - 1))) != 0)
 133            op -= 1 << o->bits;
 134      (i is the instruction, o is a pointer to this structure, and op
 135      is the result; this assumes twos complement arithmetic).
 136
 137      If this field is not NULL, then simply call it with the
 138      instruction value.  It will return the value of the operand.  If
 139      the INVALID argument is not NULL, *INVALID will be set to
 140      non-zero if this operand type can not actually be extracted from
 141      this operand (i.e., the instruction does not match).  If the
 142      operand is valid, *INVALID will not be changed.  */
 143   long (*extract) PARAMS ((unsigned long instruction, int *invalid));
 144
 145   /* One bit syntax flags.  */
 146   unsigned long flags;
 147 };
 148
 149 /* Elements in the table are retrieved by indexing with values from
 150    the operands field of the powerpc_opcodes table.  */
 151
 152 extern const struct powerpc_operand powerpc_operands[];
 153
 154 /* Values defined for the flags field of a struct powerpc_operand.  */
 155
 156 /* This operand takes signed values.  */
 157 #define PPC_OPERAND_SIGNED (01)
 158
 159 /* This operand takes signed values, but also accepts a full positive
 160    range of values when running in 32 bit mode.  That is, if bits is
 161    16, it takes any value from -0x8000 to 0xffff.  In 64 bit mode,
 162    this flag is ignored.  */
 163 #define PPC_OPERAND_SIGNOPT (02)
 164
 165 /* This operand does not actually exist in the assembler input.  This
 166    is used to support extended mnemonics such as mr, for which two
 167    operands fields are identical.  The assembler should call the
 168    insert function with any op value.  The disassembler should call
 169    the extract function, ignore the return value, and check the value
 170    placed in the valid argument.  */
 171 #define PPC_OPERAND_FAKE (04)
 172
 173 /* The next operand should be wrapped in parentheses rather than
 174    separated from this one by a comma.  This is used for the load and
 175    store instructions which want their operands to look like
 176        reg,displacement(reg)
 177    */
 178 #define PPC_OPERAND_PARENS (010)
 179
 180 /* This operand may use the symbolic names for the CR fields, which
 181    are
 182        lt  0    gt  1   eq  2   so  3   un  3
 183        cr0 0    cr1 1   cr2 2   cr3 3
 184        cr4 4    cr5 5   cr6 6   cr7 7
 185    These may be combined arithmetically, as in cr2*4+gt.  These are
 186    only supported on the PowerPC, not the POWER.  */
 187 #define PPC_OPERAND_CR (020)
 188
 189 /* This operand names a register.  The disassembler uses this to print
 190    register names with a leading 'r'.  */
 191 #define PPC_OPERAND_GPR (040)
 192
 193 /* This operand names a floating point register.  The disassembler
 194    prints these with a leading 'f'.  */
 195 #define PPC_OPERAND_FPR (0100)
 196
 197 /* This operand is a relative branch displacement.  The disassembler
 198    prints these symbolically if possible.  */
 199 #define PPC_OPERAND_RELATIVE (0200)
 200
 201 /* This operand is an absolute branch address.  The disassembler
 202    prints these symbolically if possible.  */
 203 #define PPC_OPERAND_ABSOLUTE (0400)
 204
 205 /* This operand is optional, and is zero if omitted.  This is used for
 206    the optional BF and L fields in the comparison instructions.  The
 207    assembler must count the number of operands remaining on the line,
 208    and the number of operands remaining for the opcode, and decide
 209    whether this operand is present or not.  The disassembler should
 210    print this operand out only if it is not zero.  */
 211 #define PPC_OPERAND_OPTIONAL (01000)
 212
 213 /* This flag is only used with PPC_OPERAND_OPTIONAL.  If this operand
 214    is omitted, then for the next operand use this operand value plus
 215    1, ignoring the next operand field for the opcode.  This wretched
 216    hack is needed because the Power rotate instructions can take
 217    either 4 or 5 operands.  The disassembler should print this operand
 218    out regardless of the PPC_OPERAND_OPTIONAL field.  */
 219 #define PPC_OPERAND_NEXT (02000)
 220
 221 /* This operand should be regarded as a negative number for the
 222    purposes of overflow checking (i.e., the normal most negative
 223    number is disallowed and one more than the normal most positive
 224    number is allowed).  This flag will only be set for a signed
 225    operand.  */
 226 #define PPC_OPERAND_NEGATIVE (04000)
 227
 228 /* This operand names a vector unit register.  The disassembler
 229    prints these with a leading 'v'.  */
 230 #define PPC_OPERAND_VR (010000)
 231
 232 \f
 233 /* The POWER and PowerPC assemblers use a few macros.  We keep them
 234    with the operands table for simplicity.  The macro table is an
 235    array of struct powerpc_macro.  */
 236
 237 struct powerpc_macro
 238 {
 239   /* The macro name.  */
 240   const char *name;
 241
 242   /* The number of operands the macro takes.  */
 243   unsigned int operands;
 244
 245   /* One bit flags for the opcode.  These are used to indicate which
 246      specific processors support the instructions.  The values are the
 247      same as those for the struct powerpc_opcode flags field.  */
 248   unsigned long flags;
 249
 250   /* A format string to turn the macro into a normal instruction.
 251      Each %N in the string is replaced with operand number N (zero
 252      based).  */
 253   const char *format;
 254 };
 255
 256 extern const struct powerpc_macro powerpc_macros[];
 257 extern const int powerpc_num_macros;
 258
 259 #endif /* PPC_H */