gas/config/tc-i386.h

   1 /* tc-i386.h -- Header file for tc-i386.c
   2    Copyright 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
   3    2001, 2002, 2003, 2004
   4    Free Software Foundation, Inc.
   5
   6    This file is part of GAS, the GNU Assembler.
   7
   8    GAS is free software; you can redistribute it and/or modify
   9    it under the terms of the GNU General Public License as published by
  10    the Free Software Foundation; either version 2, or (at your option)
  11    any later version.
  12
  13    GAS is distributed in the hope that it will be useful,
  14    but WITHOUT ANY WARRANTY; without even the implied warranty of
  15    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16    GNU General Public License for more details.
  17
  18    You should have received a copy of the GNU General Public License
  19    along with GAS; see the file COPYING.  If not, write to the Free
  20    Software Foundation, 59 Temple Place - Suite 330, Boston, MA
  21    02111-1307, USA.  */
  22
  23 #ifndef TC_I386
  24 #define TC_I386 1
  25
  26 #ifndef BFD_ASSEMBLER
  27 #error So, do you know what you are doing?
  28 #endif
  29
  30 #ifdef ANSI_PROTOTYPES
  31 struct fix;
  32 #endif
  33
  34 #define TARGET_BYTES_BIG_ENDIAN 0
  35
  36 #ifdef TE_LYNX
  37 #define TARGET_FORMAT           "coff-i386-lynx"
  38 #endif
  39
  40 #define TARGET_ARCH             bfd_arch_i386
  41 #define TARGET_MACH             (i386_mach ())
  42 extern unsigned long i386_mach PARAMS ((void));
  43
  44 #ifdef TE_FreeBSD
  45 #define AOUT_TARGET_FORMAT      "a.out-i386-freebsd"
  46 #endif
  47 #ifdef TE_NetBSD
  48 #define AOUT_TARGET_FORMAT      "a.out-i386-netbsd"
  49 #endif
  50 #ifdef TE_386BSD
  51 #define AOUT_TARGET_FORMAT      "a.out-i386-bsd"
  52 #endif
  53 #ifdef TE_LINUX
  54 #define AOUT_TARGET_FORMAT      "a.out-i386-linux"
  55 #endif
  56 #ifdef TE_Mach
  57 #define AOUT_TARGET_FORMAT      "a.out-mach3"
  58 #endif
  59 #ifdef TE_DYNIX
  60 #define AOUT_TARGET_FORMAT      "a.out-i386-dynix"
  61 #endif
  62 #ifndef AOUT_TARGET_FORMAT
  63 #define AOUT_TARGET_FORMAT      "a.out-i386"
  64 #endif
  65
  66 #ifdef TE_FreeBSD
  67 #define ELF_TARGET_FORMAT       "elf32-i386-freebsd"
  68 #endif
  69 #ifndef ELF_TARGET_FORMAT
  70 #define ELF_TARGET_FORMAT       "elf32-i386"
  71 #endif
  72
  73 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
  74      || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
  75 extern const char *i386_target_format PARAMS ((void));
  76 #define TARGET_FORMAT i386_target_format ()
  77 #else
  78 #ifdef OBJ_ELF
  79 #define TARGET_FORMAT           ELF_TARGET_FORMAT
  80 #endif
  81 #ifdef OBJ_AOUT
  82 #define TARGET_FORMAT           AOUT_TARGET_FORMAT
  83 #endif
  84 #endif
  85
  86 #if (defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF))
  87 #define md_end i386_elf_emit_arch_note
  88 extern void i386_elf_emit_arch_note PARAMS ((void));
  89 #endif
  90
  91 #define SUB_SEGMENT_ALIGN(SEG, FRCHAIN) 0
  92
  93 #define LOCAL_LABELS_FB 1
  94
  95 extern const char extra_symbol_chars[];
  96 #define tc_symbol_chars extra_symbol_chars
  97
  98 #define MAX_OPERANDS 3          /* max operands per insn */
  99 #define MAX_IMMEDIATE_OPERANDS 2/* max immediates per insn (lcall, ljmp) */
 100 #define MAX_MEMORY_OPERANDS 2   /* max memory refs per insn (string ops) */
 101
 102 /* Prefixes will be emitted in the order defined below.
 103    WAIT_PREFIX must be the first prefix since FWAIT is really is an
 104    instruction, and so must come before any prefixes.  */
 105 #define WAIT_PREFIX     0
 106 #define LOCKREP_PREFIX  1
 107 #define ADDR_PREFIX     2
 108 #define DATA_PREFIX     3
 109 #define SEG_PREFIX      4
 110 #define REX_PREFIX      5       /* must come last.  */
 111 #define MAX_PREFIXES    6       /* max prefixes per opcode */
 112
 113 /* we define the syntax here (modulo base,index,scale syntax) */
 114 #define REGISTER_PREFIX '%'
 115 #define IMMEDIATE_PREFIX '$'
 116 #define ABSOLUTE_PREFIX '*'
 117
 118 #define TWO_BYTE_OPCODE_ESCAPE 0x0f
 119 #define NOP_OPCODE (char) 0x90
 120
 121 /* register numbers */
 122 #define EBP_REG_NUM 5
 123 #define ESP_REG_NUM 4
 124
 125 /* modrm_byte.regmem for twobyte escape */
 126 #define ESCAPE_TO_TWO_BYTE_ADDRESSING ESP_REG_NUM
 127 /* index_base_byte.index for no index register addressing */
 128 #define NO_INDEX_REGISTER ESP_REG_NUM
 129 /* index_base_byte.base for no base register addressing */
 130 #define NO_BASE_REGISTER EBP_REG_NUM
 131 #define NO_BASE_REGISTER_16 6
 132
 133 /* these are the instruction mnemonic suffixes.  */
 134 #define WORD_MNEM_SUFFIX  'w'
 135 #define BYTE_MNEM_SUFFIX  'b'
 136 #define SHORT_MNEM_SUFFIX 's'
 137 #define LONG_MNEM_SUFFIX  'l'
 138 #define QWORD_MNEM_SUFFIX  'q'
 139 /* Intel Syntax */
 140 #define LONG_DOUBLE_MNEM_SUFFIX 'x'
 141
 142 /* modrm.mode = REGMEM_FIELD_HAS_REG when a register is in there */
 143 #define REGMEM_FIELD_HAS_REG 0x3/* always = 0x3 */
 144 #define REGMEM_FIELD_HAS_MEM (~REGMEM_FIELD_HAS_REG)
 145
 146 #define END_OF_INSN '\0'
 147
 148 /* Intel Syntax */
 149 /* Values 0-4 map onto scale factor */
 150 #define BYTE_PTR     0
 151 #define WORD_PTR     1
 152 #define DWORD_PTR    2
 153 #define QWORD_PTR    3
 154 #define XWORD_PTR    4
 155 #define SHORT        5
 156 #define OFFSET_FLAT  6
 157 #define FLAT         7
 158 #define NONE_FOUND   8
 159
 160 typedef struct
 161 {
 162   /* instruction name sans width suffix ("mov" for movl insns) */
 163   char *name;
 164
 165   /* how many operands */
 166   unsigned int operands;
 167
 168   /* base_opcode is the fundamental opcode byte without optional
 169      prefix(es).  */
 170   unsigned int base_opcode;
 171
 172   /* extension_opcode is the 3 bit extension for group <n> insns.
 173      This field is also used to store the 8-bit opcode suffix for the
 174      AMD 3DNow! instructions.
 175      If this template has no extension opcode (the usual case) use None */
 176   unsigned int extension_opcode;
 177 #define None 0xffff             /* If no extension_opcode is possible.  */
 178
 179   /* cpu feature flags */
 180   unsigned int cpu_flags;
 181 #define Cpu086            0x1   /* Any old cpu will do, 0 does the same */
 182 #define Cpu186            0x2   /* i186 or better required */
 183 #define Cpu286            0x4   /* i286 or better required */
 184 #define Cpu386            0x8   /* i386 or better required */
 185 #define Cpu486           0x10   /* i486 or better required */
 186 #define Cpu586           0x20   /* i585 or better required */
 187 #define Cpu686           0x40   /* i686 or better required */
 188 #define CpuP4            0x80   /* Pentium4 or better required */
 189 #define CpuK6           0x100   /* AMD K6 or better required*/
 190 #define CpuAthlon       0x200   /* AMD Athlon or better required*/
 191 #define CpuSledgehammer 0x400   /* Sledgehammer or better required */
 192 #define CpuMMX          0x800   /* MMX support required */
 193 #define CpuSSE         0x1000   /* Streaming SIMD extensions required */
 194 #define CpuSSE2        0x2000   /* Streaming SIMD extensions 2 required */
 195 #define Cpu3dnow       0x4000   /* 3dnow! support required */
 196 #define CpuPNI         0x8000   /* Prescott New Instructions required */
 197 #define CpuPadLock    0x10000   /* VIA PadLock required */
 198
 199   /* These flags are set by gas depending on the flag_code.  */
 200 #define Cpu64        0x4000000   /* 64bit support required  */
 201 #define CpuNo64      0x8000000   /* Not supported in the 64bit mode  */
 202
 203   /* The default value for unknown CPUs - enable all features to avoid problems.  */
 204 #define CpuUnknownFlags (Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuSledgehammer|CpuMMX|CpuSSE|CpuSSE2|CpuPNI|Cpu3dnow|CpuK6|CpuAthlon|CpuPadLock)
 205
 206   /* the bits in opcode_modifier are used to generate the final opcode from
 207      the base_opcode.  These bits also are used to detect alternate forms of
 208      the same instruction */
 209   unsigned int opcode_modifier;
 210
 211   /* opcode_modifier bits: */
 212 #define W                  0x1  /* set if operands can be words or dwords
 213                                    encoded the canonical way */
 214 #define D                  0x2  /* D = 0 if Reg --> Regmem;
 215                                    D = 1 if Regmem --> Reg:    MUST BE 0x2 */
 216 #define Modrm              0x4
 217 #define FloatR             0x8  /* src/dest swap for floats:   MUST BE 0x8 */
 218 #define ShortForm         0x10  /* register is in low 3 bits of opcode */
 219 #define FloatMF           0x20  /* FP insn memory format bit, sized by 0x4 */
 220 #define Jump              0x40  /* special case for jump insns.  */
 221 #define JumpDword         0x80  /* call and jump */
 222 #define JumpByte         0x100  /* loop and jecxz */
 223 #define JumpInterSegment 0x200  /* special case for intersegment leaps/calls */
 224 #define FloatD           0x400  /* direction for float insns:  MUST BE 0x400 */
 225 #define Seg2ShortForm    0x800  /* encoding of load segment reg insns */
 226 #define Seg3ShortForm   0x1000  /* fs/gs segment register insns.  */
 227 #define Size16          0x2000  /* needs size prefix if in 32-bit mode */
 228 #define Size32          0x4000  /* needs size prefix if in 16-bit mode */
 229 #define Size64          0x8000  /* needs size prefix if in 16-bit mode */
 230 #define IgnoreSize     0x10000  /* instruction ignores operand size prefix */
 231 #define DefaultSize    0x20000  /* default insn size depends on mode */
 232 #define No_bSuf        0x40000  /* b suffix on instruction illegal */
 233 #define No_wSuf        0x80000  /* w suffix on instruction illegal */
 234 #define No_lSuf       0x100000  /* l suffix on instruction illegal */
 235 #define No_sSuf       0x200000  /* s suffix on instruction illegal */
 236 #define No_qSuf       0x400000  /* q suffix on instruction illegal */
 237 #define No_xSuf       0x800000  /* x suffix on instruction illegal */
 238 #define FWait        0x1000000  /* instruction needs FWAIT */
 239 #define IsString     0x2000000  /* quick test for string instructions */
 240 #define regKludge    0x4000000  /* fake an extra reg operand for clr, imul */
 241 #define IsPrefix     0x8000000  /* opcode is a prefix */
 242 #define ImmExt      0x10000000  /* instruction has extension in 8 bit imm */
 243 #define NoRex64     0x20000000  /* instruction don't need Rex64 prefix.  */
 244 #define Rex64       0x40000000  /* instruction require Rex64 prefix.  */
 245 #define Ugh         0x80000000  /* deprecated fp insn, gets a warning */
 246
 247   /* operand_types[i] describes the type of operand i.  This is made
 248      by OR'ing together all of the possible type masks.  (e.g.
 249      'operand_types[i] = Reg|Imm' specifies that operand i can be
 250      either a register or an immediate operand.  */
 251   unsigned int operand_types[3];
 252
 253   /* operand_types[i] bits */
 254   /* register */
 255 #define Reg8               0x1  /* 8 bit reg */
 256 #define Reg16              0x2  /* 16 bit reg */
 257 #define Reg32              0x4  /* 32 bit reg */
 258 #define Reg64              0x8  /* 64 bit reg */
 259   /* immediate */
 260 #define Imm8              0x10  /* 8 bit immediate */
 261 #define Imm8S             0x20  /* 8 bit immediate sign extended */
 262 #define Imm16             0x40  /* 16 bit immediate */
 263 #define Imm32             0x80  /* 32 bit immediate */
 264 #define Imm32S           0x100  /* 32 bit immediate sign extended */
 265 #define Imm64            0x200  /* 64 bit immediate */
 266 #define Imm1             0x400  /* 1 bit immediate */
 267   /* memory */
 268 #define BaseIndex        0x800
 269   /* Disp8,16,32 are used in different ways, depending on the
 270      instruction.  For jumps, they specify the size of the PC relative
 271      displacement, for baseindex type instructions, they specify the
 272      size of the offset relative to the base register, and for memory
 273      offset instructions such as `mov 1234,%al' they specify the size of
 274      the offset relative to the segment base.  */
 275 #define Disp8           0x1000  /* 8 bit displacement */
 276 #define Disp16          0x2000  /* 16 bit displacement */
 277 #define Disp32          0x4000  /* 32 bit displacement */
 278 #define Disp32S         0x8000  /* 32 bit signed displacement */
 279 #define Disp64         0x10000  /* 64 bit displacement */
 280   /* specials */
 281 #define InOutPortReg   0x20000  /* register to hold in/out port addr = dx */
 282 #define ShiftCount     0x40000  /* register to hold shift cound = cl */
 283 #define Control        0x80000  /* Control register */
 284 #define Debug         0x100000  /* Debug register */
 285 #define Test          0x200000  /* Test register */
 286 #define FloatReg      0x400000  /* Float register */
 287 #define FloatAcc      0x800000  /* Float stack top %st(0) */
 288 #define SReg2        0x1000000  /* 2 bit segment register */
 289 #define SReg3        0x2000000  /* 3 bit segment register */
 290 #define Acc          0x4000000  /* Accumulator %al or %ax or %eax */
 291 #define JumpAbsolute 0x8000000
 292 #define RegMMX      0x10000000  /* MMX register */
 293 #define RegXMM      0x20000000  /* XMM registers in PIII */
 294 #define EsSeg       0x40000000  /* String insn operand with fixed es segment */
 295
 296   /* InvMem is for instructions with a modrm byte that only allow a
 297      general register encoding in the i.tm.mode and i.tm.regmem fields,
 298      eg. control reg moves.  They really ought to support a memory form,
 299      but don't, so we add an InvMem flag to the register operand to
 300      indicate that it should be encoded in the i.tm.regmem field.  */
 301 #define InvMem      0x80000000
 302
 303 #define Reg     (Reg8|Reg16|Reg32|Reg64) /* gen'l register */
 304 #define WordReg (Reg16|Reg32|Reg64)
 305 #define ImplicitRegister (InOutPortReg|ShiftCount|Acc|FloatAcc)
 306 #define Imm     (Imm8|Imm8S|Imm16|Imm32S|Imm32|Imm64) /* gen'l immediate */
 307 #define EncImm  (Imm8|Imm16|Imm32|Imm32S) /* Encodable gen'l immediate */
 308 #define Disp    (Disp8|Disp16|Disp32|Disp32S|Disp64) /* General displacement */
 309 #define AnyMem  (Disp8|Disp16|Disp32|Disp32S|BaseIndex|InvMem)  /* General memory */
 310   /* The following aliases are defined because the opcode table
 311      carefully specifies the allowed memory types for each instruction.
 312      At the moment we can only tell a memory reference size by the
 313      instruction suffix, so there's not much point in defining Mem8,
 314      Mem16, Mem32 and Mem64 opcode modifiers - We might as well just use
 315      the suffix directly to check memory operands.  */
 316 #define LLongMem AnyMem         /* 64 bits (or more) */
 317 #define LongMem AnyMem          /* 32 bit memory ref */
 318 #define ShortMem AnyMem         /* 16 bit memory ref */
 319 #define WordMem AnyMem          /* 16 or 32 bit memory ref */
 320 #define ByteMem AnyMem          /* 8 bit memory ref */
 321 }
 322 template;
 323
 324 /*
 325   'templates' is for grouping together 'template' structures for opcodes
 326   of the same name.  This is only used for storing the insns in the grand
 327   ole hash table of insns.
 328   The templates themselves start at START and range up to (but not including)
 329   END.
 330   */
 331 typedef struct
 332 {
 333   const template *start;
 334   const template *end;
 335 }
 336 templates;
 337
 338 /* these are for register name --> number & type hash lookup */
 339 typedef struct
 340 {
 341   char *reg_name;
 342   unsigned int reg_type;
 343   unsigned int reg_flags;
 344 #define RegRex      0x1  /* Extended register.  */
 345 #define RegRex64    0x2  /* Extended 8 bit register.  */
 346   unsigned int reg_num;
 347 }
 348 reg_entry;
 349
 350 typedef struct
 351 {
 352   char *seg_name;
 353   unsigned int seg_prefix;
 354 }
 355 seg_entry;
 356
 357 /* 386 operand encoding bytes:  see 386 book for details of this.  */
 358 typedef struct
 359 {
 360   unsigned int regmem;  /* codes register or memory operand */
 361   unsigned int reg;     /* codes register operand (or extended opcode) */
 362   unsigned int mode;    /* how to interpret regmem & reg */
 363 }
 364 modrm_byte;
 365
 366 /* x86-64 extension prefix.  */
 367 typedef int rex_byte;
 368 #define REX_OPCODE      0x40
 369
 370 /* Indicates 64 bit operand size.  */
 371 #define REX_MODE64      8
 372 /* High extension to reg field of modrm byte.  */
 373 #define REX_EXTX        4
 374 /* High extension to SIB index field.  */
 375 #define REX_EXTY        2
 376 /* High extension to base field of modrm or SIB, or reg field of opcode.  */
 377 #define REX_EXTZ        1
 378
 379 /* 386 opcode byte to code indirect addressing.  */
 380 typedef struct
 381 {
 382   unsigned base;
 383   unsigned index;
 384   unsigned scale;
 385 }
 386 sib_byte;
 387
 388 /* x86 arch names and features */
 389 typedef struct
 390 {
 391   const char *name;     /* arch name */
 392   unsigned int flags;   /* cpu feature flags */
 393 }
 394 arch_entry;
 395
 396 /* The name of the global offset table generated by the compiler. Allow
 397    this to be overridden if need be.  */
 398 #ifndef GLOBAL_OFFSET_TABLE_NAME
 399 #define GLOBAL_OFFSET_TABLE_NAME "_GLOBAL_OFFSET_TABLE_"
 400 #endif
 401
 402 #ifndef LEX_AT
 403 #define TC_PARSE_CONS_EXPRESSION(EXP, NBYTES) x86_cons (EXP, NBYTES)
 404 extern void x86_cons PARAMS ((expressionS *, int));
 405
 406 #define TC_CONS_FIX_NEW(FRAG,OFF,LEN,EXP) x86_cons_fix_new(FRAG, OFF, LEN, EXP)
 407 extern void x86_cons_fix_new
 408   PARAMS ((fragS *, unsigned int, unsigned int, expressionS *));
 409 #endif
 410
 411 #ifdef TE_PE
 412 #define TC_CONS_FIX_NEW(FRAG,OFF,LEN,EXP) x86_pe_cons_fix_new(FRAG, OFF, LEN, EXP)
 413 extern void x86_pe_cons_fix_new
 414   PARAMS ((fragS *, unsigned int, unsigned int, expressionS *));
 415 #endif
 416
 417 #define DIFF_EXPR_OK    /* foo-. gets turned into PC relative relocs */
 418
 419 #define NO_RELOC BFD_RELOC_NONE
 420
 421 void i386_validate_fix PARAMS ((struct fix *));
 422 #define TC_VALIDATE_FIX(FIX,SEGTYPE,SKIP) i386_validate_fix(FIX)
 423
 424 #define tc_fix_adjustable(X)  tc_i386_fix_adjustable(X)
 425 extern int tc_i386_fix_adjustable PARAMS ((struct fix *));
 426
 427 /* Values passed to md_apply_fix3 don't include the symbol value.  */
 428 #define MD_APPLY_SYM_VALUE(FIX) 0
 429
 430 /* ELF wants external syms kept, as does PE COFF.  */
 431 #if defined (TE_PE) && defined (STRICT_PE_FORMAT)
 432 #define EXTERN_FORCE_RELOC                              \
 433   (OUTPUT_FLAVOR == bfd_target_elf_flavour              \
 434    || OUTPUT_FLAVOR == bfd_target_coff_flavour)
 435 #else
 436 #define EXTERN_FORCE_RELOC                              \
 437   (OUTPUT_FLAVOR == bfd_target_elf_flavour)
 438 #endif
 439
 440 /* This expression evaluates to true if the relocation is for a local
 441    object for which we still want to do the relocation at runtime.
 442    False if we are willing to perform this relocation while building
 443    the .o file.  GOTOFF does not need to be checked here because it is
 444    not pcrel.  I am not sure if some of the others are ever used with
 445    pcrel, but it is easier to be safe than sorry.  */
 446
 447 #define TC_FORCE_RELOCATION_LOCAL(FIX)                  \
 448   (!(FIX)->fx_pcrel                                     \
 449    || (FIX)->fx_plt                                     \
 450    || (FIX)->fx_r_type == BFD_RELOC_386_PLT32           \
 451    || (FIX)->fx_r_type == BFD_RELOC_386_GOT32           \
 452    || (FIX)->fx_r_type == BFD_RELOC_386_GOTPC           \
 453    || TC_FORCE_RELOCATION (FIX))
 454
 455 #define md_operand(x)
 456
 457 extern const struct relax_type md_relax_table[];
 458 #define TC_GENERIC_RELAX_TABLE md_relax_table
 459
 460 extern int optimize_align_code;
 461
 462 #define md_do_align(n, fill, len, max, around)                          \
 463 if ((n)                                                                 \
 464     && !need_pass_2                                                     \
 465     && optimize_align_code                                              \
 466     && (!(fill)                                                         \
 467         || ((char)*(fill) == (char)0x90 && (len) == 1))                 \
 468     && subseg_text_p (now_seg))                                         \
 469   {                                                                     \
 470     frag_align_code ((n), (max));                                       \
 471     goto around;                                                        \
 472   }
 473
 474 #define MAX_MEM_FOR_RS_ALIGN_CODE  15
 475
 476 extern void i386_align_code PARAMS ((fragS *, int));
 477
 478 #define HANDLE_ALIGN(fragP)                                             \
 479 if (fragP->fr_type == rs_align_code)                                    \
 480   i386_align_code (fragP, (fragP->fr_next->fr_address                   \
 481                            - fragP->fr_address                          \
 482                            - fragP->fr_fix));
 483
 484 void i386_print_statistics PARAMS ((FILE *));
 485 #define tc_print_statistics i386_print_statistics
 486
 487 #define md_number_to_chars number_to_chars_littleendian
 488
 489 #ifdef SCO_ELF
 490 #define tc_init_after_args() sco_id ()
 491 extern void sco_id PARAMS ((void));
 492 #endif
 493
 494 /* We want .cfi_* pseudo-ops for generating unwind info.  */
 495 #define TARGET_USE_CFIPOP 1
 496
 497 extern unsigned int x86_dwarf2_return_column;
 498 #define DWARF2_DEFAULT_RETURN_COLUMN x86_dwarf2_return_column
 499
 500 extern int x86_cie_data_alignment;
 501 #define DWARF2_CIE_DATA_ALIGNMENT x86_cie_data_alignment
 502
 503 #define tc_regname_to_dw2regnum tc_x86_regname_to_dw2regnum
 504 extern int tc_x86_regname_to_dw2regnum PARAMS ((const char *regname));
 505
 506 #define tc_cfi_frame_initial_instructions tc_x86_frame_initial_instructions
 507 extern void tc_x86_frame_initial_instructions PARAMS ((void));
 508
 509 #endif /* TC_I386 */