gas/config/tc-i386.h

   1 /* tc-i386.h -- Header file for tc-i386.c
   2    Copyright 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
   3    2001, 2002
   4    Free Software Foundation, Inc.
   5
   6    This file is part of GAS, the GNU Assembler.
   7
   8    GAS is free software; you can redistribute it and/or modify
   9    it under the terms of the GNU General Public License as published by
  10    the Free Software Foundation; either version 2, or (at your option)
  11    any later version.
  12
  13    GAS is distributed in the hope that it will be useful,
  14    but WITHOUT ANY WARRANTY; without even the implied warranty of
  15    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16    GNU General Public License for more details.
  17
  18    You should have received a copy of the GNU General Public License
  19    along with GAS; see the file COPYING.  If not, write to the Free
  20    Software Foundation, 59 Temple Place - Suite 330, Boston, MA
  21    02111-1307, USA.  */
  22
  23 #ifndef TC_I386
  24 #define TC_I386 1
  25
  26 #ifdef ANSI_PROTOTYPES
  27 struct fix;
  28 #endif
  29
  30 #define TARGET_BYTES_BIG_ENDIAN 0
  31
  32 #ifdef TE_LYNX
  33 #define TARGET_FORMAT           "coff-i386-lynx"
  34 #endif
  35
  36 #ifdef BFD_ASSEMBLER
  37 #define TARGET_ARCH             bfd_arch_i386
  38 #define TARGET_MACH             (i386_mach ())
  39 extern unsigned long i386_mach PARAMS ((void));
  40
  41 #ifdef TE_FreeBSD
  42 #define AOUT_TARGET_FORMAT      "a.out-i386-freebsd"
  43 #endif
  44 #ifdef TE_NetBSD
  45 #define AOUT_TARGET_FORMAT      "a.out-i386-netbsd"
  46 #endif
  47 #ifdef TE_386BSD
  48 #define AOUT_TARGET_FORMAT      "a.out-i386-bsd"
  49 #endif
  50 #ifdef TE_LINUX
  51 #define AOUT_TARGET_FORMAT      "a.out-i386-linux"
  52 #endif
  53 #ifdef TE_Mach
  54 #define AOUT_TARGET_FORMAT      "a.out-mach3"
  55 #endif
  56 #ifdef TE_DYNIX
  57 #define AOUT_TARGET_FORMAT      "a.out-i386-dynix"
  58 #endif
  59 #ifndef AOUT_TARGET_FORMAT
  60 #define AOUT_TARGET_FORMAT      "a.out-i386"
  61 #endif
  62
  63 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
  64      || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
  65 extern const char *i386_target_format PARAMS ((void));
  66 #define TARGET_FORMAT i386_target_format ()
  67 #else
  68 #ifdef OBJ_ELF
  69 #define TARGET_FORMAT           "elf32-i386"
  70 #endif
  71 #ifdef OBJ_AOUT
  72 #define TARGET_FORMAT           AOUT_TARGET_FORMAT
  73 #endif
  74 #endif
  75
  76 #if (defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF))
  77 #define md_end i386_elf_emit_arch_note
  78 extern void i386_elf_emit_arch_note PARAMS ((void));
  79 #endif
  80
  81 #define SUB_SEGMENT_ALIGN(SEG, FRCHAIN) 0
  82
  83 #else /* ! BFD_ASSEMBLER */
  84
  85 /* COFF STUFF */
  86
  87 #define COFF_MAGIC I386MAGIC
  88 #define BFD_ARCH bfd_arch_i386
  89 #define COFF_FLAGS F_AR32WR
  90 #define TC_COUNT_RELOC(x) ((x)->fx_addsy || (x)->fx_r_type==7)
  91 #define TC_COFF_FIX2RTYPE(fixP) tc_coff_fix2rtype(fixP)
  92 extern short tc_coff_fix2rtype PARAMS ((struct fix *));
  93 #define TC_COFF_SIZEMACHDEP(frag) tc_coff_sizemachdep (frag)
  94 extern int tc_coff_sizemachdep PARAMS ((fragS *frag));
  95
  96 #ifdef TE_GO32
  97 /* DJGPP now expects some sections to be 2**4 aligned.  */
  98 #define SUB_SEGMENT_ALIGN(SEG, FRCHAIN)                                 \
  99   ((strcmp (obj_segment_name (SEG), ".text") == 0                       \
 100     || strcmp (obj_segment_name (SEG), ".data") == 0                    \
 101     || strcmp (obj_segment_name (SEG), ".bss") == 0                     \
 102     || strncmp (obj_segment_name (SEG), ".gnu.linkonce.t", 15) == 0     \
 103     || strncmp (obj_segment_name (SEG), ".gnu.linkonce.d", 15) == 0     \
 104     || strncmp (obj_segment_name (SEG), ".gnu.linkonce.r", 15) == 0)    \
 105    ? 4                                                                  \
 106    : 2)
 107 #else
 108 #define SUB_SEGMENT_ALIGN(SEG, FRCHAIN) 2
 109 #endif
 110
 111 #ifdef TE_386BSD
 112 /* The BSDI linker apparently rejects objects with a machine type of
 113    M_386 (100).  */
 114 #define AOUT_MACHTYPE 0
 115 #else
 116 #define AOUT_MACHTYPE 100
 117 #endif
 118
 119 #ifndef OBJ_AOUT
 120 #ifndef TE_PE
 121 #ifndef TE_GO32
 122 /* Local labels starts with .L */
 123 #define LOCAL_LABEL(name) (name[0] == '.' \
 124                  && (name[1] == 'L' || name[1] == 'X' || name[1] == '.'))
 125 #endif
 126 #endif
 127 #endif
 128
 129 #define tc_aout_pre_write_hook(x)       {;}     /* not used */
 130 #define tc_crawl_symbol_chain(a)        {;}     /* not used */
 131 #define tc_headers_hook(a)              {;}     /* not used */
 132 #define tc_coff_symbol_emit_hook(a)     {;}     /* not used */
 133
 134 #endif /* ! BFD_ASSEMBLER */
 135
 136 #define LOCAL_LABELS_FB 1
 137
 138 extern const char extra_symbol_chars[];
 139 #define tc_symbol_chars extra_symbol_chars
 140
 141 #define MAX_OPERANDS 3          /* max operands per insn */
 142 #define MAX_IMMEDIATE_OPERANDS 2/* max immediates per insn (lcall, ljmp) */
 143 #define MAX_MEMORY_OPERANDS 2   /* max memory refs per insn (string ops) */
 144
 145 /* Prefixes will be emitted in the order defined below.
 146    WAIT_PREFIX must be the first prefix since FWAIT is really is an
 147    instruction, and so must come before any prefixes.  */
 148 #define WAIT_PREFIX     0
 149 #define LOCKREP_PREFIX  1
 150 #define ADDR_PREFIX     2
 151 #define DATA_PREFIX     3
 152 #define SEG_PREFIX      4
 153 #define REX_PREFIX      5       /* must come last.  */
 154 #define MAX_PREFIXES    6       /* max prefixes per opcode */
 155
 156 /* we define the syntax here (modulo base,index,scale syntax) */
 157 #define REGISTER_PREFIX '%'
 158 #define IMMEDIATE_PREFIX '$'
 159 #define ABSOLUTE_PREFIX '*'
 160
 161 #define TWO_BYTE_OPCODE_ESCAPE 0x0f
 162 #define NOP_OPCODE (char) 0x90
 163
 164 /* register numbers */
 165 #define EBP_REG_NUM 5
 166 #define ESP_REG_NUM 4
 167
 168 /* modrm_byte.regmem for twobyte escape */
 169 #define ESCAPE_TO_TWO_BYTE_ADDRESSING ESP_REG_NUM
 170 /* index_base_byte.index for no index register addressing */
 171 #define NO_INDEX_REGISTER ESP_REG_NUM
 172 /* index_base_byte.base for no base register addressing */
 173 #define NO_BASE_REGISTER EBP_REG_NUM
 174 #define NO_BASE_REGISTER_16 6
 175
 176 /* these are the instruction mnemonic suffixes.  */
 177 #define WORD_MNEM_SUFFIX  'w'
 178 #define BYTE_MNEM_SUFFIX  'b'
 179 #define SHORT_MNEM_SUFFIX 's'
 180 #define LONG_MNEM_SUFFIX  'l'
 181 #define QWORD_MNEM_SUFFIX  'q'
 182 /* Intel Syntax */
 183 #define LONG_DOUBLE_MNEM_SUFFIX 'x'
 184
 185 /* modrm.mode = REGMEM_FIELD_HAS_REG when a register is in there */
 186 #define REGMEM_FIELD_HAS_REG 0x3/* always = 0x3 */
 187 #define REGMEM_FIELD_HAS_MEM (~REGMEM_FIELD_HAS_REG)
 188
 189 #define END_OF_INSN '\0'
 190
 191 /* Intel Syntax */
 192 /* Values 0-4 map onto scale factor */
 193 #define BYTE_PTR     0
 194 #define WORD_PTR     1
 195 #define DWORD_PTR    2
 196 #define QWORD_PTR    3
 197 #define XWORD_PTR    4
 198 #define SHORT        5
 199 #define OFFSET_FLAT  6
 200 #define FLAT         7
 201 #define NONE_FOUND   8
 202
 203 typedef struct
 204 {
 205   /* instruction name sans width suffix ("mov" for movl insns) */
 206   char *name;
 207
 208   /* how many operands */
 209   unsigned int operands;
 210
 211   /* base_opcode is the fundamental opcode byte without optional
 212      prefix(es).  */
 213   unsigned int base_opcode;
 214
 215   /* extension_opcode is the 3 bit extension for group <n> insns.
 216      This field is also used to store the 8-bit opcode suffix for the
 217      AMD 3DNow! instructions.
 218      If this template has no extension opcode (the usual case) use None */
 219   unsigned int extension_opcode;
 220 #define None 0xffff             /* If no extension_opcode is possible.  */
 221
 222   /* cpu feature flags */
 223   unsigned int cpu_flags;
 224 #define Cpu086            0x1   /* Any old cpu will do, 0 does the same */
 225 #define Cpu186            0x2   /* i186 or better required */
 226 #define Cpu286            0x4   /* i286 or better required */
 227 #define Cpu386            0x8   /* i386 or better required */
 228 #define Cpu486           0x10   /* i486 or better required */
 229 #define Cpu586           0x20   /* i585 or better required */
 230 #define Cpu686           0x40   /* i686 or better required */
 231 #define CpuP4            0x80   /* Pentium4 or better required */
 232 #define CpuK6           0x100   /* AMD K6 or better required*/
 233 #define CpuAthlon       0x200   /* AMD Athlon or better required*/
 234 #define CpuSledgehammer 0x400   /* Sledgehammer or better required */
 235 #define CpuMMX          0x800   /* MMX support required */
 236 #define CpuSSE         0x1000   /* Streaming SIMD extensions required */
 237 #define CpuSSE2        0x2000   /* Streaming SIMD extensions 2 required */
 238 #define Cpu3dnow       0x4000   /* 3dnow! support required */
 239
 240   /* These flags are set by gas depending on the flag_code.  */
 241 #define Cpu64        0x4000000   /* 64bit support required  */
 242 #define CpuNo64      0x8000000   /* Not supported in the 64bit mode  */
 243
 244   /* The default value for unknown CPUs - enable all features to avoid problems.  */
 245 #define CpuUnknownFlags (Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuSledgehammer|CpuMMX|CpuSSE|CpuSSE2|Cpu3dnow|CpuK6|CpuAthlon)
 246
 247   /* the bits in opcode_modifier are used to generate the final opcode from
 248      the base_opcode.  These bits also are used to detect alternate forms of
 249      the same instruction */
 250   unsigned int opcode_modifier;
 251
 252   /* opcode_modifier bits: */
 253 #define W                  0x1  /* set if operands can be words or dwords
 254                                    encoded the canonical way */
 255 #define D                  0x2  /* D = 0 if Reg --> Regmem;
 256                                    D = 1 if Regmem --> Reg:    MUST BE 0x2 */
 257 #define Modrm              0x4
 258 #define FloatR             0x8  /* src/dest swap for floats:   MUST BE 0x8 */
 259 #define ShortForm         0x10  /* register is in low 3 bits of opcode */
 260 #define FloatMF           0x20  /* FP insn memory format bit, sized by 0x4 */
 261 #define Jump              0x40  /* special case for jump insns.  */
 262 #define JumpDword         0x80  /* call and jump */
 263 #define JumpByte         0x100  /* loop and jecxz */
 264 #define JumpInterSegment 0x200  /* special case for intersegment leaps/calls */
 265 #define FloatD           0x400  /* direction for float insns:  MUST BE 0x400 */
 266 #define Seg2ShortForm    0x800  /* encoding of load segment reg insns */
 267 #define Seg3ShortForm   0x1000  /* fs/gs segment register insns.  */
 268 #define Size16          0x2000  /* needs size prefix if in 32-bit mode */
 269 #define Size32          0x4000  /* needs size prefix if in 16-bit mode */
 270 #define Size64          0x8000  /* needs size prefix if in 16-bit mode */
 271 #define IgnoreSize     0x10000  /* instruction ignores operand size prefix */
 272 #define DefaultSize    0x20000  /* default insn size depends on mode */
 273 #define No_bSuf        0x40000  /* b suffix on instruction illegal */
 274 #define No_wSuf        0x80000  /* w suffix on instruction illegal */
 275 #define No_lSuf       0x100000  /* l suffix on instruction illegal */
 276 #define No_sSuf       0x200000  /* s suffix on instruction illegal */
 277 #define No_qSuf       0x400000  /* q suffix on instruction illegal */
 278 #define No_xSuf       0x800000  /* x suffix on instruction illegal */
 279 #define FWait        0x1000000  /* instruction needs FWAIT */
 280 #define IsString     0x2000000  /* quick test for string instructions */
 281 #define regKludge    0x4000000  /* fake an extra reg operand for clr, imul */
 282 #define IsPrefix     0x8000000  /* opcode is a prefix */
 283 #define ImmExt      0x10000000  /* instruction has extension in 8 bit imm */
 284 #define NoRex64     0x20000000  /* instruction don't need Rex64 prefix.  */
 285 #define Rex64       0x40000000  /* instruction require Rex64 prefix.  */
 286 #define Ugh         0x80000000  /* deprecated fp insn, gets a warning */
 287
 288   /* operand_types[i] describes the type of operand i.  This is made
 289      by OR'ing together all of the possible type masks.  (e.g.
 290      'operand_types[i] = Reg|Imm' specifies that operand i can be
 291      either a register or an immediate operand.  */
 292   unsigned int operand_types[3];
 293
 294   /* operand_types[i] bits */
 295   /* register */
 296 #define Reg8               0x1  /* 8 bit reg */
 297 #define Reg16              0x2  /* 16 bit reg */
 298 #define Reg32              0x4  /* 32 bit reg */
 299 #define Reg64              0x8  /* 64 bit reg */
 300   /* immediate */
 301 #define Imm8              0x10  /* 8 bit immediate */
 302 #define Imm8S             0x20  /* 8 bit immediate sign extended */
 303 #define Imm16             0x40  /* 16 bit immediate */
 304 #define Imm32             0x80  /* 32 bit immediate */
 305 #define Imm32S           0x100  /* 32 bit immediate sign extended */
 306 #define Imm64            0x200  /* 64 bit immediate */
 307 #define Imm1             0x400  /* 1 bit immediate */
 308   /* memory */
 309 #define BaseIndex        0x800
 310   /* Disp8,16,32 are used in different ways, depending on the
 311      instruction.  For jumps, they specify the size of the PC relative
 312      displacement, for baseindex type instructions, they specify the
 313      size of the offset relative to the base register, and for memory
 314      offset instructions such as `mov 1234,%al' they specify the size of
 315      the offset relative to the segment base.  */
 316 #define Disp8           0x1000  /* 8 bit displacement */
 317 #define Disp16          0x2000  /* 16 bit displacement */
 318 #define Disp32          0x4000  /* 32 bit displacement */
 319 #define Disp32S         0x8000  /* 32 bit signed displacement */
 320 #define Disp64         0x10000  /* 64 bit displacement */
 321   /* specials */
 322 #define InOutPortReg   0x20000  /* register to hold in/out port addr = dx */
 323 #define ShiftCount     0x40000  /* register to hold shift cound = cl */
 324 #define Control        0x80000  /* Control register */
 325 #define Debug         0x100000  /* Debug register */
 326 #define Test          0x200000  /* Test register */
 327 #define FloatReg      0x400000  /* Float register */
 328 #define FloatAcc      0x800000  /* Float stack top %st(0) */
 329 #define SReg2        0x1000000  /* 2 bit segment register */
 330 #define SReg3        0x2000000  /* 3 bit segment register */
 331 #define Acc          0x4000000  /* Accumulator %al or %ax or %eax */
 332 #define JumpAbsolute 0x8000000
 333 #define RegMMX      0x10000000  /* MMX register */
 334 #define RegXMM      0x20000000  /* XMM registers in PIII */
 335 #define EsSeg       0x40000000  /* String insn operand with fixed es segment */
 336
 337   /* InvMem is for instructions with a modrm byte that only allow a
 338      general register encoding in the i.tm.mode and i.tm.regmem fields,
 339      eg. control reg moves.  They really ought to support a memory form,
 340      but don't, so we add an InvMem flag to the register operand to
 341      indicate that it should be encoded in the i.tm.regmem field.  */
 342 #define InvMem      0x80000000
 343
 344 #define Reg     (Reg8|Reg16|Reg32|Reg64) /* gen'l register */
 345 #define WordReg (Reg16|Reg32|Reg64)
 346 #define ImplicitRegister (InOutPortReg|ShiftCount|Acc|FloatAcc)
 347 #define Imm     (Imm8|Imm8S|Imm16|Imm32S|Imm32|Imm64) /* gen'l immediate */
 348 #define EncImm  (Imm8|Imm16|Imm32|Imm32S) /* Encodable gen'l immediate */
 349 #define Disp    (Disp8|Disp16|Disp32|Disp32S|Disp64) /* General displacement */
 350 #define AnyMem  (Disp8|Disp16|Disp32|Disp32S|BaseIndex|InvMem)  /* General memory */
 351   /* The following aliases are defined because the opcode table
 352      carefully specifies the allowed memory types for each instruction.
 353      At the moment we can only tell a memory reference size by the
 354      instruction suffix, so there's not much point in defining Mem8,
 355      Mem16, Mem32 and Mem64 opcode modifiers - We might as well just use
 356      the suffix directly to check memory operands.  */
 357 #define LLongMem AnyMem         /* 64 bits (or more) */
 358 #define LongMem AnyMem          /* 32 bit memory ref */
 359 #define ShortMem AnyMem         /* 16 bit memory ref */
 360 #define WordMem AnyMem          /* 16 or 32 bit memory ref */
 361 #define ByteMem AnyMem          /* 8 bit memory ref */
 362 }
 363 template;
 364
 365 /*
 366   'templates' is for grouping together 'template' structures for opcodes
 367   of the same name.  This is only used for storing the insns in the grand
 368   ole hash table of insns.
 369   The templates themselves start at START and range up to (but not including)
 370   END.
 371   */
 372 typedef struct
 373 {
 374   const template *start;
 375   const template *end;
 376 }
 377 templates;
 378
 379 /* these are for register name --> number & type hash lookup */
 380 typedef struct
 381 {
 382   char *reg_name;
 383   unsigned int reg_type;
 384   unsigned int reg_flags;
 385 #define RegRex      0x1  /* Extended register.  */
 386 #define RegRex64    0x2  /* Extended 8 bit register.  */
 387   unsigned int reg_num;
 388 }
 389 reg_entry;
 390
 391 typedef struct
 392 {
 393   char *seg_name;
 394   unsigned int seg_prefix;
 395 }
 396 seg_entry;
 397
 398 /* 386 operand encoding bytes:  see 386 book for details of this.  */
 399 typedef struct
 400 {
 401   unsigned int regmem;  /* codes register or memory operand */
 402   unsigned int reg;     /* codes register operand (or extended opcode) */
 403   unsigned int mode;    /* how to interpret regmem & reg */
 404 }
 405 modrm_byte;
 406
 407 /* x86-64 extension prefix.  */
 408 typedef int rex_byte;
 409 #define REX_OPCODE      0x40
 410
 411 /* Indicates 64 bit operand size.  */
 412 #define REX_MODE64      8
 413 /* High extension to reg field of modrm byte.  */
 414 #define REX_EXTX        4
 415 /* High extension to SIB index field.  */
 416 #define REX_EXTY        2
 417 /* High extension to base field of modrm or SIB, or reg field of opcode.  */
 418 #define REX_EXTZ        1
 419
 420 /* 386 opcode byte to code indirect addressing.  */
 421 typedef struct
 422 {
 423   unsigned base;
 424   unsigned index;
 425   unsigned scale;
 426 }
 427 sib_byte;
 428
 429 /* x86 arch names and features */
 430 typedef struct
 431 {
 432   const char *name;     /* arch name */
 433   unsigned int flags;   /* cpu feature flags */
 434 }
 435 arch_entry;
 436
 437 /* The name of the global offset table generated by the compiler. Allow
 438    this to be overridden if need be.  */
 439 #ifndef GLOBAL_OFFSET_TABLE_NAME
 440 #define GLOBAL_OFFSET_TABLE_NAME "_GLOBAL_OFFSET_TABLE_"
 441 #endif
 442
 443 #ifndef LEX_AT
 444 #define TC_PARSE_CONS_EXPRESSION(EXP, NBYTES) x86_cons (EXP, NBYTES)
 445 extern void x86_cons PARAMS ((expressionS *, int));
 446
 447 #define TC_CONS_FIX_NEW(FRAG,OFF,LEN,EXP) x86_cons_fix_new(FRAG, OFF, LEN, EXP)
 448 extern void x86_cons_fix_new
 449   PARAMS ((fragS *, unsigned int, unsigned int, expressionS *));
 450 #endif
 451
 452 #define DIFF_EXPR_OK    /* foo-. gets turned into PC relative relocs */
 453
 454 #ifdef BFD_ASSEMBLER
 455 #define NO_RELOC BFD_RELOC_NONE
 456
 457 void i386_validate_fix PARAMS ((struct fix *));
 458 #define TC_VALIDATE_FIX(FIXP,SEGTYPE,SKIP) i386_validate_fix(FIXP)
 459
 460 /* This is used to determine relocation types in tc-i386.c.  The first
 461    parameter is the current relocation type, the second one is the desired
 462    type.  The idea is that if the original type is already some kind of PIC
 463    relocation, we leave it alone, otherwise we give it the desired type */
 464
 465 #define tc_fix_adjustable(X)  tc_i386_fix_adjustable(X)
 466 extern int tc_i386_fix_adjustable PARAMS ((struct fix *));
 467
 468 #if (defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF) || defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)) && !defined (TE_PE)
 469 /* This arranges for gas/write.c to not apply a relocation if
 470    tc_fix_adjustable() says it is not adjustable.
 471    The "! symbol_used_in_reloc_p" test is there specifically to cover
 472    the case of non-global symbols in linkonce sections.  It's the
 473    generally correct thing to do though;  If a reloc is going to be
 474    emitted against a symbol then we don't want to adjust the fixup by
 475    applying the reloc during assembly.  The reloc will be applied by
 476    the linker during final link.  */
 477 #define TC_FIX_ADJUSTABLE(fixP) \
 478   (! symbol_used_in_reloc_p ((fixP)->fx_addsy) && tc_fix_adjustable (fixP))
 479 #endif
 480
 481 #define TC_FORCE_RELOCATION(FIXP)                       \
 482   ((FIXP)->fx_r_type == BFD_RELOC_VTABLE_INHERIT        \
 483    || (FIXP)->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
 484
 485 /* This expression evaluates to false if the relocation is for a local object
 486    for which we still want to do the relocation at runtime.  True if we
 487    are willing to perform this relocation while building the .o file.
 488    This is only used for pcrel relocations, so GOTOFF does not need to be
 489    checked here.  I am not sure if some of the others are ever used with
 490    pcrel, but it is easier to be safe than sorry.  */
 491
 492 #define TC_RELOC_RTSYM_LOC_FIXUP(FIX)                           \
 493   ((FIX)->fx_r_type != BFD_RELOC_386_PLT32                      \
 494    && (FIX)->fx_r_type != BFD_RELOC_386_GOT32                   \
 495    && (FIX)->fx_r_type != BFD_RELOC_386_GOTPC                   \
 496    && ((FIX)->fx_addsy == NULL                                  \
 497        || (! S_IS_EXTERNAL ((FIX)->fx_addsy)                    \
 498            && ! S_IS_WEAK ((FIX)->fx_addsy)                     \
 499            && S_IS_DEFINED ((FIX)->fx_addsy)                    \
 500            && ! S_IS_COMMON ((FIX)->fx_addsy))))
 501
 502 #else /* ! BFD_ASSEMBLER */
 503
 504 #define NO_RELOC 0
 505
 506 #define TC_RVA_RELOC 7
 507
 508 /* Need this for PIC relocations */
 509 #define NEED_FX_R_TYPE
 510
 511 #undef REVERSE_SORT_RELOCS
 512
 513 /* For COFF.  */
 514 #define TC_FORCE_RELOCATION(FIXP)                       \
 515   ((FIXP)->fx_r_type == 7)
 516 #endif /* ! BFD_ASSEMBLER */
 517
 518 #define md_operand(x)
 519
 520 extern const struct relax_type md_relax_table[];
 521 #define TC_GENERIC_RELAX_TABLE md_relax_table
 522
 523 #define md_do_align(n, fill, len, max, around)                          \
 524 if ((n) && !need_pass_2                                                 \
 525     && (!(fill) || ((char)*(fill) == (char)0x90 && (len) == 1))         \
 526     && subseg_text_p (now_seg))                                         \
 527   {                                                                     \
 528     frag_align_code ((n), (max));                                       \
 529     goto around;                                                        \
 530   }
 531
 532 #define MAX_MEM_FOR_RS_ALIGN_CODE  15
 533
 534 extern void i386_align_code PARAMS ((fragS *, int));
 535
 536 #define HANDLE_ALIGN(fragP)                                             \
 537 if (fragP->fr_type == rs_align_code)                                    \
 538   i386_align_code (fragP, (fragP->fr_next->fr_address                   \
 539                            - fragP->fr_address                          \
 540                            - fragP->fr_fix));
 541
 542 void i386_print_statistics PARAMS ((FILE *));
 543 #define tc_print_statistics i386_print_statistics
 544
 545 #define md_number_to_chars number_to_chars_littleendian
 546
 547 #ifdef SCO_ELF
 548 #define tc_init_after_args() sco_id ()
 549 extern void sco_id PARAMS ((void));
 550 #endif
 551
 552 #endif /* TC_I386 */