opcodes/frv-desc.c

   1 /* CPU data for frv.
   2
   3 THIS FILE IS MACHINE GENERATED WITH CGEN.
   4
   5 Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
   6
   7 This file is part of the GNU Binutils and/or GDB, the GNU debugger.
   8
   9 This program is free software; you can redistribute it and/or modify
  10 it under the terms of the GNU General Public License as published by
  11 the Free Software Foundation; either version 2, or (at your option)
  12 any later version.
  13
  14 This program is distributed in the hope that it will be useful,
  15 but WITHOUT ANY WARRANTY; without even the implied warranty of
  16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17 GNU General Public License for more details.
  18
  19 You should have received a copy of the GNU General Public License along
  20 with this program; if not, write to the Free Software Foundation, Inc.,
  21 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  22
  23 */
  24
  25 #include "sysdep.h"
  26 #include <stdio.h>
  27 #include <stdarg.h>
  28 #include "ansidecl.h"
  29 #include "bfd.h"
  30 #include "symcat.h"
  31 #include "frv-desc.h"
  32 #include "frv-opc.h"
  33 #include "opintl.h"
  34 #include "libiberty.h"
  35 #include "xregex.h"
  36
  37 /* Attributes.  */
  38
  39 static const CGEN_ATTR_ENTRY bool_attr[] =
  40 {
  41   { "#f", 0 },
  42   { "#t", 1 },
  43   { 0, 0 }
  44 };
  45
  46 static const CGEN_ATTR_ENTRY MACH_attr[] =
  47 {
  48   { "base", MACH_BASE },
  49   { "frv", MACH_FRV },
  50   { "fr500", MACH_FR500 },
  51   { "fr400", MACH_FR400 },
  52   { "tomcat", MACH_TOMCAT },
  53   { "simple", MACH_SIMPLE },
  54   { "max", MACH_MAX },
  55   { 0, 0 }
  56 };
  57
  58 static const CGEN_ATTR_ENTRY ISA_attr[] =
  59 {
  60   { "frv", ISA_FRV },
  61   { "max", ISA_MAX },
  62   { 0, 0 }
  63 };
  64
  65 static const CGEN_ATTR_ENTRY UNIT_attr[] =
  66 {
  67   { "NIL", UNIT_NIL },
  68   { "I0", UNIT_I0 },
  69   { "I1", UNIT_I1 },
  70   { "I01", UNIT_I01 },
  71   { "FM0", UNIT_FM0 },
  72   { "FM1", UNIT_FM1 },
  73   { "FM01", UNIT_FM01 },
  74   { "B0", UNIT_B0 },
  75   { "B1", UNIT_B1 },
  76   { "B01", UNIT_B01 },
  77   { "C", UNIT_C },
  78   { "MULT_DIV", UNIT_MULT_DIV },
  79   { "LOAD", UNIT_LOAD },
  80   { "NUM_UNITS", UNIT_NUM_UNITS },
  81   { 0, 0 }
  82 };
  83
  84 static const CGEN_ATTR_ENTRY FR400_MAJOR_attr[] =
  85 {
  86   { "NONE", FR400_MAJOR_NONE },
  87   { "I_1", FR400_MAJOR_I_1 },
  88   { "I_2", FR400_MAJOR_I_2 },
  89   { "I_3", FR400_MAJOR_I_3 },
  90   { "I_4", FR400_MAJOR_I_4 },
  91   { "I_5", FR400_MAJOR_I_5 },
  92   { "B_1", FR400_MAJOR_B_1 },
  93   { "B_2", FR400_MAJOR_B_2 },
  94   { "B_3", FR400_MAJOR_B_3 },
  95   { "B_4", FR400_MAJOR_B_4 },
  96   { "B_5", FR400_MAJOR_B_5 },
  97   { "B_6", FR400_MAJOR_B_6 },
  98   { "C_1", FR400_MAJOR_C_1 },
  99   { "C_2", FR400_MAJOR_C_2 },
 100   { "M_1", FR400_MAJOR_M_1 },
 101   { "M_2", FR400_MAJOR_M_2 },
 102   { 0, 0 }
 103 };
 104
 105 static const CGEN_ATTR_ENTRY FR500_MAJOR_attr[] =
 106 {
 107   { "NONE", FR500_MAJOR_NONE },
 108   { "I_1", FR500_MAJOR_I_1 },
 109   { "I_2", FR500_MAJOR_I_2 },
 110   { "I_3", FR500_MAJOR_I_3 },
 111   { "I_4", FR500_MAJOR_I_4 },
 112   { "I_5", FR500_MAJOR_I_5 },
 113   { "I_6", FR500_MAJOR_I_6 },
 114   { "B_1", FR500_MAJOR_B_1 },
 115   { "B_2", FR500_MAJOR_B_2 },
 116   { "B_3", FR500_MAJOR_B_3 },
 117   { "B_4", FR500_MAJOR_B_4 },
 118   { "B_5", FR500_MAJOR_B_5 },
 119   { "B_6", FR500_MAJOR_B_6 },
 120   { "C_1", FR500_MAJOR_C_1 },
 121   { "C_2", FR500_MAJOR_C_2 },
 122   { "F_1", FR500_MAJOR_F_1 },
 123   { "F_2", FR500_MAJOR_F_2 },
 124   { "F_3", FR500_MAJOR_F_3 },
 125   { "F_4", FR500_MAJOR_F_4 },
 126   { "F_5", FR500_MAJOR_F_5 },
 127   { "F_6", FR500_MAJOR_F_6 },
 128   { "F_7", FR500_MAJOR_F_7 },
 129   { "F_8", FR500_MAJOR_F_8 },
 130   { "M_1", FR500_MAJOR_M_1 },
 131   { "M_2", FR500_MAJOR_M_2 },
 132   { "M_3", FR500_MAJOR_M_3 },
 133   { "M_4", FR500_MAJOR_M_4 },
 134   { "M_5", FR500_MAJOR_M_5 },
 135   { "M_6", FR500_MAJOR_M_6 },
 136   { "M_7", FR500_MAJOR_M_7 },
 137   { "M_8", FR500_MAJOR_M_8 },
 138   { 0, 0 }
 139 };
 140
 141 const CGEN_ATTR_TABLE frv_cgen_ifield_attr_table[] =
 142 {
 143   { "MACH", & MACH_attr[0], & MACH_attr[0] },
 144   { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
 145   { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
 146   { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
 147   { "RESERVED", &bool_attr[0], &bool_attr[0] },
 148   { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
 149   { "SIGNED", &bool_attr[0], &bool_attr[0] },
 150   { 0, 0, 0 }
 151 };
 152
 153 const CGEN_ATTR_TABLE frv_cgen_hardware_attr_table[] =
 154 {
 155   { "MACH", & MACH_attr[0], & MACH_attr[0] },
 156   { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
 157   { "CACHE-ADDR", &bool_attr[0], &bool_attr[0] },
 158   { "PC", &bool_attr[0], &bool_attr[0] },
 159   { "PROFILE", &bool_attr[0], &bool_attr[0] },
 160   { 0, 0, 0 }
 161 };
 162
 163 const CGEN_ATTR_TABLE frv_cgen_operand_attr_table[] =
 164 {
 165   { "MACH", & MACH_attr[0], & MACH_attr[0] },
 166   { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
 167   { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
 168   { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
 169   { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
 170   { "SIGNED", &bool_attr[0], &bool_attr[0] },
 171   { "NEGATIVE", &bool_attr[0], &bool_attr[0] },
 172   { "RELAX", &bool_attr[0], &bool_attr[0] },
 173   { "SEM-ONLY", &bool_attr[0], &bool_attr[0] },
 174   { "HASH-PREFIX", &bool_attr[0], &bool_attr[0] },
 175   { 0, 0, 0 }
 176 };
 177
 178 const CGEN_ATTR_TABLE frv_cgen_insn_attr_table[] =
 179 {
 180   { "MACH", & MACH_attr[0], & MACH_attr[0] },
 181   { "UNIT", & UNIT_attr[0], & UNIT_attr[0] },
 182   { "FR400-MAJOR", & FR400_MAJOR_attr[0], & FR400_MAJOR_attr[0] },
 183   { "FR500-MAJOR", & FR500_MAJOR_attr[0], & FR500_MAJOR_attr[0] },
 184   { "ALIAS", &bool_attr[0], &bool_attr[0] },
 185   { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
 186   { "UNCOND-CTI", &bool_attr[0], &bool_attr[0] },
 187   { "COND-CTI", &bool_attr[0], &bool_attr[0] },
 188   { "SKIP-CTI", &bool_attr[0], &bool_attr[0] },
 189   { "DELAY-SLOT", &bool_attr[0], &bool_attr[0] },
 190   { "RELAXABLE", &bool_attr[0], &bool_attr[0] },
 191   { "RELAX", &bool_attr[0], &bool_attr[0] },
 192   { "NO-DIS", &bool_attr[0], &bool_attr[0] },
 193   { "PBB", &bool_attr[0], &bool_attr[0] },
 194   { "PRIVILEGED", &bool_attr[0], &bool_attr[0] },
 195   { "NON-EXCEPTING", &bool_attr[0], &bool_attr[0] },
 196   { "CONDITIONAL", &bool_attr[0], &bool_attr[0] },
 197   { "FR-ACCESS", &bool_attr[0], &bool_attr[0] },
 198   { "PRESERVE-OVF", &bool_attr[0], &bool_attr[0] },
 199   { 0, 0, 0 }
 200 };
 201
 202 /* Instruction set variants.  */
 203
 204 static const CGEN_ISA frv_cgen_isa_table[] = {
 205   { "frv", 32, 32, 32, 32 },
 206   { 0, 0, 0, 0, 0 }
 207 };
 208
 209 /* Machine variants.  */
 210
 211 static const CGEN_MACH frv_cgen_mach_table[] = {
 212   { "frv", "frv", MACH_FRV, 0 },
 213   { "fr500", "fr500", MACH_FR500, 0 },
 214   { "tomcat", "tomcat", MACH_TOMCAT, 0 },
 215   { "fr400", "fr400", MACH_FR400, 0 },
 216   { "simple", "simple", MACH_SIMPLE, 0 },
 217   { 0, 0, 0, 0 }
 218 };
 219
 220 static CGEN_KEYWORD_ENTRY frv_cgen_opval_gr_names_entries[] =
 221 {
 222   { "sp", 1, {0, {0}}, 0, 0 },
 223   { "fp", 2, {0, {0}}, 0, 0 },
 224   { "gr0", 0, {0, {0}}, 0, 0 },
 225   { "gr1", 1, {0, {0}}, 0, 0 },
 226   { "gr2", 2, {0, {0}}, 0, 0 },
 227   { "gr3", 3, {0, {0}}, 0, 0 },
 228   { "gr4", 4, {0, {0}}, 0, 0 },
 229   { "gr5", 5, {0, {0}}, 0, 0 },
 230   { "gr6", 6, {0, {0}}, 0, 0 },
 231   { "gr7", 7, {0, {0}}, 0, 0 },
 232   { "gr8", 8, {0, {0}}, 0, 0 },
 233   { "gr9", 9, {0, {0}}, 0, 0 },
 234   { "gr10", 10, {0, {0}}, 0, 0 },
 235   { "gr11", 11, {0, {0}}, 0, 0 },
 236   { "gr12", 12, {0, {0}}, 0, 0 },
 237   { "gr13", 13, {0, {0}}, 0, 0 },
 238   { "gr14", 14, {0, {0}}, 0, 0 },
 239   { "gr15", 15, {0, {0}}, 0, 0 },
 240   { "gr16", 16, {0, {0}}, 0, 0 },
 241   { "gr17", 17, {0, {0}}, 0, 0 },
 242   { "gr18", 18, {0, {0}}, 0, 0 },
 243   { "gr19", 19, {0, {0}}, 0, 0 },
 244   { "gr20", 20, {0, {0}}, 0, 0 },
 245   { "gr21", 21, {0, {0}}, 0, 0 },
 246   { "gr22", 22, {0, {0}}, 0, 0 },
 247   { "gr23", 23, {0, {0}}, 0, 0 },
 248   { "gr24", 24, {0, {0}}, 0, 0 },
 249   { "gr25", 25, {0, {0}}, 0, 0 },
 250   { "gr26", 26, {0, {0}}, 0, 0 },
 251   { "gr27", 27, {0, {0}}, 0, 0 },
 252   { "gr28", 28, {0, {0}}, 0, 0 },
 253   { "gr29", 29, {0, {0}}, 0, 0 },
 254   { "gr30", 30, {0, {0}}, 0, 0 },
 255   { "gr31", 31, {0, {0}}, 0, 0 },
 256   { "gr32", 32, {0, {0}}, 0, 0 },
 257   { "gr33", 33, {0, {0}}, 0, 0 },
 258   { "gr34", 34, {0, {0}}, 0, 0 },
 259   { "gr35", 35, {0, {0}}, 0, 0 },
 260   { "gr36", 36, {0, {0}}, 0, 0 },
 261   { "gr37", 37, {0, {0}}, 0, 0 },
 262   { "gr38", 38, {0, {0}}, 0, 0 },
 263   { "gr39", 39, {0, {0}}, 0, 0 },
 264   { "gr40", 40, {0, {0}}, 0, 0 },
 265   { "gr41", 41, {0, {0}}, 0, 0 },
 266   { "gr42", 42, {0, {0}}, 0, 0 },
 267   { "gr43", 43, {0, {0}}, 0, 0 },
 268   { "gr44", 44, {0, {0}}, 0, 0 },
 269   { "gr45", 45, {0, {0}}, 0, 0 },
 270   { "gr46", 46, {0, {0}}, 0, 0 },
 271   { "gr47", 47, {0, {0}}, 0, 0 },
 272   { "gr48", 48, {0, {0}}, 0, 0 },
 273   { "gr49", 49, {0, {0}}, 0, 0 },
 274   { "gr50", 50, {0, {0}}, 0, 0 },
 275   { "gr51", 51, {0, {0}}, 0, 0 },
 276   { "gr52", 52, {0, {0}}, 0, 0 },
 277   { "gr53", 53, {0, {0}}, 0, 0 },
 278   { "gr54", 54, {0, {0}}, 0, 0 },
 279   { "gr55", 55, {0, {0}}, 0, 0 },
 280   { "gr56", 56, {0, {0}}, 0, 0 },
 281   { "gr57", 57, {0, {0}}, 0, 0 },
 282   { "gr58", 58, {0, {0}}, 0, 0 },
 283   { "gr59", 59, {0, {0}}, 0, 0 },
 284   { "gr60", 60, {0, {0}}, 0, 0 },
 285   { "gr61", 61, {0, {0}}, 0, 0 },
 286   { "gr62", 62, {0, {0}}, 0, 0 },
 287   { "gr63", 63, {0, {0}}, 0, 0 }
 288 };
 289
 290 CGEN_KEYWORD frv_cgen_opval_gr_names =
 291 {
 292   & frv_cgen_opval_gr_names_entries[0],
 293   66,
 294   0, 0, 0, 0, ""
 295 };
 296
 297 static CGEN_KEYWORD_ENTRY frv_cgen_opval_fr_names_entries[] =
 298 {
 299   { "fr0", 0, {0, {0}}, 0, 0 },
 300   { "fr1", 1, {0, {0}}, 0, 0 },
 301   { "fr2", 2, {0, {0}}, 0, 0 },
 302   { "fr3", 3, {0, {0}}, 0, 0 },
 303   { "fr4", 4, {0, {0}}, 0, 0 },
 304   { "fr5", 5, {0, {0}}, 0, 0 },
 305   { "fr6", 6, {0, {0}}, 0, 0 },
 306   { "fr7", 7, {0, {0}}, 0, 0 },
 307   { "fr8", 8, {0, {0}}, 0, 0 },
 308   { "fr9", 9, {0, {0}}, 0, 0 },
 309   { "fr10", 10, {0, {0}}, 0, 0 },
 310   { "fr11", 11, {0, {0}}, 0, 0 },
 311   { "fr12", 12, {0, {0}}, 0, 0 },
 312   { "fr13", 13, {0, {0}}, 0, 0 },
 313   { "fr14", 14, {0, {0}}, 0, 0 },
 314   { "fr15", 15, {0, {0}}, 0, 0 },
 315   { "fr16", 16, {0, {0}}, 0, 0 },
 316   { "fr17", 17, {0, {0}}, 0, 0 },
 317   { "fr18", 18, {0, {0}}, 0, 0 },
 318   { "fr19", 19, {0, {0}}, 0, 0 },
 319   { "fr20", 20, {0, {0}}, 0, 0 },
 320   { "fr21", 21, {0, {0}}, 0, 0 },
 321   { "fr22", 22, {0, {0}}, 0, 0 },
 322   { "fr23", 23, {0, {0}}, 0, 0 },
 323   { "fr24", 24, {0, {0}}, 0, 0 },
 324   { "fr25", 25, {0, {0}}, 0, 0 },
 325   { "fr26", 26, {0, {0}}, 0, 0 },
 326   { "fr27", 27, {0, {0}}, 0, 0 },
 327   { "fr28", 28, {0, {0}}, 0, 0 },
 328   { "fr29", 29, {0, {0}}, 0, 0 },
 329   { "fr30", 30, {0, {0}}, 0, 0 },
 330   { "fr31", 31, {0, {0}}, 0, 0 },
 331   { "fr32", 32, {0, {0}}, 0, 0 },
 332   { "fr33", 33, {0, {0}}, 0, 0 },
 333   { "fr34", 34, {0, {0}}, 0, 0 },
 334   { "fr35", 35, {0, {0}}, 0, 0 },
 335   { "fr36", 36, {0, {0}}, 0, 0 },
 336   { "fr37", 37, {0, {0}}, 0, 0 },
 337   { "fr38", 38, {0, {0}}, 0, 0 },
 338   { "fr39", 39, {0, {0}}, 0, 0 },
 339   { "fr40", 40, {0, {0}}, 0, 0 },
 340   { "fr41", 41, {0, {0}}, 0, 0 },
 341   { "fr42", 42, {0, {0}}, 0, 0 },
 342   { "fr43", 43, {0, {0}}, 0, 0 },
 343   { "fr44", 44, {0, {0}}, 0, 0 },
 344   { "fr45", 45, {0, {0}}, 0, 0 },
 345   { "fr46", 46, {0, {0}}, 0, 0 },
 346   { "fr47", 47, {0, {0}}, 0, 0 },
 347   { "fr48", 48, {0, {0}}, 0, 0 },
 348   { "fr49", 49, {0, {0}}, 0, 0 },
 349   { "fr50", 50, {0, {0}}, 0, 0 },
 350   { "fr51", 51, {0, {0}}, 0, 0 },
 351   { "fr52", 52, {0, {0}}, 0, 0 },
 352   { "fr53", 53, {0, {0}}, 0, 0 },
 353   { "fr54", 54, {0, {0}}, 0, 0 },
 354   { "fr55", 55, {0, {0}}, 0, 0 },
 355   { "fr56", 56, {0, {0}}, 0, 0 },
 356   { "fr57", 57, {0, {0}}, 0, 0 },
 357   { "fr58", 58, {0, {0}}, 0, 0 },
 358   { "fr59", 59, {0, {0}}, 0, 0 },
 359   { "fr60", 60, {0, {0}}, 0, 0 },
 360   { "fr61", 61, {0, {0}}, 0, 0 },
 361   { "fr62", 62, {0, {0}}, 0, 0 },
 362   { "fr63", 63, {0, {0}}, 0, 0 }
 363 };
 364
 365 CGEN_KEYWORD frv_cgen_opval_fr_names =
 366 {
 367   & frv_cgen_opval_fr_names_entries[0],
 368   64,
 369   0, 0, 0, 0, ""
 370 };
 371
 372 static CGEN_KEYWORD_ENTRY frv_cgen_opval_cpr_names_entries[] =
 373 {
 374   { "cpr0", 0, {0, {0}}, 0, 0 },
 375   { "cpr1", 1, {0, {0}}, 0, 0 },
 376   { "cpr2", 2, {0, {0}}, 0, 0 },
 377   { "cpr3", 3, {0, {0}}, 0, 0 },
 378   { "cpr4", 4, {0, {0}}, 0, 0 },
 379   { "cpr5", 5, {0, {0}}, 0, 0 },
 380   { "cpr6", 6, {0, {0}}, 0, 0 },
 381   { "cpr7", 7, {0, {0}}, 0, 0 },
 382   { "cpr8", 8, {0, {0}}, 0, 0 },
 383   { "cpr9", 9, {0, {0}}, 0, 0 },
 384   { "cpr10", 10, {0, {0}}, 0, 0 },
 385   { "cpr11", 11, {0, {0}}, 0, 0 },
 386   { "cpr12", 12, {0, {0}}, 0, 0 },
 387   { "cpr13", 13, {0, {0}}, 0, 0 },
 388   { "cpr14", 14, {0, {0}}, 0, 0 },
 389   { "cpr15", 15, {0, {0}}, 0, 0 },
 390   { "cpr16", 16, {0, {0}}, 0, 0 },
 391   { "cpr17", 17, {0, {0}}, 0, 0 },
 392   { "cpr18", 18, {0, {0}}, 0, 0 },
 393   { "cpr19", 19, {0, {0}}, 0, 0 },
 394   { "cpr20", 20, {0, {0}}, 0, 0 },
 395   { "cpr21", 21, {0, {0}}, 0, 0 },
 396   { "cpr22", 22, {0, {0}}, 0, 0 },
 397   { "cpr23", 23, {0, {0}}, 0, 0 },
 398   { "cpr24", 24, {0, {0}}, 0, 0 },
 399   { "cpr25", 25, {0, {0}}, 0, 0 },
 400   { "cpr26", 26, {0, {0}}, 0, 0 },
 401   { "cpr27", 27, {0, {0}}, 0, 0 },
 402   { "cpr28", 28, {0, {0}}, 0, 0 },
 403   { "cpr29", 29, {0, {0}}, 0, 0 },
 404   { "cpr30", 30, {0, {0}}, 0, 0 },
 405   { "cpr31", 31, {0, {0}}, 0, 0 },
 406   { "cpr32", 32, {0, {0}}, 0, 0 },
 407   { "cpr33", 33, {0, {0}}, 0, 0 },
 408   { "cpr34", 34, {0, {0}}, 0, 0 },
 409   { "cpr35", 35, {0, {0}}, 0, 0 },
 410   { "cpr36", 36, {0, {0}}, 0, 0 },
 411   { "cpr37", 37, {0, {0}}, 0, 0 },
 412   { "cpr38", 38, {0, {0}}, 0, 0 },
 413   { "cpr39", 39, {0, {0}}, 0, 0 },
 414   { "cpr40", 40, {0, {0}}, 0, 0 },
 415   { "cpr41", 41, {0, {0}}, 0, 0 },
 416   { "cpr42", 42, {0, {0}}, 0, 0 },
 417   { "cpr43", 43, {0, {0}}, 0, 0 },
 418   { "cpr44", 44, {0, {0}}, 0, 0 },
 419   { "cpr45", 45, {0, {0}}, 0, 0 },
 420   { "cpr46", 46, {0, {0}}, 0, 0 },
 421   { "cpr47", 47, {0, {0}}, 0, 0 },
 422   { "cpr48", 48, {0, {0}}, 0, 0 },
 423   { "cpr49", 49, {0, {0}}, 0, 0 },
 424   { "cpr50", 50, {0, {0}}, 0, 0 },
 425   { "cpr51", 51, {0, {0}}, 0, 0 },
 426   { "cpr52", 52, {0, {0}}, 0, 0 },
 427   { "cpr53", 53, {0, {0}}, 0, 0 },
 428   { "cpr54", 54, {0, {0}}, 0, 0 },
 429   { "cpr55", 55, {0, {0}}, 0, 0 },
 430   { "cpr56", 56, {0, {0}}, 0, 0 },
 431   { "cpr57", 57, {0, {0}}, 0, 0 },
 432   { "cpr58", 58, {0, {0}}, 0, 0 },
 433   { "cpr59", 59, {0, {0}}, 0, 0 },
 434   { "cpr60", 60, {0, {0}}, 0, 0 },
 435   { "cpr61", 61, {0, {0}}, 0, 0 },
 436   { "cpr62", 62, {0, {0}}, 0, 0 },
 437   { "cpr63", 63, {0, {0}}, 0, 0 }
 438 };
 439
 440 CGEN_KEYWORD frv_cgen_opval_cpr_names =
 441 {
 442   & frv_cgen_opval_cpr_names_entries[0],
 443   64,
 444   0, 0, 0, 0, ""
 445 };
 446
 447 static CGEN_KEYWORD_ENTRY frv_cgen_opval_spr_names_entries[] =
 448 {
 449   { "psr", 0, {0, {0}}, 0, 0 },
 450   { "pcsr", 1, {0, {0}}, 0, 0 },
 451   { "bpcsr", 2, {0, {0}}, 0, 0 },
 452   { "tbr", 3, {0, {0}}, 0, 0 },
 453   { "bpsr", 4, {0, {0}}, 0, 0 },
 454   { "hsr0", 16, {0, {0}}, 0, 0 },
 455   { "hsr1", 17, {0, {0}}, 0, 0 },
 456   { "hsr2", 18, {0, {0}}, 0, 0 },
 457   { "hsr3", 19, {0, {0}}, 0, 0 },
 458   { "hsr4", 20, {0, {0}}, 0, 0 },
 459   { "hsr5", 21, {0, {0}}, 0, 0 },
 460   { "hsr6", 22, {0, {0}}, 0, 0 },
 461   { "hsr7", 23, {0, {0}}, 0, 0 },
 462   { "hsr8", 24, {0, {0}}, 0, 0 },
 463   { "hsr9", 25, {0, {0}}, 0, 0 },
 464   { "hsr10", 26, {0, {0}}, 0, 0 },
 465   { "hsr11", 27, {0, {0}}, 0, 0 },
 466   { "hsr12", 28, {0, {0}}, 0, 0 },
 467   { "hsr13", 29, {0, {0}}, 0, 0 },
 468   { "hsr14", 30, {0, {0}}, 0, 0 },
 469   { "hsr15", 31, {0, {0}}, 0, 0 },
 470   { "hsr16", 32, {0, {0}}, 0, 0 },
 471   { "hsr17", 33, {0, {0}}, 0, 0 },
 472   { "hsr18", 34, {0, {0}}, 0, 0 },
 473   { "hsr19", 35, {0, {0}}, 0, 0 },
 474   { "hsr20", 36, {0, {0}}, 0, 0 },
 475   { "hsr21", 37, {0, {0}}, 0, 0 },
 476   { "hsr22", 38, {0, {0}}, 0, 0 },
 477   { "hsr23", 39, {0, {0}}, 0, 0 },
 478   { "hsr24", 40, {0, {0}}, 0, 0 },
 479   { "hsr25", 41, {0, {0}}, 0, 0 },
 480   { "hsr26", 42, {0, {0}}, 0, 0 },
 481   { "hsr27", 43, {0, {0}}, 0, 0 },
 482   { "hsr28", 44, {0, {0}}, 0, 0 },
 483   { "hsr29", 45, {0, {0}}, 0, 0 },
 484   { "hsr30", 46, {0, {0}}, 0, 0 },
 485   { "hsr31", 47, {0, {0}}, 0, 0 },
 486   { "hsr32", 48, {0, {0}}, 0, 0 },
 487   { "hsr33", 49, {0, {0}}, 0, 0 },
 488   { "hsr34", 50, {0, {0}}, 0, 0 },
 489   { "hsr35", 51, {0, {0}}, 0, 0 },
 490   { "hsr36", 52, {0, {0}}, 0, 0 },
 491   { "hsr37", 53, {0, {0}}, 0, 0 },
 492   { "hsr38", 54, {0, {0}}, 0, 0 },
 493   { "hsr39", 55, {0, {0}}, 0, 0 },
 494   { "hsr40", 56, {0, {0}}, 0, 0 },
 495   { "hsr41", 57, {0, {0}}, 0, 0 },
 496   { "hsr42", 58, {0, {0}}, 0, 0 },
 497   { "hsr43", 59, {0, {0}}, 0, 0 },
 498   { "hsr44", 60, {0, {0}}, 0, 0 },
 499   { "hsr45", 61, {0, {0}}, 0, 0 },
 500   { "hsr46", 62, {0, {0}}, 0, 0 },
 501   { "hsr47", 63, {0, {0}}, 0, 0 },
 502   { "hsr48", 64, {0, {0}}, 0, 0 },
 503   { "hsr49", 65, {0, {0}}, 0, 0 },
 504   { "hsr50", 66, {0, {0}}, 0, 0 },
 505   { "hsr51", 67, {0, {0}}, 0, 0 },
 506   { "hsr52", 68, {0, {0}}, 0, 0 },
 507   { "hsr53", 69, {0, {0}}, 0, 0 },
 508   { "hsr54", 70, {0, {0}}, 0, 0 },
 509   { "hsr55", 71, {0, {0}}, 0, 0 },
 510   { "hsr56", 72, {0, {0}}, 0, 0 },
 511   { "hsr57", 73, {0, {0}}, 0, 0 },
 512   { "hsr58", 74, {0, {0}}, 0, 0 },
 513   { "hsr59", 75, {0, {0}}, 0, 0 },
 514   { "hsr60", 76, {0, {0}}, 0, 0 },
 515   { "hsr61", 77, {0, {0}}, 0, 0 },
 516   { "hsr62", 78, {0, {0}}, 0, 0 },
 517   { "hsr63", 79, {0, {0}}, 0, 0 },
 518   { "ccr", 256, {0, {0}}, 0, 0 },
 519   { "cccr", 263, {0, {0}}, 0, 0 },
 520   { "lr", 272, {0, {0}}, 0, 0 },
 521   { "lcr", 273, {0, {0}}, 0, 0 },
 522   { "isr", 288, {0, {0}}, 0, 0 },
 523   { "neear0", 352, {0, {0}}, 0, 0 },
 524   { "neear1", 353, {0, {0}}, 0, 0 },
 525   { "neear2", 354, {0, {0}}, 0, 0 },
 526   { "neear3", 355, {0, {0}}, 0, 0 },
 527   { "neear4", 356, {0, {0}}, 0, 0 },
 528   { "neear5", 357, {0, {0}}, 0, 0 },
 529   { "neear6", 358, {0, {0}}, 0, 0 },
 530   { "neear7", 359, {0, {0}}, 0, 0 },
 531   { "neear8", 360, {0, {0}}, 0, 0 },
 532   { "neear9", 361, {0, {0}}, 0, 0 },
 533   { "neear10", 362, {0, {0}}, 0, 0 },
 534   { "neear11", 363, {0, {0}}, 0, 0 },
 535   { "neear12", 364, {0, {0}}, 0, 0 },
 536   { "neear13", 365, {0, {0}}, 0, 0 },
 537   { "neear14", 366, {0, {0}}, 0, 0 },
 538   { "neear15", 367, {0, {0}}, 0, 0 },
 539   { "neear16", 368, {0, {0}}, 0, 0 },
 540   { "neear17", 369, {0, {0}}, 0, 0 },
 541   { "neear18", 370, {0, {0}}, 0, 0 },
 542   { "neear19", 371, {0, {0}}, 0, 0 },
 543   { "neear20", 372, {0, {0}}, 0, 0 },
 544   { "neear21", 373, {0, {0}}, 0, 0 },
 545   { "neear22", 374, {0, {0}}, 0, 0 },
 546   { "neear23", 375, {0, {0}}, 0, 0 },
 547   { "neear24", 376, {0, {0}}, 0, 0 },
 548   { "neear25", 377, {0, {0}}, 0, 0 },
 549   { "neear26", 378, {0, {0}}, 0, 0 },
 550   { "neear27", 379, {0, {0}}, 0, 0 },
 551   { "neear28", 380, {0, {0}}, 0, 0 },
 552   { "neear29", 381, {0, {0}}, 0, 0 },
 553   { "neear30", 382, {0, {0}}, 0, 0 },
 554   { "neear31", 383, {0, {0}}, 0, 0 },
 555   { "nesr0", 384, {0, {0}}, 0, 0 },
 556   { "nesr1", 385, {0, {0}}, 0, 0 },
 557   { "nesr2", 386, {0, {0}}, 0, 0 },
 558   { "nesr3", 387, {0, {0}}, 0, 0 },
 559   { "nesr4", 388, {0, {0}}, 0, 0 },
 560   { "nesr5", 389, {0, {0}}, 0, 0 },
 561   { "nesr6", 390, {0, {0}}, 0, 0 },
 562   { "nesr7", 391, {0, {0}}, 0, 0 },
 563   { "nesr8", 392, {0, {0}}, 0, 0 },
 564   { "nesr9", 393, {0, {0}}, 0, 0 },
 565   { "nesr10", 394, {0, {0}}, 0, 0 },
 566   { "nesr11", 395, {0, {0}}, 0, 0 },
 567   { "nesr12", 396, {0, {0}}, 0, 0 },
 568   { "nesr13", 397, {0, {0}}, 0, 0 },
 569   { "nesr14", 398, {0, {0}}, 0, 0 },
 570   { "nesr15", 399, {0, {0}}, 0, 0 },
 571   { "nesr16", 400, {0, {0}}, 0, 0 },
 572   { "nesr17", 401, {0, {0}}, 0, 0 },
 573   { "nesr18", 402, {0, {0}}, 0, 0 },
 574   { "nesr19", 403, {0, {0}}, 0, 0 },
 575   { "nesr20", 404, {0, {0}}, 0, 0 },
 576   { "nesr21", 405, {0, {0}}, 0, 0 },
 577   { "nesr22", 406, {0, {0}}, 0, 0 },
 578   { "nesr23", 407, {0, {0}}, 0, 0 },
 579   { "nesr24", 408, {0, {0}}, 0, 0 },
 580   { "nesr25", 409, {0, {0}}, 0, 0 },
 581   { "nesr26", 410, {0, {0}}, 0, 0 },
 582   { "nesr27", 411, {0, {0}}, 0, 0 },
 583   { "nesr28", 412, {0, {0}}, 0, 0 },
 584   { "nesr29", 413, {0, {0}}, 0, 0 },
 585   { "nesr30", 414, {0, {0}}, 0, 0 },
 586   { "nesr31", 415, {0, {0}}, 0, 0 },
 587   { "necr", 416, {0, {0}}, 0, 0 },
 588   { "gner0", 432, {0, {0}}, 0, 0 },
 589   { "gner1", 433, {0, {0}}, 0, 0 },
 590   { "fner0", 434, {0, {0}}, 0, 0 },
 591   { "fner1", 435, {0, {0}}, 0, 0 },
 592   { "epcr0", 512, {0, {0}}, 0, 0 },
 593   { "epcr1", 513, {0, {0}}, 0, 0 },
 594   { "epcr2", 514, {0, {0}}, 0, 0 },
 595   { "epcr3", 515, {0, {0}}, 0, 0 },
 596   { "epcr4", 516, {0, {0}}, 0, 0 },
 597   { "epcr5", 517, {0, {0}}, 0, 0 },
 598   { "epcr6", 518, {0, {0}}, 0, 0 },
 599   { "epcr7", 519, {0, {0}}, 0, 0 },
 600   { "epcr8", 520, {0, {0}}, 0, 0 },
 601   { "epcr9", 521, {0, {0}}, 0, 0 },
 602   { "epcr10", 522, {0, {0}}, 0, 0 },
 603   { "epcr11", 523, {0, {0}}, 0, 0 },
 604   { "epcr12", 524, {0, {0}}, 0, 0 },
 605   { "epcr13", 525, {0, {0}}, 0, 0 },
 606   { "epcr14", 526, {0, {0}}, 0, 0 },
 607   { "epcr15", 527, {0, {0}}, 0, 0 },
 608   { "epcr16", 528, {0, {0}}, 0, 0 },
 609   { "epcr17", 529, {0, {0}}, 0, 0 },
 610   { "epcr18", 530, {0, {0}}, 0, 0 },
 611   { "epcr19", 531, {0, {0}}, 0, 0 },
 612   { "epcr20", 532, {0, {0}}, 0, 0 },
 613   { "epcr21", 533, {0, {0}}, 0, 0 },
 614   { "epcr22", 534, {0, {0}}, 0, 0 },
 615   { "epcr23", 535, {0, {0}}, 0, 0 },
 616   { "epcr24", 536, {0, {0}}, 0, 0 },
 617   { "epcr25", 537, {0, {0}}, 0, 0 },
 618   { "epcr26", 538, {0, {0}}, 0, 0 },
 619   { "epcr27", 539, {0, {0}}, 0, 0 },
 620   { "epcr28", 540, {0, {0}}, 0, 0 },
 621   { "epcr29", 541, {0, {0}}, 0, 0 },
 622   { "epcr30", 542, {0, {0}}, 0, 0 },
 623   { "epcr31", 543, {0, {0}}, 0, 0 },
 624   { "epcr32", 544, {0, {0}}, 0, 0 },
 625   { "epcr33", 545, {0, {0}}, 0, 0 },
 626   { "epcr34", 546, {0, {0}}, 0, 0 },
 627   { "epcr35", 547, {0, {0}}, 0, 0 },
 628   { "epcr36", 548, {0, {0}}, 0, 0 },
 629   { "epcr37", 549, {0, {0}}, 0, 0 },
 630   { "epcr38", 550, {0, {0}}, 0, 0 },
 631   { "epcr39", 551, {0, {0}}, 0, 0 },
 632   { "epcr40", 552, {0, {0}}, 0, 0 },
 633   { "epcr41", 553, {0, {0}}, 0, 0 },
 634   { "epcr42", 554, {0, {0}}, 0, 0 },
 635   { "epcr43", 555, {0, {0}}, 0, 0 },
 636   { "epcr44", 556, {0, {0}}, 0, 0 },
 637   { "epcr45", 557, {0, {0}}, 0, 0 },
 638   { "epcr46", 558, {0, {0}}, 0, 0 },
 639   { "epcr47", 559, {0, {0}}, 0, 0 },
 640   { "epcr48", 560, {0, {0}}, 0, 0 },
 641   { "epcr49", 561, {0, {0}}, 0, 0 },
 642   { "epcr50", 562, {0, {0}}, 0, 0 },
 643   { "epcr51", 563, {0, {0}}, 0, 0 },
 644   { "epcr52", 564, {0, {0}}, 0, 0 },
 645   { "epcr53", 565, {0, {0}}, 0, 0 },
 646   { "epcr54", 566, {0, {0}}, 0, 0 },
 647   { "epcr55", 567, {0, {0}}, 0, 0 },
 648   { "epcr56", 568, {0, {0}}, 0, 0 },
 649   { "epcr57", 569, {0, {0}}, 0, 0 },
 650   { "epcr58", 570, {0, {0}}, 0, 0 },
 651   { "epcr59", 571, {0, {0}}, 0, 0 },
 652   { "epcr60", 572, {0, {0}}, 0, 0 },
 653   { "epcr61", 573, {0, {0}}, 0, 0 },
 654   { "epcr62", 574, {0, {0}}, 0, 0 },
 655   { "epcr63", 575, {0, {0}}, 0, 0 },
 656   { "esr0", 576, {0, {0}}, 0, 0 },
 657   { "esr1", 577, {0, {0}}, 0, 0 },
 658   { "esr2", 578, {0, {0}}, 0, 0 },
 659   { "esr3", 579, {0, {0}}, 0, 0 },
 660   { "esr4", 580, {0, {0}}, 0, 0 },
 661   { "esr5", 581, {0, {0}}, 0, 0 },
 662   { "esr6", 582, {0, {0}}, 0, 0 },
 663   { "esr7", 583, {0, {0}}, 0, 0 },
 664   { "esr8", 584, {0, {0}}, 0, 0 },
 665   { "esr9", 585, {0, {0}}, 0, 0 },
 666   { "esr10", 586, {0, {0}}, 0, 0 },
 667   { "esr11", 587, {0, {0}}, 0, 0 },
 668   { "esr12", 588, {0, {0}}, 0, 0 },
 669   { "esr13", 589, {0, {0}}, 0, 0 },
 670   { "esr14", 590, {0, {0}}, 0, 0 },
 671   { "esr15", 591, {0, {0}}, 0, 0 },
 672   { "esr16", 592, {0, {0}}, 0, 0 },
 673   { "esr17", 593, {0, {0}}, 0, 0 },
 674   { "esr18", 594, {0, {0}}, 0, 0 },
 675   { "esr19", 595, {0, {0}}, 0, 0 },
 676   { "esr20", 596, {0, {0}}, 0, 0 },
 677   { "esr21", 597, {0, {0}}, 0, 0 },
 678   { "esr22", 598, {0, {0}}, 0, 0 },
 679   { "esr23", 599, {0, {0}}, 0, 0 },
 680   { "esr24", 600, {0, {0}}, 0, 0 },
 681   { "esr25", 601, {0, {0}}, 0, 0 },
 682   { "esr26", 602, {0, {0}}, 0, 0 },
 683   { "esr27", 603, {0, {0}}, 0, 0 },
 684   { "esr28", 604, {0, {0}}, 0, 0 },
 685   { "esr29", 605, {0, {0}}, 0, 0 },
 686   { "esr30", 606, {0, {0}}, 0, 0 },
 687   { "esr31", 607, {0, {0}}, 0, 0 },
 688   { "esr32", 608, {0, {0}}, 0, 0 },
 689   { "esr33", 609, {0, {0}}, 0, 0 },
 690   { "esr34", 610, {0, {0}}, 0, 0 },
 691   { "esr35", 611, {0, {0}}, 0, 0 },
 692   { "esr36", 612, {0, {0}}, 0, 0 },
 693   { "esr37", 613, {0, {0}}, 0, 0 },
 694   { "esr38", 614, {0, {0}}, 0, 0 },
 695   { "esr39", 615, {0, {0}}, 0, 0 },
 696   { "esr40", 616, {0, {0}}, 0, 0 },
 697   { "esr41", 617, {0, {0}}, 0, 0 },
 698   { "esr42", 618, {0, {0}}, 0, 0 },
 699   { "esr43", 619, {0, {0}}, 0, 0 },
 700   { "esr44", 620, {0, {0}}, 0, 0 },
 701   { "esr45", 621, {0, {0}}, 0, 0 },
 702   { "esr46", 622, {0, {0}}, 0, 0 },
 703   { "esr47", 623, {0, {0}}, 0, 0 },
 704   { "esr48", 624, {0, {0}}, 0, 0 },
 705   { "esr49", 625, {0, {0}}, 0, 0 },
 706   { "esr50", 626, {0, {0}}, 0, 0 },
 707   { "esr51", 627, {0, {0}}, 0, 0 },
 708   { "esr52", 628, {0, {0}}, 0, 0 },
 709   { "esr53", 629, {0, {0}}, 0, 0 },
 710   { "esr54", 630, {0, {0}}, 0, 0 },
 711   { "esr55", 631, {0, {0}}, 0, 0 },
 712   { "esr56", 632, {0, {0}}, 0, 0 },
 713   { "esr57", 633, {0, {0}}, 0, 0 },
 714   { "esr58", 634, {0, {0}}, 0, 0 },
 715   { "esr59", 635, {0, {0}}, 0, 0 },
 716   { "esr60", 636, {0, {0}}, 0, 0 },
 717   { "esr61", 637, {0, {0}}, 0, 0 },
 718   { "esr62", 638, {0, {0}}, 0, 0 },
 719   { "esr63", 639, {0, {0}}, 0, 0 },
 720   { "eir0", 640, {0, {0}}, 0, 0 },
 721   { "eir1", 641, {0, {0}}, 0, 0 },
 722   { "eir2", 642, {0, {0}}, 0, 0 },
 723   { "eir3", 643, {0, {0}}, 0, 0 },
 724   { "eir4", 644, {0, {0}}, 0, 0 },
 725   { "eir5", 645, {0, {0}}, 0, 0 },
 726   { "eir6", 646, {0, {0}}, 0, 0 },
 727   { "eir7", 647, {0, {0}}, 0, 0 },
 728   { "eir8", 648, {0, {0}}, 0, 0 },
 729   { "eir9", 649, {0, {0}}, 0, 0 },
 730   { "eir10", 650, {0, {0}}, 0, 0 },
 731   { "eir11", 651, {0, {0}}, 0, 0 },
 732   { "eir12", 652, {0, {0}}, 0, 0 },
 733   { "eir13", 653, {0, {0}}, 0, 0 },
 734   { "eir14", 654, {0, {0}}, 0, 0 },
 735   { "eir15", 655, {0, {0}}, 0, 0 },
 736   { "eir16", 656, {0, {0}}, 0, 0 },
 737   { "eir17", 657, {0, {0}}, 0, 0 },
 738   { "eir18", 658, {0, {0}}, 0, 0 },
 739   { "eir19", 659, {0, {0}}, 0, 0 },
 740   { "eir20", 660, {0, {0}}, 0, 0 },
 741   { "eir21", 661, {0, {0}}, 0, 0 },
 742   { "eir22", 662, {0, {0}}, 0, 0 },
 743   { "eir23", 663, {0, {0}}, 0, 0 },
 744   { "eir24", 664, {0, {0}}, 0, 0 },
 745   { "eir25", 665, {0, {0}}, 0, 0 },
 746   { "eir26", 666, {0, {0}}, 0, 0 },
 747   { "eir27", 667, {0, {0}}, 0, 0 },
 748   { "eir28", 668, {0, {0}}, 0, 0 },
 749   { "eir29", 669, {0, {0}}, 0, 0 },
 750   { "eir30", 670, {0, {0}}, 0, 0 },
 751   { "eir31", 671, {0, {0}}, 0, 0 },
 752   { "esfr0", 672, {0, {0}}, 0, 0 },
 753   { "esfr1", 673, {0, {0}}, 0, 0 },
 754   { "sr0", 768, {0, {0}}, 0, 0 },
 755   { "sr1", 769, {0, {0}}, 0, 0 },
 756   { "sr2", 770, {0, {0}}, 0, 0 },
 757   { "sr3", 771, {0, {0}}, 0, 0 },
 758   { "fsr0", 1024, {0, {0}}, 0, 0 },
 759   { "fsr1", 1025, {0, {0}}, 0, 0 },
 760   { "fsr2", 1026, {0, {0}}, 0, 0 },
 761   { "fsr3", 1027, {0, {0}}, 0, 0 },
 762   { "fsr4", 1028, {0, {0}}, 0, 0 },
 763   { "fsr5", 1029, {0, {0}}, 0, 0 },
 764   { "fsr6", 1030, {0, {0}}, 0, 0 },
 765   { "fsr7", 1031, {0, {0}}, 0, 0 },
 766   { "fsr8", 1032, {0, {0}}, 0, 0 },
 767   { "fsr9", 1033, {0, {0}}, 0, 0 },
 768   { "fsr10", 1034, {0, {0}}, 0, 0 },
 769   { "fsr11", 1035, {0, {0}}, 0, 0 },
 770   { "fsr12", 1036, {0, {0}}, 0, 0 },
 771   { "fsr13", 1037, {0, {0}}, 0, 0 },
 772   { "fsr14", 1038, {0, {0}}, 0, 0 },
 773   { "fsr15", 1039, {0, {0}}, 0, 0 },
 774   { "fsr16", 1040, {0, {0}}, 0, 0 },
 775   { "fsr17", 1041, {0, {0}}, 0, 0 },
 776   { "fsr18", 1042, {0, {0}}, 0, 0 },
 777   { "fsr19", 1043, {0, {0}}, 0, 0 },
 778   { "fsr20", 1044, {0, {0}}, 0, 0 },
 779   { "fsr21", 1045, {0, {0}}, 0, 0 },
 780   { "fsr22", 1046, {0, {0}}, 0, 0 },
 781   { "fsr23", 1047, {0, {0}}, 0, 0 },
 782   { "fsr24", 1048, {0, {0}}, 0, 0 },
 783   { "fsr25", 1049, {0, {0}}, 0, 0 },
 784   { "fsr26", 1050, {0, {0}}, 0, 0 },
 785   { "fsr27", 1051, {0, {0}}, 0, 0 },
 786   { "fsr28", 1052, {0, {0}}, 0, 0 },
 787   { "fsr29", 1053, {0, {0}}, 0, 0 },
 788   { "fsr30", 1054, {0, {0}}, 0, 0 },
 789   { "fsr31", 1055, {0, {0}}, 0, 0 },
 790   { "fsr32", 1056, {0, {0}}, 0, 0 },
 791   { "fsr33", 1057, {0, {0}}, 0, 0 },
 792   { "fsr34", 1058, {0, {0}}, 0, 0 },
 793   { "fsr35", 1059, {0, {0}}, 0, 0 },
 794   { "fsr36", 1060, {0, {0}}, 0, 0 },
 795   { "fsr37", 1061, {0, {0}}, 0, 0 },
 796   { "fsr38", 1062, {0, {0}}, 0, 0 },
 797   { "fsr39", 1063, {0, {0}}, 0, 0 },
 798   { "fsr40", 1064, {0, {0}}, 0, 0 },
 799   { "fsr41", 1065, {0, {0}}, 0, 0 },
 800   { "fsr42", 1066, {0, {0}}, 0, 0 },
 801   { "fsr43", 1067, {0, {0}}, 0, 0 },
 802   { "fsr44", 1068, {0, {0}}, 0, 0 },
 803   { "fsr45", 1069, {0, {0}}, 0, 0 },
 804   { "fsr46", 1070, {0, {0}}, 0, 0 },
 805   { "fsr47", 1071, {0, {0}}, 0, 0 },
 806   { "fsr48", 1072, {0, {0}}, 0, 0 },
 807   { "fsr49", 1073, {0, {0}}, 0, 0 },
 808   { "fsr50", 1074, {0, {0}}, 0, 0 },
 809   { "fsr51", 1075, {0, {0}}, 0, 0 },
 810   { "fsr52", 1076, {0, {0}}, 0, 0 },
 811   { "fsr53", 1077, {0, {0}}, 0, 0 },
 812   { "fsr54", 1078, {0, {0}}, 0, 0 },
 813   { "fsr55", 1079, {0, {0}}, 0, 0 },
 814   { "fsr56", 1080, {0, {0}}, 0, 0 },
 815   { "fsr57", 1081, {0, {0}}, 0, 0 },
 816   { "fsr58", 1082, {0, {0}}, 0, 0 },
 817   { "fsr59", 1083, {0, {0}}, 0, 0 },
 818   { "fsr60", 1084, {0, {0}}, 0, 0 },
 819   { "fsr61", 1085, {0, {0}}, 0, 0 },
 820   { "fsr62", 1086, {0, {0}}, 0, 0 },
 821   { "fsr63", 1087, {0, {0}}, 0, 0 },
 822   { "fqop0", 1088, {0, {0}}, 0, 0 },
 823   { "fqop1", 1090, {0, {0}}, 0, 0 },
 824   { "fqop2", 1092, {0, {0}}, 0, 0 },
 825   { "fqop3", 1094, {0, {0}}, 0, 0 },
 826   { "fqop4", 1096, {0, {0}}, 0, 0 },
 827   { "fqop5", 1098, {0, {0}}, 0, 0 },
 828   { "fqop6", 1100, {0, {0}}, 0, 0 },
 829   { "fqop7", 1102, {0, {0}}, 0, 0 },
 830   { "fqop8", 1104, {0, {0}}, 0, 0 },
 831   { "fqop9", 1106, {0, {0}}, 0, 0 },
 832   { "fqop10", 1108, {0, {0}}, 0, 0 },
 833   { "fqop11", 1110, {0, {0}}, 0, 0 },
 834   { "fqop12", 1112, {0, {0}}, 0, 0 },
 835   { "fqop13", 1114, {0, {0}}, 0, 0 },
 836   { "fqop14", 1116, {0, {0}}, 0, 0 },
 837   { "fqop15", 1118, {0, {0}}, 0, 0 },
 838   { "fqop16", 1120, {0, {0}}, 0, 0 },
 839   { "fqop17", 1122, {0, {0}}, 0, 0 },
 840   { "fqop18", 1124, {0, {0}}, 0, 0 },
 841   { "fqop19", 1126, {0, {0}}, 0, 0 },
 842   { "fqop20", 1128, {0, {0}}, 0, 0 },
 843   { "fqop21", 1130, {0, {0}}, 0, 0 },
 844   { "fqop22", 1132, {0, {0}}, 0, 0 },
 845   { "fqop23", 1134, {0, {0}}, 0, 0 },
 846   { "fqop24", 1136, {0, {0}}, 0, 0 },
 847   { "fqop25", 1138, {0, {0}}, 0, 0 },
 848   { "fqop26", 1140, {0, {0}}, 0, 0 },
 849   { "fqop27", 1142, {0, {0}}, 0, 0 },
 850   { "fqop28", 1144, {0, {0}}, 0, 0 },
 851   { "fqop29", 1146, {0, {0}}, 0, 0 },
 852   { "fqop30", 1148, {0, {0}}, 0, 0 },
 853   { "fqop31", 1150, {0, {0}}, 0, 0 },
 854   { "fqst0", 1089, {0, {0}}, 0, 0 },
 855   { "fqst1", 1091, {0, {0}}, 0, 0 },
 856   { "fqst2", 1093, {0, {0}}, 0, 0 },
 857   { "fqst3", 1095, {0, {0}}, 0, 0 },
 858   { "fqst4", 1097, {0, {0}}, 0, 0 },
 859   { "fqst5", 1099, {0, {0}}, 0, 0 },
 860   { "fqst6", 1101, {0, {0}}, 0, 0 },
 861   { "fqst7", 1103, {0, {0}}, 0, 0 },
 862   { "fqst8", 1105, {0, {0}}, 0, 0 },
 863   { "fqst9", 1107, {0, {0}}, 0, 0 },
 864   { "fqst10", 1109, {0, {0}}, 0, 0 },
 865   { "fqst11", 1111, {0, {0}}, 0, 0 },
 866   { "fqst12", 1113, {0, {0}}, 0, 0 },
 867   { "fqst13", 1115, {0, {0}}, 0, 0 },
 868   { "fqst14", 1117, {0, {0}}, 0, 0 },
 869   { "fqst15", 1119, {0, {0}}, 0, 0 },
 870   { "fqst16", 1121, {0, {0}}, 0, 0 },
 871   { "fqst17", 1123, {0, {0}}, 0, 0 },
 872   { "fqst18", 1125, {0, {0}}, 0, 0 },
 873   { "fqst19", 1127, {0, {0}}, 0, 0 },
 874   { "fqst20", 1129, {0, {0}}, 0, 0 },
 875   { "fqst21", 1131, {0, {0}}, 0, 0 },
 876   { "fqst22", 1133, {0, {0}}, 0, 0 },
 877   { "fqst23", 1135, {0, {0}}, 0, 0 },
 878   { "fqst24", 1137, {0, {0}}, 0, 0 },
 879   { "fqst25", 1139, {0, {0}}, 0, 0 },
 880   { "fqst26", 1141, {0, {0}}, 0, 0 },
 881   { "fqst27", 1143, {0, {0}}, 0, 0 },
 882   { "fqst28", 1145, {0, {0}}, 0, 0 },
 883   { "fqst29", 1147, {0, {0}}, 0, 0 },
 884   { "fqst30", 1149, {0, {0}}, 0, 0 },
 885   { "fqst31", 1151, {0, {0}}, 0, 0 },
 886   { "mcilr0", 1272, {0, {0}}, 0, 0 },
 887   { "mcilr1", 1273, {0, {0}}, 0, 0 },
 888   { "msr0", 1280, {0, {0}}, 0, 0 },
 889   { "msr1", 1281, {0, {0}}, 0, 0 },
 890   { "msr2", 1282, {0, {0}}, 0, 0 },
 891   { "msr3", 1283, {0, {0}}, 0, 0 },
 892   { "msr4", 1284, {0, {0}}, 0, 0 },
 893   { "msr5", 1285, {0, {0}}, 0, 0 },
 894   { "msr6", 1286, {0, {0}}, 0, 0 },
 895   { "msr7", 1287, {0, {0}}, 0, 0 },
 896   { "msr8", 1288, {0, {0}}, 0, 0 },
 897   { "msr9", 1289, {0, {0}}, 0, 0 },
 898   { "msr10", 1290, {0, {0}}, 0, 0 },
 899   { "msr11", 1291, {0, {0}}, 0, 0 },
 900   { "msr12", 1292, {0, {0}}, 0, 0 },
 901   { "msr13", 1293, {0, {0}}, 0, 0 },
 902   { "msr14", 1294, {0, {0}}, 0, 0 },
 903   { "msr15", 1295, {0, {0}}, 0, 0 },
 904   { "msr16", 1296, {0, {0}}, 0, 0 },
 905   { "msr17", 1297, {0, {0}}, 0, 0 },
 906   { "msr18", 1298, {0, {0}}, 0, 0 },
 907   { "msr19", 1299, {0, {0}}, 0, 0 },
 908   { "msr20", 1300, {0, {0}}, 0, 0 },
 909   { "msr21", 1301, {0, {0}}, 0, 0 },
 910   { "msr22", 1302, {0, {0}}, 0, 0 },
 911   { "msr23", 1303, {0, {0}}, 0, 0 },
 912   { "msr24", 1304, {0, {0}}, 0, 0 },
 913   { "msr25", 1305, {0, {0}}, 0, 0 },
 914   { "msr26", 1306, {0, {0}}, 0, 0 },
 915   { "msr27", 1307, {0, {0}}, 0, 0 },
 916   { "msr28", 1308, {0, {0}}, 0, 0 },
 917   { "msr29", 1309, {0, {0}}, 0, 0 },
 918   { "msr30", 1310, {0, {0}}, 0, 0 },
 919   { "msr31", 1311, {0, {0}}, 0, 0 },
 920   { "msr32", 1312, {0, {0}}, 0, 0 },
 921   { "msr33", 1313, {0, {0}}, 0, 0 },
 922   { "msr34", 1314, {0, {0}}, 0, 0 },
 923   { "msr35", 1315, {0, {0}}, 0, 0 },
 924   { "msr36", 1316, {0, {0}}, 0, 0 },
 925   { "msr37", 1317, {0, {0}}, 0, 0 },
 926   { "msr38", 1318, {0, {0}}, 0, 0 },
 927   { "msr39", 1319, {0, {0}}, 0, 0 },
 928   { "msr40", 1320, {0, {0}}, 0, 0 },
 929   { "msr41", 1321, {0, {0}}, 0, 0 },
 930   { "msr42", 1322, {0, {0}}, 0, 0 },
 931   { "msr43", 1323, {0, {0}}, 0, 0 },
 932   { "msr44", 1324, {0, {0}}, 0, 0 },
 933   { "msr45", 1325, {0, {0}}, 0, 0 },
 934   { "msr46", 1326, {0, {0}}, 0, 0 },
 935   { "msr47", 1327, {0, {0}}, 0, 0 },
 936   { "msr48", 1328, {0, {0}}, 0, 0 },
 937   { "msr49", 1329, {0, {0}}, 0, 0 },
 938   { "msr50", 1330, {0, {0}}, 0, 0 },
 939   { "msr51", 1331, {0, {0}}, 0, 0 },
 940   { "msr52", 1332, {0, {0}}, 0, 0 },
 941   { "msr53", 1333, {0, {0}}, 0, 0 },
 942   { "msr54", 1334, {0, {0}}, 0, 0 },
 943   { "msr55", 1335, {0, {0}}, 0, 0 },
 944   { "msr56", 1336, {0, {0}}, 0, 0 },
 945   { "msr57", 1337, {0, {0}}, 0, 0 },
 946   { "msr58", 1338, {0, {0}}, 0, 0 },
 947   { "msr59", 1339, {0, {0}}, 0, 0 },
 948   { "msr60", 1340, {0, {0}}, 0, 0 },
 949   { "msr61", 1341, {0, {0}}, 0, 0 },
 950   { "msr62", 1342, {0, {0}}, 0, 0 },
 951   { "msr63", 1343, {0, {0}}, 0, 0 },
 952   { "mqop0", 1344, {0, {0}}, 0, 0 },
 953   { "mqop1", 1346, {0, {0}}, 0, 0 },
 954   { "mqop2", 1348, {0, {0}}, 0, 0 },
 955   { "mqop3", 1350, {0, {0}}, 0, 0 },
 956   { "mqop4", 1352, {0, {0}}, 0, 0 },
 957   { "mqop5", 1354, {0, {0}}, 0, 0 },
 958   { "mqop6", 1356, {0, {0}}, 0, 0 },
 959   { "mqop7", 1358, {0, {0}}, 0, 0 },
 960   { "mqop8", 1360, {0, {0}}, 0, 0 },
 961   { "mqop9", 1362, {0, {0}}, 0, 0 },
 962   { "mqop10", 1364, {0, {0}}, 0, 0 },
 963   { "mqop11", 1366, {0, {0}}, 0, 0 },
 964   { "mqop12", 1368, {0, {0}}, 0, 0 },
 965   { "mqop13", 1370, {0, {0}}, 0, 0 },
 966   { "mqop14", 1372, {0, {0}}, 0, 0 },
 967   { "mqop15", 1374, {0, {0}}, 0, 0 },
 968   { "mqop16", 1376, {0, {0}}, 0, 0 },
 969   { "mqop17", 1378, {0, {0}}, 0, 0 },
 970   { "mqop18", 1380, {0, {0}}, 0, 0 },
 971   { "mqop19", 1382, {0, {0}}, 0, 0 },
 972   { "mqop20", 1384, {0, {0}}, 0, 0 },
 973   { "mqop21", 1386, {0, {0}}, 0, 0 },
 974   { "mqop22", 1388, {0, {0}}, 0, 0 },
 975   { "mqop23", 1390, {0, {0}}, 0, 0 },
 976   { "mqop24", 1392, {0, {0}}, 0, 0 },
 977   { "mqop25", 1394, {0, {0}}, 0, 0 },
 978   { "mqop26", 1396, {0, {0}}, 0, 0 },
 979   { "mqop27", 1398, {0, {0}}, 0, 0 },
 980   { "mqop28", 1400, {0, {0}}, 0, 0 },
 981   { "mqop29", 1402, {0, {0}}, 0, 0 },
 982   { "mqop30", 1404, {0, {0}}, 0, 0 },
 983   { "mqop31", 1406, {0, {0}}, 0, 0 },
 984   { "mqst0", 1345, {0, {0}}, 0, 0 },
 985   { "mqst1", 1347, {0, {0}}, 0, 0 },
 986   { "mqst2", 1349, {0, {0}}, 0, 0 },
 987   { "mqst3", 1351, {0, {0}}, 0, 0 },
 988   { "mqst4", 1353, {0, {0}}, 0, 0 },
 989   { "mqst5", 1355, {0, {0}}, 0, 0 },
 990   { "mqst6", 1357, {0, {0}}, 0, 0 },
 991   { "mqst7", 1359, {0, {0}}, 0, 0 },
 992   { "mqst8", 1361, {0, {0}}, 0, 0 },
 993   { "mqst9", 1363, {0, {0}}, 0, 0 },
 994   { "mqst10", 1365, {0, {0}}, 0, 0 },
 995   { "mqst11", 1367, {0, {0}}, 0, 0 },
 996   { "mqst12", 1369, {0, {0}}, 0, 0 },
 997   { "mqst13", 1371, {0, {0}}, 0, 0 },
 998   { "mqst14", 1373, {0, {0}}, 0, 0 },
 999   { "mqst15", 1375, {0, {0}}, 0, 0 },
1000   { "mqst16", 1377, {0, {0}}, 0, 0 },
1001   { "mqst17", 1379, {0, {0}}, 0, 0 },
1002   { "mqst18", 1381, {0, {0}}, 0, 0 },
1003   { "mqst19", 1383, {0, {0}}, 0, 0 },
1004   { "mqst20", 1385, {0, {0}}, 0, 0 },
1005   { "mqst21", 1387, {0, {0}}, 0, 0 },
1006   { "mqst22", 1389, {0, {0}}, 0, 0 },
1007   { "mqst23", 1391, {0, {0}}, 0, 0 },
1008   { "mqst24", 1393, {0, {0}}, 0, 0 },
1009   { "mqst25", 1395, {0, {0}}, 0, 0 },
1010   { "mqst26", 1397, {0, {0}}, 0, 0 },
1011   { "mqst27", 1399, {0, {0}}, 0, 0 },
1012   { "mqst28", 1401, {0, {0}}, 0, 0 },
1013   { "mqst29", 1403, {0, {0}}, 0, 0 },
1014   { "mqst30", 1405, {0, {0}}, 0, 0 },
1015   { "mqst31", 1407, {0, {0}}, 0, 0 },
1016   { "ear0", 1536, {0, {0}}, 0, 0 },
1017   { "ear1", 1537, {0, {0}}, 0, 0 },
1018   { "ear2", 1538, {0, {0}}, 0, 0 },
1019   { "ear3", 1539, {0, {0}}, 0, 0 },
1020   { "ear4", 1540, {0, {0}}, 0, 0 },
1021   { "ear5", 1541, {0, {0}}, 0, 0 },
1022   { "ear6", 1542, {0, {0}}, 0, 0 },
1023   { "ear7", 1543, {0, {0}}, 0, 0 },
1024   { "ear8", 1544, {0, {0}}, 0, 0 },
1025   { "ear9", 1545, {0, {0}}, 0, 0 },
1026   { "ear10", 1546, {0, {0}}, 0, 0 },
1027   { "ear11", 1547, {0, {0}}, 0, 0 },
1028   { "ear12", 1548, {0, {0}}, 0, 0 },
1029   { "ear13", 1549, {0, {0}}, 0, 0 },
1030   { "ear14", 1550, {0, {0}}, 0, 0 },
1031   { "ear15", 1551, {0, {0}}, 0, 0 },
1032   { "ear16", 1552, {0, {0}}, 0, 0 },
1033   { "ear17", 1553, {0, {0}}, 0, 0 },
1034   { "ear18", 1554, {0, {0}}, 0, 0 },
1035   { "ear19", 1555, {0, {0}}, 0, 0 },
1036   { "ear20", 1556, {0, {0}}, 0, 0 },
1037   { "ear21", 1557, {0, {0}}, 0, 0 },
1038   { "ear22", 1558, {0, {0}}, 0, 0 },
1039   { "ear23", 1559, {0, {0}}, 0, 0 },
1040   { "ear24", 1560, {0, {0}}, 0, 0 },
1041   { "ear25", 1561, {0, {0}}, 0, 0 },
1042   { "ear26", 1562, {0, {0}}, 0, 0 },
1043   { "ear27", 1563, {0, {0}}, 0, 0 },
1044   { "ear28", 1564, {0, {0}}, 0, 0 },
1045   { "ear29", 1565, {0, {0}}, 0, 0 },
1046   { "ear30", 1566, {0, {0}}, 0, 0 },
1047   { "ear31", 1567, {0, {0}}, 0, 0 },
1048   { "ear32", 1568, {0, {0}}, 0, 0 },
1049   { "ear33", 1569, {0, {0}}, 0, 0 },
1050   { "ear34", 1570, {0, {0}}, 0, 0 },
1051   { "ear35", 1571, {0, {0}}, 0, 0 },
1052   { "ear36", 1572, {0, {0}}, 0, 0 },
1053   { "ear37", 1573, {0, {0}}, 0, 0 },
1054   { "ear38", 1574, {0, {0}}, 0, 0 },
1055   { "ear39", 1575, {0, {0}}, 0, 0 },
1056   { "ear40", 1576, {0, {0}}, 0, 0 },
1057   { "ear41", 1577, {0, {0}}, 0, 0 },
1058   { "ear42", 1578, {0, {0}}, 0, 0 },
1059   { "ear43", 1579, {0, {0}}, 0, 0 },
1060   { "ear44", 1580, {0, {0}}, 0, 0 },
1061   { "ear45", 1581, {0, {0}}, 0, 0 },
1062   { "ear46", 1582, {0, {0}}, 0, 0 },
1063   { "ear47", 1583, {0, {0}}, 0, 0 },
1064   { "ear48", 1584, {0, {0}}, 0, 0 },
1065   { "ear49", 1585, {0, {0}}, 0, 0 },
1066   { "ear50", 1586, {0, {0}}, 0, 0 },
1067   { "ear51", 1587, {0, {0}}, 0, 0 },
1068   { "ear52", 1588, {0, {0}}, 0, 0 },
1069   { "ear53", 1589, {0, {0}}, 0, 0 },
1070   { "ear54", 1590, {0, {0}}, 0, 0 },
1071   { "ear55", 1591, {0, {0}}, 0, 0 },
1072   { "ear56", 1592, {0, {0}}, 0, 0 },
1073   { "ear57", 1593, {0, {0}}, 0, 0 },
1074   { "ear58", 1594, {0, {0}}, 0, 0 },
1075   { "ear59", 1595, {0, {0}}, 0, 0 },
1076   { "ear60", 1596, {0, {0}}, 0, 0 },
1077   { "ear61", 1597, {0, {0}}, 0, 0 },
1078   { "ear62", 1598, {0, {0}}, 0, 0 },
1079   { "ear63", 1599, {0, {0}}, 0, 0 },
1080   { "edr0", 1600, {0, {0}}, 0, 0 },
1081   { "edr1", 1601, {0, {0}}, 0, 0 },
1082   { "edr2", 1602, {0, {0}}, 0, 0 },
1083   { "edr3", 1603, {0, {0}}, 0, 0 },
1084   { "edr4", 1604, {0, {0}}, 0, 0 },
1085   { "edr5", 1605, {0, {0}}, 0, 0 },
1086   { "edr6", 1606, {0, {0}}, 0, 0 },
1087   { "edr7", 1607, {0, {0}}, 0, 0 },
1088   { "edr8", 1608, {0, {0}}, 0, 0 },
1089   { "edr9", 1609, {0, {0}}, 0, 0 },
1090   { "edr10", 1610, {0, {0}}, 0, 0 },
1091   { "edr11", 1611, {0, {0}}, 0, 0 },
1092   { "edr12", 1612, {0, {0}}, 0, 0 },
1093   { "edr13", 1613, {0, {0}}, 0, 0 },
1094   { "edr14", 1614, {0, {0}}, 0, 0 },
1095   { "edr15", 1615, {0, {0}}, 0, 0 },
1096   { "edr16", 1616, {0, {0}}, 0, 0 },
1097   { "edr17", 1617, {0, {0}}, 0, 0 },
1098   { "edr18", 1618, {0, {0}}, 0, 0 },
1099   { "edr19", 1619, {0, {0}}, 0, 0 },
1100   { "edr20", 1620, {0, {0}}, 0, 0 },
1101   { "edr21", 1621, {0, {0}}, 0, 0 },
1102   { "edr22", 1622, {0, {0}}, 0, 0 },
1103   { "edr23", 1623, {0, {0}}, 0, 0 },
1104   { "edr24", 1624, {0, {0}}, 0, 0 },
1105   { "edr25", 1625, {0, {0}}, 0, 0 },
1106   { "edr26", 1626, {0, {0}}, 0, 0 },
1107   { "edr27", 1627, {0, {0}}, 0, 0 },
1108   { "edr28", 1628, {0, {0}}, 0, 0 },
1109   { "edr29", 1629, {0, {0}}, 0, 0 },
1110   { "edr30", 1630, {0, {0}}, 0, 0 },
1111   { "edr31", 1631, {0, {0}}, 0, 0 },
1112   { "edr32", 1632, {0, {0}}, 0, 0 },
1113   { "edr33", 1636, {0, {0}}, 0, 0 },
1114   { "edr34", 1634, {0, {0}}, 0, 0 },
1115   { "edr35", 1635, {0, {0}}, 0, 0 },
1116   { "edr36", 1636, {0, {0}}, 0, 0 },
1117   { "edr37", 1637, {0, {0}}, 0, 0 },
1118   { "edr38", 1638, {0, {0}}, 0, 0 },
1119   { "edr39", 1639, {0, {0}}, 0, 0 },
1120   { "edr40", 1640, {0, {0}}, 0, 0 },
1121   { "edr41", 1641, {0, {0}}, 0, 0 },
1122   { "edr42", 1642, {0, {0}}, 0, 0 },
1123   { "edr43", 1643, {0, {0}}, 0, 0 },
1124   { "edr44", 1644, {0, {0}}, 0, 0 },
1125   { "edr45", 1645, {0, {0}}, 0, 0 },
1126   { "edr46", 1646, {0, {0}}, 0, 0 },
1127   { "edr47", 1647, {0, {0}}, 0, 0 },
1128   { "edr48", 1648, {0, {0}}, 0, 0 },
1129   { "edr49", 1649, {0, {0}}, 0, 0 },
1130   { "edr50", 1650, {0, {0}}, 0, 0 },
1131   { "edr51", 1651, {0, {0}}, 0, 0 },
1132   { "edr52", 1652, {0, {0}}, 0, 0 },
1133   { "edr53", 1653, {0, {0}}, 0, 0 },
1134   { "edr54", 1654, {0, {0}}, 0, 0 },
1135   { "edr55", 1655, {0, {0}}, 0, 0 },
1136   { "edr56", 1656, {0, {0}}, 0, 0 },
1137   { "edr57", 1657, {0, {0}}, 0, 0 },
1138   { "edr58", 1658, {0, {0}}, 0, 0 },
1139   { "edr59", 1659, {0, {0}}, 0, 0 },
1140   { "edr60", 1660, {0, {0}}, 0, 0 },
1141   { "edr61", 1661, {0, {0}}, 0, 0 },
1142   { "edr62", 1662, {0, {0}}, 0, 0 },
1143   { "edr63", 1663, {0, {0}}, 0, 0 },
1144   { "iamlr0", 1664, {0, {0}}, 0, 0 },
1145   { "iamlr1", 1665, {0, {0}}, 0, 0 },
1146   { "iamlr2", 1666, {0, {0}}, 0, 0 },
1147   { "iamlr3", 1667, {0, {0}}, 0, 0 },
1148   { "iamlr4", 1668, {0, {0}}, 0, 0 },
1149   { "iamlr5", 1669, {0, {0}}, 0, 0 },
1150   { "iamlr6", 1670, {0, {0}}, 0, 0 },
1151   { "iamlr7", 1671, {0, {0}}, 0, 0 },
1152   { "iamlr8", 1672, {0, {0}}, 0, 0 },
1153   { "iamlr9", 1673, {0, {0}}, 0, 0 },
1154   { "iamlr10", 1674, {0, {0}}, 0, 0 },
1155   { "iamlr11", 1675, {0, {0}}, 0, 0 },
1156   { "iamlr12", 1676, {0, {0}}, 0, 0 },
1157   { "iamlr13", 1677, {0, {0}}, 0, 0 },
1158   { "iamlr14", 1678, {0, {0}}, 0, 0 },
1159   { "iamlr15", 1679, {0, {0}}, 0, 0 },
1160   { "iamlr16", 1680, {0, {0}}, 0, 0 },
1161   { "iamlr17", 1681, {0, {0}}, 0, 0 },
1162   { "iamlr18", 1682, {0, {0}}, 0, 0 },
1163   { "iamlr19", 1683, {0, {0}}, 0, 0 },
1164   { "iamlr20", 1684, {0, {0}}, 0, 0 },
1165   { "iamlr21", 1685, {0, {0}}, 0, 0 },
1166   { "iamlr22", 1686, {0, {0}}, 0, 0 },
1167   { "iamlr23", 1687, {0, {0}}, 0, 0 },
1168   { "iamlr24", 1688, {0, {0}}, 0, 0 },
1169   { "iamlr25", 1689, {0, {0}}, 0, 0 },
1170   { "iamlr26", 1690, {0, {0}}, 0, 0 },
1171   { "iamlr27", 1691, {0, {0}}, 0, 0 },
1172   { "iamlr28", 1692, {0, {0}}, 0, 0 },
1173   { "iamlr29", 1693, {0, {0}}, 0, 0 },
1174   { "iamlr30", 1694, {0, {0}}, 0, 0 },
1175   { "iamlr31", 1695, {0, {0}}, 0, 0 },
1176   { "iamlr32", 1696, {0, {0}}, 0, 0 },
1177   { "iamlr33", 1697, {0, {0}}, 0, 0 },
1178   { "iamlr34", 1698, {0, {0}}, 0, 0 },
1179   { "iamlr35", 1699, {0, {0}}, 0, 0 },
1180   { "iamlr36", 1700, {0, {0}}, 0, 0 },
1181   { "iamlr37", 1701, {0, {0}}, 0, 0 },
1182   { "iamlr38", 1702, {0, {0}}, 0, 0 },
1183   { "iamlr39", 1703, {0, {0}}, 0, 0 },
1184   { "iamlr40", 1704, {0, {0}}, 0, 0 },
1185   { "iamlr41", 1705, {0, {0}}, 0, 0 },
1186   { "iamlr42", 1706, {0, {0}}, 0, 0 },
1187   { "iamlr43", 1707, {0, {0}}, 0, 0 },
1188   { "iamlr44", 1708, {0, {0}}, 0, 0 },
1189   { "iamlr45", 1709, {0, {0}}, 0, 0 },
1190   { "iamlr46", 1710, {0, {0}}, 0, 0 },
1191   { "iamlr47", 1711, {0, {0}}, 0, 0 },
1192   { "iamlr48", 1712, {0, {0}}, 0, 0 },
1193   { "iamlr49", 1713, {0, {0}}, 0, 0 },
1194   { "iamlr50", 1714, {0, {0}}, 0, 0 },
1195   { "iamlr51", 1715, {0, {0}}, 0, 0 },
1196   { "iamlr52", 1716, {0, {0}}, 0, 0 },
1197   { "iamlr53", 1717, {0, {0}}, 0, 0 },
1198   { "iamlr54", 1718, {0, {0}}, 0, 0 },
1199   { "iamlr55", 1719, {0, {0}}, 0, 0 },
1200   { "iamlr56", 1720, {0, {0}}, 0, 0 },
1201   { "iamlr57", 1721, {0, {0}}, 0, 0 },
1202   { "iamlr58", 1722, {0, {0}}, 0, 0 },
1203   { "iamlr59", 1723, {0, {0}}, 0, 0 },
1204   { "iamlr60", 1724, {0, {0}}, 0, 0 },
1205   { "iamlr61", 1725, {0, {0}}, 0, 0 },
1206   { "iamlr62", 1726, {0, {0}}, 0, 0 },
1207   { "iamlr63", 1727, {0, {0}}, 0, 0 },
1208   { "iampr0", 1728, {0, {0}}, 0, 0 },
1209   { "iampr1", 1729, {0, {0}}, 0, 0 },
1210   { "iampr2", 1730, {0, {0}}, 0, 0 },
1211   { "iampr3", 1731, {0, {0}}, 0, 0 },
1212   { "iampr4", 1732, {0, {0}}, 0, 0 },
1213   { "iampr5", 1733, {0, {0}}, 0, 0 },
1214   { "iampr6", 1734, {0, {0}}, 0, 0 },
1215   { "iampr7", 1735, {0, {0}}, 0, 0 },
1216   { "iampr8", 1736, {0, {0}}, 0, 0 },
1217   { "iampr9", 1737, {0, {0}}, 0, 0 },
1218   { "iampr10", 1738, {0, {0}}, 0, 0 },
1219   { "iampr11", 1739, {0, {0}}, 0, 0 },
1220   { "iampr12", 1740, {0, {0}}, 0, 0 },
1221   { "iampr13", 1741, {0, {0}}, 0, 0 },
1222   { "iampr14", 1742, {0, {0}}, 0, 0 },
1223   { "iampr15", 1743, {0, {0}}, 0, 0 },
1224   { "iampr16", 1744, {0, {0}}, 0, 0 },
1225   { "iampr17", 1745, {0, {0}}, 0, 0 },
1226   { "iampr18", 1746, {0, {0}}, 0, 0 },
1227   { "iampr19", 1747, {0, {0}}, 0, 0 },
1228   { "iampr20", 1748, {0, {0}}, 0, 0 },
1229   { "iampr21", 1749, {0, {0}}, 0, 0 },
1230   { "iampr22", 1750, {0, {0}}, 0, 0 },
1231   { "iampr23", 1751, {0, {0}}, 0, 0 },
1232   { "iampr24", 1752, {0, {0}}, 0, 0 },
1233   { "iampr25", 1753, {0, {0}}, 0, 0 },
1234   { "iampr26", 1754, {0, {0}}, 0, 0 },
1235   { "iampr27", 1755, {0, {0}}, 0, 0 },
1236   { "iampr28", 1756, {0, {0}}, 0, 0 },
1237   { "iampr29", 1757, {0, {0}}, 0, 0 },
1238   { "iampr30", 1758, {0, {0}}, 0, 0 },
1239   { "iampr31", 1759, {0, {0}}, 0, 0 },
1240   { "iampr32", 1760, {0, {0}}, 0, 0 },
1241   { "iampr33", 1761, {0, {0}}, 0, 0 },
1242   { "iampr34", 1762, {0, {0}}, 0, 0 },
1243   { "iampr35", 1763, {0, {0}}, 0, 0 },
1244   { "iampr36", 1764, {0, {0}}, 0, 0 },
1245   { "iampr37", 1765, {0, {0}}, 0, 0 },
1246   { "iampr38", 1766, {0, {0}}, 0, 0 },
1247   { "iampr39", 1767, {0, {0}}, 0, 0 },
1248   { "iampr40", 1768, {0, {0}}, 0, 0 },
1249   { "iampr41", 1769, {0, {0}}, 0, 0 },
1250   { "iampr42", 1770, {0, {0}}, 0, 0 },
1251   { "iampr43", 1771, {0, {0}}, 0, 0 },
1252   { "iampr44", 1772, {0, {0}}, 0, 0 },
1253   { "iampr45", 1773, {0, {0}}, 0, 0 },
1254   { "iampr46", 1774, {0, {0}}, 0, 0 },
1255   { "iampr47", 1775, {0, {0}}, 0, 0 },
1256   { "iampr48", 1776, {0, {0}}, 0, 0 },
1257   { "iampr49", 1777, {0, {0}}, 0, 0 },
1258   { "iampr50", 1778, {0, {0}}, 0, 0 },
1259   { "iampr51", 1779, {0, {0}}, 0, 0 },
1260   { "iampr52", 1780, {0, {0}}, 0, 0 },
1261   { "iampr53", 1781, {0, {0}}, 0, 0 },
1262   { "iampr54", 1782, {0, {0}}, 0, 0 },
1263   { "iampr55", 1783, {0, {0}}, 0, 0 },
1264   { "iampr56", 1784, {0, {0}}, 0, 0 },
1265   { "iampr57", 1785, {0, {0}}, 0, 0 },
1266   { "iampr58", 1786, {0, {0}}, 0, 0 },
1267   { "iampr59", 1787, {0, {0}}, 0, 0 },
1268   { "iampr60", 1788, {0, {0}}, 0, 0 },
1269   { "iampr61", 1789, {0, {0}}, 0, 0 },
1270   { "iampr62", 1790, {0, {0}}, 0, 0 },
1271   { "iampr63", 1791, {0, {0}}, 0, 0 },
1272   { "damlr0", 1792, {0, {0}}, 0, 0 },
1273   { "damlr1", 1793, {0, {0}}, 0, 0 },
1274   { "damlr2", 1794, {0, {0}}, 0, 0 },
1275   { "damlr3", 1795, {0, {0}}, 0, 0 },
1276   { "damlr4", 1796, {0, {0}}, 0, 0 },
1277   { "damlr5", 1797, {0, {0}}, 0, 0 },
1278   { "damlr6", 1798, {0, {0}}, 0, 0 },
1279   { "damlr7", 1799, {0, {0}}, 0, 0 },
1280   { "damlr8", 1800, {0, {0}}, 0, 0 },
1281   { "damlr9", 1801, {0, {0}}, 0, 0 },
1282   { "damlr10", 1802, {0, {0}}, 0, 0 },
1283   { "damlr11", 1803, {0, {0}}, 0, 0 },
1284   { "damlr12", 1804, {0, {0}}, 0, 0 },
1285   { "damlr13", 1805, {0, {0}}, 0, 0 },
1286   { "damlr14", 1806, {0, {0}}, 0, 0 },
1287   { "damlr15", 1807, {0, {0}}, 0, 0 },
1288   { "damlr16", 1808, {0, {0}}, 0, 0 },
1289   { "damlr17", 1809, {0, {0}}, 0, 0 },
1290   { "damlr18", 1810, {0, {0}}, 0, 0 },
1291   { "damlr19", 1811, {0, {0}}, 0, 0 },
1292   { "damlr20", 1812, {0, {0}}, 0, 0 },
1293   { "damlr21", 1813, {0, {0}}, 0, 0 },
1294   { "damlr22", 1814, {0, {0}}, 0, 0 },
1295   { "damlr23", 1815, {0, {0}}, 0, 0 },
1296   { "damlr24", 1816, {0, {0}}, 0, 0 },
1297   { "damlr25", 1817, {0, {0}}, 0, 0 },
1298   { "damlr26", 1818, {0, {0}}, 0, 0 },
1299   { "damlr27", 1819, {0, {0}}, 0, 0 },
1300   { "damlr28", 1820, {0, {0}}, 0, 0 },
1301   { "damlr29", 1821, {0, {0}}, 0, 0 },
1302   { "damlr30", 1822, {0, {0}}, 0, 0 },
1303   { "damlr31", 1823, {0, {0}}, 0, 0 },
1304   { "damlr32", 1824, {0, {0}}, 0, 0 },
1305   { "damlr33", 1825, {0, {0}}, 0, 0 },
1306   { "damlr34", 1826, {0, {0}}, 0, 0 },
1307   { "damlr35", 1827, {0, {0}}, 0, 0 },
1308   { "damlr36", 1828, {0, {0}}, 0, 0 },
1309   { "damlr37", 1829, {0, {0}}, 0, 0 },
1310   { "damlr38", 1830, {0, {0}}, 0, 0 },
1311   { "damlr39", 1831, {0, {0}}, 0, 0 },
1312   { "damlr40", 1832, {0, {0}}, 0, 0 },
1313   { "damlr41", 1833, {0, {0}}, 0, 0 },
1314   { "damlr42", 1834, {0, {0}}, 0, 0 },
1315   { "damlr43", 1835, {0, {0}}, 0, 0 },
1316   { "damlr44", 1836, {0, {0}}, 0, 0 },
1317   { "damlr45", 1837, {0, {0}}, 0, 0 },
1318   { "damlr46", 1838, {0, {0}}, 0, 0 },
1319   { "damlr47", 1839, {0, {0}}, 0, 0 },
1320   { "damlr48", 1840, {0, {0}}, 0, 0 },
1321   { "damlr49", 1841, {0, {0}}, 0, 0 },
1322   { "damlr50", 1842, {0, {0}}, 0, 0 },
1323   { "damlr51", 1843, {0, {0}}, 0, 0 },
1324   { "damlr52", 1844, {0, {0}}, 0, 0 },
1325   { "damlr53", 1845, {0, {0}}, 0, 0 },
1326   { "damlr54", 1846, {0, {0}}, 0, 0 },
1327   { "damlr55", 1847, {0, {0}}, 0, 0 },
1328   { "damlr56", 1848, {0, {0}}, 0, 0 },
1329   { "damlr57", 1849, {0, {0}}, 0, 0 },
1330   { "damlr58", 1850, {0, {0}}, 0, 0 },
1331   { "damlr59", 1851, {0, {0}}, 0, 0 },
1332   { "damlr60", 1852, {0, {0}}, 0, 0 },
1333   { "damlr61", 1853, {0, {0}}, 0, 0 },
1334   { "damlr62", 1854, {0, {0}}, 0, 0 },
1335   { "damlr63", 1855, {0, {0}}, 0, 0 },
1336   { "dampr0", 1856, {0, {0}}, 0, 0 },
1337   { "dampr1", 1857, {0, {0}}, 0, 0 },
1338   { "dampr2", 1858, {0, {0}}, 0, 0 },
1339   { "dampr3", 1859, {0, {0}}, 0, 0 },
1340   { "dampr4", 1860, {0, {0}}, 0, 0 },
1341   { "dampr5", 1861, {0, {0}}, 0, 0 },
1342   { "dampr6", 1862, {0, {0}}, 0, 0 },
1343   { "dampr7", 1863, {0, {0}}, 0, 0 },
1344   { "dampr8", 1864, {0, {0}}, 0, 0 },
1345   { "dampr9", 1865, {0, {0}}, 0, 0 },
1346   { "dampr10", 1866, {0, {0}}, 0, 0 },
1347   { "dampr11", 1867, {0, {0}}, 0, 0 },
1348   { "dampr12", 1868, {0, {0}}, 0, 0 },
1349   { "dampr13", 1869, {0, {0}}, 0, 0 },
1350   { "dampr14", 1870, {0, {0}}, 0, 0 },
1351   { "dampr15", 1871, {0, {0}}, 0, 0 },
1352   { "dampr16", 1872, {0, {0}}, 0, 0 },
1353   { "dampr17", 1873, {0, {0}}, 0, 0 },
1354   { "dampr18", 1874, {0, {0}}, 0, 0 },
1355   { "dampr19", 1875, {0, {0}}, 0, 0 },
1356   { "dampr20", 1876, {0, {0}}, 0, 0 },
1357   { "dampr21", 1877, {0, {0}}, 0, 0 },
1358   { "dampr22", 1878, {0, {0}}, 0, 0 },
1359   { "dampr23", 1879, {0, {0}}, 0, 0 },
1360   { "dampr24", 1880, {0, {0}}, 0, 0 },
1361   { "dampr25", 1881, {0, {0}}, 0, 0 },
1362   { "dampr26", 1882, {0, {0}}, 0, 0 },
1363   { "dampr27", 1883, {0, {0}}, 0, 0 },
1364   { "dampr28", 1884, {0, {0}}, 0, 0 },
1365   { "dampr29", 1885, {0, {0}}, 0, 0 },
1366   { "dampr30", 1886, {0, {0}}, 0, 0 },
1367   { "dampr31", 1887, {0, {0}}, 0, 0 },
1368   { "dampr32", 1888, {0, {0}}, 0, 0 },
1369   { "dampr33", 1889, {0, {0}}, 0, 0 },
1370   { "dampr34", 1890, {0, {0}}, 0, 0 },
1371   { "dampr35", 1891, {0, {0}}, 0, 0 },
1372   { "dampr36", 1892, {0, {0}}, 0, 0 },
1373   { "dampr37", 1893, {0, {0}}, 0, 0 },
1374   { "dampr38", 1894, {0, {0}}, 0, 0 },
1375   { "dampr39", 1895, {0, {0}}, 0, 0 },
1376   { "dampr40", 1896, {0, {0}}, 0, 0 },
1377   { "dampr41", 1897, {0, {0}}, 0, 0 },
1378   { "dampr42", 1898, {0, {0}}, 0, 0 },
1379   { "dampr43", 1899, {0, {0}}, 0, 0 },
1380   { "dampr44", 1900, {0, {0}}, 0, 0 },
1381   { "dampr45", 1901, {0, {0}}, 0, 0 },
1382   { "dampr46", 1902, {0, {0}}, 0, 0 },
1383   { "dampr47", 1903, {0, {0}}, 0, 0 },
1384   { "dampr48", 1904, {0, {0}}, 0, 0 },
1385   { "dampr49", 1905, {0, {0}}, 0, 0 },
1386   { "dampr50", 1906, {0, {0}}, 0, 0 },
1387   { "dampr51", 1907, {0, {0}}, 0, 0 },
1388   { "dampr52", 1908, {0, {0}}, 0, 0 },
1389   { "dampr53", 1909, {0, {0}}, 0, 0 },
1390   { "dampr54", 1910, {0, {0}}, 0, 0 },
1391   { "dampr55", 1911, {0, {0}}, 0, 0 },
1392   { "dampr56", 1912, {0, {0}}, 0, 0 },
1393   { "dampr57", 1913, {0, {0}}, 0, 0 },
1394   { "dampr58", 1914, {0, {0}}, 0, 0 },
1395   { "dampr59", 1915, {0, {0}}, 0, 0 },
1396   { "dampr60", 1916, {0, {0}}, 0, 0 },
1397   { "dampr61", 1917, {0, {0}}, 0, 0 },
1398   { "dampr62", 1918, {0, {0}}, 0, 0 },
1399   { "dampr63", 1919, {0, {0}}, 0, 0 },
1400   { "amcr", 1920, {0, {0}}, 0, 0 },
1401   { "stbar", 1921, {0, {0}}, 0, 0 },
1402   { "mmcr", 1922, {0, {0}}, 0, 0 },
1403   { "dcr", 2048, {0, {0}}, 0, 0 },
1404   { "brr", 2049, {0, {0}}, 0, 0 },
1405   { "nmar", 2050, {0, {0}}, 0, 0 },
1406   { "ibar0", 2052, {0, {0}}, 0, 0 },
1407   { "ibar1", 2053, {0, {0}}, 0, 0 },
1408   { "ibar2", 2054, {0, {0}}, 0, 0 },
1409   { "ibar3", 2055, {0, {0}}, 0, 0 },
1410   { "dbar0", 2056, {0, {0}}, 0, 0 },
1411   { "dbar1", 2057, {0, {0}}, 0, 0 },
1412   { "dbar2", 2058, {0, {0}}, 0, 0 },
1413   { "dbar3", 2059, {0, {0}}, 0, 0 },
1414   { "dbdr00", 2060, {0, {0}}, 0, 0 },
1415   { "dbdr01", 2061, {0, {0}}, 0, 0 },
1416   { "dbdr02", 2062, {0, {0}}, 0, 0 },
1417   { "dbdr03", 2063, {0, {0}}, 0, 0 },
1418   { "dbdr10", 2064, {0, {0}}, 0, 0 },
1419   { "dbdr11", 2065, {0, {0}}, 0, 0 },
1420   { "dbdr12", 2066, {0, {0}}, 0, 0 },
1421   { "dbdr13", 2067, {0, {0}}, 0, 0 },
1422   { "dbdr20", 2068, {0, {0}}, 0, 0 },
1423   { "dbdr21", 2069, {0, {0}}, 0, 0 },
1424   { "dbdr22", 2070, {0, {0}}, 0, 0 },
1425   { "dbdr23", 2071, {0, {0}}, 0, 0 },
1426   { "dbdr30", 2072, {0, {0}}, 0, 0 },
1427   { "dbdr31", 2073, {0, {0}}, 0, 0 },
1428   { "dbdr32", 2074, {0, {0}}, 0, 0 },
1429   { "dbdr33", 2075, {0, {0}}, 0, 0 },
1430   { "dbmr00", 2076, {0, {0}}, 0, 0 },
1431   { "dbmr01", 2077, {0, {0}}, 0, 0 },
1432   { "dbmr02", 2078, {0, {0}}, 0, 0 },
1433   { "dbmr03", 2079, {0, {0}}, 0, 0 },
1434   { "dbmr10", 2080, {0, {0}}, 0, 0 },
1435   { "dbmr11", 2081, {0, {0}}, 0, 0 },
1436   { "dbmr12", 2082, {0, {0}}, 0, 0 },
1437   { "dbmr13", 2083, {0, {0}}, 0, 0 },
1438   { "dbmr20", 2084, {0, {0}}, 0, 0 },
1439   { "dbmr21", 2085, {0, {0}}, 0, 0 },
1440   { "dbmr22", 2086, {0, {0}}, 0, 0 },
1441   { "dbmr23", 2087, {0, {0}}, 0, 0 },
1442   { "dbmr30", 2088, {0, {0}}, 0, 0 },
1443   { "dbmr31", 2089, {0, {0}}, 0, 0 },
1444   { "dbmr32", 2090, {0, {0}}, 0, 0 },
1445   { "dbmr33", 2091, {0, {0}}, 0, 0 },
1446   { "cpcfr", 2092, {0, {0}}, 0, 0 },
1447   { "cpcr", 2093, {0, {0}}, 0, 0 },
1448   { "cpsr", 2094, {0, {0}}, 0, 0 },
1449   { "cpesr0", 2096, {0, {0}}, 0, 0 },
1450   { "cpesr1", 2097, {0, {0}}, 0, 0 },
1451   { "cpemr0", 2098, {0, {0}}, 0, 0 },
1452   { "cpemr1", 2099, {0, {0}}, 0, 0 },
1453   { "ihsr8", 3848, {0, {0}}, 0, 0 }
1454 };
1455
1456 CGEN_KEYWORD frv_cgen_opval_spr_names =
1457 {
1458   & frv_cgen_opval_spr_names_entries[0],
1459   1005,
1460   0, 0, 0, 0, ""
1461 };
1462
1463 static CGEN_KEYWORD_ENTRY frv_cgen_opval_accg_names_entries[] =
1464 {
1465   { "accg0", 0, {0, {0}}, 0, 0 },
1466   { "accg1", 1, {0, {0}}, 0, 0 },
1467   { "accg2", 2, {0, {0}}, 0, 0 },
1468   { "accg3", 3, {0, {0}}, 0, 0 },
1469   { "accg4", 4, {0, {0}}, 0, 0 },
1470   { "accg5", 5, {0, {0}}, 0, 0 },
1471   { "accg6", 6, {0, {0}}, 0, 0 },
1472   { "accg7", 7, {0, {0}}, 0, 0 },
1473   { "accg8", 8, {0, {0}}, 0, 0 },
1474   { "accg9", 9, {0, {0}}, 0, 0 },
1475   { "accg10", 10, {0, {0}}, 0, 0 },
1476   { "accg11", 11, {0, {0}}, 0, 0 },
1477   { "accg12", 12, {0, {0}}, 0, 0 },
1478   { "accg13", 13, {0, {0}}, 0, 0 },
1479   { "accg14", 14, {0, {0}}, 0, 0 },
1480   { "accg15", 15, {0, {0}}, 0, 0 },
1481   { "accg16", 16, {0, {0}}, 0, 0 },
1482   { "accg17", 17, {0, {0}}, 0, 0 },
1483   { "accg18", 18, {0, {0}}, 0, 0 },
1484   { "accg19", 19, {0, {0}}, 0, 0 },
1485   { "accg20", 20, {0, {0}}, 0, 0 },
1486   { "accg21", 21, {0, {0}}, 0, 0 },
1487   { "accg22", 22, {0, {0}}, 0, 0 },
1488   { "accg23", 23, {0, {0}}, 0, 0 },
1489   { "accg24", 24, {0, {0}}, 0, 0 },
1490   { "accg25", 25, {0, {0}}, 0, 0 },
1491   { "accg26", 26, {0, {0}}, 0, 0 },
1492   { "accg27", 27, {0, {0}}, 0, 0 },
1493   { "accg28", 28, {0, {0}}, 0, 0 },
1494   { "accg29", 29, {0, {0}}, 0, 0 },
1495   { "accg30", 30, {0, {0}}, 0, 0 },
1496   { "accg31", 31, {0, {0}}, 0, 0 },
1497   { "accg32", 32, {0, {0}}, 0, 0 },
1498   { "accg33", 33, {0, {0}}, 0, 0 },
1499   { "accg34", 34, {0, {0}}, 0, 0 },
1500   { "accg35", 35, {0, {0}}, 0, 0 },
1501   { "accg36", 36, {0, {0}}, 0, 0 },
1502   { "accg37", 37, {0, {0}}, 0, 0 },
1503   { "accg38", 38, {0, {0}}, 0, 0 },
1504   { "accg39", 39, {0, {0}}, 0, 0 },
1505   { "accg40", 40, {0, {0}}, 0, 0 },
1506   { "accg41", 41, {0, {0}}, 0, 0 },
1507   { "accg42", 42, {0, {0}}, 0, 0 },
1508   { "accg43", 43, {0, {0}}, 0, 0 },
1509   { "accg44", 44, {0, {0}}, 0, 0 },
1510   { "accg45", 45, {0, {0}}, 0, 0 },
1511   { "accg46", 46, {0, {0}}, 0, 0 },
1512   { "accg47", 47, {0, {0}}, 0, 0 },
1513   { "accg48", 48, {0, {0}}, 0, 0 },
1514   { "accg49", 49, {0, {0}}, 0, 0 },
1515   { "accg50", 50, {0, {0}}, 0, 0 },
1516   { "accg51", 51, {0, {0}}, 0, 0 },
1517   { "accg52", 52, {0, {0}}, 0, 0 },
1518   { "accg53", 53, {0, {0}}, 0, 0 },
1519   { "accg54", 54, {0, {0}}, 0, 0 },
1520   { "accg55", 55, {0, {0}}, 0, 0 },
1521   { "accg56", 56, {0, {0}}, 0, 0 },
1522   { "accg57", 57, {0, {0}}, 0, 0 },
1523   { "accg58", 58, {0, {0}}, 0, 0 },
1524   { "accg59", 59, {0, {0}}, 0, 0 },
1525   { "accg60", 60, {0, {0}}, 0, 0 },
1526   { "accg61", 61, {0, {0}}, 0, 0 },
1527   { "accg62", 62, {0, {0}}, 0, 0 },
1528   { "accg63", 63, {0, {0}}, 0, 0 }
1529 };
1530
1531 CGEN_KEYWORD frv_cgen_opval_accg_names =
1532 {
1533   & frv_cgen_opval_accg_names_entries[0],
1534   64,
1535   0, 0, 0, 0, ""
1536 };
1537
1538 static CGEN_KEYWORD_ENTRY frv_cgen_opval_acc_names_entries[] =
1539 {
1540   { "acc0", 0, {0, {0}}, 0, 0 },
1541   { "acc1", 1, {0, {0}}, 0, 0 },
1542   { "acc2", 2, {0, {0}}, 0, 0 },
1543   { "acc3", 3, {0, {0}}, 0, 0 },
1544   { "acc4", 4, {0, {0}}, 0, 0 },
1545   { "acc5", 5, {0, {0}}, 0, 0 },
1546   { "acc6", 6, {0, {0}}, 0, 0 },
1547   { "acc7", 7, {0, {0}}, 0, 0 },
1548   { "acc8", 8, {0, {0}}, 0, 0 },
1549   { "acc9", 9, {0, {0}}, 0, 0 },
1550   { "acc10", 10, {0, {0}}, 0, 0 },
1551   { "acc11", 11, {0, {0}}, 0, 0 },
1552   { "acc12", 12, {0, {0}}, 0, 0 },
1553   { "acc13", 13, {0, {0}}, 0, 0 },
1554   { "acc14", 14, {0, {0}}, 0, 0 },
1555   { "acc15", 15, {0, {0}}, 0, 0 },
1556   { "acc16", 16, {0, {0}}, 0, 0 },
1557   { "acc17", 17, {0, {0}}, 0, 0 },
1558   { "acc18", 18, {0, {0}}, 0, 0 },
1559   { "acc19", 19, {0, {0}}, 0, 0 },
1560   { "acc20", 20, {0, {0}}, 0, 0 },
1561   { "acc21", 21, {0, {0}}, 0, 0 },
1562   { "acc22", 22, {0, {0}}, 0, 0 },
1563   { "acc23", 23, {0, {0}}, 0, 0 },
1564   { "acc24", 24, {0, {0}}, 0, 0 },
1565   { "acc25", 25, {0, {0}}, 0, 0 },
1566   { "acc26", 26, {0, {0}}, 0, 0 },
1567   { "acc27", 27, {0, {0}}, 0, 0 },
1568   { "acc28", 28, {0, {0}}, 0, 0 },
1569   { "acc29", 29, {0, {0}}, 0, 0 },
1570   { "acc30", 30, {0, {0}}, 0, 0 },
1571   { "acc31", 31, {0, {0}}, 0, 0 },
1572   { "acc32", 32, {0, {0}}, 0, 0 },
1573   { "acc33", 33, {0, {0}}, 0, 0 },
1574   { "acc34", 34, {0, {0}}, 0, 0 },
1575   { "acc35", 35, {0, {0}}, 0, 0 },
1576   { "acc36", 36, {0, {0}}, 0, 0 },
1577   { "acc37", 37, {0, {0}}, 0, 0 },
1578   { "acc38", 38, {0, {0}}, 0, 0 },
1579   { "acc39", 39, {0, {0}}, 0, 0 },
1580   { "acc40", 40, {0, {0}}, 0, 0 },
1581   { "acc41", 41, {0, {0}}, 0, 0 },
1582   { "acc42", 42, {0, {0}}, 0, 0 },
1583   { "acc43", 43, {0, {0}}, 0, 0 },
1584   { "acc44", 44, {0, {0}}, 0, 0 },
1585   { "acc45", 45, {0, {0}}, 0, 0 },
1586   { "acc46", 46, {0, {0}}, 0, 0 },
1587   { "acc47", 47, {0, {0}}, 0, 0 },
1588   { "acc48", 48, {0, {0}}, 0, 0 },
1589   { "acc49", 49, {0, {0}}, 0, 0 },
1590   { "acc50", 50, {0, {0}}, 0, 0 },
1591   { "acc51", 51, {0, {0}}, 0, 0 },
1592   { "acc52", 52, {0, {0}}, 0, 0 },
1593   { "acc53", 53, {0, {0}}, 0, 0 },
1594   { "acc54", 54, {0, {0}}, 0, 0 },
1595   { "acc55", 55, {0, {0}}, 0, 0 },
1596   { "acc56", 56, {0, {0}}, 0, 0 },
1597   { "acc57", 57, {0, {0}}, 0, 0 },
1598   { "acc58", 58, {0, {0}}, 0, 0 },
1599   { "acc59", 59, {0, {0}}, 0, 0 },
1600   { "acc60", 60, {0, {0}}, 0, 0 },
1601   { "acc61", 61, {0, {0}}, 0, 0 },
1602   { "acc62", 62, {0, {0}}, 0, 0 },
1603   { "acc63", 63, {0, {0}}, 0, 0 }
1604 };
1605
1606 CGEN_KEYWORD frv_cgen_opval_acc_names =
1607 {
1608   & frv_cgen_opval_acc_names_entries[0],
1609   64,
1610   0, 0, 0, 0, ""
1611 };
1612
1613 static CGEN_KEYWORD_ENTRY frv_cgen_opval_iccr_names_entries[] =
1614 {
1615   { "icc0", 0, {0, {0}}, 0, 0 },
1616   { "icc1", 1, {0, {0}}, 0, 0 },
1617   { "icc2", 2, {0, {0}}, 0, 0 },
1618   { "icc3", 3, {0, {0}}, 0, 0 }
1619 };
1620
1621 CGEN_KEYWORD frv_cgen_opval_iccr_names =
1622 {
1623   & frv_cgen_opval_iccr_names_entries[0],
1624   4,
1625   0, 0, 0, 0, ""
1626 };
1627
1628 static CGEN_KEYWORD_ENTRY frv_cgen_opval_fccr_names_entries[] =
1629 {
1630   { "fcc0", 0, {0, {0}}, 0, 0 },
1631   { "fcc1", 1, {0, {0}}, 0, 0 },
1632   { "fcc2", 2, {0, {0}}, 0, 0 },
1633   { "fcc3", 3, {0, {0}}, 0, 0 }
1634 };
1635
1636 CGEN_KEYWORD frv_cgen_opval_fccr_names =
1637 {
1638   & frv_cgen_opval_fccr_names_entries[0],
1639   4,
1640   0, 0, 0, 0, ""
1641 };
1642
1643 static CGEN_KEYWORD_ENTRY frv_cgen_opval_cccr_names_entries[] =
1644 {
1645   { "cc0", 0, {0, {0}}, 0, 0 },
1646   { "cc1", 1, {0, {0}}, 0, 0 },
1647   { "cc2", 2, {0, {0}}, 0, 0 },
1648   { "cc3", 3, {0, {0}}, 0, 0 },
1649   { "cc4", 4, {0, {0}}, 0, 0 },
1650   { "cc5", 5, {0, {0}}, 0, 0 },
1651   { "cc6", 6, {0, {0}}, 0, 0 },
1652   { "cc7", 7, {0, {0}}, 0, 0 }
1653 };
1654
1655 CGEN_KEYWORD frv_cgen_opval_cccr_names =
1656 {
1657   & frv_cgen_opval_cccr_names_entries[0],
1658   8,
1659   0, 0, 0, 0, ""
1660 };
1661
1662 static CGEN_KEYWORD_ENTRY frv_cgen_opval_h_pack_entries[] =
1663 {
1664   { "", 1, {0, {0}}, 0, 0 },
1665   { ".p", 0, {0, {0}}, 0, 0 },
1666   { ".P", 0, {0, {0}}, 0, 0 }
1667 };
1668
1669 CGEN_KEYWORD frv_cgen_opval_h_pack =
1670 {
1671   & frv_cgen_opval_h_pack_entries[0],
1672   3,
1673   0, 0, 0, 0, ""
1674 };
1675
1676 static CGEN_KEYWORD_ENTRY frv_cgen_opval_h_hint_taken_entries[] =
1677 {
1678   { "", 2, {0, {0}}, 0, 0 },
1679   { "", 0, {0, {0}}, 0, 0 },
1680   { "", 1, {0, {0}}, 0, 0 },
1681   { "", 3, {0, {0}}, 0, 0 }
1682 };
1683
1684 CGEN_KEYWORD frv_cgen_opval_h_hint_taken =
1685 {
1686   & frv_cgen_opval_h_hint_taken_entries[0],
1687   4,
1688   0, 0, 0, 0, ""
1689 };
1690
1691 static CGEN_KEYWORD_ENTRY frv_cgen_opval_h_hint_not_taken_entries[] =
1692 {
1693   { "", 0, {0, {0}}, 0, 0 },
1694   { "", 1, {0, {0}}, 0, 0 },
1695   { "", 2, {0, {0}}, 0, 0 },
1696   { "", 3, {0, {0}}, 0, 0 }
1697 };
1698
1699 CGEN_KEYWORD frv_cgen_opval_h_hint_not_taken =
1700 {
1701   & frv_cgen_opval_h_hint_not_taken_entries[0],
1702   4,
1703   0, 0, 0, 0, ""
1704 };
1705
1706
1707 /* The hardware table.  */
1708
1709 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
1710 #define A(a) (1 << CGEN_HW_##a)
1711 #else
1712 #define A(a) (1 << CGEN_HW_/**/a)
1713 #endif
1714
1715 const CGEN_HW_ENTRY frv_cgen_hw_table[] =
1716 {
1717   { "h-memory", HW_H_MEMORY, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
1718   { "h-sint", HW_H_SINT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
1719   { "h-uint", HW_H_UINT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
1720   { "h-addr", HW_H_ADDR, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
1721   { "h-iaddr", HW_H_IADDR, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
1722   { "h-pc", HW_H_PC, CGEN_ASM_NONE, 0, { 0|A(PROFILE)|A(PC), { (1<<MACH_BASE) } } },
1723   { "h-psr_imple", HW_H_PSR_IMPLE, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
1724   { "h-psr_ver", HW_H_PSR_VER, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
1725   { "h-psr_ice", HW_H_PSR_ICE, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
1726   { "h-psr_nem", HW_H_PSR_NEM, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
1727   { "h-psr_cm", HW_H_PSR_CM, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
1728   { "h-psr_be", HW_H_PSR_BE, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
1729   { "h-psr_esr", HW_H_PSR_ESR, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
1730   { "h-psr_ef", HW_H_PSR_EF, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
1731   { "h-psr_em", HW_H_PSR_EM, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
1732   { "h-psr_pil", HW_H_PSR_PIL, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
1733   { "h-psr_ps", HW_H_PSR_PS, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
1734   { "h-psr_et", HW_H_PSR_ET, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
1735   { "h-psr_s", HW_H_PSR_S, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
1736   { "h-tbr_tba", HW_H_TBR_TBA, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
1737   { "h-tbr_tt", HW_H_TBR_TT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
1738   { "h-bpsr_bs", HW_H_BPSR_BS, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
1739   { "h-bpsr_bet", HW_H_BPSR_BET, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
1740   { "h-gr", HW_H_GR, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_gr_names, { 0|A(PROFILE), { (1<<MACH_BASE) } } },
1741   { "h-gr_double", HW_H_GR_DOUBLE, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_gr_names, { 0|A(VIRTUAL)|A(PROFILE), { (1<<MACH_BASE) } } },
1742   { "h-gr_hi", HW_H_GR_HI, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_gr_names, { 0|A(VIRTUAL)|A(PROFILE), { (1<<MACH_BASE) } } },
1743   { "h-gr_lo", HW_H_GR_LO, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_gr_names, { 0|A(VIRTUAL)|A(PROFILE), { (1<<MACH_BASE) } } },
1744   { "h-fr", HW_H_FR, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_fr_names, { 0|A(PROFILE), { (1<<MACH_BASE) } } },
1745   { "h-fr_double", HW_H_FR_DOUBLE, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_fr_names, { 0|A(VIRTUAL)|A(PROFILE), { (1<<MACH_BASE) } } },
1746   { "h-fr_int", HW_H_FR_INT, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_fr_names, { 0|A(VIRTUAL)|A(PROFILE), { (1<<MACH_BASE) } } },
1747   { "h-fr_hi", HW_H_FR_HI, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_fr_names, { 0|A(VIRTUAL)|A(PROFILE), { (1<<MACH_BASE) } } },
1748   { "h-fr_lo", HW_H_FR_LO, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_fr_names, { 0|A(VIRTUAL)|A(PROFILE), { (1<<MACH_BASE) } } },
1749   { "h-fr_0", HW_H_FR_0, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_fr_names, { 0|A(VIRTUAL)|A(PROFILE), { (1<<MACH_BASE) } } },
1750   { "h-fr_1", HW_H_FR_1, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_fr_names, { 0|A(VIRTUAL)|A(PROFILE), { (1<<MACH_BASE) } } },
1751   { "h-fr_2", HW_H_FR_2, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_fr_names, { 0|A(VIRTUAL)|A(PROFILE), { (1<<MACH_BASE) } } },
1752   { "h-fr_3", HW_H_FR_3, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_fr_names, { 0|A(VIRTUAL)|A(PROFILE), { (1<<MACH_BASE) } } },
1753   { "h-cpr", HW_H_CPR, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_cpr_names, { 0|A(PROFILE), { (1<<MACH_FRV) } } },
1754   { "h-cpr_double", HW_H_CPR_DOUBLE, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_cpr_names, { 0|A(VIRTUAL)|A(PROFILE), { (1<<MACH_FRV) } } },
1755   { "h-spr", HW_H_SPR, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_spr_names, { 0|A(PROFILE), { (1<<MACH_BASE) } } },
1756   { "h-accg", HW_H_ACCG, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_accg_names, { 0|A(VIRTUAL)|A(PROFILE), { (1<<MACH_BASE) } } },
1757   { "h-acc40S", HW_H_ACC40S, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_acc_names, { 0|A(VIRTUAL)|A(PROFILE), { (1<<MACH_BASE) } } },
1758   { "h-acc40U", HW_H_ACC40U, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_acc_names, { 0|A(VIRTUAL)|A(PROFILE), { (1<<MACH_BASE) } } },
1759   { "h-iccr", HW_H_ICCR, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_iccr_names, { 0|A(PROFILE), { (1<<MACH_BASE) } } },
1760   { "h-fccr", HW_H_FCCR, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_fccr_names, { 0|A(PROFILE), { (1<<MACH_BASE) } } },
1761   { "h-cccr", HW_H_CCCR, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_cccr_names, { 0|A(PROFILE), { (1<<MACH_BASE) } } },
1762   { "h-pack", HW_H_PACK, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_h_pack, { 0, { (1<<MACH_BASE) } } },
1763   { "h-hint-taken", HW_H_HINT_TAKEN, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_h_hint_taken, { 0, { (1<<MACH_BASE) } } },
1764   { "h-hint-not-taken", HW_H_HINT_NOT_TAKEN, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_h_hint_not_taken, { 0, { (1<<MACH_BASE) } } },
1765   { 0, 0, CGEN_ASM_NONE, 0, {0, {0}} }
1766 };
1767
1768 #undef A
1769
1770
1771 /* The instruction field table.  */
1772
1773 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
1774 #define A(a) (1 << CGEN_IFLD_##a)
1775 #else
1776 #define A(a) (1 << CGEN_IFLD_/**/a)
1777 #endif
1778
1779 const CGEN_IFLD frv_cgen_ifld_table[] =
1780 {
1781   { FRV_F_NIL, "f-nil", 0, 0, 0, 0, { 0, { (1<<MACH_BASE) } }  },
1782   { FRV_F_ANYOF, "f-anyof", 0, 0, 0, 0, { 0, { (1<<MACH_BASE) } }  },
1783   { FRV_F_PACK, "f-pack", 0, 32, 31, 1, { 0, { (1<<MACH_BASE) } }  },
1784   { FRV_F_OP, "f-op", 0, 32, 24, 7, { 0, { (1<<MACH_BASE) } }  },
1785   { FRV_F_OPE1, "f-ope1", 0, 32, 11, 6, { 0, { (1<<MACH_BASE) } }  },
1786   { FRV_F_OPE2, "f-ope2", 0, 32, 9, 4, { 0, { (1<<MACH_BASE) } }  },
1787   { FRV_F_OPE3, "f-ope3", 0, 32, 15, 3, { 0, { (1<<MACH_BASE) } }  },
1788   { FRV_F_OPE4, "f-ope4", 0, 32, 7, 2, { 0, { (1<<MACH_BASE) } }  },
1789   { FRV_F_GRI, "f-GRi", 0, 32, 17, 6, { 0, { (1<<MACH_BASE) } }  },
1790   { FRV_F_GRJ, "f-GRj", 0, 32, 5, 6, { 0, { (1<<MACH_BASE) } }  },
1791   { FRV_F_GRK, "f-GRk", 0, 32, 30, 6, { 0, { (1<<MACH_BASE) } }  },
1792   { FRV_F_FRI, "f-FRi", 0, 32, 17, 6, { 0, { (1<<MACH_BASE) } }  },
1793   { FRV_F_FRJ, "f-FRj", 0, 32, 5, 6, { 0, { (1<<MACH_BASE) } }  },
1794   { FRV_F_FRK, "f-FRk", 0, 32, 30, 6, { 0, { (1<<MACH_BASE) } }  },
1795   { FRV_F_CPRI, "f-CPRi", 0, 32, 17, 6, { 0, { (1<<MACH_BASE) } }  },
1796   { FRV_F_CPRJ, "f-CPRj", 0, 32, 5, 6, { 0, { (1<<MACH_BASE) } }  },
1797   { FRV_F_CPRK, "f-CPRk", 0, 32, 30, 6, { 0, { (1<<MACH_BASE) } }  },
1798   { FRV_F_ACCGI, "f-ACCGi", 0, 32, 17, 6, { 0, { (1<<MACH_BASE) } }  },
1799   { FRV_F_ACCGK, "f-ACCGk", 0, 32, 30, 6, { 0, { (1<<MACH_BASE) } }  },
1800   { FRV_F_ACC40SI, "f-ACC40Si", 0, 32, 17, 6, { 0, { (1<<MACH_BASE) } }  },
1801   { FRV_F_ACC40UI, "f-ACC40Ui", 0, 32, 17, 6, { 0, { (1<<MACH_BASE) } }  },
1802   { FRV_F_ACC40SK, "f-ACC40Sk", 0, 32, 30, 6, { 0, { (1<<MACH_BASE) } }  },
1803   { FRV_F_ACC40UK, "f-ACC40Uk", 0, 32, 30, 6, { 0, { (1<<MACH_BASE) } }  },
1804   { FRV_F_CRI, "f-CRi", 0, 32, 14, 3, { 0, { (1<<MACH_BASE) } }  },
1805   { FRV_F_CRJ, "f-CRj", 0, 32, 2, 3, { 0, { (1<<MACH_BASE) } }  },
1806   { FRV_F_CRK, "f-CRk", 0, 32, 27, 3, { 0, { (1<<MACH_BASE) } }  },
1807   { FRV_F_CCI, "f-CCi", 0, 32, 11, 3, { 0, { (1<<MACH_BASE) } }  },
1808   { FRV_F_CRJ_INT, "f-CRj_int", 0, 32, 26, 2, { 0, { (1<<MACH_BASE) } }  },
1809   { FRV_F_CRJ_FLOAT, "f-CRj_float", 0, 32, 26, 2, { 0, { (1<<MACH_BASE) } }  },
1810   { FRV_F_ICCI_1, "f-ICCi_1", 0, 32, 11, 2, { 0, { (1<<MACH_BASE) } }  },
1811   { FRV_F_ICCI_2, "f-ICCi_2", 0, 32, 26, 2, { 0, { (1<<MACH_BASE) } }  },
1812   { FRV_F_ICCI_3, "f-ICCi_3", 0, 32, 1, 2, { 0, { (1<<MACH_BASE) } }  },
1813   { FRV_F_FCCI_1, "f-FCCi_1", 0, 32, 11, 2, { 0, { (1<<MACH_BASE) } }  },
1814   { FRV_F_FCCI_2, "f-FCCi_2", 0, 32, 26, 2, { 0, { (1<<MACH_BASE) } }  },
1815   { FRV_F_FCCI_3, "f-FCCi_3", 0, 32, 1, 2, { 0, { (1<<MACH_BASE) } }  },
1816   { FRV_F_FCCK, "f-FCCk", 0, 32, 26, 2, { 0, { (1<<MACH_BASE) } }  },
1817   { FRV_F_EIR, "f-eir", 0, 32, 17, 6, { 0, { (1<<MACH_BASE) } }  },
1818   { FRV_F_S10, "f-s10", 0, 32, 9, 10, { 0, { (1<<MACH_BASE) } }  },
1819   { FRV_F_S12, "f-s12", 0, 32, 11, 12, { 0, { (1<<MACH_BASE) } }  },
1820   { FRV_F_D12, "f-d12", 0, 32, 11, 12, { 0, { (1<<MACH_BASE) } }  },
1821   { FRV_F_U16, "f-u16", 0, 32, 15, 16, { 0, { (1<<MACH_BASE) } }  },
1822   { FRV_F_S16, "f-s16", 0, 32, 15, 16, { 0, { (1<<MACH_BASE) } }  },
1823   { FRV_F_S6, "f-s6", 0, 32, 5, 6, { 0, { (1<<MACH_BASE) } }  },
1824   { FRV_F_S6_1, "f-s6_1", 0, 32, 11, 6, { 0, { (1<<MACH_BASE) } }  },
1825   { FRV_F_U6, "f-u6", 0, 32, 5, 6, { 0, { (1<<MACH_BASE) } }  },
1826   { FRV_F_S5, "f-s5", 0, 32, 4, 5, { 0, { (1<<MACH_BASE) } }  },
1827   { FRV_F_U12_H, "f-u12-h", 0, 32, 17, 6, { 0, { (1<<MACH_BASE) } }  },
1828   { FRV_F_U12_L, "f-u12-l", 0, 32, 5, 6, { 0, { (1<<MACH_BASE) } }  },
1829   { FRV_F_INT_CC, "f-int-cc", 0, 32, 30, 4, { 0, { (1<<MACH_BASE) } }  },
1830   { FRV_F_FLT_CC, "f-flt-cc", 0, 32, 30, 4, { 0, { (1<<MACH_BASE) } }  },
1831   { FRV_F_COND, "f-cond", 0, 32, 8, 1, { 0, { (1<<MACH_BASE) } }  },
1832   { FRV_F_CCOND, "f-ccond", 0, 32, 12, 1, { 0, { (1<<MACH_BASE) } }  },
1833   { FRV_F_HINT, "f-hint", 0, 32, 17, 2, { 0, { (1<<MACH_BASE) } }  },
1834   { FRV_F_LI, "f-LI", 0, 32, 25, 1, { 0, { (1<<MACH_BASE) } }  },
1835   { FRV_F_LOCK, "f-lock", 0, 32, 25, 1, { 0, { (1<<MACH_BASE) } }  },
1836   { FRV_F_DEBUG, "f-debug", 0, 32, 25, 1, { 0, { (1<<MACH_BASE) } }  },
1837   { FRV_F_A, "f-A", 0, 32, 17, 1, { 0, { (1<<MACH_BASE) } }  },
1838   { FRV_F_AE, "f-ae", 0, 32, 25, 1, { 0, { (1<<MACH_BASE) } }  },
1839   { FRV_F_SPR_H, "f-spr-h", 0, 32, 30, 6, { 0, { (1<<MACH_BASE) } }  },
1840   { FRV_F_SPR_L, "f-spr-l", 0, 32, 17, 6, { 0, { (1<<MACH_BASE) } }  },
1841   { FRV_F_LABEL16, "f-label16", 0, 32, 15, 16, { 0|A(PCREL_ADDR), { (1<<MACH_BASE) } }  },
1842   { FRV_F_LABELH6, "f-labelH6", 0, 32, 30, 6, { 0, { (1<<MACH_BASE) } }  },
1843   { FRV_F_LABELL18, "f-labelL18", 0, 32, 17, 18, { 0, { (1<<MACH_BASE) } }  },
1844   { FRV_F_ICCI_1_NULL, "f-ICCi_1-null", 0, 32, 11, 2, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
1845   { FRV_F_ICCI_2_NULL, "f-ICCi_2-null", 0, 32, 26, 2, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
1846   { FRV_F_ICCI_3_NULL, "f-ICCi_3-null", 0, 32, 1, 2, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
1847   { FRV_F_FCCI_1_NULL, "f-FCCi_1-null", 0, 32, 11, 2, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
1848   { FRV_F_FCCI_2_NULL, "f-FCCi_2-null", 0, 32, 26, 2, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
1849   { FRV_F_FCCI_3_NULL, "f-FCCi_3-null", 0, 32, 1, 2, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
1850   { FRV_F_RS_NULL, "f-rs-null", 0, 32, 17, 6, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
1851   { FRV_F_GRI_NULL, "f-GRi-null", 0, 32, 17, 6, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
1852   { FRV_F_GRJ_NULL, "f-GRj-null", 0, 32, 5, 6, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
1853   { FRV_F_GRK_NULL, "f-GRk-null", 0, 32, 30, 6, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
1854   { FRV_F_FRI_NULL, "f-FRi-null", 0, 32, 17, 6, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
1855   { FRV_F_FRJ_NULL, "f-FRj-null", 0, 32, 5, 6, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
1856   { FRV_F_ACCJ_NULL, "f-ACCj-null", 0, 32, 5, 6, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
1857   { FRV_F_RD_NULL, "f-rd-null", 0, 32, 30, 6, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
1858   { FRV_F_COND_NULL, "f-cond-null", 0, 32, 30, 4, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
1859   { FRV_F_CCOND_NULL, "f-ccond-null", 0, 32, 12, 1, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
1860   { FRV_F_S12_NULL, "f-s12-null", 0, 32, 11, 12, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
1861   { FRV_F_LABEL16_NULL, "f-label16-null", 0, 32, 15, 16, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
1862   { FRV_F_MISC_NULL_1, "f-misc-null-1", 0, 32, 30, 5, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
1863   { FRV_F_MISC_NULL_2, "f-misc-null-2", 0, 32, 11, 6, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
1864   { FRV_F_MISC_NULL_3, "f-misc-null-3", 0, 32, 11, 4, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
1865   { FRV_F_MISC_NULL_4, "f-misc-null-4", 0, 32, 17, 2, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
1866   { FRV_F_MISC_NULL_5, "f-misc-null-5", 0, 32, 17, 16, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
1867   { FRV_F_MISC_NULL_6, "f-misc-null-6", 0, 32, 30, 3, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
1868   { FRV_F_MISC_NULL_7, "f-misc-null-7", 0, 32, 17, 3, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
1869   { FRV_F_MISC_NULL_8, "f-misc-null-8", 0, 32, 5, 3, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
1870   { FRV_F_MISC_NULL_9, "f-misc-null-9", 0, 32, 5, 4, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
1871   { FRV_F_MISC_NULL_10, "f-misc-null-10", 0, 32, 16, 5, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
1872   { FRV_F_MISC_NULL_11, "f-misc-null-11", 0, 32, 5, 1, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
1873   { FRV_F_LI_OFF, "f-LI-off", 0, 32, 25, 1, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
1874   { FRV_F_LI_ON, "f-LI-on", 0, 32, 25, 1, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
1875   { 0, 0, 0, 0, 0, 0, {0, {0}} }
1876 };
1877
1878 #undef A
1879
1880
1881
1882 /* multi ifield declarations */
1883
1884 const CGEN_MAYBE_MULTI_IFLD FRV_F_U12_MULTI_IFIELD [];
1885 const CGEN_MAYBE_MULTI_IFLD FRV_F_SPR_MULTI_IFIELD [];
1886 const CGEN_MAYBE_MULTI_IFLD FRV_F_LABEL24_MULTI_IFIELD [];
1887
1888
1889 /* multi ifield definitions */
1890
1891 const CGEN_MAYBE_MULTI_IFLD FRV_F_U12_MULTI_IFIELD [] =
1892 {
1893     { 0, { (const PTR) &frv_cgen_ifld_table[46] } },
1894     { 0, { (const PTR) &frv_cgen_ifld_table[47] } },
1895     { 0, { (const PTR) 0 } }
1896 };
1897 const CGEN_MAYBE_MULTI_IFLD FRV_F_SPR_MULTI_IFIELD [] =
1898 {
1899     { 0, { (const PTR) &frv_cgen_ifld_table[58] } },
1900     { 0, { (const PTR) &frv_cgen_ifld_table[59] } },
1901     { 0, { (const PTR) 0 } }
1902 };
1903 const CGEN_MAYBE_MULTI_IFLD FRV_F_LABEL24_MULTI_IFIELD [] =
1904 {
1905     { 0, { (const PTR) &frv_cgen_ifld_table[61] } },
1906     { 0, { (const PTR) &frv_cgen_ifld_table[62] } },
1907     { 0, { (const PTR) 0 } }
1908 };
1909
1910 /* The operand table.  */
1911
1912 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
1913 #define A(a) (1 << CGEN_OPERAND_##a)
1914 #else
1915 #define A(a) (1 << CGEN_OPERAND_/**/a)
1916 #endif
1917 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
1918 #define OPERAND(op) FRV_OPERAND_##op
1919 #else
1920 #define OPERAND(op) FRV_OPERAND_/**/op
1921 #endif
1922
1923 const CGEN_OPERAND frv_cgen_operand_table[] =
1924 {
1925 /* pc: program counter */
1926   { "pc", FRV_OPERAND_PC, HW_H_PC, 0, 0,
1927     { 0, { (const PTR) &frv_cgen_ifld_table[0] } },
1928     { 0|A(SEM_ONLY), { (1<<MACH_BASE) } }  },
1929 /* pack: packing bit */
1930   { "pack", FRV_OPERAND_PACK, HW_H_PACK, 31, 1,
1931     { 0, { (const PTR) &frv_cgen_ifld_table[2] } },
1932     { 0, { (1<<MACH_BASE) } }  },
1933 /* GRi: source register 1 */
1934   { "GRi", FRV_OPERAND_GRI, HW_H_GR, 17, 6,
1935     { 0, { (const PTR) &frv_cgen_ifld_table[8] } },
1936     { 0, { (1<<MACH_BASE) } }  },
1937 /* GRj: source register 2 */
1938   { "GRj", FRV_OPERAND_GRJ, HW_H_GR, 5, 6,
1939     { 0, { (const PTR) &frv_cgen_ifld_table[9] } },
1940     { 0, { (1<<MACH_BASE) } }  },
1941 /* GRk: destination register */
1942   { "GRk", FRV_OPERAND_GRK, HW_H_GR, 30, 6,
1943     { 0, { (const PTR) &frv_cgen_ifld_table[10] } },
1944     { 0, { (1<<MACH_BASE) } }  },
1945 /* GRkhi: destination register */
1946   { "GRkhi", FRV_OPERAND_GRKHI, HW_H_GR_HI, 30, 6,
1947     { 0, { (const PTR) &frv_cgen_ifld_table[10] } },
1948     { 0, { (1<<MACH_BASE) } }  },
1949 /* GRklo: destination register */
1950   { "GRklo", FRV_OPERAND_GRKLO, HW_H_GR_LO, 30, 6,
1951     { 0, { (const PTR) &frv_cgen_ifld_table[10] } },
1952     { 0, { (1<<MACH_BASE) } }  },
1953 /* GRdoublek: destination register */
1954   { "GRdoublek", FRV_OPERAND_GRDOUBLEK, HW_H_GR_DOUBLE, 30, 6,
1955     { 0, { (const PTR) &frv_cgen_ifld_table[10] } },
1956     { 0, { (1<<MACH_BASE) } }  },
1957 /* ACC40Si: signed accumulator */
1958   { "ACC40Si", FRV_OPERAND_ACC40SI, HW_H_ACC40S, 17, 6,
1959     { 0, { (const PTR) &frv_cgen_ifld_table[19] } },
1960     { 0, { (1<<MACH_BASE) } }  },
1961 /* ACC40Ui: unsigned accumulator */
1962   { "ACC40Ui", FRV_OPERAND_ACC40UI, HW_H_ACC40U, 17, 6,
1963     { 0, { (const PTR) &frv_cgen_ifld_table[20] } },
1964     { 0, { (1<<MACH_BASE) } }  },
1965 /* ACC40Sk: target accumulator */
1966   { "ACC40Sk", FRV_OPERAND_ACC40SK, HW_H_ACC40S, 30, 6,
1967     { 0, { (const PTR) &frv_cgen_ifld_table[21] } },
1968     { 0, { (1<<MACH_BASE) } }  },
1969 /* ACC40Uk: target accumulator */
1970   { "ACC40Uk", FRV_OPERAND_ACC40UK, HW_H_ACC40U, 30, 6,
1971     { 0, { (const PTR) &frv_cgen_ifld_table[22] } },
1972     { 0, { (1<<MACH_BASE) } }  },
1973 /* ACCGi: source register */
1974   { "ACCGi", FRV_OPERAND_ACCGI, HW_H_ACCG, 17, 6,
1975     { 0, { (const PTR) &frv_cgen_ifld_table[17] } },
1976     { 0, { (1<<MACH_BASE) } }  },
1977 /* ACCGk: target register */
1978   { "ACCGk", FRV_OPERAND_ACCGK, HW_H_ACCG, 30, 6,
1979     { 0, { (const PTR) &frv_cgen_ifld_table[18] } },
1980     { 0, { (1<<MACH_BASE) } }  },
1981 /* CPRi: source register */
1982   { "CPRi", FRV_OPERAND_CPRI, HW_H_CPR, 17, 6,
1983     { 0, { (const PTR) &frv_cgen_ifld_table[14] } },
1984     { 0, { (1<<MACH_FRV) } }  },
1985 /* CPRj: source register */
1986   { "CPRj", FRV_OPERAND_CPRJ, HW_H_CPR, 5, 6,
1987     { 0, { (const PTR) &frv_cgen_ifld_table[15] } },
1988     { 0, { (1<<MACH_FRV) } }  },
1989 /* CPRk: destination register */
1990   { "CPRk", FRV_OPERAND_CPRK, HW_H_CPR, 30, 6,
1991     { 0, { (const PTR) &frv_cgen_ifld_table[16] } },
1992     { 0, { (1<<MACH_FRV) } }  },
1993 /* CPRdoublek: destination register */
1994   { "CPRdoublek", FRV_OPERAND_CPRDOUBLEK, HW_H_CPR_DOUBLE, 30, 6,
1995     { 0, { (const PTR) &frv_cgen_ifld_table[16] } },
1996     { 0, { (1<<MACH_FRV) } }  },
1997 /* FRinti: source register 1 */
1998   { "FRinti", FRV_OPERAND_FRINTI, HW_H_FR_INT, 17, 6,
1999     { 0, { (const PTR) &frv_cgen_ifld_table[11] } },
2000     { 0, { (1<<MACH_BASE) } }  },
2001 /* FRintj: source register 2 */
2002   { "FRintj", FRV_OPERAND_FRINTJ, HW_H_FR_INT, 5, 6,
2003     { 0, { (const PTR) &frv_cgen_ifld_table[12] } },
2004     { 0, { (1<<MACH_BASE) } }  },
2005 /* FRintk: target register */
2006   { "FRintk", FRV_OPERAND_FRINTK, HW_H_FR_INT, 30, 6,
2007     { 0, { (const PTR) &frv_cgen_ifld_table[13] } },
2008     { 0, { (1<<MACH_BASE) } }  },
2009 /* FRi: source register 1 */
2010   { "FRi", FRV_OPERAND_FRI, HW_H_FR, 17, 6,
2011     { 0, { (const PTR) &frv_cgen_ifld_table[11] } },
2012     { 0, { (1<<MACH_BASE) } }  },
2013 /* FRj: source register 2 */
2014   { "FRj", FRV_OPERAND_FRJ, HW_H_FR, 5, 6,
2015     { 0, { (const PTR) &frv_cgen_ifld_table[12] } },
2016     { 0, { (1<<MACH_BASE) } }  },
2017 /* FRk: destination register */
2018   { "FRk", FRV_OPERAND_FRK, HW_H_FR, 30, 6,
2019     { 0, { (const PTR) &frv_cgen_ifld_table[13] } },
2020     { 0, { (1<<MACH_BASE) } }  },
2021 /* FRkhi: destination register */
2022   { "FRkhi", FRV_OPERAND_FRKHI, HW_H_FR_HI, 30, 6,
2023     { 0, { (const PTR) &frv_cgen_ifld_table[13] } },
2024     { 0, { (1<<MACH_BASE) } }  },
2025 /* FRklo: destination register */
2026   { "FRklo", FRV_OPERAND_FRKLO, HW_H_FR_LO, 30, 6,
2027     { 0, { (const PTR) &frv_cgen_ifld_table[13] } },
2028     { 0, { (1<<MACH_BASE) } }  },
2029 /* FRdoublei: source register 1 */
2030   { "FRdoublei", FRV_OPERAND_FRDOUBLEI, HW_H_FR_DOUBLE, 17, 6,
2031     { 0, { (const PTR) &frv_cgen_ifld_table[11] } },
2032     { 0, { (1<<MACH_BASE) } }  },
2033 /* FRdoublej: source register 2 */
2034   { "FRdoublej", FRV_OPERAND_FRDOUBLEJ, HW_H_FR_DOUBLE, 5, 6,
2035     { 0, { (const PTR) &frv_cgen_ifld_table[12] } },
2036     { 0, { (1<<MACH_BASE) } }  },
2037 /* FRdoublek: target register */
2038   { "FRdoublek", FRV_OPERAND_FRDOUBLEK, HW_H_FR_DOUBLE, 30, 6,
2039     { 0, { (const PTR) &frv_cgen_ifld_table[13] } },
2040     { 0, { (1<<MACH_BASE) } }  },
2041 /* CRi: source register 1 */
2042   { "CRi", FRV_OPERAND_CRI, HW_H_CCCR, 14, 3,
2043     { 0, { (const PTR) &frv_cgen_ifld_table[23] } },
2044     { 0, { (1<<MACH_BASE) } }  },
2045 /* CRj: source register 2 */
2046   { "CRj", FRV_OPERAND_CRJ, HW_H_CCCR, 2, 3,
2047     { 0, { (const PTR) &frv_cgen_ifld_table[24] } },
2048     { 0, { (1<<MACH_BASE) } }  },
2049 /* CRj_int: destination register */
2050   { "CRj_int", FRV_OPERAND_CRJ_INT, HW_H_CCCR, 26, 2,
2051     { 0, { (const PTR) &frv_cgen_ifld_table[27] } },
2052     { 0, { (1<<MACH_BASE) } }  },
2053 /* CRj_float: destination register */
2054   { "CRj_float", FRV_OPERAND_CRJ_FLOAT, HW_H_CCCR, 26, 2,
2055     { 0, { (const PTR) &frv_cgen_ifld_table[28] } },
2056     { 0, { (1<<MACH_BASE) } }  },
2057 /* CRk: destination register */
2058   { "CRk", FRV_OPERAND_CRK, HW_H_CCCR, 27, 3,
2059     { 0, { (const PTR) &frv_cgen_ifld_table[25] } },
2060     { 0, { (1<<MACH_BASE) } }  },
2061 /* CCi: condition   register */
2062   { "CCi", FRV_OPERAND_CCI, HW_H_CCCR, 11, 3,
2063     { 0, { (const PTR) &frv_cgen_ifld_table[26] } },
2064     { 0, { (1<<MACH_BASE) } }  },
2065 /* ICCi_1: condition   register */
2066   { "ICCi_1", FRV_OPERAND_ICCI_1, HW_H_ICCR, 11, 2,
2067     { 0, { (const PTR) &frv_cgen_ifld_table[29] } },
2068     { 0, { (1<<MACH_BASE) } }  },
2069 /* ICCi_2: condition   register */
2070   { "ICCi_2", FRV_OPERAND_ICCI_2, HW_H_ICCR, 26, 2,
2071     { 0, { (const PTR) &frv_cgen_ifld_table[30] } },
2072     { 0, { (1<<MACH_BASE) } }  },
2073 /* ICCi_3: condition   register */
2074   { "ICCi_3", FRV_OPERAND_ICCI_3, HW_H_ICCR, 1, 2,
2075     { 0, { (const PTR) &frv_cgen_ifld_table[31] } },
2076     { 0, { (1<<MACH_BASE) } }  },
2077 /* FCCi_1: condition   register */
2078   { "FCCi_1", FRV_OPERAND_FCCI_1, HW_H_FCCR, 11, 2,
2079     { 0, { (const PTR) &frv_cgen_ifld_table[32] } },
2080     { 0, { (1<<MACH_BASE) } }  },
2081 /* FCCi_2: condition   register */
2082   { "FCCi_2", FRV_OPERAND_FCCI_2, HW_H_FCCR, 26, 2,
2083     { 0, { (const PTR) &frv_cgen_ifld_table[33] } },
2084     { 0, { (1<<MACH_BASE) } }  },
2085 /* FCCi_3: condition   register */
2086   { "FCCi_3", FRV_OPERAND_FCCI_3, HW_H_FCCR, 1, 2,
2087     { 0, { (const PTR) &frv_cgen_ifld_table[34] } },
2088     { 0, { (1<<MACH_BASE) } }  },
2089 /* FCCk: condition   register */
2090   { "FCCk", FRV_OPERAND_FCCK, HW_H_FCCR, 26, 2,
2091     { 0, { (const PTR) &frv_cgen_ifld_table[35] } },
2092     { 0, { (1<<MACH_BASE) } }  },
2093 /* eir: exception insn reg */
2094   { "eir", FRV_OPERAND_EIR, HW_H_UINT, 17, 6,
2095     { 0, { (const PTR) &frv_cgen_ifld_table[36] } },
2096     { 0, { (1<<MACH_BASE) } }  },
2097 /* s10: 10 bit signed immediate */
2098   { "s10", FRV_OPERAND_S10, HW_H_SINT, 9, 10,
2099     { 0, { (const PTR) &frv_cgen_ifld_table[37] } },
2100     { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
2101 /* u16: 16 bit unsigned immediate */
2102   { "u16", FRV_OPERAND_U16, HW_H_UINT, 15, 16,
2103     { 0, { (const PTR) &frv_cgen_ifld_table[40] } },
2104     { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
2105 /* s16: 16 bit signed   immediate */
2106   { "s16", FRV_OPERAND_S16, HW_H_SINT, 15, 16,
2107     { 0, { (const PTR) &frv_cgen_ifld_table[41] } },
2108     { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
2109 /* s6: 6  bit signed   immediate */
2110   { "s6", FRV_OPERAND_S6, HW_H_SINT, 5, 6,
2111     { 0, { (const PTR) &frv_cgen_ifld_table[42] } },
2112     { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
2113 /* s6_1: 6  bit signed   immediate */
2114   { "s6_1", FRV_OPERAND_S6_1, HW_H_SINT, 11, 6,
2115     { 0, { (const PTR) &frv_cgen_ifld_table[43] } },
2116     { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
2117 /* u6: 6  bit unsigned immediate */
2118   { "u6", FRV_OPERAND_U6, HW_H_UINT, 5, 6,
2119     { 0, { (const PTR) &frv_cgen_ifld_table[44] } },
2120     { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
2121 /* s5: 5  bit signed   immediate */
2122   { "s5", FRV_OPERAND_S5, HW_H_SINT, 4, 5,
2123     { 0, { (const PTR) &frv_cgen_ifld_table[45] } },
2124     { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
2125 /* cond: conditional arithmetic */
2126   { "cond", FRV_OPERAND_COND, HW_H_UINT, 8, 1,
2127     { 0, { (const PTR) &frv_cgen_ifld_table[50] } },
2128     { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
2129 /* ccond: lr branch condition */
2130   { "ccond", FRV_OPERAND_CCOND, HW_H_UINT, 12, 1,
2131     { 0, { (const PTR) &frv_cgen_ifld_table[51] } },
2132     { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
2133 /* hint: 2 bit branch predictor */
2134   { "hint", FRV_OPERAND_HINT, HW_H_UINT, 17, 2,
2135     { 0, { (const PTR) &frv_cgen_ifld_table[52] } },
2136     { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
2137 /* hint_taken: 2 bit branch predictor */
2138   { "hint_taken", FRV_OPERAND_HINT_TAKEN, HW_H_HINT_TAKEN, 17, 2,
2139     { 0, { (const PTR) &frv_cgen_ifld_table[52] } },
2140     { 0, { (1<<MACH_BASE) } }  },
2141 /* hint_not_taken: 2 bit branch predictor */
2142   { "hint_not_taken", FRV_OPERAND_HINT_NOT_TAKEN, HW_H_HINT_NOT_TAKEN, 17, 2,
2143     { 0, { (const PTR) &frv_cgen_ifld_table[52] } },
2144     { 0, { (1<<MACH_BASE) } }  },
2145 /* LI: link indicator */
2146   { "LI", FRV_OPERAND_LI, HW_H_UINT, 25, 1,
2147     { 0, { (const PTR) &frv_cgen_ifld_table[53] } },
2148     { 0, { (1<<MACH_BASE) } }  },
2149 /* lock: cache lock indicator */
2150   { "lock", FRV_OPERAND_LOCK, HW_H_UINT, 25, 1,
2151     { 0, { (const PTR) &frv_cgen_ifld_table[54] } },
2152     { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
2153 /* debug: debug mode indicator */
2154   { "debug", FRV_OPERAND_DEBUG, HW_H_UINT, 25, 1,
2155     { 0, { (const PTR) &frv_cgen_ifld_table[55] } },
2156     { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
2157 /* A: all accumulator indicator */
2158   { "A", FRV_OPERAND_A, HW_H_UINT, 17, 1,
2159     { 0, { (const PTR) &frv_cgen_ifld_table[56] } },
2160     { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
2161 /* ae: all entries indicator */
2162   { "ae", FRV_OPERAND_AE, HW_H_UINT, 25, 1,
2163     { 0, { (const PTR) &frv_cgen_ifld_table[57] } },
2164     { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
2165 /* label16: 18 bit pc relative address */
2166   { "label16", FRV_OPERAND_LABEL16, HW_H_IADDR, 15, 16,
2167     { 0, { (const PTR) &frv_cgen_ifld_table[60] } },
2168     { 0|A(PCREL_ADDR), { (1<<MACH_BASE) } }  },
2169 /* label24: 26 bit pc relative address */
2170   { "label24", FRV_OPERAND_LABEL24, HW_H_IADDR, 17, 24,
2171     { 2, { (const PTR) &FRV_F_LABEL24_MULTI_IFIELD[0] } },
2172     { 0|A(PCREL_ADDR)|A(VIRTUAL), { (1<<MACH_BASE) } }  },
2173 /* d12: 12 bit signed immediate */
2174   { "d12", FRV_OPERAND_D12, HW_H_SINT, 11, 12,
2175     { 0, { (const PTR) &frv_cgen_ifld_table[39] } },
2176     { 0, { (1<<MACH_BASE) } }  },
2177 /* s12: 12 bit signed immediate */
2178   { "s12", FRV_OPERAND_S12, HW_H_SINT, 11, 12,
2179     { 0, { (const PTR) &frv_cgen_ifld_table[39] } },
2180     { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
2181 /* u12: 12 bit signed immediate */
2182   { "u12", FRV_OPERAND_U12, HW_H_SINT, 5, 12,
2183     { 2, { (const PTR) &FRV_F_U12_MULTI_IFIELD[0] } },
2184     { 0|A(HASH_PREFIX)|A(VIRTUAL), { (1<<MACH_BASE) } }  },
2185 /* spr: special purpose register */
2186   { "spr", FRV_OPERAND_SPR, HW_H_SPR, 17, 12,
2187     { 2, { (const PTR) &FRV_F_SPR_MULTI_IFIELD[0] } },
2188     { 0|A(VIRTUAL), { (1<<MACH_BASE) } }  },
2189 /* ulo16: 16 bit unsigned immediate, for #lo() */
2190   { "ulo16", FRV_OPERAND_ULO16, HW_H_UINT, 15, 16,
2191     { 0, { (const PTR) &frv_cgen_ifld_table[40] } },
2192     { 0, { (1<<MACH_BASE) } }  },
2193 /* slo16: 16 bit unsigned immediate, for #lo() */
2194   { "slo16", FRV_OPERAND_SLO16, HW_H_SINT, 15, 16,
2195     { 0, { (const PTR) &frv_cgen_ifld_table[41] } },
2196     { 0, { (1<<MACH_BASE) } }  },
2197 /* uhi16: 16 bit unsigned immediate, for #hi() */
2198   { "uhi16", FRV_OPERAND_UHI16, HW_H_UINT, 15, 16,
2199     { 0, { (const PTR) &frv_cgen_ifld_table[40] } },
2200     { 0, { (1<<MACH_BASE) } }  },
2201 /* psr_esr: PSR.ESR bit */
2202   { "psr_esr", FRV_OPERAND_PSR_ESR, HW_H_PSR_ESR, 0, 0,
2203     { 0, { (const PTR) 0 } },
2204     { 0|A(SEM_ONLY), { (1<<MACH_BASE) } }  },
2205 /* psr_s: PSR.S   bit */
2206   { "psr_s", FRV_OPERAND_PSR_S, HW_H_PSR_S, 0, 0,
2207     { 0, { (const PTR) 0 } },
2208     { 0|A(SEM_ONLY), { (1<<MACH_BASE) } }  },
2209 /* psr_ps: PSR.PS  bit */
2210   { "psr_ps", FRV_OPERAND_PSR_PS, HW_H_PSR_PS, 0, 0,
2211     { 0, { (const PTR) 0 } },
2212     { 0|A(SEM_ONLY), { (1<<MACH_BASE) } }  },
2213 /* psr_et: PSR.ET  bit */
2214   { "psr_et", FRV_OPERAND_PSR_ET, HW_H_PSR_ET, 0, 0,
2215     { 0, { (const PTR) 0 } },
2216     { 0|A(SEM_ONLY), { (1<<MACH_BASE) } }  },
2217 /* bpsr_bs: BPSR.BS  bit */
2218   { "bpsr_bs", FRV_OPERAND_BPSR_BS, HW_H_BPSR_BS, 0, 0,
2219     { 0, { (const PTR) 0 } },
2220     { 0|A(SEM_ONLY), { (1<<MACH_BASE) } }  },
2221 /* bpsr_bet: BPSR.BET bit */
2222   { "bpsr_bet", FRV_OPERAND_BPSR_BET, HW_H_BPSR_BET, 0, 0,
2223     { 0, { (const PTR) 0 } },
2224     { 0|A(SEM_ONLY), { (1<<MACH_BASE) } }  },
2225 /* tbr_tba: TBR.TBA */
2226   { "tbr_tba", FRV_OPERAND_TBR_TBA, HW_H_TBR_TBA, 0, 0,
2227     { 0, { (const PTR) 0 } },
2228     { 0|A(SEM_ONLY), { (1<<MACH_BASE) } }  },
2229 /* tbr_tt: TBR.TT */
2230   { "tbr_tt", FRV_OPERAND_TBR_TT, HW_H_TBR_TT, 0, 0,
2231     { 0, { (const PTR) 0 } },
2232     { 0|A(SEM_ONLY), { (1<<MACH_BASE) } }  },
2233 /* sentinel */
2234   { 0, 0, 0, 0, 0,
2235     { 0, { (const PTR) 0 } },
2236     { 0, { 0 } } }
2237 };
2238
2239 #undef A
2240
2241
2242 /* The instruction table.  */
2243
2244 #define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
2245 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
2246 #define A(a) (1 << CGEN_INSN_##a)
2247 #else
2248 #define A(a) (1 << CGEN_INSN_/**/a)
2249 #endif
2250
2251 static const CGEN_IBASE frv_cgen_insn_table[MAX_INSNS] =
2252 {
2253   /* Special null first entry.
2254      A `num' value of zero is thus invalid.
2255      Also, the special `invalid' insn resides here.  */
2256   { 0, 0, 0, 0, {0, {0}} },
2257 /* add$pack $GRi,$GRj,$GRk */
2258   {
2259     FRV_INSN_ADD, "add", "add", 32,
2260     { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2261   },
2262 /* sub$pack $GRi,$GRj,$GRk */
2263   {
2264     FRV_INSN_SUB, "sub", "sub", 32,
2265     { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2266   },
2267 /* and$pack $GRi,$GRj,$GRk */
2268   {
2269     FRV_INSN_AND, "and", "and", 32,
2270     { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2271   },
2272 /* or$pack $GRi,$GRj,$GRk */
2273   {
2274     FRV_INSN_OR, "or", "or", 32,
2275     { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2276   },
2277 /* xor$pack $GRi,$GRj,$GRk */
2278   {
2279     FRV_INSN_XOR, "xor", "xor", 32,
2280     { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2281   },
2282 /* not$pack $GRj,$GRk */
2283   {
2284     FRV_INSN_NOT, "not", "not", 32,
2285     { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2286   },
2287 /* sdiv$pack $GRi,$GRj,$GRk */
2288   {
2289     FRV_INSN_SDIV, "sdiv", "sdiv", 32,
2290     { 0, { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2291   },
2292 /* nsdiv$pack $GRi,$GRj,$GRk */
2293   {
2294     FRV_INSN_NSDIV, "nsdiv", "nsdiv", 32,
2295     { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_MULT_DIV, FR400_MAJOR_NONE, FR500_MAJOR_I_1 } }
2296   },
2297 /* udiv$pack $GRi,$GRj,$GRk */
2298   {
2299     FRV_INSN_UDIV, "udiv", "udiv", 32,
2300     { 0, { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2301   },
2302 /* nudiv$pack $GRi,$GRj,$GRk */
2303   {
2304     FRV_INSN_NUDIV, "nudiv", "nudiv", 32,
2305     { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_MULT_DIV, FR400_MAJOR_NONE, FR500_MAJOR_I_1 } }
2306   },
2307 /* smul$pack $GRi,$GRj,$GRdoublek */
2308   {
2309     FRV_INSN_SMUL, "smul", "smul", 32,
2310     { 0, { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2311   },
2312 /* umul$pack $GRi,$GRj,$GRdoublek */
2313   {
2314     FRV_INSN_UMUL, "umul", "umul", 32,
2315     { 0, { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2316   },
2317 /* sll$pack $GRi,$GRj,$GRk */
2318   {
2319     FRV_INSN_SLL, "sll", "sll", 32,
2320     { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2321   },
2322 /* srl$pack $GRi,$GRj,$GRk */
2323   {
2324     FRV_INSN_SRL, "srl", "srl", 32,
2325     { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2326   },
2327 /* sra$pack $GRi,$GRj,$GRk */
2328   {
2329     FRV_INSN_SRA, "sra", "sra", 32,
2330     { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2331   },
2332 /* scan$pack $GRi,$GRj,$GRk */
2333   {
2334     FRV_INSN_SCAN, "scan", "scan", 32,
2335     { 0, { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2336   },
2337 /* cadd$pack $GRi,$GRj,$GRk,$CCi,$cond */
2338   {
2339     FRV_INSN_CADD, "cadd", "cadd", 32,
2340     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2341   },
2342 /* csub$pack $GRi,$GRj,$GRk,$CCi,$cond */
2343   {
2344     FRV_INSN_CSUB, "csub", "csub", 32,
2345     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2346   },
2347 /* cand$pack $GRi,$GRj,$GRk,$CCi,$cond */
2348   {
2349     FRV_INSN_CAND, "cand", "cand", 32,
2350     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2351   },
2352 /* cor$pack $GRi,$GRj,$GRk,$CCi,$cond */
2353   {
2354     FRV_INSN_COR, "cor", "cor", 32,
2355     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2356   },
2357 /* cxor$pack $GRi,$GRj,$GRk,$CCi,$cond */
2358   {
2359     FRV_INSN_CXOR, "cxor", "cxor", 32,
2360     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2361   },
2362 /* cnot$pack $GRj,$GRk,$CCi,$cond */
2363   {
2364     FRV_INSN_CNOT, "cnot", "cnot", 32,
2365     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2366   },
2367 /* csmul$pack $GRi,$GRj,$GRdoublek,$CCi,$cond */
2368   {
2369     FRV_INSN_CSMUL, "csmul", "csmul", 32,
2370     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2371   },
2372 /* csdiv$pack $GRi,$GRj,$GRk,$CCi,$cond */
2373   {
2374     FRV_INSN_CSDIV, "csdiv", "csdiv", 32,
2375     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2376   },
2377 /* cudiv$pack $GRi,$GRj,$GRk,$CCi,$cond */
2378   {
2379     FRV_INSN_CUDIV, "cudiv", "cudiv", 32,
2380     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2381   },
2382 /* csll$pack $GRi,$GRj,$GRk,$CCi,$cond */
2383   {
2384     FRV_INSN_CSLL, "csll", "csll", 32,
2385     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2386   },
2387 /* csrl$pack $GRi,$GRj,$GRk,$CCi,$cond */
2388   {
2389     FRV_INSN_CSRL, "csrl", "csrl", 32,
2390     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2391   },
2392 /* csra$pack $GRi,$GRj,$GRk,$CCi,$cond */
2393   {
2394     FRV_INSN_CSRA, "csra", "csra", 32,
2395     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2396   },
2397 /* cscan$pack $GRi,$GRj,$GRk,$CCi,$cond */
2398   {
2399     FRV_INSN_CSCAN, "cscan", "cscan", 32,
2400     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2401   },
2402 /* addcc$pack $GRi,$GRj,$GRk,$ICCi_1 */
2403   {
2404     FRV_INSN_ADDCC, "addcc", "addcc", 32,
2405     { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2406   },
2407 /* subcc$pack $GRi,$GRj,$GRk,$ICCi_1 */
2408   {
2409     FRV_INSN_SUBCC, "subcc", "subcc", 32,
2410     { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2411   },
2412 /* andcc$pack $GRi,$GRj,$GRk,$ICCi_1 */
2413   {
2414     FRV_INSN_ANDCC, "andcc", "andcc", 32,
2415     { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2416   },
2417 /* orcc$pack $GRi,$GRj,$GRk,$ICCi_1 */
2418   {
2419     FRV_INSN_ORCC, "orcc", "orcc", 32,
2420     { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2421   },
2422 /* xorcc$pack $GRi,$GRj,$GRk,$ICCi_1 */
2423   {
2424     FRV_INSN_XORCC, "xorcc", "xorcc", 32,
2425     { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2426   },
2427 /* sllcc$pack $GRi,$GRj,$GRk,$ICCi_1 */
2428   {
2429     FRV_INSN_SLLCC, "sllcc", "sllcc", 32,
2430     { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2431   },
2432 /* srlcc$pack $GRi,$GRj,$GRk,$ICCi_1 */
2433   {
2434     FRV_INSN_SRLCC, "srlcc", "srlcc", 32,
2435     { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2436   },
2437 /* sracc$pack $GRi,$GRj,$GRk,$ICCi_1 */
2438   {
2439     FRV_INSN_SRACC, "sracc", "sracc", 32,
2440     { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2441   },
2442 /* smulcc$pack $GRi,$GRj,$GRdoublek,$ICCi_1 */
2443   {
2444     FRV_INSN_SMULCC, "smulcc", "smulcc", 32,
2445     { 0, { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2446   },
2447 /* umulcc$pack $GRi,$GRj,$GRdoublek,$ICCi_1 */
2448   {
2449     FRV_INSN_UMULCC, "umulcc", "umulcc", 32,
2450     { 0, { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2451   },
2452 /* caddcc$pack $GRi,$GRj,$GRk,$CCi,$cond */
2453   {
2454     FRV_INSN_CADDCC, "caddcc", "caddcc", 32,
2455     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2456   },
2457 /* csubcc$pack $GRi,$GRj,$GRk,$CCi,$cond */
2458   {
2459     FRV_INSN_CSUBCC, "csubcc", "csubcc", 32,
2460     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2461   },
2462 /* csmulcc$pack $GRi,$GRj,$GRdoublek,$CCi,$cond */
2463   {
2464     FRV_INSN_CSMULCC, "csmulcc", "csmulcc", 32,
2465     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2466   },
2467 /* candcc$pack $GRi,$GRj,$GRk,$CCi,$cond */
2468   {
2469     FRV_INSN_CANDCC, "candcc", "candcc", 32,
2470     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2471   },
2472 /* corcc$pack $GRi,$GRj,$GRk,$CCi,$cond */
2473   {
2474     FRV_INSN_CORCC, "corcc", "corcc", 32,
2475     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2476   },
2477 /* cxorcc$pack $GRi,$GRj,$GRk,$CCi,$cond */
2478   {
2479     FRV_INSN_CXORCC, "cxorcc", "cxorcc", 32,
2480     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2481   },
2482 /* csllcc$pack $GRi,$GRj,$GRk,$CCi,$cond */
2483   {
2484     FRV_INSN_CSLLCC, "csllcc", "csllcc", 32,
2485     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2486   },
2487 /* csrlcc$pack $GRi,$GRj,$GRk,$CCi,$cond */
2488   {
2489     FRV_INSN_CSRLCC, "csrlcc", "csrlcc", 32,
2490     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2491   },
2492 /* csracc$pack $GRi,$GRj,$GRk,$CCi,$cond */
2493   {
2494     FRV_INSN_CSRACC, "csracc", "csracc", 32,
2495     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2496   },
2497 /* addx$pack $GRi,$GRj,$GRk,$ICCi_1 */
2498   {
2499     FRV_INSN_ADDX, "addx", "addx", 32,
2500     { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2501   },
2502 /* subx$pack $GRi,$GRj,$GRk,$ICCi_1 */
2503   {
2504     FRV_INSN_SUBX, "subx", "subx", 32,
2505     { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2506   },
2507 /* addxcc$pack $GRi,$GRj,$GRk,$ICCi_1 */
2508   {
2509     FRV_INSN_ADDXCC, "addxcc", "addxcc", 32,
2510     { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2511   },
2512 /* subxcc$pack $GRi,$GRj,$GRk,$ICCi_1 */
2513   {
2514     FRV_INSN_SUBXCC, "subxcc", "subxcc", 32,
2515     { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2516   },
2517 /* addi$pack $GRi,$s12,$GRk */
2518   {
2519     FRV_INSN_ADDI, "addi", "addi", 32,
2520     { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2521   },
2522 /* subi$pack $GRi,$s12,$GRk */
2523   {
2524     FRV_INSN_SUBI, "subi", "subi", 32,
2525     { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2526   },
2527 /* andi$pack $GRi,$s12,$GRk */
2528   {
2529     FRV_INSN_ANDI, "andi", "andi", 32,
2530     { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2531   },
2532 /* ori$pack $GRi,$s12,$GRk */
2533   {
2534     FRV_INSN_ORI, "ori", "ori", 32,
2535     { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2536   },
2537 /* xori$pack $GRi,$s12,$GRk */
2538   {
2539     FRV_INSN_XORI, "xori", "xori", 32,
2540     { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2541   },
2542 /* sdivi$pack $GRi,$s12,$GRk */
2543   {
2544     FRV_INSN_SDIVI, "sdivi", "sdivi", 32,
2545     { 0, { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2546   },
2547 /* nsdivi$pack $GRi,$s12,$GRk */
2548   {
2549     FRV_INSN_NSDIVI, "nsdivi", "nsdivi", 32,
2550     { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_MULT_DIV, FR400_MAJOR_NONE, FR500_MAJOR_I_1 } }
2551   },
2552 /* udivi$pack $GRi,$s12,$GRk */
2553   {
2554     FRV_INSN_UDIVI, "udivi", "udivi", 32,
2555     { 0, { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2556   },
2557 /* nudivi$pack $GRi,$s12,$GRk */
2558   {
2559     FRV_INSN_NUDIVI, "nudivi", "nudivi", 32,
2560     { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_MULT_DIV, FR400_MAJOR_NONE, FR500_MAJOR_I_1 } }
2561   },
2562 /* smuli$pack $GRi,$s12,$GRdoublek */
2563   {
2564     FRV_INSN_SMULI, "smuli", "smuli", 32,
2565     { 0, { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2566   },
2567 /* umuli$pack $GRi,$s12,$GRdoublek */
2568   {
2569     FRV_INSN_UMULI, "umuli", "umuli", 32,
2570     { 0, { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2571   },
2572 /* slli$pack $GRi,$s12,$GRk */
2573   {
2574     FRV_INSN_SLLI, "slli", "slli", 32,
2575     { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2576   },
2577 /* srli$pack $GRi,$s12,$GRk */
2578   {
2579     FRV_INSN_SRLI, "srli", "srli", 32,
2580     { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2581   },
2582 /* srai$pack $GRi,$s12,$GRk */
2583   {
2584     FRV_INSN_SRAI, "srai", "srai", 32,
2585     { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2586   },
2587 /* scani$pack $GRi,$s12,$GRk */
2588   {
2589     FRV_INSN_SCANI, "scani", "scani", 32,
2590     { 0, { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2591   },
2592 /* addicc$pack $GRi,$s10,$GRk,$ICCi_1 */
2593   {
2594     FRV_INSN_ADDICC, "addicc", "addicc", 32,
2595     { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2596   },
2597 /* subicc$pack $GRi,$s10,$GRk,$ICCi_1 */
2598   {
2599     FRV_INSN_SUBICC, "subicc", "subicc", 32,
2600     { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2601   },
2602 /* andicc$pack $GRi,$s10,$GRk,$ICCi_1 */
2603   {
2604     FRV_INSN_ANDICC, "andicc", "andicc", 32,
2605     { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2606   },
2607 /* oricc$pack $GRi,$s10,$GRk,$ICCi_1 */
2608   {
2609     FRV_INSN_ORICC, "oricc", "oricc", 32,
2610     { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2611   },
2612 /* xoricc$pack $GRi,$s10,$GRk,$ICCi_1 */
2613   {
2614     FRV_INSN_XORICC, "xoricc", "xoricc", 32,
2615     { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2616   },
2617 /* smulicc$pack $GRi,$s10,$GRdoublek,$ICCi_1 */
2618   {
2619     FRV_INSN_SMULICC, "smulicc", "smulicc", 32,
2620     { 0, { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2621   },
2622 /* umulicc$pack $GRi,$s10,$GRdoublek,$ICCi_1 */
2623   {
2624     FRV_INSN_UMULICC, "umulicc", "umulicc", 32,
2625     { 0, { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2626   },
2627 /* sllicc$pack $GRi,$s10,$GRk,$ICCi_1 */
2628   {
2629     FRV_INSN_SLLICC, "sllicc", "sllicc", 32,
2630     { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2631   },
2632 /* srlicc$pack $GRi,$s10,$GRk,$ICCi_1 */
2633   {
2634     FRV_INSN_SRLICC, "srlicc", "srlicc", 32,
2635     { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2636   },
2637 /* sraicc$pack $GRi,$s10,$GRk,$ICCi_1 */
2638   {
2639     FRV_INSN_SRAICC, "sraicc", "sraicc", 32,
2640     { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2641   },
2642 /* addxi$pack $GRi,$s10,$GRk,$ICCi_1 */
2643   {
2644     FRV_INSN_ADDXI, "addxi", "addxi", 32,
2645     { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2646   },
2647 /* subxi$pack $GRi,$s10,$GRk,$ICCi_1 */
2648   {
2649     FRV_INSN_SUBXI, "subxi", "subxi", 32,
2650     { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2651   },
2652 /* addxicc$pack $GRi,$s10,$GRk,$ICCi_1 */
2653   {
2654     FRV_INSN_ADDXICC, "addxicc", "addxicc", 32,
2655     { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2656   },
2657 /* subxicc$pack $GRi,$s10,$GRk,$ICCi_1 */
2658   {
2659     FRV_INSN_SUBXICC, "subxicc", "subxicc", 32,
2660     { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2661   },
2662 /* cmpb$pack $GRi,$GRj,$ICCi_1 */
2663   {
2664     FRV_INSN_CMPB, "cmpb", "cmpb", 32,
2665     { 0, { (1<<MACH_FR400), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_NONE } }
2666   },
2667 /* cmpba$pack $GRi,$GRj,$ICCi_1 */
2668   {
2669     FRV_INSN_CMPBA, "cmpba", "cmpba", 32,
2670     { 0, { (1<<MACH_FR400), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_NONE } }
2671   },
2672 /* setlo$pack $ulo16,$GRklo */
2673   {
2674     FRV_INSN_SETLO, "setlo", "setlo", 32,
2675     { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2676   },
2677 /* sethi$pack $uhi16,$GRkhi */
2678   {
2679     FRV_INSN_SETHI, "sethi", "sethi", 32,
2680     { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2681   },
2682 /* setlos$pack $slo16,$GRk */
2683   {
2684     FRV_INSN_SETLOS, "setlos", "setlos", 32,
2685     { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2686   },
2687 /* ldsb$pack @($GRi,$GRj),$GRk */
2688   {
2689     FRV_INSN_LDSB, "ldsb", "ldsb", 32,
2690     { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
2691   },
2692 /* ldub$pack @($GRi,$GRj),$GRk */
2693   {
2694     FRV_INSN_LDUB, "ldub", "ldub", 32,
2695     { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
2696   },
2697 /* ldsh$pack @($GRi,$GRj),$GRk */
2698   {
2699     FRV_INSN_LDSH, "ldsh", "ldsh", 32,
2700     { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
2701   },
2702 /* lduh$pack @($GRi,$GRj),$GRk */
2703   {
2704     FRV_INSN_LDUH, "lduh", "lduh", 32,
2705     { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
2706   },
2707 /* ld$pack @($GRi,$GRj),$GRk */
2708   {
2709     FRV_INSN_LD, "ld", "ld", 32,
2710     { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
2711   },
2712 /* ldbf$pack @($GRi,$GRj),$FRintk */
2713   {
2714     FRV_INSN_LDBF, "ldbf", "ldbf", 32,
2715     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
2716   },
2717 /* ldhf$pack @($GRi,$GRj),$FRintk */
2718   {
2719     FRV_INSN_LDHF, "ldhf", "ldhf", 32,
2720     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
2721   },
2722 /* ldf$pack @($GRi,$GRj),$FRintk */
2723   {
2724     FRV_INSN_LDF, "ldf", "ldf", 32,
2725     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
2726   },
2727 /* ldc$pack @($GRi,$GRj),$CPRk */
2728   {
2729     FRV_INSN_LDC, "ldc", "ldc", 32,
2730     { 0, { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
2731   },
2732 /* nldsb$pack @($GRi,$GRj),$GRk */
2733   {
2734     FRV_INSN_NLDSB, "nldsb", "nldsb", 32,
2735     { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
2736   },
2737 /* nldub$pack @($GRi,$GRj),$GRk */
2738   {
2739     FRV_INSN_NLDUB, "nldub", "nldub", 32,
2740     { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
2741   },
2742 /* nldsh$pack @($GRi,$GRj),$GRk */
2743   {
2744     FRV_INSN_NLDSH, "nldsh", "nldsh", 32,
2745     { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
2746   },
2747 /* nlduh$pack @($GRi,$GRj),$GRk */
2748   {
2749     FRV_INSN_NLDUH, "nlduh", "nlduh", 32,
2750     { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
2751   },
2752 /* nld$pack @($GRi,$GRj),$GRk */
2753   {
2754     FRV_INSN_NLD, "nld", "nld", 32,
2755     { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
2756   },
2757 /* nldbf$pack @($GRi,$GRj),$FRintk */
2758   {
2759     FRV_INSN_NLDBF, "nldbf", "nldbf", 32,
2760     { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
2761   },
2762 /* nldhf$pack @($GRi,$GRj),$FRintk */
2763   {
2764     FRV_INSN_NLDHF, "nldhf", "nldhf", 32,
2765     { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
2766   },
2767 /* nldf$pack @($GRi,$GRj),$FRintk */
2768   {
2769     FRV_INSN_NLDF, "nldf", "nldf", 32,
2770     { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
2771   },
2772 /* ldd$pack @($GRi,$GRj),$GRdoublek */
2773   {
2774     FRV_INSN_LDD, "ldd", "ldd", 32,
2775     { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
2776   },
2777 /* lddf$pack @($GRi,$GRj),$FRdoublek */
2778   {
2779     FRV_INSN_LDDF, "lddf", "lddf", 32,
2780     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
2781   },
2782 /* lddc$pack @($GRi,$GRj),$CPRdoublek */
2783   {
2784     FRV_INSN_LDDC, "lddc", "lddc", 32,
2785     { 0, { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
2786   },
2787 /* nldd$pack @($GRi,$GRj),$GRdoublek */
2788   {
2789     FRV_INSN_NLDD, "nldd", "nldd", 32,
2790     { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
2791   },
2792 /* nlddf$pack @($GRi,$GRj),$FRdoublek */
2793   {
2794     FRV_INSN_NLDDF, "nlddf", "nlddf", 32,
2795     { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
2796   },
2797 /* ldq$pack @($GRi,$GRj),$GRk */
2798   {
2799     FRV_INSN_LDQ, "ldq", "ldq", 32,
2800     { 0, { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
2801   },
2802 /* ldqf$pack @($GRi,$GRj),$FRintk */
2803   {
2804     FRV_INSN_LDQF, "ldqf", "ldqf", 32,
2805     { 0|A(FR_ACCESS), { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
2806   },
2807 /* ldqc$pack @($GRi,$GRj),$CPRk */
2808   {
2809     FRV_INSN_LDQC, "ldqc", "ldqc", 32,
2810     { 0, { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
2811   },
2812 /* nldq$pack @($GRi,$GRj),$GRk */
2813   {
2814     FRV_INSN_NLDQ, "nldq", "nldq", 32,
2815     { 0|A(NON_EXCEPTING), { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
2816   },
2817 /* nldqf$pack @($GRi,$GRj),$FRintk */
2818   {
2819     FRV_INSN_NLDQF, "nldqf", "nldqf", 32,
2820     { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
2821   },
2822 /* ldsbu$pack @($GRi,$GRj),$GRk */
2823   {
2824     FRV_INSN_LDSBU, "ldsbu", "ldsbu", 32,
2825     { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
2826   },
2827 /* ldubu$pack @($GRi,$GRj),$GRk */
2828   {
2829     FRV_INSN_LDUBU, "ldubu", "ldubu", 32,
2830     { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
2831   },
2832 /* ldshu$pack @($GRi,$GRj),$GRk */
2833   {
2834     FRV_INSN_LDSHU, "ldshu", "ldshu", 32,
2835     { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
2836   },
2837 /* lduhu$pack @($GRi,$GRj),$GRk */
2838   {
2839     FRV_INSN_LDUHU, "lduhu", "lduhu", 32,
2840     { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
2841   },
2842 /* ldu$pack @($GRi,$GRj),$GRk */
2843   {
2844     FRV_INSN_LDU, "ldu", "ldu", 32,
2845     { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
2846   },
2847 /* nldsbu$pack @($GRi,$GRj),$GRk */
2848   {
2849     FRV_INSN_NLDSBU, "nldsbu", "nldsbu", 32,
2850     { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
2851   },
2852 /* nldubu$pack @($GRi,$GRj),$GRk */
2853   {
2854     FRV_INSN_NLDUBU, "nldubu", "nldubu", 32,
2855     { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
2856   },
2857 /* nldshu$pack @($GRi,$GRj),$GRk */
2858   {
2859     FRV_INSN_NLDSHU, "nldshu", "nldshu", 32,
2860     { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
2861   },
2862 /* nlduhu$pack @($GRi,$GRj),$GRk */
2863   {
2864     FRV_INSN_NLDUHU, "nlduhu", "nlduhu", 32,
2865     { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
2866   },
2867 /* nldu$pack @($GRi,$GRj),$GRk */
2868   {
2869     FRV_INSN_NLDU, "nldu", "nldu", 32,
2870     { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
2871   },
2872 /* ldbfu$pack @($GRi,$GRj),$FRintk */
2873   {
2874     FRV_INSN_LDBFU, "ldbfu", "ldbfu", 32,
2875     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
2876   },
2877 /* ldhfu$pack @($GRi,$GRj),$FRintk */
2878   {
2879     FRV_INSN_LDHFU, "ldhfu", "ldhfu", 32,
2880     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
2881   },
2882 /* ldfu$pack @($GRi,$GRj),$FRintk */
2883   {
2884     FRV_INSN_LDFU, "ldfu", "ldfu", 32,
2885     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
2886   },
2887 /* ldcu$pack @($GRi,$GRj),$CPRk */
2888   {
2889     FRV_INSN_LDCU, "ldcu", "ldcu", 32,
2890     { 0, { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
2891   },
2892 /* nldbfu$pack @($GRi,$GRj),$FRintk */
2893   {
2894     FRV_INSN_NLDBFU, "nldbfu", "nldbfu", 32,
2895     { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
2896   },
2897 /* nldhfu$pack @($GRi,$GRj),$FRintk */
2898   {
2899     FRV_INSN_NLDHFU, "nldhfu", "nldhfu", 32,
2900     { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
2901   },
2902 /* nldfu$pack @($GRi,$GRj),$FRintk */
2903   {
2904     FRV_INSN_NLDFU, "nldfu", "nldfu", 32,
2905     { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
2906   },
2907 /* lddu$pack @($GRi,$GRj),$GRdoublek */
2908   {
2909     FRV_INSN_LDDU, "lddu", "lddu", 32,
2910     { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
2911   },
2912 /* nlddu$pack @($GRi,$GRj),$GRdoublek */
2913   {
2914     FRV_INSN_NLDDU, "nlddu", "nlddu", 32,
2915     { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
2916   },
2917 /* lddfu$pack @($GRi,$GRj),$FRdoublek */
2918   {
2919     FRV_INSN_LDDFU, "lddfu", "lddfu", 32,
2920     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
2921   },
2922 /* lddcu$pack @($GRi,$GRj),$CPRdoublek */
2923   {
2924     FRV_INSN_LDDCU, "lddcu", "lddcu", 32,
2925     { 0, { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
2926   },
2927 /* nlddfu$pack @($GRi,$GRj),$FRdoublek */
2928   {
2929     FRV_INSN_NLDDFU, "nlddfu", "nlddfu", 32,
2930     { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
2931   },
2932 /* ldqu$pack @($GRi,$GRj),$GRk */
2933   {
2934     FRV_INSN_LDQU, "ldqu", "ldqu", 32,
2935     { 0, { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
2936   },
2937 /* nldqu$pack @($GRi,$GRj),$GRk */
2938   {
2939     FRV_INSN_NLDQU, "nldqu", "nldqu", 32,
2940     { 0|A(NON_EXCEPTING), { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
2941   },
2942 /* ldqfu$pack @($GRi,$GRj),$FRintk */
2943   {
2944     FRV_INSN_LDQFU, "ldqfu", "ldqfu", 32,
2945     { 0|A(FR_ACCESS), { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
2946   },
2947 /* ldqcu$pack @($GRi,$GRj),$CPRk */
2948   {
2949     FRV_INSN_LDQCU, "ldqcu", "ldqcu", 32,
2950     { 0, { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
2951   },
2952 /* nldqfu$pack @($GRi,$GRj),$FRintk */
2953   {
2954     FRV_INSN_NLDQFU, "nldqfu", "nldqfu", 32,
2955     { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
2956   },
2957 /* ldsbi$pack @($GRi,$d12),$GRk */
2958   {
2959     FRV_INSN_LDSBI, "ldsbi", "ldsbi", 32,
2960     { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
2961   },
2962 /* ldshi$pack @($GRi,$d12),$GRk */
2963   {
2964     FRV_INSN_LDSHI, "ldshi", "ldshi", 32,
2965     { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
2966   },
2967 /* ldi$pack @($GRi,$d12),$GRk */
2968   {
2969     FRV_INSN_LDI, "ldi", "ldi", 32,
2970     { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
2971   },
2972 /* ldubi$pack @($GRi,$d12),$GRk */
2973   {
2974     FRV_INSN_LDUBI, "ldubi", "ldubi", 32,
2975     { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
2976   },
2977 /* lduhi$pack @($GRi,$d12),$GRk */
2978   {
2979     FRV_INSN_LDUHI, "lduhi", "lduhi", 32,
2980     { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
2981   },
2982 /* ldbfi$pack @($GRi,$d12),$FRintk */
2983   {
2984     FRV_INSN_LDBFI, "ldbfi", "ldbfi", 32,
2985     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
2986   },
2987 /* ldhfi$pack @($GRi,$d12),$FRintk */
2988   {
2989     FRV_INSN_LDHFI, "ldhfi", "ldhfi", 32,
2990     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
2991   },
2992 /* ldfi$pack @($GRi,$d12),$FRintk */
2993   {
2994     FRV_INSN_LDFI, "ldfi", "ldfi", 32,
2995     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
2996   },
2997 /* nldsbi$pack @($GRi,$d12),$GRk */
2998   {
2999     FRV_INSN_NLDSBI, "nldsbi", "nldsbi", 32,
3000     { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
3001   },
3002 /* nldubi$pack @($GRi,$d12),$GRk */
3003   {
3004     FRV_INSN_NLDUBI, "nldubi", "nldubi", 32,
3005     { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
3006   },
3007 /* nldshi$pack @($GRi,$d12),$GRk */
3008   {
3009     FRV_INSN_NLDSHI, "nldshi", "nldshi", 32,
3010     { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
3011   },
3012 /* nlduhi$pack @($GRi,$d12),$GRk */
3013   {
3014     FRV_INSN_NLDUHI, "nlduhi", "nlduhi", 32,
3015     { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
3016   },
3017 /* nldi$pack @($GRi,$d12),$GRk */
3018   {
3019     FRV_INSN_NLDI, "nldi", "nldi", 32,
3020     { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
3021   },
3022 /* nldbfi$pack @($GRi,$d12),$FRintk */
3023   {
3024     FRV_INSN_NLDBFI, "nldbfi", "nldbfi", 32,
3025     { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
3026   },
3027 /* nldhfi$pack @($GRi,$d12),$FRintk */
3028   {
3029     FRV_INSN_NLDHFI, "nldhfi", "nldhfi", 32,
3030     { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
3031   },
3032 /* nldfi$pack @($GRi,$d12),$FRintk */
3033   {
3034     FRV_INSN_NLDFI, "nldfi", "nldfi", 32,
3035     { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
3036   },
3037 /* lddi$pack @($GRi,$d12),$GRdoublek */
3038   {
3039     FRV_INSN_LDDI, "lddi", "lddi", 32,
3040     { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
3041   },
3042 /* lddfi$pack @($GRi,$d12),$FRdoublek */
3043   {
3044     FRV_INSN_LDDFI, "lddfi", "lddfi", 32,
3045     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
3046   },
3047 /* nlddi$pack @($GRi,$d12),$GRdoublek */
3048   {
3049     FRV_INSN_NLDDI, "nlddi", "nlddi", 32,
3050     { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
3051   },
3052 /* nlddfi$pack @($GRi,$d12),$FRdoublek */
3053   {
3054     FRV_INSN_NLDDFI, "nlddfi", "nlddfi", 32,
3055     { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
3056   },
3057 /* ldqi$pack @($GRi,$d12),$GRk */
3058   {
3059     FRV_INSN_LDQI, "ldqi", "ldqi", 32,
3060     { 0, { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
3061   },
3062 /* ldqfi$pack @($GRi,$d12),$FRintk */
3063   {
3064     FRV_INSN_LDQFI, "ldqfi", "ldqfi", 32,
3065     { 0|A(FR_ACCESS), { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
3066   },
3067 /* nldqi$pack @($GRi,$d12),$GRk */
3068   {
3069     FRV_INSN_NLDQI, "nldqi", "nldqi", 32,
3070     { 0|A(NON_EXCEPTING), { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
3071   },
3072 /* nldqfi$pack @($GRi,$d12),$FRintk */
3073   {
3074     FRV_INSN_NLDQFI, "nldqfi", "nldqfi", 32,
3075     { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
3076   },
3077 /* stb$pack $GRk,@($GRi,$GRj) */
3078   {
3079     FRV_INSN_STB, "stb", "stb", 32,
3080     { 0, { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
3081   },
3082 /* sth$pack $GRk,@($GRi,$GRj) */
3083   {
3084     FRV_INSN_STH, "sth", "sth", 32,
3085     { 0, { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
3086   },
3087 /* st$pack $GRk,@($GRi,$GRj) */
3088   {
3089     FRV_INSN_ST, "st", "st", 32,
3090     { 0, { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
3091   },
3092 /* stbf$pack $FRintk,@($GRi,$GRj) */
3093   {
3094     FRV_INSN_STBF, "stbf", "stbf", 32,
3095     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
3096   },
3097 /* sthf$pack $FRintk,@($GRi,$GRj) */
3098   {
3099     FRV_INSN_STHF, "sthf", "sthf", 32,
3100     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
3101   },
3102 /* stf$pack $FRintk,@($GRi,$GRj) */
3103   {
3104     FRV_INSN_STF, "stf", "stf", 32,
3105     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
3106   },
3107 /* stc$pack $CPRk,@($GRi,$GRj) */
3108   {
3109     FRV_INSN_STC, "stc", "stc", 32,
3110     { 0, { (1<<MACH_FRV), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
3111   },
3112 /* rstb$pack $GRk,@($GRi,$GRj) */
3113   {
3114     FRV_INSN_RSTB, "rstb", "rstb", 32,
3115     { 0, { (1<<MACH_FRV), UNIT_I0, FR400_MAJOR_NONE, FR500_MAJOR_I_3 } }
3116   },
3117 /* rsth$pack $GRk,@($GRi,$GRj) */
3118   {
3119     FRV_INSN_RSTH, "rsth", "rsth", 32,
3120     { 0, { (1<<MACH_FRV), UNIT_I0, FR400_MAJOR_NONE, FR500_MAJOR_I_3 } }
3121   },
3122 /* rst$pack $GRk,@($GRi,$GRj) */
3123   {
3124     FRV_INSN_RST, "rst", "rst", 32,
3125     { 0, { (1<<MACH_FRV), UNIT_I0, FR400_MAJOR_NONE, FR500_MAJOR_I_3 } }
3126   },
3127 /* rstbf$pack $FRintk,@($GRi,$GRj) */
3128   {
3129     FRV_INSN_RSTBF, "rstbf", "rstbf", 32,
3130     { 0, { (1<<MACH_FRV), UNIT_I0, FR400_MAJOR_NONE, FR500_MAJOR_I_3 } }
3131   },
3132 /* rsthf$pack $FRintk,@($GRi,$GRj) */
3133   {
3134     FRV_INSN_RSTHF, "rsthf", "rsthf", 32,
3135     { 0, { (1<<MACH_FRV), UNIT_I0, FR400_MAJOR_NONE, FR500_MAJOR_I_3 } }
3136   },
3137 /* rstf$pack $FRintk,@($GRi,$GRj) */
3138   {
3139     FRV_INSN_RSTF, "rstf", "rstf", 32,
3140     { 0, { (1<<MACH_FRV), UNIT_I0, FR400_MAJOR_NONE, FR500_MAJOR_I_3 } }
3141   },
3142 /* std$pack $GRk,@($GRi,$GRj) */
3143   {
3144     FRV_INSN_STD, "std", "std", 32,
3145     { 0, { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
3146   },
3147 /* stdf$pack $FRk,@($GRi,$GRj) */
3148   {
3149     FRV_INSN_STDF, "stdf", "stdf", 32,
3150     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
3151   },
3152 /* stdc$pack $CPRk,@($GRi,$GRj) */
3153   {
3154     FRV_INSN_STDC, "stdc", "stdc", 32,
3155     { 0, { (1<<MACH_FRV), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
3156   },
3157 /* rstd$pack $GRk,@($GRi,$GRj) */
3158   {
3159     FRV_INSN_RSTD, "rstd", "rstd", 32,
3160     { 0, { (1<<MACH_FRV), UNIT_I0, FR400_MAJOR_NONE, FR500_MAJOR_I_3 } }
3161   },
3162 /* rstdf$pack $FRk,@($GRi,$GRj) */
3163   {
3164     FRV_INSN_RSTDF, "rstdf", "rstdf", 32,
3165     { 0|A(FR_ACCESS), { (1<<MACH_FRV), UNIT_I0, FR400_MAJOR_NONE, FR500_MAJOR_I_3 } }
3166   },
3167 /* stq$pack $GRk,@($GRi,$GRj) */
3168   {
3169     FRV_INSN_STQ, "stq", "stq", 32,
3170     { 0, { (1<<MACH_FRV), UNIT_I0, FR400_MAJOR_NONE, FR500_MAJOR_I_3 } }
3171   },
3172 /* stqf$pack $FRintk,@($GRi,$GRj) */
3173   {
3174     FRV_INSN_STQF, "stqf", "stqf", 32,
3175     { 0|A(FR_ACCESS), { (1<<MACH_FRV), UNIT_I0, FR400_MAJOR_NONE, FR500_MAJOR_I_3 } }
3176   },
3177 /* stqc$pack $CPRk,@($GRi,$GRj) */
3178   {
3179     FRV_INSN_STQC, "stqc", "stqc", 32,
3180     { 0, { (1<<MACH_FRV), UNIT_I0, FR400_MAJOR_NONE, FR500_MAJOR_I_3 } }
3181   },
3182 /* rstq$pack $GRk,@($GRi,$GRj) */
3183   {
3184     FRV_INSN_RSTQ, "rstq", "rstq", 32,
3185     { 0, { (1<<MACH_FRV), UNIT_I0, FR400_MAJOR_NONE, FR500_MAJOR_I_3 } }
3186   },
3187 /* rstqf$pack $FRintk,@($GRi,$GRj) */
3188   {
3189     FRV_INSN_RSTQF, "rstqf", "rstqf", 32,
3190     { 0|A(FR_ACCESS), { (1<<MACH_FRV), UNIT_I0, FR400_MAJOR_NONE, FR500_MAJOR_I_3 } }
3191   },
3192 /* stbu$pack $GRk,@($GRi,$GRj) */
3193   {
3194     FRV_INSN_STBU, "stbu", "stbu", 32,
3195     { 0, { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
3196   },
3197 /* sthu$pack $GRk,@($GRi,$GRj) */
3198   {
3199     FRV_INSN_STHU, "sthu", "sthu", 32,
3200     { 0, { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
3201   },
3202 /* stu$pack $GRk,@($GRi,$GRj) */
3203   {
3204     FRV_INSN_STU, "stu", "stu", 32,
3205     { 0, { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
3206   },
3207 /* stbfu$pack $FRintk,@($GRi,$GRj) */
3208   {
3209     FRV_INSN_STBFU, "stbfu", "stbfu", 32,
3210     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
3211   },
3212 /* sthfu$pack $FRintk,@($GRi,$GRj) */
3213   {
3214     FRV_INSN_STHFU, "sthfu", "sthfu", 32,
3215     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
3216   },
3217 /* stfu$pack $FRintk,@($GRi,$GRj) */
3218   {
3219     FRV_INSN_STFU, "stfu", "stfu", 32,
3220     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
3221   },
3222 /* stcu$pack $CPRk,@($GRi,$GRj) */
3223   {
3224     FRV_INSN_STCU, "stcu", "stcu", 32,
3225     { 0, { (1<<MACH_FRV), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
3226   },
3227 /* stdu$pack $GRk,@($GRi,$GRj) */
3228   {
3229     FRV_INSN_STDU, "stdu", "stdu", 32,
3230     { 0, { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
3231   },
3232 /* stdfu$pack $FRk,@($GRi,$GRj) */
3233   {
3234     FRV_INSN_STDFU, "stdfu", "stdfu", 32,
3235     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
3236   },
3237 /* stdcu$pack $CPRk,@($GRi,$GRj) */
3238   {
3239     FRV_INSN_STDCU, "stdcu", "stdcu", 32,
3240     { 0, { (1<<MACH_FRV), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
3241   },
3242 /* stqu$pack $GRk,@($GRi,$GRj) */
3243   {
3244     FRV_INSN_STQU, "stqu", "stqu", 32,
3245     { 0, { (1<<MACH_FRV), UNIT_I0, FR400_MAJOR_NONE, FR500_MAJOR_I_3 } }
3246   },
3247 /* stqfu$pack $FRintk,@($GRi,$GRj) */
3248   {
3249     FRV_INSN_STQFU, "stqfu", "stqfu", 32,
3250     { 0|A(FR_ACCESS), { (1<<MACH_FRV), UNIT_I0, FR400_MAJOR_NONE, FR500_MAJOR_I_3 } }
3251   },
3252 /* stqcu$pack $CPRk,@($GRi,$GRj) */
3253   {
3254     FRV_INSN_STQCU, "stqcu", "stqcu", 32,
3255     { 0, { (1<<MACH_FRV), UNIT_I0, FR400_MAJOR_NONE, FR500_MAJOR_I_3 } }
3256   },
3257 /* cldsb$pack @($GRi,$GRj),$GRk,$CCi,$cond */
3258   {
3259     FRV_INSN_CLDSB, "cldsb", "cldsb", 32,
3260     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
3261   },
3262 /* cldub$pack @($GRi,$GRj),$GRk,$CCi,$cond */
3263   {
3264     FRV_INSN_CLDUB, "cldub", "cldub", 32,
3265     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
3266   },
3267 /* cldsh$pack @($GRi,$GRj),$GRk,$CCi,$cond */
3268   {
3269     FRV_INSN_CLDSH, "cldsh", "cldsh", 32,
3270     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
3271   },
3272 /* clduh$pack @($GRi,$GRj),$GRk,$CCi,$cond */
3273   {
3274     FRV_INSN_CLDUH, "clduh", "clduh", 32,
3275     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
3276   },
3277 /* cld$pack @($GRi,$GRj),$GRk,$CCi,$cond */
3278   {
3279     FRV_INSN_CLD, "cld", "cld", 32,
3280     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
3281   },
3282 /* cldbf$pack @($GRi,$GRj),$FRintk,$CCi,$cond */
3283   {
3284     FRV_INSN_CLDBF, "cldbf", "cldbf", 32,
3285     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
3286   },
3287 /* cldhf$pack @($GRi,$GRj),$FRintk,$CCi,$cond */
3288   {
3289     FRV_INSN_CLDHF, "cldhf", "cldhf", 32,
3290     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
3291   },
3292 /* cldf$pack @($GRi,$GRj),$FRintk,$CCi,$cond */
3293   {
3294     FRV_INSN_CLDF, "cldf", "cldf", 32,
3295     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
3296   },
3297 /* cldd$pack @($GRi,$GRj),$GRdoublek,$CCi,$cond */
3298   {
3299     FRV_INSN_CLDD, "cldd", "cldd", 32,
3300     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
3301   },
3302 /* clddf$pack @($GRi,$GRj),$FRdoublek,$CCi,$cond */
3303   {
3304     FRV_INSN_CLDDF, "clddf", "clddf", 32,
3305     { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
3306   },
3307 /* cldq$pack @($GRi,$GRj),$GRk,$CCi,$cond */
3308   {
3309     FRV_INSN_CLDQ, "cldq", "cldq", 32,
3310     { 0|A(CONDITIONAL), { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
3311   },
3312 /* cldsbu$pack @($GRi,$GRj),$GRk,$CCi,$cond */
3313   {
3314     FRV_INSN_CLDSBU, "cldsbu", "cldsbu", 32,
3315     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
3316   },
3317 /* cldubu$pack @($GRi,$GRj),$GRk,$CCi,$cond */
3318   {
3319     FRV_INSN_CLDUBU, "cldubu", "cldubu", 32,
3320     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
3321   },
3322 /* cldshu$pack @($GRi,$GRj),$GRk,$CCi,$cond */
3323   {
3324     FRV_INSN_CLDSHU, "cldshu", "cldshu", 32,
3325     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
3326   },
3327 /* clduhu$pack @($GRi,$GRj),$GRk,$CCi,$cond */
3328   {
3329     FRV_INSN_CLDUHU, "clduhu", "clduhu", 32,
3330     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
3331   },
3332 /* cldu$pack @($GRi,$GRj),$GRk,$CCi,$cond */
3333   {
3334     FRV_INSN_CLDU, "cldu", "cldu", 32,
3335     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
3336   },
3337 /* cldbfu$pack @($GRi,$GRj),$FRintk,$CCi,$cond */
3338   {
3339     FRV_INSN_CLDBFU, "cldbfu", "cldbfu", 32,
3340     { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
3341   },
3342 /* cldhfu$pack @($GRi,$GRj),$FRintk,$CCi,$cond */
3343   {
3344     FRV_INSN_CLDHFU, "cldhfu", "cldhfu", 32,
3345     { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
3346   },
3347 /* cldfu$pack @($GRi,$GRj),$FRintk,$CCi,$cond */
3348   {
3349     FRV_INSN_CLDFU, "cldfu", "cldfu", 32,
3350     { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
3351   },
3352 /* clddu$pack @($GRi,$GRj),$GRdoublek,$CCi,$cond */
3353   {
3354     FRV_INSN_CLDDU, "clddu", "clddu", 32,
3355     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
3356   },
3357 /* clddfu$pack @($GRi,$GRj),$FRdoublek,$CCi,$cond */
3358   {
3359     FRV_INSN_CLDDFU, "clddfu", "clddfu", 32,
3360     { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
3361   },
3362 /* cldqu$pack @($GRi,$GRj),$GRk,$CCi,$cond */
3363   {
3364     FRV_INSN_CLDQU, "cldqu", "cldqu", 32,
3365     { 0|A(CONDITIONAL), { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
3366   },
3367 /* cstb$pack $GRk,@($GRi,$GRj),$CCi,$cond */
3368   {
3369     FRV_INSN_CSTB, "cstb", "cstb", 32,
3370     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
3371   },
3372 /* csth$pack $GRk,@($GRi,$GRj),$CCi,$cond */
3373   {
3374     FRV_INSN_CSTH, "csth", "csth", 32,
3375     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
3376   },
3377 /* cst$pack $GRk,@($GRi,$GRj),$CCi,$cond */
3378   {
3379     FRV_INSN_CST, "cst", "cst", 32,
3380     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
3381   },
3382 /* cstbf$pack $FRintk,@($GRi,$GRj),$CCi,$cond */
3383   {
3384     FRV_INSN_CSTBF, "cstbf", "cstbf", 32,
3385     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
3386   },
3387 /* csthf$pack $FRintk,@($GRi,$GRj),$CCi,$cond */
3388   {
3389     FRV_INSN_CSTHF, "csthf", "csthf", 32,
3390     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
3391   },
3392 /* cstf$pack $FRintk,@($GRi,$GRj),$CCi,$cond */
3393   {
3394     FRV_INSN_CSTF, "cstf", "cstf", 32,
3395     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
3396   },
3397 /* cstd$pack $GRk,@($GRi,$GRj),$CCi,$cond */
3398   {
3399     FRV_INSN_CSTD, "cstd", "cstd", 32,
3400     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
3401   },
3402 /* cstdf$pack $FRk,@($GRi,$GRj),$CCi,$cond */
3403   {
3404     FRV_INSN_CSTDF, "cstdf", "cstdf", 32,
3405     { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
3406   },
3407 /* cstq$pack $GRk,@($GRi,$GRj),$CCi,$cond */
3408   {
3409     FRV_INSN_CSTQ, "cstq", "cstq", 32,
3410     { 0|A(CONDITIONAL), { (1<<MACH_FRV), UNIT_I0, FR400_MAJOR_NONE, FR500_MAJOR_I_3 } }
3411   },
3412 /* cstbu$pack $GRk,@($GRi,$GRj),$CCi,$cond */
3413   {
3414     FRV_INSN_CSTBU, "cstbu", "cstbu", 32,
3415     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
3416   },
3417 /* csthu$pack $GRk,@($GRi,$GRj),$CCi,$cond */
3418   {
3419     FRV_INSN_CSTHU, "csthu", "csthu", 32,
3420     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
3421   },
3422 /* cstu$pack $GRk,@($GRi,$GRj),$CCi,$cond */
3423   {
3424     FRV_INSN_CSTU, "cstu", "cstu", 32,
3425     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
3426   },
3427 /* cstbfu$pack $FRintk,@($GRi,$GRj),$CCi,$cond */
3428   {
3429     FRV_INSN_CSTBFU, "cstbfu", "cstbfu", 32,
3430     { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
3431   },
3432 /* csthfu$pack $FRintk,@($GRi,$GRj),$CCi,$cond */
3433   {
3434     FRV_INSN_CSTHFU, "csthfu", "csthfu", 32,
3435     { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
3436   },
3437 /* cstfu$pack $FRintk,@($GRi,$GRj),$CCi,$cond */
3438   {
3439     FRV_INSN_CSTFU, "cstfu", "cstfu", 32,
3440     { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
3441   },
3442 /* cstdu$pack $GRk,@($GRi,$GRj),$CCi,$cond */
3443   {
3444     FRV_INSN_CSTDU, "cstdu", "cstdu", 32,
3445     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
3446   },
3447 /* cstdfu$pack $FRk,@($GRi,$GRj),$CCi,$cond */
3448   {
3449     FRV_INSN_CSTDFU, "cstdfu", "cstdfu", 32,
3450     { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
3451   },
3452 /* stbi$pack $GRk,@($GRi,$d12) */
3453   {
3454     FRV_INSN_STBI, "stbi", "stbi", 32,
3455     { 0, { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
3456   },
3457 /* sthi$pack $GRk,@($GRi,$d12) */
3458   {
3459     FRV_INSN_STHI, "sthi", "sthi", 32,
3460     { 0, { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
3461   },
3462 /* sti$pack $GRk,@($GRi,$d12) */
3463   {
3464     FRV_INSN_STI, "sti", "sti", 32,
3465     { 0, { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
3466   },
3467 /* stbfi$pack $FRintk,@($GRi,$d12) */
3468   {
3469     FRV_INSN_STBFI, "stbfi", "stbfi", 32,
3470     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
3471   },
3472 /* sthfi$pack $FRintk,@($GRi,$d12) */
3473   {
3474     FRV_INSN_STHFI, "sthfi", "sthfi", 32,
3475     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
3476   },
3477 /* stfi$pack $FRintk,@($GRi,$d12) */
3478   {
3479     FRV_INSN_STFI, "stfi", "stfi", 32,
3480     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
3481   },
3482 /* stdi$pack $GRk,@($GRi,$d12) */
3483   {
3484     FRV_INSN_STDI, "stdi", "stdi", 32,
3485     { 0, { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
3486   },
3487 /* stdfi$pack $FRk,@($GRi,$d12) */
3488   {
3489     FRV_INSN_STDFI, "stdfi", "stdfi", 32,
3490     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
3491   },
3492 /* stqi$pack $GRk,@($GRi,$d12) */
3493   {
3494     FRV_INSN_STQI, "stqi", "stqi", 32,
3495     { 0, { (1<<MACH_FRV), UNIT_I0, FR400_MAJOR_NONE, FR500_MAJOR_I_3 } }
3496   },
3497 /* stqfi$pack $FRintk,@($GRi,$d12) */
3498   {
3499     FRV_INSN_STQFI, "stqfi", "stqfi", 32,
3500     { 0|A(FR_ACCESS), { (1<<MACH_FRV), UNIT_I0, FR400_MAJOR_NONE, FR500_MAJOR_I_3 } }
3501   },
3502 /* swap$pack @($GRi,$GRj),$GRk */
3503   {
3504     FRV_INSN_SWAP, "swap", "swap", 32,
3505     { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR500_MAJOR_C_2 } }
3506   },
3507 /* swapi$pack @($GRi,$d12),$GRk */
3508   {
3509     FRV_INSN_SWAPI, "swapi", "swapi", 32,
3510     { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR500_MAJOR_C_2 } }
3511   },
3512 /* cswap$pack @($GRi,$GRj),$GRk,$CCi,$cond */
3513   {
3514     FRV_INSN_CSWAP, "cswap", "cswap", 32,
3515     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR500_MAJOR_C_2 } }
3516   },
3517 /* movgf$pack $GRj,$FRintk */
3518   {
3519     FRV_INSN_MOVGF, "movgf", "movgf", 32,
3520     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_4, FR500_MAJOR_I_4 } }
3521   },
3522 /* movfg$pack $FRintk,$GRj */
3523   {
3524     FRV_INSN_MOVFG, "movfg", "movfg", 32,
3525     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_4, FR500_MAJOR_I_4 } }
3526   },
3527 /* movgfd$pack $GRj,$FRintk */
3528   {
3529     FRV_INSN_MOVGFD, "movgfd", "movgfd", 32,
3530     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_4, FR500_MAJOR_I_4 } }
3531   },
3532 /* movfgd$pack $FRintk,$GRj */
3533   {
3534     FRV_INSN_MOVFGD, "movfgd", "movfgd", 32,
3535     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_4, FR500_MAJOR_I_4 } }
3536   },
3537 /* movgfq$pack $GRj,$FRintk */
3538   {
3539     FRV_INSN_MOVGFQ, "movgfq", "movgfq", 32,
3540     { 0|A(FR_ACCESS), { (1<<MACH_FRV), UNIT_I0, FR400_MAJOR_NONE, FR500_MAJOR_I_4 } }
3541   },
3542 /* movfgq$pack $FRintk,$GRj */
3543   {
3544     FRV_INSN_MOVFGQ, "movfgq", "movfgq", 32,
3545     { 0|A(FR_ACCESS), { (1<<MACH_FRV), UNIT_I0, FR400_MAJOR_NONE, FR500_MAJOR_I_4 } }
3546   },
3547 /* cmovgf$pack $GRj,$FRintk,$CCi,$cond */
3548   {
3549     FRV_INSN_CMOVGF, "cmovgf", "cmovgf", 32,
3550     { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_4, FR500_MAJOR_I_4 } }
3551   },
3552 /* cmovfg$pack $FRintk,$GRj,$CCi,$cond */
3553   {
3554     FRV_INSN_CMOVFG, "cmovfg", "cmovfg", 32,
3555     { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_4, FR500_MAJOR_I_4 } }
3556   },
3557 /* cmovgfd$pack $GRj,$FRintk,$CCi,$cond */
3558   {
3559     FRV_INSN_CMOVGFD, "cmovgfd", "cmovgfd", 32,
3560     { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_4, FR500_MAJOR_I_4 } }
3561   },
3562 /* cmovfgd$pack $FRintk,$GRj,$CCi,$cond */
3563   {
3564     FRV_INSN_CMOVFGD, "cmovfgd", "cmovfgd", 32,
3565     { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_4, FR500_MAJOR_I_4 } }
3566   },
3567 /* movgs$pack $GRj,$spr */
3568   {
3569     FRV_INSN_MOVGS, "movgs", "movgs", 32,
3570     { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR500_MAJOR_C_2 } }
3571   },
3572 /* movsg$pack $spr,$GRj */
3573   {
3574     FRV_INSN_MOVSG, "movsg", "movsg", 32,
3575     { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR500_MAJOR_C_2 } }
3576   },
3577 /* bra$pack $hint_taken$label16 */
3578   {
3579     FRV_INSN_BRA, "bra", "bra", 32,
3580     { 0|A(UNCOND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
3581   },
3582 /* bno$pack$hint_not_taken */
3583   {
3584     FRV_INSN_BNO, "bno", "bno", 32,
3585     { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
3586   },
3587 /* beq$pack $ICCi_2,$hint,$label16 */
3588   {
3589     FRV_INSN_BEQ, "beq", "beq", 32,
3590     { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
3591   },
3592 /* bne$pack $ICCi_2,$hint,$label16 */
3593   {
3594     FRV_INSN_BNE, "bne", "bne", 32,
3595     { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
3596   },
3597 /* ble$pack $ICCi_2,$hint,$label16 */
3598   {
3599     FRV_INSN_BLE, "ble", "ble", 32,
3600     { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
3601   },
3602 /* bgt$pack $ICCi_2,$hint,$label16 */
3603   {
3604     FRV_INSN_BGT, "bgt", "bgt", 32,
3605     { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
3606   },
3607 /* blt$pack $ICCi_2,$hint,$label16 */
3608   {
3609     FRV_INSN_BLT, "blt", "blt", 32,
3610     { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
3611   },
3612 /* bge$pack $ICCi_2,$hint,$label16 */
3613   {
3614     FRV_INSN_BGE, "bge", "bge", 32,
3615     { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
3616   },
3617 /* bls$pack $ICCi_2,$hint,$label16 */
3618   {
3619     FRV_INSN_BLS, "bls", "bls", 32,
3620     { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
3621   },
3622 /* bhi$pack $ICCi_2,$hint,$label16 */
3623   {
3624     FRV_INSN_BHI, "bhi", "bhi", 32,
3625     { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
3626   },
3627 /* bc$pack $ICCi_2,$hint,$label16 */
3628   {
3629     FRV_INSN_BC, "bc", "bc", 32,
3630     { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
3631   },
3632 /* bnc$pack $ICCi_2,$hint,$label16 */
3633   {
3634     FRV_INSN_BNC, "bnc", "bnc", 32,
3635     { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
3636   },
3637 /* bn$pack $ICCi_2,$hint,$label16 */
3638   {
3639     FRV_INSN_BN, "bn", "bn", 32,
3640     { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
3641   },
3642 /* bp$pack $ICCi_2,$hint,$label16 */
3643   {
3644     FRV_INSN_BP, "bp", "bp", 32,
3645     { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
3646   },
3647 /* bv$pack $ICCi_2,$hint,$label16 */
3648   {
3649     FRV_INSN_BV, "bv", "bv", 32,
3650     { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
3651   },
3652 /* bnv$pack $ICCi_2,$hint,$label16 */
3653   {
3654     FRV_INSN_BNV, "bnv", "bnv", 32,
3655     { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
3656   },
3657 /* fbra$pack $hint_taken$label16 */
3658   {
3659     FRV_INSN_FBRA, "fbra", "fbra", 32,
3660     { 0|A(FR_ACCESS)|A(UNCOND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
3661   },
3662 /* fbno$pack$hint_not_taken */
3663   {
3664     FRV_INSN_FBNO, "fbno", "fbno", 32,
3665     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
3666   },
3667 /* fbne$pack $FCCi_2,$hint,$label16 */
3668   {
3669     FRV_INSN_FBNE, "fbne", "fbne", 32,
3670     { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
3671   },
3672 /* fbeq$pack $FCCi_2,$hint,$label16 */
3673   {
3674     FRV_INSN_FBEQ, "fbeq", "fbeq", 32,
3675     { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
3676   },
3677 /* fblg$pack $FCCi_2,$hint,$label16 */
3678   {
3679     FRV_INSN_FBLG, "fblg", "fblg", 32,
3680     { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
3681   },
3682 /* fbue$pack $FCCi_2,$hint,$label16 */
3683   {
3684     FRV_INSN_FBUE, "fbue", "fbue", 32,
3685     { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
3686   },
3687 /* fbul$pack $FCCi_2,$hint,$label16 */
3688   {
3689     FRV_INSN_FBUL, "fbul", "fbul", 32,
3690     { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
3691   },
3692 /* fbge$pack $FCCi_2,$hint,$label16 */
3693   {
3694     FRV_INSN_FBGE, "fbge", "fbge", 32,
3695     { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
3696   },
3697 /* fblt$pack $FCCi_2,$hint,$label16 */
3698   {
3699     FRV_INSN_FBLT, "fblt", "fblt", 32,
3700     { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
3701   },
3702 /* fbuge$pack $FCCi_2,$hint,$label16 */
3703   {
3704     FRV_INSN_FBUGE, "fbuge", "fbuge", 32,
3705     { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
3706   },
3707 /* fbug$pack $FCCi_2,$hint,$label16 */
3708   {
3709     FRV_INSN_FBUG, "fbug", "fbug", 32,
3710     { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
3711   },
3712 /* fble$pack $FCCi_2,$hint,$label16 */
3713   {
3714     FRV_INSN_FBLE, "fble", "fble", 32,
3715     { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
3716   },
3717 /* fbgt$pack $FCCi_2,$hint,$label16 */
3718   {
3719     FRV_INSN_FBGT, "fbgt", "fbgt", 32,
3720     { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
3721   },
3722 /* fbule$pack $FCCi_2,$hint,$label16 */
3723   {
3724     FRV_INSN_FBULE, "fbule", "fbule", 32,
3725     { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
3726   },
3727 /* fbu$pack $FCCi_2,$hint,$label16 */
3728   {
3729     FRV_INSN_FBU, "fbu", "fbu", 32,
3730     { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
3731   },
3732 /* fbo$pack $FCCi_2,$hint,$label16 */
3733   {
3734     FRV_INSN_FBO, "fbo", "fbo", 32,
3735     { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
3736   },
3737 /* bctrlr$pack $ccond,$hint */
3738   {
3739     FRV_INSN_BCTRLR, "bctrlr", "bctrlr", 32,
3740     { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
3741   },
3742 /* bralr$pack$hint_taken */
3743   {
3744     FRV_INSN_BRALR, "bralr", "bralr", 32,
3745     { 0|A(UNCOND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
3746   },
3747 /* bnolr$pack$hint_not_taken */
3748   {
3749     FRV_INSN_BNOLR, "bnolr", "bnolr", 32,
3750     { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
3751   },
3752 /* beqlr$pack $ICCi_2,$hint */
3753   {
3754     FRV_INSN_BEQLR, "beqlr", "beqlr", 32,
3755     { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
3756   },
3757 /* bnelr$pack $ICCi_2,$hint */
3758   {
3759     FRV_INSN_BNELR, "bnelr", "bnelr", 32,
3760     { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
3761   },
3762 /* blelr$pack $ICCi_2,$hint */
3763   {
3764     FRV_INSN_BLELR, "blelr", "blelr", 32,
3765     { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
3766   },
3767 /* bgtlr$pack $ICCi_2,$hint */
3768   {
3769     FRV_INSN_BGTLR, "bgtlr", "bgtlr", 32,
3770     { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
3771   },
3772 /* bltlr$pack $ICCi_2,$hint */
3773   {
3774     FRV_INSN_BLTLR, "bltlr", "bltlr", 32,
3775     { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
3776   },
3777 /* bgelr$pack $ICCi_2,$hint */
3778   {
3779     FRV_INSN_BGELR, "bgelr", "bgelr", 32,
3780     { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
3781   },
3782 /* blslr$pack $ICCi_2,$hint */
3783   {
3784     FRV_INSN_BLSLR, "blslr", "blslr", 32,
3785     { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
3786   },
3787 /* bhilr$pack $ICCi_2,$hint */
3788   {
3789     FRV_INSN_BHILR, "bhilr", "bhilr", 32,
3790     { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
3791   },
3792 /* bclr$pack $ICCi_2,$hint */
3793   {
3794     FRV_INSN_BCLR, "bclr", "bclr", 32,
3795     { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
3796   },
3797 /* bnclr$pack $ICCi_2,$hint */
3798   {
3799     FRV_INSN_BNCLR, "bnclr", "bnclr", 32,
3800     { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
3801   },
3802 /* bnlr$pack $ICCi_2,$hint */
3803   {
3804     FRV_INSN_BNLR, "bnlr", "bnlr", 32,
3805     { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
3806   },
3807 /* bplr$pack $ICCi_2,$hint */
3808   {
3809     FRV_INSN_BPLR, "bplr", "bplr", 32,
3810     { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
3811   },
3812 /* bvlr$pack $ICCi_2,$hint */
3813   {
3814     FRV_INSN_BVLR, "bvlr", "bvlr", 32,
3815     { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
3816   },
3817 /* bnvlr$pack $ICCi_2,$hint */
3818   {
3819     FRV_INSN_BNVLR, "bnvlr", "bnvlr", 32,
3820     { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
3821   },
3822 /* fbralr$pack$hint_taken */
3823   {
3824     FRV_INSN_FBRALR, "fbralr", "fbralr", 32,
3825     { 0|A(FR_ACCESS)|A(UNCOND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
3826   },
3827 /* fbnolr$pack$hint_not_taken */
3828   {
3829     FRV_INSN_FBNOLR, "fbnolr", "fbnolr", 32,
3830     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
3831   },
3832 /* fbeqlr$pack $FCCi_2,$hint */
3833   {
3834     FRV_INSN_FBEQLR, "fbeqlr", "fbeqlr", 32,
3835     { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
3836   },
3837 /* fbnelr$pack $FCCi_2,$hint */
3838   {
3839     FRV_INSN_FBNELR, "fbnelr", "fbnelr", 32,
3840     { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
3841   },
3842 /* fblglr$pack $FCCi_2,$hint */
3843   {
3844     FRV_INSN_FBLGLR, "fblglr", "fblglr", 32,
3845     { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
3846   },
3847 /* fbuelr$pack $FCCi_2,$hint */
3848   {
3849     FRV_INSN_FBUELR, "fbuelr", "fbuelr", 32,
3850     { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
3851   },
3852 /* fbullr$pack $FCCi_2,$hint */
3853   {
3854     FRV_INSN_FBULLR, "fbullr", "fbullr", 32,
3855     { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
3856   },
3857 /* fbgelr$pack $FCCi_2,$hint */
3858   {
3859     FRV_INSN_FBGELR, "fbgelr", "fbgelr", 32,
3860     { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
3861   },
3862 /* fbltlr$pack $FCCi_2,$hint */
3863   {
3864     FRV_INSN_FBLTLR, "fbltlr", "fbltlr", 32,
3865     { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
3866   },
3867 /* fbugelr$pack $FCCi_2,$hint */
3868   {
3869     FRV_INSN_FBUGELR, "fbugelr", "fbugelr", 32,
3870     { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
3871   },
3872 /* fbuglr$pack $FCCi_2,$hint */
3873   {
3874     FRV_INSN_FBUGLR, "fbuglr", "fbuglr", 32,
3875     { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
3876   },
3877 /* fblelr$pack $FCCi_2,$hint */
3878   {
3879     FRV_INSN_FBLELR, "fblelr", "fblelr", 32,
3880     { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
3881   },
3882 /* fbgtlr$pack $FCCi_2,$hint */
3883   {
3884     FRV_INSN_FBGTLR, "fbgtlr", "fbgtlr", 32,
3885     { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
3886   },
3887 /* fbulelr$pack $FCCi_2,$hint */
3888   {
3889     FRV_INSN_FBULELR, "fbulelr", "fbulelr", 32,
3890     { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
3891   },
3892 /* fbulr$pack $FCCi_2,$hint */
3893   {
3894     FRV_INSN_FBULR, "fbulr", "fbulr", 32,
3895     { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
3896   },
3897 /* fbolr$pack $FCCi_2,$hint */
3898   {
3899     FRV_INSN_FBOLR, "fbolr", "fbolr", 32,
3900     { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
3901   },
3902 /* bcralr$pack $ccond$hint_taken */
3903   {
3904     FRV_INSN_BCRALR, "bcralr", "bcralr", 32,
3905     { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
3906   },
3907 /* bcnolr$pack$hint_not_taken */
3908   {
3909     FRV_INSN_BCNOLR, "bcnolr", "bcnolr", 32,
3910     { 0, { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
3911   },
3912 /* bceqlr$pack $ICCi_2,$ccond,$hint */
3913   {
3914     FRV_INSN_BCEQLR, "bceqlr", "bceqlr", 32,
3915     { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
3916   },
3917 /* bcnelr$pack $ICCi_2,$ccond,$hint */
3918   {
3919     FRV_INSN_BCNELR, "bcnelr", "bcnelr", 32,
3920     { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
3921   },
3922 /* bclelr$pack $ICCi_2,$ccond,$hint */
3923   {
3924     FRV_INSN_BCLELR, "bclelr", "bclelr", 32,
3925     { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
3926   },
3927 /* bcgtlr$pack $ICCi_2,$ccond,$hint */
3928   {
3929     FRV_INSN_BCGTLR, "bcgtlr", "bcgtlr", 32,
3930     { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
3931   },
3932 /* bcltlr$pack $ICCi_2,$ccond,$hint */
3933   {
3934     FRV_INSN_BCLTLR, "bcltlr", "bcltlr", 32,
3935     { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
3936   },
3937 /* bcgelr$pack $ICCi_2,$ccond,$hint */
3938   {
3939     FRV_INSN_BCGELR, "bcgelr", "bcgelr", 32,
3940     { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
3941   },
3942 /* bclslr$pack $ICCi_2,$ccond,$hint */
3943   {
3944     FRV_INSN_BCLSLR, "bclslr", "bclslr", 32,
3945     { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
3946   },
3947 /* bchilr$pack $ICCi_2,$ccond,$hint */
3948   {
3949     FRV_INSN_BCHILR, "bchilr", "bchilr", 32,
3950     { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
3951   },
3952 /* bcclr$pack $ICCi_2,$ccond,$hint */
3953   {
3954     FRV_INSN_BCCLR, "bcclr", "bcclr", 32,
3955     { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
3956   },
3957 /* bcnclr$pack $ICCi_2,$ccond,$hint */
3958   {
3959     FRV_INSN_BCNCLR, "bcnclr", "bcnclr", 32,
3960     { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
3961   },
3962 /* bcnlr$pack $ICCi_2,$ccond,$hint */
3963   {
3964     FRV_INSN_BCNLR, "bcnlr", "bcnlr", 32,
3965     { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
3966   },
3967 /* bcplr$pack $ICCi_2,$ccond,$hint */
3968   {
3969     FRV_INSN_BCPLR, "bcplr", "bcplr", 32,
3970     { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
3971   },
3972 /* bcvlr$pack $ICCi_2,$ccond,$hint */
3973   {
3974     FRV_INSN_BCVLR, "bcvlr", "bcvlr", 32,
3975     { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
3976   },
3977 /* bcnvlr$pack $ICCi_2,$ccond,$hint */
3978   {
3979     FRV_INSN_BCNVLR, "bcnvlr", "bcnvlr", 32,
3980     { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
3981   },
3982 /* fcbralr$pack $ccond$hint_taken */
3983   {
3984     FRV_INSN_FCBRALR, "fcbralr", "fcbralr", 32,
3985     { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
3986   },
3987 /* fcbnolr$pack$hint_not_taken */
3988   {
3989     FRV_INSN_FCBNOLR, "fcbnolr", "fcbnolr", 32,
3990     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
3991   },
3992 /* fcbeqlr$pack $FCCi_2,$ccond,$hint */
3993   {
3994     FRV_INSN_FCBEQLR, "fcbeqlr", "fcbeqlr", 32,
3995     { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
3996   },
3997 /* fcbnelr$pack $FCCi_2,$ccond,$hint */
3998   {
3999     FRV_INSN_FCBNELR, "fcbnelr", "fcbnelr", 32,
4000     { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
4001   },
4002 /* fcblglr$pack $FCCi_2,$ccond,$hint */
4003   {
4004     FRV_INSN_FCBLGLR, "fcblglr", "fcblglr", 32,
4005     { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
4006   },
4007 /* fcbuelr$pack $FCCi_2,$ccond,$hint */
4008   {
4009     FRV_INSN_FCBUELR, "fcbuelr", "fcbuelr", 32,
4010     { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
4011   },
4012 /* fcbullr$pack $FCCi_2,$ccond,$hint */
4013   {
4014     FRV_INSN_FCBULLR, "fcbullr", "fcbullr", 32,
4015     { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
4016   },
4017 /* fcbgelr$pack $FCCi_2,$ccond,$hint */
4018   {
4019     FRV_INSN_FCBGELR, "fcbgelr", "fcbgelr", 32,
4020     { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
4021   },
4022 /* fcbltlr$pack $FCCi_2,$ccond,$hint */
4023   {
4024     FRV_INSN_FCBLTLR, "fcbltlr", "fcbltlr", 32,
4025     { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
4026   },
4027 /* fcbugelr$pack $FCCi_2,$ccond,$hint */
4028   {
4029     FRV_INSN_FCBUGELR, "fcbugelr", "fcbugelr", 32,
4030     { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
4031   },
4032 /* fcbuglr$pack $FCCi_2,$ccond,$hint */
4033   {
4034     FRV_INSN_FCBUGLR, "fcbuglr", "fcbuglr", 32,
4035     { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
4036   },
4037 /* fcblelr$pack $FCCi_2,$ccond,$hint */
4038   {
4039     FRV_INSN_FCBLELR, "fcblelr", "fcblelr", 32,
4040     { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
4041   },
4042 /* fcbgtlr$pack $FCCi_2,$ccond,$hint */
4043   {
4044     FRV_INSN_FCBGTLR, "fcbgtlr", "fcbgtlr", 32,
4045     { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
4046   },
4047 /* fcbulelr$pack $FCCi_2,$ccond,$hint */
4048   {
4049     FRV_INSN_FCBULELR, "fcbulelr", "fcbulelr", 32,
4050     { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
4051   },
4052 /* fcbulr$pack $FCCi_2,$ccond,$hint */
4053   {
4054     FRV_INSN_FCBULR, "fcbulr", "fcbulr", 32,
4055     { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
4056   },
4057 /* fcbolr$pack $FCCi_2,$ccond,$hint */
4058   {
4059     FRV_INSN_FCBOLR, "fcbolr", "fcbolr", 32,
4060     { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
4061   },
4062 /* jmpl$pack @($GRi,$GRj) */
4063   {
4064     FRV_INSN_JMPL, "jmpl", "jmpl", 32,
4065     { 0|A(UNCOND_CTI), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_5, FR500_MAJOR_I_5 } }
4066   },
4067 /* calll$pack @($GRi,$GRj) */
4068   {
4069     FRV_INSN_CALLL, "calll", "calll", 32,
4070     { 0|A(UNCOND_CTI), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_5, FR500_MAJOR_I_5 } }
4071   },
4072 /* jmpil$pack @($GRi,$s12) */
4073   {
4074     FRV_INSN_JMPIL, "jmpil", "jmpil", 32,
4075     { 0|A(UNCOND_CTI), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_5, FR500_MAJOR_I_5 } }
4076   },
4077 /* callil$pack @($GRi,$s12) */
4078   {
4079     FRV_INSN_CALLIL, "callil", "callil", 32,
4080     { 0|A(UNCOND_CTI), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_5, FR500_MAJOR_I_5 } }
4081   },
4082 /* call$pack $label24 */
4083   {
4084     FRV_INSN_CALL, "call", "call", 32,
4085     { 0|A(UNCOND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_4, FR500_MAJOR_B_4 } }
4086   },
4087 /* rett$pack $debug */
4088   {
4089     FRV_INSN_RETT, "rett", "rett", 32,
4090     { 0|A(PRIVILEGED)|A(UNCOND_CTI), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR500_MAJOR_C_2 } }
4091   },
4092 /* rei$pack $eir */
4093   {
4094     FRV_INSN_REI, "rei", "rei", 32,
4095     { 0|A(PRIVILEGED), { (1<<MACH_FRV), UNIT_C, FR400_MAJOR_NONE, FR500_MAJOR_C_1 } }
4096   },
4097 /* tra$pack $GRi,$GRj */
4098   {
4099     FRV_INSN_TRA, "tra", "tra", 32,
4100     { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4101   },
4102 /* tno$pack */
4103   {
4104     FRV_INSN_TNO, "tno", "tno", 32,
4105     { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4106   },
4107 /* teq$pack $ICCi_2,$GRi,$GRj */
4108   {
4109     FRV_INSN_TEQ, "teq", "teq", 32,
4110     { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4111   },
4112 /* tne$pack $ICCi_2,$GRi,$GRj */
4113   {
4114     FRV_INSN_TNE, "tne", "tne", 32,
4115     { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4116   },
4117 /* tle$pack $ICCi_2,$GRi,$GRj */
4118   {
4119     FRV_INSN_TLE, "tle", "tle", 32,
4120     { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4121   },
4122 /* tgt$pack $ICCi_2,$GRi,$GRj */
4123   {
4124     FRV_INSN_TGT, "tgt", "tgt", 32,
4125     { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4126   },
4127 /* tlt$pack $ICCi_2,$GRi,$GRj */
4128   {
4129     FRV_INSN_TLT, "tlt", "tlt", 32,
4130     { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4131   },
4132 /* tge$pack $ICCi_2,$GRi,$GRj */
4133   {
4134     FRV_INSN_TGE, "tge", "tge", 32,
4135     { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4136   },
4137 /* tls$pack $ICCi_2,$GRi,$GRj */
4138   {
4139     FRV_INSN_TLS, "tls", "tls", 32,
4140     { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4141   },
4142 /* thi$pack $ICCi_2,$GRi,$GRj */
4143   {
4144     FRV_INSN_THI, "thi", "thi", 32,
4145     { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4146   },
4147 /* tc$pack $ICCi_2,$GRi,$GRj */
4148   {
4149     FRV_INSN_TC, "tc", "tc", 32,
4150     { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4151   },
4152 /* tnc$pack $ICCi_2,$GRi,$GRj */
4153   {
4154     FRV_INSN_TNC, "tnc", "tnc", 32,
4155     { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4156   },
4157 /* tn$pack $ICCi_2,$GRi,$GRj */
4158   {
4159     FRV_INSN_TN, "tn", "tn", 32,
4160     { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4161   },
4162 /* tp$pack $ICCi_2,$GRi,$GRj */
4163   {
4164     FRV_INSN_TP, "tp", "tp", 32,
4165     { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4166   },
4167 /* tv$pack $ICCi_2,$GRi,$GRj */
4168   {
4169     FRV_INSN_TV, "tv", "tv", 32,
4170     { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4171   },
4172 /* tnv$pack $ICCi_2,$GRi,$GRj */
4173   {
4174     FRV_INSN_TNV, "tnv", "tnv", 32,
4175     { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4176   },
4177 /* ftra$pack $GRi,$GRj */
4178   {
4179     FRV_INSN_FTRA, "ftra", "ftra", 32,
4180     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4181   },
4182 /* ftno$pack */
4183   {
4184     FRV_INSN_FTNO, "ftno", "ftno", 32,
4185     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4186   },
4187 /* ftne$pack $FCCi_2,$GRi,$GRj */
4188   {
4189     FRV_INSN_FTNE, "ftne", "ftne", 32,
4190     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4191   },
4192 /* fteq$pack $FCCi_2,$GRi,$GRj */
4193   {
4194     FRV_INSN_FTEQ, "fteq", "fteq", 32,
4195     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4196   },
4197 /* ftlg$pack $FCCi_2,$GRi,$GRj */
4198   {
4199     FRV_INSN_FTLG, "ftlg", "ftlg", 32,
4200     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4201   },
4202 /* ftue$pack $FCCi_2,$GRi,$GRj */
4203   {
4204     FRV_INSN_FTUE, "ftue", "ftue", 32,
4205     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4206   },
4207 /* ftul$pack $FCCi_2,$GRi,$GRj */
4208   {
4209     FRV_INSN_FTUL, "ftul", "ftul", 32,
4210     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4211   },
4212 /* ftge$pack $FCCi_2,$GRi,$GRj */
4213   {
4214     FRV_INSN_FTGE, "ftge", "ftge", 32,
4215     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4216   },
4217 /* ftlt$pack $FCCi_2,$GRi,$GRj */
4218   {
4219     FRV_INSN_FTLT, "ftlt", "ftlt", 32,
4220     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4221   },
4222 /* ftuge$pack $FCCi_2,$GRi,$GRj */
4223   {
4224     FRV_INSN_FTUGE, "ftuge", "ftuge", 32,
4225     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4226   },
4227 /* ftug$pack $FCCi_2,$GRi,$GRj */
4228   {
4229     FRV_INSN_FTUG, "ftug", "ftug", 32,
4230     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4231   },
4232 /* ftle$pack $FCCi_2,$GRi,$GRj */
4233   {
4234     FRV_INSN_FTLE, "ftle", "ftle", 32,
4235     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4236   },
4237 /* ftgt$pack $FCCi_2,$GRi,$GRj */
4238   {
4239     FRV_INSN_FTGT, "ftgt", "ftgt", 32,
4240     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4241   },
4242 /* ftule$pack $FCCi_2,$GRi,$GRj */
4243   {
4244     FRV_INSN_FTULE, "ftule", "ftule", 32,
4245     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4246   },
4247 /* ftu$pack $FCCi_2,$GRi,$GRj */
4248   {
4249     FRV_INSN_FTU, "ftu", "ftu", 32,
4250     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4251   },
4252 /* fto$pack $FCCi_2,$GRi,$GRj */
4253   {
4254     FRV_INSN_FTO, "fto", "fto", 32,
4255     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4256   },
4257 /* tira$pack $GRi,$s12 */
4258   {
4259     FRV_INSN_TIRA, "tira", "tira", 32,
4260     { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4261   },
4262 /* tino$pack */
4263   {
4264     FRV_INSN_TINO, "tino", "tino", 32,
4265     { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4266   },
4267 /* tieq$pack $ICCi_2,$GRi,$s12 */
4268   {
4269     FRV_INSN_TIEQ, "tieq", "tieq", 32,
4270     { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4271   },
4272 /* tine$pack $ICCi_2,$GRi,$s12 */
4273   {
4274     FRV_INSN_TINE, "tine", "tine", 32,
4275     { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4276   },
4277 /* tile$pack $ICCi_2,$GRi,$s12 */
4278   {
4279     FRV_INSN_TILE, "tile", "tile", 32,
4280     { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4281   },
4282 /* tigt$pack $ICCi_2,$GRi,$s12 */
4283   {
4284     FRV_INSN_TIGT, "tigt", "tigt", 32,
4285     { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4286   },
4287 /* tilt$pack $ICCi_2,$GRi,$s12 */
4288   {
4289     FRV_INSN_TILT, "tilt", "tilt", 32,
4290     { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4291   },
4292 /* tige$pack $ICCi_2,$GRi,$s12 */
4293   {
4294     FRV_INSN_TIGE, "tige", "tige", 32,
4295     { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4296   },
4297 /* tils$pack $ICCi_2,$GRi,$s12 */
4298   {
4299     FRV_INSN_TILS, "tils", "tils", 32,
4300     { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4301   },
4302 /* tihi$pack $ICCi_2,$GRi,$s12 */
4303   {
4304     FRV_INSN_TIHI, "tihi", "tihi", 32,
4305     { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4306   },
4307 /* tic$pack $ICCi_2,$GRi,$s12 */
4308   {
4309     FRV_INSN_TIC, "tic", "tic", 32,
4310     { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4311   },
4312 /* tinc$pack $ICCi_2,$GRi,$s12 */
4313   {
4314     FRV_INSN_TINC, "tinc", "tinc", 32,
4315     { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4316   },
4317 /* tin$pack $ICCi_2,$GRi,$s12 */
4318   {
4319     FRV_INSN_TIN, "tin", "tin", 32,
4320     { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4321   },
4322 /* tip$pack $ICCi_2,$GRi,$s12 */
4323   {
4324     FRV_INSN_TIP, "tip", "tip", 32,
4325     { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4326   },
4327 /* tiv$pack $ICCi_2,$GRi,$s12 */
4328   {
4329     FRV_INSN_TIV, "tiv", "tiv", 32,
4330     { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4331   },
4332 /* tinv$pack $ICCi_2,$GRi,$s12 */
4333   {
4334     FRV_INSN_TINV, "tinv", "tinv", 32,
4335     { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4336   },
4337 /* ftira$pack $GRi,$s12 */
4338   {
4339     FRV_INSN_FTIRA, "ftira", "ftira", 32,
4340     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4341   },
4342 /* ftino$pack */
4343   {
4344     FRV_INSN_FTINO, "ftino", "ftino", 32,
4345     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4346   },
4347 /* ftine$pack $FCCi_2,$GRi,$s12 */
4348   {
4349     FRV_INSN_FTINE, "ftine", "ftine", 32,
4350     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4351   },
4352 /* ftieq$pack $FCCi_2,$GRi,$s12 */
4353   {
4354     FRV_INSN_FTIEQ, "ftieq", "ftieq", 32,
4355     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4356   },
4357 /* ftilg$pack $FCCi_2,$GRi,$s12 */
4358   {
4359     FRV_INSN_FTILG, "ftilg", "ftilg", 32,
4360     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4361   },
4362 /* ftiue$pack $FCCi_2,$GRi,$s12 */
4363   {
4364     FRV_INSN_FTIUE, "ftiue", "ftiue", 32,
4365     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4366   },
4367 /* ftiul$pack $FCCi_2,$GRi,$s12 */
4368   {
4369     FRV_INSN_FTIUL, "ftiul", "ftiul", 32,
4370     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4371   },
4372 /* ftige$pack $FCCi_2,$GRi,$s12 */
4373   {
4374     FRV_INSN_FTIGE, "ftige", "ftige", 32,
4375     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4376   },
4377 /* ftilt$pack $FCCi_2,$GRi,$s12 */
4378   {
4379     FRV_INSN_FTILT, "ftilt", "ftilt", 32,
4380     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4381   },
4382 /* ftiuge$pack $FCCi_2,$GRi,$s12 */
4383   {
4384     FRV_INSN_FTIUGE, "ftiuge", "ftiuge", 32,
4385     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4386   },
4387 /* ftiug$pack $FCCi_2,$GRi,$s12 */
4388   {
4389     FRV_INSN_FTIUG, "ftiug", "ftiug", 32,
4390     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4391   },
4392 /* ftile$pack $FCCi_2,$GRi,$s12 */
4393   {
4394     FRV_INSN_FTILE, "ftile", "ftile", 32,
4395     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4396   },
4397 /* ftigt$pack $FCCi_2,$GRi,$s12 */
4398   {
4399     FRV_INSN_FTIGT, "ftigt", "ftigt", 32,
4400     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4401   },
4402 /* ftiule$pack $FCCi_2,$GRi,$s12 */
4403   {
4404     FRV_INSN_FTIULE, "ftiule", "ftiule", 32,
4405     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4406   },
4407 /* ftiu$pack $FCCi_2,$GRi,$s12 */
4408   {
4409     FRV_INSN_FTIU, "ftiu", "ftiu", 32,
4410     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4411   },
4412 /* ftio$pack $FCCi_2,$GRi,$s12 */
4413   {
4414     FRV_INSN_FTIO, "ftio", "ftio", 32,
4415     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4416   },
4417 /* break$pack */
4418   {
4419     FRV_INSN_BREAK, "break", "break", 32,
4420     { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4421   },
4422 /* mtrap$pack */
4423   {
4424     FRV_INSN_MTRAP, "mtrap", "mtrap", 32,
4425     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4426   },
4427 /* andcr$pack $CRi,$CRj,$CRk */
4428   {
4429     FRV_INSN_ANDCR, "andcr", "andcr", 32,
4430     { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_6, FR500_MAJOR_B_6 } }
4431   },
4432 /* orcr$pack $CRi,$CRj,$CRk */
4433   {
4434     FRV_INSN_ORCR, "orcr", "orcr", 32,
4435     { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_6, FR500_MAJOR_B_6 } }
4436   },
4437 /* xorcr$pack $CRi,$CRj,$CRk */
4438   {
4439     FRV_INSN_XORCR, "xorcr", "xorcr", 32,
4440     { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_6, FR500_MAJOR_B_6 } }
4441   },
4442 /* nandcr$pack $CRi,$CRj,$CRk */
4443   {
4444     FRV_INSN_NANDCR, "nandcr", "nandcr", 32,
4445     { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_6, FR500_MAJOR_B_6 } }
4446   },
4447 /* norcr$pack $CRi,$CRj,$CRk */
4448   {
4449     FRV_INSN_NORCR, "norcr", "norcr", 32,
4450     { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_6, FR500_MAJOR_B_6 } }
4451   },
4452 /* andncr$pack $CRi,$CRj,$CRk */
4453   {
4454     FRV_INSN_ANDNCR, "andncr", "andncr", 32,
4455     { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_6, FR500_MAJOR_B_6 } }
4456   },
4457 /* orncr$pack $CRi,$CRj,$CRk */
4458   {
4459     FRV_INSN_ORNCR, "orncr", "orncr", 32,
4460     { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_6, FR500_MAJOR_B_6 } }
4461   },
4462 /* nandncr$pack $CRi,$CRj,$CRk */
4463   {
4464     FRV_INSN_NANDNCR, "nandncr", "nandncr", 32,
4465     { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_6, FR500_MAJOR_B_6 } }
4466   },
4467 /* norncr$pack $CRi,$CRj,$CRk */
4468   {
4469     FRV_INSN_NORNCR, "norncr", "norncr", 32,
4470     { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_6, FR500_MAJOR_B_6 } }
4471   },
4472 /* notcr$pack $CRj,$CRk */
4473   {
4474     FRV_INSN_NOTCR, "notcr", "notcr", 32,
4475     { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_6, FR500_MAJOR_B_6 } }
4476   },
4477 /* ckra$pack $CRj_int */
4478   {
4479     FRV_INSN_CKRA, "ckra", "ckra", 32,
4480     { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4481   },
4482 /* ckno$pack $CRj_int */
4483   {
4484     FRV_INSN_CKNO, "ckno", "ckno", 32,
4485     { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4486   },
4487 /* ckeq$pack $ICCi_3,$CRj_int */
4488   {
4489     FRV_INSN_CKEQ, "ckeq", "ckeq", 32,
4490     { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4491   },
4492 /* ckne$pack $ICCi_3,$CRj_int */
4493   {
4494     FRV_INSN_CKNE, "ckne", "ckne", 32,
4495     { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4496   },
4497 /* ckle$pack $ICCi_3,$CRj_int */
4498   {
4499     FRV_INSN_CKLE, "ckle", "ckle", 32,
4500     { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4501   },
4502 /* ckgt$pack $ICCi_3,$CRj_int */
4503   {
4504     FRV_INSN_CKGT, "ckgt", "ckgt", 32,
4505     { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4506   },
4507 /* cklt$pack $ICCi_3,$CRj_int */
4508   {
4509     FRV_INSN_CKLT, "cklt", "cklt", 32,
4510     { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4511   },
4512 /* ckge$pack $ICCi_3,$CRj_int */
4513   {
4514     FRV_INSN_CKGE, "ckge", "ckge", 32,
4515     { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4516   },
4517 /* ckls$pack $ICCi_3,$CRj_int */
4518   {
4519     FRV_INSN_CKLS, "ckls", "ckls", 32,
4520     { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4521   },
4522 /* ckhi$pack $ICCi_3,$CRj_int */
4523   {
4524     FRV_INSN_CKHI, "ckhi", "ckhi", 32,
4525     { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4526   },
4527 /* ckc$pack $ICCi_3,$CRj_int */
4528   {
4529     FRV_INSN_CKC, "ckc", "ckc", 32,
4530     { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4531   },
4532 /* cknc$pack $ICCi_3,$CRj_int */
4533   {
4534     FRV_INSN_CKNC, "cknc", "cknc", 32,
4535     { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4536   },
4537 /* ckn$pack $ICCi_3,$CRj_int */
4538   {
4539     FRV_INSN_CKN, "ckn", "ckn", 32,
4540     { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4541   },
4542 /* ckp$pack $ICCi_3,$CRj_int */
4543   {
4544     FRV_INSN_CKP, "ckp", "ckp", 32,
4545     { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4546   },
4547 /* ckv$pack $ICCi_3,$CRj_int */
4548   {
4549     FRV_INSN_CKV, "ckv", "ckv", 32,
4550     { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4551   },
4552 /* cknv$pack $ICCi_3,$CRj_int */
4553   {
4554     FRV_INSN_CKNV, "cknv", "cknv", 32,
4555     { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4556   },
4557 /* fckra$pack $CRj_float */
4558   {
4559     FRV_INSN_FCKRA, "fckra", "fckra", 32,
4560     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4561   },
4562 /* fckno$pack $CRj_float */
4563   {
4564     FRV_INSN_FCKNO, "fckno", "fckno", 32,
4565     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4566   },
4567 /* fckne$pack $FCCi_3,$CRj_float */
4568   {
4569     FRV_INSN_FCKNE, "fckne", "fckne", 32,
4570     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4571   },
4572 /* fckeq$pack $FCCi_3,$CRj_float */
4573   {
4574     FRV_INSN_FCKEQ, "fckeq", "fckeq", 32,
4575     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4576   },
4577 /* fcklg$pack $FCCi_3,$CRj_float */
4578   {
4579     FRV_INSN_FCKLG, "fcklg", "fcklg", 32,
4580     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4581   },
4582 /* fckue$pack $FCCi_3,$CRj_float */
4583   {
4584     FRV_INSN_FCKUE, "fckue", "fckue", 32,
4585     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4586   },
4587 /* fckul$pack $FCCi_3,$CRj_float */
4588   {
4589     FRV_INSN_FCKUL, "fckul", "fckul", 32,
4590     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4591   },
4592 /* fckge$pack $FCCi_3,$CRj_float */
4593   {
4594     FRV_INSN_FCKGE, "fckge", "fckge", 32,
4595     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4596   },
4597 /* fcklt$pack $FCCi_3,$CRj_float */
4598   {
4599     FRV_INSN_FCKLT, "fcklt", "fcklt", 32,
4600     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4601   },
4602 /* fckuge$pack $FCCi_3,$CRj_float */
4603   {
4604     FRV_INSN_FCKUGE, "fckuge", "fckuge", 32,
4605     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4606   },
4607 /* fckug$pack $FCCi_3,$CRj_float */
4608   {
4609     FRV_INSN_FCKUG, "fckug", "fckug", 32,
4610     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4611   },
4612 /* fckle$pack $FCCi_3,$CRj_float */
4613   {
4614     FRV_INSN_FCKLE, "fckle", "fckle", 32,
4615     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4616   },
4617 /* fckgt$pack $FCCi_3,$CRj_float */
4618   {
4619     FRV_INSN_FCKGT, "fckgt", "fckgt", 32,
4620     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4621   },
4622 /* fckule$pack $FCCi_3,$CRj_float */
4623   {
4624     FRV_INSN_FCKULE, "fckule", "fckule", 32,
4625     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4626   },
4627 /* fcku$pack $FCCi_3,$CRj_float */
4628   {
4629     FRV_INSN_FCKU, "fcku", "fcku", 32,
4630     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4631   },
4632 /* fcko$pack $FCCi_3,$CRj_float */
4633   {
4634     FRV_INSN_FCKO, "fcko", "fcko", 32,
4635     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4636   },
4637 /* cckra$pack $CRj_int,$CCi,$cond */
4638   {
4639     FRV_INSN_CCKRA, "cckra", "cckra", 32,
4640     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4641   },
4642 /* cckno$pack $CRj_int,$CCi,$cond */
4643   {
4644     FRV_INSN_CCKNO, "cckno", "cckno", 32,
4645     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4646   },
4647 /* cckeq$pack $ICCi_3,$CRj_int,$CCi,$cond */
4648   {
4649     FRV_INSN_CCKEQ, "cckeq", "cckeq", 32,
4650     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4651   },
4652 /* cckne$pack $ICCi_3,$CRj_int,$CCi,$cond */
4653   {
4654     FRV_INSN_CCKNE, "cckne", "cckne", 32,
4655     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4656   },
4657 /* cckle$pack $ICCi_3,$CRj_int,$CCi,$cond */
4658   {
4659     FRV_INSN_CCKLE, "cckle", "cckle", 32,
4660     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4661   },
4662 /* cckgt$pack $ICCi_3,$CRj_int,$CCi,$cond */
4663   {
4664     FRV_INSN_CCKGT, "cckgt", "cckgt", 32,
4665     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4666   },
4667 /* ccklt$pack $ICCi_3,$CRj_int,$CCi,$cond */
4668   {
4669     FRV_INSN_CCKLT, "ccklt", "ccklt", 32,
4670     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4671   },
4672 /* cckge$pack $ICCi_3,$CRj_int,$CCi,$cond */
4673   {
4674     FRV_INSN_CCKGE, "cckge", "cckge", 32,
4675     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4676   },
4677 /* cckls$pack $ICCi_3,$CRj_int,$CCi,$cond */
4678   {
4679     FRV_INSN_CCKLS, "cckls", "cckls", 32,
4680     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4681   },
4682 /* cckhi$pack $ICCi_3,$CRj_int,$CCi,$cond */
4683   {
4684     FRV_INSN_CCKHI, "cckhi", "cckhi", 32,
4685     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4686   },
4687 /* cckc$pack $ICCi_3,$CRj_int,$CCi,$cond */
4688   {
4689     FRV_INSN_CCKC, "cckc", "cckc", 32,
4690     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4691   },
4692 /* ccknc$pack $ICCi_3,$CRj_int,$CCi,$cond */
4693   {
4694     FRV_INSN_CCKNC, "ccknc", "ccknc", 32,
4695     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4696   },
4697 /* cckn$pack $ICCi_3,$CRj_int,$CCi,$cond */
4698   {
4699     FRV_INSN_CCKN, "cckn", "cckn", 32,
4700     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4701   },
4702 /* cckp$pack $ICCi_3,$CRj_int,$CCi,$cond */
4703   {
4704     FRV_INSN_CCKP, "cckp", "cckp", 32,
4705     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4706   },
4707 /* cckv$pack $ICCi_3,$CRj_int,$CCi,$cond */
4708   {
4709     FRV_INSN_CCKV, "cckv", "cckv", 32,
4710     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4711   },
4712 /* ccknv$pack $ICCi_3,$CRj_int,$CCi,$cond */
4713   {
4714     FRV_INSN_CCKNV, "ccknv", "ccknv", 32,
4715     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4716   },
4717 /* cfckra$pack $CRj_float,$CCi,$cond */
4718   {
4719     FRV_INSN_CFCKRA, "cfckra", "cfckra", 32,
4720     { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4721   },
4722 /* cfckno$pack $CRj_float,$CCi,$cond */
4723   {
4724     FRV_INSN_CFCKNO, "cfckno", "cfckno", 32,
4725     { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4726   },
4727 /* cfckne$pack $FCCi_3,$CRj_float,$CCi,$cond */
4728   {
4729     FRV_INSN_CFCKNE, "cfckne", "cfckne", 32,
4730     { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4731   },
4732 /* cfckeq$pack $FCCi_3,$CRj_float,$CCi,$cond */
4733   {
4734     FRV_INSN_CFCKEQ, "cfckeq", "cfckeq", 32,
4735     { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4736   },
4737 /* cfcklg$pack $FCCi_3,$CRj_float,$CCi,$cond */
4738   {
4739     FRV_INSN_CFCKLG, "cfcklg", "cfcklg", 32,
4740     { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4741   },
4742 /* cfckue$pack $FCCi_3,$CRj_float,$CCi,$cond */
4743   {
4744     FRV_INSN_CFCKUE, "cfckue", "cfckue", 32,
4745     { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4746   },
4747 /* cfckul$pack $FCCi_3,$CRj_float,$CCi,$cond */
4748   {
4749     FRV_INSN_CFCKUL, "cfckul", "cfckul", 32,
4750     { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4751   },
4752 /* cfckge$pack $FCCi_3,$CRj_float,$CCi,$cond */
4753   {
4754     FRV_INSN_CFCKGE, "cfckge", "cfckge", 32,
4755     { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4756   },
4757 /* cfcklt$pack $FCCi_3,$CRj_float,$CCi,$cond */
4758   {
4759     FRV_INSN_CFCKLT, "cfcklt", "cfcklt", 32,
4760     { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4761   },
4762 /* cfckuge$pack $FCCi_3,$CRj_float,$CCi,$cond */
4763   {
4764     FRV_INSN_CFCKUGE, "cfckuge", "cfckuge", 32,
4765     { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4766   },
4767 /* cfckug$pack $FCCi_3,$CRj_float,$CCi,$cond */
4768   {
4769     FRV_INSN_CFCKUG, "cfckug", "cfckug", 32,
4770     { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4771   },
4772 /* cfckle$pack $FCCi_3,$CRj_float,$CCi,$cond */
4773   {
4774     FRV_INSN_CFCKLE, "cfckle", "cfckle", 32,
4775     { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4776   },
4777 /* cfckgt$pack $FCCi_3,$CRj_float,$CCi,$cond */
4778   {
4779     FRV_INSN_CFCKGT, "cfckgt", "cfckgt", 32,
4780     { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4781   },
4782 /* cfckule$pack $FCCi_3,$CRj_float,$CCi,$cond */
4783   {
4784     FRV_INSN_CFCKULE, "cfckule", "cfckule", 32,
4785     { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4786   },
4787 /* cfcku$pack $FCCi_3,$CRj_float,$CCi,$cond */
4788   {
4789     FRV_INSN_CFCKU, "cfcku", "cfcku", 32,
4790     { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4791   },
4792 /* cfcko$pack $FCCi_3,$CRj_float,$CCi,$cond */
4793   {
4794     FRV_INSN_CFCKO, "cfcko", "cfcko", 32,
4795     { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4796   },
4797 /* cjmpl$pack @($GRi,$GRj),$CCi,$cond */
4798   {
4799     FRV_INSN_CJMPL, "cjmpl", "cjmpl", 32,
4800     { 0|A(CONDITIONAL)|A(COND_CTI), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_5, FR500_MAJOR_I_5 } }
4801   },
4802 /* ccalll$pack @($GRi,$GRj),$CCi,$cond */
4803   {
4804     FRV_INSN_CCALLL, "ccalll", "ccalll", 32,
4805     { 0|A(CONDITIONAL)|A(COND_CTI), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_5, FR500_MAJOR_I_5 } }
4806   },
4807 /* ici$pack @($GRi,$GRj) */
4808   {
4809     FRV_INSN_ICI, "ici", "ici", 32,
4810     { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR500_MAJOR_C_2 } }
4811   },
4812 /* dci$pack @($GRi,$GRj) */
4813   {
4814     FRV_INSN_DCI, "dci", "dci", 32,
4815     { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR500_MAJOR_C_2 } }
4816   },
4817 /* icei$pack @($GRi,$GRj),$ae */
4818   {
4819     FRV_INSN_ICEI, "icei", "icei", 32,
4820     { 0, { (1<<MACH_FR400), UNIT_C, FR400_MAJOR_C_2, FR500_MAJOR_NONE } }
4821   },
4822 /* dcei$pack @($GRi,$GRj),$ae */
4823   {
4824     FRV_INSN_DCEI, "dcei", "dcei", 32,
4825     { 0, { (1<<MACH_FR400), UNIT_C, FR400_MAJOR_C_2, FR500_MAJOR_NONE } }
4826   },
4827 /* dcf$pack @($GRi,$GRj) */
4828   {
4829     FRV_INSN_DCF, "dcf", "dcf", 32,
4830     { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR500_MAJOR_C_2 } }
4831   },
4832 /* dcef$pack @($GRi,$GRj),$ae */
4833   {
4834     FRV_INSN_DCEF, "dcef", "dcef", 32,
4835     { 0, { (1<<MACH_FR400), UNIT_C, FR400_MAJOR_C_2, FR500_MAJOR_NONE } }
4836   },
4837 /* witlb$pack $GRk,@($GRi,$GRj) */
4838   {
4839     FRV_INSN_WITLB, "witlb", "witlb", 32,
4840     { 0|A(PRIVILEGED), { (1<<MACH_FRV), UNIT_C, FR400_MAJOR_NONE, FR500_MAJOR_C_2 } }
4841   },
4842 /* wdtlb$pack $GRk,@($GRi,$GRj) */
4843   {
4844     FRV_INSN_WDTLB, "wdtlb", "wdtlb", 32,
4845     { 0|A(PRIVILEGED), { (1<<MACH_FRV), UNIT_C, FR400_MAJOR_NONE, FR500_MAJOR_C_2 } }
4846   },
4847 /* itlbi$pack @($GRi,$GRj) */
4848   {
4849     FRV_INSN_ITLBI, "itlbi", "itlbi", 32,
4850     { 0|A(PRIVILEGED), { (1<<MACH_FRV), UNIT_C, FR400_MAJOR_NONE, FR500_MAJOR_C_2 } }
4851   },
4852 /* dtlbi$pack @($GRi,$GRj) */
4853   {
4854     FRV_INSN_DTLBI, "dtlbi", "dtlbi", 32,
4855     { 0|A(PRIVILEGED), { (1<<MACH_FRV), UNIT_C, FR400_MAJOR_NONE, FR500_MAJOR_C_2 } }
4856   },
4857 /* icpl$pack $GRi,$GRj,$lock */
4858   {
4859     FRV_INSN_ICPL, "icpl", "icpl", 32,
4860     { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR500_MAJOR_C_2 } }
4861   },
4862 /* dcpl$pack $GRi,$GRj,$lock */
4863   {
4864     FRV_INSN_DCPL, "dcpl", "dcpl", 32,
4865     { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR500_MAJOR_C_2 } }
4866   },
4867 /* icul$pack $GRi */
4868   {
4869     FRV_INSN_ICUL, "icul", "icul", 32,
4870     { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR500_MAJOR_C_2 } }
4871   },
4872 /* dcul$pack $GRi */
4873   {
4874     FRV_INSN_DCUL, "dcul", "dcul", 32,
4875     { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR500_MAJOR_C_2 } }
4876   },
4877 /* bar$pack */
4878   {
4879     FRV_INSN_BAR, "bar", "bar", 32,
4880     { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR500_MAJOR_C_2 } }
4881   },
4882 /* membar$pack */
4883   {
4884     FRV_INSN_MEMBAR, "membar", "membar", 32,
4885     { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR500_MAJOR_C_2 } }
4886   },
4887 /* cop1$pack $s6_1,$CPRi,$CPRj,$CPRk */
4888   {
4889     FRV_INSN_COP1, "cop1", "cop1", 32,
4890     { 0, { (1<<MACH_FRV), UNIT_C, FR400_MAJOR_NONE, FR500_MAJOR_C_2 } }
4891   },
4892 /* cop2$pack $s6_1,$CPRi,$CPRj,$CPRk */
4893   {
4894     FRV_INSN_COP2, "cop2", "cop2", 32,
4895     { 0, { (1<<MACH_FRV), UNIT_C, FR400_MAJOR_NONE, FR500_MAJOR_C_2 } }
4896   },
4897 /* clrgr$pack $GRk */
4898   {
4899     FRV_INSN_CLRGR, "clrgr", "clrgr", 32,
4900     { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_I01, FR400_MAJOR_NONE, FR500_MAJOR_I_6 } }
4901   },
4902 /* clrfr$pack $FRk */
4903   {
4904     FRV_INSN_CLRFR, "clrfr", "clrfr", 32,
4905     { 0|A(FR_ACCESS), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_I01, FR400_MAJOR_NONE, FR500_MAJOR_I_6 } }
4906   },
4907 /* clrga$pack */
4908   {
4909     FRV_INSN_CLRGA, "clrga", "clrga", 32,
4910     { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_I01, FR400_MAJOR_NONE, FR500_MAJOR_I_6 } }
4911   },
4912 /* clrfa$pack */
4913   {
4914     FRV_INSN_CLRFA, "clrfa", "clrfa", 32,
4915     { 0|A(FR_ACCESS), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_I01, FR400_MAJOR_NONE, FR500_MAJOR_I_6 } }
4916   },
4917 /* commitgr$pack $GRk */
4918   {
4919     FRV_INSN_COMMITGR, "commitgr", "commitgr", 32,
4920     { 0, { (1<<MACH_FRV)|(1<<MACH_FR500), UNIT_I01, FR400_MAJOR_NONE, FR500_MAJOR_I_6 } }
4921   },
4922 /* commitfr$pack $FRk */
4923   {
4924     FRV_INSN_COMMITFR, "commitfr", "commitfr", 32,
4925     { 0|A(FR_ACCESS), { (1<<MACH_FRV)|(1<<MACH_FR500), UNIT_I01, FR400_MAJOR_NONE, FR500_MAJOR_I_6 } }
4926   },
4927 /* commitga$pack */
4928   {
4929     FRV_INSN_COMMITGA, "commitga", "commitga", 32,
4930     { 0, { (1<<MACH_FRV)|(1<<MACH_FR500), UNIT_I01, FR400_MAJOR_NONE, FR500_MAJOR_I_6 } }
4931   },
4932 /* commitfa$pack */
4933   {
4934     FRV_INSN_COMMITFA, "commitfa", "commitfa", 32,
4935     { 0|A(FR_ACCESS), { (1<<MACH_FRV)|(1<<MACH_FR500), UNIT_I01, FR400_MAJOR_NONE, FR500_MAJOR_I_6 } }
4936   },
4937 /* fitos$pack $FRintj,$FRk */
4938   {
4939     FRV_INSN_FITOS, "fitos", "fitos", 32,
4940     { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } }
4941   },
4942 /* fstoi$pack $FRj,$FRintk */
4943   {
4944     FRV_INSN_FSTOI, "fstoi", "fstoi", 32,
4945     { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } }
4946   },
4947 /* fitod$pack $FRintj,$FRdoublek */
4948   {
4949     FRV_INSN_FITOD, "fitod", "fitod", 32,
4950     { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } }
4951   },
4952 /* fdtoi$pack $FRdoublej,$FRintk */
4953   {
4954     FRV_INSN_FDTOI, "fdtoi", "fdtoi", 32,
4955     { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } }
4956   },
4957 /* fditos$pack $FRintj,$FRk */
4958   {
4959     FRV_INSN_FDITOS, "fditos", "fditos", 32,
4960     { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } }
4961   },
4962 /* fdstoi$pack $FRj,$FRintk */
4963   {
4964     FRV_INSN_FDSTOI, "fdstoi", "fdstoi", 32,
4965     { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } }
4966   },
4967 /* nfditos$pack $FRintj,$FRk */
4968   {
4969     FRV_INSN_NFDITOS, "nfditos", "nfditos", 32,
4970     { 0|A(NON_EXCEPTING), { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } }
4971   },
4972 /* nfdstoi$pack $FRj,$FRintk */
4973   {
4974     FRV_INSN_NFDSTOI, "nfdstoi", "nfdstoi", 32,
4975     { 0|A(NON_EXCEPTING), { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } }
4976   },
4977 /* cfitos$pack $FRintj,$FRk,$CCi,$cond */
4978   {
4979     FRV_INSN_CFITOS, "cfitos", "cfitos", 32,
4980     { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } }
4981   },
4982 /* cfstoi$pack $FRj,$FRintk,$CCi,$cond */
4983   {
4984     FRV_INSN_CFSTOI, "cfstoi", "cfstoi", 32,
4985     { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } }
4986   },
4987 /* nfitos$pack $FRintj,$FRk */
4988   {
4989     FRV_INSN_NFITOS, "nfitos", "nfitos", 32,
4990     { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } }
4991   },
4992 /* nfstoi$pack $FRj,$FRintk */
4993   {
4994     FRV_INSN_NFSTOI, "nfstoi", "nfstoi", 32,
4995     { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } }
4996   },
4997 /* fmovs$pack $FRj,$FRk */
4998   {
4999     FRV_INSN_FMOVS, "fmovs", "fmovs", 32,
5000     { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } }
5001   },
5002 /* fmovd$pack $FRdoublej,$FRdoublek */
5003   {
5004     FRV_INSN_FMOVD, "fmovd", "fmovd", 32,
5005     { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } }
5006   },
5007 /* fdmovs$pack $FRj,$FRk */
5008   {
5009     FRV_INSN_FDMOVS, "fdmovs", "fdmovs", 32,
5010     { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } }
5011   },
5012 /* cfmovs$pack $FRj,$FRk,$CCi,$cond */
5013   {
5014     FRV_INSN_CFMOVS, "cfmovs", "cfmovs", 32,
5015     { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } }
5016   },
5017 /* fnegs$pack $FRj,$FRk */
5018   {
5019     FRV_INSN_FNEGS, "fnegs", "fnegs", 32,
5020     { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } }
5021   },
5022 /* fnegd$pack $FRdoublej,$FRdoublek */
5023   {
5024     FRV_INSN_FNEGD, "fnegd", "fnegd", 32,
5025     { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } }
5026   },
5027 /* fdnegs$pack $FRj,$FRk */
5028   {
5029     FRV_INSN_FDNEGS, "fdnegs", "fdnegs", 32,
5030     { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } }
5031   },
5032 /* cfnegs$pack $FRj,$FRk,$CCi,$cond */
5033   {
5034     FRV_INSN_CFNEGS, "cfnegs", "cfnegs", 32,
5035     { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } }
5036   },
5037 /* fabss$pack $FRj,$FRk */
5038   {
5039     FRV_INSN_FABSS, "fabss", "fabss", 32,
5040     { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } }
5041   },
5042 /* fabsd$pack $FRdoublej,$FRdoublek */
5043   {
5044     FRV_INSN_FABSD, "fabsd", "fabsd", 32,
5045     { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } }
5046   },
5047 /* fdabss$pack $FRj,$FRk */
5048   {
5049     FRV_INSN_FDABSS, "fdabss", "fdabss", 32,
5050     { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } }
5051   },
5052 /* cfabss$pack $FRj,$FRk,$CCi,$cond */
5053   {
5054     FRV_INSN_CFABSS, "cfabss", "cfabss", 32,
5055     { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } }
5056   },
5057 /* fsqrts$pack $FRj,$FRk */
5058   {
5059     FRV_INSN_FSQRTS, "fsqrts", "fsqrts", 32,
5060     { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_4 } }
5061   },
5062 /* fdsqrts$pack $FRj,$FRk */
5063   {
5064     FRV_INSN_FDSQRTS, "fdsqrts", "fdsqrts", 32,
5065     { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_4 } }
5066   },
5067 /* nfdsqrts$pack $FRj,$FRk */
5068   {
5069     FRV_INSN_NFDSQRTS, "nfdsqrts", "nfdsqrts", 32,
5070     { 0|A(NON_EXCEPTING), { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_4 } }
5071   },
5072 /* fsqrtd$pack $FRdoublej,$FRdoublek */
5073   {
5074     FRV_INSN_FSQRTD, "fsqrtd", "fsqrtd", 32,
5075     { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_4 } }
5076   },
5077 /* cfsqrts$pack $FRj,$FRk,$CCi,$cond */
5078   {
5079     FRV_INSN_CFSQRTS, "cfsqrts", "cfsqrts", 32,
5080     { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_4 } }
5081   },
5082 /* nfsqrts$pack $FRj,$FRk */
5083   {
5084     FRV_INSN_NFSQRTS, "nfsqrts", "nfsqrts", 32,
5085     { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_4 } }
5086   },
5087 /* fadds$pack $FRi,$FRj,$FRk */
5088   {
5089     FRV_INSN_FADDS, "fadds", "fadds", 32,
5090     { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_2 } }
5091   },
5092 /* fsubs$pack $FRi,$FRj,$FRk */
5093   {
5094     FRV_INSN_FSUBS, "fsubs", "fsubs", 32,
5095     { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_2 } }
5096   },
5097 /* fmuls$pack $FRi,$FRj,$FRk */
5098   {
5099     FRV_INSN_FMULS, "fmuls", "fmuls", 32,
5100     { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_3 } }
5101   },
5102 /* fdivs$pack $FRi,$FRj,$FRk */
5103   {
5104     FRV_INSN_FDIVS, "fdivs", "fdivs", 32,
5105     { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_4 } }
5106   },
5107 /* faddd$pack $FRdoublei,$FRdoublej,$FRdoublek */
5108   {
5109     FRV_INSN_FADDD, "faddd", "faddd", 32,
5110     { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_2 } }
5111   },
5112 /* fsubd$pack $FRdoublei,$FRdoublej,$FRdoublek */
5113   {
5114     FRV_INSN_FSUBD, "fsubd", "fsubd", 32,
5115     { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_2 } }
5116   },
5117 /* fmuld$pack $FRdoublei,$FRdoublej,$FRdoublek */
5118   {
5119     FRV_INSN_FMULD, "fmuld", "fmuld", 32,
5120     { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_3 } }
5121   },
5122 /* fdivd$pack $FRdoublei,$FRdoublej,$FRdoublek */
5123   {
5124     FRV_INSN_FDIVD, "fdivd", "fdivd", 32,
5125     { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_4 } }
5126   },
5127 /* cfadds$pack $FRi,$FRj,$FRk,$CCi,$cond */
5128   {
5129     FRV_INSN_CFADDS, "cfadds", "cfadds", 32,
5130     { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_2 } }
5131   },
5132 /* cfsubs$pack $FRi,$FRj,$FRk,$CCi,$cond */
5133   {
5134     FRV_INSN_CFSUBS, "cfsubs", "cfsubs", 32,
5135     { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_2 } }
5136   },
5137 /* cfmuls$pack $FRi,$FRj,$FRk,$CCi,$cond */
5138   {
5139     FRV_INSN_CFMULS, "cfmuls", "cfmuls", 32,
5140     { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_3 } }
5141   },
5142 /* cfdivs$pack $FRi,$FRj,$FRk,$CCi,$cond */
5143   {
5144     FRV_INSN_CFDIVS, "cfdivs", "cfdivs", 32,
5145     { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_4 } }
5146   },
5147 /* nfadds$pack $FRi,$FRj,$FRk */
5148   {
5149     FRV_INSN_NFADDS, "nfadds", "nfadds", 32,
5150     { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_2 } }
5151   },
5152 /* nfsubs$pack $FRi,$FRj,$FRk */
5153   {
5154     FRV_INSN_NFSUBS, "nfsubs", "nfsubs", 32,
5155     { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_2 } }
5156   },
5157 /* nfmuls$pack $FRi,$FRj,$FRk */
5158   {
5159     FRV_INSN_NFMULS, "nfmuls", "nfmuls", 32,
5160     { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_3 } }
5161   },
5162 /* nfdivs$pack $FRi,$FRj,$FRk */
5163   {
5164     FRV_INSN_NFDIVS, "nfdivs", "nfdivs", 32,
5165     { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_4 } }
5166   },
5167 /* fcmps$pack $FRi,$FRj,$FCCi_2 */
5168   {
5169     FRV_INSN_FCMPS, "fcmps", "fcmps", 32,
5170     { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_2 } }
5171   },
5172 /* fcmpd$pack $FRdoublei,$FRdoublej,$FCCi_2 */
5173   {
5174     FRV_INSN_FCMPD, "fcmpd", "fcmpd", 32,
5175     { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_2 } }
5176   },
5177 /* cfcmps$pack $FRi,$FRj,$FCCi_2,$CCi,$cond */
5178   {
5179     FRV_INSN_CFCMPS, "cfcmps", "cfcmps", 32,
5180     { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_2 } }
5181   },
5182 /* fdcmps$pack $FRi,$FRj,$FCCi_2 */
5183   {
5184     FRV_INSN_FDCMPS, "fdcmps", "fdcmps", 32,
5185     { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_6 } }
5186   },
5187 /* fmadds$pack $FRi,$FRj,$FRk */
5188   {
5189     FRV_INSN_FMADDS, "fmadds", "fmadds", 32,
5190     { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_5 } }
5191   },
5192 /* fmsubs$pack $FRi,$FRj,$FRk */
5193   {
5194     FRV_INSN_FMSUBS, "fmsubs", "fmsubs", 32,
5195     { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_5 } }
5196   },
5197 /* fmaddd$pack $FRdoublei,$FRdoublej,$FRdoublek */
5198   {
5199     FRV_INSN_FMADDD, "fmaddd", "fmaddd", 32,
5200     { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_5 } }
5201   },
5202 /* fmsubd$pack $FRdoublei,$FRdoublej,$FRdoublek */
5203   {
5204     FRV_INSN_FMSUBD, "fmsubd", "fmsubd", 32,
5205     { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_5 } }
5206   },
5207 /* fdmadds$pack $FRi,$FRj,$FRk */
5208   {
5209     FRV_INSN_FDMADDS, "fdmadds", "fdmadds", 32,
5210     { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_5 } }
5211   },
5212 /* nfdmadds$pack $FRi,$FRj,$FRk */
5213   {
5214     FRV_INSN_NFDMADDS, "nfdmadds", "nfdmadds", 32,
5215     { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_5 } }
5216   },
5217 /* cfmadds$pack $FRi,$FRj,$FRk,$CCi,$cond */
5218   {
5219     FRV_INSN_CFMADDS, "cfmadds", "cfmadds", 32,
5220     { 0|A(CONDITIONAL), { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_5 } }
5221   },
5222 /* cfmsubs$pack $FRi,$FRj,$FRk,$CCi,$cond */
5223   {
5224     FRV_INSN_CFMSUBS, "cfmsubs", "cfmsubs", 32,
5225     { 0|A(CONDITIONAL), { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_5 } }
5226   },
5227 /* nfmadds$pack $FRi,$FRj,$FRk */
5228   {
5229     FRV_INSN_NFMADDS, "nfmadds", "nfmadds", 32,
5230     { 0|A(NON_EXCEPTING), { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_5 } }
5231   },
5232 /* nfmsubs$pack $FRi,$FRj,$FRk */
5233   {
5234     FRV_INSN_NFMSUBS, "nfmsubs", "nfmsubs", 32,
5235     { 0|A(NON_EXCEPTING), { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_5 } }
5236   },
5237 /* fmas$pack $FRi,$FRj,$FRk */
5238   {
5239     FRV_INSN_FMAS, "fmas", "fmas", 32,
5240     { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_5 } }
5241   },
5242 /* fmss$pack $FRi,$FRj,$FRk */
5243   {
5244     FRV_INSN_FMSS, "fmss", "fmss", 32,
5245     { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_5 } }
5246   },
5247 /* fdmas$pack $FRi,$FRj,$FRk */
5248   {
5249     FRV_INSN_FDMAS, "fdmas", "fdmas", 32,
5250     { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_5 } }
5251   },
5252 /* fdmss$pack $FRi,$FRj,$FRk */
5253   {
5254     FRV_INSN_FDMSS, "fdmss", "fdmss", 32,
5255     { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_5 } }
5256   },
5257 /* nfdmas$pack $FRi,$FRj,$FRk */
5258   {
5259     FRV_INSN_NFDMAS, "nfdmas", "nfdmas", 32,
5260     { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_5 } }
5261   },
5262 /* nfdmss$pack $FRi,$FRj,$FRk */
5263   {
5264     FRV_INSN_NFDMSS, "nfdmss", "nfdmss", 32,
5265     { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_5 } }
5266   },
5267 /* cfmas$pack $FRi,$FRj,$FRk,$CCi,$cond */
5268   {
5269     FRV_INSN_CFMAS, "cfmas", "cfmas", 32,
5270     { 0|A(CONDITIONAL), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_5 } }
5271   },
5272 /* cfmss$pack $FRi,$FRj,$FRk,$CCi,$cond */
5273   {
5274     FRV_INSN_CFMSS, "cfmss", "cfmss", 32,
5275     { 0|A(CONDITIONAL), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_5 } }
5276   },
5277 /* fmad$pack $FRi,$FRj,$FRk */
5278   {
5279     FRV_INSN_FMAD, "fmad", "fmad", 32,
5280     { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_5 } }
5281   },
5282 /* fmsd$pack $FRi,$FRj,$FRk */
5283   {
5284     FRV_INSN_FMSD, "fmsd", "fmsd", 32,
5285     { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_5 } }
5286   },
5287 /* nfmas$pack $FRi,$FRj,$FRk */
5288   {
5289     FRV_INSN_NFMAS, "nfmas", "nfmas", 32,
5290     { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_5 } }
5291   },
5292 /* nfmss$pack $FRi,$FRj,$FRk */
5293   {
5294     FRV_INSN_NFMSS, "nfmss", "nfmss", 32,
5295     { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_5 } }
5296   },
5297 /* fdadds$pack $FRi,$FRj,$FRk */
5298   {
5299     FRV_INSN_FDADDS, "fdadds", "fdadds", 32,
5300     { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_6 } }
5301   },
5302 /* fdsubs$pack $FRi,$FRj,$FRk */
5303   {
5304     FRV_INSN_FDSUBS, "fdsubs", "fdsubs", 32,
5305     { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_6 } }
5306   },
5307 /* fdmuls$pack $FRi,$FRj,$FRk */
5308   {
5309     FRV_INSN_FDMULS, "fdmuls", "fdmuls", 32,
5310     { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_7 } }
5311   },
5312 /* fddivs$pack $FRi,$FRj,$FRk */
5313   {
5314     FRV_INSN_FDDIVS, "fddivs", "fddivs", 32,
5315     { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_7 } }
5316   },
5317 /* fdsads$pack $FRi,$FRj,$FRk */
5318   {
5319     FRV_INSN_FDSADS, "fdsads", "fdsads", 32,
5320     { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_6 } }
5321   },
5322 /* fdmulcs$pack $FRi,$FRj,$FRk */
5323   {
5324     FRV_INSN_FDMULCS, "fdmulcs", "fdmulcs", 32,
5325     { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_7 } }
5326   },
5327 /* nfdmulcs$pack $FRi,$FRj,$FRk */
5328   {
5329     FRV_INSN_NFDMULCS, "nfdmulcs", "nfdmulcs", 32,
5330     { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_7 } }
5331   },
5332 /* nfdadds$pack $FRi,$FRj,$FRk */
5333   {
5334     FRV_INSN_NFDADDS, "nfdadds", "nfdadds", 32,
5335     { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_6 } }
5336   },
5337 /* nfdsubs$pack $FRi,$FRj,$FRk */
5338   {
5339     FRV_INSN_NFDSUBS, "nfdsubs", "nfdsubs", 32,
5340     { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_6 } }
5341   },
5342 /* nfdmuls$pack $FRi,$FRj,$FRk */
5343   {
5344     FRV_INSN_NFDMULS, "nfdmuls", "nfdmuls", 32,
5345     { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_7 } }
5346   },
5347 /* nfddivs$pack $FRi,$FRj,$FRk */
5348   {
5349     FRV_INSN_NFDDIVS, "nfddivs", "nfddivs", 32,
5350     { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_7 } }
5351   },
5352 /* nfdsads$pack $FRi,$FRj,$FRk */
5353   {
5354     FRV_INSN_NFDSADS, "nfdsads", "nfdsads", 32,
5355     { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_6 } }
5356   },
5357 /* nfdcmps$pack $FRi,$FRj,$FCCi_2 */
5358   {
5359     FRV_INSN_NFDCMPS, "nfdcmps", "nfdcmps", 32,
5360     { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_6 } }
5361   },
5362 /* mhsetlos$pack $u12,$FRklo */
5363   {
5364     FRV_INSN_MHSETLOS, "mhsetlos", "mhsetlos", 32,
5365     { 0, { (1<<MACH_FR400), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_NONE } }
5366   },
5367 /* mhsethis$pack $u12,$FRkhi */
5368   {
5369     FRV_INSN_MHSETHIS, "mhsethis", "mhsethis", 32,
5370     { 0, { (1<<MACH_FR400), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_NONE } }
5371   },
5372 /* mhdsets$pack $u12,$FRintk */
5373   {
5374     FRV_INSN_MHDSETS, "mhdsets", "mhdsets", 32,
5375     { 0, { (1<<MACH_FR400), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_NONE } }
5376   },
5377 /* mhsetloh$pack $s5,$FRklo */
5378   {
5379     FRV_INSN_MHSETLOH, "mhsetloh", "mhsetloh", 32,
5380     { 0, { (1<<MACH_FR400), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_NONE } }
5381   },
5382 /* mhsethih$pack $s5,$FRkhi */
5383   {
5384     FRV_INSN_MHSETHIH, "mhsethih", "mhsethih", 32,
5385     { 0, { (1<<MACH_FR400), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_NONE } }
5386   },
5387 /* mhdseth$pack $s5,$FRintk */
5388   {
5389     FRV_INSN_MHDSETH, "mhdseth", "mhdseth", 32,
5390     { 0, { (1<<MACH_FR400), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_NONE } }
5391   },
5392 /* mand$pack $FRinti,$FRintj,$FRintk */
5393   {
5394     FRV_INSN_MAND, "mand", "mand", 32,
5395     { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_1 } }
5396   },
5397 /* mor$pack $FRinti,$FRintj,$FRintk */
5398   {
5399     FRV_INSN_MOR, "mor", "mor", 32,
5400     { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_1 } }
5401   },
5402 /* mxor$pack $FRinti,$FRintj,$FRintk */
5403   {
5404     FRV_INSN_MXOR, "mxor", "mxor", 32,
5405     { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_1 } }
5406   },
5407 /* cmand$pack $FRinti,$FRintj,$FRintk,$CCi,$cond */
5408   {
5409     FRV_INSN_CMAND, "cmand", "cmand", 32,
5410     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_1 } }
5411   },
5412 /* cmor$pack $FRinti,$FRintj,$FRintk,$CCi,$cond */
5413   {
5414     FRV_INSN_CMOR, "cmor", "cmor", 32,
5415     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_1 } }
5416   },
5417 /* cmxor$pack $FRinti,$FRintj,$FRintk,$CCi,$cond */
5418   {
5419     FRV_INSN_CMXOR, "cmxor", "cmxor", 32,
5420     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_1 } }
5421   },
5422 /* mnot$pack $FRintj,$FRintk */
5423   {
5424     FRV_INSN_MNOT, "mnot", "mnot", 32,
5425     { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_1 } }
5426   },
5427 /* cmnot$pack $FRintj,$FRintk,$CCi,$cond */
5428   {
5429     FRV_INSN_CMNOT, "cmnot", "cmnot", 32,
5430     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_1 } }
5431   },
5432 /* mrotli$pack $FRinti,$u6,$FRintk */
5433   {
5434     FRV_INSN_MROTLI, "mrotli", "mrotli", 32,
5435     { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_2 } }
5436   },
5437 /* mrotri$pack $FRinti,$u6,$FRintk */
5438   {
5439     FRV_INSN_MROTRI, "mrotri", "mrotri", 32,
5440     { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_2 } }
5441   },
5442 /* mwcut$pack $FRinti,$FRintj,$FRintk */
5443   {
5444     FRV_INSN_MWCUT, "mwcut", "mwcut", 32,
5445     { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_2 } }
5446   },
5447 /* mwcuti$pack $FRinti,$u6,$FRintk */
5448   {
5449     FRV_INSN_MWCUTI, "mwcuti", "mwcuti", 32,
5450     { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_2 } }
5451   },
5452 /* mcut$pack $ACC40Si,$FRintj,$FRintk */
5453   {
5454     FRV_INSN_MCUT, "mcut", "mcut", 32,
5455     { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_2 } }
5456   },
5457 /* mcuti$pack $ACC40Si,$s6,$FRintk */
5458   {
5459     FRV_INSN_MCUTI, "mcuti", "mcuti", 32,
5460     { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_2 } }
5461   },
5462 /* mcutss$pack $ACC40Si,$FRintj,$FRintk */
5463   {
5464     FRV_INSN_MCUTSS, "mcutss", "mcutss", 32,
5465     { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_2 } }
5466   },
5467 /* mcutssi$pack $ACC40Si,$s6,$FRintk */
5468   {
5469     FRV_INSN_MCUTSSI, "mcutssi", "mcutssi", 32,
5470     { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_2 } }
5471   },
5472 /* mdcutssi$pack $ACC40Si,$s6,$FRintk */
5473   {
5474     FRV_INSN_MDCUTSSI, "mdcutssi", "mdcutssi", 32,
5475     { 0, { (1<<MACH_FR400), UNIT_FM0, FR400_MAJOR_M_2, FR500_MAJOR_NONE } }
5476   },
5477 /* maveh$pack $FRinti,$FRintj,$FRintk */
5478   {
5479     FRV_INSN_MAVEH, "maveh", "maveh", 32,
5480     { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_1 } }
5481   },
5482 /* msllhi$pack $FRinti,$u6,$FRintk */
5483   {
5484     FRV_INSN_MSLLHI, "msllhi", "msllhi", 32,
5485     { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_2 } }
5486   },
5487 /* msrlhi$pack $FRinti,$u6,$FRintk */
5488   {
5489     FRV_INSN_MSRLHI, "msrlhi", "msrlhi", 32,
5490     { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_2 } }
5491   },
5492 /* msrahi$pack $FRinti,$u6,$FRintk */
5493   {
5494     FRV_INSN_MSRAHI, "msrahi", "msrahi", 32,
5495     { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_2 } }
5496   },
5497 /* mdrotli$pack $FRinti,$u6,$FRintk */
5498   {
5499     FRV_INSN_MDROTLI, "mdrotli", "mdrotli", 32,
5500     { 0, { (1<<MACH_FR400), UNIT_FM0, FR400_MAJOR_M_2, FR500_MAJOR_NONE } }
5501   },
5502 /* mcplhi$pack $FRinti,$u6,$FRintk */
5503   {
5504     FRV_INSN_MCPLHI, "mcplhi", "mcplhi", 32,
5505     { 0, { (1<<MACH_FR400), UNIT_FM0, FR400_MAJOR_M_2, FR500_MAJOR_NONE } }
5506   },
5507 /* mcpli$pack $FRinti,$u6,$FRintk */
5508   {
5509     FRV_INSN_MCPLI, "mcpli", "mcpli", 32,
5510     { 0, { (1<<MACH_FR400), UNIT_FM0, FR400_MAJOR_M_2, FR500_MAJOR_NONE } }
5511   },
5512 /* msaths$pack $FRinti,$FRintj,$FRintk */
5513   {
5514     FRV_INSN_MSATHS, "msaths", "msaths", 32,
5515     { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_1 } }
5516   },
5517 /* mqsaths$pack $FRinti,$FRintj,$FRintk */
5518   {
5519     FRV_INSN_MQSATHS, "mqsaths", "mqsaths", 32,
5520     { 0, { (1<<MACH_FR400), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_NONE } }
5521   },
5522 /* msathu$pack $FRinti,$FRintj,$FRintk */
5523   {
5524     FRV_INSN_MSATHU, "msathu", "msathu", 32,
5525     { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_1 } }
5526   },
5527 /* mcmpsh$pack $FRinti,$FRintj,$FCCk */
5528   {
5529     FRV_INSN_MCMPSH, "mcmpsh", "mcmpsh", 32,
5530     { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_1 } }
5531   },
5532 /* mcmpuh$pack $FRinti,$FRintj,$FCCk */
5533   {
5534     FRV_INSN_MCMPUH, "mcmpuh", "mcmpuh", 32,
5535     { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_1 } }
5536   },
5537 /* mabshs$pack $FRintj,$FRintk */
5538   {
5539     FRV_INSN_MABSHS, "mabshs", "mabshs", 32,
5540     { 0, { (1<<MACH_FR400), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_NONE } }
5541   },
5542 /* maddhss$pack $FRinti,$FRintj,$FRintk */
5543   {
5544     FRV_INSN_MADDHSS, "maddhss", "maddhss", 32,
5545     { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_1 } }
5546   },
5547 /* maddhus$pack $FRinti,$FRintj,$FRintk */
5548   {
5549     FRV_INSN_MADDHUS, "maddhus", "maddhus", 32,
5550     { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_1 } }
5551   },
5552 /* msubhss$pack $FRinti,$FRintj,$FRintk */
5553   {
5554     FRV_INSN_MSUBHSS, "msubhss", "msubhss", 32,
5555     { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_1 } }
5556   },
5557 /* msubhus$pack $FRinti,$FRintj,$FRintk */
5558   {
5559     FRV_INSN_MSUBHUS, "msubhus", "msubhus", 32,
5560     { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_1 } }
5561   },
5562 /* cmaddhss$pack $FRinti,$FRintj,$FRintk,$CCi,$cond */
5563   {
5564     FRV_INSN_CMADDHSS, "cmaddhss", "cmaddhss", 32,
5565     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_1 } }
5566   },
5567 /* cmaddhus$pack $FRinti,$FRintj,$FRintk,$CCi,$cond */
5568   {
5569     FRV_INSN_CMADDHUS, "cmaddhus", "cmaddhus", 32,
5570     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_1 } }
5571   },
5572 /* cmsubhss$pack $FRinti,$FRintj,$FRintk,$CCi,$cond */
5573   {
5574     FRV_INSN_CMSUBHSS, "cmsubhss", "cmsubhss", 32,
5575     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_1 } }
5576   },
5577 /* cmsubhus$pack $FRinti,$FRintj,$FRintk,$CCi,$cond */
5578   {
5579     FRV_INSN_CMSUBHUS, "cmsubhus", "cmsubhus", 32,
5580     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_1 } }
5581   },
5582 /* mqaddhss$pack $FRinti,$FRintj,$FRintk */
5583   {
5584     FRV_INSN_MQADDHSS, "mqaddhss", "mqaddhss", 32,
5585     { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_1 } }
5586   },
5587 /* mqaddhus$pack $FRinti,$FRintj,$FRintk */
5588   {
5589     FRV_INSN_MQADDHUS, "mqaddhus", "mqaddhus", 32,
5590     { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_1 } }
5591   },
5592 /* mqsubhss$pack $FRinti,$FRintj,$FRintk */
5593   {
5594     FRV_INSN_MQSUBHSS, "mqsubhss", "mqsubhss", 32,
5595     { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_1 } }
5596   },
5597 /* mqsubhus$pack $FRinti,$FRintj,$FRintk */
5598   {
5599     FRV_INSN_MQSUBHUS, "mqsubhus", "mqsubhus", 32,
5600     { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_1 } }
5601   },
5602 /* cmqaddhss$pack $FRinti,$FRintj,$FRintk,$CCi,$cond */
5603   {
5604     FRV_INSN_CMQADDHSS, "cmqaddhss", "cmqaddhss", 32,
5605     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_1 } }
5606   },
5607 /* cmqaddhus$pack $FRinti,$FRintj,$FRintk,$CCi,$cond */
5608   {
5609     FRV_INSN_CMQADDHUS, "cmqaddhus", "cmqaddhus", 32,
5610     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_1 } }
5611   },
5612 /* cmqsubhss$pack $FRinti,$FRintj,$FRintk,$CCi,$cond */
5613   {
5614     FRV_INSN_CMQSUBHSS, "cmqsubhss", "cmqsubhss", 32,
5615     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_1 } }
5616   },
5617 /* cmqsubhus$pack $FRinti,$FRintj,$FRintk,$CCi,$cond */
5618   {
5619     FRV_INSN_CMQSUBHUS, "cmqsubhus", "cmqsubhus", 32,
5620     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_1 } }
5621   },
5622 /* maddaccs$pack $ACC40Si,$ACC40Sk */
5623   {
5624     FRV_INSN_MADDACCS, "maddaccs", "maddaccs", 32,
5625     { 0, { (1<<MACH_FR400), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_NONE } }
5626   },
5627 /* msubaccs$pack $ACC40Si,$ACC40Sk */
5628   {
5629     FRV_INSN_MSUBACCS, "msubaccs", "msubaccs", 32,
5630     { 0, { (1<<MACH_FR400), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_NONE } }
5631   },
5632 /* mdaddaccs$pack $ACC40Si,$ACC40Sk */
5633   {
5634     FRV_INSN_MDADDACCS, "mdaddaccs", "mdaddaccs", 32,
5635     { 0, { (1<<MACH_FR400), UNIT_FM0, FR400_MAJOR_M_2, FR500_MAJOR_NONE } }
5636   },
5637 /* mdsubaccs$pack $ACC40Si,$ACC40Sk */
5638   {
5639     FRV_INSN_MDSUBACCS, "mdsubaccs", "mdsubaccs", 32,
5640     { 0, { (1<<MACH_FR400), UNIT_FM0, FR400_MAJOR_M_2, FR500_MAJOR_NONE } }
5641   },
5642 /* masaccs$pack $ACC40Si,$ACC40Sk */
5643   {
5644     FRV_INSN_MASACCS, "masaccs", "masaccs", 32,
5645     { 0, { (1<<MACH_FR400), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_NONE } }
5646   },
5647 /* mdasaccs$pack $ACC40Si,$ACC40Sk */
5648   {
5649     FRV_INSN_MDASACCS, "mdasaccs", "mdasaccs", 32,
5650     { 0, { (1<<MACH_FR400), UNIT_FM0, FR400_MAJOR_M_2, FR500_MAJOR_NONE } }
5651   },
5652 /* mmulhs$pack $FRinti,$FRintj,$ACC40Sk */
5653   {
5654     FRV_INSN_MMULHS, "mmulhs", "mmulhs", 32,
5655     { 0|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_4 } }
5656   },
5657 /* mmulhu$pack $FRinti,$FRintj,$ACC40Sk */
5658   {
5659     FRV_INSN_MMULHU, "mmulhu", "mmulhu", 32,
5660     { 0|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_4 } }
5661   },
5662 /* mmulxhs$pack $FRinti,$FRintj,$ACC40Sk */
5663   {
5664     FRV_INSN_MMULXHS, "mmulxhs", "mmulxhs", 32,
5665     { 0|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_4 } }
5666   },
5667 /* mmulxhu$pack $FRinti,$FRintj,$ACC40Sk */
5668   {
5669     FRV_INSN_MMULXHU, "mmulxhu", "mmulxhu", 32,
5670     { 0|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_4 } }
5671   },
5672 /* cmmulhs$pack $FRinti,$FRintj,$ACC40Sk,$CCi,$cond */
5673   {
5674     FRV_INSN_CMMULHS, "cmmulhs", "cmmulhs", 32,
5675     { 0|A(CONDITIONAL)|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_4 } }
5676   },
5677 /* cmmulhu$pack $FRinti,$FRintj,$ACC40Sk,$CCi,$cond */
5678   {
5679     FRV_INSN_CMMULHU, "cmmulhu", "cmmulhu", 32,
5680     { 0|A(CONDITIONAL)|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_4 } }
5681   },
5682 /* mqmulhs$pack $FRinti,$FRintj,$ACC40Sk */
5683   {
5684     FRV_INSN_MQMULHS, "mqmulhs", "mqmulhs", 32,
5685     { 0|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_4 } }
5686   },
5687 /* mqmulhu$pack $FRinti,$FRintj,$ACC40Sk */
5688   {
5689     FRV_INSN_MQMULHU, "mqmulhu", "mqmulhu", 32,
5690     { 0|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_4 } }
5691   },
5692 /* mqmulxhs$pack $FRinti,$FRintj,$ACC40Sk */
5693   {
5694     FRV_INSN_MQMULXHS, "mqmulxhs", "mqmulxhs", 32,
5695     { 0|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_4 } }
5696   },
5697 /* mqmulxhu$pack $FRinti,$FRintj,$ACC40Sk */
5698   {
5699     FRV_INSN_MQMULXHU, "mqmulxhu", "mqmulxhu", 32,
5700     { 0|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_4 } }
5701   },
5702 /* cmqmulhs$pack $FRinti,$FRintj,$ACC40Sk,$CCi,$cond */
5703   {
5704     FRV_INSN_CMQMULHS, "cmqmulhs", "cmqmulhs", 32,
5705     { 0|A(CONDITIONAL)|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_4 } }
5706   },
5707 /* cmqmulhu$pack $FRinti,$FRintj,$ACC40Sk,$CCi,$cond */
5708   {
5709     FRV_INSN_CMQMULHU, "cmqmulhu", "cmqmulhu", 32,
5710     { 0|A(CONDITIONAL)|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_4 } }
5711   },
5712 /* mmachs$pack $FRinti,$FRintj,$ACC40Sk */
5713   {
5714     FRV_INSN_MMACHS, "mmachs", "mmachs", 32,
5715     { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_4 } }
5716   },
5717 /* mmachu$pack $FRinti,$FRintj,$ACC40Uk */
5718   {
5719     FRV_INSN_MMACHU, "mmachu", "mmachu", 32,
5720     { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_4 } }
5721   },
5722 /* mmrdhs$pack $FRinti,$FRintj,$ACC40Sk */
5723   {
5724     FRV_INSN_MMRDHS, "mmrdhs", "mmrdhs", 32,
5725     { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_4 } }
5726   },
5727 /* mmrdhu$pack $FRinti,$FRintj,$ACC40Uk */
5728   {
5729     FRV_INSN_MMRDHU, "mmrdhu", "mmrdhu", 32,
5730     { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_4 } }
5731   },
5732 /* cmmachs$pack $FRinti,$FRintj,$ACC40Sk,$CCi,$cond */
5733   {
5734     FRV_INSN_CMMACHS, "cmmachs", "cmmachs", 32,
5735     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_4 } }
5736   },
5737 /* cmmachu$pack $FRinti,$FRintj,$ACC40Uk,$CCi,$cond */
5738   {
5739     FRV_INSN_CMMACHU, "cmmachu", "cmmachu", 32,
5740     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_4 } }
5741   },
5742 /* mqmachs$pack $FRinti,$FRintj,$ACC40Sk */
5743   {
5744     FRV_INSN_MQMACHS, "mqmachs", "mqmachs", 32,
5745     { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_4 } }
5746   },
5747 /* mqmachu$pack $FRinti,$FRintj,$ACC40Uk */
5748   {
5749     FRV_INSN_MQMACHU, "mqmachu", "mqmachu", 32,
5750     { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_4 } }
5751   },
5752 /* cmqmachs$pack $FRinti,$FRintj,$ACC40Sk,$CCi,$cond */
5753   {
5754     FRV_INSN_CMQMACHS, "cmqmachs", "cmqmachs", 32,
5755     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_4 } }
5756   },
5757 /* cmqmachu$pack $FRinti,$FRintj,$ACC40Uk,$CCi,$cond */
5758   {
5759     FRV_INSN_CMQMACHU, "cmqmachu", "cmqmachu", 32,
5760     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_4 } }
5761   },
5762 /* mqxmachs$pack $FRinti,$FRintj,$ACC40Sk */
5763   {
5764     FRV_INSN_MQXMACHS, "mqxmachs", "mqxmachs", 32,
5765     { 0, { (1<<MACH_FR400), UNIT_FM0, FR400_MAJOR_M_2, FR500_MAJOR_NONE } }
5766   },
5767 /* mqxmacxhs$pack $FRinti,$FRintj,$ACC40Sk */
5768   {
5769     FRV_INSN_MQXMACXHS, "mqxmacxhs", "mqxmacxhs", 32,
5770     { 0, { (1<<MACH_FR400), UNIT_FM0, FR400_MAJOR_M_2, FR500_MAJOR_NONE } }
5771   },
5772 /* mqmacxhs$pack $FRinti,$FRintj,$ACC40Sk */
5773   {
5774     FRV_INSN_MQMACXHS, "mqmacxhs", "mqmacxhs", 32,
5775     { 0, { (1<<MACH_FR400), UNIT_FM0, FR400_MAJOR_M_2, FR500_MAJOR_NONE } }
5776   },
5777 /* mcpxrs$pack $FRinti,$FRintj,$ACC40Sk */
5778   {
5779     FRV_INSN_MCPXRS, "mcpxrs", "mcpxrs", 32,
5780     { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_4 } }
5781   },
5782 /* mcpxru$pack $FRinti,$FRintj,$ACC40Sk */
5783   {
5784     FRV_INSN_MCPXRU, "mcpxru", "mcpxru", 32,
5785     { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_4 } }
5786   },
5787 /* mcpxis$pack $FRinti,$FRintj,$ACC40Sk */
5788   {
5789     FRV_INSN_MCPXIS, "mcpxis", "mcpxis", 32,
5790     { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_4 } }
5791   },
5792 /* mcpxiu$pack $FRinti,$FRintj,$ACC40Sk */
5793   {
5794     FRV_INSN_MCPXIU, "mcpxiu", "mcpxiu", 32,
5795     { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_4 } }
5796   },
5797 /* cmcpxrs$pack $FRinti,$FRintj,$ACC40Sk,$CCi,$cond */
5798   {
5799     FRV_INSN_CMCPXRS, "cmcpxrs", "cmcpxrs", 32,
5800     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_4 } }
5801   },
5802 /* cmcpxru$pack $FRinti,$FRintj,$ACC40Sk,$CCi,$cond */
5803   {
5804     FRV_INSN_CMCPXRU, "cmcpxru", "cmcpxru", 32,
5805     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_4 } }
5806   },
5807 /* cmcpxis$pack $FRinti,$FRintj,$ACC40Sk,$CCi,$cond */
5808   {
5809     FRV_INSN_CMCPXIS, "cmcpxis", "cmcpxis", 32,
5810     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_4 } }
5811   },
5812 /* cmcpxiu$pack $FRinti,$FRintj,$ACC40Sk,$CCi,$cond */
5813   {
5814     FRV_INSN_CMCPXIU, "cmcpxiu", "cmcpxiu", 32,
5815     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_4 } }
5816   },
5817 /* mqcpxrs$pack $FRinti,$FRintj,$ACC40Sk */
5818   {
5819     FRV_INSN_MQCPXRS, "mqcpxrs", "mqcpxrs", 32,
5820     { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_4 } }
5821   },
5822 /* mqcpxru$pack $FRinti,$FRintj,$ACC40Sk */
5823   {
5824     FRV_INSN_MQCPXRU, "mqcpxru", "mqcpxru", 32,
5825     { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_4 } }
5826   },
5827 /* mqcpxis$pack $FRinti,$FRintj,$ACC40Sk */
5828   {
5829     FRV_INSN_MQCPXIS, "mqcpxis", "mqcpxis", 32,
5830     { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_4 } }
5831   },
5832 /* mqcpxiu$pack $FRinti,$FRintj,$ACC40Sk */
5833   {
5834     FRV_INSN_MQCPXIU, "mqcpxiu", "mqcpxiu", 32,
5835     { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_4 } }
5836   },
5837 /* mexpdhw$pack $FRinti,$u6,$FRintk */
5838   {
5839     FRV_INSN_MEXPDHW, "mexpdhw", "mexpdhw", 32,
5840     { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_2 } }
5841   },
5842 /* cmexpdhw$pack $FRinti,$u6,$FRintk,$CCi,$cond */
5843   {
5844     FRV_INSN_CMEXPDHW, "cmexpdhw", "cmexpdhw", 32,
5845     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_2 } }
5846   },
5847 /* mexpdhd$pack $FRinti,$u6,$FRintk */
5848   {
5849     FRV_INSN_MEXPDHD, "mexpdhd", "mexpdhd", 32,
5850     { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_2 } }
5851   },
5852 /* cmexpdhd$pack $FRinti,$u6,$FRintk,$CCi,$cond */
5853   {
5854     FRV_INSN_CMEXPDHD, "cmexpdhd", "cmexpdhd", 32,
5855     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_2 } }
5856   },
5857 /* mpackh$pack $FRinti,$FRintj,$FRintk */
5858   {
5859     FRV_INSN_MPACKH, "mpackh", "mpackh", 32,
5860     { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_2 } }
5861   },
5862 /* mdpackh$pack $FRinti,$FRintj,$FRintk */
5863   {
5864     FRV_INSN_MDPACKH, "mdpackh", "mdpackh", 32,
5865     { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_5 } }
5866   },
5867 /* munpackh$pack $FRinti,$FRintk */
5868   {
5869     FRV_INSN_MUNPACKH, "munpackh", "munpackh", 32,
5870     { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_2 } }
5871   },
5872 /* mdunpackh$pack $FRinti,$FRintk */
5873   {
5874     FRV_INSN_MDUNPACKH, "mdunpackh", "mdunpackh", 32,
5875     { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_M_7 } }
5876   },
5877 /* mbtoh$pack $FRintj,$FRintk */
5878   {
5879     FRV_INSN_MBTOH, "mbtoh", "mbtoh", 32,
5880     { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_2 } }
5881   },
5882 /* cmbtoh$pack $FRintj,$FRintk,$CCi,$cond */
5883   {
5884     FRV_INSN_CMBTOH, "cmbtoh", "cmbtoh", 32,
5885     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_2 } }
5886   },
5887 /* mhtob$pack $FRintj,$FRintk */
5888   {
5889     FRV_INSN_MHTOB, "mhtob", "mhtob", 32,
5890     { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_2 } }
5891   },
5892 /* cmhtob$pack $FRintj,$FRintk,$CCi,$cond */
5893   {
5894     FRV_INSN_CMHTOB, "cmhtob", "cmhtob", 32,
5895     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_2 } }
5896   },
5897 /* mbtohe$pack $FRintj,$FRintk */
5898   {
5899     FRV_INSN_MBTOHE, "mbtohe", "mbtohe", 32,
5900     { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_M_7 } }
5901   },
5902 /* cmbtohe$pack $FRintj,$FRintk,$CCi,$cond */
5903   {
5904     FRV_INSN_CMBTOHE, "cmbtohe", "cmbtohe", 32,
5905     { 0|A(CONDITIONAL), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_M_7 } }
5906   },
5907 /* mclracc$pack $ACC40Sk,$A */
5908   {
5909     FRV_INSN_MCLRACC, "mclracc", "mclracc", 32,
5910     { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_M_3 } }
5911   },
5912 /* mrdacc$pack $ACC40Si,$FRintk */
5913   {
5914     FRV_INSN_MRDACC, "mrdacc", "mrdacc", 32,
5915     { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_2 } }
5916   },
5917 /* mrdaccg$pack $ACCGi,$FRintk */
5918   {
5919     FRV_INSN_MRDACCG, "mrdaccg", "mrdaccg", 32,
5920     { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_2 } }
5921   },
5922 /* mwtacc$pack $FRinti,$ACC40Sk */
5923   {
5924     FRV_INSN_MWTACC, "mwtacc", "mwtacc", 32,
5925     { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_3 } }
5926   },
5927 /* mwtaccg$pack $FRinti,$ACCGk */
5928   {
5929     FRV_INSN_MWTACCG, "mwtaccg", "mwtaccg", 32,
5930     { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_3 } }
5931   },
5932 /* mcop1$pack $FRi,$FRj,$FRk */
5933   {
5934     FRV_INSN_MCOP1, "mcop1", "mcop1", 32,
5935     { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_M_1 } }
5936   },
5937 /* mcop2$pack $FRi,$FRj,$FRk */
5938   {
5939     FRV_INSN_MCOP2, "mcop2", "mcop2", 32,
5940     { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_M_1 } }
5941   },
5942 /* fnop$pack */
5943   {
5944     FRV_INSN_FNOP, "fnop", "fnop", 32,
5945     { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_8 } }
5946   },
5947 };
5948
5949 #undef OP
5950 #undef A
5951
5952 /* Initialize anything needed to be done once, before any cpu_open call.  */
5953 static void init_tables PARAMS ((void));
5954
5955 static void
5956 init_tables ()
5957 {
5958 }
5959
5960 static const CGEN_MACH * lookup_mach_via_bfd_name
5961   PARAMS ((const CGEN_MACH *, const char *));
5962 static void build_hw_table  PARAMS ((CGEN_CPU_TABLE *));
5963 static void build_ifield_table  PARAMS ((CGEN_CPU_TABLE *));
5964 static void build_operand_table PARAMS ((CGEN_CPU_TABLE *));
5965 static void build_insn_table    PARAMS ((CGEN_CPU_TABLE *));
5966 static void frv_cgen_rebuild_tables PARAMS ((CGEN_CPU_TABLE *));
5967
5968 /* Subroutine of frv_cgen_cpu_open to look up a mach via its bfd name.  */
5969
5970 static const CGEN_MACH *
5971 lookup_mach_via_bfd_name (table, name)
5972      const CGEN_MACH *table;
5973      const char *name;
5974 {
5975   while (table->name)
5976     {
5977       if (strcmp (name, table->bfd_name) == 0)
5978         return table;
5979       ++table;
5980     }
5981   abort ();
5982 }
5983
5984 /* Subroutine of frv_cgen_cpu_open to build the hardware table.  */
5985
5986 static void
5987 build_hw_table (cd)
5988      CGEN_CPU_TABLE *cd;
5989 {
5990   int i;
5991   int machs = cd->machs;
5992   const CGEN_HW_ENTRY *init = & frv_cgen_hw_table[0];
5993   /* MAX_HW is only an upper bound on the number of selected entries.
5994      However each entry is indexed by it's enum so there can be holes in
5995      the table.  */
5996   const CGEN_HW_ENTRY **selected =
5997     (const CGEN_HW_ENTRY **) xmalloc (MAX_HW * sizeof (CGEN_HW_ENTRY *));
5998
5999   cd->hw_table.init_entries = init;
6000   cd->hw_table.entry_size = sizeof (CGEN_HW_ENTRY);
6001   memset (selected, 0, MAX_HW * sizeof (CGEN_HW_ENTRY *));
6002   /* ??? For now we just use machs to determine which ones we want.  */
6003   for (i = 0; init[i].name != NULL; ++i)
6004     if (CGEN_HW_ATTR_VALUE (&init[i], CGEN_HW_MACH)
6005         & machs)
6006       selected[init[i].type] = &init[i];
6007   cd->hw_table.entries = selected;
6008   cd->hw_table.num_entries = MAX_HW;
6009 }
6010
6011 /* Subroutine of frv_cgen_cpu_open to build the hardware table.  */
6012
6013 static void
6014 build_ifield_table (cd)
6015      CGEN_CPU_TABLE *cd;
6016 {
6017   cd->ifld_table = & frv_cgen_ifld_table[0];
6018 }
6019
6020 /* Subroutine of frv_cgen_cpu_open to build the hardware table.  */
6021
6022 static void
6023 build_operand_table (cd)
6024      CGEN_CPU_TABLE *cd;
6025 {
6026   int i;
6027   int machs = cd->machs;
6028   const CGEN_OPERAND *init = & frv_cgen_operand_table[0];
6029   /* MAX_OPERANDS is only an upper bound on the number of selected entries.
6030      However each entry is indexed by it's enum so there can be holes in
6031      the table.  */
6032   const CGEN_OPERAND **selected =
6033     (const CGEN_OPERAND **) xmalloc (MAX_OPERANDS * sizeof (CGEN_OPERAND *));
6034
6035   cd->operand_table.init_entries = init;
6036   cd->operand_table.entry_size = sizeof (CGEN_OPERAND);
6037   memset (selected, 0, MAX_OPERANDS * sizeof (CGEN_OPERAND *));
6038   /* ??? For now we just use mach to determine which ones we want.  */
6039   for (i = 0; init[i].name != NULL; ++i)
6040     if (CGEN_OPERAND_ATTR_VALUE (&init[i], CGEN_OPERAND_MACH)
6041         & machs)
6042       selected[init[i].type] = &init[i];
6043   cd->operand_table.entries = selected;
6044   cd->operand_table.num_entries = MAX_OPERANDS;
6045 }
6046
6047 /* Subroutine of frv_cgen_cpu_open to build the hardware table.
6048    ??? This could leave out insns not supported by the specified mach/isa,
6049    but that would cause errors like "foo only supported by bar" to become
6050    "unknown insn", so for now we include all insns and require the app to
6051    do the checking later.
6052    ??? On the other hand, parsing of such insns may require their hardware or
6053    operand elements to be in the table [which they mightn't be].  */
6054
6055 static void
6056 build_insn_table (cd)
6057      CGEN_CPU_TABLE *cd;
6058 {
6059   int i;
6060   const CGEN_IBASE *ib = & frv_cgen_insn_table[0];
6061   CGEN_INSN *insns = (CGEN_INSN *) xmalloc (MAX_INSNS * sizeof (CGEN_INSN));
6062
6063   memset (insns, 0, MAX_INSNS * sizeof (CGEN_INSN));
6064   for (i = 0; i < MAX_INSNS; ++i)
6065     insns[i].base = &ib[i];
6066   cd->insn_table.init_entries = insns;
6067   cd->insn_table.entry_size = sizeof (CGEN_IBASE);
6068   cd->insn_table.num_init_entries = MAX_INSNS;
6069 }
6070
6071 /* Subroutine of frv_cgen_cpu_open to rebuild the tables.  */
6072
6073 static void
6074 frv_cgen_rebuild_tables (cd)
6075      CGEN_CPU_TABLE *cd;
6076 {
6077   int i;
6078   unsigned int isas = cd->isas;
6079   unsigned int machs = cd->machs;
6080
6081   cd->int_insn_p = CGEN_INT_INSN_P;
6082
6083   /* Data derived from the isa spec.  */
6084 #define UNSET (CGEN_SIZE_UNKNOWN + 1)
6085   cd->default_insn_bitsize = UNSET;
6086   cd->base_insn_bitsize = UNSET;
6087   cd->min_insn_bitsize = 65535; /* some ridiculously big number */
6088   cd->max_insn_bitsize = 0;
6089   for (i = 0; i < MAX_ISAS; ++i)
6090     if (((1 << i) & isas) != 0)
6091       {
6092         const CGEN_ISA *isa = & frv_cgen_isa_table[i];
6093
6094         /* Default insn sizes of all selected isas must be
6095            equal or we set the result to 0, meaning "unknown".  */
6096         if (cd->default_insn_bitsize == UNSET)
6097           cd->default_insn_bitsize = isa->default_insn_bitsize;
6098         else if (isa->default_insn_bitsize == cd->default_insn_bitsize)
6099           ; /* this is ok */
6100         else
6101           cd->default_insn_bitsize = CGEN_SIZE_UNKNOWN;
6102
6103         /* Base insn sizes of all selected isas must be equal
6104            or we set the result to 0, meaning "unknown".  */
6105         if (cd->base_insn_bitsize == UNSET)
6106           cd->base_insn_bitsize = isa->base_insn_bitsize;
6107         else if (isa->base_insn_bitsize == cd->base_insn_bitsize)
6108           ; /* this is ok */
6109         else
6110           cd->base_insn_bitsize = CGEN_SIZE_UNKNOWN;
6111
6112         /* Set min,max insn sizes.  */
6113         if (isa->min_insn_bitsize < cd->min_insn_bitsize)
6114           cd->min_insn_bitsize = isa->min_insn_bitsize;
6115         if (isa->max_insn_bitsize > cd->max_insn_bitsize)
6116           cd->max_insn_bitsize = isa->max_insn_bitsize;
6117       }
6118
6119   /* Data derived from the mach spec.  */
6120   for (i = 0; i < MAX_MACHS; ++i)
6121     if (((1 << i) & machs) != 0)
6122       {
6123         const CGEN_MACH *mach = & frv_cgen_mach_table[i];
6124
6125         if (mach->insn_chunk_bitsize != 0)
6126         {
6127           if (cd->insn_chunk_bitsize != 0 && cd->insn_chunk_bitsize != mach->insn_chunk_bitsize)
6128             {
6129               fprintf (stderr, "frv_cgen_rebuild_tables: conflicting insn-chunk-bitsize values: `%d' vs. `%d'\n",
6130                        cd->insn_chunk_bitsize, mach->insn_chunk_bitsize);
6131               abort ();
6132             }
6133
6134           cd->insn_chunk_bitsize = mach->insn_chunk_bitsize;
6135         }
6136       }
6137
6138   /* Determine which hw elements are used by MACH.  */
6139   build_hw_table (cd);
6140
6141   /* Build the ifield table.  */
6142   build_ifield_table (cd);
6143
6144   /* Determine which operands are used by MACH/ISA.  */
6145   build_operand_table (cd);
6146
6147   /* Build the instruction table.  */
6148   build_insn_table (cd);
6149 }
6150
6151 /* Initialize a cpu table and return a descriptor.
6152    It's much like opening a file, and must be the first function called.
6153    The arguments are a set of (type/value) pairs, terminated with
6154    CGEN_CPU_OPEN_END.
6155
6156    Currently supported values:
6157    CGEN_CPU_OPEN_ISAS:    bitmap of values in enum isa_attr
6158    CGEN_CPU_OPEN_MACHS:   bitmap of values in enum mach_attr
6159    CGEN_CPU_OPEN_BFDMACH: specify 1 mach using bfd name
6160    CGEN_CPU_OPEN_ENDIAN:  specify endian choice
6161    CGEN_CPU_OPEN_END:     terminates arguments
6162
6163    ??? Simultaneous multiple isas might not make sense, but it's not (yet)
6164    precluded.
6165
6166    ??? We only support ISO C stdargs here, not K&R.
6167    Laziness, plus experiment to see if anything requires K&R - eventually
6168    K&R will no longer be supported - e.g. GDB is currently trying this.  */
6169
6170 CGEN_CPU_DESC
6171 frv_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...)
6172 {
6173   CGEN_CPU_TABLE *cd = (CGEN_CPU_TABLE *) xmalloc (sizeof (CGEN_CPU_TABLE));
6174   static int init_p;
6175   unsigned int isas = 0;  /* 0 = "unspecified" */
6176   unsigned int machs = 0; /* 0 = "unspecified" */
6177   enum cgen_endian endian = CGEN_ENDIAN_UNKNOWN;
6178   va_list ap;
6179
6180   if (! init_p)
6181     {
6182       init_tables ();
6183       init_p = 1;
6184     }
6185
6186   memset (cd, 0, sizeof (*cd));
6187
6188   va_start (ap, arg_type);
6189   while (arg_type != CGEN_CPU_OPEN_END)
6190     {
6191       switch (arg_type)
6192         {
6193         case CGEN_CPU_OPEN_ISAS :
6194           isas = va_arg (ap, unsigned int);
6195           break;
6196         case CGEN_CPU_OPEN_MACHS :
6197           machs = va_arg (ap, unsigned int);
6198           break;
6199         case CGEN_CPU_OPEN_BFDMACH :
6200           {
6201             const char *name = va_arg (ap, const char *);
6202             const CGEN_MACH *mach =
6203               lookup_mach_via_bfd_name (frv_cgen_mach_table, name);
6204
6205             machs |= 1 << mach->num;
6206             break;
6207           }
6208         case CGEN_CPU_OPEN_ENDIAN :
6209           endian = va_arg (ap, enum cgen_endian);
6210           break;
6211         default :
6212           fprintf (stderr, "frv_cgen_cpu_open: unsupported argument `%d'\n",
6213                    arg_type);
6214           abort (); /* ??? return NULL? */
6215         }
6216       arg_type = va_arg (ap, enum cgen_cpu_open_arg);
6217     }
6218   va_end (ap);
6219
6220   /* mach unspecified means "all" */
6221   if (machs == 0)
6222     machs = (1 << MAX_MACHS) - 1;
6223   /* base mach is always selected */
6224   machs |= 1;
6225   /* isa unspecified means "all" */
6226   if (isas == 0)
6227     isas = (1 << MAX_ISAS) - 1;
6228   if (endian == CGEN_ENDIAN_UNKNOWN)
6229     {
6230       /* ??? If target has only one, could have a default.  */
6231       fprintf (stderr, "frv_cgen_cpu_open: no endianness specified\n");
6232       abort ();
6233     }
6234
6235   cd->isas = isas;
6236   cd->machs = machs;
6237   cd->endian = endian;
6238   /* FIXME: for the sparc case we can determine insn-endianness statically.
6239      The worry here is where both data and insn endian can be independently
6240      chosen, in which case this function will need another argument.
6241      Actually, will want to allow for more arguments in the future anyway.  */
6242   cd->insn_endian = endian;
6243
6244   /* Table (re)builder.  */
6245   cd->rebuild_tables = frv_cgen_rebuild_tables;
6246   frv_cgen_rebuild_tables (cd);
6247
6248   /* Default to not allowing signed overflow.  */
6249   cd->signed_overflow_ok_p = 0;
6250
6251   return (CGEN_CPU_DESC) cd;
6252 }
6253
6254 /* Cover fn to frv_cgen_cpu_open to handle the simple case of 1 isa, 1 mach.
6255    MACH_NAME is the bfd name of the mach.  */
6256
6257 CGEN_CPU_DESC
6258 frv_cgen_cpu_open_1 (mach_name, endian)
6259      const char *mach_name;
6260      enum cgen_endian endian;
6261 {
6262   return frv_cgen_cpu_open (CGEN_CPU_OPEN_BFDMACH, mach_name,
6263                                CGEN_CPU_OPEN_ENDIAN, endian,
6264                                CGEN_CPU_OPEN_END);
6265 }
6266
6267 /* Close a cpu table.
6268    ??? This can live in a machine independent file, but there's currently
6269    no place to put this file (there's no libcgen).  libopcodes is the wrong
6270    place as some simulator ports use this but they don't use libopcodes.  */
6271
6272 void
6273 frv_cgen_cpu_close (cd)
6274      CGEN_CPU_DESC cd;
6275 {
6276   unsigned int i;
6277   const CGEN_INSN *insns;
6278
6279   if (cd->macro_insn_table.init_entries)
6280     {
6281       insns = cd->macro_insn_table.init_entries;
6282       for (i = 0; i < cd->macro_insn_table.num_init_entries; ++i, ++insns)
6283         {
6284           if (CGEN_INSN_RX ((insns)))
6285             regfree (CGEN_INSN_RX (insns));
6286         }
6287     }
6288
6289   if (cd->insn_table.init_entries)
6290     {
6291       insns = cd->insn_table.init_entries;
6292       for (i = 0; i < cd->insn_table.num_init_entries; ++i, ++insns)
6293         {
6294           if (CGEN_INSN_RX (insns))
6295             regfree (CGEN_INSN_RX (insns));
6296         }
6297     }
6298
6299
6300
6301   if (cd->macro_insn_table.init_entries)
6302     free ((CGEN_INSN *) cd->macro_insn_table.init_entries);
6303
6304   if (cd->insn_table.init_entries)
6305     free ((CGEN_INSN *) cd->insn_table.init_entries);
6306
6307   if (cd->hw_table.entries)
6308     free ((CGEN_HW_ENTRY *) cd->hw_table.entries);
6309
6310   if (cd->operand_table.entries)
6311     free ((CGEN_HW_ENTRY *) cd->operand_table.entries);
6312
6313   free (cd);
6314 }
6315