1 @c Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005,
2 @c 2006, 2007, 2008, 2009 Free Software Foundation, Inc.
3 @c This is part of the GAS manual.
4 @c For copying conditions, see the file as.texinfo.
9 @chapter ARM Dependent Features
13 @node Machine Dependencies
14 @chapter ARM Dependent Features
20 * ARM Options:: Options
22 * ARM Floating Point:: Floating Point
23 * ARM Directives:: ARM Machine Directives
24 * ARM Opcodes:: Opcodes
25 * ARM Mapping Symbols:: Mapping Symbols
26 * ARM Unwinding Tutorial:: Unwinding
31 @cindex ARM options (none)
32 @cindex options for ARM (none)
36 @cindex @code{-mcpu=} command line option, ARM
37 @item -mcpu=@var{processor}[+@var{extension}@dots{}]
38 This option specifies the target processor. The assembler will issue an
39 error message if an attempt is made to assemble an instruction which
40 will not execute on the target processor. The following processor names are
85 @code{fa526} (Faraday FA526 processor),
86 @code{fa626} (Faraday FA626 processor),
105 @code{fa626te} (Faraday FA626TE processor),
106 @code{fa726te} (Faraday FA726TE processor),
122 @code{ep9312} (ARM920 with Cirrus Maverick coprocessor),
123 @code{i80200} (Intel XScale processor)
124 @code{iwmmxt} (Intel(r) XScale processor with Wireless MMX(tm) technology coprocessor)
127 The special name @code{all} may be used to allow the
128 assembler to accept instructions valid for any ARM processor.
130 In addition to the basic instruction set, the assembler can be told to
131 accept various extension mnemonics that extend the processor using the
132 co-processor instruction space. For example, @code{-mcpu=arm920+maverick}
133 is equivalent to specifying @code{-mcpu=ep9312}. The following extensions
134 are currently supported:
140 @cindex @code{-march=} command line option, ARM
141 @item -march=@var{architecture}[+@var{extension}@dots{}]
142 This option specifies the target architecture. The assembler will issue
143 an error message if an attempt is made to assemble an instruction which
144 will not execute on the target architecture. The following architecture
145 names are recognized:
173 If both @code{-mcpu} and
174 @code{-march} are specified, the assembler will use
175 the setting for @code{-mcpu}.
177 The architecture option can be extended with the same instruction set
178 extension options as the @code{-mcpu} option.
180 @cindex @code{-mfpu=} command line option, ARM
181 @item -mfpu=@var{floating-point-format}
183 This option specifies the floating point format to assemble for. The
184 assembler will issue an error message if an attempt is made to assemble
185 an instruction which will not execute on the target floating point unit.
186 The following format options are recognized:
212 In addition to determining which instructions are assembled, this option
213 also affects the way in which the @code{.double} assembler directive behaves
214 when assembling little-endian code.
216 The default is dependent on the processor selected. For Architecture 5 or
217 later, the default is to assembler for VFP instructions; for earlier
218 architectures the default is to assemble for FPA instructions.
220 @cindex @code{-mthumb} command line option, ARM
222 This option specifies that the assembler should start assembling Thumb
223 instructions; that is, it should behave as though the file starts with a
224 @code{.code 16} directive.
226 @cindex @code{-mthumb-interwork} command line option, ARM
227 @item -mthumb-interwork
228 This option specifies that the output generated by the assembler should
229 be marked as supporting interworking.
231 @cindex @code{-mimplicit-it} command line option, ARM
232 @item -mimplicit-it=never
233 @itemx -mimplicit-it=always
234 @itemx -mimplicit-it=arm
235 @itemx -mimplicit-it=thumb
236 The @code{-mimplicit-it} option controls the behavior of the assembler when
237 conditional instructions are not enclosed in IT blocks.
238 There are four possible behaviors.
239 If @code{never} is specified, such constructs cause a warning in ARM
240 code and an error in Thumb-2 code.
241 If @code{always} is specified, such constructs are accepted in both
242 ARM and Thumb-2 code, where the IT instruction is added implicitly.
243 If @code{arm} is specified, such constructs are accepted in ARM code
244 and cause an error in Thumb-2 code.
245 If @code{thumb} is specified, such constructs cause a warning in ARM
246 code and are accepted in Thumb-2 code. If you omit this option, the
247 behavior is equivalent to @code{-mimplicit-it=arm}.
249 @cindex @code{-mapcs} command line option, ARM
250 @item -mapcs @code{[26|32]}
251 This option specifies that the output generated by the assembler should
252 be marked as supporting the indicated version of the Arm Procedure.
255 @cindex @code{-matpcs} command line option, ARM
257 This option specifies that the output generated by the assembler should
258 be marked as supporting the Arm/Thumb Procedure Calling Standard. If
259 enabled this option will cause the assembler to create an empty
260 debugging section in the object file called .arm.atpcs. Debuggers can
261 use this to determine the ABI being used by.
263 @cindex @code{-mapcs-float} command line option, ARM
265 This indicates the floating point variant of the APCS should be
266 used. In this variant floating point arguments are passed in FP
267 registers rather than integer registers.
269 @cindex @code{-mapcs-reentrant} command line option, ARM
270 @item -mapcs-reentrant
271 This indicates that the reentrant variant of the APCS should be used.
272 This variant supports position independent code.
274 @cindex @code{-mfloat-abi=} command line option, ARM
275 @item -mfloat-abi=@var{abi}
276 This option specifies that the output generated by the assembler should be
277 marked as using specified floating point ABI.
278 The following values are recognized:
284 @cindex @code{-eabi=} command line option, ARM
285 @item -meabi=@var{ver}
286 This option specifies which EABI version the produced object files should
288 The following values are recognized:
294 @cindex @code{-EB} command line option, ARM
296 This option specifies that the output generated by the assembler should
297 be marked as being encoded for a big-endian processor.
299 @cindex @code{-EL} command line option, ARM
301 This option specifies that the output generated by the assembler should
302 be marked as being encoded for a little-endian processor.
304 @cindex @code{-k} command line option, ARM
305 @cindex PIC code generation for ARM
307 This option specifies that the output of the assembler should be marked
308 as position-independent code (PIC).
310 @cindex @code{--fix-v4bx} command line option, ARM
312 Allow @code{BX} instructions in ARMv4 code. This is intended for use with
313 the linker option of the same name.
315 @cindex @code{-mwarn-deprecated} command line option, ARM
316 @item -mwarn-deprecated
317 @itemx -mno-warn-deprecated
318 Enable or disable warnings about using deprecated options or
319 features. The default is to warn.
327 * ARM-Instruction-Set:: Instruction Set
328 * ARM-Chars:: Special Characters
329 * ARM-Regs:: Register Names
330 * ARM-Relocations:: Relocations
333 @node ARM-Instruction-Set
334 @subsection Instruction Set Syntax
335 Two slightly different syntaxes are support for ARM and THUMB
336 instructions. The default, @code{divided}, uses the old style where
337 ARM and THUMB instructions had their own, separate syntaxes. The new,
338 @code{unified} syntax, which can be selected via the @code{.syntax}
339 directive, and has the following main features:
343 Immediate operands do not require a @code{#} prefix.
346 The @code{IT} instruction may appear, and if it does it is validated
347 against subsequent conditional affixes. In ARM mode it does not
348 generate machine code, in THUMB mode it does.
351 For ARM instructions the conditional affixes always appear at the end
352 of the instruction. For THUMB instructions conditional affixes can be
353 used, but only inside the scope of an @code{IT} instruction.
356 All of the instructions new to the V6T2 architecture (and later) are
357 available. (Only a few such instructions can be written in the
358 @code{divided} syntax).
361 The @code{.N} and @code{.W} suffixes are recognized and honored.
364 All instructions set the flags if and only if they have an @code{s}
369 @subsection Special Characters
371 @cindex line comment character, ARM
372 @cindex ARM line comment character
373 The presence of a @samp{@@} on a line indicates the start of a comment
374 that extends to the end of the current line. If a @samp{#} appears as
375 the first character of a line, the whole line is treated as a comment.
377 @cindex line separator, ARM
378 @cindex statement separator, ARM
379 @cindex ARM line separator
380 The @samp{;} character can be used instead of a newline to separate
383 @cindex immediate character, ARM
384 @cindex ARM immediate character
385 Either @samp{#} or @samp{$} can be used to indicate immediate operands.
387 @cindex identifiers, ARM
388 @cindex ARM identifiers
389 *TODO* Explain about /data modifier on symbols.
392 @subsection Register Names
394 @cindex ARM register names
395 @cindex register names, ARM
396 *TODO* Explain about ARM register naming, and the predefined names.
398 @node ARM Floating Point
399 @section Floating Point
401 @cindex floating point, ARM (@sc{ieee})
402 @cindex ARM floating point (@sc{ieee})
403 The ARM family uses @sc{ieee} floating-point numbers.
405 @node ARM-Relocations
406 @subsection ARM relocation generation
408 @cindex data relocations, ARM
409 @cindex ARM data relocations
410 Specific data relocations can be generated by putting the relocation name
411 in parentheses after the symbol name. For example:
417 This will generate an @samp{R_ARM_TARGET1} relocation against the symbol
419 The following relocations are supported:
432 For compatibility with older toolchains the assembler also accepts
433 @code{(PLT)} after branch targets. This will generate the deprecated
434 @samp{R_ARM_PLT32} relocation.
436 @cindex MOVW and MOVT relocations, ARM
437 Relocations for @samp{MOVW} and @samp{MOVT} instructions can be generated
438 by prefixing the value with @samp{#:lower16:} and @samp{#:upper16}
439 respectively. For example to load the 32-bit address of foo into r0:
442 MOVW r0, #:lower16:foo
443 MOVT r0, #:upper16:foo
447 @section ARM Machine Directives
449 @cindex machine directives, ARM
450 @cindex ARM machine directives
453 @c AAAAAAAAAAAAAAAAAAAAAAAAA
455 @cindex @code{.2byte} directive, ARM
456 @cindex @code{.4byte} directive, ARM
457 @cindex @code{.8byte} directive, ARM
458 @item .2byte @var{expression} [, @var{expression}]*
459 @itemx .4byte @var{expression} [, @var{expression}]*
460 @itemx .8byte @var{expression} [, @var{expression}]*
461 These directives write 2, 4 or 8 byte values to the output section.
463 @cindex @code{.align} directive, ARM
464 @item .align @var{expression} [, @var{expression}]
465 This is the generic @var{.align} directive. For the ARM however if the
466 first argument is zero (ie no alignment is needed) the assembler will
467 behave as if the argument had been 2 (ie pad to the next four byte
468 boundary). This is for compatibility with ARM's own assembler.
470 @cindex @code{.arch} directive, ARM
471 @item .arch @var{name}
472 Select the target architecture. Valid values for @var{name} are the same as
473 for the @option{-march} commandline option.
475 @cindex @code{.arm} directive, ARM
477 This performs the same action as @var{.code 32}.
480 @cindex @code{.pad} directive, ARM
481 @item .pad #@var{count}
482 Generate unwinder annotations for a stack adjustment of @var{count} bytes.
483 A positive value indicates the function prologue allocated stack space by
484 decrementing the stack pointer.
486 @c BBBBBBBBBBBBBBBBBBBBBBBBBB
488 @cindex @code{.bss} directive, ARM
490 This directive switches to the @code{.bss} section.
492 @c CCCCCCCCCCCCCCCCCCCCCCCCCC
494 @cindex @code{.cantunwind} directive, ARM
496 Prevents unwinding through the current function. No personality routine
497 or exception table data is required or permitted.
499 @cindex @code{.code} directive, ARM
500 @item .code @code{[16|32]}
501 This directive selects the instruction set being generated. The value 16
502 selects Thumb, with the value 32 selecting ARM.
504 @cindex @code{.cpu} directive, ARM
505 @item .cpu @var{name}
506 Select the target processor. Valid values for @var{name} are the same as
507 for the @option{-mcpu} commandline option.
509 @c DDDDDDDDDDDDDDDDDDDDDDDDDD
511 @cindex @code{.dn} and @code{.qn} directives, ARM
512 @item @var{name} .dn @var{register name} [@var{.type}] [[@var{index}]]
513 @item @var{name} .qn @var{register name} [@var{.type}] [[@var{index}]]
515 The @code{dn} and @code{qn} directives are used to create typed
516 and/or indexed register aliases for use in Advanced SIMD Extension
517 (Neon) instructions. The former should be used to create aliases
518 of double-precision registers, and the latter to create aliases of
519 quad-precision registers.
521 If these directives are used to create typed aliases, those aliases can
522 be used in Neon instructions instead of writing types after the mnemonic
523 or after each operand. For example:
532 This is equivalent to writing the following:
538 Aliases created using @code{dn} or @code{qn} can be destroyed using
541 @c EEEEEEEEEEEEEEEEEEEEEEEEEE
543 @cindex @code{.eabi_attribute} directive, ARM
544 @item .eabi_attribute @var{tag}, @var{value}
545 Set the EABI object attribute @var{tag} to @var{value}.
547 The @var{tag} is either an attribute number, or one of the following:
548 @code{Tag_CPU_raw_name}, @code{Tag_CPU_name}, @code{Tag_CPU_arch},
549 @code{Tag_CPU_arch_profile}, @code{Tag_ARM_ISA_use},
550 @code{Tag_THUMB_ISA_use}, @code{Tag_VFP_arch}, @code{Tag_WMMX_arch},
551 @code{Tag_Advanced_SIMD_arch}, @code{Tag_PCS_config},
552 @code{Tag_ABI_PCS_R9_use}, @code{Tag_ABI_PCS_RW_data},
553 @code{Tag_ABI_PCS_RO_data}, @code{Tag_ABI_PCS_GOT_use},
554 @code{Tag_ABI_PCS_wchar_t}, @code{Tag_ABI_FP_rounding},
555 @code{Tag_ABI_FP_denormal}, @code{Tag_ABI_FP_exceptions},
556 @code{Tag_ABI_FP_user_exceptions}, @code{Tag_ABI_FP_number_model},
557 @code{Tag_ABI_align8_needed}, @code{Tag_ABI_align8_preserved},
558 @code{Tag_ABI_enum_size}, @code{Tag_ABI_HardFP_use},
559 @code{Tag_ABI_VFP_args}, @code{Tag_ABI_WMMX_args},
560 @code{Tag_ABI_optimization_goals}, @code{Tag_ABI_FP_optimization_goals},
561 @code{Tag_compatibility}, @code{Tag_CPU_unaligned_access},
562 @code{Tag_VFP_HP_extension}, @code{Tag_ABI_FP_16bit_format},
563 @code{Tag_nodefaults}, @code{Tag_also_compatible_with},
564 @code{Tag_conformance}, @code{Tag_T2EE_use},
565 @code{Tag_Virtualization_use}, @code{Tag_MPextension_use}
567 The @var{value} is either a @code{number}, @code{"string"}, or
568 @code{number, "string"} depending on the tag.
570 @cindex @code{.even} directive, ARM
572 This directive aligns to an even-numbered address.
574 @cindex @code{.extend} directive, ARM
575 @cindex @code{.ldouble} directive, ARM
576 @item .extend @var{expression} [, @var{expression}]*
577 @itemx .ldouble @var{expression} [, @var{expression}]*
578 These directives write 12byte long double floating-point values to the
579 output section. These are not compatible with current ARM processors
582 @c FFFFFFFFFFFFFFFFFFFFFFFFFF
585 @cindex @code{.fnend} directive, ARM
587 Marks the end of a function with an unwind table entry. The unwind index
588 table entry is created when this directive is processed.
590 If no personality routine has been specified then standard personality
591 routine 0 or 1 will be used, depending on the number of unwind opcodes
595 @cindex @code{.fnstart} directive, ARM
597 Marks the start of a function with an unwind table entry.
599 @cindex @code{.force_thumb} directive, ARM
601 This directive forces the selection of Thumb instructions, even if the
602 target processor does not support those instructions
604 @cindex @code{.fpu} directive, ARM
605 @item .fpu @var{name}
606 Select the floating-point unit to assemble for. Valid values for @var{name}
607 are the same as for the @option{-mfpu} commandline option.
609 @c GGGGGGGGGGGGGGGGGGGGGGGGGG
610 @c HHHHHHHHHHHHHHHHHHHHHHHHHH
612 @cindex @code{.handlerdata} directive, ARM
614 Marks the end of the current function, and the start of the exception table
615 entry for that function. Anything between this directive and the
616 @code{.fnend} directive will be added to the exception table entry.
618 Must be preceded by a @code{.personality} or @code{.personalityindex}
621 @c IIIIIIIIIIIIIIIIIIIIIIIIII
623 @cindex @code{.inst} directive, ARM
624 @item .inst @var{opcode} [ , @dots{} ]
625 @item .inst.n @var{opcode} [ , @dots{} ]
626 @item .inst.w @var{opcode} [ , @dots{} ]
627 Generates the instruction corresponding to the numerical value @var{opcode}.
628 @code{.inst.n} and @code{.inst.w} allow the Thumb instruction size to be
629 specified explicitly, overriding the normal encoding rules.
631 @c JJJJJJJJJJJJJJJJJJJJJJJJJJ
632 @c KKKKKKKKKKKKKKKKKKKKKKKKKK
633 @c LLLLLLLLLLLLLLLLLLLLLLLLLL
635 @item .ldouble @var{expression} [, @var{expression}]*
638 @cindex @code{.ltorg} directive, ARM
640 This directive causes the current contents of the literal pool to be
641 dumped into the current section (which is assumed to be the .text
642 section) at the current location (aligned to a word boundary).
643 @code{GAS} maintains a separate literal pool for each section and each
644 sub-section. The @code{.ltorg} directive will only affect the literal
645 pool of the current section and sub-section. At the end of assembly
646 all remaining, un-empty literal pools will automatically be dumped.
648 Note - older versions of @code{GAS} would dump the current literal
649 pool any time a section change occurred. This is no longer done, since
650 it prevents accurate control of the placement of literal pools.
652 @c MMMMMMMMMMMMMMMMMMMMMMMMMM
654 @cindex @code{.movsp} directive, ARM
655 @item .movsp @var{reg} [, #@var{offset}]
656 Tell the unwinder that @var{reg} contains an offset from the current
657 stack pointer. If @var{offset} is not specified then it is assumed to be
660 @c NNNNNNNNNNNNNNNNNNNNNNNNNN
661 @c OOOOOOOOOOOOOOOOOOOOOOOOOO
663 @cindex @code{.object_arch} directive, ARM
664 @item .object_arch @var{name}
665 Override the architecture recorded in the EABI object attribute section.
666 Valid values for @var{name} are the same as for the @code{.arch} directive.
667 Typically this is useful when code uses runtime detection of CPU features.
669 @c PPPPPPPPPPPPPPPPPPPPPPPPPP
671 @cindex @code{.packed} directive, ARM
672 @item .packed @var{expression} [, @var{expression}]*
673 This directive writes 12-byte packed floating-point values to the
674 output section. These are not compatible with current ARM processors
677 @cindex @code{.pad} directive, ARM
678 @item .pad #@var{count}
679 Generate unwinder annotations for a stack adjustment of @var{count} bytes.
680 A positive value indicates the function prologue allocated stack space by
681 decrementing the stack pointer.
683 @cindex @code{.personality} directive, ARM
684 @item .personality @var{name}
685 Sets the personality routine for the current function to @var{name}.
687 @cindex @code{.personalityindex} directive, ARM
688 @item .personalityindex @var{index}
689 Sets the personality routine for the current function to the EABI standard
690 routine number @var{index}
692 @cindex @code{.pool} directive, ARM
694 This is a synonym for .ltorg.
696 @c QQQQQQQQQQQQQQQQQQQQQQQQQQ
697 @c RRRRRRRRRRRRRRRRRRRRRRRRRR
699 @cindex @code{.req} directive, ARM
700 @item @var{name} .req @var{register name}
701 This creates an alias for @var{register name} called @var{name}. For
708 @c SSSSSSSSSSSSSSSSSSSSSSSSSS
711 @cindex @code{.save} directive, ARM
712 @item .save @var{reglist}
713 Generate unwinder annotations to restore the registers in @var{reglist}.
714 The format of @var{reglist} is the same as the corresponding store-multiple
718 @exdent @emph{core registers}
719 .save @{r4, r5, r6, lr@}
720 stmfd sp!, @{r4, r5, r6, lr@}
721 @exdent @emph{FPA registers}
724 @exdent @emph{VFP registers}
725 .save @{d8, d9, d10@}
726 fstmdx sp!, @{d8, d9, d10@}
727 @exdent @emph{iWMMXt registers}
729 wstrd wr11, [sp, #-8]!
730 wstrd wr10, [sp, #-8]!
733 wstrd wr11, [sp, #-8]!
735 wstrd wr10, [sp, #-8]!
739 @cindex @code{.setfp} directive, ARM
740 @item .setfp @var{fpreg}, @var{spreg} [, #@var{offset}]
741 Make all unwinder annotations relative to a frame pointer. Without this
742 the unwinder will use offsets from the stack pointer.
744 The syntax of this directive is the same as the @code{sub} or @code{mov}
745 instruction used to set the frame pointer. @var{spreg} must be either
746 @code{sp} or mentioned in a previous @code{.movsp} directive.
756 @cindex @code{.secrel32} directive, ARM
757 @item .secrel32 @var{expression} [, @var{expression}]*
758 This directive emits relocations that evaluate to the section-relative
759 offset of each expression's symbol. This directive is only supported
762 @cindex @code{.syntax} directive, ARM
763 @item .syntax [@code{unified} | @code{divided}]
764 This directive sets the Instruction Set Syntax as described in the
765 @ref{ARM-Instruction-Set} section.
767 @c TTTTTTTTTTTTTTTTTTTTTTTTTT
769 @cindex @code{.thumb} directive, ARM
771 This performs the same action as @var{.code 16}.
773 @cindex @code{.thumb_func} directive, ARM
775 This directive specifies that the following symbol is the name of a
776 Thumb encoded function. This information is necessary in order to allow
777 the assembler and linker to generate correct code for interworking
778 between Arm and Thumb instructions and should be used even if
779 interworking is not going to be performed. The presence of this
780 directive also implies @code{.thumb}
782 This directive is not neccessary when generating EABI objects. On these
783 targets the encoding is implicit when generating Thumb code.
785 @cindex @code{.thumb_set} directive, ARM
787 This performs the equivalent of a @code{.set} directive in that it
788 creates a symbol which is an alias for another symbol (possibly not yet
789 defined). This directive also has the added property in that it marks
790 the aliased symbol as being a thumb function entry point, in the same
791 way that the @code{.thumb_func} directive does.
793 @c UUUUUUUUUUUUUUUUUUUUUUUUUU
795 @cindex @code{.unreq} directive, ARM
796 @item .unreq @var{alias-name}
797 This undefines a register alias which was previously defined using the
798 @code{req}, @code{dn} or @code{qn} directives. For example:
805 An error occurs if the name is undefined. Note - this pseudo op can
806 be used to delete builtin in register name aliases (eg 'r0'). This
807 should only be done if it is really necessary.
809 @cindex @code{.unwind_raw} directive, ARM
810 @item .unwind_raw @var{offset}, @var{byte1}, @dots{}
811 Insert one of more arbitary unwind opcode bytes, which are known to adjust
812 the stack pointer by @var{offset} bytes.
814 For example @code{.unwind_raw 4, 0xb1, 0x01} is equivalent to
817 @c VVVVVVVVVVVVVVVVVVVVVVVVVV
819 @cindex @code{.vsave} directive, ARM
820 @item .vsave @var{vfp-reglist}
821 Generate unwinder annotations to restore the VFP registers in @var{vfp-reglist}
822 using FLDMD. Also works for VFPv3 registers
823 that are to be restored using VLDM.
824 The format of @var{vfp-reglist} is the same as the corresponding store-multiple
828 @exdent @emph{VFP registers}
829 .vsave @{d8, d9, d10@}
830 fstmdd sp!, @{d8, d9, d10@}
831 @exdent @emph{VFPv3 registers}
832 .vsave @{d15, d16, d17@}
833 vstm sp!, @{d15, d16, d17@}
836 Since FLDMX and FSTMX are now deprecated, this directive should be
837 used in favour of @code{.save} for saving VFP registers for ARMv6 and above.
839 @c WWWWWWWWWWWWWWWWWWWWWWWWWW
840 @c XXXXXXXXXXXXXXXXXXXXXXXXXX
841 @c YYYYYYYYYYYYYYYYYYYYYYYYYY
842 @c ZZZZZZZZZZZZZZZZZZZZZZZZZZ
850 @cindex opcodes for ARM
851 @code{@value{AS}} implements all the standard ARM opcodes. It also
852 implements several pseudo opcodes, including several synthetic load
857 @cindex @code{NOP} pseudo op, ARM
863 This pseudo op will always evaluate to a legal ARM instruction that does
864 nothing. Currently it will evaluate to MOV r0, r0.
866 @cindex @code{LDR reg,=<label>} pseudo op, ARM
869 ldr <register> , = <expression>
872 If expression evaluates to a numeric constant then a MOV or MVN
873 instruction will be used in place of the LDR instruction, if the
874 constant can be generated by either of these instructions. Otherwise
875 the constant will be placed into the nearest literal pool (if it not
876 already there) and a PC relative LDR instruction will be generated.
878 @cindex @code{ADR reg,<label>} pseudo op, ARM
881 adr <register> <label>
884 This instruction will load the address of @var{label} into the indicated
885 register. The instruction will evaluate to a PC relative ADD or SUB
886 instruction depending upon where the label is located. If the label is
887 out of range, or if it is not defined in the same file (and section) as
888 the ADR instruction, then an error will be generated. This instruction
889 will not make use of the literal pool.
891 @cindex @code{ADRL reg,<label>} pseudo op, ARM
894 adrl <register> <label>
897 This instruction will load the address of @var{label} into the indicated
898 register. The instruction will evaluate to one or two PC relative ADD
899 or SUB instructions depending upon where the label is located. If a
900 second instruction is not needed a NOP instruction will be generated in
901 its place, so that this instruction is always 8 bytes long.
903 If the label is out of range, or if it is not defined in the same file
904 (and section) as the ADRL instruction, then an error will be generated.
905 This instruction will not make use of the literal pool.
909 For information on the ARM or Thumb instruction sets, see @cite{ARM
910 Software Development Toolkit Reference Manual}, Advanced RISC Machines
913 @node ARM Mapping Symbols
914 @section Mapping Symbols
916 The ARM ELF specification requires that special symbols be inserted
917 into object files to mark certain features:
923 At the start of a region of code containing ARM instructions.
927 At the start of a region of code containing THUMB instructions.
931 At the start of a region of data.
935 The assembler will automatically insert these symbols for you - there
936 is no need to code them yourself. Support for tagging symbols ($b,
937 $f, $p and $m) which is also mentioned in the current ARM ELF
938 specification is not implemented. This is because they have been
939 dropped from the new EABI and so tools cannot rely upon their
942 @node ARM Unwinding Tutorial
945 The ABI for the ARM Architecture specifies a standard format for
946 exception unwind information. This information is used when an
947 exception is thrown to determine where control should be transferred.
948 In particular, the unwind information is used to determine which
949 function called the function that threw the exception, and which
950 function called that one, and so forth. This information is also used
951 to restore the values of callee-saved registers in the function
952 catching the exception.
954 If you are writing functions in assembly code, and those functions
955 call other functions that throw exceptions, you must use assembly
956 pseudo ops to ensure that appropriate exception unwind information is
957 generated. Otherwise, if one of the functions called by your assembly
958 code throws an exception, the run-time library will be unable to
959 unwind the stack through your assembly code and your program will not
962 To illustrate the use of these pseudo ops, we will examine the code
963 that G++ generates for the following C++ input:
977 This example does not show how to throw or catch an exception from
978 assembly code. That is a much more complex operation and should
979 always be done in a high-level language, such as C++, that directly
982 The code generated by one particular version of G++ when compiling the
989 @ Function supports interworking.
990 @ args = 0, pretend = 0, frame = 8
991 @ frame_needed = 1, uses_anonymous_args = 0
1013 Of course, the sequence of instructions varies based on the options
1014 you pass to GCC and on the version of GCC in use. The exact
1015 instructions are not important since we are focusing on the pseudo ops
1016 that are used to generate unwind information.
1018 An important assumption made by the unwinder is that the stack frame
1019 does not change during the body of the function. In particular, since
1020 we assume that the assembly code does not itself throw an exception,
1021 the only point where an exception can be thrown is from a call, such
1022 as the @code{bl} instruction above. At each call site, the same saved
1023 registers (including @code{lr}, which indicates the return address)
1024 must be located in the same locations relative to the frame pointer.
1026 The @code{.fnstart} (@pxref{arm_fnstart,,.fnstart pseudo op}) pseudo
1027 op appears immediately before the first instruction of the function
1028 while the @code{.fnend} (@pxref{arm_fnend,,.fnend pseudo op}) pseudo
1029 op appears immediately after the last instruction of the function.
1030 These pseudo ops specify the range of the function.
1032 Only the order of the other pseudos ops (e.g., @code{.setfp} or
1033 @code{.pad}) matters; their exact locations are irrelevant. In the
1034 example above, the compiler emits the pseudo ops with particular
1035 instructions. That makes it easier to understand the code, but it is
1036 not required for correctness. It would work just as well to emit all
1037 of the pseudo ops other than @code{.fnend} in the same order, but
1038 immediately after @code{.fnstart}.
1040 The @code{.save} (@pxref{arm_save,,.save pseudo op}) pseudo op
1041 indicates registers that have been saved to the stack so that they can
1042 be restored before the function returns. The argument to the
1043 @code{.save} pseudo op is a list of registers to save. If a register
1044 is ``callee-saved'' (as specified by the ABI) and is modified by the
1045 function you are writing, then your code must save the value before it
1046 is modified and restore the original value before the function
1047 returns. If an exception is thrown, the run-time library restores the
1048 values of these registers from their locations on the stack before
1049 returning control to the exception handler. (Of course, if an
1050 exception is not thrown, the function that contains the @code{.save}
1051 pseudo op restores these registers in the function epilogue, as is
1052 done with the @code{ldmfd} instruction above.)
1054 You do not have to save callee-saved registers at the very beginning
1055 of the function and you do not need to use the @code{.save} pseudo op
1056 immediately following the point at which the registers are saved.
1057 However, if you modify a callee-saved register, you must save it on
1058 the stack before modifying it and before calling any functions which
1059 might throw an exception. And, you must use the @code{.save} pseudo
1060 op to indicate that you have done so.
1062 The @code{.pad} (@pxref{arm_pad,,.pad}) pseudo op indicates a
1063 modification of the stack pointer that does not save any registers.
1064 The argument is the number of bytes (in decimal) that are subtracted
1065 from the stack pointer. (On ARM CPUs, the stack grows downwards, so
1066 subtracting from the stack pointer increases the size of the stack.)
1068 The @code{.setfp} (@pxref{arm_setfp,,.setfp pseudo op}) pseudo op
1069 indicates the register that contains the frame pointer. The first
1070 argument is the register that is set, which is typically @code{fp}.
1071 The second argument indicates the register from which the frame
1072 pointer takes its value. The third argument, if present, is the value
1073 (in decimal) added to the register specified by the second argument to
1074 compute the value of the frame pointer. You should not modify the
1075 frame pointer in the body of the function.
1077 If you do not use a frame pointer, then you should not use the
1078 @code{.setfp} pseudo op. If you do not use a frame pointer, then you
1079 should avoid modifying the stack pointer outside of the function
1080 prologue. Otherwise, the run-time library will be unable to find
1081 saved registers when it is unwinding the stack.
1083 The pseudo ops described above are sufficient for writing assembly
1084 code that calls functions which may throw exceptions. If you need to
1085 know more about the object-file format used to represent unwind
1086 information, you may consult the @cite{Exception Handling ABI for the
1087 ARM Architecture} available from @uref{http://infocenter.arm.com}.