ld/testsuite/ld-spu/icache1.d

   1 #source: icache1.s
   2 #ld: --soft-icache --num-lines=4 --non-ia-text --auto-overlay=tmpdir/icache1.lnk --auto-relink
   3 #objdump: -D
   4
   5 .* elf32-spu
   6
   7
   8 Disassembly of section .ovl.init:
   9 00000000 <__icache_fileoff>:
  10 .*      00 00 00 00.*
  11 .*      00 00 02 00.*
  12         \.\.\.
  13
  14 Disassembly of section \.ovly1:
  15
  16 00000000 <\.ovly1>:
  17 .*      ai      \$1,\$1,64      # 40
  18 .*      lqd     \$0,16\(\$1\)
  19 .*      bi      \$0
  20         \.\.\.
  21
  22 Disassembly of section \.ovly2:
  23
  24 00000400 <f1>:
  25 .*      40 20 00 00     nop     \$0
  26 .*      24 00 40 80     stqd    \$0,16\(\$1\)
  27 .*      1c f0 00 81     ai      \$1,\$1,-64
  28 .*      24 00 00 81     stqd    \$1,0\(\$1\)
  29 .*      33 00 78 80     brsl    \$0,7d4 .*
  30 .*      33 00 7a 00     brsl    \$0,7e4 .*
  31         \.\.\.
  32 .*      32 00 17 80     br      7f4 .*
  33         \.\.\.
  34  7d0:   00 04 09 04.*
  35  7d4:   31 02 01 cb     brasl   \$75,100c <__icache_br_handler>
  36  7d8:   a0 00 04 10.*
  37  7dc:   00 00 e6 00.*
  38  7e0:   00 04 08 00.*
  39  7e4:   31 02 01 cb     brasl   \$75,100c <__icache_br_handler>
  40  7e8:   a0 00 04 14.*
  41  7ec:   00 00 07 80.*
  42  7f0:   00 04 00 00.*
  43  7f4:   31 02 01 cb     brasl   \$75,100c <__icache_br_handler>
  44  7f8:   20 00 07 38.*
  45  7fc:   00 7f 0e 80.*
  46
  47 Disassembly of section \.ovly3:
  48
  49 00000800 <f3>:
  50         \.\.\.
  51 .*      35 00 00 00     bi      \$0
  52
  53 00000904 <f2>:
  54 .*      1c e0 00 81     ai      \$1,\$1,-128
  55 .*      24 00 00 81     stqd    \$1,0\(\$1\)
  56         \.\.\.
  57 .*      1c 20 00 81     ai      \$1,\$1,128     # 80
  58 .*      35 00 00 00     bi      \$0
  59         \.\.\.
  60
  61 Disassembly of section \.ovly4:
  62
  63 00000c00 <f5>:
  64 .*      24 00 40 80     stqd    \$0,16\(\$1\)
  65 .*      24 f8 00 81     stqd    \$1,-512\(\$1\)
  66 .*      1c 80 00 81     ai      \$1,\$1,-512
  67 .*      33 7f fe 80     brsl    \$0,c00 <f5>    # c00
  68         \.\.\.
  69 .*      42 01 00 03     ila     \$3,200.*
  70 .*      18 00 c0 81     a       \$1,\$1,\$3
  71 .*      34 00 40 80     lqd     \$0,16\(\$1\)
  72 .*      35 00 00 00     bi      \$0
  73         \.\.\.
  74
  75 Disassembly of section \.ovly5:
  76
  77 00000000 <\.ovly5>:
  78         \.\.\.
  79 .*      42 01 00 03     ila     \$3,200 .*
  80 .*      18 00 c0 81     a       \$1,\$1,\$3
  81 .*      34 00 40 80     lqd     \$0,16\(\$1\)
  82 .*      30 00 7e 80     bra     3f4 .*
  83         \.\.\.
  84  3f0:   00 04 0c 00.*
  85  3f4:   31 02 01 cb     brasl   \$75,100c <__icache_br_handler>
  86  3f8:   a0 00 03 2c.*
  87  3fc:   00 01 fe 80.*
  88
  89 Disassembly of section \.ovly6:
  90
  91 00000400 <\.ovly6>:
  92 .*      31 00 fa 80     brasl   \$0,7d4 .*
  93 .*      33 00 7c 00     brsl    \$0,7e4 .*
  94         \.\.\.
  95 .*      32 00 19 80     br      7f4 .*
  96         \.\.\.
  97  7d0:   00 08 0c 00.*
  98  7d4:   31 02 01 cb     brasl   \$75,100c <__icache_br_handler>
  99  7d8:   a0 00 04 00.*
 100  7dc:   00 01 7a 80.*
 101  7e0:   00 08 0c 00.*
 102  7e4:   31 02 01 cb     brasl   \$75,100c <__icache_br_handler>
 103  7e8:   a0 00 04 04.*
 104  7ec:   00 00 83 80.*
 105  7f0:   00 08 00 00.*
 106  7f4:   31 02 01 cb     brasl   \$75,100c <__icache_br_handler>
 107  7f8:   20 00 07 28.*
 108  7fc:   00 7f 02 80.*
 109
 110 Disassembly of section \.ovly7:
 111
 112 00000800 <\.ovly7>:
 113 .*      41 7f ff 83     ilhu    \$3,65535       # ffff
 114 .*      60 f8 30 03     iohl    \$3,61536       # f060
 115 .*      18 00 c0 84     a       \$4,\$1,\$3
 116 .*      00 20 00 00     lnop
 117 .*      04 00 02 01     ori     \$1,\$4,0
 118 .*      24 00 02 04     stqd    \$4,0\(\$4\)
 119 .*      33 00 77 80     brsl    \$0,bd4 .*
 120 .*      33 00 79 00     brsl    \$0,be4 .*
 121 .*      34 00 00 81     lqd     \$1,0\(\$1\)
 122         \.\.\.
 123 .*      32 00 16 00     br      bf4 .*
 124         \.\.\.
 125  bd0:   00 04 0c 00.*
 126  bd4:   31 02 01 cb     brasl   \$75,100c <__icache_br_handler>
 127  bd8:   a0 00 08 18.*
 128  bdc:   00 00 0a 80.*
 129  be0:   00 08 0c 00.*
 130  be4:   31 02 01 cb     brasl   \$75,100c <__icache_br_handler>
 131  be8:   a0 00 08 1c.*
 132  bec:   00 00 05 80.*
 133  bf0:   00 08 04 00.*
 134  bf4:   31 02 01 cb     brasl   \$75,100c <__icache_br_handler>
 135  bf8:   20 00 0b 44.*
 136  bfc:   00 7f 01 80.*
 137
 138 Disassembly of section \.ovly8:
 139
 140 00000c00 <f4>:
 141 .*      24 00 40 80     stqd    \$0,16\(\$1\)
 142 .*      24 f8 00 81     stqd    \$1,-512\(\$1\)
 143 .*      1c 80 00 81     ai      \$1,\$1,-512
 144 .*      31 01 fc 80     brasl   \$0,fe4 .*
 145         \.\.\.
 146 .*      32 00 18 80     br      ff4 .*
 147         \.\.\.
 148      fe0:       00 04 09 04.*
 149      fe4:       31 02 01 cb     brasl   \$75,100c <__icache_br_handler>
 150      fe8:       a0 00 0c 0c.*
 151      fec:       00 00 dc 00.*
 152      ff0:       00 08 08 00.*
 153      ff4:       31 02 01 cb     brasl   \$75,100c <__icache_br_handler>
 154      ff8:       20 00 0f 30.*
 155      ffc:       00 7f 02 80.*
 156
 157 Disassembly of section \.text:
 158
 159 00001000 <_start>:
 160 .*      41 00 02 03     ilhu    \$3,4
 161 .*      60 86 00 03     iohl    \$3,3072        # c00
 162 .*      32 00 03 80     br      1024.*
 163 0000100c <__icache_br_handler>:
 164     100c:       00 00 00 00     stop
 165 00001010 <__icache_call_handler>:
 166         \.\.\.
 167     1020:       00 04 04 00.*
 168     1024:       31 02 02 4b     brasl   \$75,1010 <__icache_call_handler>
 169     1028:       a0 00 10 08.*
 170     102c:       00 7e 7c 80.*
 171
 172 #pass