2 @c Free Software Foundation, Inc.
3 @c This is part of the GAS manual.
4 @c For copying conditions, see the file as.texinfo.
9 @chapter AVR Dependent Features
13 @node Machine Dependencies
14 @chapter AVR Dependent Features
19 * AVR Options:: Options
21 * AVR Opcodes:: Opcodes
26 @cindex AVR options (none)
27 @cindex options for AVR (none)
31 @cindex @code{-mmcu=} command line option, AVR
33 Specify ATMEL AVR instruction set or MCU type.
35 Instruction set avr1 is for the minimal AVR core, not supported by the C
36 compiler, only for assembler programs (MCU types: at90s1200, attiny10,
37 attiny11, attiny12, attiny15, attiny28).
39 Instruction set avr2 (default) is for the classic AVR core with up to
40 8K program memory space (MCU types: at90s2313, at90s2323, attiny22,
41 attiny26, at90s2333, at90s2343, at90s4414, at90s4433, at90s4434,
42 at90s8515, at90c8534, at90s8535, at86rf401, attiny13, attiny2313,
43 attiny261, attiny461, attiny861, attiny24, attiny44, attiny84, attiny25,
46 Instruction set avr3 is for the classic AVR core with up to 128K program
47 memory space (MCU types: atmega103, atmega603, at43usb320, at43usb355,
50 Instruction set avr4 is for the enhanced AVR core with up to 8K program
51 memory space (MCU types: atmega48, atmega8, atmega83, atmega85, atmega88,
52 atmega8515, atmega8535, atmega8hva, at90pwm1, at90pwm2, at90pwm3).
54 Instruction set avr5 is for the enhanced AVR core with up to 128K program
55 memory space (MCU types: atmega16, atmega161, atmega162, atmega163,
56 atmega164p, atmega165, atmega165p, atmega168, atmega169, atmega169p,
57 atmega32, atmega323, atmega324p, atmega325, atmega325p, atmega329,
58 atmega329p, atmega3250, atmega3250p, atmega3290, atmega3290p, atmega406,
59 atmega64, atmega640, atmega644, atmega644p, atmega128, atmega1280,
60 atmega1281, atmega645, atmega649, atmega6450, atmega6490, atmega16hva,
61 at90can32, at90can64, at90can128, at90usb82, at90usb162, at90usb646,
62 at90usb647, at90usb1286, at90usb1287, at94k).
64 Instruction set avr6 is for the enhanced AVR core with 256K program
65 memory space (MCU types: atmega2560, atmega2561).
67 @cindex @code{-mall-opcodes} command line option, AVR
69 Accept all AVR opcodes, even if not supported by @code{-mmcu}.
71 @cindex @code{-mno-skip-bug} command line option, AVR
73 This option disable warnings for skipping two-word instructions.
75 @cindex @code{-mno-wrap} command line option, AVR
77 This option reject @code{rjmp/rcall} instructions with 8K wrap-around.
85 * AVR-Chars:: Special Characters
86 * AVR-Regs:: Register Names
87 * AVR-Modifiers:: Relocatable Expression Modifiers
91 @subsection Special Characters
93 @cindex line comment character, AVR
94 @cindex AVR line comment character
96 The presence of a @samp{;} on a line indicates the start of a comment
97 that extends to the end of the current line. If a @samp{#} appears as
98 the first character of a line, the whole line is treated as a comment.
100 @cindex line separator, AVR
101 @cindex statement separator, AVR
102 @cindex AVR line separator
104 The @samp{$} character can be used instead of a newline to separate
108 @subsection Register Names
110 @cindex AVR register names
111 @cindex register names, AVR
113 The AVR has 32 x 8-bit general purpose working registers @samp{r0},
114 @samp{r1}, ... @samp{r31}.
115 Six of the 32 registers can be used as three 16-bit indirect address
116 register pointers for Data Space addressing. One of the these address
117 pointers can also be used as an address pointer for look up tables in
118 Flash program memory. These added function registers are the 16-bit
119 @samp{X}, @samp{Y} and @samp{Z} - registers.
128 @subsection Relocatable Expression Modifiers
130 @cindex AVR modifiers
133 The assembler supports several modifiers when using relocatable addresses
134 in AVR instruction operands. The general syntax is the following:
137 modifier(relocatable-expression)
141 @cindex symbol modifiers
145 This modifier allows you to use bits 0 through 7 of
146 an address expression as 8 bit relocatable expression.
150 This modifier allows you to use bits 7 through 15 of an address expression
151 as 8 bit relocatable expression. This is useful with, for example, the
152 AVR @samp{ldi} instruction and @samp{lo8} modifier.
163 This modifier allows you to use bits 16 through 23 of
164 an address expression as 8 bit relocatable expression.
165 Also, can be useful for loading 32 bit constants.
169 Synonym of @samp{hh8}.
173 This modifier allows you to use bits 24 through 31 of
174 an expression as 8 bit expression. This is useful with, for example, the
175 AVR @samp{ldi} instruction and @samp{lo8}, @samp{hi8}, @samp{hlo8},
176 @samp{hhi8}, modifier.
181 ldi r26, lo8(285774925)
182 ldi r27, hi8(285774925)
183 ldi r28, hlo8(285774925)
184 ldi r29, hhi8(285774925)
185 ; r29,r28,r27,r26 = 285774925
190 This modifier allows you to use bits 0 through 7 of
191 an address expression as 8 bit relocatable expression.
192 This modifier useful for addressing data or code from
193 Flash/Program memory. The using of @samp{pm_lo8} similar
198 This modifier allows you to use bits 8 through 15 of
199 an address expression as 8 bit relocatable expression.
200 This modifier useful for addressing data or code from
201 Flash/Program memory.
205 This modifier allows you to use bits 15 through 23 of
206 an address expression as 8 bit relocatable expression.
207 This modifier useful for addressing data or code from
208 Flash/Program memory.
215 @cindex AVR opcode summary
216 @cindex opcode summary, AVR
217 @cindex mnemonics, AVR
218 @cindex instruction summary, AVR
219 For detailed information on the AVR machine instruction set, see
220 @url{www.atmel.com/products/AVR}.
222 @code{@value{AS}} implements all the standard AVR opcodes.
223 The following table summarizes the AVR opcodes, and their arguments.
228 d @r{`ldi' register (r16-r31)}
229 v @r{`movw' even register (r0, r2, ..., r28, r30)}
230 a @r{`fmul' register (r16-r23)}
231 w @r{`adiw' register (r24,r26,r28,r30)}
232 e @r{pointer registers (X,Y,Z)}
233 b @r{base pointer register and displacement ([YZ]+disp)}
234 z @r{Z pointer register (for [e]lpm Rd,Z[+])}
235 M @r{immediate value from 0 to 255}
236 n @r{immediate value from 0 to 255 ( n = ~M ). Relocation impossible}
237 s @r{immediate value from 0 to 7}
238 P @r{Port address value from 0 to 63. (in, out)}
239 p @r{Port address value from 0 to 31. (cbi, sbi, sbic, sbis)}
240 K @r{immediate value from 0 to 63 (used in `adiw', `sbiw')}
241 i @r{immediate value}
242 l @r{signed pc relative offset from -64 to 63}
243 L @r{signed pc relative offset from -2048 to 2047}
244 h @r{absolute code address (call, jmp)}
245 S @r{immediate value from 0 to 7 (S = s << 4)}
246 ? @r{use this opcode entry if no parameters, else use next opcode entry}
264 100101001SSS1000 bclr S
265 100101000SSS1000 bset S
266 1001010100001001 icall
267 1001010000001001 ijmp
268 1001010111001000 lpm ?
269 1001000ddddd010+ lpm r,z
270 1001010111011000 elpm ?
271 1001000ddddd011+ elpm r,z
274 1001010100011000 reti
275 1001010110001000 sleep
276 1001010110011000 break
279 000111rdddddrrrr adc r,r
280 000011rdddddrrrr add r,r
281 001000rdddddrrrr and r,r
282 000101rdddddrrrr cp r,r
283 000001rdddddrrrr cpc r,r
284 000100rdddddrrrr cpse r,r
285 001001rdddddrrrr eor r,r
286 001011rdddddrrrr mov r,r
287 100111rdddddrrrr mul r,r
288 001010rdddddrrrr or r,r
289 000010rdddddrrrr sbc r,r
290 000110rdddddrrrr sub r,r
291 001001rdddddrrrr clr r
292 000011rdddddrrrr lsl r
293 000111rdddddrrrr rol r
294 001000rdddddrrrr tst r
295 0111KKKKddddKKKK andi d,M
296 0111KKKKddddKKKK cbr d,n
297 1110KKKKddddKKKK ldi d,M
298 11101111dddd1111 ser d
299 0110KKKKddddKKKK ori d,M
300 0110KKKKddddKKKK sbr d,M
301 0011KKKKddddKKKK cpi d,M
302 0100KKKKddddKKKK sbci d,M
303 0101KKKKddddKKKK subi d,M
304 1111110rrrrr0sss sbrc r,s
305 1111111rrrrr0sss sbrs r,s
306 1111100ddddd0sss bld r,s
307 1111101ddddd0sss bst r,s
308 10110PPdddddPPPP in r,P
309 10111PPrrrrrPPPP out P,r
310 10010110KKddKKKK adiw w,K
311 10010111KKddKKKK sbiw w,K
312 10011000pppppsss cbi p,s
313 10011010pppppsss sbi p,s
314 10011001pppppsss sbic p,s
315 10011011pppppsss sbis p,s
316 111101lllllll000 brcc l
317 111100lllllll000 brcs l
318 111100lllllll001 breq l
319 111101lllllll100 brge l
320 111101lllllll101 brhc l
321 111100lllllll101 brhs l
322 111101lllllll111 brid l
323 111100lllllll111 brie l
324 111100lllllll000 brlo l
325 111100lllllll100 brlt l
326 111100lllllll010 brmi l
327 111101lllllll001 brne l
328 111101lllllll010 brpl l
329 111101lllllll000 brsh l
330 111101lllllll110 brtc l
331 111100lllllll110 brts l
332 111101lllllll011 brvc l
333 111100lllllll011 brvs l
334 111101lllllllsss brbc s,l
335 111100lllllllsss brbs s,l
336 1101LLLLLLLLLLLL rcall L
337 1100LLLLLLLLLLLL rjmp L
338 1001010hhhhh111h call h
339 1001010hhhhh110h jmp h
340 1001010rrrrr0101 asr r
341 1001010rrrrr0000 com r
342 1001010rrrrr1010 dec r
343 1001010rrrrr0011 inc r
344 1001010rrrrr0110 lsr r
345 1001010rrrrr0001 neg r
346 1001000rrrrr1111 pop r
347 1001001rrrrr1111 push r
348 1001010rrrrr0111 ror r
349 1001010rrrrr0010 swap r
350 00000001ddddrrrr movw v,v
351 00000010ddddrrrr muls d,d
352 000000110ddd0rrr mulsu a,a
353 000000110ddd1rrr fmul a,a
354 000000111ddd0rrr fmuls a,a
355 000000111ddd1rrr fmulsu a,a
356 1001001ddddd0000 sts i,r
357 1001000ddddd0000 lds r,i
358 10o0oo0dddddbooo ldd r,b
359 100!000dddddee-+ ld r,e
360 10o0oo1rrrrrbooo std b,r
361 100!001rrrrree-+ st e,r
362 1001010100011001 eicall
363 1001010000011001 eijmp