| blob | 0ddd0cf13ad1a06d8940f8337d612aa24c5373e7 |
1 /* 32-bit ELF support for ARM
2 Copyright 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007,
3 2008, 2009, 2010, 2011 Free Software Foundation, Inc.
5 This file is part of BFD, the Binary File Descriptor library.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
20 MA 02110-1301, USA. */
23 #include <limits.h>
32 /* Return the relocation section associated with NAME. HTAB is the
33 bfd's elf32_arm_link_hash_entry. */
34 #define RELOC_SECTION(HTAB, NAME) \
37 /* Return size of a relocation entry. HTAB is the bfd's
38 elf32_arm_link_hash_entry. */
39 #define RELOC_SIZE(HTAB) \
40 ((HTAB)->use_rel \
41 ? sizeof (Elf32_External_Rel) \
42 : sizeof (Elf32_External_Rela))
44 /* Return function to swap relocations in. HTAB is the bfd's
45 elf32_arm_link_hash_entry. */
46 #define SWAP_RELOC_IN(HTAB) \
47 ((HTAB)->use_rel \
48 ? bfd_elf32_swap_reloc_in \
49 : bfd_elf32_swap_reloca_in)
51 /* Return function to swap relocations out. HTAB is the bfd's
52 elf32_arm_link_hash_entry. */
53 #define SWAP_RELOC_OUT(HTAB) \
54 ((HTAB)->use_rel \
55 ? bfd_elf32_swap_reloc_out \
56 : bfd_elf32_swap_reloca_out)
58 #define elf_info_to_howto 0
59 #define elf_info_to_howto_rel elf32_arm_info_to_howto
61 #define ARM_ELF_ABI_VERSION 0
62 #define ARM_ELF_OS_ABI_VERSION ELFOSABI_ARM
69 /* Note: code such as elf32_arm_reloc_type_lookup expect to use e.g.
70 R_ARM_PC24 as an index into this, and find the R_ARM_PC24 HOWTO
71 in that slot. */
74 {
75 /* No relocation. */
104 /* 32 bit absolute */
119 /* standard 32bit pc-relative reloc */
134 /* 8 bit absolute - R_ARM_LDR_PC_G0 in AAELF */
149 /* 16 bit absolute */
164 /* 12 bit absolute */
193 /* 8 bit absolute */
292 /* BLX instruction for the ARM. */
307 /* BLX instruction for the Thumb. */
322 /* Dynamic TLS relocations. */
366 /* Relocs used in ARM Linux */
830 /* These are declared as 13-bit signed relocations because we can
831 address -4095 .. 4095(base) by altering ADDW to SUBW or vice
832 versa. */
889 /* Group relocations. */
1269 /* End of group relocations. */
1483 /* GNU extension to record C++ vtable member usage */
1498 /* GNU extension to record C++ vtable hierarchy */
1541 /* TLS relocations */
1654 /* 112-127 private relocations. */
1672 /* R_ARM_ME_TOO, obsolete. */
1688 };
1690 /* 160 onwards: */
1692 {
1706 };
1708 /* 249-255 extended, currently unused, relocations: */
1710 {
1766 };
1770 {
1782 }
1784 static void
1787 {
1792 }
1794 struct elf32_arm_reloc_map
1795 {
1796 bfd_reloc_code_real_type bfd_reloc_val;
1798 };
1800 /* All entries in this list must also be present in elf32_arm_howto_table. */
1802 {
1889 };
1893 bfd_reloc_code_real_type code)
1894 {
1902 }
1907 {
1926 }
1928 /* Support for core dump NOTE sections. */
1930 static bfd_boolean
1932 {
1937 {
1942 /* pr_cursig */
1945 /* pr_pid */
1948 /* pr_reg */
1953 }
1955 /* Make a ".reg/999" section. */
1958 }
1960 static bfd_boolean
1962 {
1964 {
1973 }
1975 /* Note that for some reason, a spurious space is tacked
1976 onto the end of the args in some (at least one anyway)
1977 implementations, so strip it off if it exists. */
1978 {
1984 }
1987 }
1989 #define TARGET_LITTLE_SYM bfd_elf32_littlearm_vec
1991 #define TARGET_BIG_SYM bfd_elf32_bigarm_vec
1994 #define elf_backend_grok_prstatus elf32_arm_nabi_grok_prstatus
1995 #define elf_backend_grok_psinfo elf32_arm_nabi_grok_psinfo
2000 /* In lieu of proper flags, assume all EABIv4 or later objects are
2001 interworkable. */
2002 #define INTERWORK_FLAG(abfd) \
2003 (EF_ARM_EABI_VERSION (elf_elfheader (abfd)->e_flags) >= EF_ARM_EABI_VER4 \
2004 || (elf_elfheader (abfd)->e_flags & EF_ARM_INTERWORK) \
2005 || ((abfd)->flags & BFD_LINKER_CREATED))
2007 /* The linker script knows the section names for placement.
2008 The entry_names are used to do simple name mangling on the stubs.
2009 Given a function name, and its type, the stub can be found. The
2010 name can be changed. The only requirement is the %s be present. */
2025 /* The name of the dynamic interpreter. This is put in the .interp
2026 section. */
2030 {
2034 };
2037 {
2045 + dl_tlsdesc_lazy_resolver(GOT) */
2047 };
2049 #ifdef FOUR_WORD_PLT
2051 /* The first entry in a procedure linkage table looks like
2052 this. It is set up so that any shared library function that is
2053 called before the relocation has been set up calls the dynamic
2054 linker first. */
2056 {
2061 };
2063 /* Subsequent entries in a procedure linkage table look like
2064 this. */
2066 {
2071 };
2073 #else
2075 /* The first entry in a procedure linkage table looks like
2076 this. It is set up so that any shared library function that is
2077 called before the relocation has been set up calls the dynamic
2078 linker first. */
2080 {
2086 };
2088 /* Subsequent entries in a procedure linkage table look like
2089 this. */
2091 {
2095 };
2097 #endif
2099 /* The format of the first entry in the procedure linkage table
2100 for a VxWorks executable. */
2102 {
2107 };
2109 /* The format of subsequent entries in a VxWorks executable. */
2111 {
2118 };
2120 /* The format of entries in a VxWorks shared library. */
2122 {
2129 };
2131 /* An initial stub used if the PLT entry is referenced from Thumb code. */
2132 #define PLT_THUMB_STUB_SIZE 4
2134 {
2137 };
2139 /* The entries in a PLT when using a DLL-based target with multiple
2140 address spaces. */
2142 {
2145 };
2147 #define ARM_MAX_FWD_BRANCH_OFFSET ((((1 << 23) - 1) << 2) + 8)
2148 #define ARM_MAX_BWD_BRANCH_OFFSET ((-((1 << 23) << 2)) + 8)
2149 #define THM_MAX_FWD_BRANCH_OFFSET ((1 << 22) -2 + 4)
2150 #define THM_MAX_BWD_BRANCH_OFFSET (-(1 << 22) + 4)
2151 #define THM2_MAX_FWD_BRANCH_OFFSET (((1 << 24) - 2) + 4)
2152 #define THM2_MAX_BWD_BRANCH_OFFSET (-(1 << 24) + 4)
2154 enum stub_insn_type
2155 {
2157 THUMB32_TYPE,
2158 ARM_TYPE,
2159 DATA_TYPE
2160 };
2162 #define THUMB16_INSN(X) {(X), THUMB16_TYPE, R_ARM_NONE, 0}
2163 /* A bit of a hack. A Thumb conditional branch, in which the proper condition
2164 is inserted in arm_build_one_stub(). */
2165 #define THUMB16_BCOND_INSN(X) {(X), THUMB16_TYPE, R_ARM_NONE, 1}
2166 #define THUMB32_INSN(X) {(X), THUMB32_TYPE, R_ARM_NONE, 0}
2167 #define THUMB32_B_INSN(X, Z) {(X), THUMB32_TYPE, R_ARM_THM_JUMP24, (Z)}
2168 #define ARM_INSN(X) {(X), ARM_TYPE, R_ARM_NONE, 0}
2169 #define ARM_REL_INSN(X, Z) {(X), ARM_TYPE, R_ARM_JUMP24, (Z)}
2170 #define DATA_WORD(X,Y,Z) {(X), DATA_TYPE, (Y), (Z)}
2173 {
2174 bfd_vma data;
2180 /* Arm/Thumb -> Arm/Thumb long branch stub. On V5T and above, use blx
2181 to reach the stub if necessary. */
2183 {
2186 };
2188 /* V4T Arm -> Thumb long branch stub. Used on V4T where blx is not
2189 available. */
2191 {
2195 };
2197 /* Thumb -> Thumb long branch stub. Used on M-profile architectures. */
2199 {
2207 };
2209 /* V4T Thumb -> Thumb long branch stub. Using the stack is not
2210 allowed. */
2212 {
2218 };
2220 /* V4T Thumb -> ARM long branch stub. Used on V4T where blx is not
2221 available. */
2223 {
2228 };
2230 /* V4T Thumb -> ARM short branch stub. Shorter variant of the above
2231 one, when the destination is close enough. */
2233 {
2237 };
2239 /* ARM/Thumb -> ARM long branch stub, PIC. On V5T and above, use
2240 blx to reach the stub if necessary. */
2242 {
2246 };
2248 /* ARM/Thumb -> Thumb long branch stub, PIC. On V5T and above, use
2249 blx to reach the stub if necessary. We can not add into pc;
2250 it is not guaranteed to mode switch (different in ARMv6 and
2251 ARMv7). */
2253 {
2258 };
2260 /* V4T ARM -> ARM long branch stub, PIC. */
2262 {
2267 };
2269 /* V4T Thumb -> ARM long branch stub, PIC. */
2271 {
2277 };
2279 /* Thumb -> Thumb long branch stub, PIC. Used on M-profile
2280 architectures. */
2282 {
2290 };
2292 /* V4T Thumb -> Thumb long branch stub, PIC. Using the stack is not
2293 allowed. */
2295 {
2302 };
2304 /* Thumb2/ARM -> TLS trampoline. Lowest common denominator, which is a
2305 long PIC stub. We can use r1 as a scratch -- and cannot use ip. */
2307 {
2311 };
2313 /* V4T Thumb -> TLS trampoline. lowest common denominator, which is a
2314 long PIC stub. We can use r1 as a scratch -- and cannot use ip. */
2316 {
2322 };
2324 /* Cortex-A8 erratum-workaround stubs. */
2326 /* Stub used for conditional branches (which may be beyond +/-1MB away, so we
2327 can't use a conditional branch to reach this stub). */
2330 {
2334 };
2336 /* Stub used for b.w and bl.w instructions. */
2339 {
2341 };
2344 {
2346 };
2348 /* Stub used for Thumb-2 blx.w instructions. We modified the original blx.w
2349 instruction (which switches to ARM mode) to point to this stub. Jump to the
2350 real destination using an ARM-mode branch. */
2353 {
2355 };
2357 /* Section name for stubs is the associated section name plus this
2358 string. */
2361 /* One entry per long/short branch stub defined above. */
2362 #define DEF_STUBS \
2363 DEF_STUB(long_branch_any_any) \
2364 DEF_STUB(long_branch_v4t_arm_thumb) \
2365 DEF_STUB(long_branch_thumb_only) \
2366 DEF_STUB(long_branch_v4t_thumb_thumb) \
2367 DEF_STUB(long_branch_v4t_thumb_arm) \
2368 DEF_STUB(short_branch_v4t_thumb_arm) \
2369 DEF_STUB(long_branch_any_arm_pic) \
2370 DEF_STUB(long_branch_any_thumb_pic) \
2371 DEF_STUB(long_branch_v4t_thumb_thumb_pic) \
2372 DEF_STUB(long_branch_v4t_arm_thumb_pic) \
2373 DEF_STUB(long_branch_v4t_thumb_arm_pic) \
2374 DEF_STUB(long_branch_thumb_only_pic) \
2375 DEF_STUB(long_branch_any_tls_pic) \
2376 DEF_STUB(long_branch_v4t_thumb_tls_pic) \
2377 DEF_STUB(a8_veneer_b_cond) \
2378 DEF_STUB(a8_veneer_b) \
2379 DEF_STUB(a8_veneer_bl) \
2380 DEF_STUB(a8_veneer_blx)
2382 #define DEF_STUB(x) arm_stub_##x,
2384 arm_stub_none,
2385 DEF_STUBS
2386 /* Note the first a8_veneer type */
2387 arm_stub_a8_veneer_lwm = arm_stub_a8_veneer_b_cond
2388 };
2389 #undef DEF_STUB
2392 {
2397 #define DEF_STUB(x) {elf32_arm_stub_##x, ARRAY_SIZE(elf32_arm_stub_##x)},
2400 DEF_STUBS
2401 };
2403 struct elf32_arm_stub_hash_entry
2404 {
2405 /* Base hash table entry structure. */
2408 /* The stub section. */
2411 /* Offset within stub_sec of the beginning of this stub. */
2412 bfd_vma stub_offset;
2414 /* Given the symbol's value and its section we can determine its final
2415 value when building the stubs (so the stub knows where to jump). */
2416 bfd_vma target_value;
2419 /* Offset to apply to relocation referencing target_value. */
2420 bfd_vma target_addend;
2422 /* The instruction which caused this stub to be generated (only valid for
2423 Cortex-A8 erratum workaround stubs at present). */
2426 /* The stub type. */
2428 /* Its encoding size in bytes. */
2430 /* Its template. */
2432 /* The size of the template (number of entries). */
2435 /* The symbol table entry, if any, that this was derived from. */
2438 /* Type of branch. */
2441 /* Where this stub is being called from, or, in the case of combined
2442 stub sections, the first input section in the group. */
2445 /* The name for the local symbol at the start of this stub. The
2446 stub name in the hash table has to be unique; this does not, so
2447 it can be friendlier. */
2449 };
2451 /* Used to build a map of a section. This is required for mixed-endian
2452 code/data. */
2455 {
2456 bfd_vma vma;
2458 }
2459 elf32_arm_section_map;
2461 /* Information about a VFP11 erratum veneer, or a branch to such a veneer. */
2464 {
2465 VFP11_ERRATUM_BRANCH_TO_ARM_VENEER,
2466 VFP11_ERRATUM_BRANCH_TO_THUMB_VENEER,
2467 VFP11_ERRATUM_ARM_VENEER,
2468 VFP11_ERRATUM_THUMB_VENEER
2469 }
2470 elf32_vfp11_erratum_type;
2473 {
2475 bfd_vma vma;
2476 union
2477 {
2478 struct
2479 {
2483 struct
2484 {
2489 elf32_vfp11_erratum_type type;
2490 }
2491 elf32_vfp11_erratum_list;
2494 {
2495 DELETE_EXIDX_ENTRY,
2496 INSERT_EXIDX_CANTUNWIND_AT_END
2497 }
2498 arm_unwind_edit_type;
2500 /* A (sorted) list of edits to apply to an unwind table. */
2502 {
2503 arm_unwind_edit_type type;
2504 /* Note: we sometimes want to insert an unwind entry corresponding to a
2505 section different from the one we're currently writing out, so record the
2506 (text) section this edit relates to here. */
2510 }
2511 arm_unwind_table_edit;
2514 {
2515 /* Information about mapping symbols. */
2520 /* Information about CPU errata. */
2523 /* Information about unwind tables. */
2524 union
2525 {
2526 /* Unwind info attached to a text section. */
2527 struct
2528 {
2532 /* Unwind info attached to an .ARM.exidx section. */
2533 struct
2534 {
2539 }
2540 _arm_elf_section_data;
2542 #define elf32_arm_section_data(sec) \
2543 ((_arm_elf_section_data *) elf_section_data (sec))
2545 /* A fix which might be required for Cortex-A8 Thumb-2 branch/TLB erratum.
2546 These fixes are subject to a relaxation procedure (in elf32_arm_size_stubs),
2547 so may be created multiple times: we use an array of these entries whilst
2548 relaxing which we can refresh easily, then create stubs for each potentially
2549 erratum-triggering instruction once we've settled on a solution. */
2554 bfd_vma offset;
2555 bfd_vma addend;
2560 };
2562 /* A table of relocs applied to branches which might trigger Cortex-A8
2563 erratum. */
2566 bfd_vma from;
2567 bfd_vma destination;
2572 bfd_boolean non_a8_stub;
2573 };
2575 /* The size of the thread control block. */
2576 #define TCB_SIZE 8
2578 /* ARM-specific information about a PLT entry, over and above the usual
2579 gotplt_union. */
2581 /* We reference count Thumb references to a PLT entry separately,
2582 so that we can emit the Thumb trampoline only if needed. */
2583 bfd_signed_vma thumb_refcount;
2585 /* Some references from Thumb code may be eliminated by BL->BLX
2586 conversion, so record them separately. */
2587 bfd_signed_vma maybe_thumb_refcount;
2589 /* How many of the recorded PLT accesses were from non-call relocations.
2590 This information is useful when deciding whether anything takes the
2591 address of an STT_GNU_IFUNC PLT. A value of 0 means that all
2592 non-call references to the function should resolve directly to the
2593 real runtime target. */
2596 /* Since PLT entries have variable size if the Thumb prologue is
2597 used, we need to record the index into .got.plt instead of
2598 recomputing it from the PLT offset. */
2599 bfd_signed_vma got_offset;
2600 };
2602 /* Information about an .iplt entry for a local STT_GNU_IFUNC symbol. */
2604 /* The information that is usually found in the generic ELF part of
2605 the hash table entry. */
2608 /* The information that is usually found in the ARM-specific part of
2609 the hash table entry. */
2612 /* A list of all potential dynamic relocations against this symbol. */
2614 };
2616 struct elf_arm_obj_tdata
2617 {
2620 /* tls_type for each local got entry. */
2623 /* GOTPLT entries for TLS descriptors. */
2626 /* Information for local symbols that need entries in .iplt. */
2629 /* Zero to warn when linking objects with incompatible enum sizes. */
2632 /* Zero to warn when linking objects with incompatible wchar_t sizes. */
2634 };
2636 #define elf_arm_tdata(bfd) \
2637 ((struct elf_arm_obj_tdata *) (bfd)->tdata.any)
2639 #define elf32_arm_local_got_tls_type(bfd) \
2640 (elf_arm_tdata (bfd)->local_got_tls_type)
2642 #define elf32_arm_local_tlsdesc_gotent(bfd) \
2643 (elf_arm_tdata (bfd)->local_tlsdesc_gotent)
2645 #define elf32_arm_local_iplt(bfd) \
2646 (elf_arm_tdata (bfd)->local_iplt)
2648 #define is_arm_elf(bfd) \
2649 (bfd_get_flavour (bfd) == bfd_target_elf_flavour \
2650 && elf_tdata (bfd) != NULL \
2651 && elf_object_id (bfd) == ARM_ELF_DATA)
2653 static bfd_boolean
2655 {
2657 ARM_ELF_DATA);
2658 }
2660 #define elf32_arm_hash_entry(ent) ((struct elf32_arm_link_hash_entry *)(ent))
2662 /* Arm ELF linker hash entry. */
2663 struct elf32_arm_link_hash_entry
2664 {
2667 /* Track dynamic relocs copied for this symbol. */
2670 /* ARM-specific PLT information. */
2673 #define GOT_UNKNOWN 0
2674 #define GOT_NORMAL 1
2675 #define GOT_TLS_GD 2
2676 #define GOT_TLS_IE 4
2677 #define GOT_TLS_GDESC 8
2678 #define GOT_TLS_GD_ANY_P(type) ((type & GOT_TLS_GD) || (type & GOT_TLS_GDESC))
2681 /* True if the symbol's PLT entry is in .iplt rather than .plt. */
2686 /* Offset of the GOTPLT entry reserved for the TLS descriptor,
2687 starting at the end of the jump table. */
2688 bfd_vma tlsdesc_got;
2690 /* The symbol marking the real symbol location for exported thumb
2691 symbols with Arm stubs. */
2694 /* A pointer to the most recently used stub hash entry against this
2695 symbol. */
2697 };
2699 /* Traverse an arm ELF linker hash table. */
2700 #define elf32_arm_link_hash_traverse(table, func, info) \
2701 (elf_link_hash_traverse \
2702 (&(table)->root, \
2703 (bfd_boolean (*) (struct elf_link_hash_entry *, void *)) (func), \
2704 (info)))
2706 /* Get the ARM elf linker hash table from a link_info structure. */
2707 #define elf32_arm_hash_table(info) \
2708 (elf_hash_table_id ((struct elf_link_hash_table *) ((info)->hash)) \
2709 == ARM_ELF_DATA ? ((struct elf32_arm_link_hash_table *) ((info)->hash)) : NULL)
2711 #define arm_stub_hash_lookup(table, string, create, copy) \
2712 ((struct elf32_arm_stub_hash_entry *) \
2713 bfd_hash_lookup ((table), (string), (create), (copy)))
2715 /* Array to keep track of which stub sections have been created, and
2716 information on stub grouping. */
2717 struct map_stub
2718 {
2719 /* This is the section to which stubs in the group will be
2720 attached. */
2722 /* The stub section. */
2724 };
2726 #define elf32_arm_compute_jump_table_size(htab) \
2727 ((htab)->next_tls_desc_index * 4)
2729 /* ARM ELF linker hash table. */
2730 struct elf32_arm_link_hash_table
2731 {
2732 /* The main hash table. */
2735 /* The size in bytes of the section containing the Thumb-to-ARM glue. */
2736 bfd_size_type thumb_glue_size;
2738 /* The size in bytes of the section containing the ARM-to-Thumb glue. */
2739 bfd_size_type arm_glue_size;
2741 /* The size in bytes of section containing the ARMv4 BX veneers. */
2742 bfd_size_type bx_glue_size;
2744 /* Offsets of ARMv4 BX veneers. Bit1 set if present, and Bit0 set when
2745 veneer has been populated. */
2748 /* The size in bytes of the section containing glue for VFP11 erratum
2749 veneers. */
2750 bfd_size_type vfp11_erratum_glue_size;
2752 /* A table of fix locations for Cortex-A8 Thumb-2 branch/TLB erratum. This
2753 holds Cortex-A8 erratum fix locations between elf32_arm_size_stubs() and
2754 elf32_arm_write_section(). */
2758 /* An arbitrary input BFD chosen to hold the glue sections. */
2761 /* Nonzero to output a BE8 image. */
2764 /* Zero if R_ARM_TARGET1 means R_ARM_ABS32.
2765 Nonzero if R_ARM_TARGET1 means R_ARM_REL32. */
2768 /* The relocation to use for R_ARM_TARGET2 relocations. */
2771 /* 0 = Ignore R_ARM_V4BX.
2772 1 = Convert BX to MOV PC.
2773 2 = Generate v4 interworing stubs. */
2776 /* Whether we should fix the Cortex-A8 Thumb-2 branch/TLB erratum. */
2779 /* Nonzero if the ARM/Thumb BLX instructions are available for use. */
2782 /* What sort of code sequences we should look for which may trigger the
2783 VFP11 denorm erratum. */
2784 bfd_arm_vfp11_fix vfp11_fix;
2786 /* Global counter for the number of fixes we have emitted. */
2789 /* Nonzero to force PIC branch veneers. */
2792 /* The number of bytes in the initial entry in the PLT. */
2793 bfd_size_type plt_header_size;
2795 /* The number of bytes in the subsequent PLT etries. */
2796 bfd_size_type plt_entry_size;
2798 /* True if the target system is VxWorks. */
2801 /* True if the target system is Symbian OS. */
2804 /* True if the target uses REL relocations. */
2807 /* The index of the next unused R_ARM_TLS_DESC slot in .rel.plt. */
2808 bfd_vma next_tls_desc_index;
2810 /* How many R_ARM_TLS_DESC relocations were generated so far. */
2811 bfd_vma num_tls_desc;
2813 /* Short-cuts to get to dynamic linker sections. */
2817 /* The (unloaded but important) VxWorks .rela.plt.unloaded section. */
2820 /* The offset into splt of the PLT entry for the TLS descriptor
2821 resolver. Special values are 0, if not necessary (or not found
2822 to be necessary yet), and -1 if needed but not determined
2823 yet. */
2824 bfd_vma dt_tlsdesc_plt;
2826 /* The offset into sgot of the GOT entry used by the PLT entry
2827 above. */
2828 bfd_vma dt_tlsdesc_got;
2830 /* Offset in .plt section of tls_arm_trampoline. */
2831 bfd_vma tls_trampoline;
2833 /* Data for R_ARM_TLS_LDM32 relocations. */
2834 union
2835 {
2836 bfd_signed_vma refcount;
2837 bfd_vma offset;
2840 /* Small local sym cache. */
2843 /* For convenience in allocate_dynrelocs. */
2846 /* The amount of space used by the reserved portion of the sgotplt
2847 section, plus whatever space is used by the jump slots. */
2848 bfd_vma sgotplt_jump_table_size;
2850 /* The stub hash table. */
2853 /* Linker stub bfd. */
2856 /* Linker call-backs. */
2860 /* Array to keep track of which stub sections have been created, and
2861 information on stub grouping. */
2864 /* Number of elements in stub_group. */
2867 /* Assorted information used by elf32_arm_size_stubs. */
2871 };
2873 /* Create an entry in an ARM ELF linker hash table. */
2879 {
2883 /* Allocate the structure if it has not already been allocated by a
2884 subclass. */
2891 /* Call the allocation method of the superclass. */
2896 {
2908 }
2911 }
2913 /* Ensure that we have allocated bookkeeping structures for ABFD's local
2914 symbols. */
2916 static bfd_boolean
2918 {
2920 {
2921 bfd_size_type num_syms;
2922 bfd_size_type size;
2944 }
2946 }
2948 /* Return the .iplt information for local symbol R_SYMNDX, which belongs
2949 to input bfd ABFD. Create the information if it doesn't already exist.
2950 Return null if an allocation fails. */
2954 {
2965 }
2967 /* Try to obtain PLT information for the symbol with index R_SYMNDX
2968 in ABFD's symbol table. If the symbol is global, H points to its
2969 hash table entry, otherwise H is null.
2971 Return true if the symbol does have PLT information. When returning
2972 true, point *ROOT_PLT at the target-independent reference count/offset
2973 union and *ARM_PLT at the ARM-specific information. */
2975 static bfd_boolean
2979 {
2983 {
2987 }
2999 }
3001 /* Return true if the PLT described by ARM_PLT requires a Thumb stub
3002 before it. */
3004 static bfd_boolean
3007 {
3013 }
3015 /* Return a pointer to the head of the dynamic reloc list that should
3016 be used for local symbol ISYM, which is symbol number R_SYMNDX in
3017 ABFD's symbol table. Return null if an error occurs. */
3022 {
3024 {
3031 }
3032 else
3033 {
3034 /* Track dynamic relocs needed for local syms too.
3035 We really need local syms available to do this
3036 easily. Oh well. */
3046 }
3047 }
3049 /* Initialize an entry in the stub hash table. */
3055 {
3056 /* Allocate the structure if it has not already been allocated by a
3057 subclass. */
3059 {
3064 }
3066 /* Call the allocation method of the superclass. */
3069 {
3072 /* Initialize the local fields. */
3087 }
3090 }
3092 /* Create .got, .gotplt, and .rel(a).got sections in DYNOBJ, and set up
3093 shortcuts to them in our hash table. */
3095 static bfd_boolean
3097 {
3104 /* BPABI objects never have a GOT, or associated sections. */
3112 }
3114 /* Create the .iplt, .rel(a).iplt and .igot.plt sections. */
3116 static bfd_boolean
3118 {
3123 flagword flags;
3131 {
3138 }
3141 {
3148 }
3151 {
3157 }
3159 }
3161 /* Create .plt, .rel(a).plt, .got, .got.plt, .rel(a).got, .dynbss, and
3162 .rel(a).bss sections in DYNOBJ, and set up shortcuts to them in our
3163 hash table. */
3165 static bfd_boolean
3167 {
3186 {
3191 {
3193 htab->plt_entry_size
3195 }
3196 else
3197 {
3198 htab->plt_header_size
3200 htab->plt_entry_size
3202 }
3203 }
3212 }
3214 /* Copy the extra info we tack onto an elf_link_hash_entry. */
3216 static void
3220 {
3227 {
3229 {
3233 /* Add reloc counts against the indirect sym to the direct sym
3234 list. Merge any entries against the same section. */
3236 {
3241 {
3246 }
3249 }
3251 }
3255 }
3258 {
3259 /* Copy over PLT info. */
3267 /* We should only allocate a function to .iplt once the final
3268 symbol information is known. */
3272 {
3275 }
3276 }
3279 }
3281 /* Create an ARM elf linker hash table. */
3285 {
3294 elf32_arm_link_hash_newfunc,
3296 ARM_ELF_DATA))
3297 {
3300 }
3322 #ifdef FOUR_WORD_PLT
3325 #else
3328 #endif
3348 {
3351 }
3354 }
3356 /* Free the derived linker hash table. */
3358 static void
3360 {
3366 }
3368 /* Determine if we're dealing with a Thumb only architecture. */
3370 static bfd_boolean
3372 {
3374 Tag_CPU_arch);
3384 Tag_CPU_arch_profile);
3387 }
3389 /* Determine if we're dealing with a Thumb-2 object. */
3391 static bfd_boolean
3393 {
3395 Tag_CPU_arch);
3397 }
3399 /* Determine what kind of NOPs are available. */
3401 static bfd_boolean
3403 {
3405 Tag_CPU_arch);
3410 }
3412 static bfd_boolean
3414 {
3416 Tag_CPU_arch);
3419 }
3421 static bfd_boolean
3423 {
3425 {
3439 }
3440 }
3442 /* Determine the type of stub needed, if any, for a call. */
3444 static enum elf32_arm_stub_type
3451 bfd_vma destination,
3455 {
3456 bfd_vma location;
3457 bfd_signed_vma branch_offset;
3479 /* Determine where the call point is. */
3486 /* For TLS call relocs, it is the caller's responsibility to provide
3487 the address of the appropriate trampoline. */
3493 {
3498 else
3501 {
3504 /* Note when dealing with PLT entries: the main PLT stub is in
3505 ARM mode, so if the branch is in Thumb mode, another
3506 Thumb->ARM stub will be inserted later just before the ARM
3507 PLT stub. We don't take this extra distance into account
3508 here, because if a long branch stub is needed, we'll add a
3509 Thumb->Arm one and branch directly to the ARM PLT entry
3510 because it avoids spreading offset corrections in several
3511 places. */
3518 }
3519 }
3520 /* Calls to STT_GNU_IFUNC symbols should go through a PLT. */
3527 {
3528 /* Handle cases where:
3529 - this call goes too far (different Thumb/Thumb2 max
3530 distance)
3531 - it's a Thumb->Arm call and blx is not available, or it's a
3532 Thumb->Arm branch (not bl). A stub is needed in this case,
3533 but only if this call is not through a PLT entry. Indeed,
3534 PLT stubs handle mode switching already.
3535 */
3539 || (thumb2
3547 {
3549 {
3550 /* Thumb to thumb. */
3552 {
3554 /* PIC stubs. */
3557 /* V5T and above. Stub starts with ARM code, so
3558 we must be able to switch mode before
3559 reaching it, which is only possible for 'bl'
3560 (ie R_ARM_THM_CALL relocation). */
3561 ? arm_stub_long_branch_any_thumb_pic
3562 /* On V4T, use Thumb code only. */
3565 /* non-PIC stubs. */
3568 /* V5T and above. */
3569 ? arm_stub_long_branch_any_any
3570 /* V4T. */
3572 }
3573 else
3574 {
3576 /* PIC stub. */
3577 ? arm_stub_long_branch_thumb_only_pic
3578 /* non-PIC stub. */
3580 }
3581 }
3582 else
3583 {
3584 /* Thumb to arm. */
3588 {
3593 }
3595 stub_type =
3597 /* PIC stubs. */
3599 /* TLS PIC stubs */
3603 /* V5T PIC and above. */
3604 ? arm_stub_long_branch_any_arm_pic
3605 /* V4T PIC stub. */
3608 /* non-PIC stubs. */
3610 /* V5T and above. */
3611 ? arm_stub_long_branch_any_any
3612 /* V4T. */
3615 /* Handle v4t short branches. */
3620 }
3621 }
3622 }
3627 {
3629 {
3630 /* Arm to thumb. */
3635 {
3640 }
3642 /* We have an extra 2-bytes reach because of
3643 the mode change (bit 24 (H) of BLX encoding). */
3649 {
3651 /* PIC stubs. */
3653 /* V5T and above. */
3654 ? arm_stub_long_branch_any_thumb_pic
3655 /* V4T stub. */
3658 /* non-PIC stubs. */
3660 /* V5T and above. */
3661 ? arm_stub_long_branch_any_any
3662 /* V4T. */
3664 }
3665 }
3666 else
3667 {
3668 /* Arm to arm. */
3671 {
3672 stub_type =
3674 /* PIC stubs. */
3676 /* TLS PIC Stub */
3677 ? arm_stub_long_branch_any_tls_pic
3679 /* non-PIC stubs. */
3681 }
3682 }
3683 }
3685 /* If a stub is needed, record the actual destination type. */
3690 }
3692 /* Build a name for an entry in the stub hash table. */
3700 {
3702 bfd_size_type len;
3705 {
3714 }
3715 else
3716 {
3728 }
3731 }
3733 /* Look up an entry in the stub hash. Stub entries are cached because
3734 creating the stub name takes a bit of time. */
3743 {
3751 /* If this input section is part of a group of sections sharing one
3752 stub section, then use the id of the first section in the group.
3753 Stub names need to include a section id, as there may well be
3754 more than one stub used to reach say, printf, and we need to
3755 distinguish between them. */
3762 {
3764 }
3765 else
3766 {
3779 }
3782 }
3784 /* Find or create a stub section. Returns a pointer to the stub section, and
3785 the section to which the stub section will be attached (in *LINK_SEC_P).
3786 LINK_SEC_P may be NULL. */
3791 {
3798 {
3801 {
3803 bfd_size_type len;
3818 }
3820 }
3826 }
3828 /* Add a new stub entry to the stub hash. Not all fields of the new
3829 stub entry are initialised. */
3835 {
3844 /* Enter this entry into the linker stub hash table. */
3848 {
3851 stub_name);
3853 }
3860 }
3862 /* Store an Arm insn into an output section not processed by
3863 elf32_arm_write_section. */
3865 static void
3868 {
3871 else
3873 }
3875 /* Store a 16-bit Thumb insn into an output section not processed by
3876 elf32_arm_write_section. */
3878 static void
3881 {
3884 else
3886 }
3888 /* If it's possible to change R_TYPE to a more efficient access
3889 model, return the new reloc type. */
3891 static unsigned
3894 {
3900 /* We do not support relaxations for Old TLS models. */
3902 {
3909 }
3912 }
3914 static bfd_reloc_status_type elf32_arm_final_link_relocate
3920 static unsigned int
3922 {
3924 {
3949 }
3950 }
3952 static bfd_boolean
3955 {
3956 #define MAXRELOCS 2
3963 bfd_vma sym_value;
3972 /* Massage our args to the form they really have. */
3984 /* We have to do less-strictly-aligned fixes last. */
3987 /* Make a note of the offset within the stubs for this entry. */
3993 /* This is the address of the stub destination. */
4003 {
4005 {
4007 {
4010 {
4011 /* We've borrowed the reloc_addend field to mean we should
4012 insert a condition code into this (Thumb-1 branch)
4013 instruction. See THUMB16_BCOND_INSN. */
4016 }
4019 }
4029 {
4032 }
4039 /* Handle cases where the target is encoded within the
4040 instruction. */
4042 {
4045 }
4059 }
4060 }
4064 /* Stub size has already been computed in arm_size_one_stub. Check
4065 consistency. */
4068 /* Destination is Thumb. Force bit 0 to 1 to reflect this. */
4072 /* Assume there is at least one and at most MAXRELOCS entries to relocate
4073 in each stub. */
4081 {
4082 Elf_Internal_Rela rel;
4083 bfd_boolean unresolved_reloc;
4085 enum arm_st_branch_type branch_type
4096 /* The first relocation in the elf32_arm_stub_a8_veneer_b_cond[]
4097 template should refer back to the instruction after the original
4098 branch. */
4101 /* There may be unintended consequences if this is not true. */
4104 /* Note: _bfd_final_link_relocate doesn't handle these relocations
4105 properly. We should probably use this function unconditionally,
4106 rather than only for certain relocations listed in the enclosing
4107 conditional, for the sake of consistency. */
4114 }
4115 else
4116 {
4117 Elf_Internal_Rela rel;
4118 bfd_boolean unresolved_reloc;
4135 }
4138 #undef MAXRELOCS
4139 }
4141 /* Calculate the template, template size and instruction size for a stub.
4142 Return value is the instruction size. */
4144 static unsigned int
4148 {
4163 {
4165 {
4179 }
4180 }
4183 }
4185 /* As above, but don't actually build the stub. Just bump offset so
4186 we know stub section sizes. */
4188 static bfd_boolean
4191 {
4196 /* Massage our args to the form they really have. */
4213 }
4215 /* External entry points for sizing and building linker stubs. */
4217 /* Set up various things so that we can make a list of input sections
4218 for each output section included in the link. Returns -1 on error,
4219 0 when no stubs will be needed, and 1 on success. */
4221 int
4224 {
4230 bfd_size_type amt;
4238 /* Count the number of input BFDs and find the top input section id. */
4242 {
4247 {
4250 }
4251 }
4260 /* We can't use output_bfd->section_count here to find the top output
4261 section index as some sections may have been removed, and
4262 _bfd_strip_section_from_output doesn't renumber the indices. */
4266 {
4269 }
4278 /* For sections we aren't interested in, mark their entries with a
4279 value we can check later. */
4281 do
4288 {
4291 }
4294 }
4296 /* The linker repeatedly calls this function for each input section,
4297 in the order that input sections are linked into output sections.
4298 Build lists of input sections to determine groupings between which
4299 we may insert linker stubs. */
4301 void
4304 {
4311 {
4315 {
4316 /* Steal the link_sec pointer for our list. */
4317 #define PREV_SEC(sec) (htab->stub_group[(sec)->id].link_sec)
4318 /* This happens to make the list in reverse order,
4319 which we reverse later. */
4322 }
4323 }
4324 }
4326 /* See whether we can group stub sections together. Grouping stub
4327 sections may result in fewer stubs. More importantly, we need to
4328 put all .init* and .fini* stubs at the end of the .init or
4329 .fini output sections respectively, because glibc splits the
4330 _init and _fini functions into multiple parts. Putting a stub in
4331 the middle of a function is not a good idea. */
4333 static void
4335 bfd_size_type stub_group_size,
4336 bfd_boolean stubs_always_after_branch)
4337 {
4340 do
4341 {
4348 /* Reverse the list: we must avoid placing stubs at the
4349 beginning of the section because the beginning of the text
4350 section may be required for an interrupt vector in bare metal
4351 code. */
4352 #define NEXT_SEC PREV_SEC
4355 {
4356 /* Pop from tail. */
4360 /* Push on head. */
4363 }
4366 {
4370 bfd_vma end_of_next;
4374 {
4378 /* End of NEXT is too far from start, so stop. */
4380 /* Add NEXT to the group. */
4382 }
4384 /* OK, the size from the start to the start of CURR is less
4385 than stub_group_size and thus can be handled by one stub
4386 section. (Or the head section is itself larger than
4387 stub_group_size, in which case we may be toast.)
4388 We should really be keeping track of the total size of
4389 stubs added here, as stubs contribute to the final output
4390 section size. */
4391 do
4392 {
4394 /* Set up this stub group. */
4396 }
4399 /* But wait, there's more! Input sections up to stub_group_size
4400 bytes after the stub section can be handled by it too. */
4402 {
4406 {
4409 /* End of NEXT is too far from stubs, so stop. */
4411 /* Add NEXT to the stub group. */
4415 }
4416 }
4418 }
4419 }
4423 #undef PREV_SEC
4424 #undef NEXT_SEC
4425 }
4427 /* Comparison function for sorting/searching relocations relating to Cortex-A8
4428 erratum fix. */
4430 static int
4432 {
4440 else
4442 }
4447 /* Helper function to scan code for sequences which might trigger the Cortex-A8
4448 branch/TLB erratum. Fill in the table described by A8_FIXES_P,
4449 NUM_A8_FIXES_P, A8_FIX_TABLE_SIZE_P. Returns true if an error occurs, false
4450 otherwise. */
4452 static bfd_boolean
4462 {
4475 {
4479 bfd_vma base_vma;
4498 {
4509 /* Span is entirely within a single 4KB region: skip scanning. */
4514 /* Scan for 32-bit Thumb-2 branches which span two 4K regions, where:
4516 * The opcode is BLX.W, BL.W, B.W, Bcc.W
4517 * The branch target is in the same 4KB region as the
4518 first half of the branch.
4519 * The instruction before the branch is a 32-bit
4520 length non-branch instruction. */
4522 {
4531 {
4532 /* Load the rest of the insn (in manual-friendly order). */
4535 /* Encoding T4: B<c>.W. */
4537 /* Encoding T1: BL<c>.W. */
4539 /* Encoding T2: BLX<c>.W. */
4541 /* Encoding T3: B<c>.W (not permitted in IT block). */
4544 }
4549 && insn_32bit
4550 && is_32bit_branch
4551 && last_was_32bit
4553 {
4557 bfd_vma target;
4569 {
4573 /* We don't care about the error returned from this
4574 function, only if there is glue or not. */
4581 /* Keep a simpler condition, for the sake of clarity. */
4587 {
4591 else
4593 }
4594 }
4596 /* Check if we have an offending branch instruction. */
4599 /* We've already made a stub for this instruction, e.g.
4600 it's a long branch or a Thumb->ARM stub. Assume that
4601 stub will suffice to work around the A8 erratum (see
4602 setting of always_after_branch above). */
4603 ;
4605 {
4614 }
4616 {
4636 }
4639 {
4642 /* The original instruction is a BL, but the target is
4643 an ARM instruction. If we were not making a stub,
4644 the BL would have been converted to a BLX. Use the
4645 BLX stub instead in that case. */
4648 {
4652 }
4653 /* Conversely, if the original instruction was
4654 BLX but the target is Thumb mode, use the BL
4655 stub. */
4658 {
4662 }
4667 /* If we found a relocation, use the proper destination,
4668 not the offset in the (unrelocated) instruction.
4669 Note this is always done if we switched the stub type
4670 above. */
4672 offset =
4675 /* If the stub will use a Thumb-mode branch to a
4676 PLT target, redirect it to the preceding Thumb
4677 entry point. */
4683 /* The BLX stub is ARM-mode code. Adjust the offset to
4684 take the different PC value (+8 instead of +4) into
4685 account. */
4690 {
4694 {
4700 }
4703 {
4704 /* If we're doing a subsequent scan,
4705 check if we've found the same fix as
4706 before, and try and reuse the stub
4707 name. */
4711 {
4715 }
4716 }
4719 {
4723 }
4735 num_a8_fixes++;
4736 }
4737 }
4738 }
4743 }
4744 }
4748 }
4755 }
4757 /* Determine and set the size of the stub section for a final link.
4759 The basic idea here is to examine all the relocations looking for
4760 PC-relative calls to a target that is unreachable with a "bl"
4761 instruction. */
4763 bfd_boolean
4767 bfd_signed_vma group_size,
4770 {
4771 bfd_size_type stub_group_size;
4772 bfd_boolean stubs_always_after_branch;
4783 {
4788 }
4790 /* Propagate mach to stub bfd, because it may not have been
4791 finalized when we created stub_bfd. */
4795 /* Stash our params away. */
4801 /* The Cortex-A8 erratum fix depends on stubs not being in the same 4K page
4802 as the first half of a 32-bit branch straddling two 4K pages. This is a
4803 crude way of enforcing that. */
4809 else
4813 {
4814 /* Default values. */
4815 /* Thumb branch range is +-4MB has to be used as the default
4816 maximum size (a given section can contain both ARM and Thumb
4817 code, so the worst case has to be taken into account).
4819 This value is 24K less than that, which allows for 2025
4820 12-byte stubs. If we exceed that, then we will fail to link.
4821 The user will have to relink with an explicit group size
4822 option. */
4824 }
4828 /* If we're applying the cortex A8 fix, we need to determine the
4829 program header size now, because we cannot change it later --
4830 that could alter section placements. Notice the A8 erratum fix
4831 ends up requiring the section addresses to remain unchanged
4832 modulo the page size. That's something we cannot represent
4833 inside BFD, and we don't want to force the section alignment to
4834 be the page size. */
4839 {
4850 {
4857 /* We'll need the symbol table in a second. */
4862 /* Walk over each section attached to the input bfd. */
4866 {
4869 /* If there aren't any relocs, then there's nothing more
4870 to do. */
4876 /* If this section is a link-once section that will be
4877 discarded, then don't create any stubs. */
4882 /* Get the relocs. */
4883 internal_relocs
4889 /* Now examine each relocation. */
4893 {
4898 bfd_vma sym_value;
4899 bfd_vma destination;
4912 {
4914 error_ret_free_internal:
4918 }
4922 hash = elf32_arm_hash_entry
4926 /* Only look for stubs on branch instructions, or
4927 non-relaxed TLSCALL */
4940 : (elf32_arm_local_got_tls_type
4945 /* Now determine the call target, its name, value,
4946 section. */
4954 {
4955 /* A non-relaxed TLS call. The target is the
4956 plt-resident trampoline and nothing to do
4957 with the symbol. */
4964 }
4966 {
4967 /* It's a local symbol. */
4971 {
4972 local_syms
4975 local_syms
4981 }
4990 else
4991 sym_sec =
4995 /* This is an undefined symbol. It can never
4996 be resolved. */
5006 sym_name
5010 }
5011 else
5012 {
5013 /* It's an external symbol. */
5021 {
5028 /* For a destination in a shared library,
5029 use the PLT stub as target address to
5030 decide whether a branch stub is
5031 needed. */
5036 {
5040 destination = (sym_value
5043 }
5048 }
5051 {
5052 /* For a shared library, use the PLT stub as
5053 target address to decide whether a long
5054 branch stub is needed.
5055 For absolute code, they cannot be handled. */
5063 {
5067 destination = (sym_value
5070 }
5071 else
5073 }
5074 else
5075 {
5078 }
5082 }
5084 do
5085 {
5086 /* Determine what (if any) linker stub is needed. */
5094 /* Support for grouping stub sections. */
5097 /* Get the name of this stub. */
5103 /* We've either created a stub for this reloc already,
5104 or we are about to. */
5107 stub_entry = arm_stub_hash_lookup
5111 {
5112 /* The proper stub has already been created. */
5116 }
5119 htab);
5121 {
5124 }
5139 {
5142 }
5144 /* For historical reasons, use the existing names for
5145 ARM-to-Thumb and Thumb-to-ARM stubs. */
5156 else
5158 sym_name);
5161 }
5164 /* Look for relocations which might trigger Cortex-A8
5165 erratum. */
5171 {
5177 {
5178 /* Found a candidate. Note we haven't checked the
5179 destination is within 4K here: if we do so (and
5180 don't create an entry in a8_relocs) we can't tell
5181 that a branch should have been relocated when
5182 scanning later. */
5184 {
5190 }
5200 num_a8_relocs++;
5201 }
5202 }
5203 }
5205 /* We're done with the internal relocs, free them. */
5208 }
5211 {
5212 /* Sort relocs which might apply to Cortex-A8 erratum. */
5217 /* Scan for branches which might trigger Cortex-A8 erratum. */
5224 }
5225 }
5233 /* OK, we've added some stubs. Find out the new size of the
5234 stub sections. */
5238 {
5239 /* Ignore non-stub sections. */
5244 }
5248 /* Add Cortex-A8 erratum veneers to stub section sizes too. */
5251 {
5258 stub_sec->size
5260 NULL);
5261 }
5264 /* Ask the linker to do its stuff. */
5266 }
5268 /* Add stubs for Cortex-A8 erratum fixes now. */
5270 {
5272 {
5285 {
5288 stub_name);
5290 }
5309 }
5311 /* Stash the Cortex-A8 erratum fix array for use later in
5312 elf32_arm_write_section(). */
5315 }
5316 else
5317 {
5320 }
5323 error_ret_free_local:
5325 }
5327 /* Build all the stubs associated with the current output file. The
5328 stubs are kept in a hash table attached to the main linker hash
5329 table. We also set up the .plt entries for statically linked PIC
5330 functions here. This function is called via arm_elf_finish in the
5331 linker. */
5333 bfd_boolean
5335 {
5347 {
5348 bfd_size_type size;
5350 /* Ignore non-stub sections. */
5354 /* Allocate memory to hold the linker stubs. */
5360 }
5362 /* Build the stubs as directed by the stub hash table. */
5366 {
5367 /* Place the cortex a8 stubs last. */
5370 }
5373 }
5375 /* Locate the Thumb encoded calling stub for NAME. */
5381 {
5386 /* We need a pointer to the armelf specific hash table. */
5398 hash = elf_link_hash_lookup
5409 }
5411 /* Locate the ARM encoded calling stub for NAME. */
5417 {
5422 /* We need a pointer to the elfarm specific hash table. */
5434 myh = elf_link_hash_lookup
5445 }
5447 /* ARM->Thumb glue (static images):
5449 .arm
5450 __func_from_arm:
5451 ldr r12, __func_addr
5452 bx r12
5453 __func_addr:
5454 .word func @ behave as if you saw a ARM_32 reloc.
5456 (v5t static images)
5457 .arm
5458 __func_from_arm:
5459 ldr pc, __func_addr
5460 __func_addr:
5461 .word func @ behave as if you saw a ARM_32 reloc.
5463 (relocatable images)
5464 .arm
5465 __func_from_arm:
5466 ldr r12, __func_offset
5467 add r12, r12, pc
5468 bx r12
5469 __func_offset:
5470 .word func - . */
5472 #define ARM2THUMB_STATIC_GLUE_SIZE 12
5477 #define ARM2THUMB_V5_STATIC_GLUE_SIZE 8
5481 #define ARM2THUMB_PIC_GLUE_SIZE 16
5486 /* Thumb->ARM: Thumb->(non-interworking aware) ARM
5488 .thumb .thumb
5489 .align 2 .align 2
5490 __func_from_thumb: __func_from_thumb:
5491 bx pc push {r6, lr}
5492 nop ldr r6, __func_addr
5493 .arm mov lr, pc
5494 b func bx r6
5495 .arm
5496 ;; back_to_thumb
5497 ldmia r13! {r6, lr}
5498 bx lr
5499 __func_addr:
5500 .word func */
5502 #define THUMB2ARM_GLUE_SIZE 8
5507 #define VFP11_ERRATUM_VENEER_SIZE 8
5509 #define ARM_BX_VENEER_SIZE 12
5514 #ifndef ELFARM_NABI_C_INCLUDED
5515 static void
5517 {
5522 {
5523 /* Do not include empty glue sections in the output. */
5525 {
5529 }
5531 }
5542 }
5544 bfd_boolean
5546 {
5554 ARM2THUMB_GLUE_SECTION_NAME);
5558 THUMB2ARM_GLUE_SECTION_NAME);
5562 VFP11_ERRATUM_VENEER_SECTION_NAME);
5566 ARM_BX_GLUE_SECTION_NAME);
5569 }
5571 /* Allocate space and symbols for calling a Thumb function from Arm mode.
5572 returns the symbol identifying the stub. */
5577 {
5584 bfd_vma val;
5585 bfd_size_type size;
5591 s = bfd_get_section_by_name
5603 myh = elf_link_hash_lookup
5607 {
5608 /* We've already seen this guy. */
5611 }
5613 /* The only trick here is using hash_table->arm_glue_size as the value.
5614 Even though the section isn't allocated yet, this is where we will be
5615 putting it. The +1 on the value marks that the stub has not been
5616 output yet - not that it is a Thumb function. */
5634 else
5641 }
5643 /* Allocate space for ARMv4 BX veneers. */
5645 static void
5647 {
5653 bfd_vma val;
5655 /* BX PC does not need a veneer. */
5663 /* Check if this veneer has already been allocated. */
5667 s = bfd_get_section_by_name
5672 /* Add symbol for veneer. */
5680 myh = elf_link_hash_lookup
5698 }
5701 /* Add an entry to the code/data map for section SEC. */
5703 static void
5705 {
5710 {
5715 }
5720 {
5725 }
5728 {
5731 }
5732 }
5735 /* Record information about a VFP11 denorm-erratum veneer. Only ARM-mode
5736 veneers are handled for now. */
5738 static bfd_vma
5744 {
5750 bfd_vma val;
5758 s = bfd_get_section_by_name
5773 myh = elf_link_hash_lookup
5788 /* Link veneer back to calling location. */
5802 /* A symbol for the return from the veneer. */
5806 myh = elf_link_hash_lookup
5823 /* Generate a mapping symbol for the veneer section, and explicitly add an
5824 entry for that symbol to the code/data map for the section. */
5826 {
5828 /* FIXME: Creates an ARM symbol. Thumb mode will need attention if it
5829 ever requires this erratum fix. */
5839 /* The elf32_arm_init_maps function only cares about symbols from input
5840 BFDs. We must make a note of this generated mapping symbol
5841 ourselves so that code byteswapping works properly in
5842 elf32_arm_write_section. */
5844 }
5850 /* The offset of the veneer. */
5852 }
5854 #define ARM_GLUE_SECTION_FLAGS \
5855 (SEC_ALLOC | SEC_LOAD | SEC_HAS_CONTENTS | SEC_IN_MEMORY | SEC_CODE \
5856 | SEC_READONLY | SEC_LINKER_CREATED)
5858 /* Create a fake section for use by the ARM backend of the linker. */
5860 static bfd_boolean
5862 {
5867 /* Already made. */
5876 /* Set the gc mark to prevent the section from being removed by garbage
5877 collection, despite the fact that no relocs refer to this section. */
5881 }
5883 /* Add the glue sections to ABFD. This function is called from the
5884 linker scripts in ld/emultempl/{armelf}.em. */
5886 bfd_boolean
5889 {
5890 /* If we are only performing a partial
5891 link do not bother adding the glue. */
5899 }
5901 /* Select a BFD to be used to hold the sections used by the glue code.
5902 This function is called from the linker scripts in ld/emultempl/
5903 {armelf/pe}.em. */
5905 bfd_boolean
5907 {
5910 /* If we are only performing a partial link
5911 do not bother getting a bfd to hold the glue. */
5915 /* Make sure we don't attach the glue sections to a dynamic object. */
5924 /* Save the bfd for later use. */
5928 }
5930 static void
5932 {
5936 }
5938 bfd_boolean
5941 {
5950 /* If we are only performing a partial link do not bother
5951 to construct any glue. */
5955 /* Here we have a bfd that is to be included on the link. We have a
5956 hook to do reloc rummaging, before section sizes are nailed down. */
5963 {
5965 abfd);
5967 }
5969 /* PR 5398: If we have not decided to include any loadable sections in
5970 the output then we will not have a glue owner bfd. This is OK, it
5971 just means that there is nothing else for us to do here. */
5975 /* Rummage around all the relocs and map the glue vectors. */
5982 {
5991 /* Load the relocs. */
5992 internal_relocs
6000 {
6009 /* These are the only relocation types we care about. */
6014 /* Get the section contents if we haven't done so already. */
6016 {
6017 /* Get cached copy if it exists. */
6020 else
6021 {
6022 /* Go get them off disk. */
6025 }
6026 }
6029 {
6035 }
6037 /* If the relocation is not against a symbol it cannot concern us. */
6040 /* We don't care about local symbols. */
6044 /* This is an external symbol. */
6049 /* If the relocation is against a static symbol it must be within
6050 the current section and so cannot be a cross ARM/Thumb relocation. */
6054 /* If the call will go through a PLT entry then we do not need
6055 glue. */
6060 {
6062 /* This one is a call from arm code. We need to look up
6063 the target of the call. If it is a thumb target, we
6064 insert glue. */
6071 }
6072 }
6083 }
6087 error_return:
6096 }
6097 #endif
6100 /* Initialise maps of ARM/Thumb/data for input BFDs. */
6102 void
6104 {
6109 /* PR 7093: Make sure that we are dealing with an arm elf binary. */
6119 /* Obtain a buffer full of symbols for this BFD. The hdr->sh_info field
6120 should contain the number of local symbols, which should come before any
6121 global symbols. Mapping symbols are always local. */
6123 NULL);
6125 /* No internal symbols read? Skip this BFD. */
6130 {
6137 {
6142 BFD_ARM_SPECIAL_SYM_TYPE_MAP))
6144 }
6145 }
6146 }
6149 /* Auto-select enabling of Cortex-A8 erratum fix if the user didn't explicitly
6150 say what they wanted. */
6152 void
6154 {
6162 {
6163 /* Turn on Cortex-A8 erratum workaround for ARMv7-A. */
6168 else
6170 }
6171 }
6174 void
6176 {
6182 /* We assume that ARMv7+ does not need the VFP11 denorm erratum fix. */
6184 {
6186 {
6193 /* Give a warning, but do as the user requests anyway. */
6196 }
6197 }
6199 /* For earlier architectures, we might need the workaround, but do not
6200 enable it by default. If users is running with broken hardware, they
6201 must enable the erratum fix explicitly. */
6203 }
6206 enum bfd_arm_vfp11_pipe
6207 {
6208 VFP11_FMAC,
6209 VFP11_LS,
6210 VFP11_DS,
6211 VFP11_BAD
6212 };
6214 /* Return a VFP register number. This is encoded as RX:X for single-precision
6215 registers, or X:RX for double-precision registers, where RX is the group of
6216 four bits in the instruction encoding and X is the single extension bit.
6217 RX and X fields are specified using their lowest (starting) bit. The return
6218 value is:
6220 0...31: single-precision registers s0...s31
6221 32...63: double-precision registers d0...d31.
6223 Although X should be zero for VFP11 (encoding d0...d15 only), we might
6224 encounter VFP3 instructions, so we allow the full range for DP registers. */
6226 static unsigned int
6229 {
6232 else
6234 }
6236 /* Set bits in *WMASK according to a register number REG as encoded by
6237 bfd_arm_vfp11_regno(). Ignore d16-d31. */
6239 static void
6241 {
6246 }
6248 /* Return TRUE if WMASK overwrites anything in REGS. */
6250 static bfd_boolean
6252 {
6256 {
6269 }
6272 }
6274 /* In this function, we're interested in two things: finding input registers
6275 for VFP data-processing instructions, and finding the set of registers which
6276 arbitrary VFP instructions may write to. We use a 32-bit unsigned int to
6277 hold the written set, so FLDM etc. are easy to deal with (we're only
6278 interested in 32 SP registers or 16 dp registers, due to the VFP version
6279 implemented by the chip in question). DP registers are marked by setting
6280 both SP registers in the write mask). */
6282 static enum bfd_arm_vfp11_pipe
6285 {
6290 {
6300 {
6322 vfp_binop:
6330 {
6335 {
6349 /* These instructions will not bounce due to underflow. */
6355 /* fsqrt cannot underflow, but it can (perhaps) overwrite
6356 registers to cause the erratum in previous instructions. */
6362 {
6367 /* Only FCVTSD can underflow. */
6374 }
6379 }
6380 }
6385 }
6386 }
6387 /* Two-register transfer. */
6389 {
6393 {
6396 else
6397 {
6400 }
6401 }
6404 }
6406 {
6411 {
6418 {
6426 }
6436 }
6439 }
6440 /* Single-register transfer. Note L==0. */
6442 {
6447 {
6450 /* Mark fmdhr and fmdlr as writing to the whole of the DP
6451 destination register. I don't know if this is exactly right,
6452 but it is the conservative choice. */
6458 }
6461 }
6464 }
6470 /* Look for potentially-troublesome code sequences which might trigger the
6471 VFP11 denormal/antidependency erratum. See, e.g., the ARM1136 errata sheet
6472 (available from ARM) for details of the erratum. A short version is
6473 described in ld.texinfo. */
6475 bfd_boolean
6477 {
6488 /* We use a simple FSM to match troublesome VFP11 instruction sequences.
6489 The states transition as follows:
6491 0 -> 1 (vector) or 0 -> 2 (scalar)
6492 A VFP FMAC-pipeline instruction has been seen. Fill
6493 regs[0]..regs[numregs-1] with its input operands. Remember this
6494 instruction in 'first_fmac'.
6496 1 -> 2
6497 Any instruction, except for a VFP instruction which overwrites
6498 regs[*].
6500 1 -> 3 [ -> 0 ] or
6501 2 -> 3 [ -> 0 ]
6502 A VFP instruction has been seen which overwrites any of regs[*].
6503 We must make a veneer! Reset state to 0 before examining next
6504 instruction.
6506 2 -> 0
6507 If we fail to match anything in state 2, reset to state 0 and reset
6508 the instruction pointer to the instruction after 'first_fmac'.
6510 If the VFP11 vector mode is in use, there must be at least two unrelated
6511 instructions between anti-dependent VFP11 instructions to properly avoid
6512 triggering the erratum, hence the use of the extra state 1. */
6514 /* If we are only performing a partial link do not bother
6515 to construct any glue. */
6519 /* Skip if this bfd does not correspond to an ELF image. */
6523 /* We should have chosen a fix type by the time we get here. */
6529 /* Skip this BFD if it corresponds to an executable or dynamic object. */
6534 {
6538 /* If we don't have executable progbits, we're not interested in this
6539 section. Also skip if section is to be excluded. */
6559 elf32_arm_compare_mapping);
6562 {
6568 /* FIXME: Only ARM mode is supported at present. We may need to
6569 support Thumb-2 mode also at some point. */
6574 {
6589 {
6593 /* I'm assuming the VFP11 erratum can trigger with denorm
6594 operands on either the FMAC or the DS pipeline. This might
6595 lead to slightly overenthusiastic veneer insertion. */
6597 {
6601 }
6605 {
6608 other_regs,
6612 numregs))
6614 else
6616 }
6620 {
6623 other_regs,
6627 numregs))
6629 else
6630 {
6633 }
6634 }
6639 }
6642 {
6651 {
6658 }
6661 first_fmac);
6669 }
6672 }
6673 }
6679 }
6683 error_return:
6689 }
6691 /* Find virtual-memory addresses for VFP11 erratum veneers and return locations
6692 after sections have been laid out, using specially-named symbols. */
6694 void
6697 {
6705 /* Skip if this bfd does not correspond to an ELF image. */
6717 {
6722 {
6724 bfd_vma vma;
6727 {
6730 /* Find veneer symbol. */
6734 myh = elf_link_hash_lookup
6750 /* Find return location. */
6754 myh = elf_link_hash_lookup
6770 }
6771 }
6772 }
6775 }
6778 /* Set target relocation values needed during linking. */
6780 void
6787 bfd_arm_vfp11_fix vfp11_fix,
6790 {
6804 else
6805 {
6807 target2_type);
6808 }
6818 }
6820 /* Replace the target offset of a Thumb bl or b.w instruction. */
6822 static void
6824 {
6825 bfd_vma upper;
6826 bfd_vma lower;
6843 }
6845 /* Thumb code calling an ARM function. */
6847 static int
6855 bfd_vma offset,
6856 bfd_signed_vma addend,
6857 bfd_vma val,
6859 {
6861 bfd_vma my_offset;
6877 THUMB2ARM_GLUE_SECTION_NAME);
6884 {
6888 {
6895 }
6906 ret_offset =
6907 /* Address of destination of the stub. */
6910 /* Offset from the start of the current section
6911 to the start of the stubs. */
6913 /* Offset of the start of this stub from the start of the stubs. */
6914 + my_offset
6915 /* Address of the start of the current section. */
6917 /* The branch instruction is 4 bytes into the stub. */
6919 /* ARM branches work from the pc of the instruction + 8. */
6925 }
6929 /* Now go back and fix up the original BL insn to point to here. */
6930 ret_offset =
6931 /* Address of where the stub is located. */
6933 /* Address of where the BL is located. */
6936 /* Addend in the relocation. */
6937 - addend
6938 /* Biassing for PC-relative addressing. */
6944 }
6946 /* Populate an Arm to Thumb stub. Returns the stub symbol. */
6954 bfd_vma val,
6957 {
6958 bfd_vma my_offset;
6974 {
6978 {
6983 }
6990 {
6991 /* For relocatable objects we can't use absolute addresses,
6992 so construct the address from a relative offset. */
6993 /* TODO: If the offset is small it's probably worth
6994 constructing the address with adds. */
7001 /* Adjust the offset by 4 for the position of the add,
7002 and 8 for the pipeline offset. */
7009 }
7011 {
7015 /* It's a thumb address. Add the low order bit. */
7018 }
7019 else
7020 {
7027 /* It's a thumb address. Add the low order bit. */
7032 }
7033 }
7038 }
7040 /* Arm code calling a Thumb function. */
7042 static int
7050 bfd_vma offset,
7051 bfd_signed_vma addend,
7052 bfd_vma val,
7054 {
7056 bfd_vma my_offset;
7067 ARM2THUMB_GLUE_SECTION_NAME);
7081 /* Somehow these are both 4 too far, so subtract 8. */
7083 + my_offset
7095 }
7097 /* Populate Arm stub for an exported Thumb function. */
7099 static bfd_boolean
7101 {
7108 bfd_vma val;
7112 /* Allocate stubs for exported Thumb functions on v4t. */
7121 ARM2THUMB_GLUE_SECTION_NAME);
7139 }
7141 /* Populate ARMv4 BX veneers. Returns the absolute adress of the veneer. */
7143 static bfd_vma
7145 {
7147 bfd_vma glue_addr;
7156 ARM_BX_GLUE_SECTION_NAME);
7166 {
7172 }
7175 }
7177 /* Generate Arm stubs for exported Thumb symbols. */
7178 static void
7181 {
7185 /* Ignore this if we are not called by the ELF backend linker. */
7192 /* If blx is available then exported Thumb symbols are OK and there is
7193 nothing to do. */
7198 link_info);
7199 }
7201 /* Reserve space for COUNT dynamic relocations in relocation selection
7202 SRELOC. */
7204 static void
7206 bfd_size_type count)
7207 {
7215 }
7217 /* Reserve space for COUNT R_ARM_IRELATIVE relocations. If the link is
7218 dynamic, the relocations should go in SRELOC, otherwise they should
7219 go in the special .rel.iplt section. */
7221 static void
7223 bfd_size_type count)
7224 {
7230 else
7231 {
7234 }
7235 }
7237 /* Add relocation REL to the end of relocation section SRELOC. */
7239 static void
7242 {
7257 }
7259 /* Allocate room for a PLT entry described by ROOT_PLT and ARM_PLT.
7260 IS_IPLT_ENTRY says whether the entry belongs to .iplt rather than
7261 to .plt. */
7263 static void
7265 bfd_boolean is_iplt_entry,
7268 {
7276 {
7280 /* Allocate room for an R_ARM_IRELATIVE relocation in .rel.iplt. */
7282 }
7283 else
7284 {
7288 /* Allocate room for an R_JUMP_SLOT relocation in .rel.plt. */
7291 /* If this is the first .plt entry, make room for the special
7292 first entry. */
7295 }
7297 /* Allocate the PLT entry itself, including any leading Thumb stub. */
7304 {
7305 /* We also need to make an entry in the .got.plt section, which
7306 will be placed in the .got section by the linker script. */
7309 }
7310 }
7312 /* Fill in a PLT entry and its associated GOT slot. If DYNINDX == -1,
7313 the entry lives in .iplt and resolves to (*SYM_VALUE)().
7314 Otherwise, DYNINDX is the index of the symbol in the dynamic
7315 symbol table and SYM_VALUE is undefined.
7317 ROOT_PLT points to the offset of the PLT entry from the start of its
7318 section (.iplt or .plt). ARM_PLT points to the symbol's ARM-specific
7319 bookkeeping information. */
7321 static void
7326 {
7332 bfd_vma plt_index;
7333 Elf_Internal_Rela rel;
7334 bfd_vma plt_header_size;
7335 bfd_vma got_header_size;
7339 /* Pick the appropriate sections and sizes. */
7341 {
7346 /* There are no reserved entries in .igot.plt, and no special
7347 first entry in .iplt. */
7350 }
7351 else
7352 {
7359 }
7362 /* Fill in the entry in the procedure linkage table. */
7364 {
7373 /* Fill in the entry in the .rel.plt section. */
7379 /* Get the index in the procedure linkage table which
7380 corresponds to this symbol. This is the index of this symbol
7381 in all the symbols for which we are making plt entries. The
7382 first entry in the procedure linkage table is reserved. */
7385 }
7386 else
7387 {
7394 /* Get the offset into the .(i)got.plt table of the entry that
7395 corresponds to this function. */
7398 /* Get the index in the procedure linkage table which
7399 corresponds to this symbol. This is the index of this symbol
7400 in all the symbols for which we are making plt entries.
7401 After the reserved .got.plt entries, all symbols appear in
7402 the same order as in .plt. */
7405 /* Calculate the address of the GOT entry. */
7410 /* ...and the address of the PLT entry. */
7417 {
7419 bfd_vma val;
7422 {
7430 else
7432 }
7433 }
7435 {
7437 bfd_vma val;
7440 {
7450 else
7452 }
7457 /* Create the .rela.plt.unloaded R_ARM_ABS32 relocation
7458 referencing the GOT for this PLT entry. */
7465 /* Create the R_ARM_ABS32 relocation referencing the
7466 beginning of the PLT for this GOT entry. */
7471 }
7472 else
7473 {
7474 /* Calculate the displacement between the PLT slot and the
7475 entry in the GOT. The eight-byte offset accounts for the
7476 value produced by adding to pc in the first instruction
7477 of the PLT stub. */
7483 {
7488 }
7502 #ifdef FOUR_WORD_PLT
7504 #endif
7505 }
7507 /* Fill in the entry in the .rel(a).(i)plt section. */
7511 {
7512 /* .igot.plt entries use IRELATIVE relocations against SYM_VALUE.
7513 The dynamic linker or static executable then calls SYM_VALUE
7514 to determine the correct run-time value of the .igot.plt entry. */
7517 }
7518 else
7519 {
7523 }
7525 /* Fill in the entry in the global offset table. */
7528 }
7532 }
7534 /* Some relocations map to different relocations depending on the
7535 target. Return the real relocation. */
7537 static int
7540 {
7542 {
7546 else
7554 }
7555 }
7557 /* Return the base VMA address which should be subtracted from real addresses
7558 when resolving @dtpoff relocation.
7559 This is PT_TLS segment p_vaddr. */
7561 static bfd_vma
7563 {
7564 /* If tls_sec is NULL, we should have signalled an error already. */
7568 }
7570 /* Return the relocation value for @tpoff relocation
7571 if STT_TLS virtual address is ADDRESS. */
7573 static bfd_vma
7575 {
7577 bfd_vma base;
7579 /* If tls_sec is NULL, we should have signalled an error already. */
7584 }
7586 /* Perform an R_ARM_ABS12 relocation on the field pointed to by DATA.
7587 VALUE is the relocation value. */
7589 static bfd_reloc_status_type
7591 {
7598 }
7600 /* Handle TLS relaxations. Relaxing is possible for symbols that use
7601 R_ARM_GOTDESC, R_ARM_{,THM_}TLS_CALL or
7602 R_ARM_{,THM_}TLS_DESCSEQ relocations, during a static link.
7604 Return bfd_reloc_ok if we're done, bfd_reloc_continue if the caller
7605 is to then call final_link_relocate. Return other values in the
7606 case of error.
7608 FIXME:When --emit-relocs is in effect, we'll emit relocs describing
7609 the pre-relaxed code. It would be nice if the relocs were updated
7610 to match the optimization. */
7612 static bfd_reloc_status_type
7616 {
7620 {
7627 else
7628 {
7632 else
7634 }
7639 /* Thumb insn. */
7642 {
7644 /* nop */
7646 }
7648 {
7650 /* nop */
7652 else
7653 /* ldr rx,[ry] */
7655 }
7657 {
7659 /* nop */
7661 else
7662 /* mov r0, rx */
7665 }
7666 else
7667 {
7669 /* It's a 32 bit instruction, fetch the rest of it for
7670 error generation. */
7677 }
7681 /* arm insn. */
7684 {
7686 /* mov rx, ry */
7689 }
7691 {
7693 /* nop */
7695 else
7696 /* ldr rx,[ry] */
7699 }
7701 {
7703 /* nop */
7705 else
7706 /* mov r0, rx */
7709 }
7710 else
7711 {
7716 }
7720 /* GD->IE relaxation, turn the instruction into 'nop' or
7721 'ldr r0, [pc,r0]' */
7727 /* GD->IE relaxation */
7729 /* add r0,pc; ldr r0, [r0] */
7732 /* nop.w */
7734 else
7735 /* nop; nop */
7741 }
7743 }
7745 /* For a given value of n, calculate the value of G_n as required to
7746 deal with group relocations. We return it in the form of an
7747 encoded constant-and-rotation, together with the final residual. If n is
7748 specified as less than zero, then final_residual is filled with the
7749 input value and no further action is performed. */
7751 static bfd_vma
7753 {
7755 bfd_vma g_n;
7760 {
7763 /* Calculate which part of the value to mask. */
7766 else
7767 {
7770 /* Determine the most significant bit in the residual and
7771 align the resulting value to a 2-bit boundary. */
7776 /* The desired shift is now (msb - 6), or zero, whichever
7777 is the greater. */
7781 }
7783 /* Calculate g_n in 32-bit as well as encoded constant+rotation form. */
7788 /* Calculate the residual for the next time around. */
7790 }
7795 }
7797 /* Given an ARM instruction, determine whether it is an ADD or a SUB.
7798 Returns 1 if it is an ADD, -1 if it is a SUB, and 0 otherwise. */
7800 static int
7802 {
7812 }
7814 /* Perform a relocation as part of a final link. */
7816 static bfd_reloc_status_type
7823 bfd_vma value,
7832 {
7842 bfd_vma addend;
7843 bfd_signed_vma signed_addend;
7845 bfd_vma dynreloc_value;
7850 bfd_vma plt_offset;
7851 bfd_vma gotplt_offset;
7852 bfd_boolean has_iplt_entry;
7860 /* Some relocation types map to different relocations depending on the
7861 target. We pick the right one here. */
7864 /* It is possible to have linker relaxations on some TLS access
7865 models. Update our information here. */
7871 /* If the start address has been set, then set the EF_ARM_HASENTRY
7872 flag. Setting this more than once is redundant, but the cost is
7873 not too high, and it keeps the code simple.
7875 The test is done here, rather than somewhere else, because the
7876 start address is only set just before the final link commences.
7878 Note - if the user deliberately sets a start address of 0, the
7879 flag will not be set. */
7890 else
7896 {
7900 {
7904 }
7905 else
7907 }
7908 else
7911 /* Record the symbol information that should be used in dynamic
7912 relocations. */
7918 /* Find out whether the symbol has a PLT. Set ST_VALUE, BRANCH_TYPE and
7919 VALUE appropriately for relocations that we resolve at link time. */
7923 {
7928 {
7932 /* Populate .iplt entries here, because not all of them will
7933 be seen by finish_dynamic_symbol. The lower bit is set if
7934 we have already populated the entry. */
7936 plt_offset--;
7937 else
7938 {
7942 }
7944 /* Static relocations always resolve to the .iplt entry. */
7951 /* If there are non-call relocations that resolve to the .iplt
7952 entry, then all dynamic ones must too. */
7954 {
7957 }
7958 }
7959 else
7960 /* We populate the .plt entry in finish_dynamic_symbol. */
7962 }
7963 else
7964 {
7968 }
7971 {
7973 /* We don't need to find a value for this symbol. It's just a
7974 marker. */
7992 /* Handle relocations which should use the PLT entry. ABS32/REL32
7993 will use the symbol's value, which may point to a PLT entry, but we
7994 don't need to handle that here. If we created a PLT entry, all
7995 branches in this object should go to it, except if the PLT is too
7996 far away, in which case a long branch stub should be inserted. */
8003 {
8004 /* If we've created a .plt section, and assigned a PLT entry
8005 to this function, it must either be a STT_GNU_IFUNC reference
8006 or not be known to bind locally. In other cases, we should
8007 have cleared the PLT entry by now. */
8017 }
8019 /* When generating a shared object or relocatable executable, these
8020 relocations are copied into the output file to be resolved at
8021 run time. */
8038 {
8039 Elf_Internal_Rela outrel;
8045 {
8051 }
8075 else
8076 {
8079 /* This symbol is local, or marked to become local. */
8082 {
8085 /* On Symbian OS, the data segment and text segement
8086 can be relocated independently. Therefore, we
8087 must indicate the segment to which this
8088 relocation is relative. The BPABI allows us to
8089 use any symbol in the right segment; we just use
8090 the section symbol as it is convenient. (We
8091 cannot use the symbol given by "h" directly as it
8092 will not appear in the dynamic symbol table.)
8094 Note that the dynamic linker ignores the section
8095 symbol value, so we don't subtract osec->vma
8096 from the emitted reloc addend. */
8099 else
8103 {
8109 else
8112 }
8114 }
8115 else
8116 /* On SVR4-ish systems, the dynamic loader cannot
8117 relocate the text and data segments independently,
8118 so the symbol does not matter. */
8121 /* We have an STT_GNU_IFUNC symbol that doesn't resolve
8122 to the .iplt entry. Instead, every non-call reference
8123 must use an R_ARM_IRELATIVE relocation to obtain the
8124 correct run-time address. */
8126 else
8130 else
8132 }
8136 /* If this reloc is against an external symbol, we do not want to
8137 fiddle with the addend. Otherwise, we need to include the symbol
8138 value so that it becomes an addend for the dynamic reloc. */
8145 }
8147 {
8156 {
8160 {
8161 /* Check for Arm calling Arm function. */
8162 /* FIXME: Should we translate the instruction into a BL
8163 instruction instead ? */
8167 input_bfd,
8169 }
8171 {
8172 /* Check for Arm calling Thumb function. */
8174 {
8179 error_message))
8181 else
8183 }
8184 }
8186 /* Check if a stub has to be inserted because the
8187 destination is too far or we are changing mode. */
8191 {
8202 {
8203 /* The target is out of reach, so redirect the
8204 branch to the local stub for this function. */
8209 stub_type);
8214 }
8215 else
8216 {
8217 /* If the call goes through a PLT entry, make sure to
8218 check distance to the right destination address. */
8220 {
8225 /* The PLT entry is in ARM mode, regardless of the
8226 target function. */
8228 }
8229 }
8230 }
8232 /* The ARM ELF ABI says that this reloc is computed as: S - P + A
8233 where:
8234 S is the address of the symbol in the relocation.
8235 P is address of the instruction being relocated.
8236 A is the addend (extracted from the instruction) in bytes.
8238 S is held in 'value'.
8239 P is the base address of the section containing the
8240 instruction plus the offset of the reloc into that
8241 section, ie:
8242 (input_section->output_section->vma +
8243 input_section->output_offset +
8244 rel->r_offset).
8245 A is the addend, converted into bytes, ie:
8246 (signed_addend * 4)
8248 Note: None of these operations have knowledge of the pipeline
8249 size of the processor, thus it is up to the assembler to
8250 encode this information into the addend. */
8256 else
8257 /* RELA addends do not have to be adjusted by howto->size. */
8263 /* A branch to an undefined weak symbol is turned into a jump to
8264 the next instruction unless a PLT entry will be created.
8265 Do the same for local undefined symbols (but not for STN_UNDEF).
8266 The jump to the next instruction is optimized as a NOP depending
8267 on the architecture. */
8271 {
8276 else
8278 }
8279 else
8280 {
8281 /* Perform a signed range check. */
8292 {
8293 /* Set the H bit in the BLX instruction. */
8295 {
8298 else
8300 }
8302 /* Select the correct instruction (BL or BLX). */
8303 /* Only if we are not handling a BL to a stub. In this
8304 case, mode switching is performed by the stub. */
8308 {
8311 }
8312 }
8313 }
8314 }
8346 {
8347 /* Check for overflow. */
8350 }
8356 }
8364 /* There is no way to tell whether the user intended to use a signed or
8365 unsigned addend. When checking for overflow we accept either,
8366 as specified by the AAELF. */
8376 /* See comment for R_ARM_ABS8. */
8384 /* Support ldr and str instructions for the thumb. */
8386 {
8387 /* Need to refetch addend. */
8389 /* ??? Need to determine shift amount from operand size. */
8391 }
8394 /* ??? Isn't value unsigned? */
8398 /* ??? Value needs to be properly shifted into place first. */
8404 /* Corresponds to: addw.w reg, pc, #offset (and similarly for subw). */
8405 {
8406 bfd_vma insn;
8407 bfd_signed_vma relocation;
8413 {
8418 }
8440 }
8443 /* PR 10073: This reloc is not generated by the GNU toolchain,
8444 but it is supported for compatibility with third party libraries
8445 generated by other compilers, specifically the ARM/IAR. */
8446 {
8447 bfd_vma insn;
8448 bfd_signed_vma relocation;
8462 /* We do not check for overflow of this reloc. Although strictly
8463 speaking this is incorrect, it appears to be necessary in order
8464 to work with IAR generated relocs. Since GCC and GAS do not
8465 generate R_ARM_THM_PC8 relocs, the lack of a check should not be
8466 a problem for them. */
8474 }
8477 /* Corresponds to: ldr.w reg, [pc, #offset]. */
8478 {
8479 bfd_vma insn;
8480 bfd_signed_vma relocation;
8486 {
8490 }
8510 }
8515 /* Thumb BL (branch long instruction). */
8516 {
8517 bfd_vma relocation;
8518 bfd_vma reloc_sign;
8522 bfd_signed_vma reloc_signed_max;
8523 bfd_signed_vma reloc_signed_min;
8524 bfd_vma check;
8525 bfd_signed_vma signed_check;
8529 /* A branch to an undefined weak symbol is turned into a jump to
8530 the next instruction unless a PLT entry will be created.
8531 The jump to the next instruction is optimized as a NOP.W for
8532 Thumb-2 enabled architectures. */
8535 {
8537 {
8540 }
8541 else
8542 {
8545 }
8547 }
8549 /* Fetch the addend. We use the Thumb-2 encoding (backwards compatible
8550 with Thumb-1) involving the J1 and J2 bits. */
8552 {
8562 /* Sign extend. */
8566 }
8569 {
8570 /* Check for Thumb to Thumb call. */
8571 /* FIXME: Should we translate the instruction into a BL
8572 instruction instead ? */
8576 input_bfd,
8578 }
8579 else
8580 {
8581 /* If it is not a call to Thumb, assume call to Arm.
8582 If it is a call relative to a section name, then it is not a
8583 function call at all, but rather a long jump. Calls through
8584 the PLT do not require stubs. */
8586 {
8588 {
8589 /* Convert BL to BLX. */
8591 }
8594 {
8598 error_message))
8600 else
8602 }
8603 }
8607 {
8608 /* Make sure this is a BL. */
8610 }
8611 }
8615 {
8616 /* Check if a stub has to be inserted because the destination
8617 is too far. */
8629 {
8630 /* The target is out of reach or we are changing modes, so
8631 redirect the branch to the local stub for this
8632 function. */
8636 stub_type);
8642 /* If this call becomes a call to Arm, force BLX. */
8644 {
8649 }
8650 }
8651 }
8653 /* Handle calls via the PLT. */
8655 {
8661 {
8662 /* If the Thumb BLX instruction is available, convert
8663 the BL to a BLX instruction to call the ARM-mode
8664 PLT entry. */
8667 }
8668 else
8669 {
8670 /* Target the Thumb stub before the ARM PLT entry. */
8673 }
8675 }
8685 /* If this is a signed value, the rightshift just dropped
8686 leading 1 bits (assuming twos complement). */
8689 else
8692 /* Calculate the permissable maximum and minimum values for
8693 this relocation according to whether we're relocating for
8694 Thumb-2 or not. */
8701 /* Assumes two's complement. */
8706 /* For a BLX instruction, make sure that the relocation is rounded up
8707 to a word boundary. This follows the semantics of the instruction
8708 which specifies that bit 1 of the target address will come from bit
8709 1 of the base address. */
8712 /* Put RELOCATION back into the insn. Assumes two's complement.
8713 We use the Thumb-2 encoding, which is safe even if dealing with
8714 a Thumb-1 instruction by virtue of our overflow check above. */
8724 /* Put the relocated value back in the object file: */
8729 }
8733 /* Thumb32 conditional branch instruction. */
8734 {
8735 bfd_vma relocation;
8741 bfd_signed_vma signed_check;
8743 /* Need to refetch the addend, reconstruct the top three bits,
8744 and squish the two 11 bit pieces together. */
8746 {
8760 }
8762 /* Handle calls via the PLT. */
8764 {
8768 /* Target the Thumb stub before the ARM PLT entry. */
8771 }
8773 /* ??? Should handle interworking? GCC might someday try to
8774 use this for tail calls. */
8785 /* Put RELOCATION back into the insn. */
8786 {
8795 }
8797 /* Put the relocated value back in the object file: */
8802 }
8807 /* Thumb B (branch) instruction). */
8808 {
8809 bfd_signed_vma relocation;
8812 bfd_signed_vma signed_check;
8814 /* CZB cannot jump backward. */
8819 {
8820 /* Need to refetch addend. */
8823 {
8827 }
8828 else
8830 /* The value in the insn has been right shifted. We need to
8831 undo this, so that we can perform the address calculation
8832 in terms of bytes. */
8834 }
8846 else
8852 /* Assumes two's complement. */
8857 }
8862 {
8863 bfd_vma insn;
8864 bfd_vma relocation;
8868 {
8869 /* Extract the addend. */
8872 }
8882 }
8890 /* Relocation is relative to the start of the
8891 global offset table. */
8897 /* If we are addressing a Thumb function, we need to adjust the
8898 address by one, so that attempts to call the function pointer will
8899 correctly interpret it as Thumb code. */
8903 /* Note that sgot->output_offset is not involved in this
8904 calculation. We always want the start of .got. If we
8905 define _GLOBAL_OFFSET_TABLE in a different way, as is
8906 permitted by the ABI, we might have to change this
8907 calculation. */
8914 /* Use global offset table as symbol value. */
8928 /* Relocation is to the entry for this symbol in the
8929 global offset table. */
8936 {
8937 /* We have a relocation against a locally-binding STT_GNU_IFUNC
8938 symbol, and the relocation resolves directly to the runtime
8939 target rather than to the .iplt entry. This means that any
8940 .got entry would be the same value as the .igot.plt entry,
8941 so there's no point creating both. */
8944 }
8946 {
8947 bfd_vma off;
8952 {
8953 /* We have already processsed one GOT relocation against
8954 this symbol. */
8959 }
8960 else
8961 {
8962 Elf_Internal_Rela outrel;
8965 {
8966 /* If the symbol doesn't resolve locally in a static
8967 object, we have an undefined reference. If the
8968 symbol doesn't resolve locally in a dynamic object,
8969 it should be resolved by the dynamic linker. */
8971 {
8974 }
8975 else
8978 }
8979 else
8980 {
8985 else
8988 }
8990 /* The GOT entry is initialized to zero by default.
8991 See if we should install a different value. */
8994 {
8998 }
9001 {
9006 }
9008 }
9010 }
9011 else
9012 {
9013 bfd_vma off;
9020 /* The offset must always be a multiple of 4. We use the
9021 least significant bit to record whether we have already
9022 generated the necessary reloc. */
9025 else
9026 {
9031 {
9032 Elf_Internal_Rela outrel;
9040 else
9043 }
9046 }
9049 }
9065 {
9066 bfd_vma off;
9075 else
9076 {
9077 /* If we don't know the module number, create a relocation
9078 for it. */
9080 {
9081 Elf_Internal_Rela outrel;
9096 }
9097 else
9101 }
9109 }
9118 {
9126 {
9127 bfd_boolean dyn;
9132 {
9135 }
9139 }
9140 else
9141 {
9146 }
9148 /* Linker relaxations happens from one of the
9149 R_ARM_{GOTDESC,CALL,DESCSEQ} relocations to IE or LE. */
9157 else
9158 {
9160 Elf_Internal_Rela outrel;
9163 /* The GOT entries have not been initialized yet. Do it
9164 now, and emit any relocations. If both an IE GOT and a
9165 GD GOT are necessary, we emit the GD first. */
9171 {
9174 }
9177 {
9180 /* We should have relaxed, unless this is an undefined
9181 weak symbol. */
9190 + offplt
9202 /* For globals, the first word in the relocation gets
9203 the relocation index and the top bit set, or zero,
9204 if we're binding now. For locals, it gets the
9205 symbol's offset in the tls section. */
9213 /* Second word in the relocation is always zero. */
9217 }
9219 {
9221 {
9237 else
9238 {
9241 R_ARM_TLS_DTPOFF32);
9250 }
9251 }
9252 else
9253 {
9254 /* If we are not emitting relocations for a
9255 general dynamic reference, then we must be in a
9256 static link or an executable link with the
9257 symbol binding locally. Mark it as belonging
9258 to module 1, the executable. */
9263 }
9266 }
9269 {
9271 {
9274 else
9286 }
9287 else
9291 }
9295 else
9297 }
9306 {
9307 bfd_signed_vma offset;
9308 /* TLS stubs are arm mode. The original symbol is a
9309 data object, so branch_type is bogus. */
9311 enum elf32_arm_stub_type stub_type
9319 {
9321 = elf32_arm_get_stub_entry
9327 }
9328 else
9334 {
9343 }
9344 else
9345 {
9346 /* Thumb blx encodes the offset in a complicated
9347 fashion. */
9352 input_section->output_offset
9357 {
9359 }
9360 else
9361 {
9363 /* Round up the offset to a word boundary */
9365 }
9377 }
9378 }
9379 /* These relocations needs special care, as besides the fact
9380 they point somewhere in .gotplt, the addend must be
9381 adjusted accordingly depending on the type of instruction
9382 we refer to */
9384 {
9393 {
9400 /* bl/blx */
9403 /* add */
9405 else
9406 {
9412 }
9413 }
9414 else
9415 {
9419 {
9435 }
9436 }
9444 }
9445 else
9454 }
9458 {
9464 }
9465 else
9474 {
9477 /* Ensure that we have a BX instruction. */
9481 {
9482 /* Branch to veneer. */
9483 bfd_vma glue_addr;
9490 }
9491 else
9492 {
9493 /* Preserve Rm (lowest four bits) and the condition code
9494 (highest four bits). Other bits encode MOV PC,Rm. */
9496 }
9499 }
9506 /* Until we properly support segment-base-relative addressing then
9507 we assume the segment base to be zero, as for the group relocations.
9508 Thus R_ARM_MOVW_BREL_NC has the same semantics as R_ARM_MOVW_ABS_NC
9509 and R_ARM_MOVT_BREL has the same semantics as R_ARM_MOVT_ABS. */
9513 {
9517 {
9520 }
9542 }
9549 /* Until we properly support segment-base-relative addressing then
9550 we assume the segment base to be zero, as for the above relocations.
9551 Thus R_ARM_THM_MOVW_BREL_NC has the same semantics as
9552 R_ARM_THM_MOVW_ABS_NC and R_ARM_THM_MOVT_BREL has the same semantics
9553 as R_ARM_THM_MOVT_ABS. */
9557 {
9558 bfd_vma insn;
9564 {
9570 }
9596 }
9609 {
9613 /* sb should be the origin of the *segment* containing the symbol.
9614 It is not clear how to obtain this OS-dependent value, so we
9615 make an arbitrary choice of zero. */
9617 bfd_vma residual;
9618 bfd_vma g_n;
9619 bfd_signed_vma signed_value;
9622 /* Determine which group of bits to select. */
9624 {
9646 }
9648 /* If REL, extract the addend from the insn. If RELA, it will
9649 have already been fetched for us. */
9651 {
9658 else
9659 {
9660 /* Compensate for the fact that in the instruction, the
9661 rotation is stored in multiples of 2 bits. */
9664 /* Rotate "constant" right by "rotation" bits. */
9667 }
9669 /* Determine if the instruction is an ADD or a SUB.
9670 (For REL, this determines the sign of the addend.) */
9673 {
9679 }
9682 }
9684 /* Compute the value (X) to go in the place. */
9690 /* PC relative. */
9692 else
9693 /* Section base relative. */
9696 /* If the target symbol is a Thumb function, then set the
9697 Thumb bit in the address. */
9701 /* Calculate the value of the relevant G_n, in encoded
9702 constant-with-rotation format. */
9706 /* Check for overflow if required. */
9713 {
9719 }
9721 /* Mask out the value and the ADD/SUB part of the opcode; take care
9722 not to destroy the S bit. */
9725 /* Set the opcode according to whether the value to go in the
9726 place is negative. */
9729 else
9732 /* Encode the offset. */
9736 }
9745 {
9750 bfd_vma residual;
9751 bfd_signed_vma signed_value;
9754 /* Determine which groups of bits to calculate. */
9756 {
9774 }
9776 /* If REL, extract the addend from the insn. If RELA, it will
9777 have already been fetched for us. */
9779 {
9782 }
9784 /* Compute the value (X) to go in the place. */
9788 /* PC relative. */
9790 else
9791 /* Section base relative. */
9794 /* Calculate the value of the relevant G_{n-1} to obtain
9795 the residual at that stage. */
9798 /* Check for overflow. */
9800 {
9806 }
9808 /* Mask out the value and U bit. */
9811 /* Set the U bit if the value to go in the place is non-negative. */
9815 /* Encode the offset. */
9819 }
9828 {
9833 bfd_vma residual;
9834 bfd_signed_vma signed_value;
9837 /* Determine which groups of bits to calculate. */
9839 {
9857 }
9859 /* If REL, extract the addend from the insn. If RELA, it will
9860 have already been fetched for us. */
9862 {
9865 }
9867 /* Compute the value (X) to go in the place. */
9871 /* PC relative. */
9873 else
9874 /* Section base relative. */
9877 /* Calculate the value of the relevant G_{n-1} to obtain
9878 the residual at that stage. */
9881 /* Check for overflow. */
9883 {
9889 }
9891 /* Mask out the value and U bit. */
9894 /* Set the U bit if the value to go in the place is non-negative. */
9898 /* Encode the offset. */
9902 }
9911 {
9916 bfd_vma residual;
9917 bfd_signed_vma signed_value;
9920 /* Determine which groups of bits to calculate. */
9922 {
9940 }
9942 /* If REL, extract the addend from the insn. If RELA, it will
9943 have already been fetched for us. */
9945 {
9948 }
9950 /* Compute the value (X) to go in the place. */
9954 /* PC relative. */
9956 else
9957 /* Section base relative. */
9960 /* Calculate the value of the relevant G_{n-1} to obtain
9961 the residual at that stage. */
9964 /* Check for overflow. (The absolute value to go in the place must be
9965 divisible by four and, after having been divided by four, must
9966 fit in eight bits.) */
9968 {
9974 }
9976 /* Mask out the value and U bit. */
9979 /* Set the U bit if the value to go in the place is non-negative. */
9983 /* Encode the offset. */
9987 }
9992 }
9993 }
9995 /* Add INCREMENT to the reloc (of type HOWTO) at ADDRESS. */
9996 static void
10000 bfd_signed_vma increment)
10001 {
10002 bfd_signed_vma addend;
10006 {
10024 }
10025 else
10026 {
10027 bfd_vma contents;
10031 /* Get the (signed) value from the instruction. */
10034 {
10035 bfd_signed_vma mask;
10040 }
10042 /* Add in the increment, (which is a byte value). */
10044 {
10056 /* Should we check for overflow here ? */
10058 /* Drop any undesired bits. */
10061 }
10066 }
10067 }
10069 #define IS_ARM_TLS_RELOC(R_TYPE) \
10070 ((R_TYPE) == R_ARM_TLS_GD32 \
10071 || (R_TYPE) == R_ARM_TLS_LDO32 \
10072 || (R_TYPE) == R_ARM_TLS_LDM32 \
10073 || (R_TYPE) == R_ARM_TLS_DTPOFF32 \
10074 || (R_TYPE) == R_ARM_TLS_DTPMOD32 \
10075 || (R_TYPE) == R_ARM_TLS_TPOFF32 \
10076 || (R_TYPE) == R_ARM_TLS_LE32 \
10077 || (R_TYPE) == R_ARM_TLS_IE32 \
10078 || IS_ARM_TLS_GNU_RELOC (R_TYPE))
10080 /* Specific set of relocations for the gnu tls dialect. */
10081 #define IS_ARM_TLS_GNU_RELOC(R_TYPE) \
10082 ((R_TYPE) == R_ARM_TLS_GOTDESC \
10083 || (R_TYPE) == R_ARM_TLS_CALL \
10084 || (R_TYPE) == R_ARM_THM_TLS_CALL \
10085 || (R_TYPE) == R_ARM_TLS_DESCSEQ \
10086 || (R_TYPE) == R_ARM_THM_TLS_DESCSEQ)
10088 /* Relocate an ARM ELF section. */
10090 static bfd_boolean
10099 {
10117 {
10124 bfd_vma relocation;
10125 bfd_reloc_status_type r;
10126 arelent bfd_reloc;
10147 {
10152 /* An object file might have a reference to a local
10153 undefined symbol. This is a daft object file, but we
10154 should at least do something about it. V4BX & NONE
10155 relocations do not use the symbol and are explicitly
10156 allowed to use the undefined symbol, so allow those.
10157 Likewise for relocations against STN_UNDEF. */
10163 {
10170 }
10173 {
10180 {
10185 {
10207 {
10213 }
10217 /* Get the (signed) value from the instruction. */
10220 {
10221 bfd_signed_vma mask;
10226 }
10228 }
10231 addend =
10236 /* Cases here must match those in the preceding
10237 switch statement. */
10239 {
10262 }
10263 }
10264 }
10265 else
10267 }
10268 else
10269 {
10270 bfd_boolean warned;
10278 }
10285 {
10286 /* This is a relocatable link. We don't have to change
10287 anything, unless the reloc is against a section symbol,
10288 in which case we have to adjust according to where the
10289 section symbol winds up in the output section. */
10291 {
10295 else
10297 }
10299 }
10303 else
10304 {
10305 name = (bfd_elf_string_from_elf_section
10309 }
10317 {
10322 input_bfd,
10323 input_section,
10326 name);
10327 }
10329 /* We call elf32_arm_final_link_relocate unless we're completely
10330 done, i.e., the relaxation produced the final output we want,
10331 and we won't let anybody mess with it. Also, we have to do
10332 addend adjustments in case of a R_ARM_TLS_GOTDESC relocation
10333 both in relaxed and non-relaxed cases */
10339 {
10342 /* This may have been marked unresolved because it came from
10343 a shared library. But we've just dealt with that. */
10345 }
10346 else
10357 /* Dynamic relocs are not propagated for SEC_DEBUGGING sections
10358 because such sections are not SEC_ALLOC and thus ld.so will
10359 not process them. */
10363 {
10366 input_bfd,
10367 input_section,
10372 }
10375 {
10377 {
10379 /* If the overflowing reloc was to an undefined symbol,
10380 we have already printed one error message and there
10381 is no point complaining again. */
10407 /* error_message should already be set. */
10412 /* Fall through. */
10414 common_error:
10421 }
10422 }
10423 }
10426 }
10428 /* Add a new unwind edit to the list described by HEAD, TAIL. If TINDEX is zero,
10429 adds the edit to the start of the list. (The list must be built in order of
10430 ascending TINDEX: the function's callers are primarily responsible for
10431 maintaining that condition). */
10433 static void
10436 arm_unwind_edit_type type,
10439 {
10448 {
10458 }
10459 else
10460 {
10467 }
10468 }
10472 /* Increase the size of EXIDX_SEC by ADJUST bytes. ADJUST mau be negative. */
10473 static void
10475 {
10483 /* Adjust size of output section. */
10485 }
10487 /* Insert an EXIDX_CANTUNWIND marker at the end of a section. */
10488 static void
10490 {
10500 }
10502 /* Scan .ARM.exidx tables, and create a list describing edits which should be
10503 made to those tables, such that:
10505 1. Regions without unwind data are marked with EXIDX_CANTUNWIND entries.
10506 2. Duplicate entries are merged together (EXIDX_CANTUNWIND, or unwind
10507 codes which have been inlined into the index).
10509 If MERGE_EXIDX_ENTRIES is false, duplicate entries are not merged.
10511 The edits are applied when the tables are written
10512 (in elf32_arm_write_section).
10513 */
10515 bfd_boolean
10519 bfd_boolean merge_exidx_entries)
10520 {
10527 /* Walk over all EXIDX sections, and create backlinks from the corrsponding
10528 text sections. */
10530 {
10534 {
10542 {
10543 Elf_Internal_Shdr *linked_hdr
10551 /* Link this .ARM.exidx section back from the text section it
10552 describes. */
10554 }
10555 }
10556 }
10558 /* Walk all text sections in order of increasing VMA. Eilminate duplicate
10559 index table entries (EXIDX_CANTUNWIND and inlined unwind opcodes),
10560 and add EXIDX_CANTUNWIND entries for sections with no unwind table data. */
10563 {
10570 bfd_vma j;
10581 {
10582 /* Section has no unwind data. */
10586 /* Ignore zero sized sections. */
10593 }
10595 /* Skip /DISCARD/ sections. */
10612 /* An error? */
10616 {
10621 /* An EXIDX_CANTUNWIND entry. */
10623 {
10627 }
10628 /* Inlined unwinding data. Merge if equal to previous. */
10630 {
10636 }
10637 /* Normal table entry. In theory we could merge these too,
10638 but duplicate entries are likely to be much less common. */
10639 else
10643 {
10648 }
10651 }
10653 /* Free contents if we allocated it ourselves. */
10657 /* Record edits to be applied later (in elf32_arm_write_section). */
10666 }
10668 /* Add terminating CANTUNWIND entry. */
10673 }
10675 static bfd_boolean
10678 {
10694 }
10696 static bfd_boolean
10698 {
10705 /* Invoke the regular ELF backend linker to do all the work. */
10709 /* Process stub sections (eg BE8 encoding, ...). */
10713 {
10715 /* Only process it once, in its link_sec slot. */
10717 {
10723 }
10724 }
10726 /* Write out any glue sections now that we have created all the
10727 stubs. */
10729 {
10732 ARM2THUMB_GLUE_SECTION_NAME))
10737 THUMB2ARM_GLUE_SECTION_NAME))
10742 VFP11_ERRATUM_VENEER_SECTION_NAME))
10747 ARM_BX_GLUE_SECTION_NAME))
10749 }
10752 }
10754 /* Set the right machine number. */
10756 static bfd_boolean
10758 {
10769 else
10773 }
10775 /* Function to keep ARM specific flags in the ELF header. */
10777 static bfd_boolean
10779 {
10782 {
10784 {
10787 (_("Warning: Not setting interworking flag of %B since it has already been specified as non-interworking"),
10788 abfd);
10789 else
10790 _bfd_error_handler
10792 abfd);
10793 }
10794 }
10795 else
10796 {
10799 }
10802 }
10804 /* Copy backend specific data from one object module to another. */
10806 static bfd_boolean
10808 {
10809 flagword in_flags;
10810 flagword out_flags;
10821 {
10822 /* Cannot mix APCS26 and APCS32 code. */
10826 /* Cannot mix float APCS and non-float APCS code. */
10830 /* If the src and dest have different interworking flags
10831 then turn off the interworking bit. */
10833 {
10835 _bfd_error_handler
10836 (_("Warning: Clearing the interworking flag of %B because non-interworking code in %B has been linked with it"),
10840 }
10842 /* Likewise for PIC, though don't warn for this case. */
10845 }
10850 /* Also copy the EI_OSABI field. */
10854 /* Copy object attributes. */
10858 }
10860 /* Values for Tag_ABI_PCS_R9_use. */
10861 enum
10862 {
10863 AEABI_R9_V6,
10864 AEABI_R9_SB,
10865 AEABI_R9_TLS,
10866 AEABI_R9_unused
10867 };
10869 /* Values for Tag_ABI_PCS_RW_data. */
10870 enum
10871 {
10872 AEABI_PCS_RW_data_absolute,
10873 AEABI_PCS_RW_data_PCrel,
10874 AEABI_PCS_RW_data_SBrel,
10875 AEABI_PCS_RW_data_unused
10876 };
10878 /* Values for Tag_ABI_enum_size. */
10879 enum
10880 {
10881 AEABI_enum_unused,
10882 AEABI_enum_short,
10883 AEABI_enum_wide,
10884 AEABI_enum_forced_wide
10885 };
10887 /* Determine whether an object attribute tag takes an integer, a
10888 string or both. */
10890 static int
10892 {
10901 else
10903 }
10905 /* The ABI defines that Tag_conformance should be emitted first, and that
10906 Tag_nodefaults should be second (if either is defined). This sets those
10907 two positions, and bumps up the position of all the remaining tags to
10908 compensate. */
10909 static int
10911 {
10921 }
10923 /* Attribute numbers >=64 (mod 128) can be safely ignored. */
10924 static bfd_boolean
10926 {
10928 {
10929 _bfd_error_handler
10934 }
10935 else
10936 {
10937 _bfd_error_handler
10941 }
10942 }
10944 /* Read the architecture from the Tag_also_compatible_with attribute, if any.
10945 Returns -1 if no architecture could be read. */
10947 static int
10949 {
10953 /* Note: the tag and its argument below are uleb128 values, though
10954 currently-defined values fit in one byte for each. */
10961 /* This tag is "safely ignorable", so don't complain if it looks funny. */
10963 }
10965 /* Set, or unset, the architecture of the Tag_also_compatible_with attribute.
10966 The tag is removed if ARCH is -1. */
10968 static void
10970 {
10975 {
10978 }
10980 /* Note: the tag and its argument below are uleb128 values, though
10981 currently-defined values fit in one byte for each. */
10987 }
10989 /* Combine two values for Tag_CPU_arch, taking secondary compatibility tags
10990 into account. */
10992 static int
10995 {
10996 #define T(X) TAG_CPU_ARCH_##X
10999 {
11009 };
11011 {
11022 };
11024 {
11036 };
11038 {
11051 };
11053 {
11067 };
11069 {
11084 };
11086 {
11102 };
11104 {
11105 v6t2,
11106 v6k,
11107 v7,
11108 v6_m,
11109 v6s_m,
11110 v7e_m,
11111 /* Pseudo-architecture. */
11112 v4t_plus_v6_m
11113 };
11115 /* Check we've not got a higher architecture than we know about. */
11118 {
11121 }
11123 /* Override old tag if we have a Tag_also_compatible_with on the output. */
11129 /* And override the new tag if we have a Tag_also_compatible_with on the
11130 input. */
11139 /* Architectures before V6KZ add features monotonically. */
11145 /* Use Tag_CPU_arch == V4T and Tag_also_compatible_with (Tag_CPU_arch V6_M)
11146 as the canonical version. */
11148 {
11151 }
11152 else
11156 {
11160 }
11163 #undef T
11164 }
11166 /* Merge EABI object attributes from IBFD into OBFD. Raise an error if there
11167 are conflicting attributes. */
11169 static bfd_boolean
11171 {
11174 /* Some tags have 0 = don't care, 1 = strong requirement,
11175 2 = weak requirement. */
11180 /* Skip the linker stubs file. This preserves previous behavior
11181 of accepting unknown attributes in the first input file - but
11182 is that a bug? */
11187 {
11188 /* This is the first object. Copy the attributes. */
11193 /* Use the Tag_null value to indicate the attributes have been
11194 initialized. */
11197 /* We do not output objects with Tag_MPextension_use_legacy - we move
11198 the attribute's value to Tag_MPextension_use. */
11200 {
11204 {
11205 _bfd_error_handler
11209 }
11215 }
11218 }
11222 /* This needs to happen before Tag_ABI_FP_number_model is merged. */
11224 {
11225 /* Ignore mismatches if the object doesn't use floating point. */
11229 {
11230 _bfd_error_handler
11235 }
11236 }
11239 {
11240 /* Merge this attribute with existing attributes. */
11242 {
11245 /* These are merged after Tag_CPU_arch. */
11250 /* Use the first value seen. */
11254 {
11258 /* These aren't real CPU names, but we can't guess
11259 that from the architecture version alone. */
11272 "ARM v6S-M"
11273 };
11275 /* Merge Tag_CPU_arch and Tag_also_compatible_with. */
11281 secondary_compat);
11284 /* Merge Tag_CPU_name and Tag_CPU_raw_name. */
11288 {
11289 /* The output architecture has been changed to match the
11290 input architecture. Use the input names. */
11297 }
11298 else
11299 {
11302 }
11304 /* If we still don't have a value for Tag_CPU_name,
11305 make one up now. Tag_CPU_raw_name remains blank. */
11310 }
11317 /* ??? Do Advanced_SIMD (NEON) and WMMX conflict? */
11326 /* Use the largest value specified. */
11333 /* Use the smallest value specified. */
11342 {
11343 /* This error message should be enabled once all non-conformant
11344 binaries in the toolchain have had the attributes set
11345 properly.
11346 _bfd_error_handler
11347 (_("error: %B: 8-byte data alignment conflicts with %B"),
11348 obfd, ibfd);
11349 result = FALSE; */
11350 }
11351 /* Fall through. */
11354 /* Use the "greatest" from the sequence 0, 2, 1, or the largest
11355 value if greater than 2 (for future-proofing). */
11363 /* The virtualization tag effectively stores two bits of
11364 information: the intended use of TrustZone (in bit 0), and the
11365 intended use of Virtualization (in bit 1). */
11370 {
11373 else
11374 {
11375 _bfd_error_handler
11380 }
11381 }
11386 {
11387 /* 0 will merge with anything.
11388 'A' and 'S' merge to 'A'.
11389 'R' and 'S' merge to 'R'.
11390 'M' and 'A|R|S' is an error. */
11399 else
11400 {
11401 _bfd_error_handler
11403 ibfd,
11407 }
11408 }
11411 {
11412 /* Tag_ABI_HardFP_use is handled along with Tag_FP_arch since
11413 the meaning of Tag_ABI_HardFP_use depends on Tag_FP_arch
11414 when it's 0. It might mean absence of FP hardware if
11415 Tag_FP_arch is zero, otherwise it is effectively SP + DP. */
11417 static const struct
11418 {
11422 {
11430 };
11435 /* If the output has no requirement about FP hardware,
11436 follow the requirement of the input. */
11438 {
11444 }
11445 /* If the input has no requirement about FP hardware, do
11446 nothing. */
11448 {
11451 }
11453 /* Both the input and the output have nonzero Tag_FP_arch.
11454 So Tag_ABI_HardFP_use is (SP & DP) when it's zero. */
11456 /* If both the input and the output have zero Tag_ABI_HardFP_use,
11457 do nothing. */
11460 ;
11461 /* If the input and the output have different Tag_ABI_HardFP_use,
11462 the combination of them is 3 (SP & DP). */
11467 /* Now we can handle Tag_FP_arch. */
11469 /* Values greater than 6 aren't defined, so just pick the
11470 biggest */
11472 {
11475 }
11476 /* The output uses the superset of input features
11477 (ISA version) and registers. */
11484 /* This assumes all possible supersets are also a valid
11485 options. */
11487 {
11491 }
11493 }
11499 {
11500 /* It's sometimes ok to mix different configs, so this is only
11501 a warning. */
11502 _bfd_error_handler
11504 }
11510 {
11511 _bfd_error_handler
11514 }
11522 {
11523 _bfd_error_handler
11525 ibfd);
11527 }
11528 /* Use the smallest value specified. */
11535 {
11536 _bfd_error_handler
11537 (_("warning: %B uses %u-byte wchar_t yet the output is to use %u-byte wchar_t; use of wchar_t values across objects may fail"),
11539 }
11545 {
11548 {
11549 /* The existing object is compatible with anything.
11550 Use whatever requirements the new object has. */
11552 }
11556 {
11567 _bfd_error_handler
11568 (_("warning: %B uses %s enums yet the output is to use %s enums; use of enum values across objects may fail"),
11570 }
11571 }
11574 /* Aready done. */
11578 {
11579 _bfd_error_handler
11583 }
11586 /* Merged in target-independent code. */
11589 /* This is handled along with Tag_FP_arch. */
11593 {
11595 {
11596 _bfd_error_handler
11600 }
11601 }
11607 /* This tag is set to zero if we can use UDIV and SDIV in Thumb
11608 mode on a v7-M or v7-R CPU; to one if we can not use UDIV or
11609 SDIV at all; and to two if we can use UDIV or SDIV on a v7-A
11610 CPU. We will merge as follows: If the input attribute's value
11611 is one then the output attribute's value remains unchanged. If
11612 the input attribute's value is zero or two then if the output
11613 attribute's value is one the output value is set to the input
11614 value, otherwise the output value must be the same as the
11615 inputs. */
11617 {
11619 {
11620 _bfd_error_handler
11624 }
11625 }
11633 /* We don't output objects with Tag_MPextension_use_legacy - we
11634 move the value to Tag_MPextension_use. */
11636 {
11638 {
11639 _bfd_error_handler
11642 ibfd);
11644 }
11645 }
11653 /* This tag is set if it exists, but the value is unused (and is
11654 typically zero). We don't actually need to do anything here -
11655 the merge happens automatically when the type flags are merged
11656 below. */
11659 /* Already done in Tag_CPU_arch. */
11662 /* Keep the attribute if it matches. Throw it away otherwise.
11663 No attribute means no claim to conform. */
11670 result
11672 }
11674 /* If out_attr was copied from in_attr then it won't have a type yet. */
11677 }
11679 /* Merge Tag_compatibility attributes and any common GNU ones. */
11683 /* Check for any attributes not known on ARM. */
11687 }
11690 /* Return TRUE if the two EABI versions are incompatible. */
11692 static bfd_boolean
11694 {
11695 /* v4 and v5 are the same spec before and after it was released,
11696 so allow mixing them. */
11702 }
11704 /* Merge backend specific data from an object file to the output
11705 object file when linking. */
11707 static bfd_boolean
11710 /* Display the flags field. */
11712 static bfd_boolean
11714 {
11720 /* Print normal ELF private data. */
11724 /* Ignore init flag - it may not be set, despite the flags field
11725 containing valid data. */
11727 /* xgettext:c-format */
11731 {
11733 /* The following flag bits are GNU extensions and not part of the
11734 official ARM ELF extended ABI. Hence they are only decoded if
11735 the EABI version is not set. */
11741 else
11748 else
11777 else
11788 else
11811 eabi:
11824 }
11842 }
11844 static int
11846 {
11848 {
11853 /* If the symbol is not an object, return the STT_ARM_16BIT flag.
11854 This allows us to distinguish between data used by Thumb instructions
11855 and non-data (which is probably code) inside Thumb regions of an
11856 executable. */
11863 }
11866 }
11874 {
11877 {
11881 }
11884 }
11886 /* Update the got entry reference counts for the section being removed. */
11888 static bfd_boolean
11893 {
11917 {
11922 bfd_boolean call_reloc_p;
11923 bfd_boolean may_become_dynamic_p;
11924 bfd_boolean may_need_local_target_p;
11930 {
11935 }
11945 {
11951 {
11954 }
11956 {
11959 }
11980 {
11983 }
11984 /* Fall through. */
11997 /* Should the interworking branches be here also? */
12000 {
12003 {
12006 }
12007 else
12009 }
12010 else
12016 }
12020 {
12033 }
12036 {
12042 else
12043 {
12053 }
12056 {
12057 /* Everything must go for SEC. */
12060 }
12061 }
12062 }
12065 }
12067 /* Look through the relocs for a section during the first phase. */
12069 static bfd_boolean
12072 {
12080 bfd_boolean call_reloc_p;
12081 bfd_boolean may_become_dynamic_p;
12082 bfd_boolean may_need_local_target_p;
12096 /* Create dynamic sections for relocatable executables so that we can
12097 copy relocations. */
12100 {
12103 }
12118 {
12130 /* PR 9934: It is possible to have relocations that do not
12131 refer to symbols, thus it is also possible to have an
12132 object file containing relocations but no symbol table. */
12134 {
12136 r_symndx);
12138 }
12143 {
12145 {
12146 /* A local symbol. */
12151 }
12152 else
12153 {
12158 }
12159 }
12167 /* Could be done earlier, if h were already available. */
12170 {
12180 /* This symbol requires a global offset table entry. */
12181 {
12185 {
12196 }
12199 {
12202 }
12203 else
12204 {
12205 /* This is a global offset table entry for a local symbol. */
12210 }
12212 /* If a variable is accessed with both tls methods, two
12213 slots may be created. */
12218 /* We will already have issued an error message if there
12219 is a TLS/non-TLS mismatch, based on the symbol
12220 type. So just combine any TLS types needed. */
12225 /* If the symbol is accessed in both IE and GDESC
12226 method, we're able to relax. Turn off the GDESC flag,
12227 without messing up with any other kind of tls types
12228 that may be involved */
12233 {
12236 else
12238 }
12239 }
12240 /* Fall through. */
12245 /* Fall through. */
12267 /* VxWorks uses dynamic R_ARM_ABS12 relocations for
12268 ldr __GOTT_INDEX__ offsets. */
12270 {
12273 }
12274 /* Fall through. */
12281 {
12283 (_("%B: relocation %s against `%s' can not be used when making a shared object; recompile with -fPIC"),
12288 }
12290 /* Fall through. */
12300 /* Should the interworking branches be listed here? */
12303 {
12306 {
12307 /* In shared libraries and relocatable executables,
12308 we treat local relative references as calls;
12309 see the related SYMBOL_CALLS_LOCAL code in
12310 allocate_dynrelocs. */
12313 }
12314 else
12315 /* We are creating a shared library or relocatable
12316 executable, and this is a reloc against a global symbol,
12317 or a non-PC-relative reloc against a local symbol.
12318 We may need to copy the reloc into the output. */
12320 }
12321 else
12325 /* This relocation describes the C++ object vtable hierarchy.
12326 Reconstruct it for later use during GC. */
12332 /* This relocation describes which C++ vtable entries are actually
12333 used. Record for later use during GC. */
12340 }
12343 {
12345 /* We may need a .plt entry if the function this reloc
12346 refers to is in a different object, regardless of the
12347 symbol's type. We can't tell for sure yet, because
12348 something later might force the symbol local. */
12351 /* If this reloc is in a read-only section, we might
12352 need a copy reloc. We can't check reliably at this
12353 stage whether the section is read-only, as input
12354 sections have not yet been mapped to output sections.
12355 Tentatively set the flag for now, and correct in
12356 adjust_dynamic_symbol. */
12358 }
12362 {
12368 {
12371 }
12372 else
12373 {
12379 }
12381 /* If the symbol is a function that doesn't bind locally,
12382 this relocation will need a PLT entry. */
12388 /* It's too early to use htab->use_blx here, so we have to
12389 record possible blx references separately from
12390 relocs that definitely need a thumb stub. */
12398 }
12401 {
12404 /* Create a reloc section in dynobj. */
12406 {
12407 sreloc = _bfd_elf_make_dynamic_reloc_section
12413 /* BPABI objects never have dynamic relocations mapped. */
12415 {
12416 flagword flags;
12421 }
12422 }
12424 /* If this is a global symbol, count the number of
12425 relocations we need for this symbol. */
12428 else
12429 {
12433 }
12437 {
12448 }
12453 }
12454 }
12457 }
12459 /* Unwinding tables are not referenced directly. This pass marks them as
12460 required if the corresponding code section is marked. */
12462 static bfd_boolean
12464 elf_gc_mark_hook_fn gc_mark_hook)
12465 {
12468 bfd_boolean again;
12472 /* Marking EH data may cause additional code sections to be marked,
12473 requiring multiple passes. */
12476 {
12479 {
12487 {
12496 {
12500 }
12501 }
12502 }
12503 }
12506 }
12508 /* Treat mapping symbols as special target symbols. */
12510 static bfd_boolean
12512 {
12514 BFD_ARM_SPECIAL_SYM_TYPE_ANY);
12515 }
12517 /* This is a copy of elf_find_function() from elf.c except that
12518 ARM mapping symbols are ignored when looking for function names
12519 and STT_ARM_TFUNC is considered to a function type. */
12521 static bfd_boolean
12525 bfd_vma offset,
12528 {
12535 {
12541 {
12550 /* Skip mapping symbols. */
12553 BFD_ARM_SPECIAL_SYM_TYPE_ANY))
12555 /* Fall through. */
12559 {
12562 }
12564 }
12565 }
12576 }
12579 /* Find the nearest line to a particular section and offset, for error
12580 reporting. This code is a duplicate of the code in elf.c, except
12581 that it uses arm_elf_find_function. */
12583 static bfd_boolean
12587 bfd_vma offset,
12591 {
12594 /* We skip _bfd_dwarf1_find_nearest_line since no known ARM toolchain uses it. */
12600 {
12604 functionname_ptr);
12607 }
12627 }
12629 static bfd_boolean
12634 {
12635 bfd_boolean found;
12640 }
12642 /* Adjust a symbol defined by a dynamic object and referenced by a
12643 regular object. The current definition is in some section of the
12644 dynamic object, but we're not including those sections. We have to
12645 change the definition to something the rest of the link can
12646 understand. */
12648 static bfd_boolean
12651 {
12663 /* Make sure we know what is going on here. */
12674 /* If this is a function, put it in the procedure linkage table. We
12675 will fill in the contents of the procedure linkage table later,
12676 when we know the address of the .got section. */
12678 {
12679 /* Calls to STT_GNU_IFUNC symbols always use a PLT, even if the
12680 symbol binds locally. */
12686 {
12687 /* This case can occur if we saw a PLT32 reloc in an input
12688 file, but the symbol was never referred to by a dynamic
12689 object, or if all references were garbage collected. In
12690 such a case, we don't actually need to build a procedure
12691 linkage table, and we can just do a PC24 reloc instead. */
12697 }
12700 }
12701 else
12702 {
12703 /* It's possible that we incorrectly decided a .plt reloc was
12704 needed for an R_ARM_PC24 or similar reloc to a non-function sym
12705 in check_relocs. We can't decide accurately between function
12706 and non-function syms in check-relocs; Objects loaded later in
12707 the link may change h->type. So fix it now. */
12712 }
12714 /* If this is a weak symbol, and there is a real definition, the
12715 processor independent code will have arranged for us to see the
12716 real definition first, and we can just use the same value. */
12718 {
12724 }
12726 /* If there are no non-GOT references, we do not need a copy
12727 relocation. */
12731 /* This is a reference to a symbol defined by a dynamic object which
12732 is not a function. */
12734 /* If we are creating a shared library, we must presume that the
12735 only references to the symbol are via the global offset table.
12736 For such cases we need not do anything here; the relocations will
12737 be handled correctly by relocate_section. Relocatable executables
12738 can reference data in shared objects directly, so we don't need to
12739 do anything here. */
12744 {
12748 }
12750 /* We must allocate the symbol in our .dynbss section, which will
12751 become part of the .bss section of the executable. There will be
12752 an entry for this symbol in the .dynsym section. The dynamic
12753 object will contain position independent code, so all references
12754 from the dynamic object to this symbol will go through the global
12755 offset table. The dynamic linker will use the .dynsym entry to
12756 determine the address it must put in the global offset table, so
12757 both the dynamic object and the regular object will refer to the
12758 same memory location for the variable. */
12762 /* We must generate a R_ARM_COPY reloc to tell the dynamic linker to
12763 copy the initial value out of the dynamic object and into the
12764 runtime process image. We need to remember the offset into the
12765 .rel(a).bss section we are going to use. */
12767 {
12773 }
12776 }
12778 /* Allocate space in .plt, .got and associated reloc sections for
12779 dynamic relocs. */
12781 static bfd_boolean
12783 {
12801 {
12802 /* Make sure this symbol is output as a dynamic symbol.
12803 Undefined weak syms won't yet be marked as dynamic. */
12806 {
12809 }
12811 /* If the call in the PLT entry binds locally, the associated
12812 GOT entry should use an R_ARM_IRELATIVE relocation instead of
12813 the usual R_ARM_JUMP_SLOT. Put it in the .iplt section rather
12814 than the .plt section. */
12816 {
12820 /* All non-call references can be resolved directly.
12821 This means that they can (and in some cases, must)
12822 resolve directly to the run-time target, rather than
12823 to the PLT. That in turns means that any .got entry
12824 would be equal to the .igot.plt entry, so there's
12825 no point having both. */
12827 }
12832 {
12835 /* If this symbol is not defined in a regular file, and we are
12836 not generating a shared library, then set the symbol to this
12837 location in the .plt. This is required to make function
12838 pointers compare as equal between the normal executable and
12839 the shared library. */
12842 {
12846 /* Make sure the function is not marked as Thumb, in case
12847 it is the target of an ABS32 relocation, which will
12848 point to the PLT entry. */
12850 }
12854 /* VxWorks executables have a second set of relocations for
12855 each PLT entry. They go in a separate relocation section,
12856 which is processed by the kernel loader. */
12858 {
12859 /* There is a relocation for the initial PLT entry:
12860 an R_ARM_32 relocation for _GLOBAL_OFFSET_TABLE_. */
12864 /* There are two extra relocations for each subsequent
12865 PLT entry: an R_ARM_32 relocation for the GOT entry,
12866 and an R_ARM_32 relocation for the PLT entry. */
12868 }
12869 }
12870 else
12871 {
12874 }
12875 }
12876 else
12877 {
12880 }
12886 {
12888 bfd_boolean dyn;
12892 /* Make sure this symbol is output as a dynamic symbol.
12893 Undefined weak syms won't yet be marked as dynamic. */
12896 {
12899 }
12902 {
12910 /* Non-TLS symbols need one GOT slot. */
12912 else
12913 {
12915 {
12916 /* R_ARM_TLS_DESC needs 2 GOT slots. */
12917 eh->tlsdesc_got
12922 /* plt.got_offset needs to know there's a TLS_DESC
12923 reloc in the middle of .got.plt. */
12925 }
12928 {
12929 /* R_ARM_TLS_GD32 needs 2 consecutive GOT slots. If
12930 the symbol is both GD and GDESC, got.offset may
12931 have been overwritten. */
12934 }
12937 /* R_ARM_TLS_IE32 needs one GOT slot. */
12939 }
12953 {
12961 {
12963 /* GDESC needs a trampoline to jump to. */
12965 }
12967 /* Only GD needs it. GDESC just emits one relocation per
12968 2 entries. */
12971 }
12973 {
12975 /* Reserve room for the GOT entry's R_ARM_GLOB_DAT relocation. */
12977 }
12980 /* No non-call references resolve the STT_GNU_IFUNC's PLT entry;
12981 they all resolve dynamically instead. Reserve room for the
12982 GOT entry's R_ARM_IRELATIVE relocation. */
12985 /* Reserve room for the GOT entry's R_ARM_RELATIVE relocation. */
12987 }
12988 }
12989 else
12992 /* Allocate stubs for exported Thumb functions on v4t. */
12997 {
13004 /* Create a new symbol to regist the real location of the function. */
13018 /* Point the symbol at the stub. */
13023 }
13028 /* In the shared -Bsymbolic case, discard space allocated for
13029 dynamic pc-relative relocs against symbols which turn out to be
13030 defined in regular objects. For the normal shared case, discard
13031 space for pc-relative relocs that have become local due to symbol
13032 visibility changes. */
13035 {
13036 /* The only relocs that use pc_count are R_ARM_REL32 and
13037 R_ARM_REL32_NOI, which will appear on something like
13038 ".long foo - .". We want calls to protected symbols to resolve
13039 directly to the function rather than going via the plt. If people
13040 want function pointer comparisons to work as expected then they
13041 should avoid writing assembly like ".long foo - .". */
13043 {
13047 {
13052 else
13054 }
13055 }
13058 {
13062 {
13065 else
13067 }
13068 }
13070 /* Also discard relocs on undefined weak syms with non-default
13071 visibility. */
13074 {
13078 /* Make sure undefined weak symbols are output as a dynamic
13079 symbol in PIEs. */
13082 {
13085 }
13086 }
13090 {
13091 /* Output absolute symbols so that we can create relocations
13092 against them. For normal symbols we output a relocation
13093 against the section that contains them. */
13096 }
13098 }
13099 else
13100 {
13101 /* For the non-shared case, discard space for relocs against
13102 symbols which turn out to need copy relocs or are not
13103 dynamic. */
13111 {
13112 /* Make sure this symbol is output as a dynamic symbol.
13113 Undefined weak syms won't yet be marked as dynamic. */
13116 {
13119 }
13121 /* If that succeeded, we know we'll be keeping all the
13122 relocs. */
13125 }
13129 keep: ;
13130 }
13132 /* Finally, allocate space. */
13134 {
13140 else
13142 }
13145 }
13147 /* Find any dynamic relocs that apply to read-only sections. */
13149 static bfd_boolean
13151 {
13157 {
13161 {
13166 /* Not an error, just cut short the traversal. */
13168 }
13169 }
13171 }
13173 void
13176 {
13184 }
13186 /* Set the sizes of the dynamic sections. */
13188 static bfd_boolean
13191 {
13194 bfd_boolean plt;
13195 bfd_boolean relocs;
13208 {
13209 /* Set the contents of the .interp section to the interpreter. */
13211 {
13216 }
13217 }
13219 /* Set up .got offsets for local syms, and space for local dynamic
13220 relocs. */
13222 {
13228 bfd_size_type locsymcount;
13238 {
13243 {
13246 {
13247 /* Input section has been discarded, either because
13248 it is a copy of a linkonce section or due to
13249 linker script /DISCARD/, so we'll be discarding
13250 the relocs too. */
13251 }
13255 {
13256 /* Relocations in vxworks .tls_vars sections are
13257 handled specially by the loader. */
13258 }
13260 {
13265 }
13266 }
13267 }
13285 {
13289 {
13293 {
13298 /* All references to the PLT are calls, so all
13299 non-call references can resolve directly to the
13300 run-time target. This means that the .got entry
13301 would be the same as the .igot.plt entry, so there's
13302 no point creating both. */
13304 }
13305 else
13306 {
13309 }
13312 {
13318 else
13320 }
13321 }
13323 {
13328 /* TLS_GD relocs need an 8-byte structure in the GOT. */
13331 {
13336 /* plt.got_offset needs to know there's a TLS_DESC
13337 reloc in the middle of .got.plt. */
13339 }
13344 {
13345 /* If the symbol is both GD and GDESC, *local_got
13346 may have been overwritten. */
13349 }
13355 /* If all references to an STT_GNU_IFUNC PLT are calls,
13356 then all non-call references, including this GOT entry,
13357 resolve directly to the run-time target. */
13367 {
13370 }
13371 }
13372 else
13374 }
13375 }
13378 {
13379 /* Allocate two GOT entries and one dynamic relocation (if necessary)
13380 for R_ARM_TLS_LDM32 relocations. */
13385 }
13386 else
13389 /* Allocate global sym .plt and .got entries, and space for global
13390 sym dynamic relocs. */
13393 /* Here we rummage through the found bfds to collect glue information. */
13395 {
13399 /* Initialise mapping tables for code/data. */
13404 /* xgettext:c-format */
13407 }
13409 /* Allocate space for the glue sections now that we've sized them. */
13412 /* For every jump slot reserved in the sgotplt, reloc_count is
13413 incremented. However, when we reserve space for TLS descriptors,
13414 it's not incremented, so in order to compute the space reserved
13415 for them, it suffices to multiply the reloc count by the jump
13416 slot size. */
13421 {
13428 /* If we're not using lazy TLS relocations, don't generate the
13429 PLT and GOT entries they require. */
13431 {
13437 }
13438 }
13440 /* The check_relocs and adjust_dynamic_symbol entry points have
13441 determined the sizes of the various dynamic sections. Allocate
13442 memory for them. */
13446 {
13452 /* It's OK to base decisions on the section name, because none
13453 of the dynobj section names depend upon the input files. */
13457 {
13458 /* Remember whether there is a PLT. */
13460 }
13462 {
13464 {
13465 /* Remember whether there are any reloc sections other
13466 than .rel(a).plt and .rela.plt.unloaded. */
13470 /* We use the reloc_count field as a counter if we need
13471 to copy relocs into the output file. */
13473 }
13474 }
13480 {
13481 /* It's not one of our sections, so don't allocate space. */
13483 }
13486 {
13487 /* If we don't need this section, strip it from the
13488 output file. This is mostly to handle .rel(a).bss and
13489 .rel(a).plt. We must create both sections in
13490 create_dynamic_sections, because they must be created
13491 before the linker maps input sections to output
13492 sections. The linker does that before
13493 adjust_dynamic_symbol is called, and it is that
13494 function which decides whether anything needs to go
13495 into these sections. */
13498 }
13503 /* Allocate memory for the section contents. */
13507 }
13510 {
13511 /* Add some entries to the .dynamic section. We fill in the
13512 values later, in elf32_arm_finish_dynamic_sections, but we
13513 must add the entries now so that we get the correct size for
13514 the .dynamic section. The DT_DEBUG entry is filled in by the
13515 dynamic linker and used by the debugger. */
13516 #define add_dynamic_entry(TAG, VAL) \
13517 _bfd_elf_add_dynamic_entry (info, TAG, VAL)
13520 {
13523 }
13526 {
13538 }
13541 {
13543 {
13548 }
13549 else
13550 {
13555 }
13556 }
13558 /* If any dynamic relocs apply to a read-only section,
13559 then we need a DT_TEXTREL entry. */
13562 info);
13565 {
13568 }
13572 }
13573 #undef add_dynamic_entry
13576 }
13578 /* Size sections even though they're not dynamic. We use it to setup
13579 _TLS_MODULE_BASE_, if needed. */
13581 static bfd_boolean
13584 {
13593 {
13596 tlsbase = elf_link_hash_lookup
13600 {
13616 }
13617 }
13619 }
13621 /* Finish up dynamic symbol handling. We set the contents of various
13622 dynamic sections here. */
13624 static bfd_boolean
13629 {
13640 {
13642 {
13646 }
13649 {
13650 /* Mark the symbol as undefined, rather than as defined in
13651 the .plt section. Leave the value alone. */
13653 /* If the symbol is weak, we do need to clear the value.
13654 Otherwise, the PLT entry would provide a definition for
13655 the symbol even if the symbol wasn't defined anywhere,
13656 and so the symbol would never be NULL. */
13659 }
13661 {
13662 /* At least one non-call relocation references this .iplt entry,
13663 so the .iplt entry is the function's canonical address. */
13671 }
13672 }
13675 {
13677 Elf_Internal_Rela rel;
13679 /* This symbol needs a copy reloc. Set it up. */
13693 }
13695 /* Mark _DYNAMIC and _GLOBAL_OFFSET_TABLE_ as absolute. On VxWorks,
13696 the _GLOBAL_OFFSET_TABLE_ symbol is not absolute: it is relative
13697 to the ".got" section. */
13703 }
13705 static void
13709 {
13713 {
13716 /* Emit mov pc,rx if bx is not permitted. */
13720 }
13721 }
13723 /* Finish up the dynamic sections. */
13725 static bfd_boolean
13727 {
13740 /* A broken linker script might have discarded the dynamic sections.
13741 Catch this here so that we do not seg-fault later on. */
13747 {
13759 {
13760 Elf_Internal_Dyn dyn;
13767 {
13800 get_vma:
13805 else
13806 /* In the BPABI, tags in the PT_DYNAMIC section point
13807 at the file offset, not the memory address, for the
13808 convenience of the post linker. */
13813 get_vma_if_bpabi:
13828 {
13829 /* My reading of the SVR4 ABI indicates that the
13830 procedure linkage table relocs (DT_JMPREL) should be
13831 included in the overall relocs (DT_REL). This is
13832 what Solaris does. However, UnixWare can not handle
13833 that case. Therefore, we override the DT_RELSZ entry
13834 here to make it not include the JMPREL relocs. Since
13835 the linker script arranges for .rel(a).plt to follow all
13836 other relocation sections, we don't have to worry
13837 about changing the DT_REL entry. */
13843 }
13844 /* Fall through. */
13848 /* In the BPABI, the DT_REL tag must point at the file
13849 offset, not the VMA, of the first relocation
13850 section. So, we use code similar to that in
13851 elflink.c, but do not check for SHF_ALLOC on the
13852 relcoation section, since relocations sections are
13853 never allocated under the BPABI. The comments above
13854 about Unixware notwithstanding, we include all of the
13855 relocations here. */
13857 {
13863 {
13864 Elf_Internal_Shdr *hdr
13867 {
13874 }
13875 }
13877 }
13894 /* Set the bottom bit of DT_INIT/FINI if the
13895 corresponding function is Thumb. */
13901 get_sym:
13902 /* If it wasn't set by elf_bfd_final_link
13903 then there is nothing to adjust. */
13905 {
13911 {
13914 }
13915 }
13917 }
13918 }
13920 /* Fill in the first entry in the procedure linkage table. */
13922 {
13926 /* Calculate the addresses of the GOT and PLT. */
13931 {
13932 /* The VxWorks GOT is relocated by the dynamic linker.
13933 Therefore, we must emit relocations rather than simply
13934 computing the values now. */
13935 Elf_Internal_Rela rel;
13946 /* Generate a relocation for _GLOBAL_OFFSET_TABLE_. */
13952 }
13953 else
13954 {
13967 #ifdef FOUR_WORD_PLT
13968 /* The displacement value goes in the otherwise-unused
13969 last word of the second entry. */
13971 #else
13973 #endif
13974 }
13975 }
13977 /* UnixWare sets the entsize of .plt to 4, although that doesn't
13978 really seem like the right value. */
13983 {
13984 bfd_vma got_address
13988 bfd_vma plt_address
14004 }
14007 {
14011 #ifdef FOUR_WORD_PLT
14014 #endif
14015 }
14018 {
14019 /* Correct the .rel(a).plt.unloaded relocations. They will have
14020 incorrect symbol indexes. */
14029 {
14030 Elf_Internal_Rela rel;
14041 }
14042 }
14043 }
14045 /* Fill in the first three entries in the global offset table. */
14047 {
14049 {
14052 else
14058 }
14061 }
14064 }
14066 static void
14067 elf32_arm_post_process_headers (bfd * abfd, struct bfd_link_info * link_info ATTRIBUTE_UNUSED)
14068 {
14076 else
14081 {
14085 }
14086 }
14088 static enum elf_reloc_type_class
14090 {
14092 {
14101 }
14102 }
14104 static void
14106 {
14108 }
14110 /* Return TRUE if this is an unwinding table entry. */
14112 static bfd_boolean
14114 {
14117 }
14120 /* Set the type and flags for an ARM section. We do this by
14121 the section name, which is a hack, but ought to work. */
14123 static bfd_boolean
14125 {
14131 {
14134 }
14136 }
14138 /* Handle an ARM specific section when reading an object file. This is
14139 called when bfd_section_from_shdr finds a section with an unknown
14140 type. */
14142 static bfd_boolean
14147 {
14148 /* There ought to be a place to keep ELF backend specific flags, but
14149 at the moment there isn't one. We just keep track of the
14150 sections by their name, instead. Fortunately, the ABI gives
14151 names for all the ARM specific sections, so we will probably get
14152 away with this. */
14154 {
14162 }
14168 }
14172 {
14175 else
14177 }
14180 {
14189 enum map_symbol_type
14190 {
14191 ARM_MAP_ARM,
14192 ARM_MAP_THUMB,
14193 ARM_MAP_DATA
14194 };
14197 /* Output a single mapping symbol. */
14199 static bfd_boolean
14202 bfd_vma offset)
14203 {
14205 Elf_Internal_Sym sym;
14217 }
14219 /* Output mapping symbols for the PLT entry described by ROOT_PLT and ARM_PLT.
14220 IS_IPLT_ENTRY_P says whether the PLT is in .iplt rather than .plt. */
14222 static bfd_boolean
14224 bfd_boolean is_iplt_entry_p,
14227 {
14239 {
14242 }
14243 else
14244 {
14247 }
14253 {
14258 }
14260 {
14269 }
14270 else
14271 {
14272 bfd_boolean thumb_stub_p;
14276 {
14279 }
14280 #ifdef FOUR_WORD_PLT
14285 #else
14286 /* A three-word PLT with no Thumb thunk contains only Arm code,
14287 so only need to output a mapping symbol for the first PLT entry and
14288 entries with thumb thunks. */
14290 {
14293 }
14294 #endif
14295 }
14298 }
14300 /* Output mapping symbols for PLT entries associated with H. */
14302 static bfd_boolean
14304 {
14312 /* When warning symbols are created, they **replace** the "real"
14313 entry in the hash table, thus we never get to see the real
14314 symbol in a hash traversal. So look at it now. */
14320 }
14322 /* Output a single local symbol for a generated stub. */
14324 static bfd_boolean
14327 {
14328 Elf_Internal_Sym sym;
14339 }
14341 static bfd_boolean
14344 {
14347 bfd_vma addr;
14356 /* Massage our args to the form they really have. */
14362 /* Ensure this stub is attached to the current section being
14363 processed. */
14372 {
14386 }
14391 {
14393 {
14410 }
14413 {
14417 }
14420 {
14437 }
14438 }
14441 }
14443 /* Output mapping symbols for linker generated sections,
14444 and for those data-only sections that do not have a
14445 $d. */
14447 static bfd_boolean
14452 Elf_Internal_Sym *,
14453 asection *,
14455 {
14456 output_arch_syminfo osi;
14458 bfd_vma offset;
14459 bfd_size_type size;
14472 /* Add a $d mapping symbol to data-only sections that
14473 don't have any mapping symbol. This may result in (harmless) redundant
14474 mapping symbols. */
14478 {
14483 {
14488 == SEC_HAS_CONTENTS
14492 {
14497 }
14498 }
14499 }
14501 /* ARM->Thumb glue. */
14503 {
14505 ARM2THUMB_GLUE_SECTION_NAME);
14514 else
14518 {
14521 }
14522 }
14524 /* Thumb->ARM glue. */
14526 {
14528 THUMB2ARM_GLUE_SECTION_NAME);
14535 {
14538 }
14539 }
14541 /* ARMv4 BX veneers. */
14543 {
14545 ARM_BX_GLUE_SECTION_NAME);
14551 }
14553 /* Long calls stubs. */
14555 {
14561 {
14562 /* Ignore non-stub sections. */
14572 }
14573 }
14575 /* Finally, output mapping symbols for the PLT. */
14577 {
14582 /* Output mapping symbols for the plt header. SymbianOS does not have a
14583 plt header. */
14585 {
14586 /* VxWorks shared libraries have no PLT header. */
14588 {
14593 }
14594 }
14596 {
14599 #ifndef FOUR_WORD_PLT
14602 #endif
14603 }
14604 }
14607 {
14612 {
14618 {
14626 }
14627 }
14628 }
14630 {
14631 /* Mapping symbols for the lazy tls trampoline. */
14638 }
14640 {
14641 /* Mapping symbols for the tls trampoline. */
14644 #ifdef FOUR_WORD_PLT
14648 #endif
14649 }
14652 }
14654 /* Allocate target specific section data. */
14656 static bfd_boolean
14658 {
14660 {
14668 }
14671 }
14674 /* Used to order a list of mapping symbols by address. */
14676 static int
14678 {
14687 /* Ensure results do not depend on the host qsort for objects with
14688 multiple mapping symbols at the same address by sorting on type
14689 after vma. */
14693 else
14695 }
14697 /* Add OFFSET to lower 31 bits of ADDR, leaving other bits unmodified. */
14699 static unsigned long
14701 {
14703 }
14705 /* Copy an .ARM.exidx table entry, adding OFFSET to (applied) PREL31
14706 relocations. */
14708 static void
14710 {
14714 /* High bit of first word is supposed to be zero. */
14718 /* If the high bit of the first word is clear, and the bit pattern is not 0x1
14719 (EXIDX_CANTUNWIND), this is an offset to an .ARM.extab entry. */
14725 }
14727 /* Data for make_branch_to_a8_stub(). */
14732 };
14735 /* Helper to insert branches to Cortex-A8 erratum stubs in the right
14736 places for a particular section. */
14738 static bfd_boolean
14741 {
14747 bfd_signed_vma branch_offset;
14776 /* We attempt to avoid this condition by setting stubs_always_after_branch
14777 in elf32_arm_size_stubs if we've enabled the Cortex-A8 erratum workaround.
14778 This check is just to be on the safe side... */
14780 {
14784 }
14787 {
14798 {
14803 jump24:
14805 {
14806 /* There's not much we can do apart from complain if this
14807 happens. */
14811 }
14813 /* i1 = not(j1 eor s), so:
14814 not i1 = j1 eor s
14815 j1 = (not i1) eor s. */
14827 }
14833 }
14839 }
14841 /* Do code byteswapping. Return FALSE afterwards so that the section is
14842 written out as normal. */
14844 static bfd_boolean
14849 {
14855 bfd_vma ptr;
14856 bfd_vma end;
14858 bfd_byte tmp;
14864 /* If this section has not been allocated an _arm_elf_section_data
14865 structure then we cannot record anything. */
14875 {
14880 {
14884 {
14886 {
14887 bfd_vma branch_to_veneer;
14888 /* Original condition code of instruction, plus bit mask for
14889 ARM B instruction. */
14893 /* The instruction is before the label. */
14896 /* Above offset included in -4 below. */
14910 }
14914 {
14915 bfd_vma branch_from_veneer;
14918 /* Take size of veneer into account. */
14927 /* Original instruction. */
14934 /* Branch back to insn after original insn. */
14940 }
14945 }
14946 }
14947 }
14950 {
14951 arm_unwind_table_edit *edit_node
14953 /* Now, sec->size is the size of the section we will write. The original
14954 size (before we merged duplicate entries and inserted EXIDX_CANTUNWIND
14955 markers) was sec->rawsize. (This isn't the case if we perform no
14956 edits, then rawsize will be zero and we should use size). */
14963 {
14965 {
14969 {
14972 out_index++;
14973 in_index++;
14974 }
14978 {
14980 {
14982 in_index++;
14987 {
14995 /* Note: this is meant to be equivalent to an
14996 R_ARM_PREL31 relocation. These synthetic
14997 EXIDX_CANTUNWIND markers are not relocated by the
14998 usual BFD method. */
15002 /* First address we can't unwind. */
15006 /* Code for EXIDX_CANTUNWIND. */
15010 out_index++;
15012 }
15014 }
15017 }
15018 }
15019 else
15020 {
15021 /* No more edits, copy remaining entries verbatim. */
15024 out_index++;
15025 in_index++;
15026 }
15027 }
15031 edited_contents,
15035 }
15037 /* Fix code to point to Cortex-A8 erratum stubs. */
15039 {
15047 }
15053 {
15058 {
15061 else
15065 {
15067 /* Byte swap code words. */
15069 {
15077 }
15081 /* Byte swap code halfwords. */
15083 {
15088 }
15092 /* Leave data alone. */
15094 }
15096 }
15097 }
15105 }
15107 /* Mangle thumb function symbols as we read them in. */
15109 static bfd_boolean
15114 {
15118 /* New EABI objects mark thumb function symbols by setting the low bit of
15119 the address. */
15122 {
15124 {
15127 }
15128 else
15130 }
15132 {
15135 }
15138 else
15142 }
15145 /* Mangle thumb function symbols as we write them out. */
15147 static void
15152 {
15153 Elf_Internal_Sym newsym;
15155 /* We convert STT_ARM_TFUNC symbols into STT_FUNC with the low bit
15156 of the address set, as per the new EABI. We do this unconditionally
15157 because objcopy does not set the elf header flags until after
15158 it writes out the symbol table. */
15160 {
15165 {
15166 /* Do this only for defined symbols. At link type, the static
15167 linker will simulate the work of dynamic linker of resolving
15168 symbols and will carry over the thumbness of found symbols to
15169 the output symbol table. It's not clear how it happens, but
15170 the thumbness of undefined symbols can well be different at
15171 runtime, and writing '1' for them will be confusing for users
15172 and possibly for dynamic linker itself.
15173 */
15175 }
15178 }
15180 }
15182 /* Add the PT_ARM_EXIDX program header. */
15184 static bfd_boolean
15187 {
15193 {
15194 /* If there is already a PT_ARM_EXIDX header, then we do not
15195 want to add another one. This situation arises when running
15196 "strip"; the input binary already has the header. */
15201 {
15212 }
15213 }
15216 }
15218 /* We may add a PT_ARM_EXIDX program header. */
15220 static int
15223 {
15229 else
15231 }
15233 /* Hook called by the linker routine which adds symbols from an object
15234 file. */
15236 static bfd_boolean
15240 {
15252 }
15254 /* We use this to override swap_symbol_in and swap_symbol_out. */
15256 {
15269 bfd_elf32_write_out_phdrs,
15270 bfd_elf32_write_shdrs_and_ehdr,
15271 bfd_elf32_checksum_contents,
15272 bfd_elf32_write_relocs,
15273 elf32_arm_swap_symbol_in,
15274 elf32_arm_swap_symbol_out,
15275 bfd_elf32_slurp_reloc_table,
15276 bfd_elf32_slurp_symbol_table,
15277 bfd_elf32_swap_dyn_in,
15278 bfd_elf32_swap_dyn_out,
15279 bfd_elf32_swap_reloc_in,
15280 bfd_elf32_swap_reloc_out,
15281 bfd_elf32_swap_reloca_in,
15282 bfd_elf32_swap_reloca_out
15283 };
15285 #define ELF_ARCH bfd_arch_arm
15286 #define ELF_TARGET_ID ARM_ELF_DATA
15287 #define ELF_MACHINE_CODE EM_ARM
15288 #ifdef __QNXTARGET__
15289 #define ELF_MAXPAGESIZE 0x1000
15290 #else
15291 #define ELF_MAXPAGESIZE 0x8000
15292 #endif
15293 #define ELF_MINPAGESIZE 0x1000
15294 #define ELF_COMMONPAGESIZE 0x1000
15296 #define bfd_elf32_mkobject elf32_arm_mkobject
15298 #define bfd_elf32_bfd_copy_private_bfd_data elf32_arm_copy_private_bfd_data
15299 #define bfd_elf32_bfd_merge_private_bfd_data elf32_arm_merge_private_bfd_data
15300 #define bfd_elf32_bfd_set_private_flags elf32_arm_set_private_flags
15301 #define bfd_elf32_bfd_print_private_bfd_data elf32_arm_print_private_bfd_data
15302 #define bfd_elf32_bfd_link_hash_table_create elf32_arm_link_hash_table_create
15303 #define bfd_elf32_bfd_link_hash_table_free elf32_arm_hash_table_free
15304 #define bfd_elf32_bfd_reloc_type_lookup elf32_arm_reloc_type_lookup
15305 #define bfd_elf32_bfd_reloc_name_lookup elf32_arm_reloc_name_lookup
15306 #define bfd_elf32_find_nearest_line elf32_arm_find_nearest_line
15307 #define bfd_elf32_find_inliner_info elf32_arm_find_inliner_info
15308 #define bfd_elf32_new_section_hook elf32_arm_new_section_hook
15309 #define bfd_elf32_bfd_is_target_special_symbol elf32_arm_is_target_special_symbol
15310 #define bfd_elf32_bfd_final_link elf32_arm_final_link
15312 #define elf_backend_get_symbol_type elf32_arm_get_symbol_type
15313 #define elf_backend_gc_mark_hook elf32_arm_gc_mark_hook
15314 #define elf_backend_gc_mark_extra_sections elf32_arm_gc_mark_extra_sections
15315 #define elf_backend_gc_sweep_hook elf32_arm_gc_sweep_hook
15316 #define elf_backend_check_relocs elf32_arm_check_relocs
15317 #define elf_backend_relocate_section elf32_arm_relocate_section
15318 #define elf_backend_write_section elf32_arm_write_section
15319 #define elf_backend_adjust_dynamic_symbol elf32_arm_adjust_dynamic_symbol
15320 #define elf_backend_create_dynamic_sections elf32_arm_create_dynamic_sections
15321 #define elf_backend_finish_dynamic_symbol elf32_arm_finish_dynamic_symbol
15322 #define elf_backend_finish_dynamic_sections elf32_arm_finish_dynamic_sections
15323 #define elf_backend_size_dynamic_sections elf32_arm_size_dynamic_sections
15324 #define elf_backend_always_size_sections elf32_arm_always_size_sections
15325 #define elf_backend_init_index_section _bfd_elf_init_2_index_sections
15326 #define elf_backend_post_process_headers elf32_arm_post_process_headers
15327 #define elf_backend_reloc_type_class elf32_arm_reloc_type_class
15328 #define elf_backend_object_p elf32_arm_object_p
15329 #define elf_backend_fake_sections elf32_arm_fake_sections
15330 #define elf_backend_section_from_shdr elf32_arm_section_from_shdr
15331 #define elf_backend_final_write_processing elf32_arm_final_write_processing
15332 #define elf_backend_copy_indirect_symbol elf32_arm_copy_indirect_symbol
15333 #define elf_backend_size_info elf32_arm_size_info
15334 #define elf_backend_modify_segment_map elf32_arm_modify_segment_map
15335 #define elf_backend_additional_program_headers elf32_arm_additional_program_headers
15336 #define elf_backend_output_arch_local_syms elf32_arm_output_arch_local_syms
15337 #define elf_backend_begin_write_processing elf32_arm_begin_write_processing
15338 #define elf_backend_add_symbol_hook elf32_arm_add_symbol_hook
15340 #define elf_backend_can_refcount 1
15341 #define elf_backend_can_gc_sections 1
15342 #define elf_backend_plt_readonly 1
15343 #define elf_backend_want_got_plt 1
15344 #define elf_backend_want_plt_sym 0
15345 #define elf_backend_may_use_rel_p 1
15346 #define elf_backend_may_use_rela_p 0
15347 #define elf_backend_default_use_rela_p 0
15349 #define elf_backend_got_header_size 12
15351 #undef elf_backend_obj_attrs_vendor
15353 #undef elf_backend_obj_attrs_section
15355 #undef elf_backend_obj_attrs_arg_type
15356 #define elf_backend_obj_attrs_arg_type elf32_arm_obj_attrs_arg_type
15357 #undef elf_backend_obj_attrs_section_type
15358 #define elf_backend_obj_attrs_section_type SHT_ARM_ATTRIBUTES
15359 #define elf_backend_obj_attrs_order elf32_arm_obj_attrs_order
15360 #define elf_backend_obj_attrs_handle_unknown elf32_arm_obj_attrs_handle_unknown
15364 /* VxWorks Targets. */
15366 #undef TARGET_LITTLE_SYM
15367 #define TARGET_LITTLE_SYM bfd_elf32_littlearm_vxworks_vec
15368 #undef TARGET_LITTLE_NAME
15370 #undef TARGET_BIG_SYM
15371 #define TARGET_BIG_SYM bfd_elf32_bigarm_vxworks_vec
15372 #undef TARGET_BIG_NAME
15375 /* Like elf32_arm_link_hash_table_create -- but overrides
15376 appropriately for VxWorks. */
15380 {
15385 {
15390 }
15392 }
15394 static void
15396 {
15399 }
15401 #undef elf32_bed
15402 #define elf32_bed elf32_arm_vxworks_bed
15404 #undef bfd_elf32_bfd_link_hash_table_create
15405 #define bfd_elf32_bfd_link_hash_table_create elf32_arm_vxworks_link_hash_table_create
15406 #undef elf_backend_final_write_processing
15407 #define elf_backend_final_write_processing elf32_arm_vxworks_final_write_processing
15408 #undef elf_backend_emit_relocs
15409 #define elf_backend_emit_relocs elf_vxworks_emit_relocs
15411 #undef elf_backend_may_use_rel_p
15412 #define elf_backend_may_use_rel_p 0
15413 #undef elf_backend_may_use_rela_p
15414 #define elf_backend_may_use_rela_p 1
15415 #undef elf_backend_default_use_rela_p
15416 #define elf_backend_default_use_rela_p 1
15417 #undef elf_backend_want_plt_sym
15418 #define elf_backend_want_plt_sym 1
15419 #undef ELF_MAXPAGESIZE
15420 #define ELF_MAXPAGESIZE 0x1000
15425 /* Merge backend specific data from an object file to the output
15426 object file when linking. */
15428 static bfd_boolean
15430 {
15431 flagword out_flags;
15432 flagword in_flags;
15436 /* Check if we have the same endianness. */
15446 /* The input BFD must have had its flags initialised. */
15447 /* The following seems bogus to me -- The flags are initialized in
15448 the assembler but I don't think an elf_flags_init field is
15449 written into the object. */
15450 /* BFD_ASSERT (elf_flags_init (ibfd)); */
15455 /* In theory there is no reason why we couldn't handle this. However
15456 in practice it isn't even close to working and there is no real
15457 reason to want it. */
15461 {
15463 ibfd);
15465 }
15468 {
15469 /* If the input is the default architecture and had the default
15470 flags then do not bother setting the flags for the output
15471 architecture, instead allow future merges to do this. If no
15472 future merges ever set these flags then they will retain their
15473 uninitialised values, which surprise surprise, correspond
15474 to the default values. */
15487 }
15489 /* Determine what should happen if the input ARM architecture
15490 does not match the output ARM architecture. */
15494 /* Identical flags must be compatible. */
15498 /* Check to see if the input BFD actually contains any sections. If
15499 not, its flags may not have been initialised either, but it
15500 cannot actually cause any incompatiblity. Do not short-circuit
15501 dynamic objects; their section list may be emptied by
15502 elf_link_add_object_symbols.
15504 Also check to see if there are no code sections in the input.
15505 In this case there is no need to check for code specific flags.
15506 XXX - do we need to worry about floating-point format compatability
15507 in data sections ? */
15509 {
15514 {
15515 /* Ignore synthetic glue sections. */
15518 {
15526 }
15527 }
15531 }
15533 /* Complain about various flag mismatches. */
15536 {
15537 _bfd_error_handler
15543 }
15545 /* Not sure what needs to be checked for EABI versions >= 1. */
15546 /* VxWorks libraries do not use these flags. */
15550 {
15552 {
15553 _bfd_error_handler
15559 }
15562 {
15564 _bfd_error_handler
15565 (_("error: %B passes floats in float registers, whereas %B passes them in integer registers"),
15567 else
15568 _bfd_error_handler
15569 (_("error: %B passes floats in integer registers, whereas %B passes them in float registers"),
15573 }
15576 {
15578 _bfd_error_handler
15581 else
15582 _bfd_error_handler
15587 }
15590 {
15592 _bfd_error_handler
15595 else
15596 _bfd_error_handler
15601 }
15603 #ifdef EF_ARM_SOFT_FLOAT
15605 {
15606 /* We can allow interworking between code that is VFP format
15607 layout, and uses either soft float or integer regs for
15608 passing floating point arguments and results. We already
15609 know that the APCS_FLOAT flags match; similarly for VFP
15610 flags. */
15613 {
15615 _bfd_error_handler
15618 else
15619 _bfd_error_handler
15624 }
15625 }
15626 #endif
15628 /* Interworking mismatch is only a warning. */
15630 {
15632 {
15633 _bfd_error_handler
15636 }
15637 else
15638 {
15639 _bfd_error_handler
15642 }
15643 }
15644 }
15647 }
15650 /* Symbian OS Targets. */
15652 #undef TARGET_LITTLE_SYM
15653 #define TARGET_LITTLE_SYM bfd_elf32_littlearm_symbian_vec
15654 #undef TARGET_LITTLE_NAME
15656 #undef TARGET_BIG_SYM
15657 #define TARGET_BIG_SYM bfd_elf32_bigarm_symbian_vec
15658 #undef TARGET_BIG_NAME
15661 /* Like elf32_arm_link_hash_table_create -- but overrides
15662 appropriately for Symbian OS. */
15666 {
15671 {
15674 /* There is no PLT header for Symbian OS. */
15676 /* The PLT entries are each one instruction and one word. */
15679 /* Symbian uses armv5t or above, so use_blx is always true. */
15682 }
15684 }
15686 static const struct bfd_elf_special_section
15687 elf32_arm_symbian_special_sections[] =
15688 {
15689 /* In a BPABI executable, the dynamic linking sections do not go in
15690 the loadable read-only segment. The post-linker may wish to
15691 refer to these sections, but they are not part of the final
15692 program image. */
15698 /* These sections do not need to be writable as the SymbianOS
15699 postlinker will arrange things so that no dynamic relocation is
15700 required. */
15705 };
15707 static void
15710 {
15711 /* BPABI objects are never loaded directly by an OS kernel; they are
15712 processed by a postlinker first, into an OS-specific format. If
15713 the D_PAGED bit is set on the file, BFD will align segments on
15714 page boundaries, so that an OS can directly map the file. With
15715 BPABI objects, that just results in wasted space. In addition,
15716 because we clear the D_PAGED bit, map_sections_to_segments will
15717 recognize that the program headers should not be mapped into any
15718 loadable segment. */
15721 }
15723 static bfd_boolean
15726 {
15730 /* BPABI shared libraries and executables should have a PT_DYNAMIC
15731 segment. However, because the .dynamic section is not marked
15732 with SEC_LOAD, the generic ELF code will not create such a
15733 segment. */
15736 {
15742 {
15746 }
15747 }
15749 /* Also call the generic arm routine. */
15751 }
15753 /* Return address for Ith PLT stub in section PLT, for relocation REL
15754 or (bfd_vma) -1 if it should not be included. */
15756 static bfd_vma
15759 {
15761 }
15764 #undef elf32_bed
15765 #define elf32_bed elf32_arm_symbian_bed
15767 /* The dynamic sections are not allocated on SymbianOS; the postlinker
15768 will process them and then discard them. */
15769 #undef ELF_DYNAMIC_SEC_FLAGS
15770 #define ELF_DYNAMIC_SEC_FLAGS \
15771 (SEC_HAS_CONTENTS | SEC_IN_MEMORY | SEC_LINKER_CREATED)
15773 #undef elf_backend_emit_relocs
15775 #undef bfd_elf32_bfd_link_hash_table_create
15776 #define bfd_elf32_bfd_link_hash_table_create elf32_arm_symbian_link_hash_table_create
15777 #undef elf_backend_special_sections
15778 #define elf_backend_special_sections elf32_arm_symbian_special_sections
15779 #undef elf_backend_begin_write_processing
15780 #define elf_backend_begin_write_processing elf32_arm_symbian_begin_write_processing
15781 #undef elf_backend_final_write_processing
15782 #define elf_backend_final_write_processing elf32_arm_final_write_processing
15784 #undef elf_backend_modify_segment_map
15785 #define elf_backend_modify_segment_map elf32_arm_symbian_modify_segment_map
15787 /* There is no .got section for BPABI objects, and hence no header. */
15788 #undef elf_backend_got_header_size
15789 #define elf_backend_got_header_size 0
15791 /* Similarly, there is no .got.plt section. */
15792 #undef elf_backend_want_got_plt
15793 #define elf_backend_want_got_plt 0
15795 #undef elf_backend_plt_sym_val
15796 #define elf_backend_plt_sym_val elf32_arm_symbian_plt_sym_val
15798 #undef elf_backend_may_use_rel_p
15799 #define elf_backend_may_use_rel_p 1
15800 #undef elf_backend_may_use_rela_p
15801 #define elf_backend_may_use_rela_p 0
15802 #undef elf_backend_default_use_rela_p
15803 #define elf_backend_default_use_rela_p 0
15804 #undef elf_backend_want_plt_sym
15805 #define elf_backend_want_plt_sym 0
15806 #undef ELF_MAXPAGESIZE
15807 #define ELF_MAXPAGESIZE 0x8000