* config/tc-mips.c (append_insn): Correctly handle mips16 case
[binutils.git] / gas / config / tc-arm.c
blobfd95edb283e96771013c66551456f20c6e3f5220
1 /* tc-arm.c -- Assemble for the ARM
2 Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003,
3 2004, 2005
4 Free Software Foundation, Inc.
5 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
6 Modified by David Taylor (dtaylor@armltd.co.uk)
7 Cirrus coprocessor mods by Aldy Hernandez (aldyh@redhat.com)
8 Cirrus coprocessor fixes by Petko Manolov (petkan@nucleusys.com)
9 Cirrus coprocessor fixes by Vladimir Ivanov (vladitx@nucleusys.com)
11 This file is part of GAS, the GNU Assembler.
13 GAS is free software; you can redistribute it and/or modify
14 it under the terms of the GNU General Public License as published by
15 the Free Software Foundation; either version 2, or (at your option)
16 any later version.
18 GAS is distributed in the hope that it will be useful,
19 but WITHOUT ANY WARRANTY; without even the implied warranty of
20 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 GNU General Public License for more details.
23 You should have received a copy of the GNU General Public License
24 along with GAS; see the file COPYING. If not, write to the Free
25 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
26 02110-1301, USA. */
28 #include <string.h>
29 #define NO_RELOC 0
30 #include "as.h"
31 #include "safe-ctype.h"
33 /* Need TARGET_CPU. */
34 #include "config.h"
35 #include "subsegs.h"
36 #include "obstack.h"
37 #include "symbols.h"
38 #include "listing.h"
40 #include "opcode/arm.h"
42 #ifdef OBJ_ELF
43 #include "elf/arm.h"
44 #include "dwarf2dbg.h"
45 #include "dw2gencfi.h"
46 #endif
48 /* XXX Set this to 1 after the next binutils release. */
49 #define WARN_DEPRECATED 0
51 #ifdef OBJ_ELF
52 /* Must be at least the size of the largest unwind opcode (currently two). */
53 #define ARM_OPCODE_CHUNK_SIZE 8
55 /* This structure holds the unwinding state. */
57 static struct
59 symbolS * proc_start;
60 symbolS * table_entry;
61 symbolS * personality_routine;
62 int personality_index;
63 /* The segment containing the function. */
64 segT saved_seg;
65 subsegT saved_subseg;
66 /* Opcodes generated from this function. */
67 unsigned char * opcodes;
68 int opcode_count;
69 int opcode_alloc;
70 /* The number of bytes pushed to the stack. */
71 offsetT frame_size;
72 /* We don't add stack adjustment opcodes immediately so that we can merge
73 multiple adjustments. We can also omit the final adjustment
74 when using a frame pointer. */
75 offsetT pending_offset;
76 /* These two fields are set by both unwind_movsp and unwind_setfp. They
77 hold the reg+offset to use when restoring sp from a frame pointer. */
78 offsetT fp_offset;
79 int fp_reg;
80 /* Nonzero if an unwind_setfp directive has been seen. */
81 unsigned fp_used:1;
82 /* Nonzero if the last opcode restores sp from fp_reg. */
83 unsigned sp_restored:1;
84 } unwind;
86 /* Bit N indicates that an R_ARM_NONE relocation has been output for
87 __aeabi_unwind_cpp_prN already if set. This enables dependencies to be
88 emitted only once per section, to save unnecessary bloat. */
89 static unsigned int marked_pr_dependency = 0;
91 #endif /* OBJ_ELF */
93 enum arm_float_abi
95 ARM_FLOAT_ABI_HARD,
96 ARM_FLOAT_ABI_SOFTFP,
97 ARM_FLOAT_ABI_SOFT
100 /* Types of processor to assemble for. */
101 #define ARM_1 ARM_ARCH_V1
102 #define ARM_2 ARM_ARCH_V2
103 #define ARM_3 ARM_ARCH_V2S
104 #define ARM_250 ARM_ARCH_V2S
105 #define ARM_6 ARM_ARCH_V3
106 #define ARM_7 ARM_ARCH_V3
107 #define ARM_8 ARM_ARCH_V4
108 #define ARM_9 ARM_ARCH_V4T
109 #define ARM_STRONG ARM_ARCH_V4
110 #define ARM_CPU_MASK 0x0000000f /* XXX? */
112 #ifndef CPU_DEFAULT
113 #if defined __XSCALE__
114 #define CPU_DEFAULT (ARM_ARCH_XSCALE)
115 #else
116 #if defined __thumb__
117 #define CPU_DEFAULT (ARM_ARCH_V5T)
118 #else
119 #define CPU_DEFAULT ARM_ANY
120 #endif
121 #endif
122 #endif
124 #ifndef FPU_DEFAULT
125 # ifdef TE_LINUX
126 # define FPU_DEFAULT FPU_ARCH_FPA
127 # elif defined (TE_NetBSD)
128 # ifdef OBJ_ELF
129 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, but VFP order. */
130 # else
131 /* Legacy a.out format. */
132 # define FPU_DEFAULT FPU_ARCH_FPA /* Soft-float, but FPA order. */
133 # endif
134 # elif defined (TE_VXWORKS)
135 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, VFP order. */
136 # else
137 /* For backwards compatibility, default to FPA. */
138 # define FPU_DEFAULT FPU_ARCH_FPA
139 # endif
140 #endif /* ifndef FPU_DEFAULT */
142 #define streq(a, b) (strcmp (a, b) == 0)
144 static unsigned long cpu_variant;
146 /* Flags stored in private area of BFD structure. */
147 static int uses_apcs_26 = FALSE;
148 static int atpcs = FALSE;
149 static int support_interwork = FALSE;
150 static int uses_apcs_float = FALSE;
151 static int pic_code = FALSE;
153 /* Variables that we set while parsing command-line options. Once all
154 options have been read we re-process these values to set the real
155 assembly flags. */
156 static int legacy_cpu = -1;
157 static int legacy_fpu = -1;
159 static int mcpu_cpu_opt = -1;
160 static int mcpu_fpu_opt = -1;
161 static int march_cpu_opt = -1;
162 static int march_fpu_opt = -1;
163 static int mfpu_opt = -1;
164 static int mfloat_abi_opt = -1;
165 #ifdef OBJ_ELF
166 # ifdef EABI_DEFAULT
167 static int meabi_flags = EABI_DEFAULT;
168 # else
169 static int meabi_flags = EF_ARM_EABI_UNKNOWN;
170 # endif
171 #endif
173 #ifdef OBJ_ELF
174 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
175 symbolS * GOT_symbol;
176 #endif
178 /* 0: assemble for ARM,
179 1: assemble for Thumb,
180 2: assemble for Thumb even though target CPU does not support thumb
181 instructions. */
182 static int thumb_mode = 0;
184 /* If unified_syntax is true, we are processing the new unified
185 ARM/Thumb syntax. Important differences from the old ARM mode:
187 - Immediate operands do not require a # prefix.
188 - Conditional affixes always appear at the end of the
189 instruction. (For backward compatibility, those instructions
190 that formerly had them in the middle, continue to accept them
191 there.)
192 - The IT instruction may appear, and if it does is validated
193 against subsequent conditional affixes. It does not generate
194 machine code.
196 Important differences from the old Thumb mode:
198 - Immediate operands do not require a # prefix.
199 - Most of the V6T2 instructions are only available in unified mode.
200 - The .N and .W suffixes are recognized and honored (it is an error
201 if they cannot be honored).
202 - All instructions set the flags if and only if they have an 's' affix.
203 - Conditional affixes may be used. They are validated against
204 preceding IT instructions. Unlike ARM mode, you cannot use a
205 conditional affix except in the scope of an IT instruction. */
207 static bfd_boolean unified_syntax = FALSE;
209 struct arm_it
211 const char * error;
212 unsigned long instruction;
213 int size;
214 int size_req;
215 int cond;
216 struct
218 bfd_reloc_code_real_type type;
219 expressionS exp;
220 int pc_rel;
221 } reloc;
223 struct
225 unsigned reg;
226 signed int imm;
227 unsigned present : 1; /* Operand present. */
228 unsigned isreg : 1; /* Operand was a register. */
229 unsigned immisreg : 1; /* .imm field is a second register. */
230 unsigned hasreloc : 1; /* Operand has relocation suffix. */
231 unsigned writeback : 1; /* Operand has trailing ! */
232 unsigned preind : 1; /* Preindexed address. */
233 unsigned postind : 1; /* Postindexed address. */
234 unsigned negative : 1; /* Index register was negated. */
235 unsigned shifted : 1; /* Shift applied to operation. */
236 unsigned shift_kind : 3; /* Shift operation (enum shift_kind). */
237 } operands[6];
240 static struct arm_it inst;
242 #define NUM_FLOAT_VALS 8
244 const char * fp_const[] =
246 "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0
249 /* Number of littlenums required to hold an extended precision number. */
250 #define MAX_LITTLENUMS 6
252 LITTLENUM_TYPE fp_values[NUM_FLOAT_VALS][MAX_LITTLENUMS];
254 #define FAIL (-1)
255 #define SUCCESS (0)
257 #define SUFF_S 1
258 #define SUFF_D 2
259 #define SUFF_E 3
260 #define SUFF_P 4
262 #define CP_T_X 0x00008000
263 #define CP_T_Y 0x00400000
265 #define CONDS_BIT 0x00100000
266 #define LOAD_BIT 0x00100000
268 #define DOUBLE_LOAD_FLAG 0x00000001
270 struct asm_cond
272 const char * template;
273 unsigned long value;
276 #define COND_ALWAYS 0xE
278 struct asm_psr
280 const char *template;
281 unsigned long field;
284 /* The bit that distinguishes CPSR and SPSR. */
285 #define SPSR_BIT (1 << 22)
287 /* The individual PSR flag bits. */
288 #define PSR_c (1 << 16)
289 #define PSR_x (1 << 17)
290 #define PSR_s (1 << 18)
291 #define PSR_f (1 << 19)
293 struct reloc_entry
295 char *name;
296 bfd_reloc_code_real_type reloc;
299 enum vfp_sp_reg_pos
301 VFP_REG_Sd, VFP_REG_Sm, VFP_REG_Sn
304 enum vfp_ldstm_type
306 VFP_LDSTMIA, VFP_LDSTMDB, VFP_LDSTMIAX, VFP_LDSTMDBX
309 /* ARM register categories. This includes coprocessor numbers and various
310 architecture extensions' registers. */
311 enum arm_reg_type
313 REG_TYPE_RN,
314 REG_TYPE_CP,
315 REG_TYPE_CN,
316 REG_TYPE_FN,
317 REG_TYPE_VFS,
318 REG_TYPE_VFD,
319 REG_TYPE_VFC,
320 REG_TYPE_MVF,
321 REG_TYPE_MVD,
322 REG_TYPE_MVFX,
323 REG_TYPE_MVDX,
324 REG_TYPE_MVAX,
325 REG_TYPE_DSPSC,
326 REG_TYPE_MMXWR,
327 REG_TYPE_MMXWC,
328 REG_TYPE_MMXWCG,
329 REG_TYPE_XSCALE,
332 /* Structure for a hash table entry for a register. */
333 struct reg_entry
335 const char *name;
336 unsigned char number;
337 unsigned char type;
338 unsigned char builtin;
341 /* Diagnostics used when we don't get a register of the expected type. */
342 const char *const reg_expected_msgs[] =
344 N_("ARM register expected"),
345 N_("bad or missing co-processor number"),
346 N_("co-processor register expected"),
347 N_("FPA register expected"),
348 N_("VFP single precision register expected"),
349 N_("VFP double precision register expected"),
350 N_("VFP system register expected"),
351 N_("Maverick MVF register expected"),
352 N_("Maverick MVD register expected"),
353 N_("Maverick MVFX register expected"),
354 N_("Maverick MVDX register expected"),
355 N_("Maverick MVAX register expected"),
356 N_("Maverick DSPSC register expected"),
357 N_("iWMMXt data register expected"),
358 N_("iWMMXt control register expected"),
359 N_("iWMMXt scalar register expected"),
360 N_("XScale accumulator register expected"),
363 /* Some well known registers that we refer to directly elsewhere. */
364 #define REG_SP 13
365 #define REG_LR 14
366 #define REG_PC 15
368 /* ARM instructions take 4bytes in the object file, Thumb instructions
369 take 2: */
370 #define INSN_SIZE 4
372 struct asm_opcode
374 /* Basic string to match. */
375 const char *template;
377 /* Parameters to instruction. */
378 unsigned char operands[8];
380 /* Conditional tag - see opcode_lookup. */
381 unsigned int tag : 4;
383 /* Basic instruction code. */
384 unsigned int avalue : 28;
386 /* Thumb-format instruction code. */
387 unsigned int tvalue;
389 /* Which architecture variant provides this instruction. */
390 unsigned long avariant;
391 unsigned long tvariant;
393 /* Function to call to encode instruction in ARM format. */
394 void (* aencode) (void);
396 /* Function to call to encode instruction in Thumb format. */
397 void (* tencode) (void);
400 /* Defines for various bits that we will want to toggle. */
401 #define INST_IMMEDIATE 0x02000000
402 #define OFFSET_REG 0x02000000
403 #define HWOFFSET_IMM 0x00400000
404 #define SHIFT_BY_REG 0x00000010
405 #define PRE_INDEX 0x01000000
406 #define INDEX_UP 0x00800000
407 #define WRITE_BACK 0x00200000
408 #define LDM_TYPE_2_OR_3 0x00400000
410 #define LITERAL_MASK 0xf000f000
411 #define OPCODE_MASK 0xfe1fffff
412 #define V4_STR_BIT 0x00000020
414 #define DATA_OP_SHIFT 21
416 /* Codes to distinguish the arithmetic instructions. */
417 #define OPCODE_AND 0
418 #define OPCODE_EOR 1
419 #define OPCODE_SUB 2
420 #define OPCODE_RSB 3
421 #define OPCODE_ADD 4
422 #define OPCODE_ADC 5
423 #define OPCODE_SBC 6
424 #define OPCODE_RSC 7
425 #define OPCODE_TST 8
426 #define OPCODE_TEQ 9
427 #define OPCODE_CMP 10
428 #define OPCODE_CMN 11
429 #define OPCODE_ORR 12
430 #define OPCODE_MOV 13
431 #define OPCODE_BIC 14
432 #define OPCODE_MVN 15
434 #define T_OPCODE_MUL 0x4340
435 #define T_OPCODE_TST 0x4200
436 #define T_OPCODE_CMN 0x42c0
437 #define T_OPCODE_NEG 0x4240
438 #define T_OPCODE_MVN 0x43c0
440 #define T_OPCODE_ADD_R3 0x1800
441 #define T_OPCODE_SUB_R3 0x1a00
442 #define T_OPCODE_ADD_HI 0x4400
443 #define T_OPCODE_ADD_ST 0xb000
444 #define T_OPCODE_SUB_ST 0xb080
445 #define T_OPCODE_ADD_SP 0xa800
446 #define T_OPCODE_ADD_PC 0xa000
447 #define T_OPCODE_ADD_I8 0x3000
448 #define T_OPCODE_SUB_I8 0x3800
449 #define T_OPCODE_ADD_I3 0x1c00
450 #define T_OPCODE_SUB_I3 0x1e00
452 #define T_OPCODE_ASR_R 0x4100
453 #define T_OPCODE_LSL_R 0x4080
454 #define T_OPCODE_LSR_R 0x40c0
455 #define T_OPCODE_ROR_R 0x41c0
456 #define T_OPCODE_ASR_I 0x1000
457 #define T_OPCODE_LSL_I 0x0000
458 #define T_OPCODE_LSR_I 0x0800
460 #define T_OPCODE_MOV_I8 0x2000
461 #define T_OPCODE_CMP_I8 0x2800
462 #define T_OPCODE_CMP_LR 0x4280
463 #define T_OPCODE_MOV_HR 0x4600
464 #define T_OPCODE_CMP_HR 0x4500
466 #define T_OPCODE_LDR_PC 0x4800
467 #define T_OPCODE_LDR_SP 0x9800
468 #define T_OPCODE_STR_SP 0x9000
469 #define T_OPCODE_LDR_IW 0x6800
470 #define T_OPCODE_STR_IW 0x6000
471 #define T_OPCODE_LDR_IH 0x8800
472 #define T_OPCODE_STR_IH 0x8000
473 #define T_OPCODE_LDR_IB 0x7800
474 #define T_OPCODE_STR_IB 0x7000
475 #define T_OPCODE_LDR_RW 0x5800
476 #define T_OPCODE_STR_RW 0x5000
477 #define T_OPCODE_LDR_RH 0x5a00
478 #define T_OPCODE_STR_RH 0x5200
479 #define T_OPCODE_LDR_RB 0x5c00
480 #define T_OPCODE_STR_RB 0x5400
482 #define T_OPCODE_PUSH 0xb400
483 #define T_OPCODE_POP 0xbc00
485 #define T_OPCODE_BRANCH 0xe000
487 #define THUMB_SIZE 2 /* Size of thumb instruction. */
488 #define THUMB_PP_PC_LR 0x0100
489 #define THUMB_LOAD_BIT 0x0800
491 #define BAD_ARGS _("bad arguments to instruction")
492 #define BAD_PC _("r15 not allowed here")
493 #define BAD_COND _("instruction cannot be conditional")
494 #define BAD_OVERLAP _("registers may not be the same")
495 #define BAD_HIREG _("lo register required")
496 #define BAD_THUMB32 _("instruction not supported in Thumb16 mode")
498 static struct hash_control *arm_ops_hsh;
499 static struct hash_control *arm_cond_hsh;
500 static struct hash_control *arm_shift_hsh;
501 static struct hash_control *arm_psr_hsh;
502 static struct hash_control *arm_reg_hsh;
503 static struct hash_control *arm_reloc_hsh;
505 /* Stuff needed to resolve the label ambiguity
508 label: <insn>
509 may differ from:
511 label:
512 <insn>
515 symbolS * last_label_seen;
516 static int label_is_thumb_function_name = FALSE;
518 /* Literal pool structure. Held on a per-section
519 and per-sub-section basis. */
521 #define MAX_LITERAL_POOL_SIZE 1024
522 typedef struct literal_pool
524 expressionS literals [MAX_LITERAL_POOL_SIZE];
525 unsigned int next_free_entry;
526 unsigned int id;
527 symbolS * symbol;
528 segT section;
529 subsegT sub_section;
530 struct literal_pool * next;
531 } literal_pool;
533 /* Pointer to a linked list of literal pools. */
534 literal_pool * list_of_pools = NULL;
536 /* State variables for IT block handling. */
537 static bfd_boolean current_it_mask = 0;
538 static int current_cc;
541 /* Pure syntax. */
543 /* This array holds the chars that always start a comment. If the
544 pre-processor is disabled, these aren't very useful. */
545 const char comment_chars[] = "@";
547 /* This array holds the chars that only start a comment at the beginning of
548 a line. If the line seems to have the form '# 123 filename'
549 .line and .file directives will appear in the pre-processed output. */
550 /* Note that input_file.c hand checks for '#' at the beginning of the
551 first line of the input file. This is because the compiler outputs
552 #NO_APP at the beginning of its output. */
553 /* Also note that comments like this one will always work. */
554 const char line_comment_chars[] = "#";
556 const char line_separator_chars[] = ";";
558 /* Chars that can be used to separate mant
559 from exp in floating point numbers. */
560 const char EXP_CHARS[] = "eE";
562 /* Chars that mean this number is a floating point constant. */
563 /* As in 0f12.456 */
564 /* or 0d1.2345e12 */
566 const char FLT_CHARS[] = "rRsSfFdDxXeEpP";
568 /* Prefix characters that indicate the start of an immediate
569 value. */
570 #define is_immediate_prefix(C) ((C) == '#' || (C) == '$')
572 /* Separator character handling. */
574 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
576 static inline int
577 skip_past_char (char ** str, char c)
579 if (**str == c)
581 (*str)++;
582 return SUCCESS;
584 else
585 return FAIL;
587 #define skip_past_comma(str) skip_past_char (str, ',')
589 /* Arithmetic expressions (possibly involving symbols). */
591 /* Return TRUE if anything in the expression is a bignum. */
593 static int
594 walk_no_bignums (symbolS * sp)
596 if (symbol_get_value_expression (sp)->X_op == O_big)
597 return 1;
599 if (symbol_get_value_expression (sp)->X_add_symbol)
601 return (walk_no_bignums (symbol_get_value_expression (sp)->X_add_symbol)
602 || (symbol_get_value_expression (sp)->X_op_symbol
603 && walk_no_bignums (symbol_get_value_expression (sp)->X_op_symbol)));
606 return 0;
609 static int in_my_get_expression = 0;
611 /* Third argument to my_get_expression. */
612 #define GE_NO_PREFIX 0
613 #define GE_IMM_PREFIX 1
614 #define GE_OPT_PREFIX 2
616 static int
617 my_get_expression (expressionS * ep, char ** str, int prefix_mode)
619 char * save_in;
620 segT seg;
622 /* In unified syntax, all prefixes are optional. */
623 if (unified_syntax)
624 prefix_mode = GE_OPT_PREFIX;
626 switch (prefix_mode)
628 case GE_NO_PREFIX: break;
629 case GE_IMM_PREFIX:
630 if (!is_immediate_prefix (**str))
632 inst.error = _("immediate expression requires a # prefix");
633 return FAIL;
635 (*str)++;
636 break;
637 case GE_OPT_PREFIX:
638 if (is_immediate_prefix (**str))
639 (*str)++;
640 break;
641 default: abort ();
644 memset (ep, 0, sizeof (expressionS));
646 save_in = input_line_pointer;
647 input_line_pointer = *str;
648 in_my_get_expression = 1;
649 seg = expression (ep);
650 in_my_get_expression = 0;
652 if (ep->X_op == O_illegal)
654 /* We found a bad expression in md_operand(). */
655 *str = input_line_pointer;
656 input_line_pointer = save_in;
657 if (inst.error == NULL)
658 inst.error = _("bad expression");
659 return 1;
662 #ifdef OBJ_AOUT
663 if (seg != absolute_section
664 && seg != text_section
665 && seg != data_section
666 && seg != bss_section
667 && seg != undefined_section)
669 inst.error = _("bad segment");
670 *str = input_line_pointer;
671 input_line_pointer = save_in;
672 return 1;
674 #endif
676 /* Get rid of any bignums now, so that we don't generate an error for which
677 we can't establish a line number later on. Big numbers are never valid
678 in instructions, which is where this routine is always called. */
679 if (ep->X_op == O_big
680 || (ep->X_add_symbol
681 && (walk_no_bignums (ep->X_add_symbol)
682 || (ep->X_op_symbol
683 && walk_no_bignums (ep->X_op_symbol)))))
685 inst.error = _("invalid constant");
686 *str = input_line_pointer;
687 input_line_pointer = save_in;
688 return 1;
691 *str = input_line_pointer;
692 input_line_pointer = save_in;
693 return 0;
696 /* Turn a string in input_line_pointer into a floating point constant
697 of type TYPE, and store the appropriate bytes in *LITP. The number
698 of LITTLENUMS emitted is stored in *SIZEP. An error message is
699 returned, or NULL on OK.
701 Note that fp constants aren't represent in the normal way on the ARM.
702 In big endian mode, things are as expected. However, in little endian
703 mode fp constants are big-endian word-wise, and little-endian byte-wise
704 within the words. For example, (double) 1.1 in big endian mode is
705 the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is
706 the byte sequence 99 99 f1 3f 9a 99 99 99.
708 ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */
710 char *
711 md_atof (int type, char * litP, int * sizeP)
713 int prec;
714 LITTLENUM_TYPE words[MAX_LITTLENUMS];
715 char *t;
716 int i;
718 switch (type)
720 case 'f':
721 case 'F':
722 case 's':
723 case 'S':
724 prec = 2;
725 break;
727 case 'd':
728 case 'D':
729 case 'r':
730 case 'R':
731 prec = 4;
732 break;
734 case 'x':
735 case 'X':
736 prec = 6;
737 break;
739 case 'p':
740 case 'P':
741 prec = 6;
742 break;
744 default:
745 *sizeP = 0;
746 return _("bad call to MD_ATOF()");
749 t = atof_ieee (input_line_pointer, type, words);
750 if (t)
751 input_line_pointer = t;
752 *sizeP = prec * 2;
754 if (target_big_endian)
756 for (i = 0; i < prec; i++)
758 md_number_to_chars (litP, (valueT) words[i], 2);
759 litP += 2;
762 else
764 if (cpu_variant & FPU_ARCH_VFP)
765 for (i = prec - 1; i >= 0; i--)
767 md_number_to_chars (litP, (valueT) words[i], 2);
768 litP += 2;
770 else
771 /* For a 4 byte float the order of elements in `words' is 1 0.
772 For an 8 byte float the order is 1 0 3 2. */
773 for (i = 0; i < prec; i += 2)
775 md_number_to_chars (litP, (valueT) words[i + 1], 2);
776 md_number_to_chars (litP + 2, (valueT) words[i], 2);
777 litP += 4;
781 return 0;
784 /* We handle all bad expressions here, so that we can report the faulty
785 instruction in the error message. */
786 void
787 md_operand (expressionS * expr)
789 if (in_my_get_expression)
790 expr->X_op = O_illegal;
793 /* Immediate values. */
795 /* Generic immediate-value read function for use in directives.
796 Accepts anything that 'expression' can fold to a constant.
797 *val receives the number. */
798 #ifdef OBJ_ELF
799 static int
800 immediate_for_directive (int *val)
802 expressionS exp;
803 exp.X_op = O_illegal;
805 if (is_immediate_prefix (*input_line_pointer))
807 input_line_pointer++;
808 expression (&exp);
811 if (exp.X_op != O_constant)
813 as_bad (_("expected #constant"));
814 ignore_rest_of_line ();
815 return FAIL;
817 *val = exp.X_add_number;
818 return SUCCESS;
820 #endif
822 /* Register parsing. */
824 /* Generic register parser. CCP points to what should be the
825 beginning of a register name. If it is indeed a valid register
826 name, advance CCP over it and return the reg_entry structure;
827 otherwise return NULL. Does not issue diagnostics. */
829 static struct reg_entry *
830 arm_reg_parse_multi (char **ccp)
832 char *start = *ccp;
833 char *p;
834 struct reg_entry *reg;
836 #ifdef REGISTER_PREFIX
837 if (*start != REGISTER_PREFIX)
838 return FAIL;
839 start++;
840 #endif
841 #ifdef OPTIONAL_REGISTER_PREFIX
842 if (*start == OPTIONAL_REGISTER_PREFIX)
843 start++;
844 #endif
846 p = start;
847 if (!ISALPHA (*p) || !is_name_beginner (*p))
848 return NULL;
851 p++;
852 while (ISALPHA (*p) || ISDIGIT (*p) || *p == '_');
854 reg = (struct reg_entry *) hash_find_n (arm_reg_hsh, start, p - start);
856 if (!reg)
857 return NULL;
859 *ccp = p;
860 return reg;
863 /* As above, but the register must be of type TYPE, and the return
864 value is the register number or NULL. */
866 static int
867 arm_reg_parse (char **ccp, enum arm_reg_type type)
869 char *start = *ccp;
870 struct reg_entry *reg = arm_reg_parse_multi (ccp);
872 if (reg && reg->type == type)
873 return reg->number;
875 /* Alternative syntaxes are accepted for a few register classes. */
876 switch (type)
878 case REG_TYPE_MVF:
879 case REG_TYPE_MVD:
880 case REG_TYPE_MVFX:
881 case REG_TYPE_MVDX:
882 /* Generic coprocessor register names are allowed for these. */
883 if (reg->type == REG_TYPE_CN)
884 return reg->number;
885 break;
887 case REG_TYPE_CP:
888 /* For backward compatibility, a bare number is valid here. */
890 unsigned long processor = strtoul (start, ccp, 10);
891 if (*ccp != start && processor <= 15)
892 return processor;
895 case REG_TYPE_MMXWC:
896 /* WC includes WCG. ??? I'm not sure this is true for all
897 instructions that take WC registers. */
898 if (reg->type == REG_TYPE_MMXWCG)
899 return reg->number;
900 break;
902 default:
903 break;
906 *ccp = start;
907 return FAIL;
910 /* Parse an ARM register list. Returns the bitmask, or FAIL. */
911 static long
912 parse_reg_list (char ** strp)
914 char * str = * strp;
915 long range = 0;
916 int another_range;
918 /* We come back here if we get ranges concatenated by '+' or '|'. */
921 another_range = 0;
923 if (*str == '{')
925 int in_range = 0;
926 int cur_reg = -1;
928 str++;
931 int reg;
933 if ((reg = arm_reg_parse (&str, REG_TYPE_RN)) == FAIL)
935 inst.error = _(reg_expected_msgs[REG_TYPE_RN]);
936 return FAIL;
939 if (in_range)
941 int i;
943 if (reg <= cur_reg)
945 inst.error = _("bad range in register list");
946 return FAIL;
949 for (i = cur_reg + 1; i < reg; i++)
951 if (range & (1 << i))
952 as_tsktsk
953 (_("Warning: duplicated register (r%d) in register list"),
955 else
956 range |= 1 << i;
958 in_range = 0;
961 if (range & (1 << reg))
962 as_tsktsk (_("Warning: duplicated register (r%d) in register list"),
963 reg);
964 else if (reg <= cur_reg)
965 as_tsktsk (_("Warning: register range not in ascending order"));
967 range |= 1 << reg;
968 cur_reg = reg;
970 while (skip_past_comma (&str) != FAIL
971 || (in_range = 1, *str++ == '-'));
972 str--;
974 if (*str++ != '}')
976 inst.error = _("missing `}'");
977 return FAIL;
980 else
982 expressionS expr;
984 if (my_get_expression (&expr, &str, GE_NO_PREFIX))
985 return FAIL;
987 if (expr.X_op == O_constant)
989 if (expr.X_add_number
990 != (expr.X_add_number & 0x0000ffff))
992 inst.error = _("invalid register mask");
993 return FAIL;
996 if ((range & expr.X_add_number) != 0)
998 int regno = range & expr.X_add_number;
1000 regno &= -regno;
1001 regno = (1 << regno) - 1;
1002 as_tsktsk
1003 (_("Warning: duplicated register (r%d) in register list"),
1004 regno);
1007 range |= expr.X_add_number;
1009 else
1011 if (inst.reloc.type != 0)
1013 inst.error = _("expression too complex");
1014 return FAIL;
1017 memcpy (&inst.reloc.exp, &expr, sizeof (expressionS));
1018 inst.reloc.type = BFD_RELOC_ARM_MULTI;
1019 inst.reloc.pc_rel = 0;
1023 if (*str == '|' || *str == '+')
1025 str++;
1026 another_range = 1;
1029 while (another_range);
1031 *strp = str;
1032 return range;
1035 /* Parse a VFP register list. If the string is invalid return FAIL.
1036 Otherwise return the number of registers, and set PBASE to the first
1037 register. Double precision registers are matched if DP is nonzero. */
1039 static int
1040 parse_vfp_reg_list (char **str, unsigned int *pbase, int dp)
1042 int base_reg;
1043 int new_base;
1044 int regtype;
1045 int max_regs;
1046 int count = 0;
1047 int warned = 0;
1048 unsigned long mask = 0;
1049 int i;
1051 if (**str != '{')
1052 return FAIL;
1054 (*str)++;
1056 if (dp)
1058 regtype = REG_TYPE_VFD;
1059 max_regs = 16;
1061 else
1063 regtype = REG_TYPE_VFS;
1064 max_regs = 32;
1067 base_reg = max_regs;
1071 new_base = arm_reg_parse (str, regtype);
1072 if (new_base == FAIL)
1074 inst.error = gettext (reg_expected_msgs[regtype]);
1075 return FAIL;
1078 if (new_base < base_reg)
1079 base_reg = new_base;
1081 if (mask & (1 << new_base))
1083 inst.error = _("invalid register list");
1084 return FAIL;
1087 if ((mask >> new_base) != 0 && ! warned)
1089 as_tsktsk (_("register list not in ascending order"));
1090 warned = 1;
1093 mask |= 1 << new_base;
1094 count++;
1096 if (**str == '-') /* We have the start of a range expression */
1098 int high_range;
1100 (*str)++;
1102 if ((high_range = arm_reg_parse (str, regtype)) == FAIL)
1104 inst.error = gettext (reg_expected_msgs[regtype]);
1105 return FAIL;
1108 if (high_range <= new_base)
1110 inst.error = _("register range not in ascending order");
1111 return FAIL;
1114 for (new_base++; new_base <= high_range; new_base++)
1116 if (mask & (1 << new_base))
1118 inst.error = _("invalid register list");
1119 return FAIL;
1122 mask |= 1 << new_base;
1123 count++;
1127 while (skip_past_comma (str) != FAIL);
1129 (*str)++;
1131 /* Sanity check -- should have raised a parse error above. */
1132 if (count == 0 || count > max_regs)
1133 abort ();
1135 *pbase = base_reg;
1137 /* Final test -- the registers must be consecutive. */
1138 mask >>= base_reg;
1139 for (i = 0; i < count; i++)
1141 if ((mask & (1u << i)) == 0)
1143 inst.error = _("non-contiguous register range");
1144 return FAIL;
1148 return count;
1151 /* Parse an explicit relocation suffix on an expression. This is
1152 either nothing, or a word in parentheses. Note that if !OBJ_ELF,
1153 arm_reloc_hsh contains no entries, so this function can only
1154 succeed if there is no () after the word. Returns -1 on error,
1155 BFD_RELOC_UNUSED if there wasn't any suffix. */
1156 static int
1157 parse_reloc (char **str)
1159 struct reloc_entry *r;
1160 char *p, *q;
1162 if (**str != '(')
1163 return BFD_RELOC_UNUSED;
1165 p = *str + 1;
1166 q = p;
1168 while (*q && *q != ')' && *q != ',')
1169 q++;
1170 if (*q != ')')
1171 return -1;
1173 if ((r = hash_find_n (arm_reloc_hsh, p, q - p)) == NULL)
1174 return -1;
1176 *str = q + 1;
1177 return r->reloc;
1180 /* Directives: register aliases. */
1182 static void
1183 insert_reg_alias (char *str, int number, int type)
1185 struct reg_entry *new;
1186 const char *name;
1188 if ((new = hash_find (arm_reg_hsh, str)) != 0)
1190 if (new->builtin)
1191 as_warn (_("ignoring attempt to redefine built-in register '%s'"), str);
1193 /* Only warn about a redefinition if it's not defined as the
1194 same register. */
1195 else if (new->number != number || new->type != type)
1196 as_warn (_("ignoring redefinition of register alias '%s'"), str);
1198 return;
1201 name = xstrdup (str);
1202 new = xmalloc (sizeof (struct reg_entry));
1204 new->name = name;
1205 new->number = number;
1206 new->type = type;
1207 new->builtin = FALSE;
1209 if (hash_insert (arm_reg_hsh, name, (PTR) new))
1210 abort ();
1213 /* Look for the .req directive. This is of the form:
1215 new_register_name .req existing_register_name
1217 If we find one, or if it looks sufficiently like one that we want to
1218 handle any error here, return non-zero. Otherwise return zero. */
1220 static int
1221 create_register_alias (char * newname, char *p)
1223 struct reg_entry *old;
1224 char *oldname, *nbuf;
1225 size_t nlen;
1227 /* The input scrubber ensures that whitespace after the mnemonic is
1228 collapsed to single spaces. */
1229 oldname = p;
1230 if (strncmp (oldname, " .req ", 6) != 0)
1231 return 0;
1233 oldname += 6;
1234 if (*oldname == '\0')
1235 return 0;
1237 old = hash_find (arm_reg_hsh, oldname);
1238 if (!old)
1240 as_warn (_("unknown register '%s' -- .req ignored"), oldname);
1241 return 1;
1244 /* If TC_CASE_SENSITIVE is defined, then newname already points to
1245 the desired alias name, and p points to its end. If not, then
1246 the desired alias name is in the global original_case_string. */
1247 #ifdef TC_CASE_SENSITIVE
1248 nlen = p - newname;
1249 #else
1250 newname = original_case_string;
1251 nlen = strlen (newname);
1252 #endif
1254 nbuf = alloca (nlen + 1);
1255 memcpy (nbuf, newname, nlen);
1256 nbuf[nlen] = '\0';
1258 /* Create aliases under the new name as stated; an all-lowercase
1259 version of the new name; and an all-uppercase version of the new
1260 name. */
1261 insert_reg_alias (nbuf, old->number, old->type);
1263 for (p = nbuf; *p; p++)
1264 *p = TOUPPER (*p);
1266 if (strncmp (nbuf, newname, nlen))
1267 insert_reg_alias (nbuf, old->number, old->type);
1269 for (p = nbuf; *p; p++)
1270 *p = TOLOWER (*p);
1272 if (strncmp (nbuf, newname, nlen))
1273 insert_reg_alias (nbuf, old->number, old->type);
1275 return 1;
1278 /* Should never be called, as .req goes between the alias and the
1279 register name, not at the beginning of the line. */
1280 static void
1281 s_req (int a ATTRIBUTE_UNUSED)
1283 as_bad (_("invalid syntax for .req directive"));
1286 /* The .unreq directive deletes an alias which was previously defined
1287 by .req. For example:
1289 my_alias .req r11
1290 .unreq my_alias */
1292 static void
1293 s_unreq (int a ATTRIBUTE_UNUSED)
1295 char * name;
1296 char saved_char;
1298 name = input_line_pointer;
1300 while (*input_line_pointer != 0
1301 && *input_line_pointer != ' '
1302 && *input_line_pointer != '\n')
1303 ++input_line_pointer;
1305 saved_char = *input_line_pointer;
1306 *input_line_pointer = 0;
1308 if (!*name)
1309 as_bad (_("invalid syntax for .unreq directive"));
1310 else
1312 struct reg_entry *reg = hash_find (arm_reg_hsh, name);
1314 if (!reg)
1315 as_bad (_("unknown register alias '%s'"), name);
1316 else if (reg->builtin)
1317 as_warn (_("ignoring attempt to undefine built-in register '%s'"),
1318 name);
1319 else
1321 hash_delete (arm_reg_hsh, name);
1322 free ((char *) reg->name);
1323 free (reg);
1327 *input_line_pointer = saved_char;
1328 demand_empty_rest_of_line ();
1331 /* Directives: Instruction set selection. */
1333 #ifdef OBJ_ELF
1334 /* This code is to handle mapping symbols as defined in the ARM ELF spec.
1335 (See "Mapping symbols", section 4.5.5, ARM AAELF version 1.0).
1336 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
1337 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
1339 static enum mstate mapstate = MAP_UNDEFINED;
1341 static void
1342 mapping_state (enum mstate state)
1344 symbolS * symbolP;
1345 const char * symname;
1346 int type;
1348 if (mapstate == state)
1349 /* The mapping symbol has already been emitted.
1350 There is nothing else to do. */
1351 return;
1353 mapstate = state;
1355 switch (state)
1357 case MAP_DATA:
1358 symname = "$d";
1359 type = BSF_NO_FLAGS;
1360 break;
1361 case MAP_ARM:
1362 symname = "$a";
1363 type = BSF_NO_FLAGS;
1364 break;
1365 case MAP_THUMB:
1366 symname = "$t";
1367 type = BSF_NO_FLAGS;
1368 break;
1369 case MAP_UNDEFINED:
1370 return;
1371 default:
1372 abort ();
1375 seg_info (now_seg)->tc_segment_info_data.mapstate = state;
1377 symbolP = symbol_new (symname, now_seg, (valueT) frag_now_fix (), frag_now);
1378 symbol_table_insert (symbolP);
1379 symbol_get_bfdsym (symbolP)->flags |= type | BSF_LOCAL;
1381 switch (state)
1383 case MAP_ARM:
1384 THUMB_SET_FUNC (symbolP, 0);
1385 ARM_SET_THUMB (symbolP, 0);
1386 ARM_SET_INTERWORK (symbolP, support_interwork);
1387 break;
1389 case MAP_THUMB:
1390 THUMB_SET_FUNC (symbolP, 1);
1391 ARM_SET_THUMB (symbolP, 1);
1392 ARM_SET_INTERWORK (symbolP, support_interwork);
1393 break;
1395 case MAP_DATA:
1396 default:
1397 return;
1400 #else
1401 #define mapping_state(x) /* nothing */
1402 #endif
1404 /* Find the real, Thumb encoded start of a Thumb function. */
1406 static symbolS *
1407 find_real_start (symbolS * symbolP)
1409 char * real_start;
1410 const char * name = S_GET_NAME (symbolP);
1411 symbolS * new_target;
1413 /* This definition must agree with the one in gcc/config/arm/thumb.c. */
1414 #define STUB_NAME ".real_start_of"
1416 if (name == NULL)
1417 abort ();
1419 /* The compiler may generate BL instructions to local labels because
1420 it needs to perform a branch to a far away location. These labels
1421 do not have a corresponding ".real_start_of" label. We check
1422 both for S_IS_LOCAL and for a leading dot, to give a way to bypass
1423 the ".real_start_of" convention for nonlocal branches. */
1424 if (S_IS_LOCAL (symbolP) || name[0] == '.')
1425 return symbolP;
1427 real_start = ACONCAT ((STUB_NAME, name, NULL));
1428 new_target = symbol_find (real_start);
1430 if (new_target == NULL)
1432 as_warn ("Failed to find real start of function: %s\n", name);
1433 new_target = symbolP;
1436 return new_target;
1439 static void
1440 opcode_select (int width)
1442 switch (width)
1444 case 16:
1445 if (! thumb_mode)
1447 if (! (cpu_variant & ARM_EXT_V4T))
1448 as_bad (_("selected processor does not support THUMB opcodes"));
1450 thumb_mode = 1;
1451 /* No need to force the alignment, since we will have been
1452 coming from ARM mode, which is word-aligned. */
1453 record_alignment (now_seg, 1);
1455 mapping_state (MAP_THUMB);
1456 break;
1458 case 32:
1459 if (thumb_mode)
1461 if ((cpu_variant & ARM_ALL) == ARM_EXT_V4T)
1462 as_bad (_("selected processor does not support ARM opcodes"));
1464 thumb_mode = 0;
1466 if (!need_pass_2)
1467 frag_align (2, 0, 0);
1469 record_alignment (now_seg, 1);
1471 mapping_state (MAP_ARM);
1472 break;
1474 default:
1475 as_bad (_("invalid instruction size selected (%d)"), width);
1479 static void
1480 s_arm (int ignore ATTRIBUTE_UNUSED)
1482 opcode_select (32);
1483 demand_empty_rest_of_line ();
1486 static void
1487 s_thumb (int ignore ATTRIBUTE_UNUSED)
1489 opcode_select (16);
1490 demand_empty_rest_of_line ();
1493 static void
1494 s_code (int unused ATTRIBUTE_UNUSED)
1496 int temp;
1498 temp = get_absolute_expression ();
1499 switch (temp)
1501 case 16:
1502 case 32:
1503 opcode_select (temp);
1504 break;
1506 default:
1507 as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp);
1511 static void
1512 s_force_thumb (int ignore ATTRIBUTE_UNUSED)
1514 /* If we are not already in thumb mode go into it, EVEN if
1515 the target processor does not support thumb instructions.
1516 This is used by gcc/config/arm/lib1funcs.asm for example
1517 to compile interworking support functions even if the
1518 target processor should not support interworking. */
1519 if (! thumb_mode)
1521 thumb_mode = 2;
1522 record_alignment (now_seg, 1);
1525 demand_empty_rest_of_line ();
1528 static void
1529 s_thumb_func (int ignore ATTRIBUTE_UNUSED)
1531 s_thumb (0);
1533 /* The following label is the name/address of the start of a Thumb function.
1534 We need to know this for the interworking support. */
1535 label_is_thumb_function_name = TRUE;
1538 /* Perform a .set directive, but also mark the alias as
1539 being a thumb function. */
1541 static void
1542 s_thumb_set (int equiv)
1544 /* XXX the following is a duplicate of the code for s_set() in read.c
1545 We cannot just call that code as we need to get at the symbol that
1546 is created. */
1547 char * name;
1548 char delim;
1549 char * end_name;
1550 symbolS * symbolP;
1552 /* Especial apologies for the random logic:
1553 This just grew, and could be parsed much more simply!
1554 Dean - in haste. */
1555 name = input_line_pointer;
1556 delim = get_symbol_end ();
1557 end_name = input_line_pointer;
1558 *end_name = delim;
1560 if (*input_line_pointer != ',')
1562 *end_name = 0;
1563 as_bad (_("expected comma after name \"%s\""), name);
1564 *end_name = delim;
1565 ignore_rest_of_line ();
1566 return;
1569 input_line_pointer++;
1570 *end_name = 0;
1572 if (name[0] == '.' && name[1] == '\0')
1574 /* XXX - this should not happen to .thumb_set. */
1575 abort ();
1578 if ((symbolP = symbol_find (name)) == NULL
1579 && (symbolP = md_undefined_symbol (name)) == NULL)
1581 #ifndef NO_LISTING
1582 /* When doing symbol listings, play games with dummy fragments living
1583 outside the normal fragment chain to record the file and line info
1584 for this symbol. */
1585 if (listing & LISTING_SYMBOLS)
1587 extern struct list_info_struct * listing_tail;
1588 fragS * dummy_frag = xmalloc (sizeof (fragS));
1590 memset (dummy_frag, 0, sizeof (fragS));
1591 dummy_frag->fr_type = rs_fill;
1592 dummy_frag->line = listing_tail;
1593 symbolP = symbol_new (name, undefined_section, 0, dummy_frag);
1594 dummy_frag->fr_symbol = symbolP;
1596 else
1597 #endif
1598 symbolP = symbol_new (name, undefined_section, 0, &zero_address_frag);
1600 #ifdef OBJ_COFF
1601 /* "set" symbols are local unless otherwise specified. */
1602 SF_SET_LOCAL (symbolP);
1603 #endif /* OBJ_COFF */
1604 } /* Make a new symbol. */
1606 symbol_table_insert (symbolP);
1608 * end_name = delim;
1610 if (equiv
1611 && S_IS_DEFINED (symbolP)
1612 && S_GET_SEGMENT (symbolP) != reg_section)
1613 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP));
1615 pseudo_set (symbolP);
1617 demand_empty_rest_of_line ();
1619 /* XXX Now we come to the Thumb specific bit of code. */
1621 THUMB_SET_FUNC (symbolP, 1);
1622 ARM_SET_THUMB (symbolP, 1);
1623 #if defined OBJ_ELF || defined OBJ_COFF
1624 ARM_SET_INTERWORK (symbolP, support_interwork);
1625 #endif
1628 /* Directives: Mode selection. */
1630 /* .syntax [unified|divided] - choose the new unified syntax
1631 (same for Arm and Thumb encoding, modulo slight differences in what
1632 can be represented) or the old divergent syntax for each mode. */
1633 static void
1634 s_syntax (int unused ATTRIBUTE_UNUSED)
1636 char *name, delim;
1638 name = input_line_pointer;
1639 delim = get_symbol_end ();
1641 if (!strcasecmp (name, "unified"))
1642 unified_syntax = TRUE;
1643 else if (!strcasecmp (name, "divided"))
1644 unified_syntax = FALSE;
1645 else
1647 as_bad (_("unrecognized syntax mode \"%s\""), name);
1648 return;
1650 *input_line_pointer = delim;
1651 demand_empty_rest_of_line ();
1654 /* Directives: sectioning and alignment. */
1656 /* Same as s_align_ptwo but align 0 => align 2. */
1658 static void
1659 s_align (int unused ATTRIBUTE_UNUSED)
1661 int temp;
1662 long temp_fill;
1663 long max_alignment = 15;
1665 temp = get_absolute_expression ();
1666 if (temp > max_alignment)
1667 as_bad (_("alignment too large: %d assumed"), temp = max_alignment);
1668 else if (temp < 0)
1670 as_bad (_("alignment negative. 0 assumed."));
1671 temp = 0;
1674 if (*input_line_pointer == ',')
1676 input_line_pointer++;
1677 temp_fill = get_absolute_expression ();
1679 else
1680 temp_fill = 0;
1682 if (!temp)
1683 temp = 2;
1685 /* Only make a frag if we HAVE to. */
1686 if (temp && !need_pass_2)
1687 frag_align (temp, (int) temp_fill, 0);
1688 demand_empty_rest_of_line ();
1690 record_alignment (now_seg, temp);
1693 static void
1694 s_bss (int ignore ATTRIBUTE_UNUSED)
1696 /* We don't support putting frags in the BSS segment, we fake it by
1697 marking in_bss, then looking at s_skip for clues. */
1698 subseg_set (bss_section, 0);
1699 demand_empty_rest_of_line ();
1700 mapping_state (MAP_DATA);
1703 static void
1704 s_even (int ignore ATTRIBUTE_UNUSED)
1706 /* Never make frag if expect extra pass. */
1707 if (!need_pass_2)
1708 frag_align (1, 0, 0);
1710 record_alignment (now_seg, 1);
1712 demand_empty_rest_of_line ();
1715 /* Directives: Literal pools. */
1717 static literal_pool *
1718 find_literal_pool (void)
1720 literal_pool * pool;
1722 for (pool = list_of_pools; pool != NULL; pool = pool->next)
1724 if (pool->section == now_seg
1725 && pool->sub_section == now_subseg)
1726 break;
1729 return pool;
1732 static literal_pool *
1733 find_or_make_literal_pool (void)
1735 /* Next literal pool ID number. */
1736 static unsigned int latest_pool_num = 1;
1737 literal_pool * pool;
1739 pool = find_literal_pool ();
1741 if (pool == NULL)
1743 /* Create a new pool. */
1744 pool = xmalloc (sizeof (* pool));
1745 if (! pool)
1746 return NULL;
1748 pool->next_free_entry = 0;
1749 pool->section = now_seg;
1750 pool->sub_section = now_subseg;
1751 pool->next = list_of_pools;
1752 pool->symbol = NULL;
1754 /* Add it to the list. */
1755 list_of_pools = pool;
1758 /* New pools, and emptied pools, will have a NULL symbol. */
1759 if (pool->symbol == NULL)
1761 pool->symbol = symbol_create (FAKE_LABEL_NAME, undefined_section,
1762 (valueT) 0, &zero_address_frag);
1763 pool->id = latest_pool_num ++;
1766 /* Done. */
1767 return pool;
1770 /* Add the literal in the global 'inst'
1771 structure to the relevent literal pool. */
1773 static int
1774 add_to_lit_pool (void)
1776 literal_pool * pool;
1777 unsigned int entry;
1779 pool = find_or_make_literal_pool ();
1781 /* Check if this literal value is already in the pool. */
1782 for (entry = 0; entry < pool->next_free_entry; entry ++)
1784 if ((pool->literals[entry].X_op == inst.reloc.exp.X_op)
1785 && (inst.reloc.exp.X_op == O_constant)
1786 && (pool->literals[entry].X_add_number
1787 == inst.reloc.exp.X_add_number)
1788 && (pool->literals[entry].X_unsigned
1789 == inst.reloc.exp.X_unsigned))
1790 break;
1792 if ((pool->literals[entry].X_op == inst.reloc.exp.X_op)
1793 && (inst.reloc.exp.X_op == O_symbol)
1794 && (pool->literals[entry].X_add_number
1795 == inst.reloc.exp.X_add_number)
1796 && (pool->literals[entry].X_add_symbol
1797 == inst.reloc.exp.X_add_symbol)
1798 && (pool->literals[entry].X_op_symbol
1799 == inst.reloc.exp.X_op_symbol))
1800 break;
1803 /* Do we need to create a new entry? */
1804 if (entry == pool->next_free_entry)
1806 if (entry >= MAX_LITERAL_POOL_SIZE)
1808 inst.error = _("literal pool overflow");
1809 return FAIL;
1812 pool->literals[entry] = inst.reloc.exp;
1813 pool->next_free_entry += 1;
1816 inst.reloc.exp.X_op = O_symbol;
1817 inst.reloc.exp.X_add_number = ((int) entry) * 4;
1818 inst.reloc.exp.X_add_symbol = pool->symbol;
1820 return SUCCESS;
1823 /* Can't use symbol_new here, so have to create a symbol and then at
1824 a later date assign it a value. Thats what these functions do. */
1826 static void
1827 symbol_locate (symbolS * symbolP,
1828 const char * name, /* It is copied, the caller can modify. */
1829 segT segment, /* Segment identifier (SEG_<something>). */
1830 valueT valu, /* Symbol value. */
1831 fragS * frag) /* Associated fragment. */
1833 unsigned int name_length;
1834 char * preserved_copy_of_name;
1836 name_length = strlen (name) + 1; /* +1 for \0. */
1837 obstack_grow (&notes, name, name_length);
1838 preserved_copy_of_name = obstack_finish (&notes);
1840 #ifdef tc_canonicalize_symbol_name
1841 preserved_copy_of_name =
1842 tc_canonicalize_symbol_name (preserved_copy_of_name);
1843 #endif
1845 S_SET_NAME (symbolP, preserved_copy_of_name);
1847 S_SET_SEGMENT (symbolP, segment);
1848 S_SET_VALUE (symbolP, valu);
1849 symbol_clear_list_pointers (symbolP);
1851 symbol_set_frag (symbolP, frag);
1853 /* Link to end of symbol chain. */
1855 extern int symbol_table_frozen;
1857 if (symbol_table_frozen)
1858 abort ();
1861 symbol_append (symbolP, symbol_lastP, & symbol_rootP, & symbol_lastP);
1863 obj_symbol_new_hook (symbolP);
1865 #ifdef tc_symbol_new_hook
1866 tc_symbol_new_hook (symbolP);
1867 #endif
1869 #ifdef DEBUG_SYMS
1870 verify_symbol_chain (symbol_rootP, symbol_lastP);
1871 #endif /* DEBUG_SYMS */
1875 static void
1876 s_ltorg (int ignored ATTRIBUTE_UNUSED)
1878 unsigned int entry;
1879 literal_pool * pool;
1880 char sym_name[20];
1882 pool = find_literal_pool ();
1883 if (pool == NULL
1884 || pool->symbol == NULL
1885 || pool->next_free_entry == 0)
1886 return;
1888 mapping_state (MAP_DATA);
1890 /* Align pool as you have word accesses.
1891 Only make a frag if we have to. */
1892 if (!need_pass_2)
1893 frag_align (2, 0, 0);
1895 record_alignment (now_seg, 2);
1897 sprintf (sym_name, "$$lit_\002%x", pool->id);
1899 symbol_locate (pool->symbol, sym_name, now_seg,
1900 (valueT) frag_now_fix (), frag_now);
1901 symbol_table_insert (pool->symbol);
1903 ARM_SET_THUMB (pool->symbol, thumb_mode);
1905 #if defined OBJ_COFF || defined OBJ_ELF
1906 ARM_SET_INTERWORK (pool->symbol, support_interwork);
1907 #endif
1909 for (entry = 0; entry < pool->next_free_entry; entry ++)
1910 /* First output the expression in the instruction to the pool. */
1911 emit_expr (&(pool->literals[entry]), 4); /* .word */
1913 /* Mark the pool as empty. */
1914 pool->next_free_entry = 0;
1915 pool->symbol = NULL;
1918 #ifdef OBJ_ELF
1919 /* Forward declarations for functions below, in the MD interface
1920 section. */
1921 static void fix_new_arm (fragS *, int, short, expressionS *, int, int);
1922 static valueT create_unwind_entry (int);
1923 static void start_unwind_section (const segT, int);
1924 static void add_unwind_opcode (valueT, int);
1925 static void flush_pending_unwind (void);
1927 /* Directives: Data. */
1929 static void
1930 s_arm_elf_cons (int nbytes)
1932 expressionS exp;
1934 #ifdef md_flush_pending_output
1935 md_flush_pending_output ();
1936 #endif
1938 if (is_it_end_of_statement ())
1940 demand_empty_rest_of_line ();
1941 return;
1944 #ifdef md_cons_align
1945 md_cons_align (nbytes);
1946 #endif
1948 mapping_state (MAP_DATA);
1951 int reloc;
1952 char *base = input_line_pointer;
1954 expression (& exp);
1956 if (exp.X_op != O_symbol)
1957 emit_expr (&exp, (unsigned int) nbytes);
1958 else
1960 char *before_reloc = input_line_pointer;
1961 reloc = parse_reloc (&input_line_pointer);
1962 if (reloc == -1)
1964 as_bad (_("unrecognized relocation suffix"));
1965 ignore_rest_of_line ();
1966 return;
1968 else if (reloc == BFD_RELOC_UNUSED)
1969 emit_expr (&exp, (unsigned int) nbytes);
1970 else
1972 reloc_howto_type *howto = bfd_reloc_type_lookup (stdoutput, reloc);
1973 int size = bfd_get_reloc_size (howto);
1975 if (reloc == BFD_RELOC_ARM_PLT32)
1977 as_bad (_("(plt) is only valid on branch targets"));
1978 reloc = BFD_RELOC_UNUSED;
1979 size = 0;
1982 if (size > nbytes)
1983 as_bad (_("%s relocations do not fit in %d bytes"),
1984 howto->name, nbytes);
1985 else
1987 /* We've parsed an expression stopping at O_symbol.
1988 But there may be more expression left now that we
1989 have parsed the relocation marker. Parse it again.
1990 XXX Surely there is a cleaner way to do this. */
1991 char *p = input_line_pointer;
1992 int offset;
1993 char *save_buf = alloca (input_line_pointer - base);
1994 memcpy (save_buf, base, input_line_pointer - base);
1995 memmove (base + (input_line_pointer - before_reloc),
1996 base, before_reloc - base);
1998 input_line_pointer = base + (input_line_pointer-before_reloc);
1999 expression (&exp);
2000 memcpy (base, save_buf, p - base);
2002 offset = nbytes - size;
2003 p = frag_more ((int) nbytes);
2004 fix_new_exp (frag_now, p - frag_now->fr_literal + offset,
2005 size, &exp, 0, reloc);
2010 while (*input_line_pointer++ == ',');
2012 /* Put terminator back into stream. */
2013 input_line_pointer --;
2014 demand_empty_rest_of_line ();
2018 /* Parse a .rel31 directive. */
2020 static void
2021 s_arm_rel31 (int ignored ATTRIBUTE_UNUSED)
2023 expressionS exp;
2024 char *p;
2025 valueT highbit;
2027 highbit = 0;
2028 if (*input_line_pointer == '1')
2029 highbit = 0x80000000;
2030 else if (*input_line_pointer != '0')
2031 as_bad (_("expected 0 or 1"));
2033 input_line_pointer++;
2034 if (*input_line_pointer != ',')
2035 as_bad (_("missing comma"));
2036 input_line_pointer++;
2038 #ifdef md_flush_pending_output
2039 md_flush_pending_output ();
2040 #endif
2042 #ifdef md_cons_align
2043 md_cons_align (4);
2044 #endif
2046 mapping_state (MAP_DATA);
2048 expression (&exp);
2050 p = frag_more (4);
2051 md_number_to_chars (p, highbit, 4);
2052 fix_new_arm (frag_now, p - frag_now->fr_literal, 4, &exp, 1,
2053 BFD_RELOC_ARM_PREL31);
2055 demand_empty_rest_of_line ();
2058 /* Directives: AEABI stack-unwind tables. */
2060 /* Parse an unwind_fnstart directive. Simply records the current location. */
2062 static void
2063 s_arm_unwind_fnstart (int ignored ATTRIBUTE_UNUSED)
2065 demand_empty_rest_of_line ();
2066 /* Mark the start of the function. */
2067 unwind.proc_start = expr_build_dot ();
2069 /* Reset the rest of the unwind info. */
2070 unwind.opcode_count = 0;
2071 unwind.table_entry = NULL;
2072 unwind.personality_routine = NULL;
2073 unwind.personality_index = -1;
2074 unwind.frame_size = 0;
2075 unwind.fp_offset = 0;
2076 unwind.fp_reg = 13;
2077 unwind.fp_used = 0;
2078 unwind.sp_restored = 0;
2082 /* Parse a handlerdata directive. Creates the exception handling table entry
2083 for the function. */
2085 static void
2086 s_arm_unwind_handlerdata (int ignored ATTRIBUTE_UNUSED)
2088 demand_empty_rest_of_line ();
2089 if (unwind.table_entry)
2090 as_bad (_("dupicate .handlerdata directive"));
2092 create_unwind_entry (1);
2095 /* Parse an unwind_fnend directive. Generates the index table entry. */
2097 static void
2098 s_arm_unwind_fnend (int ignored ATTRIBUTE_UNUSED)
2100 long where;
2101 char *ptr;
2102 valueT val;
2104 demand_empty_rest_of_line ();
2106 /* Add eh table entry. */
2107 if (unwind.table_entry == NULL)
2108 val = create_unwind_entry (0);
2109 else
2110 val = 0;
2112 /* Add index table entry. This is two words. */
2113 start_unwind_section (unwind.saved_seg, 1);
2114 frag_align (2, 0, 0);
2115 record_alignment (now_seg, 2);
2117 ptr = frag_more (8);
2118 where = frag_now_fix () - 8;
2120 /* Self relative offset of the function start. */
2121 fix_new (frag_now, where, 4, unwind.proc_start, 0, 1,
2122 BFD_RELOC_ARM_PREL31);
2124 /* Indicate dependency on EHABI-defined personality routines to the
2125 linker, if it hasn't been done already. */
2126 if (unwind.personality_index >= 0 && unwind.personality_index < 3
2127 && !(marked_pr_dependency & (1 << unwind.personality_index)))
2129 static const char *const name[] = {
2130 "__aeabi_unwind_cpp_pr0",
2131 "__aeabi_unwind_cpp_pr1",
2132 "__aeabi_unwind_cpp_pr2"
2134 symbolS *pr = symbol_find_or_make (name[unwind.personality_index]);
2135 fix_new (frag_now, where, 0, pr, 0, 1, BFD_RELOC_NONE);
2136 marked_pr_dependency |= 1 << unwind.personality_index;
2137 seg_info (now_seg)->tc_segment_info_data.marked_pr_dependency
2138 = marked_pr_dependency;
2141 if (val)
2142 /* Inline exception table entry. */
2143 md_number_to_chars (ptr + 4, val, 4);
2144 else
2145 /* Self relative offset of the table entry. */
2146 fix_new (frag_now, where + 4, 4, unwind.table_entry, 0, 1,
2147 BFD_RELOC_ARM_PREL31);
2149 /* Restore the original section. */
2150 subseg_set (unwind.saved_seg, unwind.saved_subseg);
2154 /* Parse an unwind_cantunwind directive. */
2156 static void
2157 s_arm_unwind_cantunwind (int ignored ATTRIBUTE_UNUSED)
2159 demand_empty_rest_of_line ();
2160 if (unwind.personality_routine || unwind.personality_index != -1)
2161 as_bad (_("personality routine specified for cantunwind frame"));
2163 unwind.personality_index = -2;
2167 /* Parse a personalityindex directive. */
2169 static void
2170 s_arm_unwind_personalityindex (int ignored ATTRIBUTE_UNUSED)
2172 expressionS exp;
2174 if (unwind.personality_routine || unwind.personality_index != -1)
2175 as_bad (_("duplicate .personalityindex directive"));
2177 expression (&exp);
2179 if (exp.X_op != O_constant
2180 || exp.X_add_number < 0 || exp.X_add_number > 15)
2182 as_bad (_("bad personality routine number"));
2183 ignore_rest_of_line ();
2184 return;
2187 unwind.personality_index = exp.X_add_number;
2189 demand_empty_rest_of_line ();
2193 /* Parse a personality directive. */
2195 static void
2196 s_arm_unwind_personality (int ignored ATTRIBUTE_UNUSED)
2198 char *name, *p, c;
2200 if (unwind.personality_routine || unwind.personality_index != -1)
2201 as_bad (_("duplicate .personality directive"));
2203 name = input_line_pointer;
2204 c = get_symbol_end ();
2205 p = input_line_pointer;
2206 unwind.personality_routine = symbol_find_or_make (name);
2207 *p = c;
2208 demand_empty_rest_of_line ();
2212 /* Parse a directive saving core registers. */
2214 static void
2215 s_arm_unwind_save_core (void)
2217 valueT op;
2218 long range;
2219 int n;
2221 range = parse_reg_list (&input_line_pointer);
2222 if (range == FAIL)
2224 as_bad (_("expected register list"));
2225 ignore_rest_of_line ();
2226 return;
2229 demand_empty_rest_of_line ();
2231 /* Turn .unwind_movsp ip followed by .unwind_save {..., ip, ...}
2232 into .unwind_save {..., sp...}. We aren't bothered about the value of
2233 ip because it is clobbered by calls. */
2234 if (unwind.sp_restored && unwind.fp_reg == 12
2235 && (range & 0x3000) == 0x1000)
2237 unwind.opcode_count--;
2238 unwind.sp_restored = 0;
2239 range = (range | 0x2000) & ~0x1000;
2240 unwind.pending_offset = 0;
2243 /* See if we can use the short opcodes. These pop a block of upto 8
2244 registers starting with r4, plus maybe r14. */
2245 for (n = 0; n < 8; n++)
2247 /* Break at the first non-saved register. */
2248 if ((range & (1 << (n + 4))) == 0)
2249 break;
2251 /* See if there are any other bits set. */
2252 if (n == 0 || (range & (0xfff0 << n) & 0xbff0) != 0)
2254 /* Use the long form. */
2255 op = 0x8000 | ((range >> 4) & 0xfff);
2256 add_unwind_opcode (op, 2);
2258 else
2260 /* Use the short form. */
2261 if (range & 0x4000)
2262 op = 0xa8; /* Pop r14. */
2263 else
2264 op = 0xa0; /* Do not pop r14. */
2265 op |= (n - 1);
2266 add_unwind_opcode (op, 1);
2269 /* Pop r0-r3. */
2270 if (range & 0xf)
2272 op = 0xb100 | (range & 0xf);
2273 add_unwind_opcode (op, 2);
2276 /* Record the number of bytes pushed. */
2277 for (n = 0; n < 16; n++)
2279 if (range & (1 << n))
2280 unwind.frame_size += 4;
2285 /* Parse a directive saving FPA registers. */
2287 static void
2288 s_arm_unwind_save_fpa (int reg)
2290 expressionS exp;
2291 int num_regs;
2292 valueT op;
2294 /* Get Number of registers to transfer. */
2295 if (skip_past_comma (&input_line_pointer) != FAIL)
2296 expression (&exp);
2297 else
2298 exp.X_op = O_illegal;
2300 if (exp.X_op != O_constant)
2302 as_bad (_("expected , <constant>"));
2303 ignore_rest_of_line ();
2304 return;
2307 num_regs = exp.X_add_number;
2309 if (num_regs < 1 || num_regs > 4)
2311 as_bad (_("number of registers must be in the range [1:4]"));
2312 ignore_rest_of_line ();
2313 return;
2316 demand_empty_rest_of_line ();
2318 if (reg == 4)
2320 /* Short form. */
2321 op = 0xb4 | (num_regs - 1);
2322 add_unwind_opcode (op, 1);
2324 else
2326 /* Long form. */
2327 op = 0xc800 | (reg << 4) | (num_regs - 1);
2328 add_unwind_opcode (op, 2);
2330 unwind.frame_size += num_regs * 12;
2334 /* Parse a directive saving VFP registers. */
2336 static void
2337 s_arm_unwind_save_vfp (void)
2339 int count;
2340 unsigned int reg;
2341 valueT op;
2343 count = parse_vfp_reg_list (&input_line_pointer, &reg, 1);
2344 if (count == FAIL)
2346 as_bad (_("expected register list"));
2347 ignore_rest_of_line ();
2348 return;
2351 demand_empty_rest_of_line ();
2353 if (reg == 8)
2355 /* Short form. */
2356 op = 0xb8 | (count - 1);
2357 add_unwind_opcode (op, 1);
2359 else
2361 /* Long form. */
2362 op = 0xb300 | (reg << 4) | (count - 1);
2363 add_unwind_opcode (op, 2);
2365 unwind.frame_size += count * 8 + 4;
2369 /* Parse a directive saving iWMMXt data registers. */
2371 static void
2372 s_arm_unwind_save_mmxwr (void)
2374 int reg;
2375 int hi_reg;
2376 int i;
2377 unsigned mask = 0;
2378 valueT op;
2380 if (*input_line_pointer == '{')
2381 input_line_pointer++;
2385 reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWR);
2387 if (reg == FAIL)
2389 as_bad (_(reg_expected_msgs[REG_TYPE_MMXWR]));
2390 goto error;
2393 if (mask >> reg)
2394 as_tsktsk (_("register list not in ascending order"));
2395 mask |= 1 << reg;
2397 if (*input_line_pointer == '-')
2399 input_line_pointer++;
2400 hi_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWR);
2401 if (hi_reg == FAIL)
2403 as_bad (_(reg_expected_msgs[REG_TYPE_MMXWR]));
2404 goto error;
2406 else if (reg >= hi_reg)
2408 as_bad (_("bad register range"));
2409 goto error;
2411 for (; reg < hi_reg; reg++)
2412 mask |= 1 << reg;
2415 while (skip_past_comma (&input_line_pointer) != FAIL);
2417 if (*input_line_pointer == '}')
2418 input_line_pointer++;
2420 demand_empty_rest_of_line ();
2422 /* Generate any deferred opcodes becuuse we're going to be looking at
2423 the list. */
2424 flush_pending_unwind ();
2426 for (i = 0; i < 16; i++)
2428 if (mask & (1 << i))
2429 unwind.frame_size += 8;
2432 /* Attempt to combine with a previous opcode. We do this because gcc
2433 likes to output separate unwind directives for a single block of
2434 registers. */
2435 if (unwind.opcode_count > 0)
2437 i = unwind.opcodes[unwind.opcode_count - 1];
2438 if ((i & 0xf8) == 0xc0)
2440 i &= 7;
2441 /* Only merge if the blocks are contiguous. */
2442 if (i < 6)
2444 if ((mask & 0xfe00) == (1 << 9))
2446 mask |= ((1 << (i + 11)) - 1) & 0xfc00;
2447 unwind.opcode_count--;
2450 else if (i == 6 && unwind.opcode_count >= 2)
2452 i = unwind.opcodes[unwind.opcode_count - 2];
2453 reg = i >> 4;
2454 i &= 0xf;
2456 op = 0xffff << (reg - 1);
2457 if (reg > 0
2458 || ((mask & op) == (1u << (reg - 1))))
2460 op = (1 << (reg + i + 1)) - 1;
2461 op &= ~((1 << reg) - 1);
2462 mask |= op;
2463 unwind.opcode_count -= 2;
2469 hi_reg = 15;
2470 /* We want to generate opcodes in the order the registers have been
2471 saved, ie. descending order. */
2472 for (reg = 15; reg >= -1; reg--)
2474 /* Save registers in blocks. */
2475 if (reg < 0
2476 || !(mask & (1 << reg)))
2478 /* We found an unsaved reg. Generate opcodes to save the
2479 preceeding block. */
2480 if (reg != hi_reg)
2482 if (reg == 9)
2484 /* Short form. */
2485 op = 0xc0 | (hi_reg - 10);
2486 add_unwind_opcode (op, 1);
2488 else
2490 /* Long form. */
2491 op = 0xc600 | ((reg + 1) << 4) | ((hi_reg - reg) - 1);
2492 add_unwind_opcode (op, 2);
2495 hi_reg = reg - 1;
2499 return;
2500 error:
2501 ignore_rest_of_line ();
2504 static void
2505 s_arm_unwind_save_mmxwcg (void)
2507 int reg;
2508 int hi_reg;
2509 unsigned mask = 0;
2510 valueT op;
2512 if (*input_line_pointer == '{')
2513 input_line_pointer++;
2517 reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWCG);
2519 if (reg == FAIL)
2521 as_bad (_(reg_expected_msgs[REG_TYPE_MMXWCG]));
2522 goto error;
2525 reg -= 8;
2526 if (mask >> reg)
2527 as_tsktsk (_("register list not in ascending order"));
2528 mask |= 1 << reg;
2530 if (*input_line_pointer == '-')
2532 input_line_pointer++;
2533 hi_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWCG);
2534 if (hi_reg == FAIL)
2536 as_bad (_(reg_expected_msgs[REG_TYPE_MMXWCG]));
2537 goto error;
2539 else if (reg >= hi_reg)
2541 as_bad (_("bad register range"));
2542 goto error;
2544 for (; reg < hi_reg; reg++)
2545 mask |= 1 << reg;
2548 while (skip_past_comma (&input_line_pointer) != FAIL);
2550 if (*input_line_pointer == '}')
2551 input_line_pointer++;
2553 demand_empty_rest_of_line ();
2555 /* Generate any deferred opcodes becuuse we're going to be looking at
2556 the list. */
2557 flush_pending_unwind ();
2559 for (reg = 0; reg < 16; reg++)
2561 if (mask & (1 << reg))
2562 unwind.frame_size += 4;
2564 op = 0xc700 | mask;
2565 add_unwind_opcode (op, 2);
2566 return;
2567 error:
2568 ignore_rest_of_line ();
2572 /* Parse an unwind_save directive. */
2574 static void
2575 s_arm_unwind_save (int ignored ATTRIBUTE_UNUSED)
2577 char *peek;
2578 struct reg_entry *reg;
2579 bfd_boolean had_brace = FALSE;
2581 /* Figure out what sort of save we have. */
2582 peek = input_line_pointer;
2584 if (*peek == '{')
2586 had_brace = TRUE;
2587 peek++;
2590 reg = arm_reg_parse_multi (&peek);
2592 if (!reg)
2594 as_bad (_("register expected"));
2595 ignore_rest_of_line ();
2596 return;
2599 switch (reg->type)
2601 case REG_TYPE_FN:
2602 if (had_brace)
2604 as_bad (_("FPA .unwind_save does not take a register list"));
2605 ignore_rest_of_line ();
2606 return;
2608 s_arm_unwind_save_fpa (reg->number);
2609 return;
2611 case REG_TYPE_RN: s_arm_unwind_save_core (); return;
2612 case REG_TYPE_VFD: s_arm_unwind_save_vfp (); return;
2613 case REG_TYPE_MMXWR: s_arm_unwind_save_mmxwr (); return;
2614 case REG_TYPE_MMXWCG: s_arm_unwind_save_mmxwcg (); return;
2616 default:
2617 as_bad (_(".unwind_save does not support this kind of register"));
2618 ignore_rest_of_line ();
2623 /* Parse an unwind_movsp directive. */
2625 static void
2626 s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED)
2628 int reg;
2629 valueT op;
2631 reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN);
2632 if (reg == FAIL)
2634 as_bad (_(reg_expected_msgs[REG_TYPE_RN]));
2635 ignore_rest_of_line ();
2636 return;
2638 demand_empty_rest_of_line ();
2640 if (reg == REG_SP || reg == REG_PC)
2642 as_bad (_("SP and PC not permitted in .unwind_movsp directive"));
2643 return;
2646 if (unwind.fp_reg != REG_SP)
2647 as_bad (_("unexpected .unwind_movsp directive"));
2649 /* Generate opcode to restore the value. */
2650 op = 0x90 | reg;
2651 add_unwind_opcode (op, 1);
2653 /* Record the information for later. */
2654 unwind.fp_reg = reg;
2655 unwind.fp_offset = unwind.frame_size;
2656 unwind.sp_restored = 1;
2659 /* Parse an unwind_pad directive. */
2661 static void
2662 s_arm_unwind_pad (int ignored ATTRIBUTE_UNUSED)
2664 int offset;
2666 if (immediate_for_directive (&offset) == FAIL)
2667 return;
2669 if (offset & 3)
2671 as_bad (_("stack increment must be multiple of 4"));
2672 ignore_rest_of_line ();
2673 return;
2676 /* Don't generate any opcodes, just record the details for later. */
2677 unwind.frame_size += offset;
2678 unwind.pending_offset += offset;
2680 demand_empty_rest_of_line ();
2683 /* Parse an unwind_setfp directive. */
2685 static void
2686 s_arm_unwind_setfp (int ignored ATTRIBUTE_UNUSED)
2688 int sp_reg;
2689 int fp_reg;
2690 int offset;
2692 fp_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN);
2693 if (skip_past_comma (&input_line_pointer) == FAIL)
2694 sp_reg = FAIL;
2695 else
2696 sp_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN);
2698 if (fp_reg == FAIL || sp_reg == FAIL)
2700 as_bad (_("expected <reg>, <reg>"));
2701 ignore_rest_of_line ();
2702 return;
2705 /* Optional constant. */
2706 if (skip_past_comma (&input_line_pointer) != FAIL)
2708 if (immediate_for_directive (&offset) == FAIL)
2709 return;
2711 else
2712 offset = 0;
2714 demand_empty_rest_of_line ();
2716 if (sp_reg != 13 && sp_reg != unwind.fp_reg)
2718 as_bad (_("register must be either sp or set by a previous"
2719 "unwind_movsp directive"));
2720 return;
2723 /* Don't generate any opcodes, just record the information for later. */
2724 unwind.fp_reg = fp_reg;
2725 unwind.fp_used = 1;
2726 if (sp_reg == 13)
2727 unwind.fp_offset = unwind.frame_size - offset;
2728 else
2729 unwind.fp_offset -= offset;
2732 /* Parse an unwind_raw directive. */
2734 static void
2735 s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED)
2737 expressionS exp;
2738 /* This is an arbitary limit. */
2739 unsigned char op[16];
2740 int count;
2742 expression (&exp);
2743 if (exp.X_op == O_constant
2744 && skip_past_comma (&input_line_pointer) != FAIL)
2746 unwind.frame_size += exp.X_add_number;
2747 expression (&exp);
2749 else
2750 exp.X_op = O_illegal;
2752 if (exp.X_op != O_constant)
2754 as_bad (_("expected <offset>, <opcode>"));
2755 ignore_rest_of_line ();
2756 return;
2759 count = 0;
2761 /* Parse the opcode. */
2762 for (;;)
2764 if (count >= 16)
2766 as_bad (_("unwind opcode too long"));
2767 ignore_rest_of_line ();
2769 if (exp.X_op != O_constant || exp.X_add_number & ~0xff)
2771 as_bad (_("invalid unwind opcode"));
2772 ignore_rest_of_line ();
2773 return;
2775 op[count++] = exp.X_add_number;
2777 /* Parse the next byte. */
2778 if (skip_past_comma (&input_line_pointer) == FAIL)
2779 break;
2781 expression (&exp);
2784 /* Add the opcode bytes in reverse order. */
2785 while (count--)
2786 add_unwind_opcode (op[count], 1);
2788 demand_empty_rest_of_line ();
2790 #endif /* OBJ_ELF */
2792 /* This table describes all the machine specific pseudo-ops the assembler
2793 has to support. The fields are:
2794 pseudo-op name without dot
2795 function to call to execute this pseudo-op
2796 Integer arg to pass to the function. */
2798 const pseudo_typeS md_pseudo_table[] =
2800 /* Never called because '.req' does not start a line. */
2801 { "req", s_req, 0 },
2802 { "unreq", s_unreq, 0 },
2803 { "bss", s_bss, 0 },
2804 { "align", s_align, 0 },
2805 { "arm", s_arm, 0 },
2806 { "thumb", s_thumb, 0 },
2807 { "code", s_code, 0 },
2808 { "force_thumb", s_force_thumb, 0 },
2809 { "thumb_func", s_thumb_func, 0 },
2810 { "thumb_set", s_thumb_set, 0 },
2811 { "even", s_even, 0 },
2812 { "ltorg", s_ltorg, 0 },
2813 { "pool", s_ltorg, 0 },
2814 { "syntax", s_syntax, 0 },
2815 #ifdef OBJ_ELF
2816 { "word", s_arm_elf_cons, 4 },
2817 { "long", s_arm_elf_cons, 4 },
2818 { "rel31", s_arm_rel31, 0 },
2819 { "fnstart", s_arm_unwind_fnstart, 0 },
2820 { "fnend", s_arm_unwind_fnend, 0 },
2821 { "cantunwind", s_arm_unwind_cantunwind, 0 },
2822 { "personality", s_arm_unwind_personality, 0 },
2823 { "personalityindex", s_arm_unwind_personalityindex, 0 },
2824 { "handlerdata", s_arm_unwind_handlerdata, 0 },
2825 { "save", s_arm_unwind_save, 0 },
2826 { "movsp", s_arm_unwind_movsp, 0 },
2827 { "pad", s_arm_unwind_pad, 0 },
2828 { "setfp", s_arm_unwind_setfp, 0 },
2829 { "unwind_raw", s_arm_unwind_raw, 0 },
2830 #else
2831 { "word", cons, 4},
2832 #endif
2833 { "extend", float_cons, 'x' },
2834 { "ldouble", float_cons, 'x' },
2835 { "packed", float_cons, 'p' },
2836 { 0, 0, 0 }
2839 /* Parser functions used exclusively in instruction operands. */
2841 /* Generic immediate-value read function for use in insn parsing.
2842 STR points to the beginning of the immediate (the leading #);
2843 VAL receives the value; if the value is outside [MIN, MAX]
2844 issue an error. PREFIX_OPT is true if the immediate prefix is
2845 optional. */
2847 static int
2848 parse_immediate (char **str, int *val, int min, int max,
2849 bfd_boolean prefix_opt)
2851 expressionS exp;
2852 my_get_expression (&exp, str, prefix_opt ? GE_OPT_PREFIX : GE_IMM_PREFIX);
2853 if (exp.X_op != O_constant)
2855 inst.error = _("constant expression required");
2856 return FAIL;
2859 if (exp.X_add_number < min || exp.X_add_number > max)
2861 inst.error = _("immediate value out of range");
2862 return FAIL;
2865 *val = exp.X_add_number;
2866 return SUCCESS;
2869 /* Returns the pseudo-register number of an FPA immediate constant,
2870 or FAIL if there isn't a valid constant here. */
2872 static int
2873 parse_fpa_immediate (char ** str)
2875 LITTLENUM_TYPE words[MAX_LITTLENUMS];
2876 char * save_in;
2877 expressionS exp;
2878 int i;
2879 int j;
2881 /* First try and match exact strings, this is to guarantee
2882 that some formats will work even for cross assembly. */
2884 for (i = 0; fp_const[i]; i++)
2886 if (strncmp (*str, fp_const[i], strlen (fp_const[i])) == 0)
2888 char *start = *str;
2890 *str += strlen (fp_const[i]);
2891 if (is_end_of_line[(unsigned char) **str])
2892 return i + 8;
2893 *str = start;
2897 /* Just because we didn't get a match doesn't mean that the constant
2898 isn't valid, just that it is in a format that we don't
2899 automatically recognize. Try parsing it with the standard
2900 expression routines. */
2902 memset (words, 0, MAX_LITTLENUMS * sizeof (LITTLENUM_TYPE));
2904 /* Look for a raw floating point number. */
2905 if ((save_in = atof_ieee (*str, 'x', words)) != NULL
2906 && is_end_of_line[(unsigned char) *save_in])
2908 for (i = 0; i < NUM_FLOAT_VALS; i++)
2910 for (j = 0; j < MAX_LITTLENUMS; j++)
2912 if (words[j] != fp_values[i][j])
2913 break;
2916 if (j == MAX_LITTLENUMS)
2918 *str = save_in;
2919 return i + 8;
2924 /* Try and parse a more complex expression, this will probably fail
2925 unless the code uses a floating point prefix (eg "0f"). */
2926 save_in = input_line_pointer;
2927 input_line_pointer = *str;
2928 if (expression (&exp) == absolute_section
2929 && exp.X_op == O_big
2930 && exp.X_add_number < 0)
2932 /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it.
2933 Ditto for 15. */
2934 if (gen_to_words (words, 5, (long) 15) == 0)
2936 for (i = 0; i < NUM_FLOAT_VALS; i++)
2938 for (j = 0; j < MAX_LITTLENUMS; j++)
2940 if (words[j] != fp_values[i][j])
2941 break;
2944 if (j == MAX_LITTLENUMS)
2946 *str = input_line_pointer;
2947 input_line_pointer = save_in;
2948 return i + 8;
2954 *str = input_line_pointer;
2955 input_line_pointer = save_in;
2956 inst.error = _("invalid FPA immediate expression");
2957 return FAIL;
2960 /* Shift operands. */
2961 enum shift_kind
2963 SHIFT_LSL, SHIFT_LSR, SHIFT_ASR, SHIFT_ROR, SHIFT_RRX
2966 struct asm_shift_name
2968 const char *name;
2969 enum shift_kind kind;
2972 /* Third argument to parse_shift. */
2973 enum parse_shift_mode
2975 NO_SHIFT_RESTRICT, /* Any kind of shift is accepted. */
2976 SHIFT_IMMEDIATE, /* Shift operand must be an immediate. */
2977 SHIFT_LSL_OR_ASR_IMMEDIATE, /* Shift must be LSL or ASR immediate. */
2978 SHIFT_ASR_IMMEDIATE, /* Shift must be ASR immediate. */
2979 SHIFT_LSL_IMMEDIATE, /* Shift must be LSL immediate. */
2982 /* Parse a <shift> specifier on an ARM data processing instruction.
2983 This has three forms:
2985 (LSL|LSR|ASL|ASR|ROR) Rs
2986 (LSL|LSR|ASL|ASR|ROR) #imm
2989 Note that ASL is assimilated to LSL in the instruction encoding, and
2990 RRX to ROR #0 (which cannot be written as such). */
2992 static int
2993 parse_shift (char **str, int i, enum parse_shift_mode mode)
2995 const struct asm_shift_name *shift_name;
2996 enum shift_kind shift;
2997 char *s = *str;
2998 char *p = s;
2999 int reg;
3001 for (p = *str; ISALPHA (*p); p++)
3004 if (p == *str)
3006 inst.error = _("shift expression expected");
3007 return FAIL;
3010 shift_name = hash_find_n (arm_shift_hsh, *str, p - *str);
3012 if (shift_name == NULL)
3014 inst.error = _("shift expression expected");
3015 return FAIL;
3018 shift = shift_name->kind;
3020 switch (mode)
3022 case NO_SHIFT_RESTRICT:
3023 case SHIFT_IMMEDIATE: break;
3025 case SHIFT_LSL_OR_ASR_IMMEDIATE:
3026 if (shift != SHIFT_LSL && shift != SHIFT_ASR)
3028 inst.error = _("'LSL' or 'ASR' required");
3029 return FAIL;
3031 break;
3033 case SHIFT_LSL_IMMEDIATE:
3034 if (shift != SHIFT_LSL)
3036 inst.error = _("'LSL' required");
3037 return FAIL;
3039 break;
3041 case SHIFT_ASR_IMMEDIATE:
3042 if (shift != SHIFT_ASR)
3044 inst.error = _("'ASR' required");
3045 return FAIL;
3047 break;
3049 default: abort ();
3052 if (shift != SHIFT_RRX)
3054 /* Whitespace can appear here if the next thing is a bare digit. */
3055 skip_whitespace (p);
3057 if (mode == NO_SHIFT_RESTRICT
3058 && (reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL)
3060 inst.operands[i].imm = reg;
3061 inst.operands[i].immisreg = 1;
3063 else if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX))
3064 return FAIL;
3066 inst.operands[i].shift_kind = shift;
3067 inst.operands[i].shifted = 1;
3068 *str = p;
3069 return SUCCESS;
3072 /* Parse a <shifter_operand> for an ARM data processing instruction:
3074 #<immediate>
3075 #<immediate>, <rotate>
3076 <Rm>
3077 <Rm>, <shift>
3079 where <shift> is defined by parse_shift above, and <rotate> is a
3080 multiple of 2 between 0 and 30. Validation of immediate operands
3081 is deferred to md_apply_fix. */
3083 static int
3084 parse_shifter_operand (char **str, int i)
3086 int value;
3087 expressionS expr;
3089 if ((value = arm_reg_parse (str, REG_TYPE_RN)) != FAIL)
3091 inst.operands[i].reg = value;
3092 inst.operands[i].isreg = 1;
3094 /* parse_shift will override this if appropriate */
3095 inst.reloc.exp.X_op = O_constant;
3096 inst.reloc.exp.X_add_number = 0;
3098 if (skip_past_comma (str) == FAIL)
3099 return SUCCESS;
3101 /* Shift operation on register. */
3102 return parse_shift (str, i, NO_SHIFT_RESTRICT);
3105 if (my_get_expression (&inst.reloc.exp, str, GE_IMM_PREFIX))
3106 return FAIL;
3108 if (skip_past_comma (str) == SUCCESS)
3110 /* #x, y -- ie explicit rotation by Y. */
3111 if (my_get_expression (&expr, str, GE_NO_PREFIX))
3112 return FAIL;
3114 if (expr.X_op != O_constant || inst.reloc.exp.X_op != O_constant)
3116 inst.error = _("constant expression expected");
3117 return FAIL;
3120 value = expr.X_add_number;
3121 if (value < 0 || value > 30 || value % 2 != 0)
3123 inst.error = _("invalid rotation");
3124 return FAIL;
3126 if (inst.reloc.exp.X_add_number < 0 || inst.reloc.exp.X_add_number > 255)
3128 inst.error = _("invalid constant");
3129 return FAIL;
3132 /* Convert to decoded value. md_apply_fix will put it back. */
3133 inst.reloc.exp.X_add_number
3134 = (((inst.reloc.exp.X_add_number << (32 - value))
3135 | (inst.reloc.exp.X_add_number >> value)) & 0xffffffff);
3138 inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;
3139 inst.reloc.pc_rel = 0;
3140 return SUCCESS;
3143 /* Parse all forms of an ARM address expression. Information is written
3144 to inst.operands[i] and/or inst.reloc.
3146 Preindexed addressing (.preind=1):
3148 [Rn, #offset] .reg=Rn .reloc.exp=offset
3149 [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
3150 [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
3151 .shift_kind=shift .reloc.exp=shift_imm
3153 These three may have a trailing ! which causes .writeback to be set also.
3155 Postindexed addressing (.postind=1, .writeback=1):
3157 [Rn], #offset .reg=Rn .reloc.exp=offset
3158 [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
3159 [Rn], +/-Rm, shift .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
3160 .shift_kind=shift .reloc.exp=shift_imm
3162 Unindexed addressing (.preind=0, .postind=0):
3164 [Rn], {option} .reg=Rn .imm=option .immisreg=0
3166 Other:
3168 [Rn]{!} shorthand for [Rn,#0]{!}
3169 =immediate .isreg=0 .reloc.exp=immediate
3170 label .reg=PC .reloc.pc_rel=1 .reloc.exp=label
3172 It is the caller's responsibility to check for addressing modes not
3173 supported by the instruction, and to set inst.reloc.type. */
3175 static int
3176 parse_address (char **str, int i)
3178 char *p = *str;
3179 int reg;
3181 if (skip_past_char (&p, '[') == FAIL)
3183 if (skip_past_char (&p, '=') == FAIL)
3185 /* bare address - translate to PC-relative offset */
3186 inst.reloc.pc_rel = 1;
3187 inst.operands[i].reg = REG_PC;
3188 inst.operands[i].isreg = 1;
3189 inst.operands[i].preind = 1;
3191 /* else a load-constant pseudo op, no special treatment needed here */
3193 if (my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX))
3194 return FAIL;
3196 *str = p;
3197 return SUCCESS;
3200 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL)
3202 inst.error = _(reg_expected_msgs[REG_TYPE_RN]);
3203 return FAIL;
3205 inst.operands[i].reg = reg;
3206 inst.operands[i].isreg = 1;
3208 if (skip_past_comma (&p) == SUCCESS)
3210 inst.operands[i].preind = 1;
3212 if (*p == '+') p++;
3213 else if (*p == '-') p++, inst.operands[i].negative = 1;
3215 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL)
3217 inst.operands[i].imm = reg;
3218 inst.operands[i].immisreg = 1;
3220 if (skip_past_comma (&p) == SUCCESS)
3221 if (parse_shift (&p, i, SHIFT_IMMEDIATE) == FAIL)
3222 return FAIL;
3224 else
3226 if (inst.operands[i].negative)
3228 inst.operands[i].negative = 0;
3229 p--;
3231 if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX))
3232 return FAIL;
3236 if (skip_past_char (&p, ']') == FAIL)
3238 inst.error = _("']' expected");
3239 return FAIL;
3242 if (skip_past_char (&p, '!') == SUCCESS)
3243 inst.operands[i].writeback = 1;
3245 else if (skip_past_comma (&p) == SUCCESS)
3247 if (skip_past_char (&p, '{') == SUCCESS)
3249 /* [Rn], {expr} - unindexed, with option */
3250 if (parse_immediate (&p, &inst.operands[i].imm,
3251 0, 255, TRUE) == FAIL)
3252 return FAIL;
3254 if (skip_past_char (&p, '}') == FAIL)
3256 inst.error = _("'}' expected at end of 'option' field");
3257 return FAIL;
3259 if (inst.operands[i].preind)
3261 inst.error = _("cannot combine index with option");
3262 return FAIL;
3264 *str = p;
3265 return SUCCESS;
3267 else
3269 inst.operands[i].postind = 1;
3270 inst.operands[i].writeback = 1;
3272 if (inst.operands[i].preind)
3274 inst.error = _("cannot combine pre- and post-indexing");
3275 return FAIL;
3278 if (*p == '+') p++;
3279 else if (*p == '-') p++, inst.operands[i].negative = 1;
3281 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL)
3283 inst.operands[i].imm = reg;
3284 inst.operands[i].immisreg = 1;
3286 if (skip_past_comma (&p) == SUCCESS)
3287 if (parse_shift (&p, i, SHIFT_IMMEDIATE) == FAIL)
3288 return FAIL;
3290 else
3292 if (inst.operands[i].negative)
3294 inst.operands[i].negative = 0;
3295 p--;
3297 if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX))
3298 return FAIL;
3303 /* If at this point neither .preind nor .postind is set, we have a
3304 bare [Rn]{!}, which is shorthand for [Rn,#0]{!}. */
3305 if (inst.operands[i].preind == 0 && inst.operands[i].postind == 0)
3307 inst.operands[i].preind = 1;
3308 inst.reloc.exp.X_op = O_constant;
3309 inst.reloc.exp.X_add_number = 0;
3311 *str = p;
3312 return SUCCESS;
3315 /* Miscellaneous. */
3317 /* Parse a PSR flag operand. The value returned is FAIL on syntax error,
3318 or a bitmask suitable to be or-ed into the ARM msr instruction. */
3319 static int
3320 parse_psr (char **str)
3322 char *p;
3323 unsigned long psr_field;
3325 /* CPSR's and SPSR's can now be lowercase. This is just a convenience
3326 feature for ease of use and backwards compatibility. */
3327 p = *str;
3328 if (*p == 's' || *p == 'S')
3329 psr_field = SPSR_BIT;
3330 else if (*p == 'c' || *p == 'C')
3331 psr_field = 0;
3332 else
3333 goto error;
3335 p++;
3336 if (strncasecmp (p, "PSR", 3) != 0)
3337 goto error;
3338 p += 3;
3340 if (*p == '_')
3342 /* A suffix follows. */
3343 const struct asm_psr *psr;
3344 char *start;
3346 p++;
3347 start = p;
3350 p++;
3351 while (ISALNUM (*p) || *p == '_');
3353 psr = hash_find_n (arm_psr_hsh, start, p - start);
3354 if (!psr)
3355 goto error;
3357 psr_field |= psr->field;
3359 else
3361 if (ISALNUM (*p))
3362 goto error; /* Garbage after "[CS]PSR". */
3364 psr_field |= (PSR_c | PSR_f);
3366 *str = p;
3367 return psr_field;
3369 error:
3370 inst.error = _("flag for {c}psr instruction expected");
3371 return FAIL;
3374 /* Parse the flags argument to CPSI[ED]. Returns FAIL on error, or a
3375 value suitable for splatting into the AIF field of the instruction. */
3377 static int
3378 parse_cps_flags (char **str)
3380 int val = 0;
3381 int saw_a_flag = 0;
3382 char *s = *str;
3384 for (;;)
3385 switch (*s++)
3387 case '\0': case ',':
3388 goto done;
3390 case 'a': case 'A': saw_a_flag = 1; val |= 0x4; break;
3391 case 'i': case 'I': saw_a_flag = 1; val |= 0x2; break;
3392 case 'f': case 'F': saw_a_flag = 1; val |= 0x1; break;
3394 default:
3395 inst.error = _("unrecognized CPS flag");
3396 return FAIL;
3399 done:
3400 if (saw_a_flag == 0)
3402 inst.error = _("missing CPS flags");
3403 return FAIL;
3406 *str = s - 1;
3407 return val;
3410 /* Parse an endian specifier ("BE" or "LE", case insensitive);
3411 returns 0 for big-endian, 1 for little-endian, FAIL for an error. */
3413 static int
3414 parse_endian_specifier (char **str)
3416 int little_endian;
3417 char *s = *str;
3419 if (strncasecmp (s, "BE", 2))
3420 little_endian = 0;
3421 else if (strncasecmp (s, "LE", 2))
3422 little_endian = 1;
3423 else
3425 inst.error = _("valid endian specifiers are be or le");
3426 return FAIL;
3429 if (ISALNUM (s[2]) || s[2] == '_')
3431 inst.error = _("valid endian specifiers are be or le");
3432 return FAIL;
3435 *str = s + 2;
3436 return little_endian;
3439 /* Parse a rotation specifier: ROR #0, #8, #16, #24. *val receives a
3440 value suitable for poking into the rotate field of an sxt or sxta
3441 instruction, or FAIL on error. */
3443 static int
3444 parse_ror (char **str)
3446 int rot;
3447 char *s = *str;
3449 if (strncasecmp (s, "ROR", 3) == 0)
3450 s += 3;
3451 else
3453 inst.error = _("missing rotation field after comma");
3454 return FAIL;
3457 if (parse_immediate (&s, &rot, 0, 24, FALSE) == FAIL)
3458 return FAIL;
3460 switch (rot)
3462 case 0: *str = s; return 0x0;
3463 case 8: *str = s; return 0x1;
3464 case 16: *str = s; return 0x2;
3465 case 24: *str = s; return 0x3;
3467 default:
3468 inst.error = _("rotation can only be 0, 8, 16, or 24");
3469 return FAIL;
3473 /* Parse a conditional code (from conds[] below). The value returned is in the
3474 range 0 .. 14, or FAIL. */
3475 static int
3476 parse_cond (char **str)
3478 char *p, *q;
3479 const struct asm_cond *c;
3481 p = q = *str;
3482 while (ISALPHA (*q))
3483 q++;
3485 c = hash_find_n (arm_cond_hsh, p, q - p);
3486 if (!c)
3488 inst.error = _("condition required");
3489 return FAIL;
3492 *str = q;
3493 return c->value;
3496 /* Parse the operands of a table branch instruction. Similar to a memory
3497 operand. */
3498 static int
3499 parse_tb (char **str)
3501 char * p = *str;
3502 int reg;
3504 if (skip_past_char (&p, '[') == FAIL)
3505 return FAIL;
3507 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL)
3509 inst.error = _(reg_expected_msgs[REG_TYPE_RN]);
3510 return FAIL;
3512 inst.operands[0].reg = reg;
3514 if (skip_past_comma (&p) == FAIL)
3515 return FAIL;
3517 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL)
3519 inst.error = _(reg_expected_msgs[REG_TYPE_RN]);
3520 return FAIL;
3522 inst.operands[0].imm = reg;
3524 if (skip_past_comma (&p) == SUCCESS)
3526 if (parse_shift (&p, 0, SHIFT_LSL_IMMEDIATE) == FAIL)
3527 return FAIL;
3528 if (inst.reloc.exp.X_add_number != 1)
3530 inst.error = _("invalid shift");
3531 return FAIL;
3533 inst.operands[0].shifted = 1;
3536 if (skip_past_char (&p, ']') == FAIL)
3538 inst.error = _("']' expected");
3539 return FAIL;
3541 *str = p;
3542 return SUCCESS;
3545 /* Matcher codes for parse_operands. */
3546 enum operand_parse_code
3548 OP_stop, /* end of line */
3550 OP_RR, /* ARM register */
3551 OP_RRnpc, /* ARM register, not r15 */
3552 OP_RRnpcb, /* ARM register, not r15, in square brackets */
3553 OP_RRw, /* ARM register, not r15, optional trailing ! */
3554 OP_RCP, /* Coprocessor number */
3555 OP_RCN, /* Coprocessor register */
3556 OP_RF, /* FPA register */
3557 OP_RVS, /* VFP single precision register */
3558 OP_RVD, /* VFP double precision register */
3559 OP_RVC, /* VFP control register */
3560 OP_RMF, /* Maverick F register */
3561 OP_RMD, /* Maverick D register */
3562 OP_RMFX, /* Maverick FX register */
3563 OP_RMDX, /* Maverick DX register */
3564 OP_RMAX, /* Maverick AX register */
3565 OP_RMDS, /* Maverick DSPSC register */
3566 OP_RIWR, /* iWMMXt wR register */
3567 OP_RIWC, /* iWMMXt wC register */
3568 OP_RIWG, /* iWMMXt wCG register */
3569 OP_RXA, /* XScale accumulator register */
3571 OP_REGLST, /* ARM register list */
3572 OP_VRSLST, /* VFP single-precision register list */
3573 OP_VRDLST, /* VFP double-precision register list */
3575 OP_I7, /* immediate value 0 .. 7 */
3576 OP_I15, /* 0 .. 15 */
3577 OP_I16, /* 1 .. 16 */
3578 OP_I31, /* 0 .. 31 */
3579 OP_I31w, /* 0 .. 31, optional trailing ! */
3580 OP_I32, /* 1 .. 32 */
3581 OP_I63s, /* -64 .. 63 */
3582 OP_I255, /* 0 .. 255 */
3583 OP_Iffff, /* 0 .. 65535 */
3585 OP_I4b, /* immediate, prefix optional, 1 .. 4 */
3586 OP_I7b, /* 0 .. 7 */
3587 OP_I15b, /* 0 .. 15 */
3588 OP_I31b, /* 0 .. 31 */
3590 OP_SH, /* shifter operand */
3591 OP_ADDR, /* Memory address expression (any mode) */
3592 OP_EXP, /* arbitrary expression */
3593 OP_EXPi, /* same, with optional immediate prefix */
3594 OP_EXPr, /* same, with optional relocation suffix */
3596 OP_CPSF, /* CPS flags */
3597 OP_ENDI, /* Endianness specifier */
3598 OP_PSR, /* CPSR/SPSR mask for msr */
3599 OP_COND, /* conditional code */
3600 OP_TB, /* Table branch. */
3602 OP_RRnpc_I0, /* ARM register or literal 0 */
3603 OP_RR_EXr, /* ARM register or expression with opt. reloc suff. */
3604 OP_RR_EXi, /* ARM register or expression with imm prefix */
3605 OP_RF_IF, /* FPA register or immediate */
3606 OP_RIWR_RIWC, /* iWMMXt R or C reg */
3608 /* Optional operands. */
3609 OP_oI7b, /* immediate, prefix optional, 0 .. 7 */
3610 OP_oI31b, /* 0 .. 31 */
3611 OP_oIffffb, /* 0 .. 65535 */
3612 OP_oI255c, /* curly-brace enclosed, 0 .. 255 */
3614 OP_oRR, /* ARM register */
3615 OP_oRRnpc, /* ARM register, not the PC */
3616 OP_oSHll, /* LSL immediate */
3617 OP_oSHar, /* ASR immediate */
3618 OP_oSHllar, /* LSL or ASR immediate */
3619 OP_oROR, /* ROR 0/8/16/24 */
3621 OP_FIRST_OPTIONAL = OP_oI7b
3624 /* Generic instruction operand parser. This does no encoding and no
3625 semantic validation; it merely squirrels values away in the inst
3626 structure. Returns SUCCESS or FAIL depending on whether the
3627 specified grammar matched. */
3628 static int
3629 parse_operands (char *str, const unsigned char *pattern)
3631 unsigned const char *upat = pattern;
3632 char *backtrack_pos = 0;
3633 const char *backtrack_error = 0;
3634 int i, val, backtrack_index = 0;
3636 #define po_char_or_fail(chr) do { \
3637 if (skip_past_char (&str, chr) == FAIL) \
3638 goto bad_args; \
3639 } while (0)
3641 #define po_reg_or_fail(regtype) do { \
3642 val = arm_reg_parse (&str, regtype); \
3643 if (val == FAIL) \
3645 inst.error = _(reg_expected_msgs[regtype]); \
3646 goto failure; \
3648 inst.operands[i].reg = val; \
3649 inst.operands[i].isreg = 1; \
3650 } while (0)
3652 #define po_reg_or_goto(regtype, label) do { \
3653 val = arm_reg_parse (&str, regtype); \
3654 if (val == FAIL) \
3655 goto label; \
3657 inst.operands[i].reg = val; \
3658 inst.operands[i].isreg = 1; \
3659 } while (0)
3661 #define po_imm_or_fail(min, max, popt) do { \
3662 if (parse_immediate (&str, &val, min, max, popt) == FAIL) \
3663 goto failure; \
3664 inst.operands[i].imm = val; \
3665 } while (0)
3667 #define po_misc_or_fail(expr) do { \
3668 if (expr) \
3669 goto failure; \
3670 } while (0)
3672 skip_whitespace (str);
3674 for (i = 0; upat[i] != OP_stop; i++)
3676 if (upat[i] >= OP_FIRST_OPTIONAL)
3678 /* Remember where we are in case we need to backtrack. */
3679 assert (!backtrack_pos);
3680 backtrack_pos = str;
3681 backtrack_error = inst.error;
3682 backtrack_index = i;
3685 if (i > 0)
3686 po_char_or_fail (',');
3688 switch (upat[i])
3690 /* Registers */
3691 case OP_oRRnpc:
3692 case OP_RRnpc:
3693 case OP_oRR:
3694 case OP_RR: po_reg_or_fail (REG_TYPE_RN); break;
3695 case OP_RCP: po_reg_or_fail (REG_TYPE_CP); break;
3696 case OP_RCN: po_reg_or_fail (REG_TYPE_CN); break;
3697 case OP_RF: po_reg_or_fail (REG_TYPE_FN); break;
3698 case OP_RVS: po_reg_or_fail (REG_TYPE_VFS); break;
3699 case OP_RVD: po_reg_or_fail (REG_TYPE_VFD); break;
3700 case OP_RVC: po_reg_or_fail (REG_TYPE_VFC); break;
3701 case OP_RMF: po_reg_or_fail (REG_TYPE_MVF); break;
3702 case OP_RMD: po_reg_or_fail (REG_TYPE_MVD); break;
3703 case OP_RMFX: po_reg_or_fail (REG_TYPE_MVFX); break;
3704 case OP_RMDX: po_reg_or_fail (REG_TYPE_MVDX); break;
3705 case OP_RMAX: po_reg_or_fail (REG_TYPE_MVAX); break;
3706 case OP_RMDS: po_reg_or_fail (REG_TYPE_DSPSC); break;
3707 case OP_RIWR: po_reg_or_fail (REG_TYPE_MMXWR); break;
3708 case OP_RIWC: po_reg_or_fail (REG_TYPE_MMXWC); break;
3709 case OP_RIWG: po_reg_or_fail (REG_TYPE_MMXWCG); break;
3710 case OP_RXA: po_reg_or_fail (REG_TYPE_XSCALE); break;
3712 case OP_RRnpcb:
3713 po_char_or_fail ('[');
3714 po_reg_or_fail (REG_TYPE_RN);
3715 po_char_or_fail (']');
3716 break;
3718 case OP_RRw:
3719 po_reg_or_fail (REG_TYPE_RN);
3720 if (skip_past_char (&str, '!') == SUCCESS)
3721 inst.operands[i].writeback = 1;
3722 break;
3724 /* Immediates */
3725 case OP_I7: po_imm_or_fail ( 0, 7, FALSE); break;
3726 case OP_I15: po_imm_or_fail ( 0, 15, FALSE); break;
3727 case OP_I16: po_imm_or_fail ( 1, 16, FALSE); break;
3728 case OP_I31: po_imm_or_fail ( 0, 31, FALSE); break;
3729 case OP_I32: po_imm_or_fail ( 1, 32, FALSE); break;
3730 case OP_I63s: po_imm_or_fail (-64, 63, FALSE); break;
3731 case OP_I255: po_imm_or_fail ( 0, 255, FALSE); break;
3732 case OP_Iffff: po_imm_or_fail ( 0, 0xffff, FALSE); break;
3734 case OP_I4b: po_imm_or_fail ( 1, 4, TRUE); break;
3735 case OP_oI7b:
3736 case OP_I7b: po_imm_or_fail ( 0, 7, TRUE); break;
3737 case OP_I15b: po_imm_or_fail ( 0, 15, TRUE); break;
3738 case OP_oI31b:
3739 case OP_I31b: po_imm_or_fail ( 0, 31, TRUE); break;
3740 case OP_oIffffb: po_imm_or_fail ( 0, 0xffff, TRUE); break;
3742 /* Immediate variants */
3743 case OP_oI255c:
3744 po_char_or_fail ('{');
3745 po_imm_or_fail (0, 255, TRUE);
3746 po_char_or_fail ('}');
3747 break;
3749 case OP_I31w:
3750 /* The expression parser chokes on a trailing !, so we have
3751 to find it first and zap it. */
3753 char *s = str;
3754 while (*s && *s != ',')
3755 s++;
3756 if (s[-1] == '!')
3758 s[-1] = '\0';
3759 inst.operands[i].writeback = 1;
3761 po_imm_or_fail (0, 31, TRUE);
3762 if (str == s - 1)
3763 str = s;
3765 break;
3767 /* Expressions */
3768 case OP_EXPi: EXPi:
3769 po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str,
3770 GE_OPT_PREFIX));
3771 break;
3773 case OP_EXP:
3774 po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str,
3775 GE_NO_PREFIX));
3776 break;
3778 case OP_EXPr: EXPr:
3779 po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str,
3780 GE_NO_PREFIX));
3781 if (inst.reloc.exp.X_op == O_symbol)
3783 val = parse_reloc (&str);
3784 if (val == -1)
3786 inst.error = _("unrecognized relocation suffix");
3787 goto failure;
3789 else if (val != BFD_RELOC_UNUSED)
3791 inst.operands[i].imm = val;
3792 inst.operands[i].hasreloc = 1;
3795 break;
3797 /* Register or expression */
3798 case OP_RR_EXr: po_reg_or_goto (REG_TYPE_RN, EXPr); break;
3799 case OP_RR_EXi: po_reg_or_goto (REG_TYPE_RN, EXPi); break;
3801 /* Register or immediate */
3802 case OP_RRnpc_I0: po_reg_or_goto (REG_TYPE_RN, I0); break;
3803 I0: po_imm_or_fail (0, 0, FALSE); break;
3805 case OP_RF_IF: po_reg_or_goto (REG_TYPE_FN, IF); break;
3807 if (!is_immediate_prefix (*str))
3808 goto bad_args;
3809 str++;
3810 val = parse_fpa_immediate (&str);
3811 if (val == FAIL)
3812 goto failure;
3813 /* FPA immediates are encoded as registers 8-15.
3814 parse_fpa_immediate has already applied the offset. */
3815 inst.operands[i].reg = val;
3816 inst.operands[i].isreg = 1;
3817 break;
3819 /* Two kinds of register */
3820 case OP_RIWR_RIWC:
3822 struct reg_entry *rege = arm_reg_parse_multi (&str);
3823 if (rege->type != REG_TYPE_MMXWR
3824 && rege->type != REG_TYPE_MMXWC
3825 && rege->type != REG_TYPE_MMXWCG)
3827 inst.error = _("iWMMXt data or control register expected");
3828 goto failure;
3830 inst.operands[i].reg = rege->number;
3831 inst.operands[i].isreg = (rege->type == REG_TYPE_MMXWR);
3833 break;
3835 /* Misc */
3836 case OP_CPSF: val = parse_cps_flags (&str); break;
3837 case OP_ENDI: val = parse_endian_specifier (&str); break;
3838 case OP_oROR: val = parse_ror (&str); break;
3839 case OP_PSR: val = parse_psr (&str); break;
3840 case OP_COND: val = parse_cond (&str); break;
3842 case OP_TB:
3843 po_misc_or_fail (parse_tb (&str));
3844 break;
3846 /* Register lists */
3847 case OP_REGLST:
3848 val = parse_reg_list (&str);
3849 if (*str == '^')
3851 inst.operands[1].writeback = 1;
3852 str++;
3854 break;
3856 case OP_VRSLST:
3857 val = parse_vfp_reg_list (&str, &inst.operands[i].reg, 0);
3858 break;
3860 case OP_VRDLST:
3861 val = parse_vfp_reg_list (&str, &inst.operands[i].reg, 1);
3862 break;
3864 /* Addressing modes */
3865 case OP_ADDR:
3866 po_misc_or_fail (parse_address (&str, i));
3867 break;
3869 case OP_SH:
3870 po_misc_or_fail (parse_shifter_operand (&str, i));
3871 break;
3873 case OP_oSHll:
3874 po_misc_or_fail (parse_shift (&str, i, SHIFT_LSL_IMMEDIATE));
3875 break;
3877 case OP_oSHar:
3878 po_misc_or_fail (parse_shift (&str, i, SHIFT_ASR_IMMEDIATE));
3879 break;
3881 case OP_oSHllar:
3882 po_misc_or_fail (parse_shift (&str, i, SHIFT_LSL_OR_ASR_IMMEDIATE));
3883 break;
3885 default:
3886 as_fatal ("unhandled operand code %d", upat[i]);
3889 /* Various value-based sanity checks and shared operations. We
3890 do not signal immediate failures for the register constraints;
3891 this allows a syntax error to take precedence. */
3892 switch (upat[i])
3894 case OP_oRRnpc:
3895 case OP_RRnpc:
3896 case OP_RRnpcb:
3897 case OP_RRw:
3898 case OP_RRnpc_I0:
3899 if (inst.operands[i].isreg && inst.operands[i].reg == REG_PC)
3900 inst.error = BAD_PC;
3901 break;
3903 case OP_CPSF:
3904 case OP_ENDI:
3905 case OP_oROR:
3906 case OP_PSR:
3907 case OP_COND:
3908 case OP_REGLST:
3909 case OP_VRSLST:
3910 case OP_VRDLST:
3911 if (val == FAIL)
3912 goto failure;
3913 inst.operands[i].imm = val;
3914 break;
3916 default:
3917 break;
3920 /* If we get here, this operand was successfully parsed. */
3921 inst.operands[i].present = 1;
3922 continue;
3924 bad_args:
3925 inst.error = BAD_ARGS;
3927 failure:
3928 if (!backtrack_pos)
3929 return FAIL;
3931 /* Do not backtrack over a trailing optional argument that
3932 absorbed some text. We will only fail again, with the
3933 'garbage following instruction' error message, which is
3934 probably less helpful than the current one. */
3935 if (backtrack_index == i && backtrack_pos != str
3936 && upat[i+1] == OP_stop)
3937 return FAIL;
3939 /* Try again, skipping the optional argument at backtrack_pos. */
3940 str = backtrack_pos;
3941 inst.error = backtrack_error;
3942 inst.operands[backtrack_index].present = 0;
3943 i = backtrack_index;
3944 backtrack_pos = 0;
3947 /* Check that we have parsed all the arguments. */
3948 if (*str != '\0' && !inst.error)
3949 inst.error = _("garbage following instruction");
3951 return inst.error ? FAIL : SUCCESS;
3954 #undef po_char_or_fail
3955 #undef po_reg_or_fail
3956 #undef po_reg_or_goto
3957 #undef po_imm_or_fail
3959 /* Shorthand macro for instruction encoding functions issuing errors. */
3960 #define constraint(expr, err) do { \
3961 if (expr) \
3963 inst.error = err; \
3964 return; \
3966 } while (0)
3968 /* Functions for operand encoding. ARM, then Thumb. */
3970 #define rotate_left(v, n) (v << n | v >> (32 - n))
3972 /* If VAL can be encoded in the immediate field of an ARM instruction,
3973 return the encoded form. Otherwise, return FAIL. */
3975 static unsigned int
3976 encode_arm_immediate (unsigned int val)
3978 unsigned int a, i;
3980 for (i = 0; i < 32; i += 2)
3981 if ((a = rotate_left (val, i)) <= 0xff)
3982 return a | (i << 7); /* 12-bit pack: [shift-cnt,const]. */
3984 return FAIL;
3987 /* If VAL can be encoded in the immediate field of a Thumb32 instruction,
3988 return the encoded form. Otherwise, return FAIL. */
3989 static unsigned int
3990 encode_thumb32_immediate (unsigned int val)
3992 unsigned int a, i;
3994 if (val <= 0xff)
3995 return val;
3997 for (i = 1; i <= 24; i++)
3999 a = val >> i;
4000 if ((val & ~(0xff << i)) == 0)
4001 return ((val >> i) & 0x7f) | ((32 - i) << 7);
4004 a = val & 0xff;
4005 if (val == ((a << 16) | a))
4006 return 0x100 | a;
4007 if (val == ((a << 24) | (a << 16) | (a << 8) | a))
4008 return 0x300 | a;
4010 a = val & 0xff00;
4011 if (val == ((a << 16) | a))
4012 return 0x200 | (a >> 8);
4014 return FAIL;
4016 /* Encode a VFP SP register number into inst.instruction. */
4018 static void
4019 encode_arm_vfp_sp_reg (int reg, enum vfp_sp_reg_pos pos)
4021 switch (pos)
4023 case VFP_REG_Sd:
4024 inst.instruction |= ((reg >> 1) << 12) | ((reg & 1) << 22);
4025 break;
4027 case VFP_REG_Sn:
4028 inst.instruction |= ((reg >> 1) << 16) | ((reg & 1) << 7);
4029 break;
4031 case VFP_REG_Sm:
4032 inst.instruction |= ((reg >> 1) << 0) | ((reg & 1) << 5);
4033 break;
4035 default:
4036 abort ();
4040 /* Encode a <shift> in an ARM-format instruction. The immediate,
4041 if any, is handled by md_apply_fix. */
4042 static void
4043 encode_arm_shift (int i)
4045 if (inst.operands[i].shift_kind == SHIFT_RRX)
4046 inst.instruction |= SHIFT_ROR << 5;
4047 else
4049 inst.instruction |= inst.operands[i].shift_kind << 5;
4050 if (inst.operands[i].immisreg)
4052 inst.instruction |= SHIFT_BY_REG;
4053 inst.instruction |= inst.operands[i].imm << 8;
4055 else
4056 inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM;
4060 static void
4061 encode_arm_shifter_operand (int i)
4063 if (inst.operands[i].isreg)
4065 inst.instruction |= inst.operands[i].reg;
4066 encode_arm_shift (i);
4068 else
4069 inst.instruction |= INST_IMMEDIATE;
4072 /* Subroutine of encode_arm_addr_mode_2 and encode_arm_addr_mode_3. */
4073 static void
4074 encode_arm_addr_mode_common (int i, bfd_boolean is_t)
4076 assert (inst.operands[i].isreg);
4077 inst.instruction |= inst.operands[i].reg << 16;
4079 if (inst.operands[i].preind)
4081 if (is_t)
4083 inst.error = _("instruction does not accept preindexed addressing");
4084 return;
4086 inst.instruction |= PRE_INDEX;
4087 if (inst.operands[i].writeback)
4088 inst.instruction |= WRITE_BACK;
4091 else if (inst.operands[i].postind)
4093 assert (inst.operands[i].writeback);
4094 if (is_t)
4095 inst.instruction |= WRITE_BACK;
4097 else /* unindexed - only for coprocessor */
4099 inst.error = _("instruction does not accept unindexed addressing");
4100 return;
4103 if (((inst.instruction & WRITE_BACK) || !(inst.instruction & PRE_INDEX))
4104 && (((inst.instruction & 0x000f0000) >> 16)
4105 == ((inst.instruction & 0x0000f000) >> 12)))
4106 as_warn ((inst.instruction & LOAD_BIT)
4107 ? _("destination register same as write-back base")
4108 : _("source register same as write-back base"));
4111 /* inst.operands[i] was set up by parse_address. Encode it into an
4112 ARM-format mode 2 load or store instruction. If is_t is true,
4113 reject forms that cannot be used with a T instruction (i.e. not
4114 post-indexed). */
4115 static void
4116 encode_arm_addr_mode_2 (int i, bfd_boolean is_t)
4118 encode_arm_addr_mode_common (i, is_t);
4120 if (inst.operands[i].immisreg)
4122 inst.instruction |= INST_IMMEDIATE; /* yes, this is backwards */
4123 inst.instruction |= inst.operands[i].imm;
4124 if (!inst.operands[i].negative)
4125 inst.instruction |= INDEX_UP;
4126 if (inst.operands[i].shifted)
4128 if (inst.operands[i].shift_kind == SHIFT_RRX)
4129 inst.instruction |= SHIFT_ROR << 5;
4130 else
4132 inst.instruction |= inst.operands[i].shift_kind << 5;
4133 inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM;
4137 else /* immediate offset in inst.reloc */
4139 if (inst.reloc.type == BFD_RELOC_UNUSED)
4140 inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM;
4144 /* inst.operands[i] was set up by parse_address. Encode it into an
4145 ARM-format mode 3 load or store instruction. Reject forms that
4146 cannot be used with such instructions. If is_t is true, reject
4147 forms that cannot be used with a T instruction (i.e. not
4148 post-indexed). */
4149 static void
4150 encode_arm_addr_mode_3 (int i, bfd_boolean is_t)
4152 if (inst.operands[i].immisreg && inst.operands[i].shifted)
4154 inst.error = _("instruction does not accept scaled register index");
4155 return;
4158 encode_arm_addr_mode_common (i, is_t);
4160 if (inst.operands[i].immisreg)
4162 inst.instruction |= inst.operands[i].imm;
4163 if (!inst.operands[i].negative)
4164 inst.instruction |= INDEX_UP;
4166 else /* immediate offset in inst.reloc */
4168 inst.instruction |= HWOFFSET_IMM;
4169 if (inst.reloc.type == BFD_RELOC_UNUSED)
4170 inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM8;
4174 /* inst.operands[i] was set up by parse_address. Encode it into an
4175 ARM-format instruction. Reject all forms which cannot be encoded
4176 into a coprocessor load/store instruction. If wb_ok is false,
4177 reject use of writeback; if unind_ok is false, reject use of
4178 unindexed addressing. If reloc_override is not 0, use it instead
4179 of BFD_ARM_CP_OFF_IMM. */
4181 static int
4182 encode_arm_cp_address (int i, int wb_ok, int unind_ok, int reloc_override)
4184 inst.instruction |= inst.operands[i].reg << 16;
4186 assert (!(inst.operands[i].preind && inst.operands[i].postind));
4188 if (!inst.operands[i].preind && !inst.operands[i].postind) /* unindexed */
4190 assert (!inst.operands[i].writeback);
4191 if (!unind_ok)
4193 inst.error = _("instruction does not support unindexed addressing");
4194 return FAIL;
4196 inst.instruction |= inst.operands[i].imm;
4197 inst.instruction |= INDEX_UP;
4198 return SUCCESS;
4201 if (inst.operands[i].preind)
4202 inst.instruction |= PRE_INDEX;
4204 if (inst.operands[i].writeback)
4206 if (inst.operands[i].reg == REG_PC)
4208 inst.error = _("pc may not be used with write-back");
4209 return FAIL;
4211 if (!wb_ok)
4213 inst.error = _("instruction does not support writeback");
4214 return FAIL;
4216 inst.instruction |= WRITE_BACK;
4219 if (reloc_override)
4220 inst.reloc.type = reloc_override;
4221 else
4222 inst.reloc.type = BFD_RELOC_ARM_CP_OFF_IMM;
4223 return SUCCESS;
4226 /* inst.reloc.exp describes an "=expr" load pseudo-operation.
4227 Determine whether it can be performed with a move instruction; if
4228 it can, convert inst.instruction to that move instruction and
4229 return 1; if it can't, convert inst.instruction to a literal-pool
4230 load and return 0. If this is not a valid thing to do in the
4231 current context, set inst.error and return 1.
4233 inst.operands[i] describes the destination register. */
4235 static int
4236 move_or_literal_pool (int i, bfd_boolean thumb_p, bfd_boolean mode_3)
4238 if ((inst.instruction & (thumb_p ? THUMB_LOAD_BIT : LOAD_BIT)) == 0)
4240 inst.error = _("invalid pseudo operation");
4241 return 1;
4243 if (inst.reloc.exp.X_op != O_constant && inst.reloc.exp.X_op != O_symbol)
4245 inst.error = _("constant expression expected");
4246 return 1;
4248 if (inst.reloc.exp.X_op == O_constant)
4250 if (thumb_p)
4252 if ((inst.reloc.exp.X_add_number & ~0xFF) == 0)
4254 /* This can be done with a mov(1) instruction. */
4255 inst.instruction = T_OPCODE_MOV_I8 | (inst.operands[i].reg << 8);
4256 inst.instruction |= inst.reloc.exp.X_add_number;
4257 return 1;
4260 else
4262 int value = encode_arm_immediate (inst.reloc.exp.X_add_number);
4263 if (value != FAIL)
4265 /* This can be done with a mov instruction. */
4266 inst.instruction &= LITERAL_MASK;
4267 inst.instruction |= INST_IMMEDIATE | (OPCODE_MOV << DATA_OP_SHIFT);
4268 inst.instruction |= value & 0xfff;
4269 return 1;
4272 value = encode_arm_immediate (~inst.reloc.exp.X_add_number);
4273 if (value != FAIL)
4275 /* This can be done with a mvn instruction. */
4276 inst.instruction &= LITERAL_MASK;
4277 inst.instruction |= INST_IMMEDIATE | (OPCODE_MVN << DATA_OP_SHIFT);
4278 inst.instruction |= value & 0xfff;
4279 return 1;
4284 if (add_to_lit_pool () == FAIL)
4286 inst.error = _("literal pool insertion failed");
4287 return 1;
4289 inst.operands[1].reg = REG_PC;
4290 inst.operands[1].isreg = 1;
4291 inst.operands[1].preind = 1;
4292 inst.reloc.pc_rel = 1;
4293 inst.reloc.type = (thumb_p
4294 ? BFD_RELOC_ARM_THUMB_OFFSET
4295 : (mode_3
4296 ? BFD_RELOC_ARM_HWLITERAL
4297 : BFD_RELOC_ARM_LITERAL));
4298 return 0;
4301 /* Functions for instruction encoding, sorted by subarchitecture.
4302 First some generics; their names are taken from the conventional
4303 bit positions for register arguments in ARM format instructions. */
4305 static void
4306 do_noargs (void)
4310 static void
4311 do_rd (void)
4313 inst.instruction |= inst.operands[0].reg << 12;
4316 static void
4317 do_rd_rm (void)
4319 inst.instruction |= inst.operands[0].reg << 12;
4320 inst.instruction |= inst.operands[1].reg;
4323 static void
4324 do_rd_rn (void)
4326 inst.instruction |= inst.operands[0].reg << 12;
4327 inst.instruction |= inst.operands[1].reg << 16;
4330 static void
4331 do_rn_rd (void)
4333 inst.instruction |= inst.operands[0].reg << 16;
4334 inst.instruction |= inst.operands[1].reg << 12;
4337 static void
4338 do_rd_rm_rn (void)
4340 inst.instruction |= inst.operands[0].reg << 12;
4341 inst.instruction |= inst.operands[1].reg;
4342 inst.instruction |= inst.operands[2].reg << 16;
4345 static void
4346 do_rd_rn_rm (void)
4348 inst.instruction |= inst.operands[0].reg << 12;
4349 inst.instruction |= inst.operands[1].reg << 16;
4350 inst.instruction |= inst.operands[2].reg;
4353 static void
4354 do_rm_rd_rn (void)
4356 inst.instruction |= inst.operands[0].reg;
4357 inst.instruction |= inst.operands[1].reg << 12;
4358 inst.instruction |= inst.operands[2].reg << 16;
4361 static void
4362 do_imm0 (void)
4364 inst.instruction |= inst.operands[0].imm;
4367 static void
4368 do_rd_cpaddr (void)
4370 inst.instruction |= inst.operands[0].reg << 12;
4371 encode_arm_cp_address (1, TRUE, TRUE, 0);
4374 /* ARM instructions, in alphabetical order by function name (except
4375 that wrapper functions appear immediately after the function they
4376 wrap). */
4378 /* This is a pseudo-op of the form "adr rd, label" to be converted
4379 into a relative address of the form "add rd, pc, #label-.-8". */
4381 static void
4382 do_adr (void)
4384 inst.instruction |= (inst.operands[0].reg << 12); /* Rd */
4386 /* Frag hacking will turn this into a sub instruction if the offset turns
4387 out to be negative. */
4388 inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;
4389 inst.reloc.pc_rel = 1;
4390 inst.reloc.exp.X_add_number -= 8;
4393 /* This is a pseudo-op of the form "adrl rd, label" to be converted
4394 into a relative address of the form:
4395 add rd, pc, #low(label-.-8)"
4396 add rd, rd, #high(label-.-8)" */
4398 static void
4399 do_adrl (void)
4401 inst.instruction |= (inst.operands[0].reg << 12); /* Rd */
4403 /* Frag hacking will turn this into a sub instruction if the offset turns
4404 out to be negative. */
4405 inst.reloc.type = BFD_RELOC_ARM_ADRL_IMMEDIATE;
4406 inst.reloc.pc_rel = 1;
4407 inst.size = INSN_SIZE * 2;
4408 inst.reloc.exp.X_add_number -= 8;
4411 static void
4412 do_arit (void)
4414 if (!inst.operands[1].present)
4415 inst.operands[1].reg = inst.operands[0].reg;
4416 inst.instruction |= inst.operands[0].reg << 12;
4417 inst.instruction |= inst.operands[1].reg << 16;
4418 encode_arm_shifter_operand (2);
4421 static void
4422 do_bfc (void)
4424 unsigned int msb = inst.operands[1].imm + inst.operands[2].imm;
4425 constraint (msb > 32, _("bit-field extends past end of register"));
4426 /* The instruction encoding stores the LSB and MSB,
4427 not the LSB and width. */
4428 inst.instruction |= inst.operands[0].reg << 12;
4429 inst.instruction |= inst.operands[1].imm << 7;
4430 inst.instruction |= (msb - 1) << 16;
4433 static void
4434 do_bfi (void)
4436 unsigned int msb;
4438 /* #0 in second position is alternative syntax for bfc, which is
4439 the same instruction but with REG_PC in the Rm field. */
4440 if (!inst.operands[1].isreg)
4441 inst.operands[1].reg = REG_PC;
4443 msb = inst.operands[2].imm + inst.operands[3].imm;
4444 constraint (msb > 32, _("bit-field extends past end of register"));
4445 /* The instruction encoding stores the LSB and MSB,
4446 not the LSB and width. */
4447 inst.instruction |= inst.operands[0].reg << 12;
4448 inst.instruction |= inst.operands[1].reg;
4449 inst.instruction |= inst.operands[2].imm << 7;
4450 inst.instruction |= (msb - 1) << 16;
4453 static void
4454 do_bfx (void)
4456 constraint (inst.operands[2].imm + inst.operands[3].imm > 32,
4457 _("bit-field extends past end of register"));
4458 inst.instruction |= inst.operands[0].reg << 12;
4459 inst.instruction |= inst.operands[1].reg;
4460 inst.instruction |= inst.operands[2].imm << 7;
4461 inst.instruction |= (inst.operands[3].imm - 1) << 16;
4464 /* ARM V5 breakpoint instruction (argument parse)
4465 BKPT <16 bit unsigned immediate>
4466 Instruction is not conditional.
4467 The bit pattern given in insns[] has the COND_ALWAYS condition,
4468 and it is an error if the caller tried to override that. */
4470 static void
4471 do_bkpt (void)
4473 /* Top 12 of 16 bits to bits 19:8. */
4474 inst.instruction |= (inst.operands[0].imm & 0xfff0) << 4;
4476 /* Bottom 4 of 16 bits to bits 3:0. */
4477 inst.instruction |= inst.operands[0].imm & 0xf;
4480 static void
4481 encode_branch (int default_reloc)
4483 if (inst.operands[0].hasreloc)
4485 constraint (inst.operands[0].imm != BFD_RELOC_ARM_PLT32,
4486 _("the only suffix valid here is '(plt)'"));
4487 inst.reloc.type = BFD_RELOC_ARM_PLT32;
4489 else
4491 inst.reloc.type = default_reloc;
4493 inst.reloc.pc_rel = 1;
4496 static void
4497 do_branch (void)
4499 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH);
4502 /* ARM V5 branch-link-exchange instruction (argument parse)
4503 BLX <target_addr> ie BLX(1)
4504 BLX{<condition>} <Rm> ie BLX(2)
4505 Unfortunately, there are two different opcodes for this mnemonic.
4506 So, the insns[].value is not used, and the code here zaps values
4507 into inst.instruction.
4508 Also, the <target_addr> can be 25 bits, hence has its own reloc. */
4510 static void
4511 do_blx (void)
4513 if (inst.operands[0].isreg)
4515 /* Arg is a register; the opcode provided by insns[] is correct.
4516 It is not illegal to do "blx pc", just useless. */
4517 if (inst.operands[0].reg == REG_PC)
4518 as_tsktsk (_("use of r15 in blx in ARM mode is not really useful"));
4520 inst.instruction |= inst.operands[0].reg;
4522 else
4524 /* Arg is an address; this instruction cannot be executed
4525 conditionally, and the opcode must be adjusted. */
4526 constraint (inst.cond != COND_ALWAYS, BAD_COND);
4527 inst.instruction = 0xfa000000;
4528 encode_branch (BFD_RELOC_ARM_PCREL_BLX);
4532 static void
4533 do_bx (void)
4535 if (inst.operands[0].reg == REG_PC)
4536 as_tsktsk (_("use of r15 in bx in ARM mode is not really useful"));
4538 inst.instruction |= inst.operands[0].reg;
4542 /* ARM v5TEJ. Jump to Jazelle code. */
4544 static void
4545 do_bxj (void)
4547 if (inst.operands[0].reg == REG_PC)
4548 as_tsktsk (_("use of r15 in bxj is not really useful"));
4550 inst.instruction |= inst.operands[0].reg;
4553 /* Co-processor data operation:
4554 CDP{cond} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>}
4555 CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} */
4556 static void
4557 do_cdp (void)
4559 inst.instruction |= inst.operands[0].reg << 8;
4560 inst.instruction |= inst.operands[1].imm << 20;
4561 inst.instruction |= inst.operands[2].reg << 12;
4562 inst.instruction |= inst.operands[3].reg << 16;
4563 inst.instruction |= inst.operands[4].reg;
4564 inst.instruction |= inst.operands[5].imm << 5;
4567 static void
4568 do_cmp (void)
4570 inst.instruction |= inst.operands[0].reg << 16;
4571 encode_arm_shifter_operand (1);
4574 /* Transfer between coprocessor and ARM registers.
4575 MRC{cond} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>}
4576 MRC2
4577 MCR{cond}
4578 MCR2
4580 No special properties. */
4582 static void
4583 do_co_reg (void)
4585 inst.instruction |= inst.operands[0].reg << 8;
4586 inst.instruction |= inst.operands[1].imm << 21;
4587 inst.instruction |= inst.operands[2].reg << 12;
4588 inst.instruction |= inst.operands[3].reg << 16;
4589 inst.instruction |= inst.operands[4].reg;
4590 inst.instruction |= inst.operands[5].imm << 5;
4593 /* Transfer between coprocessor register and pair of ARM registers.
4594 MCRR{cond} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>.
4595 MCRR2
4596 MRRC{cond}
4597 MRRC2
4599 Two XScale instructions are special cases of these:
4601 MAR{cond} acc0, <RdLo>, <RdHi> == MCRR{cond} p0, #0, <RdLo>, <RdHi>, c0
4602 MRA{cond} acc0, <RdLo>, <RdHi> == MRRC{cond} p0, #0, <RdLo>, <RdHi>, c0
4604 Result unpredicatable if Rd or Rn is R15. */
4606 static void
4607 do_co_reg2c (void)
4609 inst.instruction |= inst.operands[0].reg << 8;
4610 inst.instruction |= inst.operands[1].imm << 4;
4611 inst.instruction |= inst.operands[2].reg << 12;
4612 inst.instruction |= inst.operands[3].reg << 16;
4613 inst.instruction |= inst.operands[4].reg;
4616 static void
4617 do_cpsi (void)
4619 inst.instruction |= inst.operands[0].imm << 6;
4620 inst.instruction |= inst.operands[1].imm;
4623 static void
4624 do_it (void)
4626 /* There is no IT instruction in ARM mode. We
4627 process it but do not generate code for it. */
4628 inst.size = 0;
4631 static void
4632 do_ldmstm (void)
4634 int base_reg = inst.operands[0].reg;
4635 int range = inst.operands[1].imm;
4637 inst.instruction |= base_reg << 16;
4638 inst.instruction |= range;
4640 if (inst.operands[1].writeback)
4641 inst.instruction |= LDM_TYPE_2_OR_3;
4643 if (inst.operands[0].writeback)
4645 inst.instruction |= WRITE_BACK;
4646 /* Check for unpredictable uses of writeback. */
4647 if (inst.instruction & LOAD_BIT)
4649 /* Not allowed in LDM type 2. */
4650 if ((inst.instruction & LDM_TYPE_2_OR_3)
4651 && ((range & (1 << REG_PC)) == 0))
4652 as_warn (_("writeback of base register is UNPREDICTABLE"));
4653 /* Only allowed if base reg not in list for other types. */
4654 else if (range & (1 << base_reg))
4655 as_warn (_("writeback of base register when in register list is UNPREDICTABLE"));
4657 else /* STM. */
4659 /* Not allowed for type 2. */
4660 if (inst.instruction & LDM_TYPE_2_OR_3)
4661 as_warn (_("writeback of base register is UNPREDICTABLE"));
4662 /* Only allowed if base reg not in list, or first in list. */
4663 else if ((range & (1 << base_reg))
4664 && (range & ((1 << base_reg) - 1)))
4665 as_warn (_("if writeback register is in list, it must be the lowest reg in the list"));
4670 /* ARMv5TE load-consecutive (argument parse)
4671 Mode is like LDRH.
4673 LDRccD R, mode
4674 STRccD R, mode. */
4676 static void
4677 do_ldrd (void)
4679 constraint (inst.operands[0].reg % 2 != 0,
4680 _("first destination register must be even"));
4681 constraint (inst.operands[1].present
4682 && inst.operands[1].reg != inst.operands[0].reg + 1,
4683 _("can only load two consecutive registers"));
4684 constraint (inst.operands[0].reg == REG_LR, _("r14 not allowed here"));
4685 constraint (!inst.operands[2].isreg, _("'[' expected"));
4687 if (!inst.operands[1].present)
4688 inst.operands[1].reg = inst.operands[0].reg + 1;
4690 if (inst.instruction & LOAD_BIT)
4692 /* encode_arm_addr_mode_3 will diagnose overlap between the base
4693 register and the first register written; we have to diagnose
4694 overlap between the base and the second register written here. */
4696 if (inst.operands[2].reg == inst.operands[1].reg
4697 && (inst.operands[2].writeback || inst.operands[2].postind))
4698 as_warn (_("base register written back, and overlaps "
4699 "second destination register"));
4701 /* For an index-register load, the index register must not overlap the
4702 destination (even if not write-back). */
4703 else if (inst.operands[2].immisreg
4704 && ((unsigned) inst.operands[2].imm == inst.operands[0].reg
4705 || (unsigned) inst.operands[2].imm == inst.operands[1].reg))
4706 as_warn (_("index register overlaps destination register"));
4709 inst.instruction |= inst.operands[0].reg << 12;
4710 encode_arm_addr_mode_3 (2, /*is_t=*/FALSE);
4713 static void
4714 do_ldrex (void)
4716 constraint (!inst.operands[1].isreg || !inst.operands[1].preind
4717 || inst.operands[1].postind || inst.operands[1].writeback
4718 || inst.operands[1].immisreg || inst.operands[1].shifted
4719 || inst.operands[1].negative,
4720 _("instruction does not accept this addressing mode"));
4722 constraint (inst.operands[1].reg == REG_PC, BAD_PC);
4724 constraint (inst.reloc.exp.X_op != O_constant
4725 || inst.reloc.exp.X_add_number != 0,
4726 _("offset must be zero in ARM encoding"));
4728 inst.instruction |= inst.operands[0].reg << 12;
4729 inst.instruction |= inst.operands[1].reg << 16;
4730 inst.reloc.type = BFD_RELOC_UNUSED;
4733 static void
4734 do_ldrexd (void)
4736 constraint (inst.operands[0].reg % 2 != 0,
4737 _("even register required"));
4738 constraint (inst.operands[1].present
4739 && inst.operands[1].reg != inst.operands[0].reg + 1,
4740 _("can only load two consecutive registers"));
4741 /* If op 1 were present and equal to PC, this function wouldn't
4742 have been called in the first place. */
4743 constraint (inst.operands[0].reg == REG_LR, _("r14 not allowed here"));
4745 inst.instruction |= inst.operands[0].reg << 12;
4746 inst.instruction |= inst.operands[2].reg << 16;
4749 static void
4750 do_ldst (void)
4752 inst.instruction |= inst.operands[0].reg << 12;
4753 if (!inst.operands[1].isreg)
4754 if (move_or_literal_pool (0, /*thumb_p=*/FALSE, /*mode_3=*/FALSE))
4755 return;
4756 encode_arm_addr_mode_2 (1, /*is_t=*/FALSE);
4759 static void
4760 do_ldstt (void)
4762 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
4763 reject [Rn,...]. */
4764 if (inst.operands[1].preind)
4766 constraint (inst.reloc.exp.X_op != O_constant ||
4767 inst.reloc.exp.X_add_number != 0,
4768 _("this instruction requires a post-indexed address"));
4770 inst.operands[1].preind = 0;
4771 inst.operands[1].postind = 1;
4772 inst.operands[1].writeback = 1;
4774 inst.instruction |= inst.operands[0].reg << 12;
4775 encode_arm_addr_mode_2 (1, /*is_t=*/TRUE);
4778 /* Halfword and signed-byte load/store operations. */
4780 static void
4781 do_ldstv4 (void)
4783 inst.instruction |= inst.operands[0].reg << 12;
4784 if (!inst.operands[1].isreg)
4785 if (move_or_literal_pool (0, /*thumb_p=*/FALSE, /*mode_3=*/TRUE))
4786 return;
4787 encode_arm_addr_mode_3 (1, /*is_t=*/FALSE);
4790 static void
4791 do_ldsttv4 (void)
4793 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
4794 reject [Rn,...]. */
4795 if (inst.operands[1].preind)
4797 constraint (inst.reloc.exp.X_op != O_constant ||
4798 inst.reloc.exp.X_add_number != 0,
4799 _("this instruction requires a post-indexed address"));
4801 inst.operands[1].preind = 0;
4802 inst.operands[1].postind = 1;
4803 inst.operands[1].writeback = 1;
4805 inst.instruction |= inst.operands[0].reg << 12;
4806 encode_arm_addr_mode_3 (1, /*is_t=*/TRUE);
4809 /* Co-processor register load/store.
4810 Format: <LDC|STC>{cond}[L] CP#,CRd,<address> */
4811 static void
4812 do_lstc (void)
4814 inst.instruction |= inst.operands[0].reg << 8;
4815 inst.instruction |= inst.operands[1].reg << 12;
4816 encode_arm_cp_address (2, TRUE, TRUE, 0);
4819 static void
4820 do_mlas (void)
4822 /* This restriction does not apply to mls (nor to mla in v6, but
4823 that's hard to detect at present). */
4824 if (inst.operands[0].reg == inst.operands[1].reg
4825 && !(inst.instruction & 0x00400000))
4826 as_tsktsk (_("rd and rm should be different in mla"));
4828 inst.instruction |= inst.operands[0].reg << 16;
4829 inst.instruction |= inst.operands[1].reg;
4830 inst.instruction |= inst.operands[2].reg << 8;
4831 inst.instruction |= inst.operands[3].reg << 12;
4835 static void
4836 do_mov (void)
4838 inst.instruction |= inst.operands[0].reg << 12;
4839 encode_arm_shifter_operand (1);
4842 /* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>. */
4843 static void
4844 do_mov16 (void)
4846 inst.instruction |= inst.operands[0].reg << 12;
4847 /* The value is in two pieces: 0:11, 16:19. */
4848 inst.instruction |= (inst.operands[1].imm & 0x00000fff);
4849 inst.instruction |= (inst.operands[1].imm & 0x0000f000) << 4;
4852 static void
4853 do_mrs (void)
4855 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
4856 constraint ((inst.operands[1].imm & (PSR_c|PSR_x|PSR_s|PSR_f))
4857 != (PSR_c|PSR_f),
4858 _("'CPSR' or 'SPSR' expected"));
4859 inst.instruction |= inst.operands[0].reg << 12;
4860 inst.instruction |= (inst.operands[1].imm & SPSR_BIT);
4863 /* Two possible forms:
4864 "{C|S}PSR_<field>, Rm",
4865 "{C|S}PSR_f, #expression". */
4867 static void
4868 do_msr (void)
4870 inst.instruction |= inst.operands[0].imm;
4871 if (inst.operands[1].isreg)
4872 inst.instruction |= inst.operands[1].reg;
4873 else
4875 inst.instruction |= INST_IMMEDIATE;
4876 inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;
4877 inst.reloc.pc_rel = 0;
4881 static void
4882 do_mul (void)
4884 if (!inst.operands[2].present)
4885 inst.operands[2].reg = inst.operands[0].reg;
4886 inst.instruction |= inst.operands[0].reg << 16;
4887 inst.instruction |= inst.operands[1].reg;
4888 inst.instruction |= inst.operands[2].reg << 8;
4890 if (inst.operands[0].reg == inst.operands[1].reg)
4891 as_tsktsk (_("rd and rm should be different in mul"));
4894 /* Long Multiply Parser
4895 UMULL RdLo, RdHi, Rm, Rs
4896 SMULL RdLo, RdHi, Rm, Rs
4897 UMLAL RdLo, RdHi, Rm, Rs
4898 SMLAL RdLo, RdHi, Rm, Rs. */
4900 static void
4901 do_mull (void)
4903 inst.instruction |= inst.operands[0].reg << 12;
4904 inst.instruction |= inst.operands[1].reg << 16;
4905 inst.instruction |= inst.operands[2].reg;
4906 inst.instruction |= inst.operands[3].reg << 8;
4908 /* rdhi, rdlo and rm must all be different. */
4909 if (inst.operands[0].reg == inst.operands[1].reg
4910 || inst.operands[0].reg == inst.operands[2].reg
4911 || inst.operands[1].reg == inst.operands[2].reg)
4912 as_tsktsk (_("rdhi, rdlo and rm must all be different"));
4915 static void
4916 do_nop (void)
4918 if (inst.operands[0].present)
4920 /* Architectural NOP hints are CPSR sets with no bits selected. */
4921 inst.instruction &= 0xf0000000;
4922 inst.instruction |= 0x0320f000 + inst.operands[0].imm;
4926 /* ARM V6 Pack Halfword Bottom Top instruction (argument parse).
4927 PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>}
4928 Condition defaults to COND_ALWAYS.
4929 Error if Rd, Rn or Rm are R15. */
4931 static void
4932 do_pkhbt (void)
4934 inst.instruction |= inst.operands[0].reg << 12;
4935 inst.instruction |= inst.operands[1].reg << 16;
4936 inst.instruction |= inst.operands[2].reg;
4937 if (inst.operands[3].present)
4938 encode_arm_shift (3);
4941 /* ARM V6 PKHTB (Argument Parse). */
4943 static void
4944 do_pkhtb (void)
4946 if (!inst.operands[3].present)
4948 /* If the shift specifier is omitted, turn the instruction
4949 into pkhbt rd, rm, rn. */
4950 inst.instruction &= 0xfff00010;
4951 inst.instruction |= inst.operands[0].reg << 12;
4952 inst.instruction |= inst.operands[1].reg;
4953 inst.instruction |= inst.operands[2].reg << 16;
4955 else
4957 inst.instruction |= inst.operands[0].reg << 12;
4958 inst.instruction |= inst.operands[1].reg << 16;
4959 inst.instruction |= inst.operands[2].reg;
4960 encode_arm_shift (3);
4964 /* ARMv5TE: Preload-Cache
4966 PLD <addr_mode>
4968 Syntactically, like LDR with B=1, W=0, L=1. */
4970 static void
4971 do_pld (void)
4973 constraint (!inst.operands[0].isreg,
4974 _("'[' expected after PLD mnemonic"));
4975 constraint (inst.operands[0].postind,
4976 _("post-indexed expression used in preload instruction"));
4977 constraint (inst.operands[0].writeback,
4978 _("writeback used in preload instruction"));
4979 constraint (!inst.operands[0].preind,
4980 _("unindexed addressing used in preload instruction"));
4981 inst.instruction |= inst.operands[0].reg;
4982 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE);
4985 static void
4986 do_push_pop (void)
4988 inst.operands[1] = inst.operands[0];
4989 memset (&inst.operands[0], 0, sizeof inst.operands[0]);
4990 inst.operands[0].isreg = 1;
4991 inst.operands[0].writeback = 1;
4992 inst.operands[0].reg = REG_SP;
4993 do_ldmstm ();
4996 /* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the
4997 word at the specified address and the following word
4998 respectively.
4999 Unconditionally executed.
5000 Error if Rn is R15. */
5002 static void
5003 do_rfe (void)
5005 inst.instruction |= inst.operands[0].reg << 16;
5006 if (inst.operands[0].writeback)
5007 inst.instruction |= WRITE_BACK;
5010 /* ARM V6 ssat (argument parse). */
5012 static void
5013 do_ssat (void)
5015 inst.instruction |= inst.operands[0].reg << 12;
5016 inst.instruction |= (inst.operands[1].imm - 1) << 16;
5017 inst.instruction |= inst.operands[2].reg;
5019 if (inst.operands[3].present)
5020 encode_arm_shift (3);
5023 /* ARM V6 usat (argument parse). */
5025 static void
5026 do_usat (void)
5028 inst.instruction |= inst.operands[0].reg << 12;
5029 inst.instruction |= inst.operands[1].imm << 16;
5030 inst.instruction |= inst.operands[2].reg;
5032 if (inst.operands[3].present)
5033 encode_arm_shift (3);
5036 /* ARM V6 ssat16 (argument parse). */
5038 static void
5039 do_ssat16 (void)
5041 inst.instruction |= inst.operands[0].reg << 12;
5042 inst.instruction |= ((inst.operands[1].imm - 1) << 16);
5043 inst.instruction |= inst.operands[2].reg;
5046 static void
5047 do_usat16 (void)
5049 inst.instruction |= inst.operands[0].reg << 12;
5050 inst.instruction |= inst.operands[1].imm << 16;
5051 inst.instruction |= inst.operands[2].reg;
5054 /* ARM V6 SETEND (argument parse). Sets the E bit in the CPSR while
5055 preserving the other bits.
5057 setend <endian_specifier>, where <endian_specifier> is either
5058 BE or LE. */
5060 static void
5061 do_setend (void)
5063 if (inst.operands[0].imm)
5064 inst.instruction |= 0x200;
5067 static void
5068 do_shift (void)
5070 unsigned int Rm = (inst.operands[1].present
5071 ? inst.operands[1].reg
5072 : inst.operands[0].reg);
5074 inst.instruction |= inst.operands[0].reg << 12;
5075 inst.instruction |= Rm;
5076 if (inst.operands[2].isreg) /* Rd, {Rm,} Rs */
5078 constraint (inst.operands[0].reg != Rm,
5079 _("source1 and dest must be same register"));
5080 inst.instruction |= inst.operands[2].reg << 8;
5081 inst.instruction |= SHIFT_BY_REG;
5083 else
5084 inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM;
5087 static void
5088 do_smi (void)
5090 inst.reloc.type = BFD_RELOC_ARM_SMI;
5091 inst.reloc.pc_rel = 0;
5094 static void
5095 do_swi (void)
5097 inst.reloc.type = BFD_RELOC_ARM_SWI;
5098 inst.reloc.pc_rel = 0;
5101 /* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse)
5102 SMLAxy{cond} Rd,Rm,Rs,Rn
5103 SMLAWy{cond} Rd,Rm,Rs,Rn
5104 Error if any register is R15. */
5106 static void
5107 do_smla (void)
5109 inst.instruction |= inst.operands[0].reg << 16;
5110 inst.instruction |= inst.operands[1].reg;
5111 inst.instruction |= inst.operands[2].reg << 8;
5112 inst.instruction |= inst.operands[3].reg << 12;
5115 /* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse)
5116 SMLALxy{cond} Rdlo,Rdhi,Rm,Rs
5117 Error if any register is R15.
5118 Warning if Rdlo == Rdhi. */
5120 static void
5121 do_smlal (void)
5123 inst.instruction |= inst.operands[0].reg << 12;
5124 inst.instruction |= inst.operands[1].reg << 16;
5125 inst.instruction |= inst.operands[2].reg;
5126 inst.instruction |= inst.operands[3].reg << 8;
5128 if (inst.operands[0].reg == inst.operands[1].reg)
5129 as_tsktsk (_("rdhi and rdlo must be different"));
5132 /* ARM V5E (El Segundo) signed-multiply (argument parse)
5133 SMULxy{cond} Rd,Rm,Rs
5134 Error if any register is R15. */
5136 static void
5137 do_smul (void)
5139 inst.instruction |= inst.operands[0].reg << 16;
5140 inst.instruction |= inst.operands[1].reg;
5141 inst.instruction |= inst.operands[2].reg << 8;
5144 /* ARM V6 srs (argument parse). */
5146 static void
5147 do_srs (void)
5149 inst.instruction |= inst.operands[0].imm;
5150 if (inst.operands[0].writeback)
5151 inst.instruction |= WRITE_BACK;
5154 /* ARM V6 strex (argument parse). */
5156 static void
5157 do_strex (void)
5159 constraint (!inst.operands[2].isreg || !inst.operands[2].preind
5160 || inst.operands[2].postind || inst.operands[2].writeback
5161 || inst.operands[2].immisreg || inst.operands[2].shifted
5162 || inst.operands[2].negative,
5163 _("instruction does not accept this addressing mode"));
5165 constraint (inst.operands[2].reg == REG_PC, BAD_PC);
5167 constraint (inst.operands[0].reg == inst.operands[1].reg
5168 || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP);
5170 constraint (inst.reloc.exp.X_op != O_constant
5171 || inst.reloc.exp.X_add_number != 0,
5172 _("offset must be zero in ARM encoding"));
5174 inst.instruction |= inst.operands[0].reg << 12;
5175 inst.instruction |= inst.operands[1].reg;
5176 inst.instruction |= inst.operands[2].reg << 16;
5177 inst.reloc.type = BFD_RELOC_UNUSED;
5180 static void
5181 do_strexd (void)
5183 constraint (inst.operands[1].reg % 2 != 0,
5184 _("even register required"));
5185 constraint (inst.operands[2].present
5186 && inst.operands[2].reg != inst.operands[1].reg + 1,
5187 _("can only store two consecutive registers"));
5188 /* If op 2 were present and equal to PC, this function wouldn't
5189 have been called in the first place. */
5190 constraint (inst.operands[1].reg == REG_LR, _("r14 not allowed here"));
5192 constraint (inst.operands[0].reg == inst.operands[1].reg
5193 || inst.operands[0].reg == inst.operands[1].reg + 1
5194 || inst.operands[0].reg == inst.operands[3].reg,
5195 BAD_OVERLAP);
5197 inst.instruction |= inst.operands[0].reg << 12;
5198 inst.instruction |= inst.operands[1].reg;
5199 inst.instruction |= inst.operands[3].reg << 16;
5202 /* ARM V6 SXTAH extracts a 16-bit value from a register, sign
5203 extends it to 32-bits, and adds the result to a value in another
5204 register. You can specify a rotation by 0, 8, 16, or 24 bits
5205 before extracting the 16-bit value.
5206 SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>}
5207 Condition defaults to COND_ALWAYS.
5208 Error if any register uses R15. */
5210 static void
5211 do_sxtah (void)
5213 inst.instruction |= inst.operands[0].reg << 12;
5214 inst.instruction |= inst.operands[1].reg << 16;
5215 inst.instruction |= inst.operands[2].reg;
5216 inst.instruction |= inst.operands[3].imm << 10;
5219 /* ARM V6 SXTH.
5221 SXTH {<cond>} <Rd>, <Rm>{, <rotation>}
5222 Condition defaults to COND_ALWAYS.
5223 Error if any register uses R15. */
5225 static void
5226 do_sxth (void)
5228 inst.instruction |= inst.operands[0].reg << 12;
5229 inst.instruction |= inst.operands[1].reg;
5230 inst.instruction |= inst.operands[2].imm << 10;
5233 /* VFP instructions. In a logical order: SP variant first, monad
5234 before dyad, arithmetic then move then load/store. */
5236 static void
5237 do_vfp_sp_monadic (void)
5239 encode_arm_vfp_sp_reg (inst.operands[0].reg, VFP_REG_Sd);
5240 encode_arm_vfp_sp_reg (inst.operands[1].reg, VFP_REG_Sm);
5243 static void
5244 do_vfp_sp_dyadic (void)
5246 encode_arm_vfp_sp_reg (inst.operands[0].reg, VFP_REG_Sd);
5247 encode_arm_vfp_sp_reg (inst.operands[1].reg, VFP_REG_Sn);
5248 encode_arm_vfp_sp_reg (inst.operands[2].reg, VFP_REG_Sm);
5251 static void
5252 do_vfp_sp_compare_z (void)
5254 encode_arm_vfp_sp_reg (inst.operands[0].reg, VFP_REG_Sd);
5257 static void
5258 do_vfp_dp_sp_cvt (void)
5260 inst.instruction |= inst.operands[0].reg << 12;
5261 encode_arm_vfp_sp_reg (inst.operands[1].reg, VFP_REG_Sm);
5264 static void
5265 do_vfp_sp_dp_cvt (void)
5267 encode_arm_vfp_sp_reg (inst.operands[0].reg, VFP_REG_Sd);
5268 inst.instruction |= inst.operands[1].reg;
5271 static void
5272 do_vfp_reg_from_sp (void)
5274 inst.instruction |= inst.operands[0].reg << 12;
5275 encode_arm_vfp_sp_reg (inst.operands[1].reg, VFP_REG_Sn);
5278 static void
5279 do_vfp_reg2_from_sp2 (void)
5281 constraint (inst.operands[2].imm != 2,
5282 _("only two consecutive VFP SP registers allowed here"));
5283 inst.instruction |= inst.operands[0].reg << 12;
5284 inst.instruction |= inst.operands[1].reg << 16;
5285 encode_arm_vfp_sp_reg (inst.operands[2].reg, VFP_REG_Sm);
5288 static void
5289 do_vfp_sp_from_reg (void)
5291 encode_arm_vfp_sp_reg (inst.operands[0].reg, VFP_REG_Sn);
5292 inst.instruction |= inst.operands[1].reg << 12;
5295 static void
5296 do_vfp_sp2_from_reg2 (void)
5298 constraint (inst.operands[0].imm != 2,
5299 _("only two consecutive VFP SP registers allowed here"));
5300 encode_arm_vfp_sp_reg (inst.operands[0].reg, VFP_REG_Sm);
5301 inst.instruction |= inst.operands[1].reg << 12;
5302 inst.instruction |= inst.operands[2].reg << 16;
5305 static void
5306 do_vfp_sp_ldst (void)
5308 encode_arm_vfp_sp_reg (inst.operands[0].reg, VFP_REG_Sd);
5309 encode_arm_cp_address (1, FALSE, TRUE, 0);
5312 static void
5313 do_vfp_dp_ldst (void)
5315 inst.instruction |= inst.operands[0].reg << 12;
5316 encode_arm_cp_address (1, FALSE, TRUE, 0);
5320 static void
5321 vfp_sp_ldstm (enum vfp_ldstm_type ldstm_type)
5323 if (inst.operands[0].writeback)
5324 inst.instruction |= WRITE_BACK;
5325 else
5326 constraint (ldstm_type != VFP_LDSTMIA,
5327 _("this addressing mode requires base-register writeback"));
5328 inst.instruction |= inst.operands[0].reg << 16;
5329 encode_arm_vfp_sp_reg (inst.operands[1].reg, VFP_REG_Sd);
5330 inst.instruction |= inst.operands[1].imm;
5333 static void
5334 vfp_dp_ldstm (enum vfp_ldstm_type ldstm_type)
5336 int count;
5338 if (inst.operands[0].writeback)
5339 inst.instruction |= WRITE_BACK;
5340 else
5341 constraint (ldstm_type != VFP_LDSTMIA && ldstm_type != VFP_LDSTMIAX,
5342 _("this addressing mode requires base-register writeback"));
5344 inst.instruction |= inst.operands[0].reg << 16;
5345 inst.instruction |= inst.operands[1].reg << 12;
5347 count = inst.operands[1].imm << 1;
5348 if (ldstm_type == VFP_LDSTMIAX || ldstm_type == VFP_LDSTMDBX)
5349 count += 1;
5351 inst.instruction |= count;
5354 static void
5355 do_vfp_sp_ldstmia (void)
5357 vfp_sp_ldstm (VFP_LDSTMIA);
5360 static void
5361 do_vfp_sp_ldstmdb (void)
5363 vfp_sp_ldstm (VFP_LDSTMDB);
5366 static void
5367 do_vfp_dp_ldstmia (void)
5369 vfp_dp_ldstm (VFP_LDSTMIA);
5372 static void
5373 do_vfp_dp_ldstmdb (void)
5375 vfp_dp_ldstm (VFP_LDSTMDB);
5378 static void
5379 do_vfp_xp_ldstmia (void)
5381 vfp_dp_ldstm (VFP_LDSTMIAX);
5384 static void
5385 do_vfp_xp_ldstmdb (void)
5387 vfp_dp_ldstm (VFP_LDSTMDBX);
5390 /* FPA instructions. Also in a logical order. */
5392 static void
5393 do_fpa_cmp (void)
5395 inst.instruction |= inst.operands[0].reg << 16;
5396 inst.instruction |= inst.operands[1].reg;
5399 static void
5400 do_fpa_ldmstm (void)
5402 inst.instruction |= inst.operands[0].reg << 12;
5403 switch (inst.operands[1].imm)
5405 case 1: inst.instruction |= CP_T_X; break;
5406 case 2: inst.instruction |= CP_T_Y; break;
5407 case 3: inst.instruction |= CP_T_Y | CP_T_X; break;
5408 case 4: break;
5409 default: abort ();
5412 if (inst.instruction & (PRE_INDEX | INDEX_UP))
5414 /* The instruction specified "ea" or "fd", so we can only accept
5415 [Rn]{!}. The instruction does not really support stacking or
5416 unstacking, so we have to emulate these by setting appropriate
5417 bits and offsets. */
5418 constraint (inst.reloc.exp.X_op != O_constant
5419 || inst.reloc.exp.X_add_number != 0,
5420 _("this instruction does not support indexing"));
5422 if ((inst.instruction & PRE_INDEX) || inst.operands[2].writeback)
5423 inst.reloc.exp.X_add_number = 12 * inst.operands[1].imm;
5425 if (!(inst.instruction & INDEX_UP))
5426 inst.reloc.exp.X_add_number = -inst.reloc.exp.X_add_number;
5428 if (!(inst.instruction & PRE_INDEX) && inst.operands[2].writeback)
5430 inst.operands[2].preind = 0;
5431 inst.operands[2].postind = 1;
5435 encode_arm_cp_address (2, TRUE, TRUE, 0);
5438 /* iWMMXt instructions: strictly in alphabetical order. */
5440 static void
5441 do_iwmmxt_tandorc (void)
5443 constraint (inst.operands[0].reg != REG_PC, _("only r15 allowed here"));
5446 static void
5447 do_iwmmxt_textrc (void)
5449 inst.instruction |= inst.operands[0].reg << 12;
5450 inst.instruction |= inst.operands[1].imm;
5453 static void
5454 do_iwmmxt_textrm (void)
5456 inst.instruction |= inst.operands[0].reg << 12;
5457 inst.instruction |= inst.operands[1].reg << 16;
5458 inst.instruction |= inst.operands[2].imm;
5461 static void
5462 do_iwmmxt_tinsr (void)
5464 inst.instruction |= inst.operands[0].reg << 16;
5465 inst.instruction |= inst.operands[1].reg << 12;
5466 inst.instruction |= inst.operands[2].imm;
5469 static void
5470 do_iwmmxt_tmia (void)
5472 inst.instruction |= inst.operands[0].reg << 5;
5473 inst.instruction |= inst.operands[1].reg;
5474 inst.instruction |= inst.operands[2].reg << 12;
5477 static void
5478 do_iwmmxt_waligni (void)
5480 inst.instruction |= inst.operands[0].reg << 12;
5481 inst.instruction |= inst.operands[1].reg << 16;
5482 inst.instruction |= inst.operands[2].reg;
5483 inst.instruction |= inst.operands[3].imm << 20;
5486 static void
5487 do_iwmmxt_wmov (void)
5489 /* WMOV rD, rN is an alias for WOR rD, rN, rN. */
5490 inst.instruction |= inst.operands[0].reg << 12;
5491 inst.instruction |= inst.operands[1].reg << 16;
5492 inst.instruction |= inst.operands[1].reg;
5495 static void
5496 do_iwmmxt_wldstbh (void)
5498 inst.instruction |= inst.operands[0].reg << 12;
5499 inst.reloc.exp.X_add_number *= 4;
5500 encode_arm_cp_address (1, TRUE, FALSE, BFD_RELOC_ARM_CP_OFF_IMM_S2);
5503 static void
5504 do_iwmmxt_wldstw (void)
5506 /* RIWR_RIWC clears .isreg for a control register. */
5507 if (!inst.operands[0].isreg)
5509 constraint (inst.cond != COND_ALWAYS, BAD_COND);
5510 inst.instruction |= 0xf0000000;
5513 inst.instruction |= inst.operands[0].reg << 12;
5514 encode_arm_cp_address (1, TRUE, TRUE, 0);
5517 static void
5518 do_iwmmxt_wldstd (void)
5520 inst.instruction |= inst.operands[0].reg << 12;
5521 encode_arm_cp_address (1, TRUE, FALSE, 0);
5524 static void
5525 do_iwmmxt_wshufh (void)
5527 inst.instruction |= inst.operands[0].reg << 12;
5528 inst.instruction |= inst.operands[1].reg << 16;
5529 inst.instruction |= ((inst.operands[2].imm & 0xf0) << 16);
5530 inst.instruction |= (inst.operands[2].imm & 0x0f);
5533 static void
5534 do_iwmmxt_wzero (void)
5536 /* WZERO reg is an alias for WANDN reg, reg, reg. */
5537 inst.instruction |= inst.operands[0].reg;
5538 inst.instruction |= inst.operands[0].reg << 12;
5539 inst.instruction |= inst.operands[0].reg << 16;
5542 /* Cirrus Maverick instructions. Simple 2-, 3-, and 4-register
5543 operations first, then control, shift, and load/store. */
5545 /* Insns like "foo X,Y,Z". */
5547 static void
5548 do_mav_triple (void)
5550 inst.instruction |= inst.operands[0].reg << 16;
5551 inst.instruction |= inst.operands[1].reg;
5552 inst.instruction |= inst.operands[2].reg << 12;
5555 /* Insns like "foo W,X,Y,Z".
5556 where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */
5558 static void
5559 do_mav_quad (void)
5561 inst.instruction |= inst.operands[0].reg << 5;
5562 inst.instruction |= inst.operands[1].reg << 12;
5563 inst.instruction |= inst.operands[2].reg << 16;
5564 inst.instruction |= inst.operands[3].reg;
5567 /* cfmvsc32<cond> DSPSC,MVDX[15:0]. */
5568 static void
5569 do_mav_dspsc (void)
5571 inst.instruction |= inst.operands[1].reg << 12;
5574 /* Maverick shift immediate instructions.
5575 cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0].
5576 cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0]. */
5578 static void
5579 do_mav_shift (void)
5581 int imm = inst.operands[2].imm;
5583 inst.instruction |= inst.operands[0].reg << 12;
5584 inst.instruction |= inst.operands[1].reg << 16;
5586 /* Bits 0-3 of the insn should have bits 0-3 of the immediate.
5587 Bits 5-7 of the insn should have bits 4-6 of the immediate.
5588 Bit 4 should be 0. */
5589 imm = (imm & 0xf) | ((imm & 0x70) << 1);
5591 inst.instruction |= imm;
5594 /* XScale instructions. Also sorted arithmetic before move. */
5596 /* Xscale multiply-accumulate (argument parse)
5597 MIAcc acc0,Rm,Rs
5598 MIAPHcc acc0,Rm,Rs
5599 MIAxycc acc0,Rm,Rs. */
5601 static void
5602 do_xsc_mia (void)
5604 inst.instruction |= inst.operands[1].reg;
5605 inst.instruction |= inst.operands[2].reg << 12;
5608 /* Xscale move-accumulator-register (argument parse)
5610 MARcc acc0,RdLo,RdHi. */
5612 static void
5613 do_xsc_mar (void)
5615 inst.instruction |= inst.operands[1].reg << 12;
5616 inst.instruction |= inst.operands[2].reg << 16;
5619 /* Xscale move-register-accumulator (argument parse)
5621 MRAcc RdLo,RdHi,acc0. */
5623 static void
5624 do_xsc_mra (void)
5626 constraint (inst.operands[0].reg == inst.operands[1].reg, BAD_OVERLAP);
5627 inst.instruction |= inst.operands[0].reg << 12;
5628 inst.instruction |= inst.operands[1].reg << 16;
5631 /* Encoding functions relevant only to Thumb. */
5633 /* inst.operands[i] is a shifted-register operand; encode
5634 it into inst.instruction in the format used by Thumb32. */
5636 static void
5637 encode_thumb32_shifted_operand (int i)
5639 unsigned int value = inst.reloc.exp.X_add_number;
5640 unsigned int shift = inst.operands[i].shift_kind;
5642 constraint (inst.operands[i].immisreg,
5643 _("shift by register not allowed in thumb mode"));
5644 inst.instruction |= inst.operands[i].reg;
5645 if (shift == SHIFT_RRX)
5646 inst.instruction |= SHIFT_ROR << 4;
5647 else
5649 constraint (inst.reloc.exp.X_op != O_constant,
5650 _("expression too complex"));
5652 constraint (value > 32
5653 || (value == 32 && (shift == SHIFT_LSL
5654 || shift == SHIFT_ROR)),
5655 _("shift expression is too large"));
5657 if (value == 0)
5658 shift = SHIFT_LSL;
5659 else if (value == 32)
5660 value = 0;
5662 inst.instruction |= shift << 4;
5663 inst.instruction |= (value & 0x1c) << 10;
5664 inst.instruction |= (value & 0x03) << 6;
5669 /* inst.operands[i] was set up by parse_address. Encode it into a
5670 Thumb32 format load or store instruction. Reject forms that cannot
5671 be used with such instructions. If is_t is true, reject forms that
5672 cannot be used with a T instruction; if is_d is true, reject forms
5673 that cannot be used with a D instruction. */
5675 static void
5676 encode_thumb32_addr_mode (int i, bfd_boolean is_t, bfd_boolean is_d)
5678 bfd_boolean is_pc = (inst.operands[i].reg == REG_PC);
5680 constraint (!inst.operands[i].isreg,
5681 _("Thumb does not support the ldr =N pseudo-operation"));
5683 inst.instruction |= inst.operands[i].reg << 16;
5684 if (inst.operands[i].immisreg)
5686 constraint (is_pc, _("cannot use register index with PC-relative addressing"));
5687 constraint (is_t || is_d, _("cannot use register index with this instruction"));
5688 constraint (inst.operands[i].negative,
5689 _("Thumb does not support negative register indexing"));
5690 constraint (inst.operands[i].postind,
5691 _("Thumb does not support register post-indexing"));
5692 constraint (inst.operands[i].writeback,
5693 _("Thumb does not support register indexing with writeback"));
5694 constraint (inst.operands[i].shifted && inst.operands[i].shift_kind != SHIFT_LSL,
5695 _("Thumb supports only LSL in shifted register indexing"));
5697 inst.instruction |= inst.operands[1].imm;
5698 if (inst.operands[i].shifted)
5700 constraint (inst.reloc.exp.X_op != O_constant,
5701 _("expression too complex"));
5702 constraint (inst.reloc.exp.X_add_number < 0
5703 || inst.reloc.exp.X_add_number > 3,
5704 _("shift out of range"));
5705 inst.instruction |= inst.reloc.exp.X_add_number << 4;
5707 inst.reloc.type = BFD_RELOC_UNUSED;
5709 else if (inst.operands[i].preind)
5711 constraint (is_pc && inst.operands[i].writeback,
5712 _("cannot use writeback with PC-relative addressing"));
5713 constraint (is_t && inst.operands[1].writeback,
5714 _("cannot use writeback with this instruction"));
5716 if (is_d)
5718 inst.instruction |= 0x01000000;
5719 if (inst.operands[i].writeback)
5720 inst.instruction |= 0x00200000;
5722 else
5724 inst.instruction |= 0x00000c00;
5725 if (inst.operands[i].writeback)
5726 inst.instruction |= 0x00000100;
5728 inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_IMM;
5730 else if (inst.operands[i].postind)
5732 assert (inst.operands[i].writeback);
5733 constraint (is_pc, _("cannot use post-indexing with PC-relative addressing"));
5734 constraint (is_t, _("cannot use post-indexing with this instruction"));
5736 if (is_d)
5737 inst.instruction |= 0x00200000;
5738 else
5739 inst.instruction |= 0x00000900;
5740 inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_IMM;
5742 else /* unindexed - only for coprocessor */
5743 inst.error = _("instruction does not accept unindexed addressing");
5746 /* Table of Thumb instructions which exist in both 16- and 32-bit
5747 encodings (the latter only in post-V6T2 cores). The index is the
5748 value used in the insns table below. When there is more than one
5749 possible 16-bit encoding for the instruction, this table always
5750 holds variant (1). */
5751 #define T16_32_TAB \
5752 X(adc, 4140, eb400000), \
5753 X(adcs, 4140, eb500000), \
5754 X(add, 1c00, eb000000), \
5755 X(adds, 1c00, eb100000), \
5756 X(adr, 000f, f20f0000), \
5757 X(and, 4000, ea000000), \
5758 X(ands, 4000, ea100000), \
5759 X(asr, 1000, fa40f000), \
5760 X(asrs, 1000, fa50f000), \
5761 X(bic, 4380, ea200000), \
5762 X(bics, 4380, ea300000), \
5763 X(cmn, 42c0, eb100f00), \
5764 X(cmp, 2800, ebb00f00), \
5765 X(cpsie, b660, f3af8400), \
5766 X(cpsid, b670, f3af8600), \
5767 X(cpy, 4600, ea4f0000), \
5768 X(eor, 4040, ea800000), \
5769 X(eors, 4040, ea900000), \
5770 X(ldmia, c800, e8900000), \
5771 X(ldr, 6800, f8500000), \
5772 X(ldrb, 7800, f8100000), \
5773 X(ldrh, 8800, f8300000), \
5774 X(ldrsb, 5600, f9100000), \
5775 X(ldrsh, 5e00, f9300000), \
5776 X(lsl, 0000, fa00f000), \
5777 X(lsls, 0000, fa10f000), \
5778 X(lsr, 0800, fa20f000), \
5779 X(lsrs, 0800, fa30f000), \
5780 X(mov, 2000, ea4f0000), \
5781 X(movs, 2000, ea5f0000), \
5782 X(mul, 4340, fb00f000), \
5783 X(muls, 4340, ffffffff), /* no 32b muls */ \
5784 X(mvn, 43c0, ea6f0000), \
5785 X(mvns, 43c0, ea7f0000), \
5786 X(neg, 4240, f1c00000), /* rsb #0 */ \
5787 X(negs, 4240, f1d00000), /* rsbs #0 */ \
5788 X(orr, 4300, ea400000), \
5789 X(orrs, 4300, ea500000), \
5790 X(pop, bc00, e8bd0000), /* ldmia sp!,... */ \
5791 X(push, b400, e92d0000), /* stmdb sp!,... */ \
5792 X(rev, ba00, fa90f080), \
5793 X(rev16, ba40, fa90f090), \
5794 X(revsh, bac0, fa90f0b0), \
5795 X(ror, 41c0, fa60f000), \
5796 X(rors, 41c0, fa70f000), \
5797 X(sbc, 4180, eb600000), \
5798 X(sbcs, 4180, eb700000), \
5799 X(stmia, c000, e8800000), \
5800 X(str, 6000, f8400000), \
5801 X(strb, 7000, f8000000), \
5802 X(strh, 8000, f8200000), \
5803 X(sub, 1e00, eba00000), \
5804 X(subs, 1e00, ebb00000), \
5805 X(sxtb, b240, fa4ff080), \
5806 X(sxth, b200, fa0ff080), \
5807 X(tst, 4200, ea100f00), \
5808 X(uxtb, b2c0, fa5ff080), \
5809 X(uxth, b280, fa1ff080), \
5810 X(nop, bf00, f3af8000), \
5811 X(yield, bf10, f3af8001), \
5812 X(wfe, bf20, f3af8002), \
5813 X(wfi, bf30, f3af8003), \
5814 X(sev, bf40, f3af9004), /* typo, 8004? */
5816 /* To catch errors in encoding functions, the codes are all offset by
5817 0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined
5818 as 16-bit instructions. */
5819 #define X(a,b,c) T_MNEM_##a
5820 enum t16_32_codes { T16_32_OFFSET = 0xF7FF, T16_32_TAB };
5821 #undef X
5823 #define X(a,b,c) 0x##b
5824 static const unsigned short thumb_op16[] = { T16_32_TAB };
5825 #define THUMB_OP16(n) (thumb_op16[(n) - (T16_32_OFFSET + 1)])
5826 #undef X
5828 #define X(a,b,c) 0x##c
5829 static const unsigned int thumb_op32[] = { T16_32_TAB };
5830 #define THUMB_OP32(n) (thumb_op32[(n) - (T16_32_OFFSET + 1)])
5831 #define THUMB_SETS_FLAGS(n) (THUMB_OP32 (n) & 0x00100000)
5832 #undef X
5833 #undef T16_32_TAB
5835 /* Thumb instruction encoders, in alphabetical order. */
5837 /* ADDW or SUBW. */
5838 static void
5839 do_t_add_sub_w (void)
5841 int Rd, Rn;
5843 Rd = inst.operands[0].reg;
5844 Rn = inst.operands[1].reg;
5846 constraint (Rd == 15, _("PC not allowed as destination"));
5847 inst.instruction |= (Rn << 16) | (Rd << 8);
5848 inst.reloc.type = BFD_RELOC_ARM_T32_IMM12;
5851 /* Parse an add or subtract instruction. We get here with inst.instruction
5852 equalling any of THUMB_OPCODE_add, adds, sub, or subs. */
5854 static void
5855 do_t_add_sub (void)
5857 int Rd, Rs, Rn;
5859 Rd = inst.operands[0].reg;
5860 Rs = (inst.operands[1].present
5861 ? inst.operands[1].reg /* Rd, Rs, foo */
5862 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
5864 if (unified_syntax)
5866 if (!inst.operands[2].isreg)
5868 /* ??? Convert large immediates to addw/subw. */
5869 /* ??? 16-bit adds with small immediates. */
5870 /* For an immediate, we always generate a 32-bit opcode;
5871 section relaxation will shrink it later if possible. */
5872 inst.instruction = THUMB_OP32 (inst.instruction);
5873 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
5874 inst.instruction |= inst.operands[0].reg << 8;
5875 inst.instruction |= inst.operands[1].reg << 16;
5876 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
5878 else
5880 Rn = inst.operands[2].reg;
5881 /* See if we can do this with a 16-bit instruction. */
5882 if (!inst.operands[2].shifted && inst.size_req != 4)
5884 bfd_boolean narrow;
5886 if (inst.instruction == T_MNEM_adds
5887 || inst.instruction == T_MNEM_subs)
5888 narrow = (current_it_mask == 0);
5889 else
5890 narrow = (current_it_mask != 0);
5891 if (Rd > 7 || Rs > 7 || Rn > 7)
5892 narrow = FALSE;
5894 if (narrow)
5896 inst.instruction = ((inst.instruction == T_MNEM_adds
5897 || inst.instruction == T_MNEM_add)
5898 ? T_OPCODE_ADD_R3
5899 : T_OPCODE_SUB_R3);
5900 inst.instruction |= Rd | (Rs << 3) | (Rn << 6);
5901 return;
5904 if (inst.instruction == T_MNEM_add)
5906 if (Rd == Rs)
5908 inst.instruction = T_OPCODE_ADD_HI;
5909 inst.instruction |= (Rd & 8) << 4;
5910 inst.instruction |= (Rd & 7);
5911 inst.instruction |= Rn << 3;
5912 return;
5914 /* ... because addition is commutative! */
5915 else if (Rd == Rn)
5917 inst.instruction = T_OPCODE_ADD_HI;
5918 inst.instruction |= (Rd & 8) << 4;
5919 inst.instruction |= (Rd & 7);
5920 inst.instruction |= Rs << 3;
5921 return;
5925 /* If we get here, it can't be done in 16 bits. */
5926 constraint (inst.operands[2].shifted && inst.operands[2].immisreg,
5927 _("shift must be constant"));
5928 inst.instruction = THUMB_OP32 (inst.instruction);
5929 inst.instruction |= Rd << 8;
5930 inst.instruction |= Rs << 16;
5931 encode_thumb32_shifted_operand (2);
5934 else
5936 constraint (inst.instruction == T_MNEM_adds
5937 || inst.instruction == T_MNEM_subs,
5938 BAD_THUMB32);
5940 if (!inst.operands[2].isreg) /* Rd, Rs, #imm */
5942 constraint ((Rd > 7 && (Rd != REG_SP || Rs != REG_SP))
5943 || (Rs > 7 && Rs != REG_SP && Rs != REG_PC),
5944 BAD_HIREG);
5946 inst.instruction = (inst.instruction == T_MNEM_add
5947 ? 0x0000 : 0x8000);
5948 inst.instruction |= (Rd << 4) | Rs;
5949 inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD;
5950 return;
5953 Rn = inst.operands[2].reg;
5954 constraint (inst.operands[2].shifted, _("unshifted register required"));
5956 /* We now have Rd, Rs, and Rn set to registers. */
5957 if (Rd > 7 || Rs > 7 || Rn > 7)
5959 /* Can't do this for SUB. */
5960 constraint (inst.instruction == T_MNEM_sub, BAD_HIREG);
5961 inst.instruction = T_OPCODE_ADD_HI;
5962 inst.instruction |= (Rd & 8) << 4;
5963 inst.instruction |= (Rd & 7);
5964 if (Rs == Rd)
5965 inst.instruction |= Rn << 3;
5966 else if (Rn == Rd)
5967 inst.instruction |= Rs << 3;
5968 else
5969 constraint (1, _("dest must overlap one source register"));
5971 else
5973 inst.instruction = (inst.instruction == T_MNEM_add
5974 ? T_OPCODE_ADD_R3 : T_OPCODE_SUB_R3);
5975 inst.instruction |= Rd | (Rs << 3) | (Rn << 6);
5980 static void
5981 do_t_adr (void)
5983 if (unified_syntax && inst.size_req != 2)
5985 /* Always generate a 32-bit opcode;
5986 section relaxation will shrink it later if possible. */
5987 inst.instruction = THUMB_OP32 (inst.instruction);
5988 inst.instruction |= inst.operands[0].reg << 8;
5989 inst.reloc.type = BFD_RELOC_ARM_T32_ADD_PC12;
5990 inst.reloc.pc_rel = 1;
5992 else
5994 inst.instruction = THUMB_OP16 (inst.instruction);
5995 inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD;
5996 inst.reloc.exp.X_add_number -= 4; /* PC relative adjust. */
5997 inst.reloc.pc_rel = 1;
5999 inst.instruction |= inst.operands[0].reg << 4;
6003 /* Arithmetic instructions for which there is just one 16-bit
6004 instruction encoding, and it allows only two low registers.
6005 For maximal compatibility with ARM syntax, we allow three register
6006 operands even when Thumb-32 instructions are not available, as long
6007 as the first two are identical. For instance, both "sbc r0,r1" and
6008 "sbc r0,r0,r1" are allowed. */
6009 static void
6010 do_t_arit3 (void)
6012 int Rd, Rs, Rn;
6014 Rd = inst.operands[0].reg;
6015 Rs = (inst.operands[1].present
6016 ? inst.operands[1].reg /* Rd, Rs, foo */
6017 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
6018 Rn = inst.operands[2].reg;
6020 if (unified_syntax)
6022 if (!inst.operands[2].isreg)
6024 /* For an immediate, we always generate a 32-bit opcode;
6025 section relaxation will shrink it later if possible. */
6026 inst.instruction = THUMB_OP32 (inst.instruction);
6027 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
6028 inst.instruction |= Rd << 8;
6029 inst.instruction |= Rs << 16;
6030 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
6032 else
6034 bfd_boolean narrow;
6036 /* See if we can do this with a 16-bit instruction. */
6037 if (THUMB_SETS_FLAGS (inst.instruction))
6038 narrow = current_it_mask == 0;
6039 else
6040 narrow = current_it_mask != 0;
6042 if (Rd > 7 || Rn > 7 || Rs > 7)
6043 narrow = FALSE;
6044 if (inst.operands[2].shifted)
6045 narrow = FALSE;
6046 if (inst.size_req == 4)
6047 narrow = FALSE;
6049 if (narrow
6050 && Rd == Rs)
6052 inst.instruction = THUMB_OP16 (inst.instruction);
6053 inst.instruction |= Rd;
6054 inst.instruction |= Rn << 3;
6055 return;
6058 /* If we get here, it can't be done in 16 bits. */
6059 constraint (inst.operands[2].shifted
6060 && inst.operands[2].immisreg,
6061 _("shift must be constant"));
6062 inst.instruction = THUMB_OP32 (inst.instruction);
6063 inst.instruction |= Rd << 8;
6064 inst.instruction |= Rs << 16;
6065 encode_thumb32_shifted_operand (2);
6068 else
6070 /* On its face this is a lie - the instruction does set the
6071 flags. However, the only supported mnemonic in this mode
6072 says it doesn't. */
6073 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
6075 constraint (!inst.operands[2].isreg || inst.operands[2].shifted,
6076 _("unshifted register required"));
6077 constraint (Rd > 7 || Rs > 7 || Rn > 7, BAD_HIREG);
6078 constraint (Rd != Rs,
6079 _("dest and source1 must be the same register"));
6081 inst.instruction = THUMB_OP16 (inst.instruction);
6082 inst.instruction |= Rd;
6083 inst.instruction |= Rn << 3;
6087 /* Similarly, but for instructions where the arithmetic operation is
6088 commutative, so we can allow either of them to be different from
6089 the destination operand in a 16-bit instruction. For instance, all
6090 three of "adc r0,r1", "adc r0,r0,r1", and "adc r0,r1,r0" are
6091 accepted. */
6092 static void
6093 do_t_arit3c (void)
6095 int Rd, Rs, Rn;
6097 Rd = inst.operands[0].reg;
6098 Rs = (inst.operands[1].present
6099 ? inst.operands[1].reg /* Rd, Rs, foo */
6100 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
6101 Rn = inst.operands[2].reg;
6103 if (unified_syntax)
6105 if (!inst.operands[2].isreg)
6107 /* For an immediate, we always generate a 32-bit opcode;
6108 section relaxation will shrink it later if possible. */
6109 inst.instruction = THUMB_OP32 (inst.instruction);
6110 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
6111 inst.instruction |= Rd << 8;
6112 inst.instruction |= Rs << 16;
6113 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
6115 else
6117 bfd_boolean narrow;
6119 /* See if we can do this with a 16-bit instruction. */
6120 if (THUMB_SETS_FLAGS (inst.instruction))
6121 narrow = current_it_mask == 0;
6122 else
6123 narrow = current_it_mask != 0;
6125 if (Rd > 7 || Rn > 7 || Rs > 7)
6126 narrow = FALSE;
6127 if (inst.operands[2].shifted)
6128 narrow = FALSE;
6129 if (inst.size_req == 4)
6130 narrow = FALSE;
6132 if (narrow)
6134 if (Rd == Rs)
6136 inst.instruction = THUMB_OP16 (inst.instruction);
6137 inst.instruction |= Rd;
6138 inst.instruction |= Rn << 3;
6139 return;
6141 if (Rd == Rn)
6143 inst.instruction = THUMB_OP16 (inst.instruction);
6144 inst.instruction |= Rd;
6145 inst.instruction |= Rs << 3;
6146 return;
6150 /* If we get here, it can't be done in 16 bits. */
6151 constraint (inst.operands[2].shifted
6152 && inst.operands[2].immisreg,
6153 _("shift must be constant"));
6154 inst.instruction = THUMB_OP32 (inst.instruction);
6155 inst.instruction |= Rd << 8;
6156 inst.instruction |= Rs << 16;
6157 encode_thumb32_shifted_operand (2);
6160 else
6162 /* On its face this is a lie - the instruction does set the
6163 flags. However, the only supported mnemonic in this mode
6164 says it doesn't. */
6165 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
6167 constraint (!inst.operands[2].isreg || inst.operands[2].shifted,
6168 _("unshifted register required"));
6169 constraint (Rd > 7 || Rs > 7 || Rn > 7, BAD_HIREG);
6171 inst.instruction = THUMB_OP16 (inst.instruction);
6172 inst.instruction |= Rd;
6174 if (Rd == Rs)
6175 inst.instruction |= Rn << 3;
6176 else if (Rd == Rn)
6177 inst.instruction |= Rs << 3;
6178 else
6179 constraint (1, _("dest must overlap one source register"));
6183 static void
6184 do_t_bfc (void)
6186 unsigned int msb = inst.operands[1].imm + inst.operands[2].imm;
6187 constraint (msb > 32, _("bit-field extends past end of register"));
6188 /* The instruction encoding stores the LSB and MSB,
6189 not the LSB and width. */
6190 inst.instruction |= inst.operands[0].reg << 8;
6191 inst.instruction |= (inst.operands[1].imm & 0x1c) << 10;
6192 inst.instruction |= (inst.operands[1].imm & 0x03) << 6;
6193 inst.instruction |= msb - 1;
6196 static void
6197 do_t_bfi (void)
6199 unsigned int msb;
6201 /* #0 in second position is alternative syntax for bfc, which is
6202 the same instruction but with REG_PC in the Rm field. */
6203 if (!inst.operands[1].isreg)
6204 inst.operands[1].reg = REG_PC;
6206 msb = inst.operands[2].imm + inst.operands[3].imm;
6207 constraint (msb > 32, _("bit-field extends past end of register"));
6208 /* The instruction encoding stores the LSB and MSB,
6209 not the LSB and width. */
6210 inst.instruction |= inst.operands[0].reg << 8;
6211 inst.instruction |= inst.operands[1].reg << 16;
6212 inst.instruction |= (inst.operands[2].imm & 0x1c) << 10;
6213 inst.instruction |= (inst.operands[2].imm & 0x03) << 6;
6214 inst.instruction |= msb - 1;
6217 static void
6218 do_t_bfx (void)
6220 constraint (inst.operands[2].imm + inst.operands[3].imm > 32,
6221 _("bit-field extends past end of register"));
6222 inst.instruction |= inst.operands[0].reg << 8;
6223 inst.instruction |= inst.operands[1].reg << 16;
6224 inst.instruction |= (inst.operands[2].imm & 0x1c) << 10;
6225 inst.instruction |= (inst.operands[2].imm & 0x03) << 6;
6226 inst.instruction |= inst.operands[3].imm - 1;
6229 /* ARM V5 Thumb BLX (argument parse)
6230 BLX <target_addr> which is BLX(1)
6231 BLX <Rm> which is BLX(2)
6232 Unfortunately, there are two different opcodes for this mnemonic.
6233 So, the insns[].value is not used, and the code here zaps values
6234 into inst.instruction.
6236 ??? How to take advantage of the additional two bits of displacement
6237 available in Thumb32 mode? Need new relocation? */
6239 static void
6240 do_t_blx (void)
6242 if (inst.operands[0].isreg)
6243 /* We have a register, so this is BLX(2). */
6244 inst.instruction |= inst.operands[0].reg << 3;
6245 else
6247 /* No register. This must be BLX(1). */
6248 inst.instruction = 0xf000e800;
6249 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BLX;
6250 inst.reloc.pc_rel = 1;
6254 static void
6255 do_t_branch (void)
6257 if (unified_syntax && inst.size_req != 2)
6259 if (inst.cond == COND_ALWAYS)
6261 inst.instruction = 0xf000b000;
6262 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH25;
6264 else
6266 assert (inst.cond != 0xF);
6267 inst.instruction = (inst.cond << 22) | 0xf0008000;
6268 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH20;
6271 else
6273 if (inst.cond == COND_ALWAYS)
6274 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH12;
6275 else
6277 inst.instruction = 0xd000 | (inst.cond << 8);
6278 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH9;
6282 inst.reloc.pc_rel = 1;
6285 static void
6286 do_t_bkpt (void)
6288 if (inst.operands[0].present)
6290 constraint (inst.operands[0].imm > 255,
6291 _("immediate value out of range"));
6292 inst.instruction |= inst.operands[0].imm;
6296 static void
6297 do_t_branch23 (void)
6299 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH23;
6300 inst.reloc.pc_rel = 1;
6302 /* If the destination of the branch is a defined symbol which does not have
6303 the THUMB_FUNC attribute, then we must be calling a function which has
6304 the (interfacearm) attribute. We look for the Thumb entry point to that
6305 function and change the branch to refer to that function instead. */
6306 if ( inst.reloc.exp.X_op == O_symbol
6307 && inst.reloc.exp.X_add_symbol != NULL
6308 && S_IS_DEFINED (inst.reloc.exp.X_add_symbol)
6309 && ! THUMB_IS_FUNC (inst.reloc.exp.X_add_symbol))
6310 inst.reloc.exp.X_add_symbol =
6311 find_real_start (inst.reloc.exp.X_add_symbol);
6314 static void
6315 do_t_bx (void)
6317 inst.instruction |= inst.operands[0].reg << 3;
6318 /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc
6319 should cause the alignment to be checked once it is known. This is
6320 because BX PC only works if the instruction is word aligned. */
6323 static void
6324 do_t_bxj (void)
6326 if (inst.operands[0].reg == REG_PC)
6327 as_tsktsk (_("use of r15 in bxj is not really useful"));
6329 inst.instruction |= inst.operands[0].reg << 16;
6332 static void
6333 do_t_clz (void)
6335 inst.instruction |= inst.operands[0].reg << 8;
6336 inst.instruction |= inst.operands[1].reg << 16;
6337 inst.instruction |= inst.operands[1].reg;
6340 static void
6341 do_t_cpsi (void)
6343 if (unified_syntax
6344 && (inst.operands[1].present || inst.size_req == 4))
6346 unsigned int imod = (inst.instruction & 0x0030) >> 4;
6347 inst.instruction = 0xf3af8000;
6348 inst.instruction |= imod << 9;
6349 inst.instruction |= inst.operands[0].imm << 5;
6350 if (inst.operands[1].present)
6351 inst.instruction |= 0x100 | inst.operands[1].imm;
6353 else
6355 constraint (inst.operands[1].present,
6356 _("Thumb does not support the 2-argument "
6357 "form of this instruction"));
6358 inst.instruction |= inst.operands[0].imm;
6362 /* THUMB CPY instruction (argument parse). */
6364 static void
6365 do_t_cpy (void)
6367 if (inst.size_req == 4)
6369 inst.instruction = THUMB_OP32 (T_MNEM_mov);
6370 inst.instruction |= inst.operands[0].reg << 8;
6371 inst.instruction |= inst.operands[1].reg;
6373 else
6375 inst.instruction |= (inst.operands[0].reg & 0x8) << 4;
6376 inst.instruction |= (inst.operands[0].reg & 0x7);
6377 inst.instruction |= inst.operands[1].reg << 3;
6381 static void
6382 do_t_czb (void)
6384 constraint (inst.operands[0].reg > 7, BAD_HIREG);
6385 inst.instruction |= inst.operands[0].reg;
6386 inst.reloc.pc_rel = 1;
6387 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH7;
6390 static void
6391 do_t_hint (void)
6393 if (unified_syntax && inst.size_req == 4)
6394 inst.instruction = THUMB_OP32 (inst.instruction);
6395 else
6396 inst.instruction = THUMB_OP16 (inst.instruction);
6399 static void
6400 do_t_it (void)
6402 unsigned int cond = inst.operands[0].imm;
6404 current_it_mask = (inst.instruction & 0xf) | 0x10;
6405 current_cc = cond;
6407 /* If the condition is a negative condition, invert the mask. */
6408 if ((cond & 0x1) == 0x0)
6410 unsigned int mask = inst.instruction & 0x000f;
6412 if ((mask & 0x7) == 0)
6413 /* no conversion needed */;
6414 else if ((mask & 0x3) == 0)
6415 mask ^= 0x8;
6416 else if ((mask & 0x1) == 0)
6417 mask ^= 0xC;
6418 else
6419 mask ^= 0xE;
6421 inst.instruction &= 0xfff0;
6422 inst.instruction |= mask;
6425 inst.instruction |= cond << 4;
6428 static void
6429 do_t_ldmstm (void)
6431 /* This really doesn't seem worth it. */
6432 constraint (inst.reloc.type != BFD_RELOC_UNUSED,
6433 _("expression too complex"));
6434 constraint (inst.operands[1].writeback,
6435 _("Thumb load/store multiple does not support {reglist}^"));
6437 if (unified_syntax)
6439 /* See if we can use a 16-bit instruction. */
6440 if (inst.instruction < 0xffff /* not ldmdb/stmdb */
6441 && inst.size_req != 4
6442 && inst.operands[0].reg <= 7
6443 && !(inst.operands[1].imm & ~0xff)
6444 && (inst.instruction == T_MNEM_stmia
6445 ? inst.operands[0].writeback
6446 : (inst.operands[0].writeback
6447 == !(inst.operands[1].imm & (1 << inst.operands[0].reg)))))
6449 if (inst.instruction == T_MNEM_stmia
6450 && (inst.operands[1].imm & (1 << inst.operands[0].reg))
6451 && (inst.operands[1].imm & ((1 << inst.operands[0].reg) - 1)))
6452 as_warn (_("value stored for r%d is UNPREDICTABLE"),
6453 inst.operands[0].reg);
6455 inst.instruction = THUMB_OP16 (inst.instruction);
6456 inst.instruction |= inst.operands[0].reg << 8;
6457 inst.instruction |= inst.operands[1].imm;
6459 else
6461 if (inst.operands[1].imm & (1 << 13))
6462 as_warn (_("SP should not be in register list"));
6463 if (inst.instruction == T_MNEM_stmia)
6465 if (inst.operands[1].imm & (1 << 15))
6466 as_warn (_("PC should not be in register list"));
6467 if (inst.operands[1].imm & (1 << inst.operands[0].reg))
6468 as_warn (_("value stored for r%d is UNPREDICTABLE"),
6469 inst.operands[0].reg);
6471 else
6473 if (inst.operands[1].imm & (1 << 14)
6474 && inst.operands[1].imm & (1 << 15))
6475 as_warn (_("LR and PC should not both be in register list"));
6476 if ((inst.operands[1].imm & (1 << inst.operands[0].reg))
6477 && inst.operands[0].writeback)
6478 as_warn (_("base register should not be in register list "
6479 "when written back"));
6481 if (inst.instruction < 0xffff)
6482 inst.instruction = THUMB_OP32 (inst.instruction);
6483 inst.instruction |= inst.operands[0].reg << 16;
6484 inst.instruction |= inst.operands[1].imm;
6485 if (inst.operands[0].writeback)
6486 inst.instruction |= WRITE_BACK;
6489 else
6491 constraint (inst.operands[0].reg > 7
6492 || (inst.operands[1].imm & ~0xff), BAD_HIREG);
6493 if (inst.instruction == T_MNEM_stmia)
6495 if (!inst.operands[0].writeback)
6496 as_warn (_("this instruction will write back the base register"));
6497 if ((inst.operands[1].imm & (1 << inst.operands[0].reg))
6498 && (inst.operands[1].imm & ((1 << inst.operands[0].reg) - 1)))
6499 as_warn (_("value stored for r%d is UNPREDICTABLE"),
6500 inst.operands[0].reg);
6502 else
6504 if (!inst.operands[0].writeback
6505 && !(inst.operands[1].imm & (1 << inst.operands[0].reg)))
6506 as_warn (_("this instruction will write back the base register"));
6507 else if (inst.operands[0].writeback
6508 && (inst.operands[1].imm & (1 << inst.operands[0].reg)))
6509 as_warn (_("this instruction will not write back the base register"));
6512 inst.instruction = THUMB_OP16 (inst.instruction);
6513 inst.instruction |= inst.operands[0].reg << 8;
6514 inst.instruction |= inst.operands[1].imm;
6518 static void
6519 do_t_ldrex (void)
6521 constraint (!inst.operands[1].isreg || !inst.operands[1].preind
6522 || inst.operands[1].postind || inst.operands[1].writeback
6523 || inst.operands[1].immisreg || inst.operands[1].shifted
6524 || inst.operands[1].negative,
6525 _("instruction does not accept this addressing mode"));
6527 inst.instruction |= inst.operands[0].reg << 12;
6528 inst.instruction |= inst.operands[1].reg << 16;
6529 inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_U8;
6532 static void
6533 do_t_ldrexd (void)
6535 if (!inst.operands[1].present)
6537 constraint (inst.operands[0].reg == REG_LR,
6538 _("r14 not allowed as first register "
6539 "when second register is omitted"));
6540 inst.operands[1].reg = inst.operands[0].reg + 1;
6542 constraint (inst.operands[0].reg == inst.operands[1].reg,
6543 BAD_OVERLAP);
6545 inst.instruction |= inst.operands[0].reg << 12;
6546 inst.instruction |= inst.operands[1].reg << 8;
6547 inst.instruction |= inst.operands[2].reg << 16;
6550 static void
6551 do_t_ldst (void)
6553 if (unified_syntax)
6555 /* Generation of 16-bit instructions for anything other than
6556 Rd, [Rn, Ri] is deferred to section relaxation time. */
6557 if (inst.operands[1].isreg && inst.operands[1].immisreg
6558 && !inst.operands[1].shifted && !inst.operands[1].postind
6559 && !inst.operands[1].negative && inst.operands[0].reg <= 7
6560 && inst.operands[1].reg <= 7 && inst.operands[1].imm <= 7
6561 && inst.instruction <= 0xffff)
6563 inst.instruction = THUMB_OP16 (inst.instruction);
6564 goto op16;
6567 inst.instruction = THUMB_OP32 (inst.instruction);
6568 inst.instruction |= inst.operands[0].reg << 12;
6569 encode_thumb32_addr_mode (1, /*is_t=*/FALSE, /*is_d=*/FALSE);
6570 return;
6573 constraint (inst.operands[0].reg > 7, BAD_HIREG);
6575 if (inst.instruction == T_MNEM_ldrsh || inst.instruction == T_MNEM_ldrsb)
6577 /* Only [Rn,Rm] is acceptable. */
6578 constraint (inst.operands[1].reg > 7 || inst.operands[1].imm > 7, BAD_HIREG);
6579 constraint (!inst.operands[1].isreg || !inst.operands[1].immisreg
6580 || inst.operands[1].postind || inst.operands[1].shifted
6581 || inst.operands[1].negative,
6582 _("Thumb does not support this addressing mode"));
6583 inst.instruction = THUMB_OP16 (inst.instruction);
6584 goto op16;
6587 inst.instruction = THUMB_OP16 (inst.instruction);
6588 if (!inst.operands[1].isreg)
6589 if (move_or_literal_pool (0, /*thumb_p=*/TRUE, /*mode_3=*/FALSE))
6590 return;
6592 constraint (!inst.operands[1].preind
6593 || inst.operands[1].shifted
6594 || inst.operands[1].writeback,
6595 _("Thumb does not support this addressing mode"));
6596 if (inst.operands[1].reg == REG_PC || inst.operands[1].reg == REG_SP)
6598 constraint (inst.instruction & 0x0600,
6599 _("byte or halfword not valid for base register"));
6600 constraint (inst.operands[1].reg == REG_PC
6601 && !(inst.instruction & THUMB_LOAD_BIT),
6602 _("r15 based store not allowed"));
6603 constraint (inst.operands[1].immisreg,
6604 _("invalid base register for register offset"));
6606 if (inst.operands[1].reg == REG_PC)
6607 inst.instruction = T_OPCODE_LDR_PC;
6608 else if (inst.instruction & THUMB_LOAD_BIT)
6609 inst.instruction = T_OPCODE_LDR_SP;
6610 else
6611 inst.instruction = T_OPCODE_STR_SP;
6613 inst.instruction |= inst.operands[0].reg << 8;
6614 inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
6615 return;
6618 constraint (inst.operands[1].reg > 7, BAD_HIREG);
6619 if (!inst.operands[1].immisreg)
6621 /* Immediate offset. */
6622 inst.instruction |= inst.operands[0].reg;
6623 inst.instruction |= inst.operands[1].reg << 3;
6624 inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
6625 return;
6628 /* Register offset. */
6629 constraint (inst.operands[1].imm > 7, BAD_HIREG);
6630 constraint (inst.operands[1].negative,
6631 _("Thumb does not support this addressing mode"));
6633 op16:
6634 switch (inst.instruction)
6636 case T_OPCODE_STR_IW: inst.instruction = T_OPCODE_STR_RW; break;
6637 case T_OPCODE_STR_IH: inst.instruction = T_OPCODE_STR_RH; break;
6638 case T_OPCODE_STR_IB: inst.instruction = T_OPCODE_STR_RB; break;
6639 case T_OPCODE_LDR_IW: inst.instruction = T_OPCODE_LDR_RW; break;
6640 case T_OPCODE_LDR_IH: inst.instruction = T_OPCODE_LDR_RH; break;
6641 case T_OPCODE_LDR_IB: inst.instruction = T_OPCODE_LDR_RB; break;
6642 case 0x5600 /* ldrsb */:
6643 case 0x5e00 /* ldrsh */: break;
6644 default: abort ();
6647 inst.instruction |= inst.operands[0].reg;
6648 inst.instruction |= inst.operands[1].reg << 3;
6649 inst.instruction |= inst.operands[1].imm << 6;
6652 static void
6653 do_t_ldstd (void)
6655 if (!inst.operands[1].present)
6657 inst.operands[1].reg = inst.operands[0].reg + 1;
6658 constraint (inst.operands[0].reg == REG_LR,
6659 _("r14 not allowed here"));
6661 inst.instruction |= inst.operands[0].reg << 12;
6662 inst.instruction |= inst.operands[1].reg << 8;
6663 encode_thumb32_addr_mode (2, /*is_t=*/FALSE, /*is_d=*/TRUE);
6667 static void
6668 do_t_ldstt (void)
6670 inst.instruction |= inst.operands[0].reg << 12;
6671 encode_thumb32_addr_mode (1, /*is_t=*/TRUE, /*is_d=*/FALSE);
6674 static void
6675 do_t_mla (void)
6677 inst.instruction |= inst.operands[0].reg << 8;
6678 inst.instruction |= inst.operands[1].reg << 16;
6679 inst.instruction |= inst.operands[2].reg;
6680 inst.instruction |= inst.operands[3].reg << 12;
6683 static void
6684 do_t_mlal (void)
6686 inst.instruction |= inst.operands[0].reg << 12;
6687 inst.instruction |= inst.operands[1].reg << 8;
6688 inst.instruction |= inst.operands[2].reg << 16;
6689 inst.instruction |= inst.operands[3].reg;
6692 static void
6693 do_t_mov_cmp (void)
6695 if (unified_syntax)
6697 int r0off = (inst.instruction == T_MNEM_mov
6698 || inst.instruction == T_MNEM_movs) ? 8 : 16;
6699 bfd_boolean narrow;
6700 bfd_boolean low_regs;
6702 low_regs = (inst.operands[0].reg <= 7 && inst.operands[1].reg <= 7);
6703 if (current_it_mask)
6704 narrow = inst.instruction != T_MNEM_movs;
6705 else
6706 narrow = inst.instruction != T_MNEM_movs || low_regs;
6707 if (inst.size_req == 4
6708 || inst.operands[1].shifted)
6709 narrow = FALSE;
6711 if (!inst.operands[1].isreg)
6713 /* For an immediate, we always generate a 32-bit opcode;
6714 section relaxation will shrink it later if possible. */
6715 inst.instruction = THUMB_OP32 (inst.instruction);
6716 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
6717 inst.instruction |= inst.operands[0].reg << r0off;
6718 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
6720 else if (!narrow)
6722 inst.instruction = THUMB_OP32 (inst.instruction);
6723 inst.instruction |= inst.operands[0].reg << r0off;
6724 encode_thumb32_shifted_operand (1);
6726 else
6727 switch (inst.instruction)
6729 case T_MNEM_mov:
6730 inst.instruction = T_OPCODE_MOV_HR;
6731 inst.instruction |= (inst.operands[0].reg & 0x8) << 4;
6732 inst.instruction |= (inst.operands[0].reg & 0x7);
6733 inst.instruction |= inst.operands[1].reg << 3;
6734 break;
6736 case T_MNEM_movs:
6737 /* We know we have low registers at this point.
6738 Generate ADD Rd, Rs, #0. */
6739 inst.instruction = T_OPCODE_ADD_I3;
6740 inst.instruction |= inst.operands[0].reg;
6741 inst.instruction |= inst.operands[1].reg << 3;
6742 break;
6744 case T_MNEM_cmp:
6745 if (low_regs)
6747 inst.instruction = T_OPCODE_CMP_LR;
6748 inst.instruction |= inst.operands[0].reg;
6749 inst.instruction |= inst.operands[1].reg << 3;
6751 else
6753 inst.instruction = T_OPCODE_CMP_HR;
6754 inst.instruction |= (inst.operands[0].reg & 0x8) << 4;
6755 inst.instruction |= (inst.operands[0].reg & 0x7);
6756 inst.instruction |= inst.operands[1].reg << 3;
6758 break;
6760 return;
6763 inst.instruction = THUMB_OP16 (inst.instruction);
6764 if (inst.operands[1].isreg)
6766 if (inst.operands[0].reg < 8 && inst.operands[1].reg < 8)
6768 /* A move of two lowregs is encoded as ADD Rd, Rs, #0
6769 since a MOV instruction produces unpredictable results. */
6770 if (inst.instruction == T_OPCODE_MOV_I8)
6771 inst.instruction = T_OPCODE_ADD_I3;
6772 else
6773 inst.instruction = T_OPCODE_CMP_LR;
6775 inst.instruction |= inst.operands[0].reg;
6776 inst.instruction |= inst.operands[1].reg << 3;
6778 else
6780 if (inst.instruction == T_OPCODE_MOV_I8)
6781 inst.instruction = T_OPCODE_MOV_HR;
6782 else
6783 inst.instruction = T_OPCODE_CMP_HR;
6784 do_t_cpy ();
6787 else
6789 constraint (inst.operands[0].reg > 7,
6790 _("only lo regs allowed with immediate"));
6791 inst.instruction |= inst.operands[0].reg << 8;
6792 inst.reloc.type = BFD_RELOC_ARM_THUMB_IMM;
6796 static void
6797 do_t_mov16 (void)
6799 inst.instruction |= inst.operands[0].reg << 8;
6800 inst.instruction |= (inst.operands[1].imm & 0xf000) << 4;
6801 inst.instruction |= (inst.operands[1].imm & 0x0800) << 15;
6802 inst.instruction |= (inst.operands[1].imm & 0x0700) << 4;
6803 inst.instruction |= (inst.operands[1].imm & 0x00ff);
6806 static void
6807 do_t_mvn_tst (void)
6809 if (unified_syntax)
6811 int r0off = (inst.instruction == T_MNEM_mvn
6812 || inst.instruction == T_MNEM_mvns) ? 8 : 16;
6813 bfd_boolean narrow;
6815 if (inst.size_req == 4
6816 || inst.instruction > 0xffff
6817 || inst.operands[1].shifted
6818 || inst.operands[0].reg > 7 || inst.operands[1].reg > 7)
6819 narrow = FALSE;
6820 else if (inst.instruction == T_MNEM_cmn)
6821 narrow = TRUE;
6822 else if (THUMB_SETS_FLAGS (inst.instruction))
6823 narrow = (current_it_mask == 0);
6824 else
6825 narrow = (current_it_mask != 0);
6827 if (!inst.operands[1].isreg)
6829 /* For an immediate, we always generate a 32-bit opcode;
6830 section relaxation will shrink it later if possible. */
6831 if (inst.instruction < 0xffff)
6832 inst.instruction = THUMB_OP32 (inst.instruction);
6833 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
6834 inst.instruction |= inst.operands[0].reg << r0off;
6835 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
6837 else
6839 /* See if we can do this with a 16-bit instruction. */
6840 if (narrow)
6842 inst.instruction = THUMB_OP16 (inst.instruction);
6843 inst.instruction |= inst.operands[0].reg;
6844 inst.instruction |= inst.operands[1].reg << 3;
6846 else
6848 constraint (inst.operands[1].shifted
6849 && inst.operands[1].immisreg,
6850 _("shift must be constant"));
6851 if (inst.instruction < 0xffff)
6852 inst.instruction = THUMB_OP32 (inst.instruction);
6853 inst.instruction |= inst.operands[0].reg << r0off;
6854 encode_thumb32_shifted_operand (1);
6858 else
6860 constraint (inst.instruction > 0xffff
6861 || inst.instruction == T_MNEM_mvns, BAD_THUMB32);
6862 constraint (!inst.operands[1].isreg || inst.operands[1].shifted,
6863 _("unshifted register required"));
6864 constraint (inst.operands[0].reg > 7 || inst.operands[1].reg > 7,
6865 BAD_HIREG);
6867 inst.instruction = THUMB_OP16 (inst.instruction);
6868 inst.instruction |= inst.operands[0].reg;
6869 inst.instruction |= inst.operands[1].reg << 3;
6873 static void
6874 do_t_mrs (void)
6876 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
6877 constraint ((inst.operands[1].imm & (PSR_c|PSR_x|PSR_s|PSR_f))
6878 != (PSR_c|PSR_f),
6879 _("'CPSR' or 'SPSR' expected"));
6880 inst.instruction |= inst.operands[0].reg << 8;
6881 inst.instruction |= (inst.operands[1].imm & SPSR_BIT) >> 2;
6884 static void
6885 do_t_msr (void)
6887 constraint (!inst.operands[1].isreg,
6888 _("Thumb encoding does not support an immediate here"));
6889 inst.instruction |= (inst.operands[0].imm & SPSR_BIT) >> 2;
6890 inst.instruction |= (inst.operands[0].imm & ~SPSR_BIT) >> 8;
6891 inst.instruction |= inst.operands[1].reg << 16;
6894 static void
6895 do_t_mul (void)
6897 if (!inst.operands[2].present)
6898 inst.operands[2].reg = inst.operands[0].reg;
6900 /* There is no 32-bit MULS and no 16-bit MUL. */
6901 if (unified_syntax && inst.instruction == T_MNEM_mul)
6903 inst.instruction = THUMB_OP32 (inst.instruction);
6904 inst.instruction |= inst.operands[0].reg << 8;
6905 inst.instruction |= inst.operands[1].reg << 16;
6906 inst.instruction |= inst.operands[2].reg << 0;
6908 else
6910 constraint (!unified_syntax
6911 && inst.instruction == T_MNEM_muls, BAD_THUMB32);
6912 constraint (inst.operands[0].reg > 7 || inst.operands[1].reg > 7,
6913 BAD_HIREG);
6915 inst.instruction = THUMB_OP16 (inst.instruction);
6916 inst.instruction |= inst.operands[0].reg;
6918 if (inst.operands[0].reg == inst.operands[1].reg)
6919 inst.instruction |= inst.operands[2].reg << 3;
6920 else if (inst.operands[0].reg == inst.operands[2].reg)
6921 inst.instruction |= inst.operands[1].reg << 3;
6922 else
6923 constraint (1, _("dest must overlap one source register"));
6927 static void
6928 do_t_mull (void)
6930 inst.instruction |= inst.operands[0].reg << 12;
6931 inst.instruction |= inst.operands[1].reg << 8;
6932 inst.instruction |= inst.operands[2].reg << 16;
6933 inst.instruction |= inst.operands[3].reg;
6935 if (inst.operands[0].reg == inst.operands[1].reg)
6936 as_tsktsk (_("rdhi and rdlo must be different"));
6939 static void
6940 do_t_nop (void)
6942 if (unified_syntax)
6944 if (inst.size_req == 4 || inst.operands[0].imm > 15)
6946 inst.instruction = THUMB_OP32 (inst.instruction);
6947 inst.instruction |= inst.operands[0].imm;
6949 else
6951 inst.instruction = THUMB_OP16 (inst.instruction);
6952 inst.instruction |= inst.operands[0].imm << 4;
6955 else
6957 constraint (inst.operands[0].present,
6958 _("Thumb does not support NOP with hints"));
6959 inst.instruction = 0x46c0;
6963 static void
6964 do_t_neg (void)
6966 if (unified_syntax)
6968 bfd_boolean narrow;
6970 if (THUMB_SETS_FLAGS (inst.instruction))
6971 narrow = (current_it_mask == 0);
6972 else
6973 narrow = (current_it_mask != 0);
6974 if (inst.operands[0].reg > 7 || inst.operands[1].reg > 7)
6975 narrow = FALSE;
6976 if (inst.size_req == 4)
6977 narrow = FALSE;
6979 if (!narrow)
6981 inst.instruction = THUMB_OP32 (inst.instruction);
6982 inst.instruction |= inst.operands[0].reg << 8;
6983 inst.instruction |= inst.operands[1].reg << 16;
6985 else
6987 inst.instruction = THUMB_OP16 (inst.instruction);
6988 inst.instruction |= inst.operands[0].reg;
6989 inst.instruction |= inst.operands[1].reg << 3;
6992 else
6994 constraint (inst.operands[0].reg > 7 || inst.operands[1].reg > 7,
6995 BAD_HIREG);
6996 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
6998 inst.instruction = THUMB_OP16 (inst.instruction);
6999 inst.instruction |= inst.operands[0].reg;
7000 inst.instruction |= inst.operands[1].reg << 3;
7004 static void
7005 do_t_pkhbt (void)
7007 inst.instruction |= inst.operands[0].reg << 8;
7008 inst.instruction |= inst.operands[1].reg << 16;
7009 inst.instruction |= inst.operands[2].reg;
7010 if (inst.operands[3].present)
7012 unsigned int val = inst.reloc.exp.X_add_number;
7013 constraint (inst.reloc.exp.X_op != O_constant,
7014 _("expression too complex"));
7015 inst.instruction |= (val & 0x1c) << 10;
7016 inst.instruction |= (val & 0x03) << 6;
7020 static void
7021 do_t_pkhtb (void)
7023 if (!inst.operands[3].present)
7024 inst.instruction &= ~0x00000020;
7025 do_t_pkhbt ();
7028 static void
7029 do_t_pld (void)
7031 encode_thumb32_addr_mode (0, /*is_t=*/FALSE, /*is_d=*/FALSE);
7034 static void
7035 do_t_push_pop (void)
7037 unsigned mask;
7039 constraint (inst.operands[0].writeback,
7040 _("push/pop do not support {reglist}^"));
7041 constraint (inst.reloc.type != BFD_RELOC_UNUSED,
7042 _("expression too complex"));
7044 mask = inst.operands[0].imm;
7045 if ((mask & ~0xff) == 0)
7046 inst.instruction = THUMB_OP16 (inst.instruction);
7047 else if ((inst.instruction == T_MNEM_push
7048 && (mask & ~0xff) == 1 << REG_LR)
7049 || (inst.instruction == T_MNEM_pop
7050 && (mask & ~0xff) == 1 << REG_PC))
7052 inst.instruction = THUMB_OP16 (inst.instruction);
7053 inst.instruction |= THUMB_PP_PC_LR;
7054 mask &= 0xff;
7056 else if (unified_syntax)
7058 if (mask & (1 << 13))
7059 inst.error = _("SP not allowed in register list");
7060 if (inst.instruction == T_MNEM_push)
7062 if (mask & (1 << 15))
7063 inst.error = _("PC not allowed in register list");
7065 else
7067 if (mask & (1 << 14)
7068 && mask & (1 << 15))
7069 inst.error = _("LR and PC should not both be in register list");
7071 if ((mask & (mask - 1)) == 0)
7073 /* Single register push/pop implemented as str/ldr. */
7074 if (inst.instruction == T_MNEM_push)
7075 inst.instruction = 0xf84d0d04; /* str reg, [sp, #-4]! */
7076 else
7077 inst.instruction = 0xf85d0b04; /* ldr reg, [sp], #4 */
7078 mask = ffs(mask) - 1;
7079 mask <<= 12;
7081 else
7082 inst.instruction = THUMB_OP32 (inst.instruction);
7084 else
7086 inst.error = _("invalid register list to push/pop instruction");
7087 return;
7090 inst.instruction |= mask;
7093 static void
7094 do_t_rbit (void)
7096 inst.instruction |= inst.operands[0].reg << 8;
7097 inst.instruction |= inst.operands[1].reg << 16;
7100 static void
7101 do_t_rev (void)
7103 if (inst.operands[0].reg <= 7 && inst.operands[1].reg <= 7
7104 && inst.size_req != 4)
7106 inst.instruction = THUMB_OP16 (inst.instruction);
7107 inst.instruction |= inst.operands[0].reg;
7108 inst.instruction |= inst.operands[1].reg << 3;
7110 else if (unified_syntax)
7112 inst.instruction = THUMB_OP32 (inst.instruction);
7113 inst.instruction |= inst.operands[0].reg << 8;
7114 inst.instruction |= inst.operands[1].reg << 16;
7115 inst.instruction |= inst.operands[1].reg;
7117 else
7118 inst.error = BAD_HIREG;
7121 static void
7122 do_t_rsb (void)
7124 int Rd, Rs;
7126 Rd = inst.operands[0].reg;
7127 Rs = (inst.operands[1].present
7128 ? inst.operands[1].reg /* Rd, Rs, foo */
7129 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
7131 inst.instruction |= Rd << 8;
7132 inst.instruction |= Rs << 16;
7133 if (!inst.operands[2].isreg)
7135 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
7136 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
7138 else
7139 encode_thumb32_shifted_operand (2);
7142 static void
7143 do_t_setend (void)
7145 if (inst.operands[0].imm)
7146 inst.instruction |= 0x8;
7149 static void
7150 do_t_shift (void)
7152 if (!inst.operands[1].present)
7153 inst.operands[1].reg = inst.operands[0].reg;
7155 if (unified_syntax)
7157 bfd_boolean narrow;
7158 int shift_kind;
7160 switch (inst.instruction)
7162 case T_MNEM_asr:
7163 case T_MNEM_asrs: shift_kind = SHIFT_ASR; break;
7164 case T_MNEM_lsl:
7165 case T_MNEM_lsls: shift_kind = SHIFT_LSL; break;
7166 case T_MNEM_lsr:
7167 case T_MNEM_lsrs: shift_kind = SHIFT_LSR; break;
7168 case T_MNEM_ror:
7169 case T_MNEM_rors: shift_kind = SHIFT_ROR; break;
7170 default: abort ();
7173 if (THUMB_SETS_FLAGS (inst.instruction))
7174 narrow = (current_it_mask == 0);
7175 else
7176 narrow = (current_it_mask != 0);
7177 if (inst.operands[0].reg > 7 || inst.operands[1].reg > 7)
7178 narrow = FALSE;
7179 if (!inst.operands[2].isreg && shift_kind == SHIFT_ROR)
7180 narrow = FALSE;
7181 if (inst.operands[2].isreg
7182 && (inst.operands[1].reg != inst.operands[0].reg
7183 || inst.operands[2].reg > 7))
7184 narrow = FALSE;
7185 if (inst.size_req == 4)
7186 narrow = FALSE;
7188 if (!narrow)
7190 if (inst.operands[2].isreg)
7192 inst.instruction = THUMB_OP32 (inst.instruction);
7193 inst.instruction |= inst.operands[0].reg << 8;
7194 inst.instruction |= inst.operands[1].reg << 16;
7195 inst.instruction |= inst.operands[2].reg;
7197 else
7199 inst.operands[1].shifted = 1;
7200 inst.operands[1].shift_kind = shift_kind;
7201 inst.instruction = THUMB_OP32 (THUMB_SETS_FLAGS (inst.instruction)
7202 ? T_MNEM_movs : T_MNEM_mov);
7203 inst.instruction |= inst.operands[0].reg << 8;
7204 encode_thumb32_shifted_operand (1);
7205 /* Prevent the incorrect generation of an ARM_IMMEDIATE fixup. */
7206 inst.reloc.type = BFD_RELOC_UNUSED;
7209 else
7211 if (inst.operands[2].isreg)
7213 switch (shift_kind)
7215 case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_R; break;
7216 case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_R; break;
7217 case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_R; break;
7218 case SHIFT_ROR: inst.instruction = T_OPCODE_ROR_R; break;
7219 default: abort ();
7222 inst.instruction |= inst.operands[0].reg;
7223 inst.instruction |= inst.operands[2].reg << 3;
7225 else
7227 switch (shift_kind)
7229 case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_I; break;
7230 case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_I; break;
7231 case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_I; break;
7232 default: abort ();
7234 inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT;
7235 inst.instruction |= inst.operands[0].reg;
7236 inst.instruction |= inst.operands[1].reg << 3;
7240 else
7242 constraint (inst.operands[0].reg > 7
7243 || inst.operands[1].reg > 7, BAD_HIREG);
7244 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
7246 if (inst.operands[2].isreg) /* Rd, {Rs,} Rn */
7248 constraint (inst.operands[2].reg > 7, BAD_HIREG);
7249 constraint (inst.operands[0].reg != inst.operands[1].reg,
7250 _("source1 and dest must be same register"));
7252 switch (inst.instruction)
7254 case T_MNEM_asr: inst.instruction = T_OPCODE_ASR_R; break;
7255 case T_MNEM_lsl: inst.instruction = T_OPCODE_LSL_R; break;
7256 case T_MNEM_lsr: inst.instruction = T_OPCODE_LSR_R; break;
7257 case T_MNEM_ror: inst.instruction = T_OPCODE_ROR_R; break;
7258 default: abort ();
7261 inst.instruction |= inst.operands[0].reg;
7262 inst.instruction |= inst.operands[2].reg << 3;
7264 else
7266 switch (inst.instruction)
7268 case T_MNEM_asr: inst.instruction = T_OPCODE_ASR_I; break;
7269 case T_MNEM_lsl: inst.instruction = T_OPCODE_LSL_I; break;
7270 case T_MNEM_lsr: inst.instruction = T_OPCODE_LSR_I; break;
7271 case T_MNEM_ror: inst.error = _("ror #imm not supported"); return;
7272 default: abort ();
7274 inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT;
7275 inst.instruction |= inst.operands[0].reg;
7276 inst.instruction |= inst.operands[1].reg << 3;
7281 static void
7282 do_t_simd (void)
7284 inst.instruction |= inst.operands[0].reg << 8;
7285 inst.instruction |= inst.operands[1].reg << 16;
7286 inst.instruction |= inst.operands[2].reg;
7289 static void
7290 do_t_smi (void)
7292 unsigned int value = inst.reloc.exp.X_add_number;
7293 constraint (inst.reloc.exp.X_op != O_constant,
7294 _("expression too complex"));
7295 inst.reloc.type = BFD_RELOC_UNUSED;
7296 inst.instruction |= (value & 0xf000) >> 12;
7297 inst.instruction |= (value & 0x0ff0);
7298 inst.instruction |= (value & 0x000f) << 16;
7301 static void
7302 do_t_ssat (void)
7304 inst.instruction |= inst.operands[0].reg << 8;
7305 inst.instruction |= inst.operands[1].imm - 1;
7306 inst.instruction |= inst.operands[2].reg << 16;
7308 if (inst.operands[3].present)
7310 constraint (inst.reloc.exp.X_op != O_constant,
7311 _("expression too complex"));
7313 if (inst.reloc.exp.X_add_number != 0)
7315 if (inst.operands[3].shift_kind == SHIFT_ASR)
7316 inst.instruction |= 0x00200000; /* sh bit */
7317 inst.instruction |= (inst.reloc.exp.X_add_number & 0x1c) << 10;
7318 inst.instruction |= (inst.reloc.exp.X_add_number & 0x03) << 6;
7320 inst.reloc.type = BFD_RELOC_UNUSED;
7324 static void
7325 do_t_ssat16 (void)
7327 inst.instruction |= inst.operands[0].reg << 8;
7328 inst.instruction |= inst.operands[1].imm - 1;
7329 inst.instruction |= inst.operands[2].reg << 16;
7332 static void
7333 do_t_strex (void)
7335 constraint (!inst.operands[2].isreg || !inst.operands[2].preind
7336 || inst.operands[2].postind || inst.operands[2].writeback
7337 || inst.operands[2].immisreg || inst.operands[2].shifted
7338 || inst.operands[2].negative,
7339 _("instruction does not accept this addressing mode"));
7341 inst.instruction |= inst.operands[0].reg << 8;
7342 inst.instruction |= inst.operands[1].reg << 12;
7343 inst.instruction |= inst.operands[2].reg << 16;
7344 inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_U8;
7347 static void
7348 do_t_strexd (void)
7350 if (!inst.operands[2].present)
7351 inst.operands[2].reg = inst.operands[1].reg + 1;
7353 constraint (inst.operands[0].reg == inst.operands[1].reg
7354 || inst.operands[0].reg == inst.operands[2].reg
7355 || inst.operands[0].reg == inst.operands[3].reg
7356 || inst.operands[1].reg == inst.operands[2].reg,
7357 BAD_OVERLAP);
7359 inst.instruction |= inst.operands[0].reg;
7360 inst.instruction |= inst.operands[1].reg << 12;
7361 inst.instruction |= inst.operands[2].reg << 8;
7362 inst.instruction |= inst.operands[3].reg << 16;
7365 static void
7366 do_t_sxtah (void)
7368 inst.instruction |= inst.operands[0].reg << 8;
7369 inst.instruction |= inst.operands[1].reg << 16;
7370 inst.instruction |= inst.operands[2].reg;
7371 inst.instruction |= inst.operands[3].imm << 4;
7374 static void
7375 do_t_sxth (void)
7377 if (inst.instruction <= 0xffff && inst.size_req != 4
7378 && inst.operands[0].reg <= 7 && inst.operands[1].reg <= 7
7379 && (!inst.operands[2].present || inst.operands[2].imm == 0))
7381 inst.instruction = THUMB_OP16 (inst.instruction);
7382 inst.instruction |= inst.operands[0].reg;
7383 inst.instruction |= inst.operands[1].reg << 3;
7385 else if (unified_syntax)
7387 if (inst.instruction <= 0xffff)
7388 inst.instruction = THUMB_OP32 (inst.instruction);
7389 inst.instruction |= inst.operands[0].reg << 8;
7390 inst.instruction |= inst.operands[1].reg;
7391 inst.instruction |= inst.operands[2].imm << 4;
7393 else
7395 constraint (inst.operands[2].present && inst.operands[2].imm != 0,
7396 _("Thumb encoding does not support rotation"));
7397 constraint (1, BAD_HIREG);
7401 static void
7402 do_t_swi (void)
7404 inst.reloc.type = BFD_RELOC_ARM_SWI;
7407 static void
7408 do_t_tb (void)
7410 int half;
7412 half = (inst.instruction & 0x10) != 0;
7413 constraint (inst.operands[0].imm == 15,
7414 _("PC is not a valid index register"));
7415 constraint (!half && inst.operands[0].shifted,
7416 _("instruction does not allow shifted index"));
7417 constraint (half && !inst.operands[0].shifted,
7418 _("instruction requires shifted index"));
7419 inst.instruction |= (inst.operands[0].reg << 16) | inst.operands[0].imm;
7422 static void
7423 do_t_usat (void)
7425 inst.instruction |= inst.operands[0].reg << 8;
7426 inst.instruction |= inst.operands[1].imm;
7427 inst.instruction |= inst.operands[2].reg << 16;
7429 if (inst.operands[3].present)
7431 constraint (inst.reloc.exp.X_op != O_constant,
7432 _("expression too complex"));
7433 if (inst.reloc.exp.X_add_number != 0)
7435 if (inst.operands[3].shift_kind == SHIFT_ASR)
7436 inst.instruction |= 0x00200000; /* sh bit */
7438 inst.instruction |= (inst.reloc.exp.X_add_number & 0x1c) << 10;
7439 inst.instruction |= (inst.reloc.exp.X_add_number & 0x03) << 6;
7441 inst.reloc.type = BFD_RELOC_UNUSED;
7445 static void
7446 do_t_usat16 (void)
7448 inst.instruction |= inst.operands[0].reg << 8;
7449 inst.instruction |= inst.operands[1].imm;
7450 inst.instruction |= inst.operands[2].reg << 16;
7453 /* Overall per-instruction processing. */
7455 /* We need to be able to fix up arbitrary expressions in some statements.
7456 This is so that we can handle symbols that are an arbitrary distance from
7457 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
7458 which returns part of an address in a form which will be valid for
7459 a data instruction. We do this by pushing the expression into a symbol
7460 in the expr_section, and creating a fix for that. */
7462 static void
7463 fix_new_arm (fragS * frag,
7464 int where,
7465 short int size,
7466 expressionS * exp,
7467 int pc_rel,
7468 int reloc)
7470 fixS * new_fix;
7472 switch (exp->X_op)
7474 case O_constant:
7475 case O_symbol:
7476 case O_add:
7477 case O_subtract:
7478 new_fix = fix_new_exp (frag, where, size, exp, pc_rel, reloc);
7479 break;
7481 default:
7482 new_fix = fix_new (frag, where, size, make_expr_symbol (exp), 0,
7483 pc_rel, reloc);
7484 break;
7487 /* Mark whether the fix is to a THUMB instruction, or an ARM
7488 instruction. */
7489 new_fix->tc_fix_data = thumb_mode;
7492 static void
7493 output_inst (const char * str)
7495 char * to = NULL;
7497 if (inst.error)
7499 as_bad ("%s -- `%s'", inst.error, str);
7500 return;
7502 if (inst.size == 0)
7503 return;
7505 to = frag_more (inst.size);
7507 if (thumb_mode && (inst.size > THUMB_SIZE))
7509 assert (inst.size == (2 * THUMB_SIZE));
7510 md_number_to_chars (to, inst.instruction >> 16, THUMB_SIZE);
7511 md_number_to_chars (to + THUMB_SIZE, inst.instruction, THUMB_SIZE);
7513 else if (inst.size > INSN_SIZE)
7515 assert (inst.size == (2 * INSN_SIZE));
7516 md_number_to_chars (to, inst.instruction, INSN_SIZE);
7517 md_number_to_chars (to + INSN_SIZE, inst.instruction, INSN_SIZE);
7519 else
7520 md_number_to_chars (to, inst.instruction, inst.size);
7522 if (inst.reloc.type != BFD_RELOC_UNUSED)
7523 fix_new_arm (frag_now, to - frag_now->fr_literal,
7524 inst.size, & inst.reloc.exp, inst.reloc.pc_rel,
7525 inst.reloc.type);
7527 #ifdef OBJ_ELF
7528 dwarf2_emit_insn (inst.size);
7529 #endif
7532 /* Tag values used in struct asm_opcode's tag field. */
7533 enum opcode_tag
7535 OT_unconditional, /* Instruction cannot be conditionalized.
7536 The ARM condition field is still 0xE. */
7537 OT_unconditionalF, /* Instruction cannot be conditionalized
7538 and carries 0xF in its ARM condition field. */
7539 OT_csuffix, /* Instruction takes a conditional suffix. */
7540 OT_cinfix3, /* Instruction takes a conditional infix,
7541 beginning at character index 3. (In
7542 unified mode, it becomes a suffix.) */
7543 OT_csuf_or_in3, /* Instruction takes either a conditional
7544 suffix or an infix at character index 3.
7545 (In unified mode, a suffix only. */
7546 OT_odd_infix_unc, /* This is the unconditional variant of an
7547 instruction that takes a conditional infix
7548 at an unusual position. In unified mode,
7549 this variant will accept a suffix. */
7550 OT_odd_infix_0 /* Values greater than or equal to OT_odd_infix_0
7551 are the conditional variants of instructions that
7552 take conditional infixes in unusual positions.
7553 The infix appears at character index
7554 (tag - OT_odd_infix_0). These are not accepted
7555 in unified mode. */
7558 /* Subroutine of md_assemble, responsible for looking up the primary
7559 opcode from the mnemonic the user wrote. STR points to the
7560 beginning of the mnemonic.
7562 This is not simply a hash table lookup, because of conditional
7563 variants. Most instructions have conditional variants, which are
7564 expressed with a _conditional affix_ to the mnemonic. If we were
7565 to encode each conditional variant as a literal string in the opcode
7566 table, it would have approximately 20,000 entries.
7568 Most mnemonics take this affix as a suffix, and in unified syntax,
7569 'most' is upgraded to 'all'. However, in the divided syntax, some
7570 instructions take the affix as an infix, notably the s-variants of
7571 the arithmetic instructions. Of those instructions, all but six
7572 have the infix appear after the third character of the mnemonic.
7574 Accordingly, the algorithm for looking up primary opcodes given
7575 an identifier is:
7577 1. Look up the identifier in the opcode table.
7578 If we find a match, go to step U.
7580 2. Look up the last two characters of the identifier in the
7581 conditions table. If we find a match, look up the first N-2
7582 characters of the identifier in the opcode table. If we
7583 find a match, go to step CE.
7585 3. Look up the fourth and fifth characters of the identifier in
7586 the conditions table. If we find a match, extract those
7587 characters from the identifier, and look up the remaining
7588 characters in the opcode table. If we find a match, go
7589 to step CM.
7591 4. Fail.
7593 U. Examine the tag field of the opcode structure, in case this is
7594 one of the six instructions with its conditional infix in an
7595 unusual place. If it is, the tag tells us where to find the
7596 infix; look it up in the conditions table and set inst.cond
7597 accordingly. Otherwise, this is an unconditional instruction.
7598 Again set inst.cond accordingly. Return the opcode structure.
7600 CE. Examine the tag field to make sure this is an instruction that
7601 should receive a conditional suffix. If it is not, fail.
7602 Otherwise, set inst.cond from the suffix we already looked up,
7603 and return the opcode structure.
7605 CM. Examine the tag field to make sure this is an instruction that
7606 should receive a conditional infix after the third character.
7607 If it is not, fail. Otherwise, undo the edits to the current
7608 line of input and proceed as for case CE. */
7610 static const struct asm_opcode *
7611 opcode_lookup (char **str)
7613 char *end, *base;
7614 char *affix;
7615 const struct asm_opcode *opcode;
7616 const struct asm_cond *cond;
7618 /* Scan up to the end of the mnemonic, which must end in white space,
7619 '.' (in unified mode only), or end of string. */
7620 for (base = end = *str; *end != '\0'; end++)
7621 if (*end == ' ' || (unified_syntax && *end == '.'))
7622 break;
7624 if (end == base)
7625 return 0;
7627 /* Handle a possible width suffix. */
7628 if (end[0] == '.')
7630 if (end[1] == 'w' && (end[2] == ' ' || end[2] == '\0'))
7631 inst.size_req = 4;
7632 else if (end[1] == 'n' && (end[2] == ' ' || end[2] == '\0'))
7633 inst.size_req = 2;
7634 else
7635 return 0;
7637 *str = end + 2;
7639 else
7640 *str = end;
7642 /* Look for unaffixed or special-case affixed mnemonic. */
7643 opcode = hash_find_n (arm_ops_hsh, base, end - base);
7644 if (opcode)
7646 /* step U */
7647 if (opcode->tag < OT_odd_infix_0)
7649 inst.cond = COND_ALWAYS;
7650 return opcode;
7653 if (unified_syntax)
7654 as_warn (_("conditional infixes are deprecated in unified syntax"));
7655 affix = base + (opcode->tag - OT_odd_infix_0);
7656 cond = hash_find_n (arm_cond_hsh, affix, 2);
7657 assert (cond);
7659 inst.cond = cond->value;
7660 return opcode;
7663 /* Cannot have a conditional suffix on a mnemonic of less than two
7664 characters. */
7665 if (end - base < 3)
7666 return 0;
7668 /* Look for suffixed mnemonic. */
7669 affix = end - 2;
7670 cond = hash_find_n (arm_cond_hsh, affix, 2);
7671 opcode = hash_find_n (arm_ops_hsh, base, affix - base);
7672 if (opcode && cond)
7674 /* step CE */
7675 switch (opcode->tag)
7677 case OT_cinfix3:
7678 case OT_odd_infix_unc:
7679 if (!unified_syntax)
7680 return 0;
7681 /* else fall through */
7683 case OT_csuffix:
7684 case OT_csuf_or_in3:
7685 inst.cond = cond->value;
7686 return opcode;
7688 case OT_unconditional:
7689 case OT_unconditionalF:
7690 /* delayed diagnostic */
7691 inst.error = BAD_COND;
7692 inst.cond = COND_ALWAYS;
7693 return opcode;
7695 default:
7696 return 0;
7700 /* Cannot have a usual-position infix on a mnemonic of less than
7701 six characters (five would be a suffix). */
7702 if (end - base < 6)
7703 return 0;
7705 /* Look for infixed mnemonic in the usual position. */
7706 affix = base + 3;
7707 cond = hash_find_n (arm_cond_hsh, affix, 2);
7708 if (cond)
7710 char save[2];
7711 memcpy (save, affix, 2);
7712 memmove (affix, affix + 2, (end - affix) - 2);
7713 opcode = hash_find_n (arm_ops_hsh, base, (end - base) - 2);
7714 memmove (affix + 2, affix, (end - affix) - 2);
7715 memcpy (affix, save, 2);
7717 if (opcode && (opcode->tag == OT_cinfix3 || opcode->tag == OT_csuf_or_in3))
7719 /* step CM */
7720 if (unified_syntax)
7721 as_warn (_("conditional infixes are deprecated in unified syntax"));
7723 inst.cond = cond->value;
7724 return opcode;
7727 return 0;
7730 void
7731 md_assemble (char *str)
7733 char *p = str;
7734 const struct asm_opcode * opcode;
7736 /* Align the previous label if needed. */
7737 if (last_label_seen != NULL)
7739 symbol_set_frag (last_label_seen, frag_now);
7740 S_SET_VALUE (last_label_seen, (valueT) frag_now_fix ());
7741 S_SET_SEGMENT (last_label_seen, now_seg);
7744 memset (&inst, '\0', sizeof (inst));
7745 inst.reloc.type = BFD_RELOC_UNUSED;
7747 opcode = opcode_lookup (&p);
7748 if (!opcode)
7750 /* It wasn't an instruction, but it might be a register alias of
7751 the form alias .req reg. */
7752 if (!create_register_alias (str, p))
7753 as_bad (_("bad instruction `%s'"), str);
7755 return;
7758 if (thumb_mode)
7760 /* Check that this instruction is supported for this CPU. */
7761 if (thumb_mode == 1 && (opcode->tvariant & cpu_variant) == 0)
7763 as_bad (_("selected processor does not support `%s'"), str);
7764 return;
7766 if (inst.cond != COND_ALWAYS && !unified_syntax
7767 && opcode->tencode != do_t_branch)
7769 as_bad (_("Thumb does not support conditional execution"));
7770 return;
7773 /* Check conditional suffixes. */
7774 if (current_it_mask)
7776 int cond;
7777 cond = current_cc ^ ((current_it_mask >> 4) & 1) ^ 1;
7778 if (cond != inst.cond)
7780 as_bad (_("incorrect condition in IT block"));
7781 return;
7783 current_it_mask <<= 1;
7784 current_it_mask &= 0x1f;
7786 else if (inst.cond != COND_ALWAYS && opcode->tencode != do_t_branch)
7788 as_bad (_("thumb conditional instrunction not in IT block"));
7789 return;
7792 mapping_state (MAP_THUMB);
7793 inst.instruction = opcode->tvalue;
7795 if (!parse_operands (p, opcode->operands))
7796 opcode->tencode ();
7798 /* Clear current_it_mask at the end of an IT block. */
7799 if (current_it_mask == 0x10)
7800 current_it_mask = 0;
7802 if (!inst.error)
7804 assert (inst.instruction < 0xe800 || inst.instruction > 0xffff);
7805 inst.size = (inst.instruction > 0xffff ? 4 : 2);
7806 if (inst.size_req && inst.size_req != inst.size)
7808 as_bad (_("cannot honor width suffix -- `%s'"), str);
7809 return;
7813 else
7815 /* Check that this instruction is supported for this CPU. */
7816 if ((opcode->avariant & cpu_variant) == 0)
7818 as_bad (_("selected processor does not support `%s'"), str);
7819 return;
7821 if (inst.size_req)
7823 as_bad (_("width suffixes are invalid in ARM mode -- `%s'"), str);
7824 return;
7827 mapping_state (MAP_ARM);
7828 inst.instruction = opcode->avalue;
7829 if (opcode->tag == OT_unconditionalF)
7830 inst.instruction |= 0xF << 28;
7831 else
7832 inst.instruction |= inst.cond << 28;
7833 inst.size = INSN_SIZE;
7834 if (!parse_operands (p, opcode->operands))
7835 opcode->aencode ();
7837 output_inst (str);
7840 /* Various frobbings of labels and their addresses. */
7842 void
7843 arm_start_line_hook (void)
7845 last_label_seen = NULL;
7848 void
7849 arm_frob_label (symbolS * sym)
7851 last_label_seen = sym;
7853 ARM_SET_THUMB (sym, thumb_mode);
7855 #if defined OBJ_COFF || defined OBJ_ELF
7856 ARM_SET_INTERWORK (sym, support_interwork);
7857 #endif
7859 /* Note - do not allow local symbols (.Lxxx) to be labeled
7860 as Thumb functions. This is because these labels, whilst
7861 they exist inside Thumb code, are not the entry points for
7862 possible ARM->Thumb calls. Also, these labels can be used
7863 as part of a computed goto or switch statement. eg gcc
7864 can generate code that looks like this:
7866 ldr r2, [pc, .Laaa]
7867 lsl r3, r3, #2
7868 ldr r2, [r3, r2]
7869 mov pc, r2
7871 .Lbbb: .word .Lxxx
7872 .Lccc: .word .Lyyy
7873 ..etc...
7874 .Laaa: .word Lbbb
7876 The first instruction loads the address of the jump table.
7877 The second instruction converts a table index into a byte offset.
7878 The third instruction gets the jump address out of the table.
7879 The fourth instruction performs the jump.
7881 If the address stored at .Laaa is that of a symbol which has the
7882 Thumb_Func bit set, then the linker will arrange for this address
7883 to have the bottom bit set, which in turn would mean that the
7884 address computation performed by the third instruction would end
7885 up with the bottom bit set. Since the ARM is capable of unaligned
7886 word loads, the instruction would then load the incorrect address
7887 out of the jump table, and chaos would ensue. */
7888 if (label_is_thumb_function_name
7889 && (S_GET_NAME (sym)[0] != '.' || S_GET_NAME (sym)[1] != 'L')
7890 && (bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) != 0)
7892 /* When the address of a Thumb function is taken the bottom
7893 bit of that address should be set. This will allow
7894 interworking between Arm and Thumb functions to work
7895 correctly. */
7897 THUMB_SET_FUNC (sym, 1);
7899 label_is_thumb_function_name = FALSE;
7904 arm_data_in_code (void)
7906 if (thumb_mode && ! strncmp (input_line_pointer + 1, "data:", 5))
7908 *input_line_pointer = '/';
7909 input_line_pointer += 5;
7910 *input_line_pointer = 0;
7911 return 1;
7914 return 0;
7917 char *
7918 arm_canonicalize_symbol_name (char * name)
7920 int len;
7922 if (thumb_mode && (len = strlen (name)) > 5
7923 && streq (name + len - 5, "/data"))
7924 *(name + len - 5) = 0;
7926 return name;
7929 /* Table of all register names defined by default. The user can
7930 define additional names with .req. Note that all register names
7931 should appear in both upper and lowercase variants. Some registers
7932 also have mixed-case names. */
7934 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE }
7935 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
7936 #define REGSET(p,t) \
7937 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
7938 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
7939 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
7940 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
7942 static const struct reg_entry reg_names[] =
7944 /* ARM integer registers. */
7945 REGSET(r, RN), REGSET(R, RN),
7947 /* ATPCS synonyms. */
7948 REGDEF(a1,0,RN), REGDEF(a2,1,RN), REGDEF(a3, 2,RN), REGDEF(a4, 3,RN),
7949 REGDEF(v1,4,RN), REGDEF(v2,5,RN), REGDEF(v3, 6,RN), REGDEF(v4, 7,RN),
7950 REGDEF(v5,8,RN), REGDEF(v6,9,RN), REGDEF(v7,10,RN), REGDEF(v8,11,RN),
7952 REGDEF(A1,0,RN), REGDEF(A2,1,RN), REGDEF(A3, 2,RN), REGDEF(A4, 3,RN),
7953 REGDEF(V1,4,RN), REGDEF(V2,5,RN), REGDEF(V3, 6,RN), REGDEF(V4, 7,RN),
7954 REGDEF(V5,8,RN), REGDEF(V6,9,RN), REGDEF(V7,10,RN), REGDEF(V8,11,RN),
7956 /* Well-known aliases. */
7957 REGDEF(wr, 7,RN), REGDEF(sb, 9,RN), REGDEF(sl,10,RN), REGDEF(fp,11,RN),
7958 REGDEF(ip,12,RN), REGDEF(sp,13,RN), REGDEF(lr,14,RN), REGDEF(pc,15,RN),
7960 REGDEF(WR, 7,RN), REGDEF(SB, 9,RN), REGDEF(SL,10,RN), REGDEF(FP,11,RN),
7961 REGDEF(IP,12,RN), REGDEF(SP,13,RN), REGDEF(LR,14,RN), REGDEF(PC,15,RN),
7963 /* Coprocessor numbers. */
7964 REGSET(p, CP), REGSET(P, CP),
7966 /* Coprocessor register numbers. The "cr" variants are for backward
7967 compatibility. */
7968 REGSET(c, CN), REGSET(C, CN),
7969 REGSET(cr, CN), REGSET(CR, CN),
7971 /* FPA registers. */
7972 REGNUM(f,0,FN), REGNUM(f,1,FN), REGNUM(f,2,FN), REGNUM(f,3,FN),
7973 REGNUM(f,4,FN), REGNUM(f,5,FN), REGNUM(f,6,FN), REGNUM(f,7, FN),
7975 REGNUM(F,0,FN), REGNUM(F,1,FN), REGNUM(F,2,FN), REGNUM(F,3,FN),
7976 REGNUM(F,4,FN), REGNUM(F,5,FN), REGNUM(F,6,FN), REGNUM(F,7, FN),
7978 /* VFP SP registers. */
7979 REGSET(s,VFS),
7980 REGNUM(s,16,VFS), REGNUM(s,17,VFS), REGNUM(s,18,VFS), REGNUM(s,19,VFS),
7981 REGNUM(s,20,VFS), REGNUM(s,21,VFS), REGNUM(s,22,VFS), REGNUM(s,23,VFS),
7982 REGNUM(s,24,VFS), REGNUM(s,25,VFS), REGNUM(s,26,VFS), REGNUM(s,27,VFS),
7983 REGNUM(s,28,VFS), REGNUM(s,29,VFS), REGNUM(s,30,VFS), REGNUM(s,31,VFS),
7985 REGSET(S,VFS),
7986 REGNUM(S,16,VFS), REGNUM(S,17,VFS), REGNUM(S,18,VFS), REGNUM(S,19,VFS),
7987 REGNUM(S,20,VFS), REGNUM(S,21,VFS), REGNUM(S,22,VFS), REGNUM(S,23,VFS),
7988 REGNUM(S,24,VFS), REGNUM(S,25,VFS), REGNUM(S,26,VFS), REGNUM(S,27,VFS),
7989 REGNUM(S,28,VFS), REGNUM(S,29,VFS), REGNUM(S,30,VFS), REGNUM(S,31,VFS),
7991 /* VFP DP Registers. */
7992 REGSET(d,VFD), REGSET(D,VFS),
7994 /* VFP control registers. */
7995 REGDEF(fpsid,0,VFC), REGDEF(fpscr,1,VFC), REGDEF(fpexc,8,VFC),
7996 REGDEF(FPSID,0,VFC), REGDEF(FPSCR,1,VFC), REGDEF(FPEXC,8,VFC),
7998 /* Maverick DSP coprocessor registers. */
7999 REGSET(mvf,MVF), REGSET(mvd,MVD), REGSET(mvfx,MVFX), REGSET(mvdx,MVDX),
8000 REGSET(MVF,MVF), REGSET(MVD,MVD), REGSET(MVFX,MVFX), REGSET(MVDX,MVDX),
8002 REGNUM(mvax,0,MVAX), REGNUM(mvax,1,MVAX),
8003 REGNUM(mvax,2,MVAX), REGNUM(mvax,3,MVAX),
8004 REGDEF(dspsc,0,DSPSC),
8006 REGNUM(MVAX,0,MVAX), REGNUM(MVAX,1,MVAX),
8007 REGNUM(MVAX,2,MVAX), REGNUM(MVAX,3,MVAX),
8008 REGDEF(DSPSC,0,DSPSC),
8010 /* iWMMXt data registers - p0, c0-15. */
8011 REGSET(wr,MMXWR), REGSET(wR,MMXWR), REGSET(WR, MMXWR),
8013 /* iWMMXt control registers - p1, c0-3. */
8014 REGDEF(wcid, 0,MMXWC), REGDEF(wCID, 0,MMXWC), REGDEF(WCID, 0,MMXWC),
8015 REGDEF(wcon, 1,MMXWC), REGDEF(wCon, 1,MMXWC), REGDEF(WCON, 1,MMXWC),
8016 REGDEF(wcssf, 2,MMXWC), REGDEF(wCSSF, 2,MMXWC), REGDEF(WCSSF, 2,MMXWC),
8017 REGDEF(wcasf, 3,MMXWC), REGDEF(wCASF, 3,MMXWC), REGDEF(WCASF, 3,MMXWC),
8019 /* iWMMXt scalar (constant/offset) registers - p1, c8-11. */
8020 REGDEF(wcgr0, 8,MMXWCG), REGDEF(wCGR0, 8,MMXWCG), REGDEF(WCGR0, 8,MMXWCG),
8021 REGDEF(wcgr1, 9,MMXWCG), REGDEF(wCGR1, 9,MMXWCG), REGDEF(WCGR1, 9,MMXWCG),
8022 REGDEF(wcgr2,10,MMXWCG), REGDEF(wCGR2,10,MMXWCG), REGDEF(WCGR2,10,MMXWCG),
8023 REGDEF(wcgr3,11,MMXWCG), REGDEF(wCGR3,11,MMXWCG), REGDEF(WCGR3,11,MMXWCG),
8025 /* XScale accumulator registers. */
8026 REGNUM(acc,0,XSCALE), REGNUM(ACC,0,XSCALE),
8028 #undef REGDEF
8029 #undef REGNUM
8030 #undef REGSET
8032 /* Table of all PSR suffixes. Bare "CPSR" and "SPSR" are handled
8033 within psr_required_here. */
8034 static const struct asm_psr psrs[] =
8036 /* Backward compatibility notation. Note that "all" is no longer
8037 truly all possible PSR bits. */
8038 {"all", PSR_c | PSR_f},
8039 {"flg", PSR_f},
8040 {"ctl", PSR_c},
8042 /* Individual flags. */
8043 {"f", PSR_f},
8044 {"c", PSR_c},
8045 {"x", PSR_x},
8046 {"s", PSR_s},
8047 /* Combinations of flags. */
8048 {"fs", PSR_f | PSR_s},
8049 {"fx", PSR_f | PSR_x},
8050 {"fc", PSR_f | PSR_c},
8051 {"sf", PSR_s | PSR_f},
8052 {"sx", PSR_s | PSR_x},
8053 {"sc", PSR_s | PSR_c},
8054 {"xf", PSR_x | PSR_f},
8055 {"xs", PSR_x | PSR_s},
8056 {"xc", PSR_x | PSR_c},
8057 {"cf", PSR_c | PSR_f},
8058 {"cs", PSR_c | PSR_s},
8059 {"cx", PSR_c | PSR_x},
8060 {"fsx", PSR_f | PSR_s | PSR_x},
8061 {"fsc", PSR_f | PSR_s | PSR_c},
8062 {"fxs", PSR_f | PSR_x | PSR_s},
8063 {"fxc", PSR_f | PSR_x | PSR_c},
8064 {"fcs", PSR_f | PSR_c | PSR_s},
8065 {"fcx", PSR_f | PSR_c | PSR_x},
8066 {"sfx", PSR_s | PSR_f | PSR_x},
8067 {"sfc", PSR_s | PSR_f | PSR_c},
8068 {"sxf", PSR_s | PSR_x | PSR_f},
8069 {"sxc", PSR_s | PSR_x | PSR_c},
8070 {"scf", PSR_s | PSR_c | PSR_f},
8071 {"scx", PSR_s | PSR_c | PSR_x},
8072 {"xfs", PSR_x | PSR_f | PSR_s},
8073 {"xfc", PSR_x | PSR_f | PSR_c},
8074 {"xsf", PSR_x | PSR_s | PSR_f},
8075 {"xsc", PSR_x | PSR_s | PSR_c},
8076 {"xcf", PSR_x | PSR_c | PSR_f},
8077 {"xcs", PSR_x | PSR_c | PSR_s},
8078 {"cfs", PSR_c | PSR_f | PSR_s},
8079 {"cfx", PSR_c | PSR_f | PSR_x},
8080 {"csf", PSR_c | PSR_s | PSR_f},
8081 {"csx", PSR_c | PSR_s | PSR_x},
8082 {"cxf", PSR_c | PSR_x | PSR_f},
8083 {"cxs", PSR_c | PSR_x | PSR_s},
8084 {"fsxc", PSR_f | PSR_s | PSR_x | PSR_c},
8085 {"fscx", PSR_f | PSR_s | PSR_c | PSR_x},
8086 {"fxsc", PSR_f | PSR_x | PSR_s | PSR_c},
8087 {"fxcs", PSR_f | PSR_x | PSR_c | PSR_s},
8088 {"fcsx", PSR_f | PSR_c | PSR_s | PSR_x},
8089 {"fcxs", PSR_f | PSR_c | PSR_x | PSR_s},
8090 {"sfxc", PSR_s | PSR_f | PSR_x | PSR_c},
8091 {"sfcx", PSR_s | PSR_f | PSR_c | PSR_x},
8092 {"sxfc", PSR_s | PSR_x | PSR_f | PSR_c},
8093 {"sxcf", PSR_s | PSR_x | PSR_c | PSR_f},
8094 {"scfx", PSR_s | PSR_c | PSR_f | PSR_x},
8095 {"scxf", PSR_s | PSR_c | PSR_x | PSR_f},
8096 {"xfsc", PSR_x | PSR_f | PSR_s | PSR_c},
8097 {"xfcs", PSR_x | PSR_f | PSR_c | PSR_s},
8098 {"xsfc", PSR_x | PSR_s | PSR_f | PSR_c},
8099 {"xscf", PSR_x | PSR_s | PSR_c | PSR_f},
8100 {"xcfs", PSR_x | PSR_c | PSR_f | PSR_s},
8101 {"xcsf", PSR_x | PSR_c | PSR_s | PSR_f},
8102 {"cfsx", PSR_c | PSR_f | PSR_s | PSR_x},
8103 {"cfxs", PSR_c | PSR_f | PSR_x | PSR_s},
8104 {"csfx", PSR_c | PSR_s | PSR_f | PSR_x},
8105 {"csxf", PSR_c | PSR_s | PSR_x | PSR_f},
8106 {"cxfs", PSR_c | PSR_x | PSR_f | PSR_s},
8107 {"cxsf", PSR_c | PSR_x | PSR_s | PSR_f},
8110 /* Table of all shift-in-operand names. */
8111 static const struct asm_shift_name shift_names [] =
8113 { "asl", SHIFT_LSL }, { "ASL", SHIFT_LSL },
8114 { "lsl", SHIFT_LSL }, { "LSL", SHIFT_LSL },
8115 { "lsr", SHIFT_LSR }, { "LSR", SHIFT_LSR },
8116 { "asr", SHIFT_ASR }, { "ASR", SHIFT_ASR },
8117 { "ror", SHIFT_ROR }, { "ROR", SHIFT_ROR },
8118 { "rrx", SHIFT_RRX }, { "RRX", SHIFT_RRX }
8121 /* Table of all explicit relocation names. */
8122 #ifdef OBJ_ELF
8123 static struct reloc_entry reloc_names[] =
8125 { "got", BFD_RELOC_ARM_GOT32 }, { "GOT", BFD_RELOC_ARM_GOT32 },
8126 { "gotoff", BFD_RELOC_ARM_GOTOFF }, { "GOTOFF", BFD_RELOC_ARM_GOTOFF },
8127 { "plt", BFD_RELOC_ARM_PLT32 }, { "PLT", BFD_RELOC_ARM_PLT32 },
8128 { "target1", BFD_RELOC_ARM_TARGET1 }, { "TARGET1", BFD_RELOC_ARM_TARGET1 },
8129 { "target2", BFD_RELOC_ARM_TARGET2 }, { "TARGET2", BFD_RELOC_ARM_TARGET2 },
8130 { "sbrel", BFD_RELOC_ARM_SBREL32 }, { "SBREL", BFD_RELOC_ARM_SBREL32 },
8131 { "tlsgd", BFD_RELOC_ARM_TLS_GD32}, { "TLSGD", BFD_RELOC_ARM_TLS_GD32},
8132 { "tlsldm", BFD_RELOC_ARM_TLS_LDM32}, { "TLSLDM", BFD_RELOC_ARM_TLS_LDM32},
8133 { "tlsldo", BFD_RELOC_ARM_TLS_LDO32}, { "TLSLDO", BFD_RELOC_ARM_TLS_LDO32},
8134 { "gottpoff",BFD_RELOC_ARM_TLS_IE32}, { "GOTTPOFF",BFD_RELOC_ARM_TLS_IE32},
8135 { "tpoff", BFD_RELOC_ARM_TLS_LE32}, { "TPOFF", BFD_RELOC_ARM_TLS_LE32}
8137 #endif
8139 /* Table of all conditional affixes. 0xF is not defined as a condition code. */
8140 static const struct asm_cond conds[] =
8142 {"eq", 0x0},
8143 {"ne", 0x1},
8144 {"cs", 0x2}, {"hs", 0x2},
8145 {"cc", 0x3}, {"ul", 0x3}, {"lo", 0x3},
8146 {"mi", 0x4},
8147 {"pl", 0x5},
8148 {"vs", 0x6},
8149 {"vc", 0x7},
8150 {"hi", 0x8},
8151 {"ls", 0x9},
8152 {"ge", 0xa},
8153 {"lt", 0xb},
8154 {"gt", 0xc},
8155 {"le", 0xd},
8156 {"al", 0xe}
8159 /* Table of ARM-format instructions. */
8161 /* Macros for gluing together operand strings. N.B. In all cases
8162 other than OPS0, the trailing OP_stop comes from default
8163 zero-initialization of the unspecified elements of the array. */
8164 #define OPS0() { OP_stop, }
8165 #define OPS1(a) { OP_##a, }
8166 #define OPS2(a,b) { OP_##a,OP_##b, }
8167 #define OPS3(a,b,c) { OP_##a,OP_##b,OP_##c, }
8168 #define OPS4(a,b,c,d) { OP_##a,OP_##b,OP_##c,OP_##d, }
8169 #define OPS5(a,b,c,d,e) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e, }
8170 #define OPS6(a,b,c,d,e,f) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e,OP_##f, }
8172 /* These macros abstract out the exact format of the mnemonic table and
8173 save some repeated characters. */
8175 /* The normal sort of mnemonic; has a Thumb variant; takes a conditional suffix. */
8176 #define TxCE(mnem, op, top, nops, ops, ae, te) \
8177 { #mnem, OPS##nops ops, OT_csuffix, 0x##op, top, ARM_VARIANT, \
8178 THUMB_VARIANT, do_##ae, do_##te }
8180 /* Two variants of the above - TCE for a numeric Thumb opcode, tCE for
8181 a T_MNEM_xyz enumerator. */
8182 #define TCE(mnem, aop, top, nops, ops, ae, te) \
8183 TxCE(mnem, aop, 0x##top, nops, ops, ae, te)
8184 #define tCE(mnem, aop, top, nops, ops, ae, te) \
8185 TxCE(mnem, aop, T_MNEM_##top, nops, ops, ae, te)
8187 /* Second most common sort of mnemonic: has a Thumb variant, takes a conditional
8188 infix after the third character. */
8189 #define TxC3(mnem, op, top, nops, ops, ae, te) \
8190 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, top, ARM_VARIANT, \
8191 THUMB_VARIANT, do_##ae, do_##te }
8192 #define TC3(mnem, aop, top, nops, ops, ae, te) \
8193 TxC3(mnem, aop, 0x##top, nops, ops, ae, te)
8194 #define tC3(mnem, aop, top, nops, ops, ae, te) \
8195 TxC3(mnem, aop, T_MNEM_##top, nops, ops, ae, te)
8197 /* Mnemonic with a conditional infix in an unusual place. Each and every variant has to
8198 appear in the condition table. */
8199 #define TxCM_(m1, m2, m3, op, top, nops, ops, ae, te) \
8200 { #m1 #m2 #m3, OPS##nops ops, sizeof(#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof(#m1) - 1, \
8201 0x##op, top, ARM_VARIANT, THUMB_VARIANT, do_##ae, do_##te }
8203 #define TxCM(m1, m2, op, top, nops, ops, ae, te) \
8204 TxCM_(m1, , m2, op, top, nops, ops, ae, te), \
8205 TxCM_(m1, eq, m2, op, top, nops, ops, ae, te), \
8206 TxCM_(m1, ne, m2, op, top, nops, ops, ae, te), \
8207 TxCM_(m1, cs, m2, op, top, nops, ops, ae, te), \
8208 TxCM_(m1, hs, m2, op, top, nops, ops, ae, te), \
8209 TxCM_(m1, cc, m2, op, top, nops, ops, ae, te), \
8210 TxCM_(m1, ul, m2, op, top, nops, ops, ae, te), \
8211 TxCM_(m1, lo, m2, op, top, nops, ops, ae, te), \
8212 TxCM_(m1, mi, m2, op, top, nops, ops, ae, te), \
8213 TxCM_(m1, pl, m2, op, top, nops, ops, ae, te), \
8214 TxCM_(m1, vs, m2, op, top, nops, ops, ae, te), \
8215 TxCM_(m1, vc, m2, op, top, nops, ops, ae, te), \
8216 TxCM_(m1, hi, m2, op, top, nops, ops, ae, te), \
8217 TxCM_(m1, ls, m2, op, top, nops, ops, ae, te), \
8218 TxCM_(m1, ge, m2, op, top, nops, ops, ae, te), \
8219 TxCM_(m1, lt, m2, op, top, nops, ops, ae, te), \
8220 TxCM_(m1, gt, m2, op, top, nops, ops, ae, te), \
8221 TxCM_(m1, le, m2, op, top, nops, ops, ae, te), \
8222 TxCM_(m1, al, m2, op, top, nops, ops, ae, te)
8224 #define TCM(m1,m2, aop, top, nops, ops, ae, te) \
8225 TxCM(m1,m2, aop, 0x##top, nops, ops, ae, te)
8226 #define tCM(m1,m2, aop, top, nops, ops, ae, te) \
8227 TxCM(m1,m2, aop, T_MNEM_##top, nops, ops, ae, te)
8229 /* Mnemonic that cannot be conditionalized. The ARM condition-code
8230 field is still 0xE. */
8231 #define TUE(mnem, op, top, nops, ops, ae, te) \
8232 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
8233 THUMB_VARIANT, do_##ae, do_##te }
8235 /* Mnemonic that cannot be conditionalized, and bears 0xF in its ARM
8236 condition code field. */
8237 #define TUF(mnem, op, top, nops, ops, ae, te) \
8238 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##top, ARM_VARIANT, \
8239 THUMB_VARIANT, do_##ae, do_##te }
8241 /* ARM-only variants of all the above. */
8242 #define CE(mnem, op, nops, ops, ae) \
8243 { #mnem, OPS##nops ops, OT_csuffix, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
8245 #define C3(mnem, op, nops, ops, ae) \
8246 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
8248 #define xCM_(m1, m2, m3, op, nops, ops, ae) \
8249 { #m1 #m2 #m3, OPS##nops ops, \
8250 sizeof(#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof(#m1) - 1, \
8251 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
8253 #define CM(m1, m2, op, nops, ops, ae) \
8254 xCM_(m1, , m2, op, nops, ops, ae), \
8255 xCM_(m1, eq, m2, op, nops, ops, ae), \
8256 xCM_(m1, ne, m2, op, nops, ops, ae), \
8257 xCM_(m1, cs, m2, op, nops, ops, ae), \
8258 xCM_(m1, hs, m2, op, nops, ops, ae), \
8259 xCM_(m1, cc, m2, op, nops, ops, ae), \
8260 xCM_(m1, ul, m2, op, nops, ops, ae), \
8261 xCM_(m1, lo, m2, op, nops, ops, ae), \
8262 xCM_(m1, mi, m2, op, nops, ops, ae), \
8263 xCM_(m1, pl, m2, op, nops, ops, ae), \
8264 xCM_(m1, vs, m2, op, nops, ops, ae), \
8265 xCM_(m1, vc, m2, op, nops, ops, ae), \
8266 xCM_(m1, hi, m2, op, nops, ops, ae), \
8267 xCM_(m1, ls, m2, op, nops, ops, ae), \
8268 xCM_(m1, ge, m2, op, nops, ops, ae), \
8269 xCM_(m1, lt, m2, op, nops, ops, ae), \
8270 xCM_(m1, gt, m2, op, nops, ops, ae), \
8271 xCM_(m1, le, m2, op, nops, ops, ae), \
8272 xCM_(m1, al, m2, op, nops, ops, ae)
8274 #define UE(mnem, op, nops, ops, ae) \
8275 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
8277 #define UF(mnem, op, nops, ops, ae) \
8278 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
8280 #define do_0 0
8282 /* Thumb-only, unconditional. */
8283 #define UT(mnem, op, nops, ops, te) TUE(mnem, 0, op, nops, ops, 0, te)
8285 /* ARM-only, takes either a suffix or a position-3 infix
8286 (for an FPA corner case). */
8287 #define C3E(mnem, op, nops, ops, ae) \
8288 { #mnem, OPS##nops ops, OT_csuf_or_in3, 0x##op, 0, ARM_VARIANT, 0, do_##ae, 0 }
8290 static const struct asm_opcode insns[] =
8292 #define ARM_VARIANT ARM_EXT_V1 /* Core ARM Instructions. */
8293 #define THUMB_VARIANT ARM_EXT_V4T
8294 tCE(and, 0000000, and, 3, (RR, oRR, SH), arit, t_arit3c),
8295 tC3(ands, 0100000, ands, 3, (RR, oRR, SH), arit, t_arit3c),
8296 tCE(eor, 0200000, eor, 3, (RR, oRR, SH), arit, t_arit3c),
8297 tC3(eors, 0300000, eors, 3, (RR, oRR, SH), arit, t_arit3c),
8298 tCE(sub, 0400000, sub, 3, (RR, oRR, SH), arit, t_add_sub),
8299 tC3(subs, 0500000, subs, 3, (RR, oRR, SH), arit, t_add_sub),
8300 tCE(add, 0800000, add, 3, (RR, oRR, SH), arit, t_add_sub),
8301 tC3(adds, 0900000, adds, 3, (RR, oRR, SH), arit, t_add_sub),
8302 tCE(adc, 0a00000, adc, 3, (RR, oRR, SH), arit, t_arit3c),
8303 tC3(adcs, 0b00000, adcs, 3, (RR, oRR, SH), arit, t_arit3c),
8304 tCE(sbc, 0c00000, sbc, 3, (RR, oRR, SH), arit, t_arit3),
8305 tC3(sbcs, 0d00000, sbcs, 3, (RR, oRR, SH), arit, t_arit3),
8306 tCE(orr, 1800000, orr, 3, (RR, oRR, SH), arit, t_arit3c),
8307 tC3(orrs, 1900000, orrs, 3, (RR, oRR, SH), arit, t_arit3c),
8308 tCE(bic, 1c00000, bic, 3, (RR, oRR, SH), arit, t_arit3),
8309 tC3(bics, 1d00000, bics, 3, (RR, oRR, SH), arit, t_arit3),
8311 /* The p-variants of tst/cmp/cmn/teq (below) are the pre-V6 mechanism
8312 for setting PSR flag bits. They are obsolete in V6 and do not
8313 have Thumb equivalents. */
8314 tCE(tst, 1100000, tst, 2, (RR, SH), cmp, t_mvn_tst),
8315 tC3(tsts, 1100000, tst, 2, (RR, SH), cmp, t_mvn_tst),
8316 C3(tstp, 110f000, 2, (RR, SH), cmp),
8317 tCE(cmp, 1500000, cmp, 2, (RR, SH), cmp, t_mov_cmp),
8318 tC3(cmps, 1500000, cmp, 2, (RR, SH), cmp, t_mov_cmp),
8319 C3(cmpp, 150f000, 2, (RR, SH), cmp),
8320 tCE(cmn, 1700000, cmn, 2, (RR, SH), cmp, t_mvn_tst),
8321 tC3(cmns, 1700000, cmn, 2, (RR, SH), cmp, t_mvn_tst),
8322 C3(cmnp, 170f000, 2, (RR, SH), cmp),
8324 tCE(mov, 1a00000, mov, 2, (RR, SH), mov, t_mov_cmp),
8325 tC3(movs, 1b00000, movs, 2, (RR, SH), mov, t_mov_cmp),
8326 tCE(mvn, 1e00000, mvn, 2, (RR, SH), mov, t_mvn_tst),
8327 tC3(mvns, 1f00000, mvns, 2, (RR, SH), mov, t_mvn_tst),
8329 tCE(ldr, 4100000, ldr, 2, (RR, ADDR), ldst, t_ldst),
8330 tC3(ldrb, 4500000, ldrb, 2, (RR, ADDR), ldst, t_ldst),
8331 tCE(str, 4000000, str, 2, (RR, ADDR), ldst, t_ldst),
8332 tC3(strb, 4400000, strb, 2, (RR, ADDR), ldst, t_ldst),
8334 tC3(stmia, 8800000, stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
8335 tC3(stmea, 8800000, stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
8336 tC3(ldmia, 8900000, ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
8337 tC3(ldmfd, 8900000, ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
8339 TCE(swi, f000000, df00, 1, (EXPi), swi, t_swi),
8340 TCE(b, a000000, e000, 1, (EXPr), branch, t_branch),
8341 TCE(bl, b000000, f000f800, 1, (EXPr), branch, t_branch23),
8343 /* Pseudo ops. */
8344 tCE(adr, 28f0000, adr, 2, (RR, EXP), adr, t_adr),
8345 C3(adrl, 28f0000, 2, (RR, EXP), adrl),
8346 tCE(nop, 1a00000, nop, 1, (oI255c), nop, t_nop),
8348 /* Thumb-compatibility pseudo ops. */
8349 tCE(lsl, 1a00000, lsl, 3, (RR, oRR, SH), shift, t_shift),
8350 tC3(lsls, 1b00000, lsls, 3, (RR, oRR, SH), shift, t_shift),
8351 tCE(lsr, 1a00020, lsr, 3, (RR, oRR, SH), shift, t_shift),
8352 tC3(lsrs, 1b00020, lsrs, 3, (RR, oRR, SH), shift, t_shift),
8353 tCE(asr, 1a00040, asr, 3, (RR, oRR, SH), shift, t_shift),
8354 tC3(asrs, 1b00040, asrs, 3, (RR, oRR, SH), shift, t_shift),
8355 tCE(ror, 1a00060, ror, 3, (RR, oRR, SH), shift, t_shift),
8356 tC3(rors, 1b00060, rors, 3, (RR, oRR, SH), shift, t_shift),
8357 tCE(neg, 2600000, neg, 2, (RR, RR), rd_rn, t_neg),
8358 tC3(negs, 2700000, negs, 2, (RR, RR), rd_rn, t_neg),
8359 tCE(push, 92d0000, push, 1, (REGLST), push_pop, t_push_pop),
8360 tCE(pop, 8bd0000, pop, 1, (REGLST), push_pop, t_push_pop),
8362 #undef THUMB_VARIANT
8363 #define THUMB_VARIANT ARM_EXT_V6
8364 TCE(cpy, 1a00000, 4600, 2, (RR, RR), rd_rm, t_cpy),
8366 /* V1 instructions with no Thumb analogue prior to V6T2. */
8367 #undef THUMB_VARIANT
8368 #define THUMB_VARIANT ARM_EXT_V6T2
8369 TCE(rsb, 0600000, ebc00000, 3, (RR, oRR, SH), arit, t_rsb),
8370 TC3(rsbs, 0700000, ebd00000, 3, (RR, oRR, SH), arit, t_rsb),
8371 TCE(teq, 1300000, ea900f00, 2, (RR, SH), cmp, t_mvn_tst),
8372 TC3(teqs, 1300000, ea900f00, 2, (RR, SH), cmp, t_mvn_tst),
8373 C3(teqp, 130f000, 2, (RR, SH), cmp),
8375 TC3(ldrt, 4300000, f8500e00, 2, (RR, ADDR), ldstt, t_ldstt),
8376 TC3(ldrbt, 4700000, f8300e00, 2, (RR, ADDR), ldstt, t_ldstt),
8377 TC3(strt, 4200000, f8400e00, 2, (RR, ADDR), ldstt, t_ldstt),
8378 TC3(strbt, 4600000, f8200e00, 2, (RR, ADDR), ldstt, t_ldstt),
8380 TC3(stmdb, 9000000, e9000000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
8381 TC3(stmfd, 9000000, e9000000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
8383 TC3(ldmdb, 9100000, e9100000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
8384 TC3(ldmea, 9100000, e9100000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
8386 /* V1 instructions with no Thumb analogue at all. */
8387 CE(rsc, 0e00000, 3, (RR, oRR, SH), arit),
8388 C3(rscs, 0f00000, 3, (RR, oRR, SH), arit),
8390 C3(stmib, 9800000, 2, (RRw, REGLST), ldmstm),
8391 C3(stmfa, 9800000, 2, (RRw, REGLST), ldmstm),
8392 C3(stmda, 8000000, 2, (RRw, REGLST), ldmstm),
8393 C3(stmed, 8000000, 2, (RRw, REGLST), ldmstm),
8394 C3(ldmib, 9900000, 2, (RRw, REGLST), ldmstm),
8395 C3(ldmed, 9900000, 2, (RRw, REGLST), ldmstm),
8396 C3(ldmda, 8100000, 2, (RRw, REGLST), ldmstm),
8397 C3(ldmfa, 8100000, 2, (RRw, REGLST), ldmstm),
8399 #undef ARM_VARIANT
8400 #define ARM_VARIANT ARM_EXT_V2 /* ARM 2 - multiplies. */
8401 #undef THUMB_VARIANT
8402 #define THUMB_VARIANT ARM_EXT_V4T
8403 tCE(mul, 0000090, mul, 3, (RRnpc, RRnpc, oRR), mul, t_mul),
8404 tC3(muls, 0100090, muls, 3, (RRnpc, RRnpc, oRR), mul, t_mul),
8406 #undef THUMB_VARIANT
8407 #define THUMB_VARIANT ARM_EXT_V6T2
8408 TCE(mla, 0200090, fb000000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas, t_mla),
8409 C3(mlas, 0300090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas),
8411 /* Generic coprocessor instructions. */
8412 TCE(cdp, e000000, ee000000, 6, (RCP, I15b, RCN, RCN, RCN, oI7b), cdp, cdp),
8413 TCE(ldc, c100000, ec100000, 3, (RCP, RCN, ADDR), lstc, lstc),
8414 TC3(ldcl, c500000, ec500000, 3, (RCP, RCN, ADDR), lstc, lstc),
8415 TCE(stc, c000000, ec000000, 3, (RCP, RCN, ADDR), lstc, lstc),
8416 TC3(stcl, c400000, ec400000, 3, (RCP, RCN, ADDR), lstc, lstc),
8417 TCE(mcr, e000010, ee000010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg),
8418 TCE(mrc, e100010, ee100010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg),
8420 #undef ARM_VARIANT
8421 #define ARM_VARIANT ARM_EXT_V2S /* ARM 3 - swp instructions. */
8422 CE(swp, 1000090, 3, (RRnpc, RRnpc, RRnpcb), rd_rm_rn),
8423 C3(swpb, 1400090, 3, (RRnpc, RRnpc, RRnpcb), rd_rm_rn),
8425 #undef ARM_VARIANT
8426 #define ARM_VARIANT ARM_EXT_V3 /* ARM 6 Status register instructions. */
8427 TCE(mrs, 10f0000, f3ef8000, 2, (RR, PSR), mrs, t_mrs),
8428 TCE(msr, 120f000, f3808000, 2, (PSR, RR_EXi), msr, t_msr),
8430 #undef ARM_VARIANT
8431 #define ARM_VARIANT ARM_EXT_V3M /* ARM 7M long multiplies. */
8432 TCE(smull, 0c00090, fb800000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
8433 CM(smull,s, 0d00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
8434 TCE(umull, 0800090, fba00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
8435 CM(umull,s, 0900090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
8436 TCE(smlal, 0e00090, fbc00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
8437 CM(smlal,s, 0f00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
8438 TCE(umlal, 0a00090, fbe00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
8439 CM(umlal,s, 0b00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
8441 #undef ARM_VARIANT
8442 #define ARM_VARIANT ARM_EXT_V4 /* ARM Architecture 4. */
8443 #undef THUMB_VARIANT
8444 #define THUMB_VARIANT ARM_EXT_V4T
8445 tC3(ldrh, 01000b0, ldrh, 2, (RR, ADDR), ldstv4, t_ldst),
8446 tC3(strh, 00000b0, strh, 2, (RR, ADDR), ldstv4, t_ldst),
8447 tC3(ldrsh, 01000f0, ldrsh, 2, (RR, ADDR), ldstv4, t_ldst),
8448 tC3(ldrsb, 01000d0, ldrsb, 2, (RR, ADDR), ldstv4, t_ldst),
8449 tCM(ld,sh, 01000f0, ldrsh, 2, (RR, ADDR), ldstv4, t_ldst),
8450 tCM(ld,sb, 01000d0, ldrsb, 2, (RR, ADDR), ldstv4, t_ldst),
8452 #undef ARM_VARIANT
8453 #define ARM_VARIANT ARM_EXT_V4T|ARM_EXT_V5
8454 /* ARM Architecture 4T. */
8455 /* Note: bx (and blx) are required on V5, even if the processor does
8456 not support Thumb. */
8457 TCE(bx, 12fff10, 4700, 1, (RR), bx, t_bx),
8459 #undef ARM_VARIANT
8460 #define ARM_VARIANT ARM_EXT_V5 /* ARM Architecture 5T. */
8461 #undef THUMB_VARIANT
8462 #define THUMB_VARIANT ARM_EXT_V5T
8463 /* Note: blx has 2 variants; the .value coded here is for
8464 BLX(2). Only this variant has conditional execution. */
8465 TCE(blx, 12fff30, 4780, 1, (RR_EXr), blx, t_blx),
8466 TUE(bkpt, 1200070, be00, 1, (oIffffb), bkpt, t_bkpt),
8468 #undef THUMB_VARIANT
8469 #define THUMB_VARIANT ARM_EXT_V6T2
8470 TCE(clz, 16f0f10, fab0f080, 2, (RRnpc, RRnpc), rd_rm, t_clz),
8471 TUF(ldc2, c100000, fc100000, 3, (RCP, RCN, ADDR), lstc, lstc),
8472 TUF(ldc2l, c500000, fc500000, 3, (RCP, RCN, ADDR), lstc, lstc),
8473 TUF(stc2, c000000, fc000000, 3, (RCP, RCN, ADDR), lstc, lstc),
8474 TUF(stc2l, c400000, fc400000, 3, (RCP, RCN, ADDR), lstc, lstc),
8475 TUF(cdp2, e000000, fe000000, 6, (RCP, I15b, RCN, RCN, RCN, oI7b), cdp, cdp),
8476 TUF(mcr2, e000010, fe000010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg),
8477 TUF(mrc2, e100010, fe100010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg),
8479 #undef ARM_VARIANT
8480 #define ARM_VARIANT ARM_EXT_V5ExP /* ARM Architecture 5TExP. */
8481 TCE(smlabb, 1000080, fb100000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
8482 TCE(smlatb, 10000a0, fb100020, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
8483 TCE(smlabt, 10000c0, fb100010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
8484 TCE(smlatt, 10000e0, fb100030, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
8486 TCE(smlawb, 1200080, fb300000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
8487 TCE(smlawt, 12000c0, fb300010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
8489 TCE(smlalbb, 1400080, fbc00080, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal),
8490 TCE(smlaltb, 14000a0, fbc000a0, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal),
8491 TCE(smlalbt, 14000c0, fbc00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal),
8492 TCE(smlaltt, 14000e0, fbc000b0, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal),
8494 TCE(smulbb, 1600080, fb10f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
8495 TCE(smultb, 16000a0, fb10f020, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
8496 TCE(smulbt, 16000c0, fb10f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
8497 TCE(smultt, 16000e0, fb10f030, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
8499 TCE(smulwb, 12000a0, fb30f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
8500 TCE(smulwt, 12000e0, fb30f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
8502 TCE(qadd, 1000050, fa80f080, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, rd_rm_rn),
8503 TCE(qdadd, 1400050, fa80f090, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, rd_rm_rn),
8504 TCE(qsub, 1200050, fa80f0a0, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, rd_rm_rn),
8505 TCE(qdsub, 1600050, fa80f0b0, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, rd_rm_rn),
8507 #undef ARM_VARIANT
8508 #define ARM_VARIANT ARM_EXT_V5E /* ARM Architecture 5TE. */
8509 TUF(pld, 450f000, f810f000, 1, (ADDR), pld, t_pld),
8510 TC3(ldrd, 00000d0, e9500000, 3, (RRnpc, oRRnpc, ADDR), ldrd, t_ldstd),
8511 TC3(strd, 00000f0, e9400000, 3, (RRnpc, oRRnpc, ADDR), ldrd, t_ldstd),
8513 TCE(mcrr, c400000, ec400000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
8514 TCE(mrrc, c500000, ec500000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
8516 #undef ARM_VARIANT
8517 #define ARM_VARIANT ARM_EXT_V5J /* ARM Architecture 5TEJ. */
8518 TCE(bxj, 12fff20, f3c08f00, 1, (RR), bxj, t_bxj),
8520 #undef ARM_VARIANT
8521 #define ARM_VARIANT ARM_EXT_V6 /* ARM V6. */
8522 #undef THUMB_VARIANT
8523 #define THUMB_VARIANT ARM_EXT_V6
8524 TUF(cpsie, 1080000, b660, 2, (CPSF, oI31b), cpsi, t_cpsi),
8525 TUF(cpsid, 10c0000, b670, 2, (CPSF, oI31b), cpsi, t_cpsi),
8526 tCE(rev, 6bf0f30, rev, 2, (RRnpc, RRnpc), rd_rm, t_rev),
8527 tCE(rev16, 6bf0fb0, rev16, 2, (RRnpc, RRnpc), rd_rm, t_rev),
8528 tCE(revsh, 6ff0fb0, revsh, 2, (RRnpc, RRnpc), rd_rm, t_rev),
8529 tCE(sxth, 6bf0070, sxth, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
8530 tCE(uxth, 6ff0070, uxth, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
8531 tCE(sxtb, 6af0070, sxtb, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
8532 tCE(uxtb, 6ef0070, uxtb, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
8533 TUF(setend, 1010000, b650, 1, (ENDI), setend, t_setend),
8535 #undef THUMB_VARIANT
8536 #define THUMB_VARIANT ARM_EXT_V6T2
8537 TUF(cps, 1020000, f3af8100, 1, (I31b), imm0, imm0),
8538 TCE(ldrex, 1900f9f, e8500f00, 2, (RRnpc, ADDR), ldrex, t_ldrex),
8539 TUF(mcrr2, c400000, fc400000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
8540 TUF(mrrc2, c500000, fc500000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
8541 TCE(pkhbt, 6800010, eac00000, 4, (RRnpc, RRnpc, RRnpc, oSHll), pkhbt, t_pkhbt),
8542 TCE(pkhtb, 6800050, eac00020, 4, (RRnpc, RRnpc, RRnpc, oSHar), pkhtb, t_pkhtb),
8543 TCE(qadd16, 6200f10, fa90f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8544 TCE(qadd8, 6200f90, fa80f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8545 TCE(qaddsubx, 6200f30, faa0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8546 TCE(qsub16, 6200f70, fad0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8547 TCE(qsub8, 6200ff0, fac0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8548 TCE(qsubaddx, 6200f50, fae0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8549 TCE(sadd16, 6100f10, fa90f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8550 TCE(sadd8, 6100f90, fa80f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8551 TCE(saddsubx, 6100f30, faa0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8552 TCE(shadd16, 6300f10, fa90f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8553 TCE(shadd8, 6300f90, fa80f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8554 TCE(shaddsubx, 6300f30, faa0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8555 TCE(shsub16, 6300f70, fad0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8556 TCE(shsub8, 6300ff0, fac0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8557 TCE(shsubaddx, 6300f50, fae0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8558 TCE(ssub16, 6100f70, fad0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8559 TCE(ssub8, 6100ff0, fac0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8560 TCE(ssubaddx, 6100f50, fae0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8561 TCE(uadd16, 6500f10, fa90f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8562 TCE(uadd8, 6500f90, fa80f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8563 TCE(uaddsubx, 6500f30, faa0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8564 TCE(uhadd16, 6700f10, fa90f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8565 TCE(uhadd8, 6700f90, fa80f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8566 TCE(uhaddsubx, 6700f30, faa0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8567 TCE(uhsub16, 6700f70, fad0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8568 TCE(uhsub8, 6700ff0, fac0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8569 TCE(uhsubaddx, 6700f50, fae0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8570 TCE(uqadd16, 6600f10, fa90f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8571 TCE(uqadd8, 6600f90, fa80f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8572 TCE(uqaddsubx, 6600f30, faa0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8573 TCE(uqsub16, 6600f70, fad0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8574 TCE(uqsub8, 6600ff0, fac0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8575 TCE(uqsubaddx, 6600f50, fae0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8576 TCE(usub16, 6500f70, fad0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8577 TCE(usub8, 6500ff0, fac0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8578 TCE(usubaddx, 6500f50, fae0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8579 TUF(rfeia, 8900a00, e990c000, 1, (RRw), rfe, rfe),
8580 UF(rfeib, 9900a00, 1, (RRw), rfe),
8581 UF(rfeda, 8100a00, 1, (RRw), rfe),
8582 TUF(rfedb, 9100a00, e810c000, 1, (RRw), rfe, rfe),
8583 TUF(rfefd, 8900a00, e990c000, 1, (RRw), rfe, rfe),
8584 UF(rfefa, 9900a00, 1, (RRw), rfe),
8585 UF(rfeea, 8100a00, 1, (RRw), rfe),
8586 TUF(rfeed, 9100a00, e810c000, 1, (RRw), rfe, rfe),
8587 TCE(sxtah, 6b00070, fa00f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
8588 TCE(sxtab16, 6800070, fa20f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
8589 TCE(sxtab, 6a00070, fa40f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
8590 TCE(sxtb16, 68f0070, fa2ff080, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
8591 TCE(uxtah, 6f00070, fa10f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
8592 TCE(uxtab16, 6c00070, fa30f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
8593 TCE(uxtab, 6e00070, fa50f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
8594 TCE(uxtb16, 6cf0070, fa3ff080, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
8595 TCE(sel, 68000b0, faa0f080, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8596 TCE(smlad, 7000010, fb200000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
8597 TCE(smladx, 7000030, fb200010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
8598 TCE(smlald, 7400010, fbc000c0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
8599 TCE(smlaldx, 7400030, fbc000d0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
8600 TCE(smlsd, 7000050, fb400000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
8601 TCE(smlsdx, 7000070, fb400010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
8602 TCE(smlsld, 7400050, fbd000c0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
8603 TCE(smlsldx, 7400070, fbd000d0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
8604 TCE(smmla, 7500010, fb500000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
8605 TCE(smmlar, 7500030, fb500010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
8606 TCE(smmls, 75000d0, fb600000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
8607 TCE(smmlsr, 75000f0, fb600010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
8608 TCE(smmul, 750f010, fb50f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
8609 TCE(smmulr, 750f030, fb50f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
8610 TCE(smuad, 700f010, fb20f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
8611 TCE(smuadx, 700f030, fb20f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
8612 TCE(smusd, 700f050, fb40f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
8613 TCE(smusdx, 700f070, fb40f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
8614 TUF(srsia, 8cd0500, e980c000, 1, (I31w), srs, srs),
8615 UF(srsib, 9cd0500, 1, (I31w), srs),
8616 UF(srsda, 84d0500, 1, (I31w), srs),
8617 TUF(srsdb, 94d0500, e800c000, 1, (I31w), srs, srs),
8618 TCE(ssat, 6a00010, f3000000, 4, (RRnpc, I32, RRnpc, oSHllar),ssat, t_ssat),
8619 TCE(ssat16, 6a00f30, f3200000, 3, (RRnpc, I16, RRnpc), ssat16, t_ssat16),
8620 TCE(strex, 1800f90, e8400000, 3, (RRnpc, RRnpc, ADDR), strex, t_strex),
8621 TCE(umaal, 0400090, fbe00060, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal, t_mlal),
8622 TCE(usad8, 780f010, fb70f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
8623 TCE(usada8, 7800010, fb700000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
8624 TCE(usat, 6e00010, f3800000, 4, (RRnpc, I31, RRnpc, oSHllar),usat, t_usat),
8625 TCE(usat16, 6e00f30, f3a00000, 3, (RRnpc, I15, RRnpc), usat16, t_usat16),
8627 #undef ARM_VARIANT
8628 #define ARM_VARIANT ARM_EXT_V6K
8629 #undef THUMB_VARIANT
8630 #define THUMB_VARIANT ARM_EXT_V6K
8631 tCE(yield, 320f001, yield, 0, (), noargs, t_hint),
8632 tCE(wfe, 320f002, wfe, 0, (), noargs, t_hint),
8633 tCE(wfi, 320f003, wfi, 0, (), noargs, t_hint),
8634 tCE(sev, 320f004, sev, 0, (), noargs, t_hint),
8636 #undef THUMB_VARIANT
8637 #define THUMB_VARIANT ARM_EXT_V6T2
8638 TCE(ldrexb, 1d00f9f, e8d00f4f, 2, (RRnpc, RRnpcb), rd_rn, rd_rn),
8639 TCE(ldrexh, 1f00f9f, e8d00f5f, 2, (RRnpc, RRnpcb), rd_rn, rd_rn),
8640 TCE(ldrexd, 1b00f9f, e8d0007f, 3, (RRnpc, oRRnpc, RRnpcb), ldrexd, t_ldrexd),
8641 TCE(strexb, 1c00f90, e8c00f40, 3, (RRnpc, RRnpc, ADDR), strex, rm_rd_rn),
8642 TCE(strexh, 1e00f90, e8c00f50, 3, (RRnpc, RRnpc, ADDR), strex, rm_rd_rn),
8643 TCE(strexd, 1a00f90, e8c00070, 4, (RRnpc, RRnpc, oRRnpc, RRnpcb), strexd, t_strexd),
8644 TUF(clrex, 57ff01f, f3bf8f2f, 0, (), noargs, noargs),
8646 #undef ARM_VARIANT
8647 #define ARM_VARIANT ARM_EXT_V6Z
8648 TCE(smi, 1600070, f7f08000, 1, (EXPi), smi, t_smi),
8650 #undef ARM_VARIANT
8651 #define ARM_VARIANT ARM_EXT_V6T2
8652 TCE(bfc, 7c0001f, f36f0000, 3, (RRnpc, I31, I32), bfc, t_bfc),
8653 TCE(bfi, 7c00010, f3600000, 4, (RRnpc, RRnpc_I0, I31, I32), bfi, t_bfi),
8654 TCE(sbfx, 7a00050, f3400000, 4, (RR, RR, I31, I32), bfx, t_bfx),
8655 TCE(ubfx, 7e00050, f3c00000, 4, (RR, RR, I31, I32), bfx, t_bfx),
8657 TCE(mls, 0600090, fb000010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas, t_mla),
8658 TCE(movw, 3000000, f2400000, 2, (RRnpc, Iffff), mov16, t_mov16),
8659 TCE(movt, 3400000, f2c00000, 2, (RRnpc, Iffff), mov16, t_mov16),
8660 TCE(rbit, 3ff0f30, fa90f0a0, 2, (RR, RR), rd_rm, t_rbit),
8662 TC3(ldrht, 03000b0, f8300e00, 2, (RR, ADDR), ldsttv4, t_ldstt),
8663 TC3(ldrsht, 03000f0, f9300e00, 2, (RR, ADDR), ldsttv4, t_ldstt),
8664 TC3(ldrsbt, 03000d0, f9100e00, 2, (RR, ADDR), ldsttv4, t_ldstt),
8665 TC3(strht, 02000b0, f8200e00, 2, (RR, ADDR), ldsttv4, t_ldstt),
8667 UT(cbnz, b900, 2, (RR, EXP), t_czb),
8668 UT(cbz, b100, 2, (RR, EXP), t_czb),
8669 /* ARM does not really have an IT instruction. */
8670 TUE(it, 0, bf08, 1, (COND), it, t_it),
8671 TUE(itt, 0, bf0c, 1, (COND), it, t_it),
8672 TUE(ite, 0, bf04, 1, (COND), it, t_it),
8673 TUE(ittt, 0, bf0e, 1, (COND), it, t_it),
8674 TUE(itet, 0, bf06, 1, (COND), it, t_it),
8675 TUE(itte, 0, bf0a, 1, (COND), it, t_it),
8676 TUE(itee, 0, bf02, 1, (COND), it, t_it),
8677 TUE(itttt, 0, bf0f, 1, (COND), it, t_it),
8678 TUE(itett, 0, bf07, 1, (COND), it, t_it),
8679 TUE(ittet, 0, bf0b, 1, (COND), it, t_it),
8680 TUE(iteet, 0, bf03, 1, (COND), it, t_it),
8681 TUE(ittte, 0, bf0d, 1, (COND), it, t_it),
8682 TUE(itete, 0, bf05, 1, (COND), it, t_it),
8683 TUE(ittee, 0, bf09, 1, (COND), it, t_it),
8684 TUE(iteee, 0, bf01, 1, (COND), it, t_it),
8686 /* Thumb2 only instructions. */
8687 #undef ARM_VARIANT
8688 #define ARM_VARIANT 0
8690 TCE(addw, 0, f2000000, 3, (RR, RR, EXPi), 0, t_add_sub_w),
8691 TCE(subw, 0, f2a00000, 3, (RR, RR, EXPi), 0, t_add_sub_w),
8692 TCE(tbb, 0, e8d0f000, 1, (TB), 0, t_tb),
8693 TCE(tbh, 0, e8d0f010, 1, (TB), 0, t_tb),
8695 #undef ARM_VARIANT
8696 #define ARM_VARIANT FPU_FPA_EXT_V1 /* Core FPA instruction set (V1). */
8697 CE(wfs, e200110, 1, (RR), rd),
8698 CE(rfs, e300110, 1, (RR), rd),
8699 CE(wfc, e400110, 1, (RR), rd),
8700 CE(rfc, e500110, 1, (RR), rd),
8702 C3(ldfs, c100100, 2, (RF, ADDR), rd_cpaddr),
8703 C3(ldfd, c108100, 2, (RF, ADDR), rd_cpaddr),
8704 C3(ldfe, c500100, 2, (RF, ADDR), rd_cpaddr),
8705 C3(ldfp, c508100, 2, (RF, ADDR), rd_cpaddr),
8707 C3(stfs, c000100, 2, (RF, ADDR), rd_cpaddr),
8708 C3(stfd, c008100, 2, (RF, ADDR), rd_cpaddr),
8709 C3(stfe, c400100, 2, (RF, ADDR), rd_cpaddr),
8710 C3(stfp, c408100, 2, (RF, ADDR), rd_cpaddr),
8712 C3(mvfs, e008100, 2, (RF, RF_IF), rd_rm),
8713 C3(mvfsp, e008120, 2, (RF, RF_IF), rd_rm),
8714 C3(mvfsm, e008140, 2, (RF, RF_IF), rd_rm),
8715 C3(mvfsz, e008160, 2, (RF, RF_IF), rd_rm),
8716 C3(mvfd, e008180, 2, (RF, RF_IF), rd_rm),
8717 C3(mvfdp, e0081a0, 2, (RF, RF_IF), rd_rm),
8718 C3(mvfdm, e0081c0, 2, (RF, RF_IF), rd_rm),
8719 C3(mvfdz, e0081e0, 2, (RF, RF_IF), rd_rm),
8720 C3(mvfe, e088100, 2, (RF, RF_IF), rd_rm),
8721 C3(mvfep, e088120, 2, (RF, RF_IF), rd_rm),
8722 C3(mvfem, e088140, 2, (RF, RF_IF), rd_rm),
8723 C3(mvfez, e088160, 2, (RF, RF_IF), rd_rm),
8725 C3(mnfs, e108100, 2, (RF, RF_IF), rd_rm),
8726 C3(mnfsp, e108120, 2, (RF, RF_IF), rd_rm),
8727 C3(mnfsm, e108140, 2, (RF, RF_IF), rd_rm),
8728 C3(mnfsz, e108160, 2, (RF, RF_IF), rd_rm),
8729 C3(mnfd, e108180, 2, (RF, RF_IF), rd_rm),
8730 C3(mnfdp, e1081a0, 2, (RF, RF_IF), rd_rm),
8731 C3(mnfdm, e1081c0, 2, (RF, RF_IF), rd_rm),
8732 C3(mnfdz, e1081e0, 2, (RF, RF_IF), rd_rm),
8733 C3(mnfe, e188100, 2, (RF, RF_IF), rd_rm),
8734 C3(mnfep, e188120, 2, (RF, RF_IF), rd_rm),
8735 C3(mnfem, e188140, 2, (RF, RF_IF), rd_rm),
8736 C3(mnfez, e188160, 2, (RF, RF_IF), rd_rm),
8738 C3(abss, e208100, 2, (RF, RF_IF), rd_rm),
8739 C3(abssp, e208120, 2, (RF, RF_IF), rd_rm),
8740 C3(abssm, e208140, 2, (RF, RF_IF), rd_rm),
8741 C3(abssz, e208160, 2, (RF, RF_IF), rd_rm),
8742 C3(absd, e208180, 2, (RF, RF_IF), rd_rm),
8743 C3(absdp, e2081a0, 2, (RF, RF_IF), rd_rm),
8744 C3(absdm, e2081c0, 2, (RF, RF_IF), rd_rm),
8745 C3(absdz, e2081e0, 2, (RF, RF_IF), rd_rm),
8746 C3(abse, e288100, 2, (RF, RF_IF), rd_rm),
8747 C3(absep, e288120, 2, (RF, RF_IF), rd_rm),
8748 C3(absem, e288140, 2, (RF, RF_IF), rd_rm),
8749 C3(absez, e288160, 2, (RF, RF_IF), rd_rm),
8751 C3(rnds, e308100, 2, (RF, RF_IF), rd_rm),
8752 C3(rndsp, e308120, 2, (RF, RF_IF), rd_rm),
8753 C3(rndsm, e308140, 2, (RF, RF_IF), rd_rm),
8754 C3(rndsz, e308160, 2, (RF, RF_IF), rd_rm),
8755 C3(rndd, e308180, 2, (RF, RF_IF), rd_rm),
8756 C3(rnddp, e3081a0, 2, (RF, RF_IF), rd_rm),
8757 C3(rnddm, e3081c0, 2, (RF, RF_IF), rd_rm),
8758 C3(rnddz, e3081e0, 2, (RF, RF_IF), rd_rm),
8759 C3(rnde, e388100, 2, (RF, RF_IF), rd_rm),
8760 C3(rndep, e388120, 2, (RF, RF_IF), rd_rm),
8761 C3(rndem, e388140, 2, (RF, RF_IF), rd_rm),
8762 C3(rndez, e388160, 2, (RF, RF_IF), rd_rm),
8764 C3(sqts, e408100, 2, (RF, RF_IF), rd_rm),
8765 C3(sqtsp, e408120, 2, (RF, RF_IF), rd_rm),
8766 C3(sqtsm, e408140, 2, (RF, RF_IF), rd_rm),
8767 C3(sqtsz, e408160, 2, (RF, RF_IF), rd_rm),
8768 C3(sqtd, e408180, 2, (RF, RF_IF), rd_rm),
8769 C3(sqtdp, e4081a0, 2, (RF, RF_IF), rd_rm),
8770 C3(sqtdm, e4081c0, 2, (RF, RF_IF), rd_rm),
8771 C3(sqtdz, e4081e0, 2, (RF, RF_IF), rd_rm),
8772 C3(sqte, e488100, 2, (RF, RF_IF), rd_rm),
8773 C3(sqtep, e488120, 2, (RF, RF_IF), rd_rm),
8774 C3(sqtem, e488140, 2, (RF, RF_IF), rd_rm),
8775 C3(sqtez, e488160, 2, (RF, RF_IF), rd_rm),
8777 C3(logs, e508100, 2, (RF, RF_IF), rd_rm),
8778 C3(logsp, e508120, 2, (RF, RF_IF), rd_rm),
8779 C3(logsm, e508140, 2, (RF, RF_IF), rd_rm),
8780 C3(logsz, e508160, 2, (RF, RF_IF), rd_rm),
8781 C3(logd, e508180, 2, (RF, RF_IF), rd_rm),
8782 C3(logdp, e5081a0, 2, (RF, RF_IF), rd_rm),
8783 C3(logdm, e5081c0, 2, (RF, RF_IF), rd_rm),
8784 C3(logdz, e5081e0, 2, (RF, RF_IF), rd_rm),
8785 C3(loge, e588100, 2, (RF, RF_IF), rd_rm),
8786 C3(logep, e588120, 2, (RF, RF_IF), rd_rm),
8787 C3(logem, e588140, 2, (RF, RF_IF), rd_rm),
8788 C3(logez, e588160, 2, (RF, RF_IF), rd_rm),
8790 C3(lgns, e608100, 2, (RF, RF_IF), rd_rm),
8791 C3(lgnsp, e608120, 2, (RF, RF_IF), rd_rm),
8792 C3(lgnsm, e608140, 2, (RF, RF_IF), rd_rm),
8793 C3(lgnsz, e608160, 2, (RF, RF_IF), rd_rm),
8794 C3(lgnd, e608180, 2, (RF, RF_IF), rd_rm),
8795 C3(lgndp, e6081a0, 2, (RF, RF_IF), rd_rm),
8796 C3(lgndm, e6081c0, 2, (RF, RF_IF), rd_rm),
8797 C3(lgndz, e6081e0, 2, (RF, RF_IF), rd_rm),
8798 C3(lgne, e688100, 2, (RF, RF_IF), rd_rm),
8799 C3(lgnep, e688120, 2, (RF, RF_IF), rd_rm),
8800 C3(lgnem, e688140, 2, (RF, RF_IF), rd_rm),
8801 C3(lgnez, e688160, 2, (RF, RF_IF), rd_rm),
8803 C3(exps, e708100, 2, (RF, RF_IF), rd_rm),
8804 C3(expsp, e708120, 2, (RF, RF_IF), rd_rm),
8805 C3(expsm, e708140, 2, (RF, RF_IF), rd_rm),
8806 C3(expsz, e708160, 2, (RF, RF_IF), rd_rm),
8807 C3(expd, e708180, 2, (RF, RF_IF), rd_rm),
8808 C3(expdp, e7081a0, 2, (RF, RF_IF), rd_rm),
8809 C3(expdm, e7081c0, 2, (RF, RF_IF), rd_rm),
8810 C3(expdz, e7081e0, 2, (RF, RF_IF), rd_rm),
8811 C3(expe, e788100, 2, (RF, RF_IF), rd_rm),
8812 C3(expep, e788120, 2, (RF, RF_IF), rd_rm),
8813 C3(expem, e788140, 2, (RF, RF_IF), rd_rm),
8814 C3(expdz, e788160, 2, (RF, RF_IF), rd_rm),
8816 C3(sins, e808100, 2, (RF, RF_IF), rd_rm),
8817 C3(sinsp, e808120, 2, (RF, RF_IF), rd_rm),
8818 C3(sinsm, e808140, 2, (RF, RF_IF), rd_rm),
8819 C3(sinsz, e808160, 2, (RF, RF_IF), rd_rm),
8820 C3(sind, e808180, 2, (RF, RF_IF), rd_rm),
8821 C3(sindp, e8081a0, 2, (RF, RF_IF), rd_rm),
8822 C3(sindm, e8081c0, 2, (RF, RF_IF), rd_rm),
8823 C3(sindz, e8081e0, 2, (RF, RF_IF), rd_rm),
8824 C3(sine, e888100, 2, (RF, RF_IF), rd_rm),
8825 C3(sinep, e888120, 2, (RF, RF_IF), rd_rm),
8826 C3(sinem, e888140, 2, (RF, RF_IF), rd_rm),
8827 C3(sinez, e888160, 2, (RF, RF_IF), rd_rm),
8829 C3(coss, e908100, 2, (RF, RF_IF), rd_rm),
8830 C3(cossp, e908120, 2, (RF, RF_IF), rd_rm),
8831 C3(cossm, e908140, 2, (RF, RF_IF), rd_rm),
8832 C3(cossz, e908160, 2, (RF, RF_IF), rd_rm),
8833 C3(cosd, e908180, 2, (RF, RF_IF), rd_rm),
8834 C3(cosdp, e9081a0, 2, (RF, RF_IF), rd_rm),
8835 C3(cosdm, e9081c0, 2, (RF, RF_IF), rd_rm),
8836 C3(cosdz, e9081e0, 2, (RF, RF_IF), rd_rm),
8837 C3(cose, e988100, 2, (RF, RF_IF), rd_rm),
8838 C3(cosep, e988120, 2, (RF, RF_IF), rd_rm),
8839 C3(cosem, e988140, 2, (RF, RF_IF), rd_rm),
8840 C3(cosez, e988160, 2, (RF, RF_IF), rd_rm),
8842 C3(tans, ea08100, 2, (RF, RF_IF), rd_rm),
8843 C3(tansp, ea08120, 2, (RF, RF_IF), rd_rm),
8844 C3(tansm, ea08140, 2, (RF, RF_IF), rd_rm),
8845 C3(tansz, ea08160, 2, (RF, RF_IF), rd_rm),
8846 C3(tand, ea08180, 2, (RF, RF_IF), rd_rm),
8847 C3(tandp, ea081a0, 2, (RF, RF_IF), rd_rm),
8848 C3(tandm, ea081c0, 2, (RF, RF_IF), rd_rm),
8849 C3(tandz, ea081e0, 2, (RF, RF_IF), rd_rm),
8850 C3(tane, ea88100, 2, (RF, RF_IF), rd_rm),
8851 C3(tanep, ea88120, 2, (RF, RF_IF), rd_rm),
8852 C3(tanem, ea88140, 2, (RF, RF_IF), rd_rm),
8853 C3(tanez, ea88160, 2, (RF, RF_IF), rd_rm),
8855 C3(asns, eb08100, 2, (RF, RF_IF), rd_rm),
8856 C3(asnsp, eb08120, 2, (RF, RF_IF), rd_rm),
8857 C3(asnsm, eb08140, 2, (RF, RF_IF), rd_rm),
8858 C3(asnsz, eb08160, 2, (RF, RF_IF), rd_rm),
8859 C3(asnd, eb08180, 2, (RF, RF_IF), rd_rm),
8860 C3(asndp, eb081a0, 2, (RF, RF_IF), rd_rm),
8861 C3(asndm, eb081c0, 2, (RF, RF_IF), rd_rm),
8862 C3(asndz, eb081e0, 2, (RF, RF_IF), rd_rm),
8863 C3(asne, eb88100, 2, (RF, RF_IF), rd_rm),
8864 C3(asnep, eb88120, 2, (RF, RF_IF), rd_rm),
8865 C3(asnem, eb88140, 2, (RF, RF_IF), rd_rm),
8866 C3(asnez, eb88160, 2, (RF, RF_IF), rd_rm),
8868 C3(acss, ec08100, 2, (RF, RF_IF), rd_rm),
8869 C3(acssp, ec08120, 2, (RF, RF_IF), rd_rm),
8870 C3(acssm, ec08140, 2, (RF, RF_IF), rd_rm),
8871 C3(acssz, ec08160, 2, (RF, RF_IF), rd_rm),
8872 C3(acsd, ec08180, 2, (RF, RF_IF), rd_rm),
8873 C3(acsdp, ec081a0, 2, (RF, RF_IF), rd_rm),
8874 C3(acsdm, ec081c0, 2, (RF, RF_IF), rd_rm),
8875 C3(acsdz, ec081e0, 2, (RF, RF_IF), rd_rm),
8876 C3(acse, ec88100, 2, (RF, RF_IF), rd_rm),
8877 C3(acsep, ec88120, 2, (RF, RF_IF), rd_rm),
8878 C3(acsem, ec88140, 2, (RF, RF_IF), rd_rm),
8879 C3(acsez, ec88160, 2, (RF, RF_IF), rd_rm),
8881 C3(atns, ed08100, 2, (RF, RF_IF), rd_rm),
8882 C3(atnsp, ed08120, 2, (RF, RF_IF), rd_rm),
8883 C3(atnsm, ed08140, 2, (RF, RF_IF), rd_rm),
8884 C3(atnsz, ed08160, 2, (RF, RF_IF), rd_rm),
8885 C3(atnd, ed08180, 2, (RF, RF_IF), rd_rm),
8886 C3(atndp, ed081a0, 2, (RF, RF_IF), rd_rm),
8887 C3(atndm, ed081c0, 2, (RF, RF_IF), rd_rm),
8888 C3(atndz, ed081e0, 2, (RF, RF_IF), rd_rm),
8889 C3(atne, ed88100, 2, (RF, RF_IF), rd_rm),
8890 C3(atnep, ed88120, 2, (RF, RF_IF), rd_rm),
8891 C3(atnem, ed88140, 2, (RF, RF_IF), rd_rm),
8892 C3(atnez, ed88160, 2, (RF, RF_IF), rd_rm),
8894 C3(urds, ee08100, 2, (RF, RF_IF), rd_rm),
8895 C3(urdsp, ee08120, 2, (RF, RF_IF), rd_rm),
8896 C3(urdsm, ee08140, 2, (RF, RF_IF), rd_rm),
8897 C3(urdsz, ee08160, 2, (RF, RF_IF), rd_rm),
8898 C3(urdd, ee08180, 2, (RF, RF_IF), rd_rm),
8899 C3(urddp, ee081a0, 2, (RF, RF_IF), rd_rm),
8900 C3(urddm, ee081c0, 2, (RF, RF_IF), rd_rm),
8901 C3(urddz, ee081e0, 2, (RF, RF_IF), rd_rm),
8902 C3(urde, ee88100, 2, (RF, RF_IF), rd_rm),
8903 C3(urdep, ee88120, 2, (RF, RF_IF), rd_rm),
8904 C3(urdem, ee88140, 2, (RF, RF_IF), rd_rm),
8905 C3(urdez, ee88160, 2, (RF, RF_IF), rd_rm),
8907 C3(nrms, ef08100, 2, (RF, RF_IF), rd_rm),
8908 C3(nrmsp, ef08120, 2, (RF, RF_IF), rd_rm),
8909 C3(nrmsm, ef08140, 2, (RF, RF_IF), rd_rm),
8910 C3(nrmsz, ef08160, 2, (RF, RF_IF), rd_rm),
8911 C3(nrmd, ef08180, 2, (RF, RF_IF), rd_rm),
8912 C3(nrmdp, ef081a0, 2, (RF, RF_IF), rd_rm),
8913 C3(nrmdm, ef081c0, 2, (RF, RF_IF), rd_rm),
8914 C3(nrmdz, ef081e0, 2, (RF, RF_IF), rd_rm),
8915 C3(nrme, ef88100, 2, (RF, RF_IF), rd_rm),
8916 C3(nrmep, ef88120, 2, (RF, RF_IF), rd_rm),
8917 C3(nrmem, ef88140, 2, (RF, RF_IF), rd_rm),
8918 C3(nrmez, ef88160, 2, (RF, RF_IF), rd_rm),
8920 C3(adfs, e000100, 3, (RF, RF, RF_IF), rd_rn_rm),
8921 C3(adfsp, e000120, 3, (RF, RF, RF_IF), rd_rn_rm),
8922 C3(adfsm, e000140, 3, (RF, RF, RF_IF), rd_rn_rm),
8923 C3(adfsz, e000160, 3, (RF, RF, RF_IF), rd_rn_rm),
8924 C3(adfd, e000180, 3, (RF, RF, RF_IF), rd_rn_rm),
8925 C3(adfdp, e0001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
8926 C3(adfdm, e0001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
8927 C3(adfdz, e0001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
8928 C3(adfe, e080100, 3, (RF, RF, RF_IF), rd_rn_rm),
8929 C3(adfep, e080120, 3, (RF, RF, RF_IF), rd_rn_rm),
8930 C3(adfem, e080140, 3, (RF, RF, RF_IF), rd_rn_rm),
8931 C3(adfez, e080160, 3, (RF, RF, RF_IF), rd_rn_rm),
8933 C3(sufs, e200100, 3, (RF, RF, RF_IF), rd_rn_rm),
8934 C3(sufsp, e200120, 3, (RF, RF, RF_IF), rd_rn_rm),
8935 C3(sufsm, e200140, 3, (RF, RF, RF_IF), rd_rn_rm),
8936 C3(sufsz, e200160, 3, (RF, RF, RF_IF), rd_rn_rm),
8937 C3(sufd, e200180, 3, (RF, RF, RF_IF), rd_rn_rm),
8938 C3(sufdp, e2001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
8939 C3(sufdm, e2001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
8940 C3(sufdz, e2001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
8941 C3(sufe, e280100, 3, (RF, RF, RF_IF), rd_rn_rm),
8942 C3(sufep, e280120, 3, (RF, RF, RF_IF), rd_rn_rm),
8943 C3(sufem, e280140, 3, (RF, RF, RF_IF), rd_rn_rm),
8944 C3(sufez, e280160, 3, (RF, RF, RF_IF), rd_rn_rm),
8946 C3(rsfs, e300100, 3, (RF, RF, RF_IF), rd_rn_rm),
8947 C3(rsfsp, e300120, 3, (RF, RF, RF_IF), rd_rn_rm),
8948 C3(rsfsm, e300140, 3, (RF, RF, RF_IF), rd_rn_rm),
8949 C3(rsfsz, e300160, 3, (RF, RF, RF_IF), rd_rn_rm),
8950 C3(rsfd, e300180, 3, (RF, RF, RF_IF), rd_rn_rm),
8951 C3(rsfdp, e3001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
8952 C3(rsfdm, e3001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
8953 C3(rsfdz, e3001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
8954 C3(rsfe, e380100, 3, (RF, RF, RF_IF), rd_rn_rm),
8955 C3(rsfep, e380120, 3, (RF, RF, RF_IF), rd_rn_rm),
8956 C3(rsfem, e380140, 3, (RF, RF, RF_IF), rd_rn_rm),
8957 C3(rsfez, e380160, 3, (RF, RF, RF_IF), rd_rn_rm),
8959 C3(mufs, e100100, 3, (RF, RF, RF_IF), rd_rn_rm),
8960 C3(mufsp, e100120, 3, (RF, RF, RF_IF), rd_rn_rm),
8961 C3(mufsm, e100140, 3, (RF, RF, RF_IF), rd_rn_rm),
8962 C3(mufsz, e100160, 3, (RF, RF, RF_IF), rd_rn_rm),
8963 C3(mufd, e100180, 3, (RF, RF, RF_IF), rd_rn_rm),
8964 C3(mufdp, e1001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
8965 C3(mufdm, e1001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
8966 C3(mufdz, e1001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
8967 C3(mufe, e180100, 3, (RF, RF, RF_IF), rd_rn_rm),
8968 C3(mufep, e180120, 3, (RF, RF, RF_IF), rd_rn_rm),
8969 C3(mufem, e180140, 3, (RF, RF, RF_IF), rd_rn_rm),
8970 C3(mufez, e180160, 3, (RF, RF, RF_IF), rd_rn_rm),
8972 C3(dvfs, e400100, 3, (RF, RF, RF_IF), rd_rn_rm),
8973 C3(dvfsp, e400120, 3, (RF, RF, RF_IF), rd_rn_rm),
8974 C3(dvfsm, e400140, 3, (RF, RF, RF_IF), rd_rn_rm),
8975 C3(dvfsz, e400160, 3, (RF, RF, RF_IF), rd_rn_rm),
8976 C3(dvfd, e400180, 3, (RF, RF, RF_IF), rd_rn_rm),
8977 C3(dvfdp, e4001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
8978 C3(dvfdm, e4001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
8979 C3(dvfdz, e4001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
8980 C3(dvfe, e480100, 3, (RF, RF, RF_IF), rd_rn_rm),
8981 C3(dvfep, e480120, 3, (RF, RF, RF_IF), rd_rn_rm),
8982 C3(dvfem, e480140, 3, (RF, RF, RF_IF), rd_rn_rm),
8983 C3(dvfez, e480160, 3, (RF, RF, RF_IF), rd_rn_rm),
8985 C3(rdfs, e500100, 3, (RF, RF, RF_IF), rd_rn_rm),
8986 C3(rdfsp, e500120, 3, (RF, RF, RF_IF), rd_rn_rm),
8987 C3(rdfsm, e500140, 3, (RF, RF, RF_IF), rd_rn_rm),
8988 C3(rdfsz, e500160, 3, (RF, RF, RF_IF), rd_rn_rm),
8989 C3(rdfd, e500180, 3, (RF, RF, RF_IF), rd_rn_rm),
8990 C3(rdfdp, e5001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
8991 C3(rdfdm, e5001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
8992 C3(rdfdz, e5001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
8993 C3(rdfe, e580100, 3, (RF, RF, RF_IF), rd_rn_rm),
8994 C3(rdfep, e580120, 3, (RF, RF, RF_IF), rd_rn_rm),
8995 C3(rdfem, e580140, 3, (RF, RF, RF_IF), rd_rn_rm),
8996 C3(rdfez, e580160, 3, (RF, RF, RF_IF), rd_rn_rm),
8998 C3(pows, e600100, 3, (RF, RF, RF_IF), rd_rn_rm),
8999 C3(powsp, e600120, 3, (RF, RF, RF_IF), rd_rn_rm),
9000 C3(powsm, e600140, 3, (RF, RF, RF_IF), rd_rn_rm),
9001 C3(powsz, e600160, 3, (RF, RF, RF_IF), rd_rn_rm),
9002 C3(powd, e600180, 3, (RF, RF, RF_IF), rd_rn_rm),
9003 C3(powdp, e6001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
9004 C3(powdm, e6001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
9005 C3(powdz, e6001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
9006 C3(powe, e680100, 3, (RF, RF, RF_IF), rd_rn_rm),
9007 C3(powep, e680120, 3, (RF, RF, RF_IF), rd_rn_rm),
9008 C3(powem, e680140, 3, (RF, RF, RF_IF), rd_rn_rm),
9009 C3(powez, e680160, 3, (RF, RF, RF_IF), rd_rn_rm),
9011 C3(rpws, e700100, 3, (RF, RF, RF_IF), rd_rn_rm),
9012 C3(rpwsp, e700120, 3, (RF, RF, RF_IF), rd_rn_rm),
9013 C3(rpwsm, e700140, 3, (RF, RF, RF_IF), rd_rn_rm),
9014 C3(rpwsz, e700160, 3, (RF, RF, RF_IF), rd_rn_rm),
9015 C3(rpwd, e700180, 3, (RF, RF, RF_IF), rd_rn_rm),
9016 C3(rpwdp, e7001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
9017 C3(rpwdm, e7001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
9018 C3(rpwdz, e7001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
9019 C3(rpwe, e780100, 3, (RF, RF, RF_IF), rd_rn_rm),
9020 C3(rpwep, e780120, 3, (RF, RF, RF_IF), rd_rn_rm),
9021 C3(rpwem, e780140, 3, (RF, RF, RF_IF), rd_rn_rm),
9022 C3(rpwez, e780160, 3, (RF, RF, RF_IF), rd_rn_rm),
9024 C3(rmfs, e800100, 3, (RF, RF, RF_IF), rd_rn_rm),
9025 C3(rmfsp, e800120, 3, (RF, RF, RF_IF), rd_rn_rm),
9026 C3(rmfsm, e800140, 3, (RF, RF, RF_IF), rd_rn_rm),
9027 C3(rmfsz, e800160, 3, (RF, RF, RF_IF), rd_rn_rm),
9028 C3(rmfd, e800180, 3, (RF, RF, RF_IF), rd_rn_rm),
9029 C3(rmfdp, e8001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
9030 C3(rmfdm, e8001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
9031 C3(rmfdz, e8001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
9032 C3(rmfe, e880100, 3, (RF, RF, RF_IF), rd_rn_rm),
9033 C3(rmfep, e880120, 3, (RF, RF, RF_IF), rd_rn_rm),
9034 C3(rmfem, e880140, 3, (RF, RF, RF_IF), rd_rn_rm),
9035 C3(rmfez, e880160, 3, (RF, RF, RF_IF), rd_rn_rm),
9037 C3(fmls, e900100, 3, (RF, RF, RF_IF), rd_rn_rm),
9038 C3(fmlsp, e900120, 3, (RF, RF, RF_IF), rd_rn_rm),
9039 C3(fmlsm, e900140, 3, (RF, RF, RF_IF), rd_rn_rm),
9040 C3(fmlsz, e900160, 3, (RF, RF, RF_IF), rd_rn_rm),
9041 C3(fmld, e900180, 3, (RF, RF, RF_IF), rd_rn_rm),
9042 C3(fmldp, e9001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
9043 C3(fmldm, e9001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
9044 C3(fmldz, e9001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
9045 C3(fmle, e980100, 3, (RF, RF, RF_IF), rd_rn_rm),
9046 C3(fmlep, e980120, 3, (RF, RF, RF_IF), rd_rn_rm),
9047 C3(fmlem, e980140, 3, (RF, RF, RF_IF), rd_rn_rm),
9048 C3(fmlez, e980160, 3, (RF, RF, RF_IF), rd_rn_rm),
9050 C3(fdvs, ea00100, 3, (RF, RF, RF_IF), rd_rn_rm),
9051 C3(fdvsp, ea00120, 3, (RF, RF, RF_IF), rd_rn_rm),
9052 C3(fdvsm, ea00140, 3, (RF, RF, RF_IF), rd_rn_rm),
9053 C3(fdvsz, ea00160, 3, (RF, RF, RF_IF), rd_rn_rm),
9054 C3(fdvd, ea00180, 3, (RF, RF, RF_IF), rd_rn_rm),
9055 C3(fdvdp, ea001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
9056 C3(fdvdm, ea001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
9057 C3(fdvdz, ea001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
9058 C3(fdve, ea80100, 3, (RF, RF, RF_IF), rd_rn_rm),
9059 C3(fdvep, ea80120, 3, (RF, RF, RF_IF), rd_rn_rm),
9060 C3(fdvem, ea80140, 3, (RF, RF, RF_IF), rd_rn_rm),
9061 C3(fdvez, ea80160, 3, (RF, RF, RF_IF), rd_rn_rm),
9063 C3(frds, eb00100, 3, (RF, RF, RF_IF), rd_rn_rm),
9064 C3(frdsp, eb00120, 3, (RF, RF, RF_IF), rd_rn_rm),
9065 C3(frdsm, eb00140, 3, (RF, RF, RF_IF), rd_rn_rm),
9066 C3(frdsz, eb00160, 3, (RF, RF, RF_IF), rd_rn_rm),
9067 C3(frdd, eb00180, 3, (RF, RF, RF_IF), rd_rn_rm),
9068 C3(frddp, eb001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
9069 C3(frddm, eb001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
9070 C3(frddz, eb001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
9071 C3(frde, eb80100, 3, (RF, RF, RF_IF), rd_rn_rm),
9072 C3(frdep, eb80120, 3, (RF, RF, RF_IF), rd_rn_rm),
9073 C3(frdem, eb80140, 3, (RF, RF, RF_IF), rd_rn_rm),
9074 C3(frdez, eb80160, 3, (RF, RF, RF_IF), rd_rn_rm),
9076 C3(pols, ec00100, 3, (RF, RF, RF_IF), rd_rn_rm),
9077 C3(polsp, ec00120, 3, (RF, RF, RF_IF), rd_rn_rm),
9078 C3(polsm, ec00140, 3, (RF, RF, RF_IF), rd_rn_rm),
9079 C3(polsz, ec00160, 3, (RF, RF, RF_IF), rd_rn_rm),
9080 C3(pold, ec00180, 3, (RF, RF, RF_IF), rd_rn_rm),
9081 C3(poldp, ec001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
9082 C3(poldm, ec001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
9083 C3(poldz, ec001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
9084 C3(pole, ec80100, 3, (RF, RF, RF_IF), rd_rn_rm),
9085 C3(polep, ec80120, 3, (RF, RF, RF_IF), rd_rn_rm),
9086 C3(polem, ec80140, 3, (RF, RF, RF_IF), rd_rn_rm),
9087 C3(polez, ec80160, 3, (RF, RF, RF_IF), rd_rn_rm),
9089 CE(cmf, e90f110, 2, (RF, RF_IF), fpa_cmp),
9090 C3E(cmfe, ed0f110, 2, (RF, RF_IF), fpa_cmp),
9091 CE(cnf, eb0f110, 2, (RF, RF_IF), fpa_cmp),
9092 C3E(cnfe, ef0f110, 2, (RF, RF_IF), fpa_cmp),
9094 C3(flts, e000110, 2, (RF, RR), rn_rd),
9095 C3(fltsp, e000130, 2, (RF, RR), rn_rd),
9096 C3(fltsm, e000150, 2, (RF, RR), rn_rd),
9097 C3(fltsz, e000170, 2, (RF, RR), rn_rd),
9098 C3(fltd, e000190, 2, (RF, RR), rn_rd),
9099 C3(fltdp, e0001b0, 2, (RF, RR), rn_rd),
9100 C3(fltdm, e0001d0, 2, (RF, RR), rn_rd),
9101 C3(fltdz, e0001f0, 2, (RF, RR), rn_rd),
9102 C3(flte, e080110, 2, (RF, RR), rn_rd),
9103 C3(fltep, e080130, 2, (RF, RR), rn_rd),
9104 C3(fltem, e080150, 2, (RF, RR), rn_rd),
9105 C3(fltez, e080170, 2, (RF, RR), rn_rd),
9107 /* The implementation of the FIX instruction is broken on some
9108 assemblers, in that it accepts a precision specifier as well as a
9109 rounding specifier, despite the fact that this is meaningless.
9110 To be more compatible, we accept it as well, though of course it
9111 does not set any bits. */
9112 CE(fix, e100110, 2, (RR, RF), rd_rm),
9113 C3(fixp, e100130, 2, (RR, RF), rd_rm),
9114 C3(fixm, e100150, 2, (RR, RF), rd_rm),
9115 C3(fixz, e100170, 2, (RR, RF), rd_rm),
9116 C3(fixsp, e100130, 2, (RR, RF), rd_rm),
9117 C3(fixsm, e100150, 2, (RR, RF), rd_rm),
9118 C3(fixsz, e100170, 2, (RR, RF), rd_rm),
9119 C3(fixdp, e100130, 2, (RR, RF), rd_rm),
9120 C3(fixdm, e100150, 2, (RR, RF), rd_rm),
9121 C3(fixdz, e100170, 2, (RR, RF), rd_rm),
9122 C3(fixep, e100130, 2, (RR, RF), rd_rm),
9123 C3(fixem, e100150, 2, (RR, RF), rd_rm),
9124 C3(fixez, e100170, 2, (RR, RF), rd_rm),
9126 /* Instructions that were new with the real FPA, call them V2. */
9127 #undef ARM_VARIANT
9128 #define ARM_VARIANT FPU_FPA_EXT_V2
9129 CE(lfm, c100200, 3, (RF, I4b, ADDR), fpa_ldmstm),
9130 C3(lfmfd, c900200, 3, (RF, I4b, ADDR), fpa_ldmstm),
9131 C3(lfmea, d100200, 3, (RF, I4b, ADDR), fpa_ldmstm),
9132 CE(sfm, c000200, 3, (RF, I4b, ADDR), fpa_ldmstm),
9133 C3(sfmfd, d000200, 3, (RF, I4b, ADDR), fpa_ldmstm),
9134 C3(sfmea, c800200, 3, (RF, I4b, ADDR), fpa_ldmstm),
9136 #undef ARM_VARIANT
9137 #define ARM_VARIANT FPU_VFP_EXT_V1xD /* VFP V1xD (single precision). */
9138 /* Moves and type conversions. */
9139 CE(fcpys, eb00a40, 2, (RVS, RVS), vfp_sp_monadic),
9140 CE(fmrs, e100a10, 2, (RR, RVS), vfp_reg_from_sp),
9141 CE(fmsr, e000a10, 2, (RVS, RR), vfp_sp_from_reg),
9142 CE(fmstat, ef1fa10, 0, (), noargs),
9143 CE(fsitos, eb80ac0, 2, (RVS, RVS), vfp_sp_monadic),
9144 CE(fuitos, eb80a40, 2, (RVS, RVS), vfp_sp_monadic),
9145 CE(ftosis, ebd0a40, 2, (RVS, RVS), vfp_sp_monadic),
9146 CE(ftosizs, ebd0ac0, 2, (RVS, RVS), vfp_sp_monadic),
9147 CE(ftouis, ebc0a40, 2, (RVS, RVS), vfp_sp_monadic),
9148 CE(ftouizs, ebc0ac0, 2, (RVS, RVS), vfp_sp_monadic),
9149 CE(fmrx, ef00a10, 2, (RR, RVC), rd_rn),
9150 CE(fmxr, ee00a10, 2, (RVC, RR), rn_rd),
9152 /* Memory operations. */
9153 CE(flds, d100a00, 2, (RVS, ADDR), vfp_sp_ldst),
9154 CE(fsts, d000a00, 2, (RVS, ADDR), vfp_sp_ldst),
9155 CE(fldmias, c900a00, 2, (RRw, VRSLST), vfp_sp_ldstmia),
9156 CE(fldmfds, c900a00, 2, (RRw, VRSLST), vfp_sp_ldstmia),
9157 CE(fldmdbs, d300a00, 2, (RRw, VRSLST), vfp_sp_ldstmdb),
9158 CE(fldmeas, d300a00, 2, (RRw, VRSLST), vfp_sp_ldstmdb),
9159 CE(fldmiax, c900b00, 2, (RRw, VRDLST), vfp_xp_ldstmia),
9160 CE(fldmfdx, c900b00, 2, (RRw, VRDLST), vfp_xp_ldstmia),
9161 CE(fldmdbx, d300b00, 2, (RRw, VRDLST), vfp_xp_ldstmdb),
9162 CE(fldmeax, d300b00, 2, (RRw, VRDLST), vfp_xp_ldstmdb),
9163 CE(fstmias, c800a00, 2, (RRw, VRSLST), vfp_sp_ldstmia),
9164 CE(fstmeas, c800a00, 2, (RRw, VRSLST), vfp_sp_ldstmia),
9165 CE(fstmdbs, d200a00, 2, (RRw, VRSLST), vfp_sp_ldstmdb),
9166 CE(fstmfds, d200a00, 2, (RRw, VRSLST), vfp_sp_ldstmdb),
9167 CE(fstmiax, c800b00, 2, (RRw, VRDLST), vfp_xp_ldstmia),
9168 CE(fstmeax, c800b00, 2, (RRw, VRDLST), vfp_xp_ldstmia),
9169 CE(fstmdbx, d200b00, 2, (RRw, VRDLST), vfp_xp_ldstmdb),
9170 CE(fstmfdx, d200b00, 2, (RRw, VRDLST), vfp_xp_ldstmdb),
9172 /* Monadic operations. */
9173 CE(fabss, eb00ac0, 2, (RVS, RVS), vfp_sp_monadic),
9174 CE(fnegs, eb10a40, 2, (RVS, RVS), vfp_sp_monadic),
9175 CE(fsqrts, eb10ac0, 2, (RVS, RVS), vfp_sp_monadic),
9177 /* Dyadic operations. */
9178 CE(fadds, e300a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
9179 CE(fsubs, e300a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
9180 CE(fmuls, e200a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
9181 CE(fdivs, e800a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
9182 CE(fmacs, e000a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
9183 CE(fmscs, e100a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
9184 CE(fnmuls, e200a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
9185 CE(fnmacs, e000a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
9186 CE(fnmscs, e100a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
9188 /* Comparisons. */
9189 CE(fcmps, eb40a40, 2, (RVS, RVS), vfp_sp_monadic),
9190 CE(fcmpzs, eb50a40, 1, (RVS), vfp_sp_compare_z),
9191 CE(fcmpes, eb40ac0, 2, (RVS, RVS), vfp_sp_monadic),
9192 CE(fcmpezs, eb50ac0, 1, (RVS), vfp_sp_compare_z),
9194 #undef ARM_VARIANT
9195 #define ARM_VARIANT FPU_VFP_EXT_V1 /* VFP V1 (Double precision). */
9196 /* Moves and type conversions. */
9197 CE(fcpyd, eb00b40, 2, (RVD, RVD), rd_rm),
9198 CE(fcvtds, eb70ac0, 2, (RVD, RVS), vfp_dp_sp_cvt),
9199 CE(fcvtsd, eb70bc0, 2, (RVS, RVD), vfp_sp_dp_cvt),
9200 CE(fmdhr, e200b10, 2, (RVD, RR), rn_rd),
9201 CE(fmdlr, e000b10, 2, (RVD, RR), rn_rd),
9202 CE(fmrdh, e300b10, 2, (RR, RVD), rd_rn),
9203 CE(fmrdl, e100b10, 2, (RR, RVD), rd_rn),
9204 CE(fsitod, eb80bc0, 2, (RVD, RVS), vfp_dp_sp_cvt),
9205 CE(fuitod, eb80b40, 2, (RVD, RVS), vfp_dp_sp_cvt),
9206 CE(ftosid, ebd0b40, 2, (RVS, RVD), vfp_sp_dp_cvt),
9207 CE(ftosizd, ebd0bc0, 2, (RVS, RVD), vfp_sp_dp_cvt),
9208 CE(ftouid, ebc0b40, 2, (RVS, RVD), vfp_sp_dp_cvt),
9209 CE(ftouizd, ebc0bc0, 2, (RVS, RVD), vfp_sp_dp_cvt),
9211 /* Memory operations. */
9212 CE(fldd, d100b00, 2, (RVD, ADDR), vfp_dp_ldst),
9213 CE(fstd, d000b00, 2, (RVD, ADDR), vfp_dp_ldst),
9214 CE(fldmiad, c900b00, 2, (RRw, VRDLST), vfp_dp_ldstmia),
9215 CE(fldmfdd, c900b00, 2, (RRw, VRDLST), vfp_dp_ldstmia),
9216 CE(fldmdbd, d300b00, 2, (RRw, VRDLST), vfp_dp_ldstmdb),
9217 CE(fldmead, d300b00, 2, (RRw, VRDLST), vfp_dp_ldstmdb),
9218 CE(fstmiad, c800b00, 2, (RRw, VRDLST), vfp_dp_ldstmia),
9219 CE(fstmead, c800b00, 2, (RRw, VRDLST), vfp_dp_ldstmia),
9220 CE(fstmdbd, d200b00, 2, (RRw, VRDLST), vfp_dp_ldstmdb),
9221 CE(fstmfdd, d200b00, 2, (RRw, VRDLST), vfp_dp_ldstmdb),
9223 /* Monadic operations. */
9224 CE(fabsd, eb00bc0, 2, (RVD, RVD), rd_rm),
9225 CE(fnegd, eb10b40, 2, (RVD, RVD), rd_rm),
9226 CE(fsqrtd, eb10bc0, 2, (RVD, RVD), rd_rm),
9228 /* Dyadic operations. */
9229 CE(faddd, e300b00, 3, (RVD, RVD, RVD), rd_rn_rm),
9230 CE(fsubd, e300b40, 3, (RVD, RVD, RVD), rd_rn_rm),
9231 CE(fmuld, e200b00, 3, (RVD, RVD, RVD), rd_rn_rm),
9232 CE(fdivd, e800b00, 3, (RVD, RVD, RVD), rd_rn_rm),
9233 CE(fmacd, e000b00, 3, (RVD, RVD, RVD), rd_rn_rm),
9234 CE(fmscd, e100b00, 3, (RVD, RVD, RVD), rd_rn_rm),
9235 CE(fnmuld, e200b40, 3, (RVD, RVD, RVD), rd_rn_rm),
9236 CE(fnmacd, e000b40, 3, (RVD, RVD, RVD), rd_rn_rm),
9237 CE(fnmscd, e100b40, 3, (RVD, RVD, RVD), rd_rn_rm),
9239 /* Comparisons. */
9240 CE(fcmpd, eb40b40, 2, (RVD, RVD), rd_rm),
9241 CE(fcmpzd, eb50b40, 1, (RVD), rd),
9242 CE(fcmped, eb40bc0, 2, (RVD, RVD), rd_rm),
9243 CE(fcmpezd, eb50bc0, 1, (RVD), rd),
9245 #undef ARM_VARIANT
9246 #define ARM_VARIANT FPU_VFP_EXT_V2
9247 CE(fmsrr, c400a10, 3, (VRSLST, RR, RR), vfp_sp2_from_reg2),
9248 CE(fmrrs, c500a10, 3, (RR, RR, VRSLST), vfp_reg2_from_sp2),
9249 CE(fmdrr, c400b10, 3, (RVD, RR, RR), rm_rd_rn),
9250 CE(fmrrd, c500b10, 3, (RR, RR, RVD), rd_rn_rm),
9252 #undef ARM_VARIANT
9253 #define ARM_VARIANT ARM_CEXT_XSCALE /* Intel XScale extensions. */
9254 CE(mia, e200010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
9255 CE(miaph, e280010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
9256 CE(miabb, e2c0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
9257 CE(miabt, e2d0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
9258 CE(miatb, e2e0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
9259 CE(miatt, e2f0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
9260 CE(mar, c400000, 3, (RXA, RRnpc, RRnpc), xsc_mar),
9261 CE(mra, c500000, 3, (RRnpc, RRnpc, RXA), xsc_mra),
9263 #undef ARM_VARIANT
9264 #define ARM_VARIANT ARM_CEXT_IWMMXT /* Intel Wireless MMX technology. */
9265 CE(tandcb, e13f130, 1, (RR), iwmmxt_tandorc),
9266 CE(tandch, e53f130, 1, (RR), iwmmxt_tandorc),
9267 CE(tandcw, e93f130, 1, (RR), iwmmxt_tandorc),
9268 CE(tbcstb, e400010, 2, (RIWR, RR), rn_rd),
9269 CE(tbcsth, e400050, 2, (RIWR, RR), rn_rd),
9270 CE(tbcstw, e400090, 2, (RIWR, RR), rn_rd),
9271 CE(textrcb, e130170, 2, (RR, I7), iwmmxt_textrc),
9272 CE(textrch, e530170, 2, (RR, I7), iwmmxt_textrc),
9273 CE(textrcw, e930170, 2, (RR, I7), iwmmxt_textrc),
9274 CE(textrmub, e100070, 3, (RR, RIWR, I7), iwmmxt_textrm),
9275 CE(textrmuh, e500070, 3, (RR, RIWR, I7), iwmmxt_textrm),
9276 CE(textrmuw, e900070, 3, (RR, RIWR, I7), iwmmxt_textrm),
9277 CE(textrmsb, e100078, 3, (RR, RIWR, I7), iwmmxt_textrm),
9278 CE(textrmsh, e500078, 3, (RR, RIWR, I7), iwmmxt_textrm),
9279 CE(textrmsw, e900078, 3, (RR, RIWR, I7), iwmmxt_textrm),
9280 CE(tinsrb, e600010, 3, (RIWR, RR, I7), iwmmxt_tinsr),
9281 CE(tinsrh, e600050, 3, (RIWR, RR, I7), iwmmxt_tinsr),
9282 CE(tinsrw, e600090, 3, (RIWR, RR, I7), iwmmxt_tinsr),
9283 CE(tmcr, e000110, 2, (RIWC, RR), rn_rd),
9284 CE(tmcrr, c400000, 3, (RIWR, RR, RR), rm_rd_rn),
9285 CE(tmia, e200010, 3, (RIWR, RR, RR), iwmmxt_tmia),
9286 CE(tmiaph, e280010, 3, (RIWR, RR, RR), iwmmxt_tmia),
9287 CE(tmiabb, e2c0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
9288 CE(tmiabt, e2d0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
9289 CE(tmiatb, e2e0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
9290 CE(tmiatt, e2f0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
9291 CE(tmovmskb, e100030, 2, (RR, RIWR), rd_rn),
9292 CE(tmovmskh, e500030, 2, (RR, RIWR), rd_rn),
9293 CE(tmovmskw, e900030, 2, (RR, RIWR), rd_rn),
9294 CE(tmrc, e100110, 2, (RR, RIWC), rd_rn),
9295 CE(tmrrc, c500000, 3, (RR, RR, RIWR), rd_rn_rm),
9296 CE(torcb, e13f150, 1, (RR), iwmmxt_tandorc),
9297 CE(torch, e53f150, 1, (RR), iwmmxt_tandorc),
9298 CE(torcw, e93f150, 1, (RR), iwmmxt_tandorc),
9299 CE(waccb, e0001c0, 2, (RIWR, RIWR), rd_rn),
9300 CE(wacch, e4001c0, 2, (RIWR, RIWR), rd_rn),
9301 CE(waccw, e8001c0, 2, (RIWR, RIWR), rd_rn),
9302 CE(waddbss, e300180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9303 CE(waddb, e000180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9304 CE(waddbus, e100180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9305 CE(waddhss, e700180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9306 CE(waddh, e400180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9307 CE(waddhus, e500180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9308 CE(waddwss, eb00180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9309 CE(waddw, e800180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9310 CE(waddwus, e900180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9311 CE(waligni, e000020, 4, (RIWR, RIWR, RIWR, I7), iwmmxt_waligni),
9312 CE(walignr0, e800020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9313 CE(walignr1, e900020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9314 CE(walignr2, ea00020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9315 CE(walignr3, eb00020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9316 CE(wand, e200000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9317 CE(wandn, e300000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9318 CE(wavg2b, e800000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9319 CE(wavg2br, e900000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9320 CE(wavg2h, ec00000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9321 CE(wavg2hr, ed00000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9322 CE(wcmpeqb, e000060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9323 CE(wcmpeqh, e400060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9324 CE(wcmpeqw, e800060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9325 CE(wcmpgtub, e100060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9326 CE(wcmpgtuh, e500060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9327 CE(wcmpgtuw, e900060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9328 CE(wcmpgtsb, e300060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9329 CE(wcmpgtsh, e700060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9330 CE(wcmpgtsw, eb00060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9331 CE(wldrb, c100000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
9332 CE(wldrh, c500000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
9333 CE(wldrw, c100100, 2, (RIWR_RIWC, ADDR), iwmmxt_wldstw),
9334 CE(wldrd, c500100, 2, (RIWR, ADDR), iwmmxt_wldstd),
9335 CE(wmacs, e600100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9336 CE(wmacsz, e700100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9337 CE(wmacu, e400100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9338 CE(wmacuz, e500100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9339 CE(wmadds, ea00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9340 CE(wmaddu, e800100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9341 CE(wmaxsb, e200160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9342 CE(wmaxsh, e600160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9343 CE(wmaxsw, ea00160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9344 CE(wmaxub, e000160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9345 CE(wmaxuh, e400160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9346 CE(wmaxuw, e800160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9347 CE(wminsb, e300160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9348 CE(wminsh, e700160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9349 CE(wminsw, eb00160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9350 CE(wminub, e100160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9351 CE(wminuh, e500160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9352 CE(wminuw, e900160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9353 CE(wmov, e000000, 2, (RIWR, RIWR), iwmmxt_wmov),
9354 CE(wmulsm, e300100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9355 CE(wmulsl, e200100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9356 CE(wmulum, e100100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9357 CE(wmulul, e000100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9358 CE(wor, e000000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9359 CE(wpackhss, e700080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9360 CE(wpackhus, e500080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9361 CE(wpackwss, eb00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9362 CE(wpackwus, e900080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9363 CE(wpackdss, ef00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9364 CE(wpackdus, ed00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9365 CE(wrorh, e700040, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9366 CE(wrorhg, e700148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
9367 CE(wrorw, eb00040, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9368 CE(wrorwg, eb00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
9369 CE(wrord, ef00040, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9370 CE(wrordg, ef00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
9371 CE(wsadb, e000120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9372 CE(wsadbz, e100120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9373 CE(wsadh, e400120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9374 CE(wsadhz, e500120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9375 CE(wshufh, e0001e0, 3, (RIWR, RIWR, I255), iwmmxt_wshufh),
9376 CE(wsllh, e500040, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9377 CE(wsllhg, e500148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
9378 CE(wsllw, e900040, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9379 CE(wsllwg, e900148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
9380 CE(wslld, ed00040, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9381 CE(wslldg, ed00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
9382 CE(wsrah, e400040, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9383 CE(wsrahg, e400148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
9384 CE(wsraw, e800040, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9385 CE(wsrawg, e800148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
9386 CE(wsrad, ec00040, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9387 CE(wsradg, ec00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
9388 CE(wsrlh, e600040, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9389 CE(wsrlhg, e600148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
9390 CE(wsrlw, ea00040, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9391 CE(wsrlwg, ea00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
9392 CE(wsrld, ee00040, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9393 CE(wsrldg, ee00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
9394 CE(wstrb, c000000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
9395 CE(wstrh, c400000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
9396 CE(wstrw, c000100, 2, (RIWR_RIWC, ADDR), iwmmxt_wldstw),
9397 CE(wstrd, c400100, 2, (RIWR, ADDR), iwmmxt_wldstd),
9398 CE(wsubbss, e3001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9399 CE(wsubb, e0001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9400 CE(wsubbus, e1001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9401 CE(wsubhss, e7001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9402 CE(wsubh, e4001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9403 CE(wsubhus, e5001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9404 CE(wsubwss, eb001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9405 CE(wsubw, e8001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9406 CE(wsubwus, e9001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9407 CE(wunpckehub,e0000c0, 2, (RIWR, RIWR), rd_rn),
9408 CE(wunpckehuh,e4000c0, 2, (RIWR, RIWR), rd_rn),
9409 CE(wunpckehuw,e8000c0, 2, (RIWR, RIWR), rd_rn),
9410 CE(wunpckehsb,e2000c0, 2, (RIWR, RIWR), rd_rn),
9411 CE(wunpckehsh,e6000c0, 2, (RIWR, RIWR), rd_rn),
9412 CE(wunpckehsw,ea000c0, 2, (RIWR, RIWR), rd_rn),
9413 CE(wunpckihb, e1000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9414 CE(wunpckihh, e5000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9415 CE(wunpckihw, e9000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9416 CE(wunpckelub,e0000e0, 2, (RIWR, RIWR), rd_rn),
9417 CE(wunpckeluh,e4000e0, 2, (RIWR, RIWR), rd_rn),
9418 CE(wunpckeluw,e8000e0, 2, (RIWR, RIWR), rd_rn),
9419 CE(wunpckelsb,e2000e0, 2, (RIWR, RIWR), rd_rn),
9420 CE(wunpckelsh,e6000e0, 2, (RIWR, RIWR), rd_rn),
9421 CE(wunpckelsw,ea000e0, 2, (RIWR, RIWR), rd_rn),
9422 CE(wunpckilb, e1000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9423 CE(wunpckilh, e5000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9424 CE(wunpckilw, e9000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9425 CE(wxor, e100000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9426 CE(wzero, e300000, 1, (RIWR), iwmmxt_wzero),
9428 #undef ARM_VARIANT
9429 #define ARM_VARIANT ARM_CEXT_MAVERICK /* Cirrus Maverick instructions. */
9430 CE(cfldrs, c100400, 2, (RMF, ADDR), rd_cpaddr),
9431 CE(cfldrd, c500400, 2, (RMD, ADDR), rd_cpaddr),
9432 CE(cfldr32, c100500, 2, (RMFX, ADDR), rd_cpaddr),
9433 CE(cfldr64, c500500, 2, (RMDX, ADDR), rd_cpaddr),
9434 CE(cfstrs, c000400, 2, (RMF, ADDR), rd_cpaddr),
9435 CE(cfstrd, c400400, 2, (RMD, ADDR), rd_cpaddr),
9436 CE(cfstr32, c000500, 2, (RMFX, ADDR), rd_cpaddr),
9437 CE(cfstr64, c400500, 2, (RMDX, ADDR), rd_cpaddr),
9438 CE(cfmvsr, e000450, 2, (RMF, RR), rn_rd),
9439 CE(cfmvrs, e100450, 2, (RR, RMF), rd_rn),
9440 CE(cfmvdlr, e000410, 2, (RMD, RR), rn_rd),
9441 CE(cfmvrdl, e100410, 2, (RR, RMD), rd_rn),
9442 CE(cfmvdhr, e000430, 2, (RMD, RR), rn_rd),
9443 CE(cfmvrdh, e100430, 2, (RR, RMD), rd_rn),
9444 CE(cfmv64lr, e000510, 2, (RMDX, RR), rn_rd),
9445 CE(cfmvr64l, e100510, 2, (RR, RMDX), rd_rn),
9446 CE(cfmv64hr, e000530, 2, (RMDX, RR), rn_rd),
9447 CE(cfmvr64h, e100530, 2, (RR, RMDX), rd_rn),
9448 CE(cfmval32, e200440, 2, (RMAX, RMFX), rd_rn),
9449 CE(cfmv32al, e100440, 2, (RMFX, RMAX), rd_rn),
9450 CE(cfmvam32, e200460, 2, (RMAX, RMFX), rd_rn),
9451 CE(cfmv32am, e100460, 2, (RMFX, RMAX), rd_rn),
9452 CE(cfmvah32, e200480, 2, (RMAX, RMFX), rd_rn),
9453 CE(cfmv32ah, e100480, 2, (RMFX, RMAX), rd_rn),
9454 CE(cfmva32, e2004a0, 2, (RMAX, RMFX), rd_rn),
9455 CE(cfmv32a, e1004a0, 2, (RMFX, RMAX), rd_rn),
9456 CE(cfmva64, e2004c0, 2, (RMAX, RMDX), rd_rn),
9457 CE(cfmv64a, e1004c0, 2, (RMDX, RMAX), rd_rn),
9458 CE(cfmvsc32, e2004e0, 2, (RMDS, RMDX), mav_dspsc),
9459 CE(cfmv32sc, e1004e0, 2, (RMDX, RMDS), rd),
9460 CE(cfcpys, e000400, 2, (RMF, RMF), rd_rn),
9461 CE(cfcpyd, e000420, 2, (RMD, RMD), rd_rn),
9462 CE(cfcvtsd, e000460, 2, (RMD, RMF), rd_rn),
9463 CE(cfcvtds, e000440, 2, (RMF, RMD), rd_rn),
9464 CE(cfcvt32s, e000480, 2, (RMF, RMFX), rd_rn),
9465 CE(cfcvt32d, e0004a0, 2, (RMD, RMFX), rd_rn),
9466 CE(cfcvt64s, e0004c0, 2, (RMF, RMDX), rd_rn),
9467 CE(cfcvt64d, e0004e0, 2, (RMD, RMDX), rd_rn),
9468 CE(cfcvts32, e100580, 2, (RMFX, RMF), rd_rn),
9469 CE(cfcvtd32, e1005a0, 2, (RMFX, RMD), rd_rn),
9470 CE(cftruncs32,e1005c0, 2, (RMFX, RMF), rd_rn),
9471 CE(cftruncd32,e1005e0, 2, (RMFX, RMD), rd_rn),
9472 CE(cfrshl32, e000550, 3, (RMFX, RMFX, RR), mav_triple),
9473 CE(cfrshl64, e000570, 3, (RMDX, RMDX, RR), mav_triple),
9474 CE(cfsh32, e000500, 3, (RMFX, RMFX, I63s), mav_shift),
9475 CE(cfsh64, e200500, 3, (RMDX, RMDX, I63s), mav_shift),
9476 CE(cfcmps, e100490, 3, (RR, RMF, RMF), rd_rn_rm),
9477 CE(cfcmpd, e1004b0, 3, (RR, RMD, RMD), rd_rn_rm),
9478 CE(cfcmp32, e100590, 3, (RR, RMFX, RMFX), rd_rn_rm),
9479 CE(cfcmp64, e1005b0, 3, (RR, RMDX, RMDX), rd_rn_rm),
9480 CE(cfabss, e300400, 2, (RMF, RMF), rd_rn),
9481 CE(cfabsd, e300420, 2, (RMD, RMD), rd_rn),
9482 CE(cfnegs, e300440, 2, (RMF, RMF), rd_rn),
9483 CE(cfnegd, e300460, 2, (RMD, RMD), rd_rn),
9484 CE(cfadds, e300480, 3, (RMF, RMF, RMF), rd_rn_rm),
9485 CE(cfaddd, e3004a0, 3, (RMD, RMD, RMD), rd_rn_rm),
9486 CE(cfsubs, e3004c0, 3, (RMF, RMF, RMF), rd_rn_rm),
9487 CE(cfsubd, e3004e0, 3, (RMD, RMD, RMD), rd_rn_rm),
9488 CE(cfmuls, e100400, 3, (RMF, RMF, RMF), rd_rn_rm),
9489 CE(cfmuld, e100420, 3, (RMD, RMD, RMD), rd_rn_rm),
9490 CE(cfabs32, e300500, 2, (RMFX, RMFX), rd_rn),
9491 CE(cfabs64, e300520, 2, (RMDX, RMDX), rd_rn),
9492 CE(cfneg32, e300540, 2, (RMFX, RMFX), rd_rn),
9493 CE(cfneg64, e300560, 2, (RMDX, RMDX), rd_rn),
9494 CE(cfadd32, e300580, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
9495 CE(cfadd64, e3005a0, 3, (RMDX, RMDX, RMDX), rd_rn_rm),
9496 CE(cfsub32, e3005c0, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
9497 CE(cfsub64, e3005e0, 3, (RMDX, RMDX, RMDX), rd_rn_rm),
9498 CE(cfmul32, e100500, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
9499 CE(cfmul64, e100520, 3, (RMDX, RMDX, RMDX), rd_rn_rm),
9500 CE(cfmac32, e100540, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
9501 CE(cfmsc32, e100560, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
9502 CE(cfmadd32, e000600, 4, (RMAX, RMFX, RMFX, RMFX), mav_quad),
9503 CE(cfmsub32, e100600, 4, (RMAX, RMFX, RMFX, RMFX), mav_quad),
9504 CE(cfmadda32, e200600, 4, (RMAX, RMAX, RMFX, RMFX), mav_quad),
9505 CE(cfmsuba32, e300600, 4, (RMAX, RMAX, RMFX, RMFX), mav_quad),
9507 #undef ARM_VARIANT
9508 #undef THUMB_VARIANT
9509 #undef TCE
9510 #undef TCM
9511 #undef TUE
9512 #undef TUF
9513 #undef TCC
9514 #undef CE
9515 #undef CM
9516 #undef UE
9517 #undef UF
9518 #undef UT
9519 #undef OPS0
9520 #undef OPS1
9521 #undef OPS2
9522 #undef OPS3
9523 #undef OPS4
9524 #undef OPS5
9525 #undef OPS6
9526 #undef do_0
9528 /* MD interface: bits in the object file. */
9530 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
9531 for use in the a.out file, and stores them in the array pointed to by buf.
9532 This knows about the endian-ness of the target machine and does
9533 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
9534 2 (short) and 4 (long) Floating numbers are put out as a series of
9535 LITTLENUMS (shorts, here at least). */
9537 void
9538 md_number_to_chars (char * buf, valueT val, int n)
9540 if (target_big_endian)
9541 number_to_chars_bigendian (buf, val, n);
9542 else
9543 number_to_chars_littleendian (buf, val, n);
9546 static valueT
9547 md_chars_to_number (char * buf, int n)
9549 valueT result = 0;
9550 unsigned char * where = (unsigned char *) buf;
9552 if (target_big_endian)
9554 while (n--)
9556 result <<= 8;
9557 result |= (*where++ & 255);
9560 else
9562 while (n--)
9564 result <<= 8;
9565 result |= (where[n] & 255);
9569 return result;
9572 /* MD interface: Sections. */
9575 md_estimate_size_before_relax (fragS * fragP ATTRIBUTE_UNUSED,
9576 segT segtype ATTRIBUTE_UNUSED)
9578 as_fatal (_("md_estimate_size_before_relax\n"));
9579 return 1;
9582 /* Round up a section size to the appropriate boundary. */
9584 valueT
9585 md_section_align (segT segment ATTRIBUTE_UNUSED,
9586 valueT size)
9588 #ifdef OBJ_ELF
9589 return size;
9590 #else
9591 /* Round all sects to multiple of 4. */
9592 return (size + 3) & ~3;
9593 #endif
9596 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
9597 of an rs_align_code fragment. */
9599 void
9600 arm_handle_align (fragS * fragP)
9602 static char const arm_noop[4] = { 0x00, 0x00, 0xa0, 0xe1 };
9603 static char const thumb_noop[2] = { 0xc0, 0x46 };
9604 static char const arm_bigend_noop[4] = { 0xe1, 0xa0, 0x00, 0x00 };
9605 static char const thumb_bigend_noop[2] = { 0x46, 0xc0 };
9607 int bytes, fix, noop_size;
9608 char * p;
9609 const char * noop;
9611 if (fragP->fr_type != rs_align_code)
9612 return;
9614 bytes = fragP->fr_next->fr_address - fragP->fr_address - fragP->fr_fix;
9615 p = fragP->fr_literal + fragP->fr_fix;
9616 fix = 0;
9618 if (bytes > MAX_MEM_FOR_RS_ALIGN_CODE)
9619 bytes &= MAX_MEM_FOR_RS_ALIGN_CODE;
9621 if (fragP->tc_frag_data)
9623 if (target_big_endian)
9624 noop = thumb_bigend_noop;
9625 else
9626 noop = thumb_noop;
9627 noop_size = sizeof (thumb_noop);
9629 else
9631 if (target_big_endian)
9632 noop = arm_bigend_noop;
9633 else
9634 noop = arm_noop;
9635 noop_size = sizeof (arm_noop);
9638 if (bytes & (noop_size - 1))
9640 fix = bytes & (noop_size - 1);
9641 memset (p, 0, fix);
9642 p += fix;
9643 bytes -= fix;
9646 while (bytes >= noop_size)
9648 memcpy (p, noop, noop_size);
9649 p += noop_size;
9650 bytes -= noop_size;
9651 fix += noop_size;
9654 fragP->fr_fix += fix;
9655 fragP->fr_var = noop_size;
9658 /* Called from md_do_align. Used to create an alignment
9659 frag in a code section. */
9661 void
9662 arm_frag_align_code (int n, int max)
9664 char * p;
9666 /* We assume that there will never be a requirement
9667 to support alignments greater than 32 bytes. */
9668 if (max > MAX_MEM_FOR_RS_ALIGN_CODE)
9669 as_fatal (_("alignments greater than 32 bytes not supported in .text sections."));
9671 p = frag_var (rs_align_code,
9672 MAX_MEM_FOR_RS_ALIGN_CODE,
9674 (relax_substateT) max,
9675 (symbolS *) NULL,
9676 (offsetT) n,
9677 (char *) NULL);
9678 *p = 0;
9681 /* Perform target specific initialisation of a frag. */
9683 void
9684 arm_init_frag (fragS * fragP)
9686 /* Record whether this frag is in an ARM or a THUMB area. */
9687 fragP->tc_frag_data = thumb_mode;
9690 #ifdef OBJ_ELF
9691 /* When we change sections we need to issue a new mapping symbol. */
9693 void
9694 arm_elf_change_section (void)
9696 flagword flags;
9697 segment_info_type *seginfo;
9699 /* Link an unlinked unwind index table section to the .text section. */
9700 if (elf_section_type (now_seg) == SHT_ARM_EXIDX
9701 && elf_linked_to_section (now_seg) == NULL)
9702 elf_linked_to_section (now_seg) = text_section;
9704 if (!SEG_NORMAL (now_seg))
9705 return;
9707 flags = bfd_get_section_flags (stdoutput, now_seg);
9709 /* We can ignore sections that only contain debug info. */
9710 if ((flags & SEC_ALLOC) == 0)
9711 return;
9713 seginfo = seg_info (now_seg);
9714 mapstate = seginfo->tc_segment_info_data.mapstate;
9715 marked_pr_dependency = seginfo->tc_segment_info_data.marked_pr_dependency;
9719 arm_elf_section_type (const char * str, size_t len)
9721 if (len == 5 && strncmp (str, "exidx", 5) == 0)
9722 return SHT_ARM_EXIDX;
9724 return -1;
9727 /* Code to deal with unwinding tables. */
9729 static void add_unwind_adjustsp (offsetT);
9731 /* Cenerate and deferred unwind frame offset. */
9733 static void
9734 flush_pending_unwind (void)
9736 offsetT offset;
9738 offset = unwind.pending_offset;
9739 unwind.pending_offset = 0;
9740 if (offset != 0)
9741 add_unwind_adjustsp (offset);
9744 /* Add an opcode to this list for this function. Two-byte opcodes should
9745 be passed as op[0] << 8 | op[1]. The list of opcodes is built in reverse
9746 order. */
9748 static void
9749 add_unwind_opcode (valueT op, int length)
9751 /* Add any deferred stack adjustment. */
9752 if (unwind.pending_offset)
9753 flush_pending_unwind ();
9755 unwind.sp_restored = 0;
9757 if (unwind.opcode_count + length > unwind.opcode_alloc)
9759 unwind.opcode_alloc += ARM_OPCODE_CHUNK_SIZE;
9760 if (unwind.opcodes)
9761 unwind.opcodes = xrealloc (unwind.opcodes,
9762 unwind.opcode_alloc);
9763 else
9764 unwind.opcodes = xmalloc (unwind.opcode_alloc);
9766 while (length > 0)
9768 length--;
9769 unwind.opcodes[unwind.opcode_count] = op & 0xff;
9770 op >>= 8;
9771 unwind.opcode_count++;
9775 /* Add unwind opcodes to adjust the stack pointer. */
9777 static void
9778 add_unwind_adjustsp (offsetT offset)
9780 valueT op;
9782 if (offset > 0x200)
9784 /* We need at most 5 bytes to hold a 32-bit value in a uleb128. */
9785 char bytes[5];
9786 int n;
9787 valueT o;
9789 /* Long form: 0xb2, uleb128. */
9790 /* This might not fit in a word so add the individual bytes,
9791 remembering the list is built in reverse order. */
9792 o = (valueT) ((offset - 0x204) >> 2);
9793 if (o == 0)
9794 add_unwind_opcode (0, 1);
9796 /* Calculate the uleb128 encoding of the offset. */
9797 n = 0;
9798 while (o)
9800 bytes[n] = o & 0x7f;
9801 o >>= 7;
9802 if (o)
9803 bytes[n] |= 0x80;
9804 n++;
9806 /* Add the insn. */
9807 for (; n; n--)
9808 add_unwind_opcode (bytes[n - 1], 1);
9809 add_unwind_opcode (0xb2, 1);
9811 else if (offset > 0x100)
9813 /* Two short opcodes. */
9814 add_unwind_opcode (0x3f, 1);
9815 op = (offset - 0x104) >> 2;
9816 add_unwind_opcode (op, 1);
9818 else if (offset > 0)
9820 /* Short opcode. */
9821 op = (offset - 4) >> 2;
9822 add_unwind_opcode (op, 1);
9824 else if (offset < 0)
9826 offset = -offset;
9827 while (offset > 0x100)
9829 add_unwind_opcode (0x7f, 1);
9830 offset -= 0x100;
9832 op = ((offset - 4) >> 2) | 0x40;
9833 add_unwind_opcode (op, 1);
9837 /* Finish the list of unwind opcodes for this function. */
9838 static void
9839 finish_unwind_opcodes (void)
9841 valueT op;
9843 if (unwind.fp_used)
9845 /* Adjust sp as neccessary. */
9846 unwind.pending_offset += unwind.fp_offset - unwind.frame_size;
9847 flush_pending_unwind ();
9849 /* After restoring sp from the frame pointer. */
9850 op = 0x90 | unwind.fp_reg;
9851 add_unwind_opcode (op, 1);
9853 else
9854 flush_pending_unwind ();
9858 /* Start an exception table entry. If idx is nonzero this is an index table
9859 entry. */
9861 static void
9862 start_unwind_section (const segT text_seg, int idx)
9864 const char * text_name;
9865 const char * prefix;
9866 const char * prefix_once;
9867 const char * group_name;
9868 size_t prefix_len;
9869 size_t text_len;
9870 char * sec_name;
9871 size_t sec_name_len;
9872 int type;
9873 int flags;
9874 int linkonce;
9876 if (idx)
9878 prefix = ELF_STRING_ARM_unwind;
9879 prefix_once = ELF_STRING_ARM_unwind_once;
9880 type = SHT_ARM_EXIDX;
9882 else
9884 prefix = ELF_STRING_ARM_unwind_info;
9885 prefix_once = ELF_STRING_ARM_unwind_info_once;
9886 type = SHT_PROGBITS;
9889 text_name = segment_name (text_seg);
9890 if (streq (text_name, ".text"))
9891 text_name = "";
9893 if (strncmp (text_name, ".gnu.linkonce.t.",
9894 strlen (".gnu.linkonce.t.")) == 0)
9896 prefix = prefix_once;
9897 text_name += strlen (".gnu.linkonce.t.");
9900 prefix_len = strlen (prefix);
9901 text_len = strlen (text_name);
9902 sec_name_len = prefix_len + text_len;
9903 sec_name = xmalloc (sec_name_len + 1);
9904 memcpy (sec_name, prefix, prefix_len);
9905 memcpy (sec_name + prefix_len, text_name, text_len);
9906 sec_name[prefix_len + text_len] = '\0';
9908 flags = SHF_ALLOC;
9909 linkonce = 0;
9910 group_name = 0;
9912 /* Handle COMDAT group. */
9913 if (prefix != prefix_once && (text_seg->flags & SEC_LINK_ONCE) != 0)
9915 group_name = elf_group_name (text_seg);
9916 if (group_name == NULL)
9918 as_bad ("Group section `%s' has no group signature",
9919 segment_name (text_seg));
9920 ignore_rest_of_line ();
9921 return;
9923 flags |= SHF_GROUP;
9924 linkonce = 1;
9927 obj_elf_change_section (sec_name, type, flags, 0, group_name, linkonce, 0);
9929 /* Set the setion link for index tables. */
9930 if (idx)
9931 elf_linked_to_section (now_seg) = text_seg;
9935 /* Start an unwind table entry. HAVE_DATA is nonzero if we have additional
9936 personality routine data. Returns zero, or the index table value for
9937 and inline entry. */
9939 static valueT
9940 create_unwind_entry (int have_data)
9942 int size;
9943 addressT where;
9944 char *ptr;
9945 /* The current word of data. */
9946 valueT data;
9947 /* The number of bytes left in this word. */
9948 int n;
9950 finish_unwind_opcodes ();
9952 /* Remember the current text section. */
9953 unwind.saved_seg = now_seg;
9954 unwind.saved_subseg = now_subseg;
9956 start_unwind_section (now_seg, 0);
9958 if (unwind.personality_routine == NULL)
9960 if (unwind.personality_index == -2)
9962 if (have_data)
9963 as_bad (_("handerdata in cantunwind frame"));
9964 return 1; /* EXIDX_CANTUNWIND. */
9967 /* Use a default personality routine if none is specified. */
9968 if (unwind.personality_index == -1)
9970 if (unwind.opcode_count > 3)
9971 unwind.personality_index = 1;
9972 else
9973 unwind.personality_index = 0;
9976 /* Space for the personality routine entry. */
9977 if (unwind.personality_index == 0)
9979 if (unwind.opcode_count > 3)
9980 as_bad (_("too many unwind opcodes for personality routine 0"));
9982 if (!have_data)
9984 /* All the data is inline in the index table. */
9985 data = 0x80;
9986 n = 3;
9987 while (unwind.opcode_count > 0)
9989 unwind.opcode_count--;
9990 data = (data << 8) | unwind.opcodes[unwind.opcode_count];
9991 n--;
9994 /* Pad with "finish" opcodes. */
9995 while (n--)
9996 data = (data << 8) | 0xb0;
9998 return data;
10000 size = 0;
10002 else
10003 /* We get two opcodes "free" in the first word. */
10004 size = unwind.opcode_count - 2;
10006 else
10007 /* An extra byte is required for the opcode count. */
10008 size = unwind.opcode_count + 1;
10010 size = (size + 3) >> 2;
10011 if (size > 0xff)
10012 as_bad (_("too many unwind opcodes"));
10014 frag_align (2, 0, 0);
10015 record_alignment (now_seg, 2);
10016 unwind.table_entry = expr_build_dot ();
10018 /* Allocate the table entry. */
10019 ptr = frag_more ((size << 2) + 4);
10020 where = frag_now_fix () - ((size << 2) + 4);
10022 switch (unwind.personality_index)
10024 case -1:
10025 /* ??? Should this be a PLT generating relocation? */
10026 /* Custom personality routine. */
10027 fix_new (frag_now, where, 4, unwind.personality_routine, 0, 1,
10028 BFD_RELOC_ARM_PREL31);
10030 where += 4;
10031 ptr += 4;
10033 /* Set the first byte to the number of additional words. */
10034 data = size - 1;
10035 n = 3;
10036 break;
10038 /* ABI defined personality routines. */
10039 case 0:
10040 /* Three opcodes bytes are packed into the first word. */
10041 data = 0x80;
10042 n = 3;
10043 break;
10045 case 1:
10046 case 2:
10047 /* The size and first two opcode bytes go in the first word. */
10048 data = ((0x80 + unwind.personality_index) << 8) | size;
10049 n = 2;
10050 break;
10052 default:
10053 /* Should never happen. */
10054 abort ();
10057 /* Pack the opcodes into words (MSB first), reversing the list at the same
10058 time. */
10059 while (unwind.opcode_count > 0)
10061 if (n == 0)
10063 md_number_to_chars (ptr, data, 4);
10064 ptr += 4;
10065 n = 4;
10066 data = 0;
10068 unwind.opcode_count--;
10069 n--;
10070 data = (data << 8) | unwind.opcodes[unwind.opcode_count];
10073 /* Finish off the last word. */
10074 if (n < 4)
10076 /* Pad with "finish" opcodes. */
10077 while (n--)
10078 data = (data << 8) | 0xb0;
10080 md_number_to_chars (ptr, data, 4);
10083 if (!have_data)
10085 /* Add an empty descriptor if there is no user-specified data. */
10086 ptr = frag_more (4);
10087 md_number_to_chars (ptr, 0, 4);
10090 return 0;
10093 /* Convert REGNAME to a DWARF-2 register number. */
10096 tc_arm_regname_to_dw2regnum (const char *regname)
10098 int reg = arm_reg_parse ((char **) &regname, REG_TYPE_RN);
10100 if (reg == FAIL)
10101 return -1;
10103 return reg;
10106 /* Initialize the DWARF-2 unwind information for this procedure. */
10108 void
10109 tc_arm_frame_initial_instructions (void)
10111 cfi_add_CFA_def_cfa (REG_SP, 0);
10113 #endif /* OBJ_ELF */
10116 /* MD interface: Symbol and relocation handling. */
10118 /* Return the address within the segment that a PC-relative fixup is
10119 relative to. For ARM, PC-relative fixups applied to instructions
10120 are generally relative to the location of the fixup plus 8 bytes.
10121 Thumb branches are offset by 4, and Thumb loads relative to PC
10122 require special handling. */
10124 long
10125 md_pcrel_from_section (fixS * fixP, segT seg)
10127 offsetT base = fixP->fx_where + fixP->fx_frag->fr_address;
10129 /* If this is pc-relative and we are going to emit a relocation
10130 then we just want to put out any pipeline compensation that the linker
10131 will need. Otherwise we want to use the calculated base. */
10132 if (fixP->fx_pcrel
10133 && ((fixP->fx_addsy && S_GET_SEGMENT (fixP->fx_addsy) != seg)
10134 || arm_force_relocation (fixP)))
10135 base = 0;
10137 switch (fixP->fx_r_type)
10139 /* PC relative addressing on the Thumb is slightly odd as the
10140 bottom two bits of the PC are forced to zero for the
10141 calculation. This happens *after* application of the
10142 pipeline offset. However, Thumb adrl already adjusts for
10143 this, so we need not do it again. */
10144 case BFD_RELOC_ARM_THUMB_ADD:
10145 return base & ~3;
10147 case BFD_RELOC_ARM_THUMB_OFFSET:
10148 case BFD_RELOC_ARM_T32_OFFSET_IMM:
10149 case BFD_RELOC_ARM_T32_ADD_PC12:
10150 return (base + 4) & ~3;
10152 /* Thumb branches are simply offset by +4. */
10153 case BFD_RELOC_THUMB_PCREL_BRANCH7:
10154 case BFD_RELOC_THUMB_PCREL_BRANCH9:
10155 case BFD_RELOC_THUMB_PCREL_BRANCH12:
10156 case BFD_RELOC_THUMB_PCREL_BRANCH20:
10157 case BFD_RELOC_THUMB_PCREL_BRANCH23:
10158 case BFD_RELOC_THUMB_PCREL_BRANCH25:
10159 case BFD_RELOC_THUMB_PCREL_BLX:
10160 return base + 4;
10162 /* ARM mode branches are offset by +8. However, the Windows CE
10163 loader expects the relocation not to take this into account. */
10164 case BFD_RELOC_ARM_PCREL_BRANCH:
10165 case BFD_RELOC_ARM_PCREL_BLX:
10166 case BFD_RELOC_ARM_PLT32:
10167 #ifdef TE_WINCE
10168 return base;
10169 #else
10170 return base + 8;
10171 #endif
10173 /* ARM mode loads relative to PC are also offset by +8. Unlike
10174 branches, the Windows CE loader *does* expect the relocation
10175 to take this into account. */
10176 case BFD_RELOC_ARM_OFFSET_IMM:
10177 case BFD_RELOC_ARM_OFFSET_IMM8:
10178 case BFD_RELOC_ARM_HWLITERAL:
10179 case BFD_RELOC_ARM_LITERAL:
10180 case BFD_RELOC_ARM_CP_OFF_IMM:
10181 return base + 8;
10184 /* Other PC-relative relocations are un-offset. */
10185 default:
10186 return base;
10190 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
10191 Otherwise we have no need to default values of symbols. */
10193 symbolS *
10194 md_undefined_symbol (char * name ATTRIBUTE_UNUSED)
10196 #ifdef OBJ_ELF
10197 if (name[0] == '_' && name[1] == 'G'
10198 && streq (name, GLOBAL_OFFSET_TABLE_NAME))
10200 if (!GOT_symbol)
10202 if (symbol_find (name))
10203 as_bad ("GOT already in the symbol table");
10205 GOT_symbol = symbol_new (name, undefined_section,
10206 (valueT) 0, & zero_address_frag);
10209 return GOT_symbol;
10211 #endif
10213 return 0;
10216 /* Subroutine of md_apply_fix. Check to see if an immediate can be
10217 computed as two separate immediate values, added together. We
10218 already know that this value cannot be computed by just one ARM
10219 instruction. */
10221 static unsigned int
10222 validate_immediate_twopart (unsigned int val,
10223 unsigned int * highpart)
10225 unsigned int a;
10226 unsigned int i;
10228 for (i = 0; i < 32; i += 2)
10229 if (((a = rotate_left (val, i)) & 0xff) != 0)
10231 if (a & 0xff00)
10233 if (a & ~ 0xffff)
10234 continue;
10235 * highpart = (a >> 8) | ((i + 24) << 7);
10237 else if (a & 0xff0000)
10239 if (a & 0xff000000)
10240 continue;
10241 * highpart = (a >> 16) | ((i + 16) << 7);
10243 else
10245 assert (a & 0xff000000);
10246 * highpart = (a >> 24) | ((i + 8) << 7);
10249 return (a & 0xff) | (i << 7);
10252 return FAIL;
10255 static int
10256 validate_offset_imm (unsigned int val, int hwse)
10258 if ((hwse && val > 255) || val > 4095)
10259 return FAIL;
10260 return val;
10263 /* Subroutine of md_apply_fix. Do those data_ops which can take a
10264 negative immediate constant by altering the instruction. A bit of
10265 a hack really.
10266 MOV <-> MVN
10267 AND <-> BIC
10268 ADC <-> SBC
10269 by inverting the second operand, and
10270 ADD <-> SUB
10271 CMP <-> CMN
10272 by negating the second operand. */
10274 static int
10275 negate_data_op (unsigned long * instruction,
10276 unsigned long value)
10278 int op, new_inst;
10279 unsigned long negated, inverted;
10281 negated = encode_arm_immediate (-value);
10282 inverted = encode_arm_immediate (~value);
10284 op = (*instruction >> DATA_OP_SHIFT) & 0xf;
10285 switch (op)
10287 /* First negates. */
10288 case OPCODE_SUB: /* ADD <-> SUB */
10289 new_inst = OPCODE_ADD;
10290 value = negated;
10291 break;
10293 case OPCODE_ADD:
10294 new_inst = OPCODE_SUB;
10295 value = negated;
10296 break;
10298 case OPCODE_CMP: /* CMP <-> CMN */
10299 new_inst = OPCODE_CMN;
10300 value = negated;
10301 break;
10303 case OPCODE_CMN:
10304 new_inst = OPCODE_CMP;
10305 value = negated;
10306 break;
10308 /* Now Inverted ops. */
10309 case OPCODE_MOV: /* MOV <-> MVN */
10310 new_inst = OPCODE_MVN;
10311 value = inverted;
10312 break;
10314 case OPCODE_MVN:
10315 new_inst = OPCODE_MOV;
10316 value = inverted;
10317 break;
10319 case OPCODE_AND: /* AND <-> BIC */
10320 new_inst = OPCODE_BIC;
10321 value = inverted;
10322 break;
10324 case OPCODE_BIC:
10325 new_inst = OPCODE_AND;
10326 value = inverted;
10327 break;
10329 case OPCODE_ADC: /* ADC <-> SBC */
10330 new_inst = OPCODE_SBC;
10331 value = inverted;
10332 break;
10334 case OPCODE_SBC:
10335 new_inst = OPCODE_ADC;
10336 value = inverted;
10337 break;
10339 /* We cannot do anything. */
10340 default:
10341 return FAIL;
10344 if (value == (unsigned) FAIL)
10345 return FAIL;
10347 *instruction &= OPCODE_MASK;
10348 *instruction |= new_inst << DATA_OP_SHIFT;
10349 return value;
10352 void
10353 md_apply_fix (fixS * fixP,
10354 valueT * valP,
10355 segT seg)
10357 offsetT value = * valP;
10358 offsetT newval;
10359 unsigned int newimm;
10360 unsigned long temp;
10361 int sign;
10362 char * buf = fixP->fx_where + fixP->fx_frag->fr_literal;
10364 assert (fixP->fx_r_type <= BFD_RELOC_UNUSED);
10366 /* Note whether this will delete the relocation. */
10367 if (fixP->fx_addsy == 0 && !fixP->fx_pcrel)
10368 fixP->fx_done = 1;
10370 /* On a 64-bit host, silently truncate 'value' to 32 bits for
10371 consistency with the behavior on 32-bit hosts. Remember value
10372 for emit_reloc. */
10373 value &= 0xffffffff;
10374 value ^= 0x80000000;
10375 value -= 0x80000000;
10377 *valP = value;
10378 fixP->fx_addnumber = value;
10380 /* Same treatment for fixP->fx_offset. */
10381 fixP->fx_offset &= 0xffffffff;
10382 fixP->fx_offset ^= 0x80000000;
10383 fixP->fx_offset -= 0x80000000;
10385 switch (fixP->fx_r_type)
10387 case BFD_RELOC_NONE:
10388 /* This will need to go in the object file. */
10389 fixP->fx_done = 0;
10390 break;
10392 case BFD_RELOC_ARM_IMMEDIATE:
10393 /* We claim that this fixup has been processed here,
10394 even if in fact we generate an error because we do
10395 not have a reloc for it, so tc_gen_reloc will reject it. */
10396 fixP->fx_done = 1;
10398 if (fixP->fx_addsy
10399 && ! S_IS_DEFINED (fixP->fx_addsy))
10401 as_bad_where (fixP->fx_file, fixP->fx_line,
10402 _("undefined symbol %s used as an immediate value"),
10403 S_GET_NAME (fixP->fx_addsy));
10404 break;
10407 newimm = encode_arm_immediate (value);
10408 temp = md_chars_to_number (buf, INSN_SIZE);
10410 /* If the instruction will fail, see if we can fix things up by
10411 changing the opcode. */
10412 if (newimm == (unsigned int) FAIL
10413 && (newimm = negate_data_op (&temp, value)) == (unsigned int) FAIL)
10415 as_bad_where (fixP->fx_file, fixP->fx_line,
10416 _("invalid constant (%lx) after fixup"),
10417 (unsigned long) value);
10418 break;
10421 newimm |= (temp & 0xfffff000);
10422 md_number_to_chars (buf, (valueT) newimm, INSN_SIZE);
10423 break;
10425 case BFD_RELOC_ARM_ADRL_IMMEDIATE:
10427 unsigned int highpart = 0;
10428 unsigned int newinsn = 0xe1a00000; /* nop. */
10430 newimm = encode_arm_immediate (value);
10431 temp = md_chars_to_number (buf, INSN_SIZE);
10433 /* If the instruction will fail, see if we can fix things up by
10434 changing the opcode. */
10435 if (newimm == (unsigned int) FAIL
10436 && (newimm = negate_data_op (& temp, value)) == (unsigned int) FAIL)
10438 /* No ? OK - try using two ADD instructions to generate
10439 the value. */
10440 newimm = validate_immediate_twopart (value, & highpart);
10442 /* Yes - then make sure that the second instruction is
10443 also an add. */
10444 if (newimm != (unsigned int) FAIL)
10445 newinsn = temp;
10446 /* Still No ? Try using a negated value. */
10447 else if ((newimm = validate_immediate_twopart (- value, & highpart)) != (unsigned int) FAIL)
10448 temp = newinsn = (temp & OPCODE_MASK) | OPCODE_SUB << DATA_OP_SHIFT;
10449 /* Otherwise - give up. */
10450 else
10452 as_bad_where (fixP->fx_file, fixP->fx_line,
10453 _("unable to compute ADRL instructions for PC offset of 0x%lx"),
10454 (long) value);
10455 break;
10458 /* Replace the first operand in the 2nd instruction (which
10459 is the PC) with the destination register. We have
10460 already added in the PC in the first instruction and we
10461 do not want to do it again. */
10462 newinsn &= ~ 0xf0000;
10463 newinsn |= ((newinsn & 0x0f000) << 4);
10466 newimm |= (temp & 0xfffff000);
10467 md_number_to_chars (buf, (valueT) newimm, INSN_SIZE);
10469 highpart |= (newinsn & 0xfffff000);
10470 md_number_to_chars (buf + INSN_SIZE, (valueT) highpart, INSN_SIZE);
10472 break;
10474 case BFD_RELOC_ARM_OFFSET_IMM:
10475 case BFD_RELOC_ARM_LITERAL:
10476 sign = value >= 0;
10478 if (value < 0)
10479 value = - value;
10481 if (validate_offset_imm (value, 0) == FAIL)
10483 if (fixP->fx_r_type == BFD_RELOC_ARM_LITERAL)
10484 as_bad_where (fixP->fx_file, fixP->fx_line,
10485 _("invalid literal constant: pool needs to be closer"));
10486 else
10487 as_bad_where (fixP->fx_file, fixP->fx_line,
10488 _("bad immediate value for offset (%ld)"),
10489 (long) value);
10490 break;
10493 newval = md_chars_to_number (buf, INSN_SIZE);
10494 newval &= 0xff7ff000;
10495 newval |= value | (sign ? INDEX_UP : 0);
10496 md_number_to_chars (buf, newval, INSN_SIZE);
10497 break;
10499 case BFD_RELOC_ARM_OFFSET_IMM8:
10500 case BFD_RELOC_ARM_HWLITERAL:
10501 sign = value >= 0;
10503 if (value < 0)
10504 value = - value;
10506 if (validate_offset_imm (value, 1) == FAIL)
10508 if (fixP->fx_r_type == BFD_RELOC_ARM_HWLITERAL)
10509 as_bad_where (fixP->fx_file, fixP->fx_line,
10510 _("invalid literal constant: pool needs to be closer"));
10511 else
10512 as_bad (_("bad immediate value for half-word offset (%ld)"),
10513 (long) value);
10514 break;
10517 newval = md_chars_to_number (buf, INSN_SIZE);
10518 newval &= 0xff7ff0f0;
10519 newval |= ((value >> 4) << 8) | (value & 0xf) | (sign ? INDEX_UP : 0);
10520 md_number_to_chars (buf, newval, INSN_SIZE);
10521 break;
10523 case BFD_RELOC_ARM_T32_OFFSET_U8:
10524 if (value < 0 || value > 1020 || value % 4 != 0)
10525 as_bad_where (fixP->fx_file, fixP->fx_line,
10526 _("bad immediate value for offset (%ld)"), (long) value);
10527 value /= 4;
10529 newval = md_chars_to_number (buf+2, THUMB_SIZE);
10530 newval |= value;
10531 md_number_to_chars (buf+2, newval, THUMB_SIZE);
10532 break;
10534 case BFD_RELOC_ARM_T32_OFFSET_IMM:
10535 /* This is a complicated relocation used for all varieties of Thumb32
10536 load/store instruction with immediate offset:
10538 1110 100P u1WL NNNN XXXX YYYY iiii iiii - +/-(U) pre/post(P) 8-bit,
10539 *4, optional writeback(W)
10540 (doubleword load/store)
10542 1111 100S uTTL 1111 XXXX iiii iiii iiii - +/-(U) 12-bit PC-rel
10543 1111 100S 0TTL NNNN XXXX 1Pu1 iiii iiii - +/-(U) pre/post(P) 8-bit
10544 1111 100S 0TTL NNNN XXXX 1110 iiii iiii - positive 8-bit (T instruction)
10545 1111 100S 1TTL NNNN XXXX iiii iiii iiii - positive 12-bit
10546 1111 100S 0TTL NNNN XXXX 1100 iiii iiii - negative 8-bit
10548 Uppercase letters indicate bits that are already encoded at
10549 this point. Lowercase letters are our problem. For the
10550 second block of instructions, the secondary opcode nybble
10551 (bits 8..11) is present, and bit 23 is zero, even if this is
10552 a PC-relative operation. */
10553 newval = md_chars_to_number (buf, THUMB_SIZE);
10554 newval <<= 16;
10555 newval |= md_chars_to_number (buf+THUMB_SIZE, THUMB_SIZE);
10557 if ((newval & 0xf0000000) == 0xe0000000)
10559 /* Doubleword load/store: 8-bit offset, scaled by 4. */
10560 if (value >= 0)
10561 newval |= (1 << 23);
10562 else
10563 value = -value;
10564 if (value % 4 != 0)
10566 as_bad_where (fixP->fx_file, fixP->fx_line,
10567 _("offset not a multiple of 4"));
10568 break;
10570 value /= 4;
10571 if (value >= 0xff)
10573 as_bad_where (fixP->fx_file, fixP->fx_line,
10574 _("offset out of range"));
10575 break;
10577 newval &= ~0xff;
10579 else if ((newval & 0x000f0000) == 0x000f0000)
10581 /* PC-relative, 12-bit offset. */
10582 if (value >= 0)
10583 newval |= (1 << 23);
10584 else
10585 value = -value;
10586 if (value >= 0xfff)
10588 as_bad_where (fixP->fx_file, fixP->fx_line,
10589 _("offset out of range"));
10590 break;
10592 newval &= ~0xfff;
10594 else if ((newval & 0x00000100) == 0x00000100)
10596 /* Writeback: 8-bit, +/- offset. */
10597 if (value >= 0)
10598 newval |= (1 << 9);
10599 else
10600 value = -value;
10601 if (value >= 0xff)
10603 as_bad_where (fixP->fx_file, fixP->fx_line,
10604 _("offset out of range"));
10605 break;
10607 newval &= ~0xff;
10609 else if ((newval & 0x00000f00) == 0x00000e00)
10611 /* T-instruction: positive 8-bit offset. */
10612 if (value < 0 || value >= 0xff)
10614 as_bad_where (fixP->fx_file, fixP->fx_line,
10615 _("offset out of range"));
10616 break;
10618 newval &= ~0xff;
10619 newval |= value;
10621 else
10623 /* Positive 12-bit or negative 8-bit offset. */
10624 int limit;
10625 if (value >= 0)
10627 newval |= (1 << 23);
10628 limit = 0xfff;
10630 else
10632 value = -value;
10633 limit = 0xff;
10635 if (value > limit)
10637 as_bad_where (fixP->fx_file, fixP->fx_line,
10638 _("offset out of range"));
10639 break;
10641 newval &= ~limit;
10644 newval |= value;
10645 md_number_to_chars (buf, (newval >> 16) & 0xffff, THUMB_SIZE);
10646 md_number_to_chars (buf + THUMB_SIZE, newval & 0xffff, THUMB_SIZE);
10647 break;
10649 case BFD_RELOC_ARM_SHIFT_IMM:
10650 newval = md_chars_to_number (buf, INSN_SIZE);
10651 if (((unsigned long) value) > 32
10652 || (value == 32
10653 && (((newval & 0x60) == 0) || (newval & 0x60) == 0x60)))
10655 as_bad_where (fixP->fx_file, fixP->fx_line,
10656 _("shift expression is too large"));
10657 break;
10660 if (value == 0)
10661 /* Shifts of zero must be done as lsl. */
10662 newval &= ~0x60;
10663 else if (value == 32)
10664 value = 0;
10665 newval &= 0xfffff07f;
10666 newval |= (value & 0x1f) << 7;
10667 md_number_to_chars (buf, newval, INSN_SIZE);
10668 break;
10670 case BFD_RELOC_ARM_T32_IMMEDIATE:
10671 case BFD_RELOC_ARM_T32_IMM12:
10672 case BFD_RELOC_ARM_T32_ADD_PC12:
10673 /* We claim that this fixup has been processed here,
10674 even if in fact we generate an error because we do
10675 not have a reloc for it, so tc_gen_reloc will reject it. */
10676 fixP->fx_done = 1;
10678 if (fixP->fx_addsy
10679 && ! S_IS_DEFINED (fixP->fx_addsy))
10681 as_bad_where (fixP->fx_file, fixP->fx_line,
10682 _("undefined symbol %s used as an immediate value"),
10683 S_GET_NAME (fixP->fx_addsy));
10684 break;
10687 newval = md_chars_to_number (buf, THUMB_SIZE);
10688 newval <<= 16;
10689 newval |= md_chars_to_number (buf+2, THUMB_SIZE);
10691 /* FUTURE: Implement analogue of negate_data_op for T32. */
10692 if (fixP->fx_r_type == BFD_RELOC_ARM_T32_IMMEDIATE)
10693 newimm = encode_thumb32_immediate (value);
10694 else
10696 /* 12 bit immediate for addw/subw. */
10697 if (value < 0)
10699 value = -value;
10700 newval ^= 0x00a00000;
10702 if (value > 0xfff)
10703 newimm = (unsigned int) FAIL;
10704 else
10705 newimm = value;
10708 if (newimm == (unsigned int)FAIL)
10710 as_bad_where (fixP->fx_file, fixP->fx_line,
10711 _("invalid constant (%lx) after fixup"),
10712 (unsigned long) value);
10713 break;
10716 newval |= (newimm & 0x800) << 15;
10717 newval |= (newimm & 0x700) << 4;
10718 newval |= (newimm & 0x0ff);
10720 md_number_to_chars (buf, (valueT) ((newval >> 16) & 0xffff), THUMB_SIZE);
10721 md_number_to_chars (buf+2, (valueT) (newval & 0xffff), THUMB_SIZE);
10722 break;
10724 case BFD_RELOC_ARM_SMI:
10725 if (((unsigned long) value) > 0xffff)
10726 as_bad_where (fixP->fx_file, fixP->fx_line,
10727 _("invalid smi expression"));
10728 newval = md_chars_to_number (buf, INSN_SIZE);
10729 newval |= (value & 0xf) | ((value & 0xfff0) << 4);
10730 md_number_to_chars (buf, newval, INSN_SIZE);
10731 break;
10733 case BFD_RELOC_ARM_SWI:
10734 if (fixP->tc_fix_data != 0)
10736 if (((unsigned long) value) > 0xff)
10737 as_bad_where (fixP->fx_file, fixP->fx_line,
10738 _("invalid swi expression"));
10739 newval = md_chars_to_number (buf, THUMB_SIZE);
10740 newval |= value;
10741 md_number_to_chars (buf, newval, THUMB_SIZE);
10743 else
10745 if (((unsigned long) value) > 0x00ffffff)
10746 as_bad_where (fixP->fx_file, fixP->fx_line,
10747 _("invalid swi expression"));
10748 newval = md_chars_to_number (buf, INSN_SIZE);
10749 newval |= value;
10750 md_number_to_chars (buf, newval, INSN_SIZE);
10752 break;
10754 case BFD_RELOC_ARM_MULTI:
10755 if (((unsigned long) value) > 0xffff)
10756 as_bad_where (fixP->fx_file, fixP->fx_line,
10757 _("invalid expression in load/store multiple"));
10758 newval = value | md_chars_to_number (buf, INSN_SIZE);
10759 md_number_to_chars (buf, newval, INSN_SIZE);
10760 break;
10762 case BFD_RELOC_ARM_PCREL_BRANCH:
10763 #ifdef OBJ_ELF
10764 case BFD_RELOC_ARM_PLT32:
10765 #endif
10767 /* We are going to store value (shifted right by two) in the
10768 instruction, in a 24 bit, signed field. Bits 0 and 1 must be
10769 clear, and bits 26 through 32 either all clear or all set. */
10770 if (value & 0x00000003)
10771 as_bad_where (fixP->fx_file, fixP->fx_line,
10772 _("misaligned branch destination"));
10773 if ((value & (offsetT)0xfe000000) != (offsetT)0
10774 && (value & (offsetT)0xfe000000) != (offsetT)0xfe000000)
10775 as_bad_where (fixP->fx_file, fixP->fx_line,
10776 _("branch out of range"));
10778 if (fixP->fx_done || !seg->use_rela_p)
10780 newval = md_chars_to_number (buf, INSN_SIZE);
10781 newval |= (value >> 2) & 0x00ffffff;
10782 md_number_to_chars (buf, newval, INSN_SIZE);
10784 break;
10786 case BFD_RELOC_ARM_PCREL_BLX:
10787 /* BLX allows bit 1 to be set in the branch destination, since
10788 it targets a Thumb instruction which is only required to be
10789 aligned modulo 2. Other constraints are as for B/BL. */
10790 if (value & 0x00000001)
10791 as_bad_where (fixP->fx_file, fixP->fx_line,
10792 _("misaligned BLX destination"));
10793 if ((value & (offsetT)0xfe000000) != (offsetT)0
10794 && (value & (offsetT)0xfe000000) != (offsetT)0xfe000000)
10795 as_bad_where (fixP->fx_file, fixP->fx_line,
10796 _("branch out of range"));
10798 if (fixP->fx_done || !seg->use_rela_p)
10800 offsetT hbit;
10801 hbit = (value >> 1) & 1;
10802 value = (value >> 2) & 0x00ffffff;
10804 newval = md_chars_to_number (buf, INSN_SIZE);
10805 newval |= value | hbit << 24;
10806 md_number_to_chars (buf, newval, INSN_SIZE);
10808 break;
10810 case BFD_RELOC_THUMB_PCREL_BRANCH7: /* CZB */
10811 /* CZB can only branch forward. */
10812 if (value & ~0x7e)
10813 as_bad_where (fixP->fx_file, fixP->fx_line,
10814 _("branch out of range"));
10816 if (fixP->fx_done || !seg->use_rela_p)
10818 newval = md_chars_to_number (buf, THUMB_SIZE);
10819 newval |= ((value & 0x2e) << 2) | ((value & 0x40) << 3);
10820 md_number_to_chars (buf, newval, THUMB_SIZE);
10822 break;
10824 case BFD_RELOC_THUMB_PCREL_BRANCH9: /* Conditional branch. */
10825 if ((value & ~0xff) && ((value & ~0xff) != ~0xff))
10826 as_bad_where (fixP->fx_file, fixP->fx_line,
10827 _("branch out of range"));
10829 if (fixP->fx_done || !seg->use_rela_p)
10831 newval = md_chars_to_number (buf, THUMB_SIZE);
10832 newval |= (value & 0x1ff) >> 1;
10833 md_number_to_chars (buf, newval, THUMB_SIZE);
10835 break;
10837 case BFD_RELOC_THUMB_PCREL_BRANCH12: /* Unconditional branch. */
10838 if ((value & ~0x7ff) && ((value & ~0x7ff) != ~0x7ff))
10839 as_bad_where (fixP->fx_file, fixP->fx_line,
10840 _("branch out of range"));
10842 if (fixP->fx_done || !seg->use_rela_p)
10844 newval = md_chars_to_number (buf, THUMB_SIZE);
10845 newval |= (value & 0xfff) >> 1;
10846 md_number_to_chars (buf, newval, THUMB_SIZE);
10848 break;
10850 case BFD_RELOC_THUMB_PCREL_BRANCH20:
10851 if ((value & ~0x1fffff) && ((value & ~0x1fffff) != ~0x1fffff))
10852 as_bad_where (fixP->fx_file, fixP->fx_line,
10853 _("conditional branch out of range"));
10855 if (fixP->fx_done || !seg->use_rela_p)
10857 offsetT newval2;
10858 addressT S, J1, J2, lo, hi;
10860 S = (value & 0x00100000) >> 20;
10861 J2 = (value & 0x00080000) >> 19;
10862 J1 = (value & 0x00040000) >> 18;
10863 hi = (value & 0x0003f000) >> 12;
10864 lo = (value & 0x00000ffe) >> 1;
10866 newval = md_chars_to_number (buf, THUMB_SIZE);
10867 newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
10868 newval |= (S << 10) | hi;
10869 newval2 |= (J1 << 13) | (J2 << 11) | lo;
10870 md_number_to_chars (buf, newval, THUMB_SIZE);
10871 md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE);
10873 break;
10875 case BFD_RELOC_THUMB_PCREL_BLX:
10876 case BFD_RELOC_THUMB_PCREL_BRANCH23:
10877 if ((value & ~0x3fffff) && ((value & ~0x3fffff) != ~0x3fffff))
10878 as_bad_where (fixP->fx_file, fixP->fx_line,
10879 _("branch out of range"));
10881 if (fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BLX)
10882 /* For a BLX instruction, make sure that the relocation is rounded up
10883 to a word boundary. This follows the semantics of the instruction
10884 which specifies that bit 1 of the target address will come from bit
10885 1 of the base address. */
10886 value = (value + 1) & ~ 1;
10888 if (fixP->fx_done || !seg->use_rela_p)
10890 offsetT newval2;
10892 newval = md_chars_to_number (buf, THUMB_SIZE);
10893 newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
10894 newval |= (value & 0x7fffff) >> 12;
10895 newval2 |= (value & 0xfff) >> 1;
10896 md_number_to_chars (buf, newval, THUMB_SIZE);
10897 md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE);
10899 break;
10901 case BFD_RELOC_THUMB_PCREL_BRANCH25:
10902 if ((value & ~0x1ffffff) && ((value & ~0x1ffffff) != ~0x1ffffff))
10903 as_bad_where (fixP->fx_file, fixP->fx_line,
10904 _("branch out of range"));
10906 if (fixP->fx_done || !seg->use_rela_p)
10908 offsetT newval2;
10909 addressT S, I1, I2, lo, hi;
10911 S = (value & 0x01000000) >> 24;
10912 I1 = (value & 0x00800000) >> 23;
10913 I2 = (value & 0x00400000) >> 22;
10914 hi = (value & 0x003ff000) >> 12;
10915 lo = (value & 0x00000ffe) >> 1;
10917 I1 = !(I1 ^ S);
10918 I2 = !(I2 ^ S);
10920 newval = md_chars_to_number (buf, THUMB_SIZE);
10921 newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
10922 newval |= (S << 10) | hi;
10923 newval2 |= (I1 << 13) | (I2 << 11) | lo;
10924 md_number_to_chars (buf, newval, THUMB_SIZE);
10925 md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE);
10927 break;
10929 case BFD_RELOC_8:
10930 if (fixP->fx_done || !seg->use_rela_p)
10931 md_number_to_chars (buf, value, 1);
10932 break;
10934 case BFD_RELOC_16:
10935 if (fixP->fx_done || !seg->use_rela_p)
10936 md_number_to_chars (buf, value, 2);
10937 break;
10939 #ifdef OBJ_ELF
10940 case BFD_RELOC_ARM_TLS_GD32:
10941 case BFD_RELOC_ARM_TLS_LE32:
10942 case BFD_RELOC_ARM_TLS_IE32:
10943 case BFD_RELOC_ARM_TLS_LDM32:
10944 case BFD_RELOC_ARM_TLS_LDO32:
10945 S_SET_THREAD_LOCAL (fixP->fx_addsy);
10946 /* fall through */
10948 case BFD_RELOC_ARM_GOT32:
10949 case BFD_RELOC_ARM_GOTOFF:
10950 case BFD_RELOC_ARM_TARGET2:
10951 if (fixP->fx_done || !seg->use_rela_p)
10952 md_number_to_chars (buf, 0, 4);
10953 break;
10954 #endif
10956 case BFD_RELOC_RVA:
10957 case BFD_RELOC_32:
10958 case BFD_RELOC_ARM_TARGET1:
10959 case BFD_RELOC_ARM_ROSEGREL32:
10960 case BFD_RELOC_ARM_SBREL32:
10961 case BFD_RELOC_32_PCREL:
10962 if (fixP->fx_done || !seg->use_rela_p)
10963 md_number_to_chars (buf, value, 4);
10964 break;
10966 #ifdef OBJ_ELF
10967 case BFD_RELOC_ARM_PREL31:
10968 if (fixP->fx_done || !seg->use_rela_p)
10970 newval = md_chars_to_number (buf, 4) & 0x80000000;
10971 if ((value ^ (value >> 1)) & 0x40000000)
10973 as_bad_where (fixP->fx_file, fixP->fx_line,
10974 _("rel31 relocation overflow"));
10976 newval |= value & 0x7fffffff;
10977 md_number_to_chars (buf, newval, 4);
10979 break;
10980 #endif
10982 case BFD_RELOC_ARM_CP_OFF_IMM:
10983 if (value < -1023 || value > 1023 || (value & 3))
10984 as_bad_where (fixP->fx_file, fixP->fx_line,
10985 _("co-processor offset out of range"));
10986 cp_off_common:
10987 sign = value >= 0;
10988 if (value < 0)
10989 value = -value;
10990 newval = md_chars_to_number (buf, INSN_SIZE) & 0xff7fff00;
10991 newval |= (value >> 2) | (sign ? INDEX_UP : 0);
10992 if (value == 0)
10993 newval &= ~WRITE_BACK;
10994 md_number_to_chars (buf, newval, INSN_SIZE);
10995 break;
10997 case BFD_RELOC_ARM_CP_OFF_IMM_S2:
10998 if (value < -255 || value > 255)
10999 as_bad_where (fixP->fx_file, fixP->fx_line,
11000 _("co-processor offset out of range"));
11001 goto cp_off_common;
11003 case BFD_RELOC_ARM_THUMB_OFFSET:
11004 newval = md_chars_to_number (buf, THUMB_SIZE);
11005 /* Exactly what ranges, and where the offset is inserted depends
11006 on the type of instruction, we can establish this from the
11007 top 4 bits. */
11008 switch (newval >> 12)
11010 case 4: /* PC load. */
11011 /* Thumb PC loads are somewhat odd, bit 1 of the PC is
11012 forced to zero for these loads; md_pcrel_from has already
11013 compensated for this. */
11014 if (value & 3)
11015 as_bad_where (fixP->fx_file, fixP->fx_line,
11016 _("invalid offset, target not word aligned (0x%08lX)"),
11017 (((unsigned int) fixP->fx_frag->fr_address
11018 + (unsigned int) fixP->fx_where) & ~3) + value);
11020 if (value & ~0x3fc)
11021 as_bad_where (fixP->fx_file, fixP->fx_line,
11022 _("invalid offset, value too big (0x%08lX)"),
11023 (long) value);
11025 newval |= value >> 2;
11026 break;
11028 case 9: /* SP load/store. */
11029 if (value & ~0x3fc)
11030 as_bad_where (fixP->fx_file, fixP->fx_line,
11031 _("invalid offset, value too big (0x%08lX)"),
11032 (long) value);
11033 newval |= value >> 2;
11034 break;
11036 case 6: /* Word load/store. */
11037 if (value & ~0x7c)
11038 as_bad_where (fixP->fx_file, fixP->fx_line,
11039 _("invalid offset, value too big (0x%08lX)"),
11040 (long) value);
11041 newval |= value << 4; /* 6 - 2. */
11042 break;
11044 case 7: /* Byte load/store. */
11045 if (value & ~0x1f)
11046 as_bad_where (fixP->fx_file, fixP->fx_line,
11047 _("invalid offset, value too big (0x%08lX)"),
11048 (long) value);
11049 newval |= value << 6;
11050 break;
11052 case 8: /* Halfword load/store. */
11053 if (value & ~0x3e)
11054 as_bad_where (fixP->fx_file, fixP->fx_line,
11055 _("invalid offset, value too big (0x%08lX)"),
11056 (long) value);
11057 newval |= value << 5; /* 6 - 1. */
11058 break;
11060 default:
11061 as_bad_where (fixP->fx_file, fixP->fx_line,
11062 "Unable to process relocation for thumb opcode: %lx",
11063 (unsigned long) newval);
11064 break;
11066 md_number_to_chars (buf, newval, THUMB_SIZE);
11067 break;
11069 case BFD_RELOC_ARM_THUMB_ADD:
11070 /* This is a complicated relocation, since we use it for all of
11071 the following immediate relocations:
11073 3bit ADD/SUB
11074 8bit ADD/SUB
11075 9bit ADD/SUB SP word-aligned
11076 10bit ADD PC/SP word-aligned
11078 The type of instruction being processed is encoded in the
11079 instruction field:
11081 0x8000 SUB
11082 0x00F0 Rd
11083 0x000F Rs
11085 newval = md_chars_to_number (buf, THUMB_SIZE);
11087 int rd = (newval >> 4) & 0xf;
11088 int rs = newval & 0xf;
11089 int subtract = !!(newval & 0x8000);
11091 /* Check for HI regs, only very restricted cases allowed:
11092 Adjusting SP, and using PC or SP to get an address. */
11093 if ((rd > 7 && (rd != REG_SP || rs != REG_SP))
11094 || (rs > 7 && rs != REG_SP && rs != REG_PC))
11095 as_bad_where (fixP->fx_file, fixP->fx_line,
11096 _("invalid Hi register with immediate"));
11098 /* If value is negative, choose the opposite instruction. */
11099 if (value < 0)
11101 value = -value;
11102 subtract = !subtract;
11103 if (value < 0)
11104 as_bad_where (fixP->fx_file, fixP->fx_line,
11105 _("immediate value out of range"));
11108 if (rd == REG_SP)
11110 if (value & ~0x1fc)
11111 as_bad_where (fixP->fx_file, fixP->fx_line,
11112 _("invalid immediate for stack address calculation"));
11113 newval = subtract ? T_OPCODE_SUB_ST : T_OPCODE_ADD_ST;
11114 newval |= value >> 2;
11116 else if (rs == REG_PC || rs == REG_SP)
11118 if (subtract || value & ~0x3fc)
11119 as_bad_where (fixP->fx_file, fixP->fx_line,
11120 _("invalid immediate for address calculation (value = 0x%08lX)"),
11121 (unsigned long) value);
11122 newval = (rs == REG_PC ? T_OPCODE_ADD_PC : T_OPCODE_ADD_SP);
11123 newval |= rd << 8;
11124 newval |= value >> 2;
11126 else if (rs == rd)
11128 if (value & ~0xff)
11129 as_bad_where (fixP->fx_file, fixP->fx_line,
11130 _("immediate value out of range"));
11131 newval = subtract ? T_OPCODE_SUB_I8 : T_OPCODE_ADD_I8;
11132 newval |= (rd << 8) | value;
11134 else
11136 if (value & ~0x7)
11137 as_bad_where (fixP->fx_file, fixP->fx_line,
11138 _("immediate value out of range"));
11139 newval = subtract ? T_OPCODE_SUB_I3 : T_OPCODE_ADD_I3;
11140 newval |= rd | (rs << 3) | (value << 6);
11143 md_number_to_chars (buf, newval, THUMB_SIZE);
11144 break;
11146 case BFD_RELOC_ARM_THUMB_IMM:
11147 newval = md_chars_to_number (buf, THUMB_SIZE);
11148 if (value < 0 || value > 255)
11149 as_bad_where (fixP->fx_file, fixP->fx_line,
11150 _("invalid immediate: %ld is too large"),
11151 (long) value);
11152 newval |= value;
11153 md_number_to_chars (buf, newval, THUMB_SIZE);
11154 break;
11156 case BFD_RELOC_ARM_THUMB_SHIFT:
11157 /* 5bit shift value (0..32). LSL cannot take 32. */
11158 newval = md_chars_to_number (buf, THUMB_SIZE) & 0xf83f;
11159 temp = newval & 0xf800;
11160 if (value < 0 || value > 32 || (value == 32 && temp == T_OPCODE_LSL_I))
11161 as_bad_where (fixP->fx_file, fixP->fx_line,
11162 _("invalid shift value: %ld"), (long) value);
11163 /* Shifts of zero must be encoded as LSL. */
11164 if (value == 0)
11165 newval = (newval & 0x003f) | T_OPCODE_LSL_I;
11166 /* Shifts of 32 are encoded as zero. */
11167 else if (value == 32)
11168 value = 0;
11169 newval |= value << 6;
11170 md_number_to_chars (buf, newval, THUMB_SIZE);
11171 break;
11173 case BFD_RELOC_VTABLE_INHERIT:
11174 case BFD_RELOC_VTABLE_ENTRY:
11175 fixP->fx_done = 0;
11176 return;
11178 case BFD_RELOC_UNUSED:
11179 default:
11180 as_bad_where (fixP->fx_file, fixP->fx_line,
11181 _("bad relocation fixup type (%d)"), fixP->fx_r_type);
11185 /* Translate internal representation of relocation info to BFD target
11186 format. */
11188 arelent *
11189 tc_gen_reloc (asection * section ATTRIBUTE_UNUSED,
11190 fixS * fixp)
11192 arelent * reloc;
11193 bfd_reloc_code_real_type code;
11195 reloc = xmalloc (sizeof (arelent));
11197 reloc->sym_ptr_ptr = xmalloc (sizeof (asymbol *));
11198 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
11199 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
11201 if (fixp->fx_pcrel)
11202 fixp->fx_offset = reloc->address;
11203 reloc->addend = fixp->fx_offset;
11205 switch (fixp->fx_r_type)
11207 case BFD_RELOC_8:
11208 if (fixp->fx_pcrel)
11210 code = BFD_RELOC_8_PCREL;
11211 break;
11214 case BFD_RELOC_16:
11215 if (fixp->fx_pcrel)
11217 code = BFD_RELOC_16_PCREL;
11218 break;
11221 case BFD_RELOC_32:
11222 if (fixp->fx_pcrel)
11224 code = BFD_RELOC_32_PCREL;
11225 break;
11228 case BFD_RELOC_NONE:
11229 case BFD_RELOC_ARM_PCREL_BRANCH:
11230 case BFD_RELOC_ARM_PCREL_BLX:
11231 case BFD_RELOC_RVA:
11232 case BFD_RELOC_THUMB_PCREL_BRANCH7:
11233 case BFD_RELOC_THUMB_PCREL_BRANCH9:
11234 case BFD_RELOC_THUMB_PCREL_BRANCH12:
11235 case BFD_RELOC_THUMB_PCREL_BRANCH20:
11236 case BFD_RELOC_THUMB_PCREL_BRANCH23:
11237 case BFD_RELOC_THUMB_PCREL_BRANCH25:
11238 case BFD_RELOC_THUMB_PCREL_BLX:
11239 case BFD_RELOC_VTABLE_ENTRY:
11240 case BFD_RELOC_VTABLE_INHERIT:
11241 code = fixp->fx_r_type;
11242 break;
11244 case BFD_RELOC_ARM_LITERAL:
11245 case BFD_RELOC_ARM_HWLITERAL:
11246 /* If this is called then the a literal has
11247 been referenced across a section boundary. */
11248 as_bad_where (fixp->fx_file, fixp->fx_line,
11249 _("literal referenced across section boundary"));
11250 return NULL;
11252 #ifdef OBJ_ELF
11253 case BFD_RELOC_ARM_GOT32:
11254 case BFD_RELOC_ARM_GOTOFF:
11255 case BFD_RELOC_ARM_PLT32:
11256 case BFD_RELOC_ARM_TARGET1:
11257 case BFD_RELOC_ARM_ROSEGREL32:
11258 case BFD_RELOC_ARM_SBREL32:
11259 case BFD_RELOC_ARM_PREL31:
11260 case BFD_RELOC_ARM_TARGET2:
11261 case BFD_RELOC_ARM_TLS_LE32:
11262 case BFD_RELOC_ARM_TLS_LDO32:
11263 code = fixp->fx_r_type;
11264 break;
11266 case BFD_RELOC_ARM_TLS_GD32:
11267 case BFD_RELOC_ARM_TLS_IE32:
11268 case BFD_RELOC_ARM_TLS_LDM32:
11269 /* BFD will include the symbol's address in the addend.
11270 But we don't want that, so subtract it out again here. */
11271 if (!S_IS_COMMON (fixp->fx_addsy))
11272 reloc->addend -= (*reloc->sym_ptr_ptr)->value;
11273 code = fixp->fx_r_type;
11274 break;
11275 #endif
11277 case BFD_RELOC_ARM_IMMEDIATE:
11278 as_bad_where (fixp->fx_file, fixp->fx_line,
11279 _("internal relocation (type: IMMEDIATE) not fixed up"));
11280 return NULL;
11282 case BFD_RELOC_ARM_ADRL_IMMEDIATE:
11283 as_bad_where (fixp->fx_file, fixp->fx_line,
11284 _("ADRL used for a symbol not defined in the same file"));
11285 return NULL;
11287 case BFD_RELOC_ARM_OFFSET_IMM:
11288 if (fixp->fx_addsy != NULL
11289 && !S_IS_DEFINED (fixp->fx_addsy)
11290 && S_IS_LOCAL (fixp->fx_addsy))
11292 as_bad_where (fixp->fx_file, fixp->fx_line,
11293 _("undefined local label `%s'"),
11294 S_GET_NAME (fixp->fx_addsy));
11295 return NULL;
11298 as_bad_where (fixp->fx_file, fixp->fx_line,
11299 _("internal_relocation (type: OFFSET_IMM) not fixed up"));
11300 return NULL;
11302 default:
11304 char * type;
11306 switch (fixp->fx_r_type)
11308 case BFD_RELOC_NONE: type = "NONE"; break;
11309 case BFD_RELOC_ARM_OFFSET_IMM8: type = "OFFSET_IMM8"; break;
11310 case BFD_RELOC_ARM_SHIFT_IMM: type = "SHIFT_IMM"; break;
11311 case BFD_RELOC_ARM_SMI: type = "SMI"; break;
11312 case BFD_RELOC_ARM_SWI: type = "SWI"; break;
11313 case BFD_RELOC_ARM_MULTI: type = "MULTI"; break;
11314 case BFD_RELOC_ARM_CP_OFF_IMM: type = "CP_OFF_IMM"; break;
11315 case BFD_RELOC_ARM_THUMB_ADD: type = "THUMB_ADD"; break;
11316 case BFD_RELOC_ARM_THUMB_SHIFT: type = "THUMB_SHIFT"; break;
11317 case BFD_RELOC_ARM_THUMB_IMM: type = "THUMB_IMM"; break;
11318 case BFD_RELOC_ARM_THUMB_OFFSET: type = "THUMB_OFFSET"; break;
11319 default: type = _("<unknown>"); break;
11321 as_bad_where (fixp->fx_file, fixp->fx_line,
11322 _("cannot represent %s relocation in this object file format"),
11323 type);
11324 return NULL;
11328 #ifdef OBJ_ELF
11329 if ((code == BFD_RELOC_32_PCREL || code == BFD_RELOC_32)
11330 && GOT_symbol
11331 && fixp->fx_addsy == GOT_symbol)
11333 code = BFD_RELOC_ARM_GOTPC;
11334 reloc->addend = fixp->fx_offset = reloc->address;
11336 #endif
11338 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
11340 if (reloc->howto == NULL)
11342 as_bad_where (fixp->fx_file, fixp->fx_line,
11343 _("cannot represent %s relocation in this object file format"),
11344 bfd_get_reloc_code_name (code));
11345 return NULL;
11348 /* HACK: Since arm ELF uses Rel instead of Rela, encode the
11349 vtable entry to be used in the relocation's section offset. */
11350 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
11351 reloc->address = fixp->fx_offset;
11353 return reloc;
11356 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
11358 void
11359 cons_fix_new_arm (fragS * frag,
11360 int where,
11361 int size,
11362 expressionS * exp)
11364 bfd_reloc_code_real_type type;
11365 int pcrel = 0;
11367 /* Pick a reloc.
11368 FIXME: @@ Should look at CPU word size. */
11369 switch (size)
11371 case 1:
11372 type = BFD_RELOC_8;
11373 break;
11374 case 2:
11375 type = BFD_RELOC_16;
11376 break;
11377 case 4:
11378 default:
11379 type = BFD_RELOC_32;
11380 break;
11381 case 8:
11382 type = BFD_RELOC_64;
11383 break;
11386 fix_new_exp (frag, where, (int) size, exp, pcrel, type);
11389 #if defined OBJ_COFF || defined OBJ_ELF
11390 void
11391 arm_validate_fix (fixS * fixP)
11393 /* If the destination of the branch is a defined symbol which does not have
11394 the THUMB_FUNC attribute, then we must be calling a function which has
11395 the (interfacearm) attribute. We look for the Thumb entry point to that
11396 function and change the branch to refer to that function instead. */
11397 if (fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BRANCH23
11398 && fixP->fx_addsy != NULL
11399 && S_IS_DEFINED (fixP->fx_addsy)
11400 && ! THUMB_IS_FUNC (fixP->fx_addsy))
11402 fixP->fx_addsy = find_real_start (fixP->fx_addsy);
11405 #endif
11408 arm_force_relocation (struct fix * fixp)
11410 #if defined (OBJ_COFF) && defined (TE_PE)
11411 if (fixp->fx_r_type == BFD_RELOC_RVA)
11412 return 1;
11413 #endif
11415 /* Resolve these relocations even if the symbol is extern or weak. */
11416 if (fixp->fx_r_type == BFD_RELOC_ARM_IMMEDIATE
11417 || fixp->fx_r_type == BFD_RELOC_ARM_OFFSET_IMM
11418 || fixp->fx_r_type == BFD_RELOC_ARM_ADRL_IMMEDIATE)
11419 return 0;
11421 return generic_force_reloc (fixp);
11424 #ifdef OBJ_COFF
11425 /* This is a little hack to help the gas/arm/adrl.s test. It prevents
11426 local labels from being added to the output symbol table when they
11427 are used with the ADRL pseudo op. The ADRL relocation should always
11428 be resolved before the binbary is emitted, so it is safe to say that
11429 it is adjustable. */
11431 bfd_boolean
11432 arm_fix_adjustable (fixS * fixP)
11434 if (fixP->fx_r_type == BFD_RELOC_ARM_ADRL_IMMEDIATE)
11435 return 1;
11436 return 0;
11438 #endif
11440 #ifdef OBJ_ELF
11441 /* Relocations against Thumb function names must be left unadjusted,
11442 so that the linker can use this information to correctly set the
11443 bottom bit of their addresses. The MIPS version of this function
11444 also prevents relocations that are mips-16 specific, but I do not
11445 know why it does this.
11447 FIXME:
11448 There is one other problem that ought to be addressed here, but
11449 which currently is not: Taking the address of a label (rather
11450 than a function) and then later jumping to that address. Such
11451 addresses also ought to have their bottom bit set (assuming that
11452 they reside in Thumb code), but at the moment they will not. */
11454 bfd_boolean
11455 arm_fix_adjustable (fixS * fixP)
11457 if (fixP->fx_addsy == NULL)
11458 return 1;
11460 if (THUMB_IS_FUNC (fixP->fx_addsy)
11461 && fixP->fx_subsy == NULL)
11462 return 0;
11464 /* We need the symbol name for the VTABLE entries. */
11465 if ( fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
11466 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
11467 return 0;
11469 /* Don't allow symbols to be discarded on GOT related relocs. */
11470 if (fixP->fx_r_type == BFD_RELOC_ARM_PLT32
11471 || fixP->fx_r_type == BFD_RELOC_ARM_GOT32
11472 || fixP->fx_r_type == BFD_RELOC_ARM_GOTOFF
11473 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_GD32
11474 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LE32
11475 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_IE32
11476 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LDM32
11477 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LDO32
11478 || fixP->fx_r_type == BFD_RELOC_ARM_TARGET2)
11479 return 0;
11481 return 1;
11484 const char *
11485 elf32_arm_target_format (void)
11487 #ifdef TE_SYMBIAN
11488 return (target_big_endian
11489 ? "elf32-bigarm-symbian"
11490 : "elf32-littlearm-symbian");
11491 #elif defined (TE_VXWORKS)
11492 return (target_big_endian
11493 ? "elf32-bigarm-vxworks"
11494 : "elf32-littlearm-vxworks");
11495 #else
11496 if (target_big_endian)
11497 return "elf32-bigarm";
11498 else
11499 return "elf32-littlearm";
11500 #endif
11503 void
11504 armelf_frob_symbol (symbolS * symp,
11505 int * puntp)
11507 elf_frob_symbol (symp, puntp);
11509 #endif
11511 /* MD interface: Finalization. */
11513 /* A good place to do this, although this was probably not intended
11514 for this kind of use. We need to dump the literal pool before
11515 references are made to a null symbol pointer. */
11517 void
11518 arm_cleanup (void)
11520 literal_pool * pool;
11522 for (pool = list_of_pools; pool; pool = pool->next)
11524 /* Put it at the end of the relevent section. */
11525 subseg_set (pool->section, pool->sub_section);
11526 #ifdef OBJ_ELF
11527 arm_elf_change_section ();
11528 #endif
11529 s_ltorg (0);
11533 /* Adjust the symbol table. This marks Thumb symbols as distinct from
11534 ARM ones. */
11536 void
11537 arm_adjust_symtab (void)
11539 #ifdef OBJ_COFF
11540 symbolS * sym;
11542 for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym))
11544 if (ARM_IS_THUMB (sym))
11546 if (THUMB_IS_FUNC (sym))
11548 /* Mark the symbol as a Thumb function. */
11549 if ( S_GET_STORAGE_CLASS (sym) == C_STAT
11550 || S_GET_STORAGE_CLASS (sym) == C_LABEL) /* This can happen! */
11551 S_SET_STORAGE_CLASS (sym, C_THUMBSTATFUNC);
11553 else if (S_GET_STORAGE_CLASS (sym) == C_EXT)
11554 S_SET_STORAGE_CLASS (sym, C_THUMBEXTFUNC);
11555 else
11556 as_bad (_("%s: unexpected function type: %d"),
11557 S_GET_NAME (sym), S_GET_STORAGE_CLASS (sym));
11559 else switch (S_GET_STORAGE_CLASS (sym))
11561 case C_EXT:
11562 S_SET_STORAGE_CLASS (sym, C_THUMBEXT);
11563 break;
11564 case C_STAT:
11565 S_SET_STORAGE_CLASS (sym, C_THUMBSTAT);
11566 break;
11567 case C_LABEL:
11568 S_SET_STORAGE_CLASS (sym, C_THUMBLABEL);
11569 break;
11570 default:
11571 /* Do nothing. */
11572 break;
11576 if (ARM_IS_INTERWORK (sym))
11577 coffsymbol (symbol_get_bfdsym (sym))->native->u.syment.n_flags = 0xFF;
11579 #endif
11580 #ifdef OBJ_ELF
11581 symbolS * sym;
11582 char bind;
11584 for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym))
11586 if (ARM_IS_THUMB (sym))
11588 elf_symbol_type * elf_sym;
11590 elf_sym = elf_symbol (symbol_get_bfdsym (sym));
11591 bind = ELF_ST_BIND (elf_sym->internal_elf_sym.st_info);
11593 if (! bfd_is_arm_mapping_symbol_name (elf_sym->symbol.name))
11595 /* If it's a .thumb_func, declare it as so,
11596 otherwise tag label as .code 16. */
11597 if (THUMB_IS_FUNC (sym))
11598 elf_sym->internal_elf_sym.st_info =
11599 ELF_ST_INFO (bind, STT_ARM_TFUNC);
11600 else
11601 elf_sym->internal_elf_sym.st_info =
11602 ELF_ST_INFO (bind, STT_ARM_16BIT);
11606 #endif
11609 /* MD interface: Initialization. */
11611 static void
11612 set_constant_flonums (void)
11614 int i;
11616 for (i = 0; i < NUM_FLOAT_VALS; i++)
11617 if (atof_ieee ((char *) fp_const[i], 'x', fp_values[i]) == NULL)
11618 abort ();
11621 void
11622 md_begin (void)
11624 unsigned mach;
11625 unsigned int i;
11627 if ( (arm_ops_hsh = hash_new ()) == NULL
11628 || (arm_cond_hsh = hash_new ()) == NULL
11629 || (arm_shift_hsh = hash_new ()) == NULL
11630 || (arm_psr_hsh = hash_new ()) == NULL
11631 || (arm_reg_hsh = hash_new ()) == NULL
11632 || (arm_reloc_hsh = hash_new ()) == NULL)
11633 as_fatal (_("virtual memory exhausted"));
11635 for (i = 0; i < sizeof (insns) / sizeof (struct asm_opcode); i++)
11636 hash_insert (arm_ops_hsh, insns[i].template, (PTR) (insns + i));
11637 for (i = 0; i < sizeof (conds) / sizeof (struct asm_cond); i++)
11638 hash_insert (arm_cond_hsh, conds[i].template, (PTR) (conds + i));
11639 for (i = 0; i < sizeof (shift_names) / sizeof (struct asm_shift_name); i++)
11640 hash_insert (arm_shift_hsh, shift_names[i].name, (PTR) (shift_names + i));
11641 for (i = 0; i < sizeof (psrs) / sizeof (struct asm_psr); i++)
11642 hash_insert (arm_psr_hsh, psrs[i].template, (PTR) (psrs + i));
11643 for (i = 0; i < sizeof (reg_names) / sizeof (struct reg_entry); i++)
11644 hash_insert (arm_reg_hsh, reg_names[i].name, (PTR) (reg_names + i));
11645 #ifdef OBJ_ELF
11646 for (i = 0; i < sizeof (reloc_names) / sizeof (struct reloc_entry); i++)
11647 hash_insert (arm_reloc_hsh, reloc_names[i].name, (PTR) (reloc_names + i));
11648 #endif
11650 set_constant_flonums ();
11652 /* Set the cpu variant based on the command-line options. We prefer
11653 -mcpu= over -march= if both are set (as for GCC); and we prefer
11654 -mfpu= over any other way of setting the floating point unit.
11655 Use of legacy options with new options are faulted. */
11656 if (legacy_cpu != -1)
11658 if (mcpu_cpu_opt != -1 || march_cpu_opt != -1)
11659 as_bad (_("use of old and new-style options to set CPU type"));
11661 mcpu_cpu_opt = legacy_cpu;
11663 else if (mcpu_cpu_opt == -1)
11664 mcpu_cpu_opt = march_cpu_opt;
11666 if (legacy_fpu != -1)
11668 if (mfpu_opt != -1)
11669 as_bad (_("use of old and new-style options to set FPU type"));
11671 mfpu_opt = legacy_fpu;
11673 else if (mfpu_opt == -1)
11675 #if !(defined (TE_LINUX) || defined (TE_NetBSD) || defined (TE_VXWORKS))
11676 /* Some environments specify a default FPU. If they don't, infer it
11677 from the processor. */
11678 if (mcpu_fpu_opt != -1)
11679 mfpu_opt = mcpu_fpu_opt;
11680 else
11681 mfpu_opt = march_fpu_opt;
11682 #else
11683 mfpu_opt = FPU_DEFAULT;
11684 #endif
11687 if (mfpu_opt == -1)
11689 if (mcpu_cpu_opt == -1)
11690 mfpu_opt = FPU_DEFAULT;
11691 else if (mcpu_cpu_opt & ARM_EXT_V5)
11692 mfpu_opt = FPU_ARCH_VFP_V2;
11693 else
11694 mfpu_opt = FPU_ARCH_FPA;
11697 if (mcpu_cpu_opt == -1)
11698 mcpu_cpu_opt = CPU_DEFAULT;
11700 cpu_variant = mcpu_cpu_opt | mfpu_opt;
11702 #if defined OBJ_COFF || defined OBJ_ELF
11704 unsigned int flags = 0;
11706 #if defined OBJ_ELF
11707 flags = meabi_flags;
11709 switch (meabi_flags)
11711 case EF_ARM_EABI_UNKNOWN:
11712 #endif
11713 /* Set the flags in the private structure. */
11714 if (uses_apcs_26) flags |= F_APCS26;
11715 if (support_interwork) flags |= F_INTERWORK;
11716 if (uses_apcs_float) flags |= F_APCS_FLOAT;
11717 if (pic_code) flags |= F_PIC;
11718 if ((cpu_variant & FPU_ANY) == FPU_NONE
11719 || (cpu_variant & FPU_ANY) == FPU_ARCH_VFP) /* VFP layout only. */
11720 flags |= F_SOFT_FLOAT;
11722 switch (mfloat_abi_opt)
11724 case ARM_FLOAT_ABI_SOFT:
11725 case ARM_FLOAT_ABI_SOFTFP:
11726 flags |= F_SOFT_FLOAT;
11727 break;
11729 case ARM_FLOAT_ABI_HARD:
11730 if (flags & F_SOFT_FLOAT)
11731 as_bad (_("hard-float conflicts with specified fpu"));
11732 break;
11735 /* Using VFP conventions (even if soft-float). */
11736 if (cpu_variant & FPU_VFP_EXT_NONE)
11737 flags |= F_VFP_FLOAT;
11739 #if defined OBJ_ELF
11740 if (cpu_variant & FPU_ARCH_MAVERICK)
11741 flags |= EF_ARM_MAVERICK_FLOAT;
11742 break;
11744 case EF_ARM_EABI_VER4:
11745 /* No additional flags to set. */
11746 break;
11748 default:
11749 abort ();
11751 #endif
11752 bfd_set_private_flags (stdoutput, flags);
11754 /* We have run out flags in the COFF header to encode the
11755 status of ATPCS support, so instead we create a dummy,
11756 empty, debug section called .arm.atpcs. */
11757 if (atpcs)
11759 asection * sec;
11761 sec = bfd_make_section (stdoutput, ".arm.atpcs");
11763 if (sec != NULL)
11765 bfd_set_section_flags
11766 (stdoutput, sec, SEC_READONLY | SEC_DEBUGGING /* | SEC_HAS_CONTENTS */);
11767 bfd_set_section_size (stdoutput, sec, 0);
11768 bfd_set_section_contents (stdoutput, sec, NULL, 0, 0);
11772 #endif
11774 /* Record the CPU type as well. */
11775 switch (cpu_variant & ARM_CPU_MASK)
11777 case ARM_2:
11778 mach = bfd_mach_arm_2;
11779 break;
11781 case ARM_3: /* Also ARM_250. */
11782 mach = bfd_mach_arm_2a;
11783 break;
11785 case ARM_6: /* Also ARM_7. */
11786 mach = bfd_mach_arm_3;
11787 break;
11789 default:
11790 mach = bfd_mach_arm_unknown;
11791 break;
11794 /* Catch special cases. */
11795 if (cpu_variant & ARM_CEXT_IWMMXT)
11796 mach = bfd_mach_arm_iWMMXt;
11797 else if (cpu_variant & ARM_CEXT_XSCALE)
11798 mach = bfd_mach_arm_XScale;
11799 else if (cpu_variant & ARM_CEXT_MAVERICK)
11800 mach = bfd_mach_arm_ep9312;
11801 else if (cpu_variant & ARM_EXT_V5E)
11802 mach = bfd_mach_arm_5TE;
11803 else if (cpu_variant & ARM_EXT_V5)
11805 if (cpu_variant & ARM_EXT_V4T)
11806 mach = bfd_mach_arm_5T;
11807 else
11808 mach = bfd_mach_arm_5;
11810 else if (cpu_variant & ARM_EXT_V4)
11812 if (cpu_variant & ARM_EXT_V4T)
11813 mach = bfd_mach_arm_4T;
11814 else
11815 mach = bfd_mach_arm_4;
11817 else if (cpu_variant & ARM_EXT_V3M)
11818 mach = bfd_mach_arm_3M;
11820 bfd_set_arch_mach (stdoutput, TARGET_ARCH, mach);
11823 /* Command line processing. */
11825 /* md_parse_option
11826 Invocation line includes a switch not recognized by the base assembler.
11827 See if it's a processor-specific option.
11829 This routine is somewhat complicated by the need for backwards
11830 compatibility (since older releases of gcc can't be changed).
11831 The new options try to make the interface as compatible as
11832 possible with GCC.
11834 New options (supported) are:
11836 -mcpu=<cpu name> Assemble for selected processor
11837 -march=<architecture name> Assemble for selected architecture
11838 -mfpu=<fpu architecture> Assemble for selected FPU.
11839 -EB/-mbig-endian Big-endian
11840 -EL/-mlittle-endian Little-endian
11841 -k Generate PIC code
11842 -mthumb Start in Thumb mode
11843 -mthumb-interwork Code supports ARM/Thumb interworking
11845 For now we will also provide support for:
11847 -mapcs-32 32-bit Program counter
11848 -mapcs-26 26-bit Program counter
11849 -macps-float Floats passed in FP registers
11850 -mapcs-reentrant Reentrant code
11851 -matpcs
11852 (sometime these will probably be replaced with -mapcs=<list of options>
11853 and -matpcs=<list of options>)
11855 The remaining options are only supported for back-wards compatibility.
11856 Cpu variants, the arm part is optional:
11857 -m[arm]1 Currently not supported.
11858 -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor
11859 -m[arm]3 Arm 3 processor
11860 -m[arm]6[xx], Arm 6 processors
11861 -m[arm]7[xx][t][[d]m] Arm 7 processors
11862 -m[arm]8[10] Arm 8 processors
11863 -m[arm]9[20][tdmi] Arm 9 processors
11864 -mstrongarm[110[0]] StrongARM processors
11865 -mxscale XScale processors
11866 -m[arm]v[2345[t[e]]] Arm architectures
11867 -mall All (except the ARM1)
11868 FP variants:
11869 -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions
11870 -mfpe-old (No float load/store multiples)
11871 -mvfpxd VFP Single precision
11872 -mvfp All VFP
11873 -mno-fpu Disable all floating point instructions
11875 The following CPU names are recognized:
11876 arm1, arm2, arm250, arm3, arm6, arm600, arm610, arm620,
11877 arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700,
11878 arm700i, arm710 arm710t, arm720, arm720t, arm740t, arm710c,
11879 arm7100, arm7500, arm7500fe, arm7tdmi, arm8, arm810, arm9,
11880 arm920, arm920t, arm940t, arm946, arm966, arm9tdmi, arm9e,
11881 arm10t arm10e, arm1020t, arm1020e, arm10200e,
11882 strongarm, strongarm110, strongarm1100, strongarm1110, xscale.
11886 const char * md_shortopts = "m:k";
11888 #ifdef ARM_BI_ENDIAN
11889 #define OPTION_EB (OPTION_MD_BASE + 0)
11890 #define OPTION_EL (OPTION_MD_BASE + 1)
11891 #else
11892 #if TARGET_BYTES_BIG_ENDIAN
11893 #define OPTION_EB (OPTION_MD_BASE + 0)
11894 #else
11895 #define OPTION_EL (OPTION_MD_BASE + 1)
11896 #endif
11897 #endif
11899 struct option md_longopts[] =
11901 #ifdef OPTION_EB
11902 {"EB", no_argument, NULL, OPTION_EB},
11903 #endif
11904 #ifdef OPTION_EL
11905 {"EL", no_argument, NULL, OPTION_EL},
11906 #endif
11907 {NULL, no_argument, NULL, 0}
11910 size_t md_longopts_size = sizeof (md_longopts);
11912 struct arm_option_table
11914 char *option; /* Option name to match. */
11915 char *help; /* Help information. */
11916 int *var; /* Variable to change. */
11917 int value; /* What to change it to. */
11918 char *deprecated; /* If non-null, print this message. */
11921 struct arm_option_table arm_opts[] =
11923 {"k", N_("generate PIC code"), &pic_code, 1, NULL},
11924 {"mthumb", N_("assemble Thumb code"), &thumb_mode, 1, NULL},
11925 {"mthumb-interwork", N_("support ARM/Thumb interworking"),
11926 &support_interwork, 1, NULL},
11927 {"mapcs-32", N_("code uses 32-bit program counter"), &uses_apcs_26, 0, NULL},
11928 {"mapcs-26", N_("code uses 26-bit program counter"), &uses_apcs_26, 1, NULL},
11929 {"mapcs-float", N_("floating point args are in fp regs"), &uses_apcs_float,
11930 1, NULL},
11931 {"mapcs-reentrant", N_("re-entrant code"), &pic_code, 1, NULL},
11932 {"matpcs", N_("code is ATPCS conformant"), &atpcs, 1, NULL},
11933 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian, 1, NULL},
11934 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian, 0,
11935 NULL},
11937 /* These are recognized by the assembler, but have no affect on code. */
11938 {"mapcs-frame", N_("use frame pointer"), NULL, 0, NULL},
11939 {"mapcs-stack-check", N_("use stack size checking"), NULL, 0, NULL},
11941 /* DON'T add any new processors to this list -- we want the whole list
11942 to go away... Add them to the processors table instead. */
11943 {"marm1", NULL, &legacy_cpu, ARM_ARCH_V1, N_("use -mcpu=arm1")},
11944 {"m1", NULL, &legacy_cpu, ARM_ARCH_V1, N_("use -mcpu=arm1")},
11945 {"marm2", NULL, &legacy_cpu, ARM_ARCH_V2, N_("use -mcpu=arm2")},
11946 {"m2", NULL, &legacy_cpu, ARM_ARCH_V2, N_("use -mcpu=arm2")},
11947 {"marm250", NULL, &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm250")},
11948 {"m250", NULL, &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm250")},
11949 {"marm3", NULL, &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm3")},
11950 {"m3", NULL, &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm3")},
11951 {"marm6", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm6")},
11952 {"m6", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm6")},
11953 {"marm600", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm600")},
11954 {"m600", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm600")},
11955 {"marm610", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm610")},
11956 {"m610", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm610")},
11957 {"marm620", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm620")},
11958 {"m620", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm620")},
11959 {"marm7", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7")},
11960 {"m7", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7")},
11961 {"marm70", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm70")},
11962 {"m70", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm70")},
11963 {"marm700", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700")},
11964 {"m700", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700")},
11965 {"marm700i", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700i")},
11966 {"m700i", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700i")},
11967 {"marm710", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710")},
11968 {"m710", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710")},
11969 {"marm710c", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710c")},
11970 {"m710c", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710c")},
11971 {"marm720", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm720")},
11972 {"m720", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm720")},
11973 {"marm7d", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7d")},
11974 {"m7d", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7d")},
11975 {"marm7di", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7di")},
11976 {"m7di", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7di")},
11977 {"marm7m", NULL, &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7m")},
11978 {"m7m", NULL, &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7m")},
11979 {"marm7dm", NULL, &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dm")},
11980 {"m7dm", NULL, &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dm")},
11981 {"marm7dmi", NULL, &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dmi")},
11982 {"m7dmi", NULL, &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dmi")},
11983 {"marm7100", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7100")},
11984 {"m7100", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7100")},
11985 {"marm7500", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500")},
11986 {"m7500", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500")},
11987 {"marm7500fe", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500fe")},
11988 {"m7500fe", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500fe")},
11989 {"marm7t", NULL, &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
11990 {"m7t", NULL, &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
11991 {"marm7tdmi", NULL, &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
11992 {"m7tdmi", NULL, &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
11993 {"marm710t", NULL, &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm710t")},
11994 {"m710t", NULL, &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm710t")},
11995 {"marm720t", NULL, &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm720t")},
11996 {"m720t", NULL, &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm720t")},
11997 {"marm740t", NULL, &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm740t")},
11998 {"m740t", NULL, &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm740t")},
11999 {"marm8", NULL, &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm8")},
12000 {"m8", NULL, &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm8")},
12001 {"marm810", NULL, &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm810")},
12002 {"m810", NULL, &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm810")},
12003 {"marm9", NULL, &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9")},
12004 {"m9", NULL, &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9")},
12005 {"marm9tdmi", NULL, &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9tdmi")},
12006 {"m9tdmi", NULL, &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9tdmi")},
12007 {"marm920", NULL, &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm920")},
12008 {"m920", NULL, &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm920")},
12009 {"marm940", NULL, &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm940")},
12010 {"m940", NULL, &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm940")},
12011 {"mstrongarm", NULL, &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=strongarm")},
12012 {"mstrongarm110", NULL, &legacy_cpu, ARM_ARCH_V4,
12013 N_("use -mcpu=strongarm110")},
12014 {"mstrongarm1100", NULL, &legacy_cpu, ARM_ARCH_V4,
12015 N_("use -mcpu=strongarm1100")},
12016 {"mstrongarm1110", NULL, &legacy_cpu, ARM_ARCH_V4,
12017 N_("use -mcpu=strongarm1110")},
12018 {"mxscale", NULL, &legacy_cpu, ARM_ARCH_XSCALE, N_("use -mcpu=xscale")},
12019 {"miwmmxt", NULL, &legacy_cpu, ARM_ARCH_IWMMXT, N_("use -mcpu=iwmmxt")},
12020 {"mall", NULL, &legacy_cpu, ARM_ANY, N_("use -mcpu=all")},
12022 /* Architecture variants -- don't add any more to this list either. */
12023 {"mv2", NULL, &legacy_cpu, ARM_ARCH_V2, N_("use -march=armv2")},
12024 {"marmv2", NULL, &legacy_cpu, ARM_ARCH_V2, N_("use -march=armv2")},
12025 {"mv2a", NULL, &legacy_cpu, ARM_ARCH_V2S, N_("use -march=armv2a")},
12026 {"marmv2a", NULL, &legacy_cpu, ARM_ARCH_V2S, N_("use -march=armv2a")},
12027 {"mv3", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -march=armv3")},
12028 {"marmv3", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -march=armv3")},
12029 {"mv3m", NULL, &legacy_cpu, ARM_ARCH_V3M, N_("use -march=armv3m")},
12030 {"marmv3m", NULL, &legacy_cpu, ARM_ARCH_V3M, N_("use -march=armv3m")},
12031 {"mv4", NULL, &legacy_cpu, ARM_ARCH_V4, N_("use -march=armv4")},
12032 {"marmv4", NULL, &legacy_cpu, ARM_ARCH_V4, N_("use -march=armv4")},
12033 {"mv4t", NULL, &legacy_cpu, ARM_ARCH_V4T, N_("use -march=armv4t")},
12034 {"marmv4t", NULL, &legacy_cpu, ARM_ARCH_V4T, N_("use -march=armv4t")},
12035 {"mv5", NULL, &legacy_cpu, ARM_ARCH_V5, N_("use -march=armv5")},
12036 {"marmv5", NULL, &legacy_cpu, ARM_ARCH_V5, N_("use -march=armv5")},
12037 {"mv5t", NULL, &legacy_cpu, ARM_ARCH_V5T, N_("use -march=armv5t")},
12038 {"marmv5t", NULL, &legacy_cpu, ARM_ARCH_V5T, N_("use -march=armv5t")},
12039 {"mv5e", NULL, &legacy_cpu, ARM_ARCH_V5TE, N_("use -march=armv5te")},
12040 {"marmv5e", NULL, &legacy_cpu, ARM_ARCH_V5TE, N_("use -march=armv5te")},
12042 /* Floating point variants -- don't add any more to this list either. */
12043 {"mfpe-old", NULL, &legacy_fpu, FPU_ARCH_FPE, N_("use -mfpu=fpe")},
12044 {"mfpa10", NULL, &legacy_fpu, FPU_ARCH_FPA, N_("use -mfpu=fpa10")},
12045 {"mfpa11", NULL, &legacy_fpu, FPU_ARCH_FPA, N_("use -mfpu=fpa11")},
12046 {"mno-fpu", NULL, &legacy_fpu, 0,
12047 N_("use either -mfpu=softfpa or -mfpu=softvfp")},
12049 {NULL, NULL, NULL, 0, NULL}
12052 struct arm_cpu_option_table
12054 char *name;
12055 int value;
12056 /* For some CPUs we assume an FPU unless the user explicitly sets
12057 -mfpu=... */
12058 int default_fpu;
12061 /* This list should, at a minimum, contain all the cpu names
12062 recognized by GCC. */
12063 static struct arm_cpu_option_table arm_cpus[] =
12065 {"all", ARM_ANY, FPU_ARCH_FPA},
12066 {"arm1", ARM_ARCH_V1, FPU_ARCH_FPA},
12067 {"arm2", ARM_ARCH_V2, FPU_ARCH_FPA},
12068 {"arm250", ARM_ARCH_V2S, FPU_ARCH_FPA},
12069 {"arm3", ARM_ARCH_V2S, FPU_ARCH_FPA},
12070 {"arm6", ARM_ARCH_V3, FPU_ARCH_FPA},
12071 {"arm60", ARM_ARCH_V3, FPU_ARCH_FPA},
12072 {"arm600", ARM_ARCH_V3, FPU_ARCH_FPA},
12073 {"arm610", ARM_ARCH_V3, FPU_ARCH_FPA},
12074 {"arm620", ARM_ARCH_V3, FPU_ARCH_FPA},
12075 {"arm7", ARM_ARCH_V3, FPU_ARCH_FPA},
12076 {"arm7m", ARM_ARCH_V3M, FPU_ARCH_FPA},
12077 {"arm7d", ARM_ARCH_V3, FPU_ARCH_FPA},
12078 {"arm7dm", ARM_ARCH_V3M, FPU_ARCH_FPA},
12079 {"arm7di", ARM_ARCH_V3, FPU_ARCH_FPA},
12080 {"arm7dmi", ARM_ARCH_V3M, FPU_ARCH_FPA},
12081 {"arm70", ARM_ARCH_V3, FPU_ARCH_FPA},
12082 {"arm700", ARM_ARCH_V3, FPU_ARCH_FPA},
12083 {"arm700i", ARM_ARCH_V3, FPU_ARCH_FPA},
12084 {"arm710", ARM_ARCH_V3, FPU_ARCH_FPA},
12085 {"arm710t", ARM_ARCH_V4T, FPU_ARCH_FPA},
12086 {"arm720", ARM_ARCH_V3, FPU_ARCH_FPA},
12087 {"arm720t", ARM_ARCH_V4T, FPU_ARCH_FPA},
12088 {"arm740t", ARM_ARCH_V4T, FPU_ARCH_FPA},
12089 {"arm710c", ARM_ARCH_V3, FPU_ARCH_FPA},
12090 {"arm7100", ARM_ARCH_V3, FPU_ARCH_FPA},
12091 {"arm7500", ARM_ARCH_V3, FPU_ARCH_FPA},
12092 {"arm7500fe", ARM_ARCH_V3, FPU_ARCH_FPA},
12093 {"arm7t", ARM_ARCH_V4T, FPU_ARCH_FPA},
12094 {"arm7tdmi", ARM_ARCH_V4T, FPU_ARCH_FPA},
12095 {"arm7tdmi-s", ARM_ARCH_V4T, FPU_ARCH_FPA},
12096 {"arm8", ARM_ARCH_V4, FPU_ARCH_FPA},
12097 {"arm810", ARM_ARCH_V4, FPU_ARCH_FPA},
12098 {"strongarm", ARM_ARCH_V4, FPU_ARCH_FPA},
12099 {"strongarm1", ARM_ARCH_V4, FPU_ARCH_FPA},
12100 {"strongarm110", ARM_ARCH_V4, FPU_ARCH_FPA},
12101 {"strongarm1100", ARM_ARCH_V4, FPU_ARCH_FPA},
12102 {"strongarm1110", ARM_ARCH_V4, FPU_ARCH_FPA},
12103 {"arm9", ARM_ARCH_V4T, FPU_ARCH_FPA},
12104 {"arm920", ARM_ARCH_V4T, FPU_ARCH_FPA},
12105 {"arm920t", ARM_ARCH_V4T, FPU_ARCH_FPA},
12106 {"arm922t", ARM_ARCH_V4T, FPU_ARCH_FPA},
12107 {"arm940t", ARM_ARCH_V4T, FPU_ARCH_FPA},
12108 {"arm9tdmi", ARM_ARCH_V4T, FPU_ARCH_FPA},
12109 /* For V5 or later processors we default to using VFP; but the user
12110 should really set the FPU type explicitly. */
12111 {"arm9e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2},
12112 {"arm9e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2},
12113 {"arm926ej", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2},
12114 {"arm926ejs", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2},
12115 {"arm926ej-s", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2},
12116 {"arm946e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2},
12117 {"arm946e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2},
12118 {"arm966e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2},
12119 {"arm966e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2},
12120 {"arm10t", ARM_ARCH_V5T, FPU_ARCH_VFP_V1},
12121 {"arm10e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2},
12122 {"arm1020", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2},
12123 {"arm1020t", ARM_ARCH_V5T, FPU_ARCH_VFP_V1},
12124 {"arm1020e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2},
12125 {"arm1026ejs", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2},
12126 {"arm1026ej-s", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2},
12127 {"arm1136js", ARM_ARCH_V6, FPU_NONE},
12128 {"arm1136j-s", ARM_ARCH_V6, FPU_NONE},
12129 {"arm1136jfs", ARM_ARCH_V6, FPU_ARCH_VFP_V2},
12130 {"arm1136jf-s", ARM_ARCH_V6, FPU_ARCH_VFP_V2},
12131 {"mpcore", ARM_ARCH_V6K, FPU_ARCH_VFP_V2},
12132 {"mpcorenovfp", ARM_ARCH_V6K, FPU_NONE},
12133 {"arm1176jz-s", ARM_ARCH_V6ZK, FPU_NONE},
12134 {"arm1176jzf-s", ARM_ARCH_V6ZK, FPU_ARCH_VFP_V2},
12135 /* ??? XSCALE is really an architecture. */
12136 {"xscale", ARM_ARCH_XSCALE, FPU_ARCH_VFP_V2},
12137 /* ??? iwmmxt is not a processor. */
12138 {"iwmmxt", ARM_ARCH_IWMMXT, FPU_ARCH_VFP_V2},
12139 {"i80200", ARM_ARCH_XSCALE, FPU_ARCH_VFP_V2},
12140 /* Maverick */
12141 {"ep9312", ARM_ARCH_V4T | ARM_CEXT_MAVERICK, FPU_ARCH_MAVERICK},
12142 {NULL, 0, 0}
12145 struct arm_arch_option_table
12147 char *name;
12148 int value;
12149 int default_fpu;
12152 /* This list should, at a minimum, contain all the architecture names
12153 recognized by GCC. */
12154 static struct arm_arch_option_table arm_archs[] =
12156 {"all", ARM_ANY, FPU_ARCH_FPA},
12157 {"armv1", ARM_ARCH_V1, FPU_ARCH_FPA},
12158 {"armv2", ARM_ARCH_V2, FPU_ARCH_FPA},
12159 {"armv2a", ARM_ARCH_V2S, FPU_ARCH_FPA},
12160 {"armv2s", ARM_ARCH_V2S, FPU_ARCH_FPA},
12161 {"armv3", ARM_ARCH_V3, FPU_ARCH_FPA},
12162 {"armv3m", ARM_ARCH_V3M, FPU_ARCH_FPA},
12163 {"armv4", ARM_ARCH_V4, FPU_ARCH_FPA},
12164 {"armv4xm", ARM_ARCH_V4xM, FPU_ARCH_FPA},
12165 {"armv4t", ARM_ARCH_V4T, FPU_ARCH_FPA},
12166 {"armv4txm", ARM_ARCH_V4TxM, FPU_ARCH_FPA},
12167 {"armv5", ARM_ARCH_V5, FPU_ARCH_VFP},
12168 {"armv5t", ARM_ARCH_V5T, FPU_ARCH_VFP},
12169 {"armv5txm", ARM_ARCH_V5TxM, FPU_ARCH_VFP},
12170 {"armv5te", ARM_ARCH_V5TE, FPU_ARCH_VFP},
12171 {"armv5texp", ARM_ARCH_V5TExP, FPU_ARCH_VFP},
12172 {"armv5tej", ARM_ARCH_V5TEJ, FPU_ARCH_VFP},
12173 {"armv6", ARM_ARCH_V6, FPU_ARCH_VFP},
12174 {"armv6j", ARM_ARCH_V6, FPU_ARCH_VFP},
12175 {"armv6k", ARM_ARCH_V6K, FPU_ARCH_VFP},
12176 {"armv6z", ARM_ARCH_V6Z, FPU_ARCH_VFP},
12177 {"armv6zk", ARM_ARCH_V6ZK, FPU_ARCH_VFP},
12178 {"armv6t2", ARM_ARCH_V6T2, FPU_ARCH_VFP},
12179 {"armv6kt2", ARM_ARCH_V6KT2, FPU_ARCH_VFP},
12180 {"armv6zt2", ARM_ARCH_V6ZT2, FPU_ARCH_VFP},
12181 {"armv6zkt2", ARM_ARCH_V6ZKT2, FPU_ARCH_VFP},
12182 {"xscale", ARM_ARCH_XSCALE, FPU_ARCH_VFP},
12183 {"iwmmxt", ARM_ARCH_IWMMXT, FPU_ARCH_VFP},
12184 {NULL, 0, 0}
12187 /* ISA extensions in the co-processor space. */
12188 struct arm_option_value_table
12190 char *name;
12191 int value;
12194 static struct arm_option_value_table arm_extensions[] =
12196 {"maverick", ARM_CEXT_MAVERICK},
12197 {"xscale", ARM_CEXT_XSCALE},
12198 {"iwmmxt", ARM_CEXT_IWMMXT},
12199 {NULL, 0}
12202 /* This list should, at a minimum, contain all the fpu names
12203 recognized by GCC. */
12204 static struct arm_option_value_table arm_fpus[] =
12206 {"softfpa", FPU_NONE},
12207 {"fpe", FPU_ARCH_FPE},
12208 {"fpe2", FPU_ARCH_FPE},
12209 {"fpe3", FPU_ARCH_FPA}, /* Third release supports LFM/SFM. */
12210 {"fpa", FPU_ARCH_FPA},
12211 {"fpa10", FPU_ARCH_FPA},
12212 {"fpa11", FPU_ARCH_FPA},
12213 {"arm7500fe", FPU_ARCH_FPA},
12214 {"softvfp", FPU_ARCH_VFP},
12215 {"softvfp+vfp", FPU_ARCH_VFP_V2},
12216 {"vfp", FPU_ARCH_VFP_V2},
12217 {"vfp9", FPU_ARCH_VFP_V2},
12218 {"vfp10", FPU_ARCH_VFP_V2},
12219 {"vfp10-r0", FPU_ARCH_VFP_V1},
12220 {"vfpxd", FPU_ARCH_VFP_V1xD},
12221 {"arm1020t", FPU_ARCH_VFP_V1},
12222 {"arm1020e", FPU_ARCH_VFP_V2},
12223 {"arm1136jfs", FPU_ARCH_VFP_V2},
12224 {"arm1136jf-s", FPU_ARCH_VFP_V2},
12225 {"maverick", FPU_ARCH_MAVERICK},
12226 {NULL, 0}
12229 static struct arm_option_value_table arm_float_abis[] =
12231 {"hard", ARM_FLOAT_ABI_HARD},
12232 {"softfp", ARM_FLOAT_ABI_SOFTFP},
12233 {"soft", ARM_FLOAT_ABI_SOFT},
12234 {NULL, 0}
12237 #ifdef OBJ_ELF
12238 /* We only know how to output GNU and ver 4 (AAELF) formats. */
12239 static struct arm_option_value_table arm_eabis[] =
12241 {"gnu", EF_ARM_EABI_UNKNOWN},
12242 {"4", EF_ARM_EABI_VER4},
12243 {NULL, 0}
12245 #endif
12247 struct arm_long_option_table
12249 char * option; /* Substring to match. */
12250 char * help; /* Help information. */
12251 int (* func) (char * subopt); /* Function to decode sub-option. */
12252 char * deprecated; /* If non-null, print this message. */
12255 static int
12256 arm_parse_extension (char * str, int * opt_p)
12258 while (str != NULL && *str != 0)
12260 struct arm_option_value_table * opt;
12261 char * ext;
12262 int optlen;
12264 if (*str != '+')
12266 as_bad (_("invalid architectural extension"));
12267 return 0;
12270 str++;
12271 ext = strchr (str, '+');
12273 if (ext != NULL)
12274 optlen = ext - str;
12275 else
12276 optlen = strlen (str);
12278 if (optlen == 0)
12280 as_bad (_("missing architectural extension"));
12281 return 0;
12284 for (opt = arm_extensions; opt->name != NULL; opt++)
12285 if (strncmp (opt->name, str, optlen) == 0)
12287 *opt_p |= opt->value;
12288 break;
12291 if (opt->name == NULL)
12293 as_bad (_("unknown architectural extnsion `%s'"), str);
12294 return 0;
12297 str = ext;
12300 return 1;
12303 static int
12304 arm_parse_cpu (char * str)
12306 struct arm_cpu_option_table * opt;
12307 char * ext = strchr (str, '+');
12308 int optlen;
12310 if (ext != NULL)
12311 optlen = ext - str;
12312 else
12313 optlen = strlen (str);
12315 if (optlen == 0)
12317 as_bad (_("missing cpu name `%s'"), str);
12318 return 0;
12321 for (opt = arm_cpus; opt->name != NULL; opt++)
12322 if (strncmp (opt->name, str, optlen) == 0)
12324 mcpu_cpu_opt = opt->value;
12325 mcpu_fpu_opt = opt->default_fpu;
12327 if (ext != NULL)
12328 return arm_parse_extension (ext, &mcpu_cpu_opt);
12330 return 1;
12333 as_bad (_("unknown cpu `%s'"), str);
12334 return 0;
12337 static int
12338 arm_parse_arch (char * str)
12340 struct arm_arch_option_table *opt;
12341 char *ext = strchr (str, '+');
12342 int optlen;
12344 if (ext != NULL)
12345 optlen = ext - str;
12346 else
12347 optlen = strlen (str);
12349 if (optlen == 0)
12351 as_bad (_("missing architecture name `%s'"), str);
12352 return 0;
12356 for (opt = arm_archs; opt->name != NULL; opt++)
12357 if (streq (opt->name, str))
12359 march_cpu_opt = opt->value;
12360 march_fpu_opt = opt->default_fpu;
12362 if (ext != NULL)
12363 return arm_parse_extension (ext, &march_cpu_opt);
12365 return 1;
12368 as_bad (_("unknown architecture `%s'\n"), str);
12369 return 0;
12372 static int
12373 arm_parse_fpu (char * str)
12375 struct arm_option_value_table * opt;
12377 for (opt = arm_fpus; opt->name != NULL; opt++)
12378 if (streq (opt->name, str))
12380 mfpu_opt = opt->value;
12381 return 1;
12384 as_bad (_("unknown floating point format `%s'\n"), str);
12385 return 0;
12388 static int
12389 arm_parse_float_abi (char * str)
12391 struct arm_option_value_table * opt;
12393 for (opt = arm_float_abis; opt->name != NULL; opt++)
12394 if (streq (opt->name, str))
12396 mfloat_abi_opt = opt->value;
12397 return 1;
12400 as_bad (_("unknown floating point abi `%s'\n"), str);
12401 return 0;
12404 #ifdef OBJ_ELF
12405 static int
12406 arm_parse_eabi (char * str)
12408 struct arm_option_value_table *opt;
12410 for (opt = arm_eabis; opt->name != NULL; opt++)
12411 if (streq (opt->name, str))
12413 meabi_flags = opt->value;
12414 return 1;
12416 as_bad (_("unknown EABI `%s'\n"), str);
12417 return 0;
12419 #endif
12421 struct arm_long_option_table arm_long_opts[] =
12423 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
12424 arm_parse_cpu, NULL},
12425 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
12426 arm_parse_arch, NULL},
12427 {"mfpu=", N_("<fpu name>\t assemble for FPU architecture <fpu name>"),
12428 arm_parse_fpu, NULL},
12429 {"mfloat-abi=", N_("<abi>\t assemble for floating point ABI <abi>"),
12430 arm_parse_float_abi, NULL},
12431 #ifdef OBJ_ELF
12432 {"meabi=", N_("<ver>\t assemble for eabi version <ver>"),
12433 arm_parse_eabi, NULL},
12434 #endif
12435 {NULL, NULL, 0, NULL}
12439 md_parse_option (int c, char * arg)
12441 struct arm_option_table *opt;
12442 struct arm_long_option_table *lopt;
12444 switch (c)
12446 #ifdef OPTION_EB
12447 case OPTION_EB:
12448 target_big_endian = 1;
12449 break;
12450 #endif
12452 #ifdef OPTION_EL
12453 case OPTION_EL:
12454 target_big_endian = 0;
12455 break;
12456 #endif
12458 case 'a':
12459 /* Listing option. Just ignore these, we don't support additional
12460 ones. */
12461 return 0;
12463 default:
12464 for (opt = arm_opts; opt->option != NULL; opt++)
12466 if (c == opt->option[0]
12467 && ((arg == NULL && opt->option[1] == 0)
12468 || streq (arg, opt->option + 1)))
12470 #if WARN_DEPRECATED
12471 /* If the option is deprecated, tell the user. */
12472 if (opt->deprecated != NULL)
12473 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c,
12474 arg ? arg : "", _(opt->deprecated));
12475 #endif
12477 if (opt->var != NULL)
12478 *opt->var = opt->value;
12480 return 1;
12484 for (lopt = arm_long_opts; lopt->option != NULL; lopt++)
12486 /* These options are expected to have an argument. */
12487 if (c == lopt->option[0]
12488 && arg != NULL
12489 && strncmp (arg, lopt->option + 1,
12490 strlen (lopt->option + 1)) == 0)
12492 #if WARN_DEPRECATED
12493 /* If the option is deprecated, tell the user. */
12494 if (lopt->deprecated != NULL)
12495 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c, arg,
12496 _(lopt->deprecated));
12497 #endif
12499 /* Call the sup-option parser. */
12500 return lopt->func (arg + strlen (lopt->option) - 1);
12504 return 0;
12507 return 1;
12510 void
12511 md_show_usage (FILE * fp)
12513 struct arm_option_table *opt;
12514 struct arm_long_option_table *lopt;
12516 fprintf (fp, _(" ARM-specific assembler options:\n"));
12518 for (opt = arm_opts; opt->option != NULL; opt++)
12519 if (opt->help != NULL)
12520 fprintf (fp, " -%-23s%s\n", opt->option, _(opt->help));
12522 for (lopt = arm_long_opts; lopt->option != NULL; lopt++)
12523 if (lopt->help != NULL)
12524 fprintf (fp, " -%s%s\n", lopt->option, _(lopt->help));
12526 #ifdef OPTION_EB
12527 fprintf (fp, _("\
12528 -EB assemble code for a big-endian cpu\n"));
12529 #endif
12531 #ifdef OPTION_EL
12532 fprintf (fp, _("\
12533 -EL assemble code for a little-endian cpu\n"));
12534 #endif