1 /* tc-m68k.c -- Assemble for the m68k family
2 Copyright 1987, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
5 This file is part of GAS, the GNU Assembler.
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to the Free
19 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
23 #include "safe-ctype.h"
26 #include "dwarf2dbg.h"
27 #include "dw2gencfi.h"
29 #include "opcode/m68k.h"
30 #include "m68k-parse.h"
40 /* This string holds the chars that always start a comment. If the
41 pre-processor is disabled, these aren't very useful. The macro
42 tc_comment_chars points to this. We use this, rather than the
43 usual comment_chars, so that the --bitwise-or option will work. */
44 #if defined (TE_SVR4) || defined (TE_DELTA)
45 const char *m68k_comment_chars
= "|#";
47 const char *m68k_comment_chars
= "|";
50 /* This array holds the chars that only start a comment at the beginning of
51 a line. If the line seems to have the form '# 123 filename'
52 .line and .file directives will appear in the pre-processed output */
53 /* Note that input_file.c hand checks for '#' at the beginning of the
54 first line of the input file. This is because the compiler outputs
55 #NO_APP at the beginning of its output. */
56 /* Also note that comments like this one will always work. */
57 const char line_comment_chars
[] = "#*";
59 const char line_separator_chars
[] = ";";
61 /* Chars that can be used to separate mant from exp in floating point nums. */
62 const char EXP_CHARS
[] = "eE";
64 /* Chars that mean this number is a floating point constant, as
65 in "0f12.456" or "0d1.2345e12". */
67 const char FLT_CHARS
[] = "rRsSfFdDxXeEpP";
69 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
70 changed in read.c . Ideally it shouldn't have to know about it at all,
71 but nothing is ideal around here. */
73 /* Are we trying to generate PIC code? If so, absolute references
74 ought to be made into linkage table references or pc-relative
75 references. Not implemented. For ELF there are other means
76 to denote pic relocations. */
79 static int flag_short_refs
; /* -l option. */
80 static int flag_long_jumps
; /* -S option. */
81 static int flag_keep_pcrel
; /* --pcrel option. */
83 #ifdef REGISTER_PREFIX_OPTIONAL
84 int flag_reg_prefix_optional
= REGISTER_PREFIX_OPTIONAL
;
86 int flag_reg_prefix_optional
;
89 /* Whether --register-prefix-optional was used on the command line. */
90 static int reg_prefix_optional_seen
;
92 /* The floating point coprocessor to use by default. */
93 static enum m68k_register m68k_float_copnum
= COP1
;
95 /* If this is non-zero, then references to number(%pc) will be taken
96 to refer to number, rather than to %pc + number. */
97 static int m68k_abspcadd
;
99 /* If this is non-zero, then the quick forms of the move, add, and sub
100 instructions are used when possible. */
101 static int m68k_quick
= 1;
103 /* If this is non-zero, then if the size is not specified for a base
104 or outer displacement, the assembler assumes that the size should
106 static int m68k_rel32
= 1;
108 /* This is non-zero if m68k_rel32 was set from the command line. */
109 static int m68k_rel32_from_cmdline
;
111 /* The default width to use for an index register when using a base
113 static enum m68k_size m68k_index_width_default
= SIZE_LONG
;
115 /* We want to warn if any text labels are misaligned. In order to get
116 the right line number, we need to record the line number for each
120 struct label_line
*next
;
127 /* The list of labels. */
129 static struct label_line
*labels
;
131 /* The current label. */
133 static struct label_line
*current_label
;
135 /* Pointer to list holding the opcodes sorted by name. */
136 static struct m68k_opcode
const ** m68k_sorted_opcodes
;
138 /* Its an arbitrary name: This means I don't approve of it.
140 static struct obstack robyn
;
144 const char *m_operands
;
145 unsigned long m_opcode
;
149 struct m68k_incant
*m_next
;
152 #define getone(x) ((((x)->m_opcode)>>16)&0xffff)
153 #define gettwo(x) (((x)->m_opcode)&0xffff)
155 static const enum m68k_register m68000_control_regs
[] = { 0 };
156 static const enum m68k_register m68010_control_regs
[] = {
160 static const enum m68k_register m68020_control_regs
[] = {
161 SFC
, DFC
, USP
, VBR
, CACR
, CAAR
, MSP
, ISP
,
164 static const enum m68k_register m68040_control_regs
[] = {
165 SFC
, DFC
, CACR
, TC
, ITT0
, ITT1
, DTT0
, DTT1
,
166 USP
, VBR
, MSP
, ISP
, MMUSR
, URP
, SRP
,
169 static const enum m68k_register m68060_control_regs
[] = {
170 SFC
, DFC
, CACR
, TC
, ITT0
, ITT1
, DTT0
, DTT1
, BUSCR
,
171 USP
, VBR
, URP
, SRP
, PCR
,
174 static const enum m68k_register mcf_control_regs
[] = {
175 CACR
, TC
, ACR0
, ACR1
, ACR2
, ACR3
, VBR
, ROMBAR
,
176 RAMBAR0
, RAMBAR1
, MBAR
,
179 static const enum m68k_register mcf5249_control_regs
[] = {
180 CACR
, ACR0
, ACR1
, VBR
, RAMBAR0
, RAMBAR1
, MBAR
, MBAR2
,
183 static const enum m68k_register mcf528x_control_regs
[] = {
184 CACR
, ACR0
, ACR1
, VBR
, FLASHBAR
, RAMBAR
,
187 static const enum m68k_register mcfv4e_control_regs
[] = {
188 CACR
, TC
, ITT0
, ITT1
, DTT0
, DTT1
, BUSCR
, VBR
, PC
, ROMBAR
,
189 ROMBAR1
, RAMBAR0
, RAMBAR1
, MPCR
, EDRAMBAR
, SECMBAR
, MBAR
, MBAR0
, MBAR1
,
190 PCR1U0
, PCR1L0
, PCR1U1
, PCR1L1
, PCR2U0
, PCR2L0
, PCR2U1
, PCR2L1
,
191 PCR3U0
, PCR3L0
, PCR3U1
, PCR3L1
,
194 #define cpu32_control_regs m68010_control_regs
196 static const enum m68k_register
*control_regs
;
198 /* Internal form of a 68020 instruction. */
202 const char *args
; /* List of opcode info. */
205 int numo
; /* Number of shorts in opcode. */
208 struct m68k_op operands
[6];
210 int nexp
; /* Number of exprs in use. */
211 struct m68k_exp exprs
[4];
213 int nfrag
; /* Number of frags we have to produce. */
216 int fragoff
; /* Where in the current opcode the frag ends. */
223 int nrel
; /* Num of reloc strucs in use. */
230 /* In a pc relative address the difference between the address
231 of the offset and the address that the offset is relative
232 to. This depends on the addressing mode. Basically this
233 is the value to put in the offset field to address the
234 first byte of the offset, without regarding the special
235 significance of some values (in the branch instruction, for
239 /* Whether this expression needs special pic relocation, and if
241 enum pic_relocation pic_reloc
;
244 reloc
[5]; /* Five is enough??? */
247 #define cpu_of_arch(x) ((x) & (m68000up | mcfisa_a))
248 #define float_of_arch(x) ((x) & mfloat)
249 #define mmu_of_arch(x) ((x) & mmmu)
250 #define arch_coldfire_p(x) ((x) & mcfisa_a)
251 #define arch_coldfire_fpu(x) ((x) & cfloat)
253 /* Macros for determining if cpu supports a specific addressing mode. */
254 #define HAVE_LONG_BRANCH(x) ((x) & (m68020|m68030|m68040|m68060|cpu32|mcfisa_b))
256 static struct m68k_it the_ins
; /* The instruction being assembled. */
258 #define op(ex) ((ex)->exp.X_op)
259 #define adds(ex) ((ex)->exp.X_add_symbol)
260 #define subs(ex) ((ex)->exp.X_op_symbol)
261 #define offs(ex) ((ex)->exp.X_add_number)
263 /* Macros for adding things to the m68k_it struct. */
264 #define addword(w) (the_ins.opcode[the_ins.numo++] = (w))
266 /* Like addword, but goes BEFORE general operands. */
269 insop (int w
, const struct m68k_incant
*opcode
)
272 for (z
= the_ins
.numo
; z
> opcode
->m_codenum
; --z
)
273 the_ins
.opcode
[z
] = the_ins
.opcode
[z
- 1];
274 for (z
= 0; z
< the_ins
.nrel
; z
++)
275 the_ins
.reloc
[z
].n
+= 2;
276 for (z
= 0; z
< the_ins
.nfrag
; z
++)
277 the_ins
.fragb
[z
].fragoff
++;
278 the_ins
.opcode
[opcode
->m_codenum
] = w
;
282 /* The numo+1 kludge is so we can hit the low order byte of the prev word.
285 add_fix (int width
, struct m68k_exp
*exp
, int pc_rel
, int pc_fix
)
287 the_ins
.reloc
[the_ins
.nrel
].n
= (width
== 'B' || width
== '3'
288 ? the_ins
.numo
* 2 - 1
290 ? the_ins
.numo
* 2 + 1
291 : the_ins
.numo
* 2));
292 the_ins
.reloc
[the_ins
.nrel
].exp
= exp
->exp
;
293 the_ins
.reloc
[the_ins
.nrel
].wid
= width
;
294 the_ins
.reloc
[the_ins
.nrel
].pcrel_fix
= pc_fix
;
296 the_ins
.reloc
[the_ins
.nrel
].pic_reloc
= exp
->pic_reloc
;
298 the_ins
.reloc
[the_ins
.nrel
++].pcrel
= pc_rel
;
301 /* Cause an extra frag to be generated here, inserting up to 10 bytes
302 (that value is chosen in the frag_var call in md_assemble). TYPE
303 is the subtype of the frag to be generated; its primary type is
304 rs_machine_dependent.
306 The TYPE parameter is also used by md_convert_frag_1 and
307 md_estimate_size_before_relax. The appropriate type of fixup will
308 be emitted by md_convert_frag_1.
310 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
312 add_frag (symbolS
*add
, offsetT off
, int type
)
314 the_ins
.fragb
[the_ins
.nfrag
].fragoff
= the_ins
.numo
;
315 the_ins
.fragb
[the_ins
.nfrag
].fadd
= add
;
316 the_ins
.fragb
[the_ins
.nfrag
].foff
= off
;
317 the_ins
.fragb
[the_ins
.nfrag
++].fragty
= type
;
321 (op (ex) != O_constant && op (ex) != O_big)
323 static char *crack_operand (char *str
, struct m68k_op
*opP
);
324 static int get_num (struct m68k_exp
*exp
, int ok
);
325 static int reverse_16_bits (int in
);
326 static int reverse_8_bits (int in
);
327 static void install_gen_operand (int mode
, int val
);
328 static void install_operand (int mode
, int val
);
329 static void s_bss (int);
330 static void s_data1 (int);
331 static void s_data2 (int);
332 static void s_even (int);
333 static void s_proc (int);
334 static void s_chip (int);
335 static void s_fopt (int);
336 static void s_opt (int);
337 static void s_reg (int);
338 static void s_restore (int);
339 static void s_save (int);
340 static void s_mri_if (int);
341 static void s_mri_else (int);
342 static void s_mri_endi (int);
343 static void s_mri_break (int);
344 static void s_mri_next (int);
345 static void s_mri_for (int);
346 static void s_mri_endf (int);
347 static void s_mri_repeat (int);
348 static void s_mri_until (int);
349 static void s_mri_while (int);
350 static void s_mri_endw (int);
352 static int current_architecture
;
353 static int current_chip
;
363 static const struct m68k_cpu archs
[] =
365 { m68000
, m68000
, "68000", 0 },
366 { m68010
, m68010
, "68010", 0 },
367 { m68020
, m68020
, "68020", 0 },
368 { m68030
, m68030
, "68030", 0 },
369 { m68040
, m68040
, "68040", 0 },
370 { m68060
, m68060
, "68060", 0 },
371 { cpu32
, cpu32
, "cpu32", 0 },
372 { m68881
, m68881
, "68881", 0 },
373 { m68851
, m68851
, "68851", 0 },
374 { mcfisa_a
, mcf5200
, "5200", 0 },
375 { mcfisa_a
|mcfhwdiv
|mcfmac
, mcf5206e
, "5206e", 0 },
376 { mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf521x
, "521x", 0 },
377 { mcfisa_a
|mcfhwdiv
|mcfemac
, mcf5249
, "5249", 0 },
378 { mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf528x
, "528x", 0 },
379 { mcfisa_a
|mcfhwdiv
|mcfmac
, mcf5307
, "5307", 0 },
380 { mcfisa_a
|mcfhwdiv
|mcfisa_b
|mcfmac
, mcf5407
, "5407", 0 },
381 { mcfisa_a
|mcfhwdiv
|mcfisa_b
|mcfemac
|mcfusp
|cfloat
, mcf5470
, "547x", 0 },
382 { mcfisa_a
|mcfhwdiv
|mcfisa_b
|mcfemac
|mcfusp
|cfloat
, mcf5480
, "548x", 0 },
383 /* Aliases (effectively, so far as gas is concerned) for the above
385 { m68020
, m68020
, "68k", 1 },
386 { m68000
, m68000
, "68008", 1 },
387 { m68000
, m68000
, "68302", 1 },
388 { m68000
, m68000
, "68306", 1 },
389 { m68000
, m68000
, "68307", 1 },
390 { m68000
, m68000
, "68322", 1 },
391 { m68000
, m68000
, "68356", 1 },
392 { m68000
, m68000
, "68ec000", 1 },
393 { m68000
, m68000
, "68hc000", 1 },
394 { m68000
, m68000
, "68hc001", 1 },
395 { m68020
, m68020
, "68ec020", 1 },
396 { m68030
, m68030
, "68ec030", 1 },
397 { m68040
, m68040
, "68ec040", 1 },
398 { m68060
, m68060
, "68ec060", 1 },
399 { cpu32
, cpu32
, "68330", 1 },
400 { cpu32
, cpu32
, "68331", 1 },
401 { cpu32
, cpu32
, "68332", 1 },
402 { cpu32
, cpu32
, "68333", 1 },
403 { cpu32
, cpu32
, "68334", 1 },
404 { cpu32
, cpu32
, "68336", 1 },
405 { cpu32
, cpu32
, "68340", 1 },
406 { cpu32
, cpu32
, "68341", 1 },
407 { cpu32
, cpu32
, "68349", 1 },
408 { cpu32
, cpu32
, "68360", 1 },
409 { m68881
, m68881
, "68882", 1 },
410 { mcfisa_a
, mcf5200
, "5202", 1 },
411 { mcfisa_a
, mcf5200
, "5204", 1 },
412 { mcfisa_a
, mcf5200
, "5206", 1 },
413 { mcfisa_a
|mcfhwdiv
|mcfisa_aa
|mcfemac
, mcf521x
, "5214", 1 },
414 { mcfisa_a
|mcfhwdiv
|mcfisa_aa
|mcfemac
, mcf521x
, "5216", 1 },
415 { mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
, mcf528x
, "5280", 1 },
416 { mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
, mcf528x
, "5281", 1 },
417 { mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
, mcf528x
, "5282", 1 },
418 { mcfisa_a
|mcfhwdiv
|mcfisa_b
|mcfmac
, mcf5407
, "cfv4", 1 },
419 { mcfisa_a
|mcfhwdiv
|mcfisa_b
|mcfemac
|mcfusp
|cfloat
, mcf5470
, "5470", 1 },
420 { mcfisa_a
|mcfhwdiv
|mcfisa_b
|mcfemac
|mcfusp
|cfloat
, mcf5470
, "5471", 1 },
421 { mcfisa_a
|mcfhwdiv
|mcfisa_b
|mcfemac
|mcfusp
|cfloat
, mcf5470
, "5472", 1 },
422 { mcfisa_a
|mcfhwdiv
|mcfisa_b
|mcfemac
|mcfusp
|cfloat
, mcf5470
, "5473", 1 },
423 { mcfisa_a
|mcfhwdiv
|mcfisa_b
|mcfemac
|mcfusp
|cfloat
, mcf5470
, "5474", 1 },
424 { mcfisa_a
|mcfhwdiv
|mcfisa_b
|mcfemac
|mcfusp
|cfloat
, mcf5470
, "5475", 1 },
425 { mcfisa_a
|mcfhwdiv
|mcfisa_b
|mcfemac
|mcfusp
|cfloat
, mcf5470
, "5480", 1 },
426 { mcfisa_a
|mcfhwdiv
|mcfisa_b
|mcfemac
|mcfusp
|cfloat
, mcf5470
, "5481", 1 },
427 { mcfisa_a
|mcfhwdiv
|mcfisa_b
|mcfemac
|mcfusp
|cfloat
, mcf5470
, "5482", 1 },
428 { mcfisa_a
|mcfhwdiv
|mcfisa_b
|mcfemac
|mcfusp
|cfloat
, mcf5470
, "5483", 1 },
429 { mcfisa_a
|mcfhwdiv
|mcfisa_b
|mcfemac
|mcfusp
|cfloat
, mcf5470
, "5484", 1 },
430 { mcfisa_a
|mcfhwdiv
|mcfisa_b
|mcfemac
|mcfusp
|cfloat
, mcf5470
, "5485", 1 },
431 { mcfisa_a
|mcfhwdiv
|mcfisa_b
|mcfemac
|mcfusp
|cfloat
, mcf5470
, "cfv4e", 1 },
434 static const int n_archs
= sizeof (archs
) / sizeof (archs
[0]);
436 /* This is the assembler relaxation table for m68k. m68k is a rich CISC
437 architecture and we have a lot of relaxation modes. */
439 /* Macros used in the relaxation code. */
440 #define TAB(x,y) (((x) << 2) + (y))
441 #define TABTYPE(x) ((x) >> 2)
443 /* Relaxation states. */
449 /* Here are all the relaxation modes we support. First we can relax ordinary
450 branches. On 68020 and higher and on CPU32 all branch instructions take
451 three forms, so on these CPUs all branches always remain as such. When we
452 have to expand to the LONG form on a 68000, though, we substitute an
453 absolute jump instead. This is a direct replacement for unconditional
454 branches and a branch over a jump for conditional branches. However, if the
455 user requires PIC and disables this with --pcrel, we can only relax between
456 BYTE and SHORT forms, punting if that isn't enough. This gives us four
457 different relaxation modes for branches: */
459 #define BRANCHBWL 0 /* Branch byte, word, or long. */
460 #define BRABSJUNC 1 /* Absolute jump for LONG, unconditional. */
461 #define BRABSJCOND 2 /* Absolute jump for LONG, conditional. */
462 #define BRANCHBW 3 /* Branch byte or word. */
464 /* We also relax coprocessor branches and DBcc's. All CPUs that support
465 coprocessor branches support them in word and long forms, so we have only
466 one relaxation mode for them. DBcc's are word only on all CPUs. We can
467 relax them to the LONG form with a branch-around sequence. This sequence
468 can use a long branch (if available) or an absolute jump (if acceptable).
469 This gives us two relaxation modes. If long branches are not available and
470 absolute jumps are not acceptable, we don't relax DBcc's. */
472 #define FBRANCH 4 /* Coprocessor branch. */
473 #define DBCCLBR 5 /* DBcc relaxable with a long branch. */
474 #define DBCCABSJ 6 /* DBcc relaxable with an absolute jump. */
476 /* That's all for instruction relaxation. However, we also relax PC-relative
477 operands. Specifically, we have three operand relaxation modes. On the
478 68000 PC-relative operands can only be 16-bit, but on 68020 and higher and
479 on CPU32 they may be 16-bit or 32-bit. For the latter we relax between the
480 two. Also PC+displacement+index operands in their simple form (with a non-
481 suppressed index without memory indirection) are supported on all CPUs, but
482 on the 68000 the displacement can be 8-bit only, whereas on 68020 and higher
483 and on CPU32 we relax it to SHORT and LONG forms as well using the extended
484 form of the PC+displacement+index operand. Finally, some absolute operands
485 can be relaxed down to 16-bit PC-relative. */
487 #define PCREL1632 7 /* 16-bit or 32-bit PC-relative. */
488 #define PCINDEX 8 /* PC + displacement + index. */
489 #define ABSTOPCREL 9 /* Absolute relax down to 16-bit PC-relative. */
491 /* Note that calls to frag_var need to specify the maximum expansion
492 needed; this is currently 10 bytes for DBCC. */
495 How far Forward this mode will reach:
496 How far Backward this mode will reach:
497 How many bytes this mode will add to the size of the frag
498 Which mode to go to if the offset won't fit in this one
500 Please check tc-m68k.h:md_prepare_relax_scan if changing this table. */
501 relax_typeS md_relax_table
[] =
503 { 127, -128, 0, TAB (BRANCHBWL
, SHORT
) },
504 { 32767, -32768, 2, TAB (BRANCHBWL
, LONG
) },
508 { 127, -128, 0, TAB (BRABSJUNC
, SHORT
) },
509 { 32767, -32768, 2, TAB (BRABSJUNC
, LONG
) },
513 { 127, -128, 0, TAB (BRABSJCOND
, SHORT
) },
514 { 32767, -32768, 2, TAB (BRABSJCOND
, LONG
) },
518 { 127, -128, 0, TAB (BRANCHBW
, SHORT
) },
523 { 1, 1, 0, 0 }, /* FBRANCH doesn't come BYTE. */
524 { 32767, -32768, 2, TAB (FBRANCH
, LONG
) },
528 { 1, 1, 0, 0 }, /* DBCC doesn't come BYTE. */
529 { 32767, -32768, 2, TAB (DBCCLBR
, LONG
) },
533 { 1, 1, 0, 0 }, /* DBCC doesn't come BYTE. */
534 { 32767, -32768, 2, TAB (DBCCABSJ
, LONG
) },
538 { 1, 1, 0, 0 }, /* PCREL1632 doesn't come BYTE. */
539 { 32767, -32768, 2, TAB (PCREL1632
, LONG
) },
543 { 125, -130, 0, TAB (PCINDEX
, SHORT
) },
544 { 32765, -32770, 2, TAB (PCINDEX
, LONG
) },
548 { 1, 1, 0, 0 }, /* ABSTOPCREL doesn't come BYTE. */
549 { 32767, -32768, 2, TAB (ABSTOPCREL
, LONG
) },
554 /* These are the machine dependent pseudo-ops. These are included so
555 the assembler can work on the output from the SUN C compiler, which
558 /* This table describes all the machine specific pseudo-ops the assembler
559 has to support. The fields are:
560 pseudo-op name without dot
561 function to call to execute this pseudo-op
562 Integer arg to pass to the function. */
563 const pseudo_typeS md_pseudo_table
[] =
565 {"data1", s_data1
, 0},
566 {"data2", s_data2
, 0},
569 {"skip", s_space
, 0},
571 #if defined (TE_SUN3) || defined (OBJ_ELF)
572 {"align", s_align_bytes
, 0},
575 {"swbeg", s_ignore
, 0},
577 {"extend", float_cons
, 'x'},
578 {"ldouble", float_cons
, 'x'},
580 /* The following pseudo-ops are supported for MRI compatibility. */
582 {"comline", s_space
, 1},
584 {"mask2", s_ignore
, 0},
587 {"restore", s_restore
, 0},
591 {"if.b", s_mri_if
, 'b'},
592 {"if.w", s_mri_if
, 'w'},
593 {"if.l", s_mri_if
, 'l'},
594 {"else", s_mri_else
, 0},
595 {"else.s", s_mri_else
, 's'},
596 {"else.l", s_mri_else
, 'l'},
597 {"endi", s_mri_endi
, 0},
598 {"break", s_mri_break
, 0},
599 {"break.s", s_mri_break
, 's'},
600 {"break.l", s_mri_break
, 'l'},
601 {"next", s_mri_next
, 0},
602 {"next.s", s_mri_next
, 's'},
603 {"next.l", s_mri_next
, 'l'},
604 {"for", s_mri_for
, 0},
605 {"for.b", s_mri_for
, 'b'},
606 {"for.w", s_mri_for
, 'w'},
607 {"for.l", s_mri_for
, 'l'},
608 {"endf", s_mri_endf
, 0},
609 {"repeat", s_mri_repeat
, 0},
610 {"until", s_mri_until
, 0},
611 {"until.b", s_mri_until
, 'b'},
612 {"until.w", s_mri_until
, 'w'},
613 {"until.l", s_mri_until
, 'l'},
614 {"while", s_mri_while
, 0},
615 {"while.b", s_mri_while
, 'b'},
616 {"while.w", s_mri_while
, 'w'},
617 {"while.l", s_mri_while
, 'l'},
618 {"endw", s_mri_endw
, 0},
623 /* The mote pseudo ops are put into the opcode table, since they
624 don't start with a . they look like opcodes to gas. */
626 const pseudo_typeS mote_pseudo_table
[] =
639 {"xdef", s_globl
, 0},
641 {"align", s_align_bytes
, 0},
643 {"align", s_align_ptwo
, 0},
646 {"sect", obj_coff_section
, 0},
647 {"section", obj_coff_section
, 0},
652 /* Truncate and sign-extend at 32 bits, so that building on a 64-bit host
653 gives identical results to a 32-bit host. */
654 #define TRUNC(X) ((valueT) (X) & 0xffffffff)
655 #define SEXT(X) ((TRUNC (X) ^ 0x80000000) - 0x80000000)
657 #define issbyte(x) ((valueT) SEXT (x) + 0x80 < 0x100)
658 #define isubyte(x) ((valueT) TRUNC (x) < 0x100)
659 #define issword(x) ((valueT) SEXT (x) + 0x8000 < 0x10000)
660 #define isuword(x) ((valueT) TRUNC (x) < 0x10000)
662 #define isbyte(x) ((valueT) SEXT (x) + 0xff < 0x1ff)
663 #define isword(x) ((valueT) SEXT (x) + 0xffff < 0x1ffff)
664 #define islong(x) (1)
666 static char notend_table
[256];
667 static char alt_notend_table
[256];
669 (! (notend_table[(unsigned char) *s] \
671 && alt_notend_table[(unsigned char) s[1]])))
673 /* Return a human readable string holding the list of chips that are
674 valid for a particular architecture, suppressing aliases (unless
675 there is only one of them). */
678 find_cf_chip (int architecture
)
680 static char buf
[1024];
681 int i
, j
, n_chips
, n_alias
;
685 cp
= buf
+ strlen (buf
);
687 for (i
= 0, n_chips
= 0, n_alias
= 0; i
< n_archs
; ++i
)
688 if (archs
[i
].arch
& architecture
)
696 as_fatal (_("no matching ColdFire architectures found"));
701 for (i
= 0, j
= 0; i
< n_archs
&& j
< n_chips
; ++i
)
702 if (archs
[i
].arch
& architecture
)
706 if ((j
== n_chips
- 1 && !(n_alias
> 1)) || ! n_alias
)
710 strncpy (cp
, _(" or "), (sizeof (buf
) - (cp
- buf
)));
715 strncpy (cp
, _(", or "), (sizeof (buf
) - (cp
- buf
)));
721 strncpy (cp
, ", ", (sizeof (buf
) - (cp
- buf
)));
725 strncpy (cp
, archs
[i
].name
, (sizeof (buf
) - (cp
- buf
)));
732 strncpy (cp
, _(", or aliases"), (sizeof (buf
) - (cp
- buf
)));
736 strncpy (cp
, ")", (sizeof (buf
) - (cp
- buf
)));
743 /* Return zero if the reference to SYMBOL from within the same segment may
746 /* On an ELF system, we can't relax an externally visible symbol,
747 because it may be overridden by a shared library. However, if
748 TARGET_OS is "elf", then we presume that we are assembling for an
749 embedded system, in which case we don't have to worry about shared
750 libraries, and we can relax any external sym. */
752 #define relaxable_symbol(symbol) \
753 (!((S_IS_EXTERNAL (symbol) && EXTERN_FORCE_RELOC) \
754 || S_IS_WEAK (symbol)))
756 /* Compute the relocation code for a fixup of SIZE bytes, using pc
757 relative relocation if PCREL is non-zero. PIC says whether a special
758 pic relocation was requested. */
760 static bfd_reloc_code_real_type
761 get_reloc_code (int size
, int pcrel
, enum pic_relocation pic
)
769 return BFD_RELOC_8_GOT_PCREL
;
771 return BFD_RELOC_16_GOT_PCREL
;
773 return BFD_RELOC_32_GOT_PCREL
;
781 return BFD_RELOC_8_GOTOFF
;
783 return BFD_RELOC_16_GOTOFF
;
785 return BFD_RELOC_32_GOTOFF
;
793 return BFD_RELOC_8_PLT_PCREL
;
795 return BFD_RELOC_16_PLT_PCREL
;
797 return BFD_RELOC_32_PLT_PCREL
;
805 return BFD_RELOC_8_PLTOFF
;
807 return BFD_RELOC_16_PLTOFF
;
809 return BFD_RELOC_32_PLTOFF
;
819 return BFD_RELOC_8_PCREL
;
821 return BFD_RELOC_16_PCREL
;
823 return BFD_RELOC_32_PCREL
;
843 as_bad (_("Can not do %d byte pc-relative relocation"), size
);
845 as_bad (_("Can not do %d byte pc-relative pic relocation"), size
);
850 as_bad (_("Can not do %d byte relocation"), size
);
852 as_bad (_("Can not do %d byte pic relocation"), size
);
855 return BFD_RELOC_NONE
;
858 /* Here we decide which fixups can be adjusted to make them relative
859 to the beginning of the section instead of the symbol. Basically
860 we need to make sure that the dynamic relocations are done
861 correctly, so in some cases we force the original symbol to be
864 tc_m68k_fix_adjustable (fixS
*fixP
)
866 /* Adjust_reloc_syms doesn't know about the GOT. */
867 switch (fixP
->fx_r_type
)
869 case BFD_RELOC_8_GOT_PCREL
:
870 case BFD_RELOC_16_GOT_PCREL
:
871 case BFD_RELOC_32_GOT_PCREL
:
872 case BFD_RELOC_8_GOTOFF
:
873 case BFD_RELOC_16_GOTOFF
:
874 case BFD_RELOC_32_GOTOFF
:
875 case BFD_RELOC_8_PLT_PCREL
:
876 case BFD_RELOC_16_PLT_PCREL
:
877 case BFD_RELOC_32_PLT_PCREL
:
878 case BFD_RELOC_8_PLTOFF
:
879 case BFD_RELOC_16_PLTOFF
:
880 case BFD_RELOC_32_PLTOFF
:
883 case BFD_RELOC_VTABLE_INHERIT
:
884 case BFD_RELOC_VTABLE_ENTRY
:
894 #define get_reloc_code(SIZE,PCREL,OTHER) NO_RELOC
896 #define relaxable_symbol(symbol) 1
901 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
904 bfd_reloc_code_real_type code
;
906 /* If the tcbit is set, then this was a fixup of a negative value
907 that was never resolved. We do not have a reloc to handle this,
908 so just return. We assume that other code will have detected this
909 situation and produced a helpful error message, so we just tell the
910 user that the reloc cannot be produced. */
914 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
915 _("Unable to produce reloc against symbol '%s'"),
916 S_GET_NAME (fixp
->fx_addsy
));
920 if (fixp
->fx_r_type
!= BFD_RELOC_NONE
)
922 code
= fixp
->fx_r_type
;
924 /* Since DIFF_EXPR_OK is defined in tc-m68k.h, it is possible
925 that fixup_segment converted a non-PC relative reloc into a
926 PC relative reloc. In such a case, we need to convert the
933 code
= BFD_RELOC_8_PCREL
;
936 code
= BFD_RELOC_16_PCREL
;
939 code
= BFD_RELOC_32_PCREL
;
941 case BFD_RELOC_8_PCREL
:
942 case BFD_RELOC_16_PCREL
:
943 case BFD_RELOC_32_PCREL
:
944 case BFD_RELOC_8_GOT_PCREL
:
945 case BFD_RELOC_16_GOT_PCREL
:
946 case BFD_RELOC_32_GOT_PCREL
:
947 case BFD_RELOC_8_GOTOFF
:
948 case BFD_RELOC_16_GOTOFF
:
949 case BFD_RELOC_32_GOTOFF
:
950 case BFD_RELOC_8_PLT_PCREL
:
951 case BFD_RELOC_16_PLT_PCREL
:
952 case BFD_RELOC_32_PLT_PCREL
:
953 case BFD_RELOC_8_PLTOFF
:
954 case BFD_RELOC_16_PLTOFF
:
955 case BFD_RELOC_32_PLTOFF
:
958 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
959 _("Cannot make %s relocation PC relative"),
960 bfd_get_reloc_code_name (code
));
966 #define F(SZ,PCREL) (((SZ) << 1) + (PCREL))
967 switch (F (fixp
->fx_size
, fixp
->fx_pcrel
))
969 #define MAP(SZ,PCREL,TYPE) case F(SZ,PCREL): code = (TYPE); break
970 MAP (1, 0, BFD_RELOC_8
);
971 MAP (2, 0, BFD_RELOC_16
);
972 MAP (4, 0, BFD_RELOC_32
);
973 MAP (1, 1, BFD_RELOC_8_PCREL
);
974 MAP (2, 1, BFD_RELOC_16_PCREL
);
975 MAP (4, 1, BFD_RELOC_32_PCREL
);
983 reloc
= (arelent
*) xmalloc (sizeof (arelent
));
984 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
985 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
986 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
989 reloc
->addend
= fixp
->fx_addnumber
;
994 reloc
->addend
= fixp
->fx_addnumber
;
996 reloc
->addend
= (section
->vma
997 /* Explicit sign extension in case char is
999 + ((fixp
->fx_pcrel_adjust
& 0xff) ^ 0x80) - 0x80
1000 + fixp
->fx_addnumber
1001 + md_pcrel_from (fixp
));
1004 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
1005 assert (reloc
->howto
!= 0);
1010 /* Handle of the OPCODE hash table. NULL means any use before
1011 m68k_ip_begin() will crash. */
1012 static struct hash_control
*op_hash
;
1014 /* Assemble an m68k instruction. */
1017 m68k_ip (char *instring
)
1020 register struct m68k_op
*opP
;
1021 register const struct m68k_incant
*opcode
;
1022 register const char *s
;
1023 register int tmpreg
= 0, baseo
= 0, outro
= 0, nextword
;
1024 char *pdot
, *pdotmove
;
1025 enum m68k_size siz1
, siz2
;
1029 struct m68k_op operands_backup
[6];
1030 LITTLENUM_TYPE words
[6];
1031 LITTLENUM_TYPE
*wordp
;
1032 unsigned long ok_arch
= 0;
1034 if (*instring
== ' ')
1035 instring
++; /* Skip leading whitespace. */
1037 /* Scan up to end of operation-code, which MUST end in end-of-string
1038 or exactly 1 space. */
1040 for (p
= instring
; *p
!= '\0'; p
++)
1050 the_ins
.error
= _("No operator");
1054 /* p now points to the end of the opcode name, probably whitespace.
1055 Make sure the name is null terminated by clobbering the
1056 whitespace, look it up in the hash table, then fix it back.
1057 Remove a dot, first, since the opcode tables have none. */
1060 for (pdotmove
= pdot
; pdotmove
< p
; pdotmove
++)
1061 *pdotmove
= pdotmove
[1];
1067 opcode
= (const struct m68k_incant
*) hash_find (op_hash
, instring
);
1072 for (pdotmove
= p
; pdotmove
> pdot
; pdotmove
--)
1073 *pdotmove
= pdotmove
[-1];
1080 the_ins
.error
= _("Unknown operator");
1084 /* Found a legitimate opcode, start matching operands. */
1088 if (opcode
->m_operands
== 0)
1090 char *old
= input_line_pointer
;
1092 input_line_pointer
= p
;
1093 /* Ahh - it's a motorola style psuedo op. */
1094 mote_pseudo_table
[opcode
->m_opnum
].poc_handler
1095 (mote_pseudo_table
[opcode
->m_opnum
].poc_val
);
1096 input_line_pointer
= old
;
1102 if (flag_mri
&& opcode
->m_opnum
== 0)
1104 /* In MRI mode, random garbage is allowed after an instruction
1105 which accepts no operands. */
1106 the_ins
.args
= opcode
->m_operands
;
1107 the_ins
.numargs
= opcode
->m_opnum
;
1108 the_ins
.numo
= opcode
->m_codenum
;
1109 the_ins
.opcode
[0] = getone (opcode
);
1110 the_ins
.opcode
[1] = gettwo (opcode
);
1114 for (opP
= &the_ins
.operands
[0]; *p
; opP
++)
1116 p
= crack_operand (p
, opP
);
1120 the_ins
.error
= opP
->error
;
1125 opsfound
= opP
- &the_ins
.operands
[0];
1127 /* This ugly hack is to support the floating pt opcodes in their
1128 standard form. Essentially, we fake a first enty of type COP#1 */
1129 if (opcode
->m_operands
[0] == 'I')
1133 for (n
= opsfound
; n
> 0; --n
)
1134 the_ins
.operands
[n
] = the_ins
.operands
[n
- 1];
1136 memset (&the_ins
.operands
[0], '\0', sizeof (the_ins
.operands
[0]));
1137 the_ins
.operands
[0].mode
= CONTROL
;
1138 the_ins
.operands
[0].reg
= m68k_float_copnum
;
1142 /* We've got the operands. Find an opcode that'll accept them. */
1145 /* If we didn't get the right number of ops, or we have no
1146 common model with this pattern then reject this pattern. */
1148 ok_arch
|= opcode
->m_arch
;
1149 if (opsfound
!= opcode
->m_opnum
1150 || ((opcode
->m_arch
& current_architecture
) == 0))
1156 /* Make a copy of the operands of this insn so that
1157 we can modify them safely, should we want to. */
1158 assert (opsfound
<= (int) ARRAY_SIZE (operands_backup
));
1159 for (i
= 0; i
< opsfound
; i
++)
1160 operands_backup
[i
] = the_ins
.operands
[i
];
1162 for (s
= opcode
->m_operands
, opP
= &operands_backup
[0];
1166 /* Warning: this switch is huge! */
1167 /* I've tried to organize the cases into this order:
1168 non-alpha first, then alpha by letter. Lower-case
1169 goes directly before uppercase counterpart. */
1170 /* Code with multiple case ...: gets sorted by the lowest
1171 case ... it belongs to. I hope this makes sense. */
1277 if (opP
->reg
== PC
|| opP
->reg
== ZPC
)
1294 if (opP
->reg
== PC
|| opP
->reg
== ZPC
)
1313 if (opP
->reg
== PC
|| opP
->reg
== ZPC
)
1323 if (opP
->mode
!= IMMED
)
1325 else if (s
[1] == 'b'
1326 && ! isvar (&opP
->disp
)
1327 && (opP
->disp
.exp
.X_op
!= O_constant
1328 || ! isbyte (opP
->disp
.exp
.X_add_number
)))
1330 else if (s
[1] == 'B'
1331 && ! isvar (&opP
->disp
)
1332 && (opP
->disp
.exp
.X_op
!= O_constant
1333 || ! issbyte (opP
->disp
.exp
.X_add_number
)))
1335 else if (s
[1] == 'w'
1336 && ! isvar (&opP
->disp
)
1337 && (opP
->disp
.exp
.X_op
!= O_constant
1338 || ! isword (opP
->disp
.exp
.X_add_number
)))
1340 else if (s
[1] == 'W'
1341 && ! isvar (&opP
->disp
)
1342 && (opP
->disp
.exp
.X_op
!= O_constant
1343 || ! issword (opP
->disp
.exp
.X_add_number
)))
1349 if (opP
->mode
!= IMMED
)
1354 if (opP
->mode
== AREG
1355 || opP
->mode
== CONTROL
1356 || opP
->mode
== FPREG
1357 || opP
->mode
== IMMED
1358 || opP
->mode
== REGLST
1359 || (opP
->mode
!= ABSL
1361 || opP
->reg
== ZPC
)))
1366 if (opP
->mode
== CONTROL
1367 || opP
->mode
== FPREG
1368 || opP
->mode
== REGLST
1369 || opP
->mode
== IMMED
1370 || (opP
->mode
!= ABSL
1372 || opP
->reg
== ZPC
)))
1400 if (opP
->mode
== CONTROL
1401 || opP
->mode
== FPREG
1402 || opP
->mode
== REGLST
)
1407 if (opP
->mode
!= AINC
)
1412 if (opP
->mode
!= ADEC
)
1462 if (opP
->reg
== PC
|| opP
->reg
== ZPC
)
1483 case '~': /* For now! (JF FOO is this right?) */
1505 if (opP
->mode
!= CONTROL
1506 || (opP
->reg
!= TT0
&& opP
->reg
!= TT1
))
1511 if (opP
->mode
!= AREG
)
1516 if (opP
->mode
!= AINDR
)
1521 if (opP
->mode
!= AINDR
&& opP
->mode
!= AINC
&& opP
->mode
!= ADEC
1522 && (opP
->mode
!= DISP
1524 || opP
->reg
> ADDR7
))
1529 if (opP
->mode
!= ABSL
1531 && strncmp (instring
, "jbsr", 4) == 0))
1554 if (opP
->mode
!= CONTROL
|| opP
->reg
!= CCR
)
1559 if (opP
->mode
!= DISP
1561 || opP
->reg
> ADDR7
)
1566 if (opP
->mode
!= DREG
)
1571 if (opP
->reg
!= ACC
)
1576 if (opP
->reg
!= ACC
&& opP
->reg
!= ACC1
1577 && opP
->reg
!= ACC2
&& opP
->reg
!= ACC3
)
1582 if (opP
->mode
!= FPREG
)
1587 if (opP
->reg
!= MACSR
)
1592 if (opP
->reg
!= ACCEXT01
&& opP
->reg
!= ACCEXT23
)
1597 if (opP
->reg
!= MASK
)
1602 if (opP
->mode
!= CONTROL
1609 if (opP
->mode
!= LSH
&& opP
->mode
!= RSH
)
1614 if (opP
->mode
!= CONTROL
1616 || opP
->reg
> last_movec_reg
)
1620 const enum m68k_register
*rp
;
1621 for (rp
= control_regs
; *rp
; rp
++)
1622 if (*rp
== opP
->reg
)
1630 if (opP
->mode
!= IMMED
)
1636 if (opP
->mode
== DREG
1637 || opP
->mode
== AREG
1638 || opP
->mode
== FPREG
)
1647 opP
->mask
= 1 << (opP
->reg
- DATA0
);
1650 opP
->mask
= 1 << (opP
->reg
- ADDR0
+ 8);
1653 opP
->mask
= 1 << (opP
->reg
- FP0
+ 16);
1661 else if (opP
->mode
== CONTROL
)
1670 opP
->mask
= 1 << 24;
1673 opP
->mask
= 1 << 25;
1676 opP
->mask
= 1 << 26;
1685 else if (opP
->mode
!= REGLST
)
1687 else if (s
[1] == '8' && (opP
->mask
& 0x0ffffff) != 0)
1689 else if (s
[1] == '3' && (opP
->mask
& 0x7000000) != 0)
1694 if (opP
->mode
!= IMMED
)
1696 else if (opP
->disp
.exp
.X_op
!= O_constant
1697 || ! issbyte (opP
->disp
.exp
.X_add_number
))
1699 else if (! m68k_quick
1700 && instring
[3] != 'q'
1701 && instring
[4] != 'q')
1706 if (opP
->mode
!= DREG
1707 && opP
->mode
!= IMMED
1708 && opP
->mode
!= ABSL
)
1713 if (opP
->mode
!= IMMED
)
1715 else if (opP
->disp
.exp
.X_op
!= O_constant
1716 || TRUNC (opP
->disp
.exp
.X_add_number
) - 1 > 7)
1718 else if (! m68k_quick
1719 && (strncmp (instring
, "add", 3) == 0
1720 || strncmp (instring
, "sub", 3) == 0)
1721 && instring
[3] != 'q')
1726 if (opP
->mode
!= DREG
&& opP
->mode
!= AREG
)
1731 if (opP
->mode
!= AINDR
1732 && (opP
->mode
!= BASE
1734 && opP
->reg
!= ZADDR0
)
1735 || opP
->disp
.exp
.X_op
!= O_absent
1736 || ((opP
->index
.reg
< DATA0
1737 || opP
->index
.reg
> DATA7
)
1738 && (opP
->index
.reg
< ADDR0
1739 || opP
->index
.reg
> ADDR7
))
1740 || opP
->index
.size
!= SIZE_UNSPEC
1741 || opP
->index
.scale
!= 1))
1746 if (opP
->mode
!= CONTROL
1747 || ! (opP
->reg
== FPI
1749 || opP
->reg
== FPC
))
1754 if (opP
->mode
!= CONTROL
|| opP
->reg
!= SR
)
1759 if (opP
->mode
!= IMMED
)
1761 else if (opP
->disp
.exp
.X_op
!= O_constant
1762 || TRUNC (opP
->disp
.exp
.X_add_number
) > 7)
1767 if (opP
->mode
!= CONTROL
|| opP
->reg
!= USP
)
1772 if (opP
->mode
!= IMMED
)
1774 else if (opP
->disp
.exp
.X_op
!= O_constant
1775 || (TRUNC (opP
->disp
.exp
.X_add_number
) != 0xffffffff
1776 && TRUNC (opP
->disp
.exp
.X_add_number
) - 1 > 6))
1780 /* JF these are out of order. We could put them
1781 in order if we were willing to put up with
1782 bunches of #ifdef m68851s in the code.
1784 Don't forget that you need these operands
1785 to use 68030 MMU instructions. */
1787 /* Memory addressing mode used by pflushr. */
1789 if (opP
->mode
== CONTROL
1790 || opP
->mode
== FPREG
1791 || opP
->mode
== DREG
1792 || opP
->mode
== AREG
1793 || opP
->mode
== REGLST
)
1795 /* We should accept immediate operands, but they
1796 supposedly have to be quad word, and we don't
1797 handle that. I would like to see what a Motorola
1798 assembler does before doing something here. */
1799 if (opP
->mode
== IMMED
)
1804 if (opP
->mode
!= CONTROL
1805 || (opP
->reg
!= SFC
&& opP
->reg
!= DFC
))
1810 if (opP
->mode
!= CONTROL
|| opP
->reg
!= TC
)
1815 if (opP
->mode
!= CONTROL
|| opP
->reg
!= AC
)
1820 if (opP
->mode
!= CONTROL
1823 && opP
->reg
!= SCC
))
1828 if (opP
->mode
!= CONTROL
1834 if (opP
->mode
!= CONTROL
1837 && opP
->reg
!= CRP
))
1861 if (opP
->mode
!= CONTROL
1862 || (!(opP
->reg
>= BAD
&& opP
->reg
<= BAD
+ 7)
1863 && !(opP
->reg
>= BAC
&& opP
->reg
<= BAC
+ 7)))
1868 if (opP
->mode
!= CONTROL
|| opP
->reg
!= PSR
)
1873 if (opP
->mode
!= CONTROL
|| opP
->reg
!= PCSR
)
1878 if (opP
->mode
!= CONTROL
1887 if (opP
->mode
!= ABSL
)
1892 if (opP
->reg
< DATA0L
|| opP
->reg
> ADDR7U
)
1894 /* FIXME: kludge instead of fixing parser:
1895 upper/lower registers are *not* CONTROL
1896 registers, but ordinary ones. */
1897 if ((opP
->reg
>= DATA0L
&& opP
->reg
<= DATA7L
)
1898 || (opP
->reg
>= DATA0U
&& opP
->reg
<= DATA7U
))
1905 if (!(opP
->mode
== AINDR
1906 || (opP
->mode
== DISP
1907 && !(opP
->reg
== PC
|| opP
->reg
== ZPC
))))
1912 if (!(opP
->mode
== AINDR
|| opP
->mode
== DISP
))
1924 /* Since we have found the correct instruction, copy
1925 in the modifications that we may have made. */
1927 for (i
= 0; i
< opsfound
; i
++)
1928 the_ins
.operands
[i
] = operands_backup
[i
];
1934 opcode
= opcode
->m_next
;
1939 && !(ok_arch
& current_architecture
))
1944 _("invalid instruction for this architecture; needs "),
1946 cp
= buf
+ strlen (buf
);
1950 strncpy (cp
, _("ColdFire ISA_A"),
1951 sizeof (buf
) - (cp
- buf
));
1953 strncpy (cp
, find_cf_chip (ok_arch
),
1954 sizeof (buf
) - (cp
- buf
));
1958 strncpy (cp
, _("ColdFire hardware divide"),
1959 sizeof (buf
) - (cp
- buf
));
1961 strncpy (cp
, find_cf_chip (ok_arch
),
1962 sizeof (buf
) - (cp
- buf
));
1966 strncpy (cp
, _("ColdFire ISA_A+"),
1967 sizeof (buf
) - (cp
- buf
));
1969 strncpy (cp
, find_cf_chip (ok_arch
),
1970 sizeof (buf
) - (cp
- buf
));
1974 strncpy (cp
, _("ColdFire ISA_B"),
1975 sizeof (buf
) - (cp
- buf
));
1977 strncpy (cp
, find_cf_chip (ok_arch
),
1978 sizeof (buf
) - (cp
- buf
));
1982 strncpy (cp
, _("ColdFire fpu"), sizeof (buf
) - (cp
- buf
));
1984 strncpy (cp
, find_cf_chip (ok_arch
),
1985 sizeof (buf
) - (cp
- buf
));
1989 strcpy (cp
, _("fpu (68040, 68060 or 68881/68882)"));
1992 strcpy (cp
, _("mmu (68030 or 68851)"));
1995 strcpy (cp
, _("68020 or higher"));
1998 strcpy (cp
, _("68000 or higher"));
2001 strcpy (cp
, _("68010 or higher"));
2005 int got_one
= 0, idx
;
2007 for (idx
= 0; idx
< n_archs
; idx
++)
2009 if ((archs
[idx
].arch
& ok_arch
)
2010 && ! archs
[idx
].alias
)
2014 strcpy (cp
, " or ");
2018 strcpy (cp
, archs
[idx
].name
);
2024 cp
= xmalloc (strlen (buf
) + 1);
2029 the_ins
.error
= _("operands mismatch");
2036 /* Now assemble it. */
2037 the_ins
.args
= opcode
->m_operands
;
2038 the_ins
.numargs
= opcode
->m_opnum
;
2039 the_ins
.numo
= opcode
->m_codenum
;
2040 the_ins
.opcode
[0] = getone (opcode
);
2041 the_ins
.opcode
[1] = gettwo (opcode
);
2043 for (s
= the_ins
.args
, opP
= &the_ins
.operands
[0]; *s
; s
+= 2, opP
++)
2045 /* This switch is a doozy.
2046 Watch the first step; its a big one! */
2079 tmpreg
= 0x3c; /* 7.4 */
2080 if (strchr ("bwl", s
[1]))
2081 nextword
= get_num (&opP
->disp
, 90);
2083 nextword
= get_num (&opP
->disp
, 0);
2084 if (isvar (&opP
->disp
))
2085 add_fix (s
[1], &opP
->disp
, 0, 0);
2089 if (!isbyte (nextword
))
2090 opP
->error
= _("operand out of range");
2095 if (!isword (nextword
))
2096 opP
->error
= _("operand out of range");
2101 if (!issword (nextword
))
2102 opP
->error
= _("operand out of range");
2107 addword (nextword
>> 16);
2134 /* We gotta put out some float. */
2135 if (op (&opP
->disp
) != O_big
)
2140 /* Can other cases happen here? */
2141 if (op (&opP
->disp
) != O_constant
)
2144 val
= (valueT
) offs (&opP
->disp
);
2148 generic_bignum
[gencnt
] = (LITTLENUM_TYPE
) val
;
2149 val
>>= LITTLENUM_NUMBER_OF_BITS
;
2153 offs (&opP
->disp
) = gencnt
;
2155 if (offs (&opP
->disp
) > 0)
2157 if (offs (&opP
->disp
) > baseo
)
2159 as_warn (_("Bignum too big for %c format; truncated"),
2161 offs (&opP
->disp
) = baseo
;
2163 baseo
-= offs (&opP
->disp
);
2166 for (wordp
= generic_bignum
+ offs (&opP
->disp
) - 1;
2167 offs (&opP
->disp
)--;
2172 gen_to_words (words
, baseo
, (long) outro
);
2173 for (wordp
= words
; baseo
--; wordp
++)
2177 tmpreg
= opP
->reg
- DATA
; /* 0.dreg */
2180 tmpreg
= 0x08 + opP
->reg
- ADDR
; /* 1.areg */
2183 tmpreg
= 0x10 + opP
->reg
- ADDR
; /* 2.areg */
2186 tmpreg
= 0x20 + opP
->reg
- ADDR
; /* 4.areg */
2189 tmpreg
= 0x18 + opP
->reg
- ADDR
; /* 3.areg */
2193 nextword
= get_num (&opP
->disp
, 90);
2195 /* Convert mode 5 addressing with a zero offset into
2196 mode 2 addressing to reduce the instruction size by a
2198 if (! isvar (&opP
->disp
)
2200 && (opP
->disp
.size
== SIZE_UNSPEC
)
2201 && (opP
->reg
>= ADDR0
)
2202 && (opP
->reg
<= ADDR7
))
2204 tmpreg
= 0x10 + opP
->reg
- ADDR
; /* 2.areg */
2209 && ! isvar (&opP
->disp
)
2212 opP
->disp
.exp
.X_op
= O_symbol
;
2213 opP
->disp
.exp
.X_add_symbol
=
2214 section_symbol (absolute_section
);
2217 /* Force into index mode. Hope this works. */
2219 /* We do the first bit for 32-bit displacements, and the
2220 second bit for 16 bit ones. It is possible that we
2221 should make the default be WORD instead of LONG, but
2222 I think that'd break GCC, so we put up with a little
2223 inefficiency for the sake of working output. */
2225 if (!issword (nextword
)
2226 || (isvar (&opP
->disp
)
2227 && ((opP
->disp
.size
== SIZE_UNSPEC
2228 && flag_short_refs
== 0
2229 && cpu_of_arch (current_architecture
) >= m68020
2230 && ! arch_coldfire_p (current_architecture
))
2231 || opP
->disp
.size
== SIZE_LONG
)))
2233 if (cpu_of_arch (current_architecture
) < m68020
2234 || arch_coldfire_p (current_architecture
))
2236 _("displacement too large for this architecture; needs 68020 or higher");
2238 tmpreg
= 0x3B; /* 7.3 */
2240 tmpreg
= 0x30 + opP
->reg
- ADDR
; /* 6.areg */
2241 if (isvar (&opP
->disp
))
2245 if (opP
->disp
.size
== SIZE_LONG
2247 /* If the displacement needs pic
2248 relocation it cannot be relaxed. */
2249 || opP
->disp
.pic_reloc
!= pic_none
2254 add_fix ('l', &opP
->disp
, 1, 2);
2258 add_frag (adds (&opP
->disp
),
2259 SEXT (offs (&opP
->disp
)),
2260 TAB (PCREL1632
, SZ_UNDEF
));
2267 add_fix ('l', &opP
->disp
, 0, 0);
2272 addword (nextword
>> 16);
2277 tmpreg
= 0x3A; /* 7.2 */
2279 tmpreg
= 0x28 + opP
->reg
- ADDR
; /* 5.areg */
2281 if (isvar (&opP
->disp
))
2285 add_fix ('w', &opP
->disp
, 1, 0);
2288 add_fix ('w', &opP
->disp
, 0, 0);
2298 baseo
= get_num (&opP
->disp
, 90);
2299 if (opP
->mode
== POST
|| opP
->mode
== PRE
)
2300 outro
= get_num (&opP
->odisp
, 90);
2301 /* Figure out the `addressing mode'.
2302 Also turn on the BASE_DISABLE bit, if needed. */
2303 if (opP
->reg
== PC
|| opP
->reg
== ZPC
)
2305 tmpreg
= 0x3b; /* 7.3 */
2306 if (opP
->reg
== ZPC
)
2309 else if (opP
->reg
== 0)
2312 tmpreg
= 0x30; /* 6.garbage */
2314 else if (opP
->reg
>= ZADDR0
&& opP
->reg
<= ZADDR7
)
2317 tmpreg
= 0x30 + opP
->reg
- ZADDR0
;
2320 tmpreg
= 0x30 + opP
->reg
- ADDR
; /* 6.areg */
2322 siz1
= opP
->disp
.size
;
2323 if (opP
->mode
== POST
|| opP
->mode
== PRE
)
2324 siz2
= opP
->odisp
.size
;
2328 /* Index register stuff. */
2329 if (opP
->index
.reg
!= 0
2330 && opP
->index
.reg
>= DATA
2331 && opP
->index
.reg
<= ADDR7
)
2333 nextword
|= (opP
->index
.reg
- DATA
) << 12;
2335 if (opP
->index
.size
== SIZE_LONG
2336 || (opP
->index
.size
== SIZE_UNSPEC
2337 && m68k_index_width_default
== SIZE_LONG
))
2340 if ((opP
->index
.scale
!= 1
2341 && cpu_of_arch (current_architecture
) < m68020
)
2342 || (opP
->index
.scale
== 8
2343 && (arch_coldfire_p (current_architecture
)
2344 && !arch_coldfire_fpu (current_architecture
))))
2347 _("scale factor invalid on this architecture; needs cpu32 or 68020 or higher");
2350 if (arch_coldfire_p (current_architecture
)
2351 && opP
->index
.size
== SIZE_WORD
)
2352 opP
->error
= _("invalid index size for coldfire");
2354 switch (opP
->index
.scale
)
2371 GET US OUT OF HERE! */
2373 /* Must be INDEX, with an index register. Address
2374 register cannot be ZERO-PC, and either :b was
2375 forced, or we know it will fit. For a 68000 or
2376 68010, force this mode anyways, because the
2377 larger modes aren't supported. */
2378 if (opP
->mode
== BASE
2379 && ((opP
->reg
>= ADDR0
2380 && opP
->reg
<= ADDR7
)
2383 if (siz1
== SIZE_BYTE
2384 || cpu_of_arch (current_architecture
) < m68020
2385 || arch_coldfire_p (current_architecture
)
2386 || (siz1
== SIZE_UNSPEC
2387 && ! isvar (&opP
->disp
)
2388 && issbyte (baseo
)))
2390 nextword
+= baseo
& 0xff;
2392 if (isvar (&opP
->disp
))
2394 /* Do a byte relocation. If it doesn't
2395 fit (possible on m68000) let the
2396 fixup processing complain later. */
2398 add_fix ('B', &opP
->disp
, 1, 1);
2400 add_fix ('B', &opP
->disp
, 0, 0);
2402 else if (siz1
!= SIZE_BYTE
)
2404 if (siz1
!= SIZE_UNSPEC
)
2405 as_warn (_("Forcing byte displacement"));
2406 if (! issbyte (baseo
))
2407 opP
->error
= _("byte displacement out of range");
2412 else if (siz1
== SIZE_UNSPEC
2414 && isvar (&opP
->disp
)
2415 && subs (&opP
->disp
) == NULL
2417 /* If the displacement needs pic
2418 relocation it cannot be relaxed. */
2419 && opP
->disp
.pic_reloc
== pic_none
2423 /* The code in md_convert_frag_1 needs to be
2424 able to adjust nextword. Call frag_grow
2425 to ensure that we have enough space in
2426 the frag obstack to make all the bytes
2429 nextword
+= baseo
& 0xff;
2431 add_frag (adds (&opP
->disp
),
2432 SEXT (offs (&opP
->disp
)),
2433 TAB (PCINDEX
, SZ_UNDEF
));
2441 nextword
|= 0x40; /* No index reg. */
2442 if (opP
->index
.reg
>= ZDATA0
2443 && opP
->index
.reg
<= ZDATA7
)
2444 nextword
|= (opP
->index
.reg
- ZDATA0
) << 12;
2445 else if (opP
->index
.reg
>= ZADDR0
2446 || opP
->index
.reg
<= ZADDR7
)
2447 nextword
|= (opP
->index
.reg
- ZADDR0
+ 8) << 12;
2450 /* It isn't simple. */
2452 if (cpu_of_arch (current_architecture
) < m68020
2453 || arch_coldfire_p (current_architecture
))
2455 _("invalid operand mode for this architecture; needs 68020 or higher");
2458 /* If the guy specified a width, we assume that it is
2459 wide enough. Maybe it isn't. If so, we lose. */
2463 if (isvar (&opP
->disp
)
2465 : ! issword (baseo
))
2470 else if (! isvar (&opP
->disp
) && baseo
== 0)
2479 as_warn (_(":b not permitted; defaulting to :w"));
2489 /* Figure out inner displacement stuff. */
2490 if (opP
->mode
== POST
|| opP
->mode
== PRE
)
2492 if (cpu_of_arch (current_architecture
) & cpu32
)
2493 opP
->error
= _("invalid operand mode for this architecture; needs 68020 or higher");
2497 if (isvar (&opP
->odisp
)
2499 : ! issword (outro
))
2504 else if (! isvar (&opP
->odisp
) && outro
== 0)
2513 as_warn (_(":b not permitted; defaulting to :w"));
2522 if (opP
->mode
== POST
2523 && (nextword
& 0x40) == 0)
2528 if (siz1
!= SIZE_UNSPEC
&& isvar (&opP
->disp
))
2530 if (opP
->reg
== PC
|| opP
->reg
== ZPC
)
2531 add_fix (siz1
== SIZE_LONG
? 'l' : 'w', &opP
->disp
, 1, 2);
2533 add_fix (siz1
== SIZE_LONG
? 'l' : 'w', &opP
->disp
, 0, 0);
2535 if (siz1
== SIZE_LONG
)
2536 addword (baseo
>> 16);
2537 if (siz1
!= SIZE_UNSPEC
)
2540 if (siz2
!= SIZE_UNSPEC
&& isvar (&opP
->odisp
))
2541 add_fix (siz2
== SIZE_LONG
? 'l' : 'w', &opP
->odisp
, 0, 0);
2542 if (siz2
== SIZE_LONG
)
2543 addword (outro
>> 16);
2544 if (siz2
!= SIZE_UNSPEC
)
2550 nextword
= get_num (&opP
->disp
, 90);
2551 switch (opP
->disp
.size
)
2556 if (!isvar (&opP
->disp
) && issword (offs (&opP
->disp
)))
2558 tmpreg
= 0x38; /* 7.0 */
2562 if (isvar (&opP
->disp
)
2563 && !subs (&opP
->disp
)
2564 && adds (&opP
->disp
)
2566 /* If the displacement needs pic relocation it
2567 cannot be relaxed. */
2568 && opP
->disp
.pic_reloc
== pic_none
2571 && !strchr ("~%&$?", s
[0]))
2573 tmpreg
= 0x3A; /* 7.2 */
2574 add_frag (adds (&opP
->disp
),
2575 SEXT (offs (&opP
->disp
)),
2576 TAB (ABSTOPCREL
, SZ_UNDEF
));
2579 /* Fall through into long. */
2581 if (isvar (&opP
->disp
))
2582 add_fix ('l', &opP
->disp
, 0, 0);
2584 tmpreg
= 0x39;/* 7.1 mode */
2585 addword (nextword
>> 16);
2590 as_bad (_("unsupported byte value; use a different suffix"));
2594 if (isvar (&opP
->disp
))
2595 add_fix ('w', &opP
->disp
, 0, 0);
2597 tmpreg
= 0x38;/* 7.0 mode */
2605 as_bad (_("unknown/incorrect operand"));
2609 /* If s[0] is '4', then this is for the mac instructions
2610 that can have a trailing_ampersand set. If so, set 0x100
2611 bit on tmpreg so install_gen_operand can check for it and
2612 set the appropriate bit (word2, bit 5). */
2615 if (opP
->trailing_ampersand
)
2618 install_gen_operand (s
[1], tmpreg
);
2624 { /* JF: I hate floating point! */
2639 tmpreg
= get_num (&opP
->disp
, tmpreg
);
2640 if (isvar (&opP
->disp
))
2641 add_fix (s
[1], &opP
->disp
, 0, 0);
2644 case 'b': /* Danger: These do no check for
2645 certain types of overflow.
2647 if (!isbyte (tmpreg
))
2648 opP
->error
= _("out of range");
2649 insop (tmpreg
, opcode
);
2650 if (isvar (&opP
->disp
))
2651 the_ins
.reloc
[the_ins
.nrel
- 1].n
=
2652 (opcode
->m_codenum
) * 2 + 1;
2655 if (!issbyte (tmpreg
))
2656 opP
->error
= _("out of range");
2657 the_ins
.opcode
[the_ins
.numo
- 1] |= tmpreg
& 0xff;
2658 if (isvar (&opP
->disp
))
2659 the_ins
.reloc
[the_ins
.nrel
- 1].n
= opcode
->m_codenum
* 2 - 1;
2662 if (!isword (tmpreg
))
2663 opP
->error
= _("out of range");
2664 insop (tmpreg
, opcode
);
2665 if (isvar (&opP
->disp
))
2666 the_ins
.reloc
[the_ins
.nrel
- 1].n
= (opcode
->m_codenum
) * 2;
2669 if (!issword (tmpreg
))
2670 opP
->error
= _("out of range");
2671 insop (tmpreg
, opcode
);
2672 if (isvar (&opP
->disp
))
2673 the_ins
.reloc
[the_ins
.nrel
- 1].n
= (opcode
->m_codenum
) * 2;
2676 /* Because of the way insop works, we put these two out
2678 insop (tmpreg
, opcode
);
2679 insop (tmpreg
>> 16, opcode
);
2680 if (isvar (&opP
->disp
))
2681 the_ins
.reloc
[the_ins
.nrel
- 1].n
= (opcode
->m_codenum
) * 2;
2688 install_operand (s
[1], tmpreg
);
2699 install_operand (s
[1], opP
->reg
- ADDR
);
2703 tmpreg
= get_num (&opP
->disp
, 90);
2707 add_fix ('B', &opP
->disp
, 1, -1);
2710 add_fix ('w', &opP
->disp
, 1, 0);
2715 if (! HAVE_LONG_BRANCH (current_architecture
))
2716 as_warn (_("Can't use long branches on 68000/68010/5200"));
2717 the_ins
.opcode
[0] |= 0xff;
2718 add_fix ('l', &opP
->disp
, 1, 0);
2723 if (subs (&opP
->disp
)) /* We can't relax it. */
2727 /* If the displacement needs pic relocation it cannot be
2729 if (opP
->disp
.pic_reloc
!= pic_none
)
2732 /* This could either be a symbol, or an absolute
2733 address. If it's an absolute address, turn it into
2734 an absolute jump right here and keep it out of the
2736 if (adds (&opP
->disp
) == 0)
2738 if (the_ins
.opcode
[0] == 0x6000) /* jbra */
2739 the_ins
.opcode
[0] = 0x4EF9;
2740 else if (the_ins
.opcode
[0] == 0x6100) /* jbsr */
2741 the_ins
.opcode
[0] = 0x4EB9;
2744 the_ins
.opcode
[0] ^= 0x0100;
2745 the_ins
.opcode
[0] |= 0x0006;
2748 add_fix ('l', &opP
->disp
, 0, 0);
2754 /* Now we know it's going into the relaxer. Now figure
2755 out which mode. We try in this order of preference:
2756 long branch, absolute jump, byte/word branches only. */
2757 if (HAVE_LONG_BRANCH (current_architecture
))
2758 add_frag (adds (&opP
->disp
),
2759 SEXT (offs (&opP
->disp
)),
2760 TAB (BRANCHBWL
, SZ_UNDEF
));
2761 else if (! flag_keep_pcrel
)
2763 if ((the_ins
.opcode
[0] == 0x6000)
2764 || (the_ins
.opcode
[0] == 0x6100))
2765 add_frag (adds (&opP
->disp
),
2766 SEXT (offs (&opP
->disp
)),
2767 TAB (BRABSJUNC
, SZ_UNDEF
));
2769 add_frag (adds (&opP
->disp
),
2770 SEXT (offs (&opP
->disp
)),
2771 TAB (BRABSJCOND
, SZ_UNDEF
));
2774 add_frag (adds (&opP
->disp
),
2775 SEXT (offs (&opP
->disp
)),
2776 TAB (BRANCHBW
, SZ_UNDEF
));
2779 if (isvar (&opP
->disp
))
2781 /* Check for DBcc instructions. We can relax them,
2782 but only if we have long branches and/or absolute
2784 if (((the_ins
.opcode
[0] & 0xf0f8) == 0x50c8)
2785 && (HAVE_LONG_BRANCH (current_architecture
)
2786 || (! flag_keep_pcrel
)))
2788 if (HAVE_LONG_BRANCH (current_architecture
))
2789 add_frag (adds (&opP
->disp
),
2790 SEXT (offs (&opP
->disp
)),
2791 TAB (DBCCLBR
, SZ_UNDEF
));
2793 add_frag (adds (&opP
->disp
),
2794 SEXT (offs (&opP
->disp
)),
2795 TAB (DBCCABSJ
, SZ_UNDEF
));
2798 add_fix ('w', &opP
->disp
, 1, 0);
2802 case 'C': /* Fixed size LONG coproc branches. */
2803 add_fix ('l', &opP
->disp
, 1, 0);
2807 case 'c': /* Var size Coprocesssor branches. */
2808 if (subs (&opP
->disp
) || (adds (&opP
->disp
) == 0))
2810 the_ins
.opcode
[the_ins
.numo
- 1] |= 0x40;
2811 add_fix ('l', &opP
->disp
, 1, 0);
2816 add_frag (adds (&opP
->disp
),
2817 SEXT (offs (&opP
->disp
)),
2818 TAB (FBRANCH
, SZ_UNDEF
));
2825 case 'C': /* Ignore it. */
2828 case 'd': /* JF this is a kludge. */
2829 install_operand ('s', opP
->reg
- ADDR
);
2830 tmpreg
= get_num (&opP
->disp
, 90);
2831 if (!issword (tmpreg
))
2833 as_warn (_("Expression out of range, using 0"));
2840 install_operand (s
[1], opP
->reg
- DATA
);
2843 case 'e': /* EMAC ACCx, reg/reg. */
2844 install_operand (s
[1], opP
->reg
- ACC
);
2847 case 'E': /* Ignore it. */
2851 install_operand (s
[1], opP
->reg
- FP0
);
2854 case 'g': /* EMAC ACCEXTx. */
2855 install_operand (s
[1], opP
->reg
- ACCEXT01
);
2858 case 'G': /* Ignore it. */
2863 tmpreg
= opP
->reg
- COP0
;
2864 install_operand (s
[1], tmpreg
);
2867 case 'i': /* MAC/EMAC scale factor. */
2868 install_operand (s
[1], opP
->mode
== LSH
? 0x1 : 0x3);
2871 case 'J': /* JF foo. */
3001 install_operand (s
[1], tmpreg
);
3005 tmpreg
= get_num (&opP
->disp
, 55);
3006 install_operand (s
[1], tmpreg
& 0x7f);
3013 if (tmpreg
& 0x7FF0000)
3014 as_bad (_("Floating point register in register list"));
3015 insop (reverse_16_bits (tmpreg
), opcode
);
3019 if (tmpreg
& 0x700FFFF)
3020 as_bad (_("Wrong register in floating-point reglist"));
3021 install_operand (s
[1], reverse_8_bits (tmpreg
>> 16));
3029 if (tmpreg
& 0x7FF0000)
3030 as_bad (_("Floating point register in register list"));
3031 insop (tmpreg
, opcode
);
3033 else if (s
[1] == '8')
3035 if (tmpreg
& 0x0FFFFFF)
3036 as_bad (_("incorrect register in reglist"));
3037 install_operand (s
[1], tmpreg
>> 24);
3041 if (tmpreg
& 0x700FFFF)
3042 as_bad (_("wrong register in floating-point reglist"));
3044 install_operand (s
[1], tmpreg
>> 16);
3049 install_operand (s
[1], get_num (&opP
->disp
, 60));
3053 tmpreg
= ((opP
->mode
== DREG
)
3054 ? 0x20 + (int) (opP
->reg
- DATA
)
3055 : (get_num (&opP
->disp
, 40) & 0x1F));
3056 install_operand (s
[1], tmpreg
);
3060 tmpreg
= get_num (&opP
->disp
, 10);
3063 install_operand (s
[1], tmpreg
);
3067 /* This depends on the fact that ADDR registers are eight
3068 more than their corresponding DATA regs, so the result
3069 will have the ADDR_REG bit set. */
3070 install_operand (s
[1], opP
->reg
- DATA
);
3074 if (opP
->mode
== AINDR
)
3075 install_operand (s
[1], opP
->reg
- DATA
);
3077 install_operand (s
[1], opP
->index
.reg
- DATA
);
3081 if (opP
->reg
== FPI
)
3083 else if (opP
->reg
== FPS
)
3085 else if (opP
->reg
== FPC
)
3089 install_operand (s
[1], tmpreg
);
3092 case 'S': /* Ignore it. */
3096 install_operand (s
[1], get_num (&opP
->disp
, 30));
3099 case 'U': /* Ignore it. */
3118 as_fatal (_("failed sanity check"));
3119 } /* switch on cache token. */
3120 install_operand (s
[1], tmpreg
);
3123 /* JF: These are out of order, I fear. */
3136 install_operand (s
[1], tmpreg
);
3162 install_operand (s
[1], tmpreg
);
3166 if (opP
->reg
== VAL
)
3185 install_operand (s
[1], tmpreg
);
3199 tmpreg
= (4 << 10) | ((opP
->reg
- BAD
) << 2);
3210 tmpreg
= (5 << 10) | ((opP
->reg
- BAC
) << 2);
3216 install_operand (s
[1], tmpreg
);
3219 know (opP
->reg
== PSR
);
3222 know (opP
->reg
== PCSR
);
3237 install_operand (s
[1], tmpreg
);
3240 tmpreg
= get_num (&opP
->disp
, 20);
3241 install_operand (s
[1], tmpreg
);
3243 case '_': /* used only for move16 absolute 32-bit address. */
3244 if (isvar (&opP
->disp
))
3245 add_fix ('l', &opP
->disp
, 0, 0);
3246 tmpreg
= get_num (&opP
->disp
, 90);
3247 addword (tmpreg
>> 16);
3248 addword (tmpreg
& 0xFFFF);
3251 install_operand (s
[1], opP
->reg
- DATA0L
);
3252 opP
->reg
-= (DATA0L
);
3253 opP
->reg
&= 0x0F; /* remove upper/lower bit. */
3256 tmpreg
= get_num (&opP
->disp
, 80);
3259 install_operand (s
[1], tmpreg
);
3266 /* By the time whe get here (FINALLY) the_ins contains the complete
3267 instruction, ready to be emitted. . . */
3271 reverse_16_bits (int in
)
3276 static int mask
[16] =
3278 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
3279 0x0100, 0x0200, 0x0400, 0x0800, 0x1000, 0x2000, 0x4000, 0x8000
3281 for (n
= 0; n
< 16; n
++)
3284 out
|= mask
[15 - n
];
3287 } /* reverse_16_bits() */
3290 reverse_8_bits (int in
)
3295 static int mask
[8] =
3297 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
3300 for (n
= 0; n
< 8; n
++)
3306 } /* reverse_8_bits() */
3308 /* Cause an extra frag to be generated here, inserting up to 10 bytes
3309 (that value is chosen in the frag_var call in md_assemble). TYPE
3310 is the subtype of the frag to be generated; its primary type is
3311 rs_machine_dependent.
3313 The TYPE parameter is also used by md_convert_frag_1 and
3314 md_estimate_size_before_relax. The appropriate type of fixup will
3315 be emitted by md_convert_frag_1.
3317 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
3319 install_operand (int mode
, int val
)
3324 the_ins
.opcode
[0] |= val
& 0xFF; /* JF FF is for M kludge. */
3327 the_ins
.opcode
[0] |= val
<< 9;
3330 the_ins
.opcode
[1] |= val
<< 12;
3333 the_ins
.opcode
[1] |= val
<< 6;
3336 the_ins
.opcode
[1] |= val
;
3339 the_ins
.opcode
[2] |= val
<< 12;
3342 the_ins
.opcode
[2] |= val
<< 6;
3345 /* DANGER! This is a hack to force cas2l and cas2w cmds to be
3346 three words long! */
3348 the_ins
.opcode
[2] |= val
;
3351 the_ins
.opcode
[1] |= val
<< 7;
3354 the_ins
.opcode
[1] |= val
<< 10;
3358 the_ins
.opcode
[1] |= val
<< 5;
3363 the_ins
.opcode
[1] |= (val
<< 10) | (val
<< 7);
3366 the_ins
.opcode
[1] |= (val
<< 12) | val
;
3369 the_ins
.opcode
[0] |= val
= 0xff;
3372 the_ins
.opcode
[0] |= val
<< 9;
3375 the_ins
.opcode
[1] |= val
;
3378 the_ins
.opcode
[1] |= val
;
3379 the_ins
.numo
++; /* What a hack. */
3382 the_ins
.opcode
[1] |= val
<< 4;
3390 the_ins
.opcode
[0] |= (val
<< 6);
3393 the_ins
.opcode
[1] = (val
>> 16);
3394 the_ins
.opcode
[2] = val
& 0xffff;
3397 the_ins
.opcode
[0] |= ((val
& 0x8) << (6 - 3));
3398 the_ins
.opcode
[0] |= ((val
& 0x7) << 9);
3399 the_ins
.opcode
[1] |= ((val
& 0x10) << (7 - 4));
3401 case 'n': /* MAC/EMAC Rx on !load. */
3402 the_ins
.opcode
[0] |= ((val
& 0x8) << (6 - 3));
3403 the_ins
.opcode
[0] |= ((val
& 0x7) << 9);
3404 the_ins
.opcode
[1] |= ((val
& 0x10) << (7 - 4));
3406 case 'o': /* MAC/EMAC Rx on load. */
3407 the_ins
.opcode
[1] |= val
<< 12;
3408 the_ins
.opcode
[1] |= ((val
& 0x10) << (7 - 4));
3410 case 'M': /* MAC/EMAC Ry on !load. */
3411 the_ins
.opcode
[0] |= (val
& 0xF);
3412 the_ins
.opcode
[1] |= ((val
& 0x10) << (6 - 4));
3414 case 'N': /* MAC/EMAC Ry on load. */
3415 the_ins
.opcode
[1] |= (val
& 0xF);
3416 the_ins
.opcode
[1] |= ((val
& 0x10) << (6 - 4));
3419 the_ins
.opcode
[1] |= ((val
!= 1) << 10);
3422 the_ins
.opcode
[0] |= ((val
& 0x3) << 9);
3425 the_ins
.opcode
[0] |= ((val
& 0x3) << 0);
3427 case 'G': /* EMAC accumulator in a EMAC load instruction. */
3428 the_ins
.opcode
[0] |= ((~val
& 0x1) << 7);
3429 the_ins
.opcode
[1] |= ((val
& 0x2) << (4 - 1));
3431 case 'H': /* EMAC accumulator in a EMAC non-load instruction. */
3432 the_ins
.opcode
[0] |= ((val
& 0x1) << 7);
3433 the_ins
.opcode
[1] |= ((val
& 0x2) << (4 - 1));
3436 the_ins
.opcode
[1] |= ((val
& 0x3) << 9);
3439 the_ins
.opcode
[0] |= (val
& 0x1) <<10;
3443 as_fatal (_("failed sanity check."));
3448 install_gen_operand (int mode
, int val
)
3452 case '/': /* Special for mask loads for mac/msac insns with
3453 possible mask; trailing_ampersend set in bit 8. */
3454 the_ins
.opcode
[0] |= (val
& 0x3f);
3455 the_ins
.opcode
[1] |= (((val
& 0x100) >> 8) << 5);
3458 the_ins
.opcode
[0] |= val
;
3461 /* This is a kludge!!! */
3462 the_ins
.opcode
[0] |= (val
& 0x07) << 9 | (val
& 0x38) << 3;
3471 the_ins
.opcode
[0] |= val
;
3473 /* more stuff goes here. */
3475 as_fatal (_("failed sanity check."));
3479 /* Verify that we have some number of paren pairs, do m68k_ip_op(), and
3480 then deal with the bitfield hack. */
3483 crack_operand (char *str
, struct m68k_op
*opP
)
3485 register int parens
;
3487 register char *beg_str
;
3495 for (parens
= 0; *str
&& (parens
> 0 || inquote
|| notend (str
)); str
++)
3501 else if (*str
== ')')
3505 opP
->error
= _("Extra )");
3511 if (flag_mri
&& *str
== '\'')
3512 inquote
= ! inquote
;
3514 if (!*str
&& parens
)
3516 opP
->error
= _("Missing )");
3521 if (m68k_ip_op (beg_str
, opP
) != 0)
3528 c
= *++str
; /* JF bitfield hack. */
3533 as_bad (_("Missing operand"));
3536 /* Detect MRI REG symbols and convert them to REGLSTs. */
3537 if (opP
->mode
== CONTROL
&& (int)opP
->reg
< 0)
3540 opP
->mask
= ~(int)opP
->reg
;
3547 /* This is the guts of the machine-dependent assembler. STR points to a
3548 machine dependent instruction. This function is supposed to emit
3549 the frags/bytes it assembles to.
3553 insert_reg (const char *regname
, int regnum
)
3558 #ifdef REGISTER_PREFIX
3559 if (!flag_reg_prefix_optional
)
3561 buf
[0] = REGISTER_PREFIX
;
3562 strcpy (buf
+ 1, regname
);
3567 symbol_table_insert (symbol_new (regname
, reg_section
, regnum
,
3568 &zero_address_frag
));
3570 for (i
= 0; regname
[i
]; i
++)
3571 buf
[i
] = TOUPPER (regname
[i
]);
3574 symbol_table_insert (symbol_new (buf
, reg_section
, regnum
,
3575 &zero_address_frag
));
3584 static const struct init_entry init_table
[] =
3644 { "accext01", ACCEXT01
},
3645 { "accext23", ACCEXT23
},
3649 /* Control registers. */
3650 { "sfc", SFC
}, /* Source Function Code. */
3652 { "dfc", DFC
}, /* Destination Function Code. */
3654 { "cacr", CACR
}, /* Cache Control Register. */
3655 { "caar", CAAR
}, /* Cache Address Register. */
3657 { "usp", USP
}, /* User Stack Pointer. */
3658 { "vbr", VBR
}, /* Vector Base Register. */
3659 { "msp", MSP
}, /* Master Stack Pointer. */
3660 { "isp", ISP
}, /* Interrupt Stack Pointer. */
3662 { "itt0", ITT0
}, /* Instruction Transparent Translation Reg 0. */
3663 { "itt1", ITT1
}, /* Instruction Transparent Translation Reg 1. */
3664 { "dtt0", DTT0
}, /* Data Transparent Translation Register 0. */
3665 { "dtt1", DTT1
}, /* Data Transparent Translation Register 1. */
3667 /* 68ec040 versions of same */
3668 { "iacr0", ITT0
}, /* Instruction Access Control Register 0. */
3669 { "iacr1", ITT1
}, /* Instruction Access Control Register 0. */
3670 { "dacr0", DTT0
}, /* Data Access Control Register 0. */
3671 { "dacr1", DTT1
}, /* Data Access Control Register 0. */
3673 /* mcf5200 versions of same. The ColdFire programmer's reference
3674 manual indicated that the order is 2,3,0,1, but Ken Rose
3675 <rose@netcom.com> says that 0,1,2,3 is the correct order. */
3676 { "acr0", ACR0
}, /* Access Control Unit 0. */
3677 { "acr1", ACR1
}, /* Access Control Unit 1. */
3678 { "acr2", ACR2
}, /* Access Control Unit 2. */
3679 { "acr3", ACR3
}, /* Access Control Unit 3. */
3681 { "tc", TC
}, /* MMU Translation Control Register. */
3684 { "mmusr", MMUSR
}, /* MMU Status Register. */
3685 { "srp", SRP
}, /* User Root Pointer. */
3686 { "urp", URP
}, /* Supervisor Root Pointer. */
3691 { "rombar", ROMBAR
}, /* ROM Base Address Register. */
3692 { "rambar0", RAMBAR0
}, /* ROM Base Address Register. */
3693 { "rambar1", RAMBAR1
}, /* ROM Base Address Register. */
3694 { "mbar", MBAR
}, /* Module Base Address Register. */
3696 { "mbar0", MBAR0
}, /* mcfv4e registers. */
3697 { "mbar1", MBAR1
}, /* mcfv4e registers. */
3698 { "rombar0", ROMBAR
}, /* mcfv4e registers. */
3699 { "rombar1", ROMBAR1
}, /* mcfv4e registers. */
3700 { "mpcr", MPCR
}, /* mcfv4e registers. */
3701 { "edrambar", EDRAMBAR
}, /* mcfv4e registers. */
3702 { "secmbar", SECMBAR
}, /* mcfv4e registers. */
3703 { "asid", TC
}, /* mcfv4e registers. */
3704 { "mmubar", BUSCR
}, /* mcfv4e registers. */
3705 { "pcr1u0", PCR1U0
}, /* mcfv4e registers. */
3706 { "pcr1l0", PCR1L0
}, /* mcfv4e registers. */
3707 { "pcr2u0", PCR2U0
}, /* mcfv4e registers. */
3708 { "pcr2l0", PCR2L0
}, /* mcfv4e registers. */
3709 { "pcr3u0", PCR3U0
}, /* mcfv4e registers. */
3710 { "pcr3l0", PCR3L0
}, /* mcfv4e registers. */
3711 { "pcr1u1", PCR1U1
}, /* mcfv4e registers. */
3712 { "pcr1l1", PCR1L1
}, /* mcfv4e registers. */
3713 { "pcr2u1", PCR2U1
}, /* mcfv4e registers. */
3714 { "pcr2l1", PCR2L1
}, /* mcfv4e registers. */
3715 { "pcr3u1", PCR3U1
}, /* mcfv4e registers. */
3716 { "pcr3l1", PCR3L1
}, /* mcfv4e registers. */
3718 { "flashbar", FLASHBAR
}, /* mcf528x registers. */
3719 { "rambar", RAMBAR
}, /* mcf528x registers. */
3721 { "mbar2", MBAR2
}, /* mcf5249 registers. */
3722 /* End of control registers. */
3756 /* 68ec030 versions of same. */
3759 /* 68ec030 access control unit, identical to 030 MMU status reg. */
3762 /* Suppressed data and address registers. */
3780 /* Upper and lower data and address registers, used by macw and msacw. */
3821 init_regtable (void)
3824 for (i
= 0; init_table
[i
].name
; i
++)
3825 insert_reg (init_table
[i
].name
, init_table
[i
].number
);
3828 static int no_68851
, no_68881
;
3831 md_assemble (char *str
)
3838 int shorts_this_frag
;
3841 /* In MRI mode, the instruction and operands are separated by a
3842 space. Anything following the operands is a comment. The label
3843 has already been removed. */
3851 for (s
= str
; *s
!= '\0'; s
++)
3853 if ((*s
== ' ' || *s
== '\t') && ! inquote
)
3871 inquote
= ! inquote
;
3876 memset (&the_ins
, '\0', sizeof (the_ins
));
3881 for (n
= 0; n
< the_ins
.numargs
; n
++)
3882 if (the_ins
.operands
[n
].error
)
3884 er
= the_ins
.operands
[n
].error
;
3890 as_bad (_("%s -- statement `%s' ignored"), er
, str
);
3894 /* If there is a current label, record that it marks an instruction. */
3895 if (current_label
!= NULL
)
3897 current_label
->text
= 1;
3898 current_label
= NULL
;
3902 /* Tie dwarf2 debug info to the address at the start of the insn. */
3903 dwarf2_emit_insn (0);
3906 if (the_ins
.nfrag
== 0)
3908 /* No frag hacking involved; just put it out. */
3909 toP
= frag_more (2 * the_ins
.numo
);
3910 fromP
= &the_ins
.opcode
[0];
3911 for (m
= the_ins
.numo
; m
; --m
)
3913 md_number_to_chars (toP
, (long) (*fromP
), 2);
3917 /* Put out symbol-dependent info. */
3918 for (m
= 0; m
< the_ins
.nrel
; m
++)
3920 switch (the_ins
.reloc
[m
].wid
)
3939 as_fatal (_("Don't know how to figure width of %c in md_assemble()"),
3940 the_ins
.reloc
[m
].wid
);
3943 fixP
= fix_new_exp (frag_now
,
3944 ((toP
- frag_now
->fr_literal
)
3945 - the_ins
.numo
* 2 + the_ins
.reloc
[m
].n
),
3947 &the_ins
.reloc
[m
].exp
,
3948 the_ins
.reloc
[m
].pcrel
,
3949 get_reloc_code (n
, the_ins
.reloc
[m
].pcrel
,
3950 the_ins
.reloc
[m
].pic_reloc
));
3951 fixP
->fx_pcrel_adjust
= the_ins
.reloc
[m
].pcrel_fix
;
3952 if (the_ins
.reloc
[m
].wid
== 'B')
3953 fixP
->fx_signed
= 1;
3958 /* There's some frag hacking. */
3960 /* Calculate the max frag size. */
3963 wid
= 2 * the_ins
.fragb
[0].fragoff
;
3964 for (n
= 1; n
< the_ins
.nfrag
; n
++)
3965 wid
+= 2 * (the_ins
.numo
- the_ins
.fragb
[n
- 1].fragoff
);
3966 /* frag_var part. */
3968 /* Make sure the whole insn fits in one chunk, in particular that
3969 the var part is attached, as we access one byte before the
3970 variable frag for byte branches. */
3974 for (n
= 0, fromP
= &the_ins
.opcode
[0]; n
< the_ins
.nfrag
; n
++)
3979 wid
= 2 * the_ins
.fragb
[n
].fragoff
;
3981 wid
= 2 * (the_ins
.numo
- the_ins
.fragb
[n
- 1].fragoff
);
3982 toP
= frag_more (wid
);
3984 shorts_this_frag
= 0;
3985 for (m
= wid
/ 2; m
; --m
)
3987 md_number_to_chars (toP
, (long) (*fromP
), 2);
3992 for (m
= 0; m
< the_ins
.nrel
; m
++)
3994 if ((the_ins
.reloc
[m
].n
) >= 2 * shorts_this_frag
)
3996 the_ins
.reloc
[m
].n
-= 2 * shorts_this_frag
;
3999 wid
= the_ins
.reloc
[m
].wid
;
4002 the_ins
.reloc
[m
].wid
= 0;
4003 wid
= (wid
== 'b') ? 1 : (wid
== 'w') ? 2 : (wid
== 'l') ? 4 : 4000;
4005 fixP
= fix_new_exp (frag_now
,
4006 ((toP
- frag_now
->fr_literal
)
4007 - the_ins
.numo
* 2 + the_ins
.reloc
[m
].n
),
4009 &the_ins
.reloc
[m
].exp
,
4010 the_ins
.reloc
[m
].pcrel
,
4011 get_reloc_code (wid
, the_ins
.reloc
[m
].pcrel
,
4012 the_ins
.reloc
[m
].pic_reloc
));
4013 fixP
->fx_pcrel_adjust
= the_ins
.reloc
[m
].pcrel_fix
;
4015 (void) frag_var (rs_machine_dependent
, 10, 0,
4016 (relax_substateT
) (the_ins
.fragb
[n
].fragty
),
4017 the_ins
.fragb
[n
].fadd
, the_ins
.fragb
[n
].foff
, to_beg_P
);
4019 n
= (the_ins
.numo
- the_ins
.fragb
[n
- 1].fragoff
);
4020 shorts_this_frag
= 0;
4023 toP
= frag_more (n
* 2);
4026 md_number_to_chars (toP
, (long) (*fromP
), 2);
4032 for (m
= 0; m
< the_ins
.nrel
; m
++)
4036 wid
= the_ins
.reloc
[m
].wid
;
4039 the_ins
.reloc
[m
].wid
= 0;
4040 wid
= (wid
== 'b') ? 1 : (wid
== 'w') ? 2 : (wid
== 'l') ? 4 : 4000;
4042 fixP
= fix_new_exp (frag_now
,
4043 ((the_ins
.reloc
[m
].n
+ toP
- frag_now
->fr_literal
)
4044 - shorts_this_frag
* 2),
4046 &the_ins
.reloc
[m
].exp
,
4047 the_ins
.reloc
[m
].pcrel
,
4048 get_reloc_code (wid
, the_ins
.reloc
[m
].pcrel
,
4049 the_ins
.reloc
[m
].pic_reloc
));
4050 fixP
->fx_pcrel_adjust
= the_ins
.reloc
[m
].pcrel_fix
;
4054 /* Comparison function used by qsort to rank the opcode entries by name. */
4057 m68k_compare_opcode (const void * v1
, const void * v2
)
4059 struct m68k_opcode
* op1
, * op2
;
4065 op1
= *(struct m68k_opcode
**) v1
;
4066 op2
= *(struct m68k_opcode
**) v2
;
4068 /* Compare the two names. If different, return the comparison.
4069 If the same, return the order they are in the opcode table. */
4070 ret
= strcmp (op1
->name
, op2
->name
);
4081 const struct m68k_opcode
*ins
;
4082 struct m68k_incant
*hack
, *slak
;
4083 const char *retval
= 0; /* Empty string, or error msg text. */
4086 /* Set up hash tables with 68000 instructions.
4087 similar to what the vax assembler does. */
4088 /* RMS claims the thing to do is take the m68k-opcode.h table, and make
4089 a copy of it at runtime, adding in the information we want but isn't
4090 there. I think it'd be better to have an awk script hack the table
4091 at compile time. Or even just xstr the table and use it as-is. But
4092 my lord ghod hath spoken, so we do it this way. Excuse the ugly var
4097 flag_reg_prefix_optional
= 1;
4099 if (! m68k_rel32_from_cmdline
)
4103 /* First sort the opcode table into alphabetical order to seperate
4104 the order that the assembler wants to see the opcodes from the
4105 order that the disassembler wants to see them. */
4106 m68k_sorted_opcodes
= xmalloc (m68k_numopcodes
* sizeof (* m68k_sorted_opcodes
));
4107 if (!m68k_sorted_opcodes
)
4108 as_fatal (_("Internal Error: Can't allocate m68k_sorted_opcodes of size %d"),
4109 m68k_numopcodes
* ((int) sizeof (* m68k_sorted_opcodes
)));
4111 for (i
= m68k_numopcodes
; i
--;)
4112 m68k_sorted_opcodes
[i
] = m68k_opcodes
+ i
;
4114 qsort (m68k_sorted_opcodes
, m68k_numopcodes
,
4115 sizeof (m68k_sorted_opcodes
[0]), m68k_compare_opcode
);
4117 op_hash
= hash_new ();
4119 obstack_begin (&robyn
, 4000);
4120 for (i
= 0; i
< m68k_numopcodes
; i
++)
4122 hack
= slak
= (struct m68k_incant
*) obstack_alloc (&robyn
, sizeof (struct m68k_incant
));
4125 ins
= m68k_sorted_opcodes
[i
];
4127 /* We *could* ignore insns that don't match our
4128 arch here by just leaving them out of the hash. */
4129 slak
->m_operands
= ins
->args
;
4130 slak
->m_opnum
= strlen (slak
->m_operands
) / 2;
4131 slak
->m_arch
= ins
->arch
;
4132 slak
->m_opcode
= ins
->opcode
;
4133 /* This is kludgey. */
4134 slak
->m_codenum
= ((ins
->match
) & 0xffffL
) ? 2 : 1;
4135 if (i
+ 1 != m68k_numopcodes
4136 && !strcmp (ins
->name
, m68k_sorted_opcodes
[i
+ 1]->name
))
4138 slak
->m_next
= obstack_alloc (&robyn
, sizeof (struct m68k_incant
));
4143 slak
= slak
->m_next
;
4147 retval
= hash_insert (op_hash
, ins
->name
, (char *) hack
);
4149 as_fatal (_("Internal Error: Can't hash %s: %s"), ins
->name
, retval
);
4152 for (i
= 0; i
< m68k_numaliases
; i
++)
4154 const char *name
= m68k_opcode_aliases
[i
].primary
;
4155 const char *alias
= m68k_opcode_aliases
[i
].alias
;
4156 PTR val
= hash_find (op_hash
, name
);
4159 as_fatal (_("Internal Error: Can't find %s in hash table"), name
);
4160 retval
= hash_insert (op_hash
, alias
, val
);
4162 as_fatal (_("Internal Error: Can't hash %s: %s"), alias
, retval
);
4165 /* In MRI mode, all unsized branches are variable sized. Normally,
4166 they are word sized. */
4169 static struct m68k_opcode_alias mri_aliases
[] =
4190 i
< (int) (sizeof mri_aliases
/ sizeof mri_aliases
[0]);
4193 const char *name
= mri_aliases
[i
].primary
;
4194 const char *alias
= mri_aliases
[i
].alias
;
4195 PTR val
= hash_find (op_hash
, name
);
4198 as_fatal (_("Internal Error: Can't find %s in hash table"), name
);
4199 retval
= hash_jam (op_hash
, alias
, val
);
4201 as_fatal (_("Internal Error: Can't hash %s: %s"), alias
, retval
);
4205 for (i
= 0; i
< (int) sizeof (notend_table
); i
++)
4207 notend_table
[i
] = 0;
4208 alt_notend_table
[i
] = 0;
4211 notend_table
[','] = 1;
4212 notend_table
['{'] = 1;
4213 notend_table
['}'] = 1;
4214 alt_notend_table
['a'] = 1;
4215 alt_notend_table
['A'] = 1;
4216 alt_notend_table
['d'] = 1;
4217 alt_notend_table
['D'] = 1;
4218 alt_notend_table
['#'] = 1;
4219 alt_notend_table
['&'] = 1;
4220 alt_notend_table
['f'] = 1;
4221 alt_notend_table
['F'] = 1;
4222 #ifdef REGISTER_PREFIX
4223 alt_notend_table
[REGISTER_PREFIX
] = 1;
4226 /* We need to put '(' in alt_notend_table to handle
4227 cas2 %d0:%d2,%d3:%d4,(%a0):(%a1) */
4228 alt_notend_table
['('] = 1;
4230 /* We need to put '@' in alt_notend_table to handle
4231 cas2 %d0:%d2,%d3:%d4,@(%d0):@(%d1) */
4232 alt_notend_table
['@'] = 1;
4234 /* We need to put digits in alt_notend_table to handle
4235 bfextu %d0{24:1},%d0 */
4236 alt_notend_table
['0'] = 1;
4237 alt_notend_table
['1'] = 1;
4238 alt_notend_table
['2'] = 1;
4239 alt_notend_table
['3'] = 1;
4240 alt_notend_table
['4'] = 1;
4241 alt_notend_table
['5'] = 1;
4242 alt_notend_table
['6'] = 1;
4243 alt_notend_table
['7'] = 1;
4244 alt_notend_table
['8'] = 1;
4245 alt_notend_table
['9'] = 1;
4247 #ifndef MIT_SYNTAX_ONLY
4248 /* Insert pseudo ops, these have to go into the opcode table since
4249 gas expects pseudo ops to start with a dot. */
4253 while (mote_pseudo_table
[n
].poc_name
)
4255 hack
= obstack_alloc (&robyn
, sizeof (struct m68k_incant
));
4256 hash_insert (op_hash
,
4257 mote_pseudo_table
[n
].poc_name
, (char *) hack
);
4258 hack
->m_operands
= 0;
4268 record_alignment (text_section
, 2);
4269 record_alignment (data_section
, 2);
4270 record_alignment (bss_section
, 2);
4275 select_control_regs (void)
4277 /* Note which set of "movec" control registers is available. */
4278 switch (current_chip
)
4282 as_warn (_("architecture not yet selected: defaulting to 68020"));
4283 control_regs
= m68020_control_regs
;
4287 control_regs
= m68000_control_regs
;
4290 control_regs
= m68010_control_regs
;
4294 control_regs
= m68020_control_regs
;
4297 control_regs
= m68040_control_regs
;
4300 control_regs
= m68060_control_regs
;
4303 control_regs
= cpu32_control_regs
;
4309 control_regs
= mcf_control_regs
;
4312 control_regs
= mcf5249_control_regs
;
4316 control_regs
= mcf528x_control_regs
;
4320 control_regs
= mcfv4e_control_regs
;
4328 m68k_init_after_args (void)
4330 if (cpu_of_arch (current_architecture
) == 0)
4333 const char *default_cpu
= TARGET_CPU
;
4335 if (*default_cpu
== 'm')
4337 for (i
= 0; i
< n_archs
; i
++)
4338 if (strcasecmp (default_cpu
, archs
[i
].name
) == 0)
4342 as_bad (_("unrecognized default cpu `%s' ???"), TARGET_CPU
);
4343 current_architecture
|= m68020
;
4346 current_architecture
|= archs
[i
].arch
;
4348 /* Permit m68881 specification with all cpus; those that can't work
4349 with a coprocessor could be doing emulation. */
4350 if (current_architecture
& m68851
)
4352 if (current_architecture
& m68040
)
4353 as_warn (_("68040 and 68851 specified; mmu instructions may assemble incorrectly"));
4355 /* What other incompatibilities could we check for? */
4357 /* Toss in some default assumptions about coprocessors. */
4359 && (cpu_of_arch (current_architecture
)
4360 /* Can CPU32 have a 68881 coprocessor?? */
4361 & (m68020
| m68030
| cpu32
)))
4362 current_architecture
|= m68881
;
4365 && (cpu_of_arch (current_architecture
) & m68020up
) != 0
4366 && (cpu_of_arch (current_architecture
) & m68040up
) == 0)
4367 current_architecture
|= m68851
;
4369 if (no_68881
&& (current_architecture
& m68881
))
4370 as_bad (_("options for 68881 and no-68881 both given"));
4372 if (no_68851
&& (current_architecture
& m68851
))
4373 as_bad (_("options for 68851 and no-68851 both given"));
4375 /* Note which set of "movec" control registers is available. */
4376 select_control_regs ();
4378 if (cpu_of_arch (current_architecture
) < m68020
4379 || arch_coldfire_p (current_architecture
))
4380 md_relax_table
[TAB (PCINDEX
, BYTE
)].rlx_more
= 0;
4383 /* This is called when a label is defined. */
4386 m68k_frob_label (symbolS
*sym
)
4388 struct label_line
*n
;
4390 n
= (struct label_line
*) xmalloc (sizeof *n
);
4393 as_where (&n
->file
, &n
->line
);
4399 /* This is called when a value that is not an instruction is emitted. */
4402 m68k_flush_pending_output (void)
4404 current_label
= NULL
;
4407 /* This is called at the end of the assembly, when the final value of
4408 the label is known. We warn if this is a text symbol aligned at an
4412 m68k_frob_symbol (symbolS
*sym
)
4414 if (S_GET_SEGMENT (sym
) == reg_section
4415 && (int) S_GET_VALUE (sym
) < 0)
4417 S_SET_SEGMENT (sym
, absolute_section
);
4418 S_SET_VALUE (sym
, ~(int)S_GET_VALUE (sym
));
4420 else if ((S_GET_VALUE (sym
) & 1) != 0)
4422 struct label_line
*l
;
4424 for (l
= labels
; l
!= NULL
; l
= l
->next
)
4426 if (l
->label
== sym
)
4429 as_warn_where (l
->file
, l
->line
,
4430 _("text label `%s' aligned to odd boundary"),
4438 /* This is called if we go in or out of MRI mode because of the .mri
4442 m68k_mri_mode_change (int on
)
4446 if (! flag_reg_prefix_optional
)
4448 flag_reg_prefix_optional
= 1;
4449 #ifdef REGISTER_PREFIX
4454 if (! m68k_rel32_from_cmdline
)
4459 if (! reg_prefix_optional_seen
)
4461 #ifdef REGISTER_PREFIX_OPTIONAL
4462 flag_reg_prefix_optional
= REGISTER_PREFIX_OPTIONAL
;
4464 flag_reg_prefix_optional
= 0;
4466 #ifdef REGISTER_PREFIX
4471 if (! m68k_rel32_from_cmdline
)
4476 /* Equal to MAX_PRECISION in atof-ieee.c. */
4477 #define MAX_LITTLENUMS 6
4479 /* Turn a string in input_line_pointer into a floating point constant
4480 of type TYPE, and store the appropriate bytes in *LITP. The number
4481 of LITTLENUMS emitted is stored in *SIZEP. An error message is
4482 returned, or NULL on OK. */
4485 md_atof (int type
, char *litP
, int *sizeP
)
4488 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
4489 LITTLENUM_TYPE
*wordP
;
4520 return _("Bad call to MD_ATOF()");
4522 t
= atof_ieee (input_line_pointer
, type
, words
);
4524 input_line_pointer
= t
;
4526 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
4527 for (wordP
= words
; prec
--;)
4529 md_number_to_chars (litP
, (long) (*wordP
++), sizeof (LITTLENUM_TYPE
));
4530 litP
+= sizeof (LITTLENUM_TYPE
);
4536 md_number_to_chars (char *buf
, valueT val
, int n
)
4538 number_to_chars_bigendian (buf
, val
, n
);
4542 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
4544 offsetT val
= *valP
;
4545 addressT upper_limit
;
4546 offsetT lower_limit
;
4548 /* This is unnecessary but it convinces the native rs6000 compiler
4549 to generate the code we want. */
4550 char *buf
= fixP
->fx_frag
->fr_literal
;
4551 buf
+= fixP
->fx_where
;
4552 /* End ibm compiler workaround. */
4556 if (fixP
->fx_addsy
== NULL
&& fixP
->fx_pcrel
== 0)
4562 memset (buf
, 0, fixP
->fx_size
);
4563 fixP
->fx_addnumber
= val
; /* Remember value for emit_reloc. */
4565 if (fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
4566 && !S_IS_DEFINED (fixP
->fx_addsy
)
4567 && !S_IS_WEAK (fixP
->fx_addsy
))
4568 S_SET_WEAK (fixP
->fx_addsy
);
4573 if (fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
4574 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
4577 switch (fixP
->fx_size
)
4579 /* The cast to offsetT below are necessary to make code
4580 correct for machines where ints are smaller than offsetT. */
4584 lower_limit
= - (offsetT
) 0x80;
4587 *buf
++ = (val
>> 8);
4589 upper_limit
= 0x7fff;
4590 lower_limit
= - (offsetT
) 0x8000;
4593 *buf
++ = (val
>> 24);
4594 *buf
++ = (val
>> 16);
4595 *buf
++ = (val
>> 8);
4597 upper_limit
= 0x7fffffff;
4598 lower_limit
= - (offsetT
) 0x7fffffff - 1; /* Avoid constant overflow. */
4601 BAD_CASE (fixP
->fx_size
);
4604 /* Fix up a negative reloc. */
4605 if (fixP
->fx_addsy
== NULL
&& fixP
->fx_subsy
!= NULL
)
4607 fixP
->fx_addsy
= fixP
->fx_subsy
;
4608 fixP
->fx_subsy
= NULL
;
4612 /* For non-pc-relative values, it's conceivable we might get something
4613 like "0xff" for a byte field. So extend the upper part of the range
4614 to accept such numbers. We arbitrarily disallow "-0xff" or "0xff+0xff",
4615 so that we can do any range checking at all. */
4616 if (! fixP
->fx_pcrel
&& ! fixP
->fx_signed
)
4617 upper_limit
= upper_limit
* 2 + 1;
4619 if ((addressT
) val
> upper_limit
4620 && (val
> 0 || val
< lower_limit
))
4621 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, _("value out of range"));
4623 /* A one byte PC-relative reloc means a short branch. We can't use
4624 a short branch with a value of 0 or -1, because those indicate
4625 different opcodes (branches with longer offsets). fixup_segment
4626 in write.c may have clobbered fx_pcrel, so we need to examine the
4629 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
4630 && fixP
->fx_size
== 1
4631 && (fixP
->fx_addsy
== NULL
4632 || S_IS_DEFINED (fixP
->fx_addsy
))
4633 && (val
== 0 || val
== -1))
4634 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, _("invalid byte branch offset"));
4637 /* *fragP has been relaxed to its final size, and now needs to have
4638 the bytes inside it modified to conform to the new size There is UGLY
4642 md_convert_frag_1 (fragS
*fragP
)
4647 /* Address in object code of the displacement. */
4648 register int object_address
= fragP
->fr_fix
+ fragP
->fr_address
;
4650 /* Address in gas core of the place to store the displacement. */
4651 /* This convinces the native rs6000 compiler to generate the code we
4653 register char *buffer_address
= fragP
->fr_literal
;
4654 buffer_address
+= fragP
->fr_fix
;
4655 /* End ibm compiler workaround. */
4657 /* The displacement of the address, from current location. */
4658 disp
= fragP
->fr_symbol
? S_GET_VALUE (fragP
->fr_symbol
) : 0;
4659 disp
= (disp
+ fragP
->fr_offset
) - object_address
;
4661 switch (fragP
->fr_subtype
)
4663 case TAB (BRANCHBWL
, BYTE
):
4664 case TAB (BRABSJUNC
, BYTE
):
4665 case TAB (BRABSJCOND
, BYTE
):
4666 case TAB (BRANCHBW
, BYTE
):
4667 know (issbyte (disp
));
4669 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
4670 _("short branch with zero offset: use :w"));
4671 fixP
= fix_new (fragP
, fragP
->fr_fix
- 1, 1, fragP
->fr_symbol
,
4672 fragP
->fr_offset
, 1, RELAX_RELOC_PC8
);
4673 fixP
->fx_pcrel_adjust
= -1;
4675 case TAB (BRANCHBWL
, SHORT
):
4676 case TAB (BRABSJUNC
, SHORT
):
4677 case TAB (BRABSJCOND
, SHORT
):
4678 case TAB (BRANCHBW
, SHORT
):
4679 fragP
->fr_opcode
[1] = 0x00;
4680 fix_new (fragP
, fragP
->fr_fix
, 2, fragP
->fr_symbol
, fragP
->fr_offset
,
4681 1, RELAX_RELOC_PC16
);
4684 case TAB (BRANCHBWL
, LONG
):
4685 fragP
->fr_opcode
[1] = (char) 0xFF;
4686 fix_new (fragP
, fragP
->fr_fix
, 4, fragP
->fr_symbol
, fragP
->fr_offset
,
4687 1, RELAX_RELOC_PC32
);
4690 case TAB (BRABSJUNC
, LONG
):
4691 if (fragP
->fr_opcode
[0] == 0x61) /* jbsr */
4693 if (flag_keep_pcrel
)
4694 as_fatal (_("Tried to convert PC relative BSR to absolute JSR"));
4695 fragP
->fr_opcode
[0] = 0x4E;
4696 fragP
->fr_opcode
[1] = (char) 0xB9; /* JSR with ABSL LONG operand. */
4697 fix_new (fragP
, fragP
->fr_fix
, 4, fragP
->fr_symbol
, fragP
->fr_offset
,
4698 0, RELAX_RELOC_ABS32
);
4701 else if (fragP
->fr_opcode
[0] == 0x60) /* jbra */
4703 if (flag_keep_pcrel
)
4704 as_fatal (_("Tried to convert PC relative branch to absolute jump"));
4705 fragP
->fr_opcode
[0] = 0x4E;
4706 fragP
->fr_opcode
[1] = (char) 0xF9; /* JMP with ABSL LONG operand. */
4707 fix_new (fragP
, fragP
->fr_fix
, 4, fragP
->fr_symbol
, fragP
->fr_offset
,
4708 0, RELAX_RELOC_ABS32
);
4713 /* This cannot happen, because jbsr and jbra are the only two
4714 unconditional branches. */
4718 case TAB (BRABSJCOND
, LONG
):
4719 if (flag_keep_pcrel
)
4720 as_fatal (_("Tried to convert PC relative conditional branch to absolute jump"));
4722 /* Only Bcc 68000 instructions can come here
4723 Change bcc into b!cc/jmp absl long. */
4724 fragP
->fr_opcode
[0] ^= 0x01; /* Invert bcc. */
4725 fragP
->fr_opcode
[1] = 0x06; /* Branch offset = 6. */
4727 /* JF: these used to be fr_opcode[2,3], but they may be in a
4728 different frag, in which case referring to them is a no-no.
4729 Only fr_opcode[0,1] are guaranteed to work. */
4730 *buffer_address
++ = 0x4e; /* put in jmp long (0x4ef9) */
4731 *buffer_address
++ = (char) 0xf9;
4732 fragP
->fr_fix
+= 2; /* Account for jmp instruction. */
4733 fix_new (fragP
, fragP
->fr_fix
, 4, fragP
->fr_symbol
,
4734 fragP
->fr_offset
, 0, RELAX_RELOC_ABS32
);
4737 case TAB (FBRANCH
, SHORT
):
4738 know ((fragP
->fr_opcode
[1] & 0x40) == 0);
4739 fix_new (fragP
, fragP
->fr_fix
, 2, fragP
->fr_symbol
, fragP
->fr_offset
,
4740 1, RELAX_RELOC_PC16
);
4743 case TAB (FBRANCH
, LONG
):
4744 fragP
->fr_opcode
[1] |= 0x40; /* Turn on LONG bit. */
4745 fix_new (fragP
, fragP
->fr_fix
, 4, fragP
->fr_symbol
, fragP
->fr_offset
,
4746 1, RELAX_RELOC_PC32
);
4749 case TAB (DBCCLBR
, SHORT
):
4750 case TAB (DBCCABSJ
, SHORT
):
4751 fix_new (fragP
, fragP
->fr_fix
, 2, fragP
->fr_symbol
, fragP
->fr_offset
,
4752 1, RELAX_RELOC_PC16
);
4755 case TAB (DBCCLBR
, LONG
):
4756 /* Only DBcc instructions can come here.
4757 Change dbcc into dbcc/bral.
4758 JF: these used to be fr_opcode[2-7], but that's wrong. */
4759 if (flag_keep_pcrel
)
4760 as_fatal (_("Tried to convert DBcc to absolute jump"));
4762 *buffer_address
++ = 0x00; /* Branch offset = 4. */
4763 *buffer_address
++ = 0x04;
4764 *buffer_address
++ = 0x60; /* Put in bra pc+6. */
4765 *buffer_address
++ = 0x06;
4766 *buffer_address
++ = 0x60; /* Put in bral (0x60ff). */
4767 *buffer_address
++ = (char) 0xff;
4769 fragP
->fr_fix
+= 6; /* Account for bra/jmp instructions. */
4770 fix_new (fragP
, fragP
->fr_fix
, 4, fragP
->fr_symbol
, fragP
->fr_offset
, 1,
4774 case TAB (DBCCABSJ
, LONG
):
4775 /* Only DBcc instructions can come here.
4776 Change dbcc into dbcc/jmp.
4777 JF: these used to be fr_opcode[2-7], but that's wrong. */
4778 if (flag_keep_pcrel
)
4779 as_fatal (_("Tried to convert PC relative conditional branch to absolute jump"));
4781 *buffer_address
++ = 0x00; /* Branch offset = 4. */
4782 *buffer_address
++ = 0x04;
4783 *buffer_address
++ = 0x60; /* Put in bra pc + 6. */
4784 *buffer_address
++ = 0x06;
4785 *buffer_address
++ = 0x4e; /* Put in jmp long (0x4ef9). */
4786 *buffer_address
++ = (char) 0xf9;
4788 fragP
->fr_fix
+= 6; /* Account for bra/jmp instructions. */
4789 fix_new (fragP
, fragP
->fr_fix
, 4, fragP
->fr_symbol
, fragP
->fr_offset
, 0,
4793 case TAB (PCREL1632
, SHORT
):
4794 fragP
->fr_opcode
[1] &= ~0x3F;
4795 fragP
->fr_opcode
[1] |= 0x3A; /* 072 - mode 7.2 */
4796 fix_new (fragP
, (int) (fragP
->fr_fix
), 2, fragP
->fr_symbol
,
4797 fragP
->fr_offset
, 1, RELAX_RELOC_PC16
);
4800 case TAB (PCREL1632
, LONG
):
4801 /* Already set to mode 7.3; this indicates: PC indirect with
4802 suppressed index, 32-bit displacement. */
4803 *buffer_address
++ = 0x01;
4804 *buffer_address
++ = 0x70;
4806 fixP
= fix_new (fragP
, (int) (fragP
->fr_fix
), 4, fragP
->fr_symbol
,
4807 fragP
->fr_offset
, 1, RELAX_RELOC_PC32
);
4808 fixP
->fx_pcrel_adjust
= 2;
4811 case TAB (PCINDEX
, BYTE
):
4812 assert (fragP
->fr_fix
>= 2);
4813 buffer_address
[-2] &= ~1;
4814 fixP
= fix_new (fragP
, fragP
->fr_fix
- 1, 1, fragP
->fr_symbol
,
4815 fragP
->fr_offset
, 1, RELAX_RELOC_PC8
);
4816 fixP
->fx_pcrel_adjust
= 1;
4818 case TAB (PCINDEX
, SHORT
):
4819 assert (fragP
->fr_fix
>= 2);
4820 buffer_address
[-2] |= 0x1;
4821 buffer_address
[-1] = 0x20;
4822 fixP
= fix_new (fragP
, (int) (fragP
->fr_fix
), 2, fragP
->fr_symbol
,
4823 fragP
->fr_offset
, 1, RELAX_RELOC_PC16
);
4824 fixP
->fx_pcrel_adjust
= 2;
4827 case TAB (PCINDEX
, LONG
):
4828 assert (fragP
->fr_fix
>= 2);
4829 buffer_address
[-2] |= 0x1;
4830 buffer_address
[-1] = 0x30;
4831 fixP
= fix_new (fragP
, (int) (fragP
->fr_fix
), 4, fragP
->fr_symbol
,
4832 fragP
->fr_offset
, 1, RELAX_RELOC_PC32
);
4833 fixP
->fx_pcrel_adjust
= 2;
4836 case TAB (ABSTOPCREL
, SHORT
):
4837 fix_new (fragP
, fragP
->fr_fix
, 2, fragP
->fr_symbol
, fragP
->fr_offset
,
4838 1, RELAX_RELOC_PC16
);
4841 case TAB (ABSTOPCREL
, LONG
):
4842 if (flag_keep_pcrel
)
4843 as_fatal (_("Tried to convert PC relative conditional branch to absolute jump"));
4844 /* The thing to do here is force it to ABSOLUTE LONG, since
4845 ABSTOPCREL is really trying to shorten an ABSOLUTE address anyway. */
4846 if ((fragP
->fr_opcode
[1] & 0x3F) != 0x3A)
4848 fragP
->fr_opcode
[1] &= ~0x3F;
4849 fragP
->fr_opcode
[1] |= 0x39; /* Mode 7.1 */
4850 fix_new (fragP
, fragP
->fr_fix
, 4, fragP
->fr_symbol
, fragP
->fr_offset
,
4851 0, RELAX_RELOC_ABS32
);
4858 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
,
4859 segT sec ATTRIBUTE_UNUSED
,
4862 md_convert_frag_1 (fragP
);
4865 /* Force truly undefined symbols to their maximum size, and generally set up
4866 the frag list to be relaxed
4869 md_estimate_size_before_relax (fragS
*fragP
, segT segment
)
4871 /* Handle SZ_UNDEF first, it can be changed to BYTE or SHORT. */
4872 switch (fragP
->fr_subtype
)
4874 case TAB (BRANCHBWL
, SZ_UNDEF
):
4875 case TAB (BRABSJUNC
, SZ_UNDEF
):
4876 case TAB (BRABSJCOND
, SZ_UNDEF
):
4878 if (S_GET_SEGMENT (fragP
->fr_symbol
) == segment
4879 && relaxable_symbol (fragP
->fr_symbol
))
4881 fragP
->fr_subtype
= TAB (TABTYPE (fragP
->fr_subtype
), BYTE
);
4883 else if (flag_short_refs
)
4885 /* Symbol is undefined and we want short ref. */
4886 fragP
->fr_subtype
= TAB (TABTYPE (fragP
->fr_subtype
), SHORT
);
4890 /* Symbol is still undefined. Make it LONG. */
4891 fragP
->fr_subtype
= TAB (TABTYPE (fragP
->fr_subtype
), LONG
);
4896 case TAB (BRANCHBW
, SZ_UNDEF
):
4898 if (S_GET_SEGMENT (fragP
->fr_symbol
) == segment
4899 && relaxable_symbol (fragP
->fr_symbol
))
4901 fragP
->fr_subtype
= TAB (TABTYPE (fragP
->fr_subtype
), BYTE
);
4905 /* Symbol is undefined and we don't have long branches. */
4906 fragP
->fr_subtype
= TAB (TABTYPE (fragP
->fr_subtype
), SHORT
);
4911 case TAB (FBRANCH
, SZ_UNDEF
):
4912 case TAB (DBCCLBR
, SZ_UNDEF
):
4913 case TAB (DBCCABSJ
, SZ_UNDEF
):
4914 case TAB (PCREL1632
, SZ_UNDEF
):
4916 if ((S_GET_SEGMENT (fragP
->fr_symbol
) == segment
4917 && relaxable_symbol (fragP
->fr_symbol
))
4920 fragP
->fr_subtype
= TAB (TABTYPE (fragP
->fr_subtype
), SHORT
);
4924 fragP
->fr_subtype
= TAB (TABTYPE (fragP
->fr_subtype
), LONG
);
4929 case TAB (PCINDEX
, SZ_UNDEF
):
4930 if ((S_GET_SEGMENT (fragP
->fr_symbol
) == segment
4931 && relaxable_symbol (fragP
->fr_symbol
)))
4933 fragP
->fr_subtype
= TAB (PCINDEX
, BYTE
);
4937 fragP
->fr_subtype
= TAB (PCINDEX
, LONG
);
4941 case TAB (ABSTOPCREL
, SZ_UNDEF
):
4943 if ((S_GET_SEGMENT (fragP
->fr_symbol
) == segment
4944 && relaxable_symbol (fragP
->fr_symbol
)))
4946 fragP
->fr_subtype
= TAB (ABSTOPCREL
, SHORT
);
4950 fragP
->fr_subtype
= TAB (ABSTOPCREL
, LONG
);
4959 /* Now that SZ_UNDEF are taken care of, check others. */
4960 switch (fragP
->fr_subtype
)
4962 case TAB (BRANCHBWL
, BYTE
):
4963 case TAB (BRABSJUNC
, BYTE
):
4964 case TAB (BRABSJCOND
, BYTE
):
4965 case TAB (BRANCHBW
, BYTE
):
4966 /* We can't do a short jump to the next instruction, so in that
4967 case we force word mode. If the symbol is at the start of a
4968 frag, and it is the next frag with any data in it (usually
4969 this is just the next frag, but assembler listings may
4970 introduce empty frags), we must use word mode. */
4971 if (fragP
->fr_symbol
)
4975 sym_frag
= symbol_get_frag (fragP
->fr_symbol
);
4976 if (S_GET_VALUE (fragP
->fr_symbol
) == sym_frag
->fr_address
)
4980 for (l
= fragP
->fr_next
; l
&& l
!= sym_frag
; l
= l
->fr_next
)
4984 fragP
->fr_subtype
= TAB (TABTYPE (fragP
->fr_subtype
), SHORT
);
4991 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
4994 #if defined(OBJ_AOUT) | defined(OBJ_BOUT)
4995 /* the bit-field entries in the relocation_info struct plays hell
4996 with the byte-order problems of cross-assembly. So as a hack,
4997 I added this mach. dependent ri twiddler. Ugly, but it gets
4999 /* on m68k: first 4 bytes are normal unsigned long, next three bytes
5000 are symbolnum, most sig. byte first. Last byte is broken up with
5001 bit 7 as pcrel, bits 6 & 5 as length, bit 4 as pcrel, and the lower
5002 nibble as nuthin. (on Sun 3 at least) */
5003 /* Translate the internal relocation information into target-specific
5007 md_ri_to_chars (char *the_bytes
, struct reloc_info_generic
*ri
)
5010 md_number_to_chars (the_bytes
, ri
->r_address
, 4);
5011 /* Now the fun stuff. */
5012 the_bytes
[4] = (ri
->r_symbolnum
>> 16) & 0x0ff;
5013 the_bytes
[5] = (ri
->r_symbolnum
>> 8) & 0x0ff;
5014 the_bytes
[6] = ri
->r_symbolnum
& 0x0ff;
5015 the_bytes
[7] = (((ri
->r_pcrel
<< 7) & 0x80)
5016 | ((ri
->r_length
<< 5) & 0x60)
5017 | ((ri
->r_extern
<< 4) & 0x10));
5022 #endif /* OBJ_AOUT or OBJ_BOUT */
5024 #ifndef WORKING_DOT_WORD
5025 int md_short_jump_size
= 4;
5026 int md_long_jump_size
= 6;
5029 md_create_short_jump (char *ptr
, addressT from_addr
, addressT to_addr
,
5030 fragS
*frag ATTRIBUTE_UNUSED
,
5031 symbolS
*to_symbol ATTRIBUTE_UNUSED
)
5035 offset
= to_addr
- (from_addr
+ 2);
5037 md_number_to_chars (ptr
, (valueT
) 0x6000, 2);
5038 md_number_to_chars (ptr
+ 2, (valueT
) offset
, 2);
5042 md_create_long_jump (char *ptr
, addressT from_addr
, addressT to_addr
,
5043 fragS
*frag
, symbolS
*to_symbol
)
5047 if (!HAVE_LONG_BRANCH (current_architecture
))
5049 if (flag_keep_pcrel
)
5050 as_fatal (_("Tried to convert PC relative branch to absolute jump"));
5051 offset
= to_addr
- S_GET_VALUE (to_symbol
);
5052 md_number_to_chars (ptr
, (valueT
) 0x4EF9, 2);
5053 md_number_to_chars (ptr
+ 2, (valueT
) offset
, 4);
5054 fix_new (frag
, (ptr
+ 2) - frag
->fr_literal
, 4, to_symbol
, (offsetT
) 0,
5059 offset
= to_addr
- (from_addr
+ 2);
5060 md_number_to_chars (ptr
, (valueT
) 0x60ff, 2);
5061 md_number_to_chars (ptr
+ 2, (valueT
) offset
, 4);
5067 /* Different values of OK tell what its OK to return. Things that
5068 aren't OK are an error (what a shock, no?)
5071 10: Absolute 1:8 only
5072 20: Absolute 0:7 only
5073 30: absolute 0:15 only
5074 40: Absolute 0:31 only
5075 50: absolute 0:127 only
5076 55: absolute -64:63 only
5077 60: absolute -128:127 only
5078 70: absolute 0:4095 only
5079 80: absolute -1, 1:7 only
5083 get_num (struct m68k_exp
*exp
, int ok
)
5085 if (exp
->exp
.X_op
== O_absent
)
5087 /* Do the same thing the VAX asm does. */
5088 op (exp
) = O_constant
;
5094 as_warn (_("expression out of range: defaulting to 1"));
5098 else if (exp
->exp
.X_op
== O_constant
)
5103 if ((valueT
) TRUNC (offs (exp
)) - 1 > 7)
5105 as_warn (_("expression out of range: defaulting to 1"));
5110 if ((valueT
) TRUNC (offs (exp
)) > 7)
5114 if ((valueT
) TRUNC (offs (exp
)) > 15)
5118 if ((valueT
) TRUNC (offs (exp
)) > 32)
5122 if ((valueT
) TRUNC (offs (exp
)) > 127)
5126 if ((valueT
) SEXT (offs (exp
)) + 64 > 127)
5130 if ((valueT
) SEXT (offs (exp
)) + 128 > 255)
5134 if ((valueT
) TRUNC (offs (exp
)) > 4095)
5137 as_warn (_("expression out of range: defaulting to 0"));
5142 if ((valueT
) TRUNC (offs (exp
)) != 0xffffffff
5143 && (valueT
) TRUNC (offs (exp
)) - 1 > 6)
5145 as_warn (_("expression out of range: defaulting to 1"));
5153 else if (exp
->exp
.X_op
== O_big
)
5155 if (offs (exp
) <= 0 /* flonum. */
5156 && (ok
== 90 /* no bignums */
5157 || (ok
> 10 /* Small-int ranges including 0 ok. */
5158 /* If we have a flonum zero, a zero integer should
5159 do as well (e.g., in moveq). */
5160 && generic_floating_point_number
.exponent
== 0
5161 && generic_floating_point_number
.low
[0] == 0)))
5163 /* HACK! Turn it into a long. */
5164 LITTLENUM_TYPE words
[6];
5166 gen_to_words (words
, 2, 8L); /* These numbers are magic! */
5167 op (exp
) = O_constant
;
5170 offs (exp
) = words
[1] | (words
[0] << 16);
5174 op (exp
) = O_constant
;
5177 offs (exp
) = (ok
== 10) ? 1 : 0;
5178 as_warn (_("Can't deal with expression; defaulting to %ld"),
5184 if (ok
>= 10 && ok
<= 80)
5186 op (exp
) = O_constant
;
5189 offs (exp
) = (ok
== 10) ? 1 : 0;
5190 as_warn (_("Can't deal with expression; defaulting to %ld"),
5195 if (exp
->size
!= SIZE_UNSPEC
)
5203 if (!isbyte (offs (exp
)))
5204 as_warn (_("expression doesn't fit in BYTE"));
5207 if (!isword (offs (exp
)))
5208 as_warn (_("expression doesn't fit in WORD"));
5216 /* These are the back-ends for the various machine dependent pseudo-ops. */
5219 s_data1 (int ignore ATTRIBUTE_UNUSED
)
5221 subseg_set (data_section
, 1);
5222 demand_empty_rest_of_line ();
5226 s_data2 (int ignore ATTRIBUTE_UNUSED
)
5228 subseg_set (data_section
, 2);
5229 demand_empty_rest_of_line ();
5233 s_bss (int ignore ATTRIBUTE_UNUSED
)
5235 /* We don't support putting frags in the BSS segment, we fake it
5236 by marking in_bss, then looking at s_skip for clues. */
5238 subseg_set (bss_section
, 0);
5239 demand_empty_rest_of_line ();
5243 s_even (int ignore ATTRIBUTE_UNUSED
)
5246 register long temp_fill
;
5248 temp
= 1; /* JF should be 2? */
5249 temp_fill
= get_absolute_expression ();
5250 if (!need_pass_2
) /* Never make frag if expect extra pass. */
5251 frag_align (temp
, (int) temp_fill
, 0);
5252 demand_empty_rest_of_line ();
5253 record_alignment (now_seg
, temp
);
5257 s_proc (int ignore ATTRIBUTE_UNUSED
)
5259 demand_empty_rest_of_line ();
5262 /* Pseudo-ops handled for MRI compatibility. */
5264 /* This function returns non-zero if the argument is a conditional
5265 pseudo-op. This is called when checking whether a pending
5266 alignment is needed. */
5269 m68k_conditional_pseudoop (pseudo_typeS
*pop
)
5271 return (pop
->poc_handler
== s_mri_if
5272 || pop
->poc_handler
== s_mri_else
);
5275 /* Handle an MRI style chip specification. */
5284 s
= input_line_pointer
;
5285 /* We can't use get_symbol_end since the processor names are not proper
5287 while (is_part_of_name (c
= *input_line_pointer
++))
5289 *--input_line_pointer
= 0;
5290 for (i
= 0; i
< n_archs
; i
++)
5291 if (strcasecmp (s
, archs
[i
].name
) == 0)
5295 as_bad (_("%s: unrecognized processor name"), s
);
5296 *input_line_pointer
= c
;
5297 ignore_rest_of_line ();
5300 *input_line_pointer
= c
;
5302 if (*input_line_pointer
== '/')
5303 current_architecture
= 0;
5305 current_architecture
&= m68881
| m68851
;
5306 current_architecture
|= archs
[i
].arch
;
5307 current_chip
= archs
[i
].chip
;
5309 while (*input_line_pointer
== '/')
5311 ++input_line_pointer
;
5312 s
= input_line_pointer
;
5313 /* We can't use get_symbol_end since the processor names are not
5315 while (is_part_of_name (c
= *input_line_pointer
++))
5317 *--input_line_pointer
= 0;
5318 if (strcmp (s
, "68881") == 0)
5319 current_architecture
|= m68881
;
5320 else if (strcmp (s
, "68851") == 0)
5321 current_architecture
|= m68851
;
5322 *input_line_pointer
= c
;
5325 /* Update info about available control registers. */
5326 select_control_regs ();
5329 /* The MRI CHIP pseudo-op. */
5332 s_chip (int ignore ATTRIBUTE_UNUSED
)
5338 stop
= mri_comment_field (&stopc
);
5341 mri_comment_end (stop
, stopc
);
5342 demand_empty_rest_of_line ();
5345 /* The MRI FOPT pseudo-op. */
5348 s_fopt (int ignore ATTRIBUTE_UNUSED
)
5352 if (strncasecmp (input_line_pointer
, "ID=", 3) == 0)
5356 input_line_pointer
+= 3;
5357 temp
= get_absolute_expression ();
5358 if (temp
< 0 || temp
> 7)
5359 as_bad (_("bad coprocessor id"));
5361 m68k_float_copnum
= COP0
+ temp
;
5365 as_bad (_("unrecognized fopt option"));
5366 ignore_rest_of_line ();
5370 demand_empty_rest_of_line ();
5373 /* The structure used to handle the MRI OPT pseudo-op. */
5377 /* The name of the option. */
5380 /* If this is not NULL, just call this function. The first argument
5381 is the ARG field of this structure, the second argument is
5382 whether the option was negated. */
5383 void (*pfn
) (int arg
, int on
);
5385 /* If this is not NULL, and the PFN field is NULL, set the variable
5386 this points to. Set it to the ARG field if the option was not
5387 negated, and the NOTARG field otherwise. */
5390 /* The value to pass to PFN or to assign to *PVAR. */
5393 /* The value to assign to *PVAR if the option is negated. If PFN is
5394 NULL, and PVAR is not NULL, and ARG and NOTARG are the same, then
5395 the option may not be negated. */
5399 /* The table used to handle the MRI OPT pseudo-op. */
5401 static void skip_to_comma (int, int);
5402 static void opt_nest (int, int);
5403 static void opt_chip (int, int);
5404 static void opt_list (int, int);
5405 static void opt_list_symbols (int, int);
5407 static const struct opt_action opt_table
[] =
5409 { "abspcadd", 0, &m68k_abspcadd
, 1, 0 },
5411 /* We do relaxing, so there is little use for these options. */
5412 { "b", 0, 0, 0, 0 },
5413 { "brs", 0, 0, 0, 0 },
5414 { "brb", 0, 0, 0, 0 },
5415 { "brl", 0, 0, 0, 0 },
5416 { "brw", 0, 0, 0, 0 },
5418 { "c", 0, 0, 0, 0 },
5419 { "cex", 0, 0, 0, 0 },
5420 { "case", 0, &symbols_case_sensitive
, 1, 0 },
5421 { "cl", 0, 0, 0, 0 },
5422 { "cre", 0, 0, 0, 0 },
5423 { "d", 0, &flag_keep_locals
, 1, 0 },
5424 { "e", 0, 0, 0, 0 },
5425 { "f", 0, &flag_short_refs
, 1, 0 },
5426 { "frs", 0, &flag_short_refs
, 1, 0 },
5427 { "frl", 0, &flag_short_refs
, 0, 1 },
5428 { "g", 0, 0, 0, 0 },
5429 { "i", 0, 0, 0, 0 },
5430 { "m", 0, 0, 0, 0 },
5431 { "mex", 0, 0, 0, 0 },
5432 { "mc", 0, 0, 0, 0 },
5433 { "md", 0, 0, 0, 0 },
5434 { "nest", opt_nest
, 0, 0, 0 },
5435 { "next", skip_to_comma
, 0, 0, 0 },
5436 { "o", 0, 0, 0, 0 },
5437 { "old", 0, 0, 0, 0 },
5438 { "op", skip_to_comma
, 0, 0, 0 },
5439 { "pco", 0, 0, 0, 0 },
5440 { "p", opt_chip
, 0, 0, 0 },
5441 { "pcr", 0, 0, 0, 0 },
5442 { "pcs", 0, 0, 0, 0 },
5443 { "r", 0, 0, 0, 0 },
5444 { "quick", 0, &m68k_quick
, 1, 0 },
5445 { "rel32", 0, &m68k_rel32
, 1, 0 },
5446 { "s", opt_list
, 0, 0, 0 },
5447 { "t", opt_list_symbols
, 0, 0, 0 },
5448 { "w", 0, &flag_no_warnings
, 0, 1 },
5452 #define OPTCOUNT ((int) (sizeof opt_table / sizeof opt_table[0]))
5454 /* The MRI OPT pseudo-op. */
5457 s_opt (int ignore ATTRIBUTE_UNUSED
)
5465 const struct opt_action
*o
;
5470 if (*input_line_pointer
== '-')
5472 ++input_line_pointer
;
5475 else if (strncasecmp (input_line_pointer
, "NO", 2) == 0)
5477 input_line_pointer
+= 2;
5481 s
= input_line_pointer
;
5482 c
= get_symbol_end ();
5484 for (i
= 0, o
= opt_table
; i
< OPTCOUNT
; i
++, o
++)
5486 if (strcasecmp (s
, o
->name
) == 0)
5490 /* Restore input_line_pointer now in case the option
5492 *input_line_pointer
= c
;
5493 (*o
->pfn
) (o
->arg
, t
);
5495 else if (o
->pvar
!= NULL
)
5497 if (! t
&& o
->arg
== o
->notarg
)
5498 as_bad (_("option `%s' may not be negated"), s
);
5499 *input_line_pointer
= c
;
5500 *o
->pvar
= t
? o
->arg
: o
->notarg
;
5503 *input_line_pointer
= c
;
5509 as_bad (_("option `%s' not recognized"), s
);
5510 *input_line_pointer
= c
;
5513 while (*input_line_pointer
++ == ',');
5515 /* Move back to terminating character. */
5516 --input_line_pointer
;
5517 demand_empty_rest_of_line ();
5520 /* Skip ahead to a comma. This is used for OPT options which we do
5521 not support and which take arguments. */
5524 skip_to_comma (int arg ATTRIBUTE_UNUSED
, int on ATTRIBUTE_UNUSED
)
5526 while (*input_line_pointer
!= ','
5527 && ! is_end_of_line
[(unsigned char) *input_line_pointer
])
5528 ++input_line_pointer
;
5531 /* Handle the OPT NEST=depth option. */
5534 opt_nest (int arg ATTRIBUTE_UNUSED
, int on ATTRIBUTE_UNUSED
)
5536 if (*input_line_pointer
!= '=')
5538 as_bad (_("bad format of OPT NEST=depth"));
5542 ++input_line_pointer
;
5543 max_macro_nest
= get_absolute_expression ();
5546 /* Handle the OPT P=chip option. */
5549 opt_chip (int arg ATTRIBUTE_UNUSED
, int on ATTRIBUTE_UNUSED
)
5551 if (*input_line_pointer
!= '=')
5553 /* This is just OPT P, which we do not support. */
5557 ++input_line_pointer
;
5561 /* Handle the OPT S option. */
5564 opt_list (int arg ATTRIBUTE_UNUSED
, int on
)
5569 /* Handle the OPT T option. */
5572 opt_list_symbols (int arg ATTRIBUTE_UNUSED
, int on
)
5575 listing
|= LISTING_SYMBOLS
;
5577 listing
&= ~LISTING_SYMBOLS
;
5580 /* Handle the MRI REG pseudo-op. */
5583 s_reg (int ignore ATTRIBUTE_UNUSED
)
5592 if (line_label
== NULL
)
5594 as_bad (_("missing label"));
5595 ignore_rest_of_line ();
5600 stop
= mri_comment_field (&stopc
);
5604 s
= input_line_pointer
;
5605 while (ISALNUM (*input_line_pointer
)
5606 #ifdef REGISTER_PREFIX
5607 || *input_line_pointer
== REGISTER_PREFIX
5609 || *input_line_pointer
== '/'
5610 || *input_line_pointer
== '-')
5611 ++input_line_pointer
;
5612 c
= *input_line_pointer
;
5613 *input_line_pointer
= '\0';
5615 if (m68k_ip_op (s
, &rop
) != 0)
5617 if (rop
.error
== NULL
)
5618 as_bad (_("bad register list"));
5620 as_bad (_("bad register list: %s"), rop
.error
);
5621 *input_line_pointer
= c
;
5622 ignore_rest_of_line ();
5626 *input_line_pointer
= c
;
5628 if (rop
.mode
== REGLST
)
5630 else if (rop
.mode
== DREG
)
5631 mask
= 1 << (rop
.reg
- DATA0
);
5632 else if (rop
.mode
== AREG
)
5633 mask
= 1 << (rop
.reg
- ADDR0
+ 8);
5634 else if (rop
.mode
== FPREG
)
5635 mask
= 1 << (rop
.reg
- FP0
+ 16);
5636 else if (rop
.mode
== CONTROL
5639 else if (rop
.mode
== CONTROL
5642 else if (rop
.mode
== CONTROL
5647 as_bad (_("bad register list"));
5648 ignore_rest_of_line ();
5652 S_SET_SEGMENT (line_label
, reg_section
);
5653 S_SET_VALUE (line_label
, ~mask
);
5654 symbol_set_frag (line_label
, &zero_address_frag
);
5657 mri_comment_end (stop
, stopc
);
5659 demand_empty_rest_of_line ();
5662 /* This structure is used for the MRI SAVE and RESTORE pseudo-ops. */
5666 struct save_opts
*next
;
5668 int symbols_case_sensitive
;
5677 /* FIXME: We don't save OPT S. */
5680 /* This variable holds the stack of saved options. */
5682 static struct save_opts
*save_stack
;
5684 /* The MRI SAVE pseudo-op. */
5687 s_save (int ignore ATTRIBUTE_UNUSED
)
5689 struct save_opts
*s
;
5691 s
= (struct save_opts
*) xmalloc (sizeof (struct save_opts
));
5692 s
->abspcadd
= m68k_abspcadd
;
5693 s
->symbols_case_sensitive
= symbols_case_sensitive
;
5694 s
->keep_locals
= flag_keep_locals
;
5695 s
->short_refs
= flag_short_refs
;
5696 s
->architecture
= current_architecture
;
5697 s
->chip
= current_chip
;
5698 s
->quick
= m68k_quick
;
5699 s
->rel32
= m68k_rel32
;
5700 s
->listing
= listing
;
5701 s
->no_warnings
= flag_no_warnings
;
5703 s
->next
= save_stack
;
5706 demand_empty_rest_of_line ();
5709 /* The MRI RESTORE pseudo-op. */
5712 s_restore (int ignore ATTRIBUTE_UNUSED
)
5714 struct save_opts
*s
;
5716 if (save_stack
== NULL
)
5718 as_bad (_("restore without save"));
5719 ignore_rest_of_line ();
5724 save_stack
= s
->next
;
5726 m68k_abspcadd
= s
->abspcadd
;
5727 symbols_case_sensitive
= s
->symbols_case_sensitive
;
5728 flag_keep_locals
= s
->keep_locals
;
5729 flag_short_refs
= s
->short_refs
;
5730 current_architecture
= s
->architecture
;
5731 current_chip
= s
->chip
;
5732 m68k_quick
= s
->quick
;
5733 m68k_rel32
= s
->rel32
;
5734 listing
= s
->listing
;
5735 flag_no_warnings
= s
->no_warnings
;
5739 demand_empty_rest_of_line ();
5742 /* Types of MRI structured control directives. */
5744 enum mri_control_type
5752 /* This structure is used to stack the MRI structured control
5755 struct mri_control_info
5757 /* The directive within which this one is enclosed. */
5758 struct mri_control_info
*outer
;
5760 /* The type of directive. */
5761 enum mri_control_type type
;
5763 /* Whether an ELSE has been in an IF. */
5766 /* The add or sub statement at the end of a FOR. */
5769 /* The label of the top of a FOR or REPEAT loop. */
5772 /* The label to jump to for the next iteration, or the else
5773 expression of a conditional. */
5776 /* The label to jump to to break out of the loop, or the label past
5777 the end of a conditional. */
5781 /* The stack of MRI structured control directives. */
5783 static struct mri_control_info
*mri_control_stack
;
5785 /* The current MRI structured control directive index number, used to
5786 generate label names. */
5788 static int mri_control_index
;
5790 /* Assemble an instruction for an MRI structured control directive. */
5793 mri_assemble (char *str
)
5797 /* md_assemble expects the opcode to be in lower case. */
5798 for (s
= str
; *s
!= ' ' && *s
!= '\0'; s
++)
5804 /* Generate a new MRI label structured control directive label name. */
5807 mri_control_label (void)
5811 n
= (char *) xmalloc (20);
5812 sprintf (n
, "%smc%d", FAKE_LABEL_NAME
, mri_control_index
);
5813 ++mri_control_index
;
5817 /* Create a new MRI structured control directive. */
5819 static struct mri_control_info
*
5820 push_mri_control (enum mri_control_type type
)
5822 struct mri_control_info
*n
;
5824 n
= (struct mri_control_info
*) xmalloc (sizeof (struct mri_control_info
));
5828 if (type
== mri_if
|| type
== mri_while
)
5831 n
->top
= mri_control_label ();
5832 n
->next
= mri_control_label ();
5833 n
->bottom
= mri_control_label ();
5835 n
->outer
= mri_control_stack
;
5836 mri_control_stack
= n
;
5841 /* Pop off the stack of MRI structured control directives. */
5844 pop_mri_control (void)
5846 struct mri_control_info
*n
;
5848 n
= mri_control_stack
;
5849 mri_control_stack
= n
->outer
;
5857 /* Recognize a condition code in an MRI structured control expression. */
5860 parse_mri_condition (int *pcc
)
5864 know (*input_line_pointer
== '<');
5866 ++input_line_pointer
;
5867 c1
= *input_line_pointer
++;
5868 c2
= *input_line_pointer
++;
5870 if (*input_line_pointer
!= '>')
5872 as_bad (_("syntax error in structured control directive"));
5876 ++input_line_pointer
;
5882 *pcc
= (c1
<< 8) | c2
;
5887 /* Parse a single operand in an MRI structured control expression. */
5890 parse_mri_control_operand (int *pcc
, char **leftstart
, char **leftstop
,
5891 char **rightstart
, char **rightstop
)
5903 if (*input_line_pointer
== '<')
5905 /* It's just a condition code. */
5906 return parse_mri_condition (pcc
);
5909 /* Look ahead for the condition code. */
5910 for (s
= input_line_pointer
; *s
!= '\0'; ++s
)
5912 if (*s
== '<' && s
[1] != '\0' && s
[2] != '\0' && s
[3] == '>')
5917 as_bad (_("missing condition code in structured control directive"));
5921 *leftstart
= input_line_pointer
;
5923 if (*leftstop
> *leftstart
5924 && ((*leftstop
)[-1] == ' ' || (*leftstop
)[-1] == '\t'))
5927 input_line_pointer
= s
;
5928 if (! parse_mri_condition (pcc
))
5931 /* Look ahead for AND or OR or end of line. */
5932 for (s
= input_line_pointer
; *s
!= '\0'; ++s
)
5934 /* We must make sure we don't misinterpret AND/OR at the end of labels!
5935 if d0 <eq> #FOOAND and d1 <ne> #BAROR then
5937 if ((s
== input_line_pointer
5940 && ((strncasecmp (s
, "AND", 3) == 0
5941 && (s
[3] == '.' || ! is_part_of_name (s
[3])))
5942 || (strncasecmp (s
, "OR", 2) == 0
5943 && (s
[2] == '.' || ! is_part_of_name (s
[2])))))
5947 *rightstart
= input_line_pointer
;
5949 if (*rightstop
> *rightstart
5950 && ((*rightstop
)[-1] == ' ' || (*rightstop
)[-1] == '\t'))
5953 input_line_pointer
= s
;
5958 #define MCC(b1, b2) (((b1) << 8) | (b2))
5960 /* Swap the sense of a condition. This changes the condition so that
5961 it generates the same result when the operands are swapped. */
5964 swap_mri_condition (int cc
)
5968 case MCC ('h', 'i'): return MCC ('c', 's');
5969 case MCC ('l', 's'): return MCC ('c', 'c');
5970 /* <HS> is an alias for <CC>. */
5971 case MCC ('h', 's'):
5972 case MCC ('c', 'c'): return MCC ('l', 's');
5973 /* <LO> is an alias for <CS>. */
5974 case MCC ('l', 'o'):
5975 case MCC ('c', 's'): return MCC ('h', 'i');
5976 case MCC ('p', 'l'): return MCC ('m', 'i');
5977 case MCC ('m', 'i'): return MCC ('p', 'l');
5978 case MCC ('g', 'e'): return MCC ('l', 'e');
5979 case MCC ('l', 't'): return MCC ('g', 't');
5980 case MCC ('g', 't'): return MCC ('l', 't');
5981 case MCC ('l', 'e'): return MCC ('g', 'e');
5982 /* Issue a warning for conditions we can not swap. */
5983 case MCC ('n', 'e'): return MCC ('n', 'e'); // no problem here
5984 case MCC ('e', 'q'): return MCC ('e', 'q'); // also no problem
5985 case MCC ('v', 'c'):
5986 case MCC ('v', 's'):
5988 as_warn (_("Condition <%c%c> in structured control directive can not be encoded correctly"),
5989 (char) (cc
>> 8), (char) (cc
));
5995 /* Reverse the sense of a condition. */
5998 reverse_mri_condition (int cc
)
6002 case MCC ('h', 'i'): return MCC ('l', 's');
6003 case MCC ('l', 's'): return MCC ('h', 'i');
6004 /* <HS> is an alias for <CC> */
6005 case MCC ('h', 's'): return MCC ('l', 'o');
6006 case MCC ('c', 'c'): return MCC ('c', 's');
6007 /* <LO> is an alias for <CS> */
6008 case MCC ('l', 'o'): return MCC ('h', 's');
6009 case MCC ('c', 's'): return MCC ('c', 'c');
6010 case MCC ('n', 'e'): return MCC ('e', 'q');
6011 case MCC ('e', 'q'): return MCC ('n', 'e');
6012 case MCC ('v', 'c'): return MCC ('v', 's');
6013 case MCC ('v', 's'): return MCC ('v', 'c');
6014 case MCC ('p', 'l'): return MCC ('m', 'i');
6015 case MCC ('m', 'i'): return MCC ('p', 'l');
6016 case MCC ('g', 'e'): return MCC ('l', 't');
6017 case MCC ('l', 't'): return MCC ('g', 'e');
6018 case MCC ('g', 't'): return MCC ('l', 'e');
6019 case MCC ('l', 'e'): return MCC ('g', 't');
6024 /* Build an MRI structured control expression. This generates test
6025 and branch instructions. It goes to TRUELAB if the condition is
6026 true, and to FALSELAB if the condition is false. Exactly one of
6027 TRUELAB and FALSELAB will be NULL, meaning to fall through. QUAL
6028 is the size qualifier for the expression. EXTENT is the size to
6029 use for the branch. */
6032 build_mri_control_operand (int qual
, int cc
, char *leftstart
, char *leftstop
,
6033 char *rightstart
, char *rightstop
,
6034 const char *truelab
, const char *falselab
,
6040 if (leftstart
!= NULL
)
6042 struct m68k_op leftop
, rightop
;
6045 /* Swap the compare operands, if necessary, to produce a legal
6046 m68k compare instruction. Comparing a register operand with
6047 a non-register operand requires the register to be on the
6048 right (cmp, cmpa). Comparing an immediate value with
6049 anything requires the immediate value to be on the left
6054 (void) m68k_ip_op (leftstart
, &leftop
);
6059 (void) m68k_ip_op (rightstart
, &rightop
);
6062 if (rightop
.mode
== IMMED
6063 || ((leftop
.mode
== DREG
|| leftop
.mode
== AREG
)
6064 && (rightop
.mode
!= DREG
&& rightop
.mode
!= AREG
)))
6068 /* Correct conditional handling:
6069 if #1 <lt> d0 then ;means if (1 < d0)
6075 cmp #1,d0 if we do *not* swap the operands
6076 bgt true we need the swapped condition!
6083 leftstart
= rightstart
;
6086 leftstop
= rightstop
;
6091 cc
= swap_mri_condition (cc
);
6095 if (truelab
== NULL
)
6097 cc
= reverse_mri_condition (cc
);
6101 if (leftstart
!= NULL
)
6103 buf
= (char *) xmalloc (20
6104 + (leftstop
- leftstart
)
6105 + (rightstop
- rightstart
));
6111 *s
++ = TOLOWER (qual
);
6113 memcpy (s
, leftstart
, leftstop
- leftstart
);
6114 s
+= leftstop
- leftstart
;
6116 memcpy (s
, rightstart
, rightstop
- rightstart
);
6117 s
+= rightstop
- rightstart
;
6123 buf
= (char *) xmalloc (20 + strlen (truelab
));
6129 *s
++ = TOLOWER (extent
);
6131 strcpy (s
, truelab
);
6136 /* Parse an MRI structured control expression. This generates test
6137 and branch instructions. STOP is where the expression ends. It
6138 goes to TRUELAB if the condition is true, and to FALSELAB if the
6139 condition is false. Exactly one of TRUELAB and FALSELAB will be
6140 NULL, meaning to fall through. QUAL is the size qualifier for the
6141 expression. EXTENT is the size to use for the branch. */
6144 parse_mri_control_expression (char *stop
, int qual
, const char *truelab
,
6145 const char *falselab
, int extent
)
6157 if (! parse_mri_control_operand (&cc
, &leftstart
, &leftstop
,
6158 &rightstart
, &rightstop
))
6164 if (strncasecmp (input_line_pointer
, "AND", 3) == 0)
6168 if (falselab
!= NULL
)
6171 flab
= mri_control_label ();
6173 build_mri_control_operand (qual
, cc
, leftstart
, leftstop
, rightstart
,
6174 rightstop
, (const char *) NULL
, flab
, extent
);
6176 input_line_pointer
+= 3;
6177 if (*input_line_pointer
!= '.'
6178 || input_line_pointer
[1] == '\0')
6182 qual
= input_line_pointer
[1];
6183 input_line_pointer
+= 2;
6186 if (! parse_mri_control_operand (&cc
, &leftstart
, &leftstop
,
6187 &rightstart
, &rightstop
))
6193 build_mri_control_operand (qual
, cc
, leftstart
, leftstop
, rightstart
,
6194 rightstop
, truelab
, falselab
, extent
);
6196 if (falselab
== NULL
)
6199 else if (strncasecmp (input_line_pointer
, "OR", 2) == 0)
6203 if (truelab
!= NULL
)
6206 tlab
= mri_control_label ();
6208 build_mri_control_operand (qual
, cc
, leftstart
, leftstop
, rightstart
,
6209 rightstop
, tlab
, (const char *) NULL
, extent
);
6211 input_line_pointer
+= 2;
6212 if (*input_line_pointer
!= '.'
6213 || input_line_pointer
[1] == '\0')
6217 qual
= input_line_pointer
[1];
6218 input_line_pointer
+= 2;
6221 if (! parse_mri_control_operand (&cc
, &leftstart
, &leftstop
,
6222 &rightstart
, &rightstop
))
6228 build_mri_control_operand (qual
, cc
, leftstart
, leftstop
, rightstart
,
6229 rightstop
, truelab
, falselab
, extent
);
6231 if (truelab
== NULL
)
6236 build_mri_control_operand (qual
, cc
, leftstart
, leftstop
, rightstart
,
6237 rightstop
, truelab
, falselab
, extent
);
6241 if (input_line_pointer
!= stop
)
6242 as_bad (_("syntax error in structured control directive"));
6245 /* Handle the MRI IF pseudo-op. This may be a structured control
6246 directive, or it may be a regular assembler conditional, depending
6254 struct mri_control_info
*n
;
6256 /* A structured control directive must end with THEN with an
6257 optional qualifier. */
6258 s
= input_line_pointer
;
6259 /* We only accept '*' as introduction of comments if preceded by white space
6260 or at first column of a line (I think this can't actually happen here?)
6261 This is important when assembling:
6262 if d0 <ne> 12(a0,d0*2) then
6263 if d0 <ne> #CONST*20 then. */
6264 while (! (is_end_of_line
[(unsigned char) *s
]
6267 && (s
== input_line_pointer
6269 || *(s
-1) == '\t'))))
6272 while (s
> input_line_pointer
&& (*s
== ' ' || *s
== '\t'))
6275 if (s
- input_line_pointer
> 1
6279 if (s
- input_line_pointer
< 3
6280 || strncasecmp (s
- 3, "THEN", 4) != 0)
6284 as_bad (_("missing then"));
6285 ignore_rest_of_line ();
6289 /* It's a conditional. */
6294 /* Since this might be a conditional if, this pseudo-op will be
6295 called even if we are supported to be ignoring input. Double
6296 check now. Clobber *input_line_pointer so that ignore_input
6297 thinks that this is not a special pseudo-op. */
6298 c
= *input_line_pointer
;
6299 *input_line_pointer
= 0;
6300 if (ignore_input ())
6302 *input_line_pointer
= c
;
6303 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
6304 ++input_line_pointer
;
6305 demand_empty_rest_of_line ();
6308 *input_line_pointer
= c
;
6310 n
= push_mri_control (mri_if
);
6312 parse_mri_control_expression (s
- 3, qual
, (const char *) NULL
,
6313 n
->next
, s
[1] == '.' ? s
[2] : '\0');
6316 input_line_pointer
= s
+ 3;
6318 input_line_pointer
= s
+ 1;
6322 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
6323 ++input_line_pointer
;
6326 demand_empty_rest_of_line ();
6329 /* Handle the MRI else pseudo-op. If we are currently doing an MRI
6330 structured IF, associate the ELSE with the IF. Otherwise, assume
6331 it is a conditional else. */
6334 s_mri_else (int qual
)
6341 && (mri_control_stack
== NULL
6342 || mri_control_stack
->type
!= mri_if
6343 || mri_control_stack
->else_seen
))
6349 c
= *input_line_pointer
;
6350 *input_line_pointer
= 0;
6351 if (ignore_input ())
6353 *input_line_pointer
= c
;
6354 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
6355 ++input_line_pointer
;
6356 demand_empty_rest_of_line ();
6359 *input_line_pointer
= c
;
6361 if (mri_control_stack
== NULL
6362 || mri_control_stack
->type
!= mri_if
6363 || mri_control_stack
->else_seen
)
6365 as_bad (_("else without matching if"));
6366 ignore_rest_of_line ();
6370 mri_control_stack
->else_seen
= 1;
6372 buf
= (char *) xmalloc (20 + strlen (mri_control_stack
->bottom
));
6373 q
[0] = TOLOWER (qual
);
6375 sprintf (buf
, "bra%s %s", q
, mri_control_stack
->bottom
);
6379 colon (mri_control_stack
->next
);
6383 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
6384 ++input_line_pointer
;
6387 demand_empty_rest_of_line ();
6390 /* Handle the MRI ENDI pseudo-op. */
6393 s_mri_endi (int ignore ATTRIBUTE_UNUSED
)
6395 if (mri_control_stack
== NULL
6396 || mri_control_stack
->type
!= mri_if
)
6398 as_bad (_("endi without matching if"));
6399 ignore_rest_of_line ();
6403 /* ignore_input will not return true for ENDI, so we don't need to
6404 worry about checking it again here. */
6406 if (! mri_control_stack
->else_seen
)
6407 colon (mri_control_stack
->next
);
6408 colon (mri_control_stack
->bottom
);
6414 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
6415 ++input_line_pointer
;
6418 demand_empty_rest_of_line ();
6421 /* Handle the MRI BREAK pseudo-op. */
6424 s_mri_break (int extent
)
6426 struct mri_control_info
*n
;
6430 n
= mri_control_stack
;
6432 && n
->type
!= mri_for
6433 && n
->type
!= mri_repeat
6434 && n
->type
!= mri_while
)
6438 as_bad (_("break outside of structured loop"));
6439 ignore_rest_of_line ();
6443 buf
= (char *) xmalloc (20 + strlen (n
->bottom
));
6444 ex
[0] = TOLOWER (extent
);
6446 sprintf (buf
, "bra%s %s", ex
, n
->bottom
);
6452 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
6453 ++input_line_pointer
;
6456 demand_empty_rest_of_line ();
6459 /* Handle the MRI NEXT pseudo-op. */
6462 s_mri_next (int extent
)
6464 struct mri_control_info
*n
;
6468 n
= mri_control_stack
;
6470 && n
->type
!= mri_for
6471 && n
->type
!= mri_repeat
6472 && n
->type
!= mri_while
)
6476 as_bad (_("next outside of structured loop"));
6477 ignore_rest_of_line ();
6481 buf
= (char *) xmalloc (20 + strlen (n
->next
));
6482 ex
[0] = TOLOWER (extent
);
6484 sprintf (buf
, "bra%s %s", ex
, n
->next
);
6490 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
6491 ++input_line_pointer
;
6494 demand_empty_rest_of_line ();
6497 /* Handle the MRI FOR pseudo-op. */
6500 s_mri_for (int qual
)
6502 const char *varstart
, *varstop
;
6503 const char *initstart
, *initstop
;
6504 const char *endstart
, *endstop
;
6505 const char *bystart
, *bystop
;
6509 struct mri_control_info
*n
;
6515 FOR.q var = init { TO | DOWNTO } end [ BY by ] DO.e
6519 varstart
= input_line_pointer
;
6521 /* Look for the '='. */
6522 while (! is_end_of_line
[(unsigned char) *input_line_pointer
]
6523 && *input_line_pointer
!= '=')
6524 ++input_line_pointer
;
6525 if (*input_line_pointer
!= '=')
6527 as_bad (_("missing ="));
6528 ignore_rest_of_line ();
6532 varstop
= input_line_pointer
;
6533 if (varstop
> varstart
6534 && (varstop
[-1] == ' ' || varstop
[-1] == '\t'))
6537 ++input_line_pointer
;
6539 initstart
= input_line_pointer
;
6541 /* Look for TO or DOWNTO. */
6544 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
6546 if (strncasecmp (input_line_pointer
, "TO", 2) == 0
6547 && ! is_part_of_name (input_line_pointer
[2]))
6549 initstop
= input_line_pointer
;
6550 input_line_pointer
+= 2;
6553 if (strncasecmp (input_line_pointer
, "DOWNTO", 6) == 0
6554 && ! is_part_of_name (input_line_pointer
[6]))
6556 initstop
= input_line_pointer
;
6558 input_line_pointer
+= 6;
6561 ++input_line_pointer
;
6563 if (initstop
== NULL
)
6565 as_bad (_("missing to or downto"));
6566 ignore_rest_of_line ();
6569 if (initstop
> initstart
6570 && (initstop
[-1] == ' ' || initstop
[-1] == '\t'))
6574 endstart
= input_line_pointer
;
6576 /* Look for BY or DO. */
6579 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
6581 if (strncasecmp (input_line_pointer
, "BY", 2) == 0
6582 && ! is_part_of_name (input_line_pointer
[2]))
6584 endstop
= input_line_pointer
;
6586 input_line_pointer
+= 2;
6589 if (strncasecmp (input_line_pointer
, "DO", 2) == 0
6590 && (input_line_pointer
[2] == '.'
6591 || ! is_part_of_name (input_line_pointer
[2])))
6593 endstop
= input_line_pointer
;
6594 input_line_pointer
+= 2;
6597 ++input_line_pointer
;
6599 if (endstop
== NULL
)
6601 as_bad (_("missing do"));
6602 ignore_rest_of_line ();
6605 if (endstop
> endstart
6606 && (endstop
[-1] == ' ' || endstop
[-1] == '\t'))
6612 bystop
= bystart
+ 2;
6617 bystart
= input_line_pointer
;
6621 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
6623 if (strncasecmp (input_line_pointer
, "DO", 2) == 0
6624 && (input_line_pointer
[2] == '.'
6625 || ! is_part_of_name (input_line_pointer
[2])))
6627 bystop
= input_line_pointer
;
6628 input_line_pointer
+= 2;
6631 ++input_line_pointer
;
6635 as_bad (_("missing do"));
6636 ignore_rest_of_line ();
6639 if (bystop
> bystart
6640 && (bystop
[-1] == ' ' || bystop
[-1] == '\t'))
6644 if (*input_line_pointer
!= '.')
6648 extent
= input_line_pointer
[1];
6649 input_line_pointer
+= 2;
6652 /* We have fully parsed the FOR operands. Now build the loop. */
6653 n
= push_mri_control (mri_for
);
6655 buf
= (char *) xmalloc (50 + (input_line_pointer
- varstart
));
6657 /* Move init,var. */
6664 *s
++ = TOLOWER (qual
);
6666 memcpy (s
, initstart
, initstop
- initstart
);
6667 s
+= initstop
- initstart
;
6669 memcpy (s
, varstart
, varstop
- varstart
);
6670 s
+= varstop
- varstart
;
6682 *s
++ = TOLOWER (qual
);
6684 memcpy (s
, endstart
, endstop
- endstart
);
6685 s
+= endstop
- endstart
;
6687 memcpy (s
, varstart
, varstop
- varstart
);
6688 s
+= varstop
- varstart
;
6693 ex
[0] = TOLOWER (extent
);
6696 sprintf (buf
, "blt%s %s", ex
, n
->bottom
);
6698 sprintf (buf
, "bgt%s %s", ex
, n
->bottom
);
6701 /* Put together the add or sub instruction used by ENDF. */
6709 *s
++ = TOLOWER (qual
);
6711 memcpy (s
, bystart
, bystop
- bystart
);
6712 s
+= bystop
- bystart
;
6714 memcpy (s
, varstart
, varstop
- varstart
);
6715 s
+= varstop
- varstart
;
6721 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
6722 ++input_line_pointer
;
6725 demand_empty_rest_of_line ();
6728 /* Handle the MRI ENDF pseudo-op. */
6731 s_mri_endf (int ignore ATTRIBUTE_UNUSED
)
6733 if (mri_control_stack
== NULL
6734 || mri_control_stack
->type
!= mri_for
)
6736 as_bad (_("endf without for"));
6737 ignore_rest_of_line ();
6741 colon (mri_control_stack
->next
);
6743 mri_assemble (mri_control_stack
->incr
);
6745 sprintf (mri_control_stack
->incr
, "bra %s", mri_control_stack
->top
);
6746 mri_assemble (mri_control_stack
->incr
);
6748 free (mri_control_stack
->incr
);
6750 colon (mri_control_stack
->bottom
);
6756 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
6757 ++input_line_pointer
;
6760 demand_empty_rest_of_line ();
6763 /* Handle the MRI REPEAT pseudo-op. */
6766 s_mri_repeat (int ignore ATTRIBUTE_UNUSED
)
6768 struct mri_control_info
*n
;
6770 n
= push_mri_control (mri_repeat
);
6774 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
6775 ++input_line_pointer
;
6777 demand_empty_rest_of_line ();
6780 /* Handle the MRI UNTIL pseudo-op. */
6783 s_mri_until (int qual
)
6787 if (mri_control_stack
== NULL
6788 || mri_control_stack
->type
!= mri_repeat
)
6790 as_bad (_("until without repeat"));
6791 ignore_rest_of_line ();
6795 colon (mri_control_stack
->next
);
6797 for (s
= input_line_pointer
; ! is_end_of_line
[(unsigned char) *s
]; s
++)
6800 parse_mri_control_expression (s
, qual
, (const char *) NULL
,
6801 mri_control_stack
->top
, '\0');
6803 colon (mri_control_stack
->bottom
);
6805 input_line_pointer
= s
;
6811 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
6812 ++input_line_pointer
;
6815 demand_empty_rest_of_line ();
6818 /* Handle the MRI WHILE pseudo-op. */
6821 s_mri_while (int qual
)
6825 struct mri_control_info
*n
;
6827 s
= input_line_pointer
;
6828 /* We only accept '*' as introduction of comments if preceded by white space
6829 or at first column of a line (I think this can't actually happen here?)
6830 This is important when assembling:
6831 while d0 <ne> 12(a0,d0*2) do
6832 while d0 <ne> #CONST*20 do. */
6833 while (! (is_end_of_line
[(unsigned char) *s
]
6836 && (s
== input_line_pointer
6838 || *(s
-1) == '\t'))))
6841 while (*s
== ' ' || *s
== '\t')
6843 if (s
- input_line_pointer
> 1
6846 if (s
- input_line_pointer
< 2
6847 || strncasecmp (s
- 1, "DO", 2) != 0)
6849 as_bad (_("missing do"));
6850 ignore_rest_of_line ();
6854 n
= push_mri_control (mri_while
);
6858 parse_mri_control_expression (s
- 1, qual
, (const char *) NULL
, n
->bottom
,
6859 s
[1] == '.' ? s
[2] : '\0');
6861 input_line_pointer
= s
+ 1;
6862 if (*input_line_pointer
== '.')
6863 input_line_pointer
+= 2;
6867 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
6868 ++input_line_pointer
;
6871 demand_empty_rest_of_line ();
6874 /* Handle the MRI ENDW pseudo-op. */
6877 s_mri_endw (int ignore ATTRIBUTE_UNUSED
)
6881 if (mri_control_stack
== NULL
6882 || mri_control_stack
->type
!= mri_while
)
6884 as_bad (_("endw without while"));
6885 ignore_rest_of_line ();
6889 buf
= (char *) xmalloc (20 + strlen (mri_control_stack
->next
));
6890 sprintf (buf
, "bra %s", mri_control_stack
->next
);
6894 colon (mri_control_stack
->bottom
);
6900 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
6901 ++input_line_pointer
;
6904 demand_empty_rest_of_line ();
6908 Invocation line includes a switch not recognized by the base assembler.
6909 See if it's a processor-specific option. These are:
6911 -[A]m[c]68000, -[A]m[c]68008, -[A]m[c]68010, -[A]m[c]68020, -[A]m[c]68030, -[A]m[c]68040
6912 -[A]m[c]68881, -[A]m[c]68882, -[A]m[c]68851
6913 Select the architecture. Instructions or features not
6914 supported by the selected architecture cause fatal
6915 errors. More than one may be specified. The default is
6916 -m68020 -m68851 -m68881. Note that -m68008 is a synonym
6917 for -m68000, and -m68882 is a synonym for -m68881.
6918 -[A]m[c]no-68851, -[A]m[c]no-68881
6919 Don't accept 688?1 instructions. (The "c" is kind of silly,
6920 so don't use or document it, but that's the way the parsing
6924 -k Indicates PIC. (Sun 3 only.)
6926 Never turn PC-relative branches into absolute jumps.
6928 Permit `|' to be used in expressions. */
6931 const char *md_shortopts
= "lSA:m:kQ:V";
6933 const char *md_shortopts
= "lSA:m:k";
6936 struct option md_longopts
[] = {
6937 #define OPTION_PIC (OPTION_MD_BASE)
6938 {"pic", no_argument
, NULL
, OPTION_PIC
},
6939 #define OPTION_REGISTER_PREFIX_OPTIONAL (OPTION_MD_BASE + 1)
6940 {"register-prefix-optional", no_argument
, NULL
,
6941 OPTION_REGISTER_PREFIX_OPTIONAL
},
6942 #define OPTION_BITWISE_OR (OPTION_MD_BASE + 2)
6943 {"bitwise-or", no_argument
, NULL
, OPTION_BITWISE_OR
},
6944 #define OPTION_BASE_SIZE_DEFAULT_16 (OPTION_MD_BASE + 3)
6945 {"base-size-default-16", no_argument
, NULL
, OPTION_BASE_SIZE_DEFAULT_16
},
6946 #define OPTION_BASE_SIZE_DEFAULT_32 (OPTION_MD_BASE + 4)
6947 {"base-size-default-32", no_argument
, NULL
, OPTION_BASE_SIZE_DEFAULT_32
},
6948 #define OPTION_DISP_SIZE_DEFAULT_16 (OPTION_MD_BASE + 5)
6949 {"disp-size-default-16", no_argument
, NULL
, OPTION_DISP_SIZE_DEFAULT_16
},
6950 #define OPTION_DISP_SIZE_DEFAULT_32 (OPTION_MD_BASE + 6)
6951 {"disp-size-default-32", no_argument
, NULL
, OPTION_DISP_SIZE_DEFAULT_32
},
6952 #define OPTION_PCREL (OPTION_MD_BASE + 7)
6953 {"pcrel", no_argument
, NULL
, OPTION_PCREL
},
6954 {NULL
, no_argument
, NULL
, 0}
6956 size_t md_longopts_size
= sizeof (md_longopts
);
6959 md_parse_option (int c
, char *arg
)
6963 case 'l': /* -l means keep external to 2 bit offset
6964 rather than 16 bit one. */
6965 flag_short_refs
= 1;
6968 case 'S': /* -S means that jbsr's always turn into
6970 flag_long_jumps
= 1;
6973 case OPTION_PCREL
: /* --pcrel means never turn PC-relative
6974 branches into absolute jumps. */
6975 flag_keep_pcrel
= 1;
6981 /* Intentional fall-through. */
6984 if (arg
[0] == 'n' && arg
[1] == 'o' && arg
[2] == '-')
6993 if (arg
[0] == 'c' && arg
[1] == '6')
6996 for (i
= 0; i
< n_archs
; i
++)
6997 if (!strcmp (arg
, archs
[i
].name
))
7002 arch
= archs
[i
].arch
;
7005 else if (arch
== m68851
)
7014 if (arg
[0] == 'c' && arg
[1] == '6')
7017 for (i
= 0; i
< n_archs
; i
++)
7018 if (!strcmp (arg
, archs
[i
].name
))
7020 unsigned long arch
= archs
[i
].arch
;
7022 if (cpu_of_arch (arch
))
7023 /* It's a cpu spec. */
7025 current_architecture
&= ~m68000up
;
7026 current_architecture
|= arch
;
7027 current_chip
= archs
[i
].chip
;
7029 else if (arch
== m68881
)
7031 current_architecture
|= m68881
;
7034 else if (arch
== m68851
)
7036 current_architecture
|= m68851
;
7046 as_bad (_("unrecognized architecture specification `%s'"), arg
);
7055 break; /* -pic, Position Independent Code. */
7057 case OPTION_REGISTER_PREFIX_OPTIONAL
:
7058 flag_reg_prefix_optional
= 1;
7059 reg_prefix_optional_seen
= 1;
7062 /* -V: SVR4 argument to print version ID. */
7064 print_version_id ();
7067 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
7068 should be emitted or not. FIXME: Not implemented. */
7072 case OPTION_BITWISE_OR
:
7077 n
= (char *) xmalloc (strlen (m68k_comment_chars
) + 1);
7079 for (s
= m68k_comment_chars
; *s
!= '\0'; s
++)
7083 m68k_comment_chars
= n
;
7087 case OPTION_BASE_SIZE_DEFAULT_16
:
7088 m68k_index_width_default
= SIZE_WORD
;
7091 case OPTION_BASE_SIZE_DEFAULT_32
:
7092 m68k_index_width_default
= SIZE_LONG
;
7095 case OPTION_DISP_SIZE_DEFAULT_16
:
7097 m68k_rel32_from_cmdline
= 1;
7100 case OPTION_DISP_SIZE_DEFAULT_32
:
7102 m68k_rel32_from_cmdline
= 1;
7113 md_show_usage (FILE *stream
)
7115 const char *default_cpu
= TARGET_CPU
;
7117 unsigned int default_arch
;
7119 /* Get the canonical name for the default target CPU. */
7120 if (*default_cpu
== 'm')
7122 for (i
= 0; i
< n_archs
; i
++)
7124 if (strcasecmp (default_cpu
, archs
[i
].name
) == 0)
7126 default_arch
= archs
[i
].arch
;
7127 for (i
= 0; i
< n_archs
; i
++)
7129 if (archs
[i
].arch
== default_arch
7132 default_cpu
= archs
[i
].name
;
7139 fprintf (stream
, _("\
7141 -l use 1 word for refs to undefined symbols [default 2]\n\
7142 -m68000 | -m68008 | -m68010 | -m68020 | -m68030 | -m68040 | -m68060 |\n\
7143 -m68302 | -m68331 | -m68332 | -m68333 | -m68340 | -m68360 | -mcpu32 |\n\
7144 -m5200 | -m5202 | -m5204 | -m5206 | -m5206e | -m521x | -m5249 |\n\
7145 -m528x | -m5307 | -m5407 | -m547x | -m548x | -mcfv4 | -mcfv4e\n\
7146 specify variant of 680X0 architecture [default %s]\n\
7147 -m68881 | -m68882 | -mno-68881 | -mno-68882\n\
7148 target has/lacks floating-point coprocessor\n\
7149 [default yes for 68020, 68030, and cpu32]\n"),
7151 fprintf (stream
, _("\
7152 -m68851 | -mno-68851\n\
7153 target has/lacks memory-management unit coprocessor\n\
7154 [default yes for 68020 and up]\n\
7155 -pic, -k generate position independent code\n\
7156 -S turn jbsr into jsr\n\
7157 --pcrel never turn PC-relative branches into absolute jumps\n\
7158 --register-prefix-optional\n\
7159 recognize register names without prefix character\n\
7160 --bitwise-or do not treat `|' as a comment character\n"));
7161 fprintf (stream
, _("\
7162 --base-size-default-16 base reg without size is 16 bits\n\
7163 --base-size-default-32 base reg without size is 32 bits (default)\n\
7164 --disp-size-default-16 displacement with unknown size is 16 bits\n\
7165 --disp-size-default-32 displacement with unknown size is 32 bits (default)\n"));
7170 /* TEST2: Test md_assemble() */
7171 /* Warning, this routine probably doesn't work anymore. */
7175 struct m68k_it the_ins
;
7183 if (!gets (buf
) || !*buf
)
7185 if (buf
[0] == '|' || buf
[1] == '.')
7187 for (cp
= buf
; *cp
; cp
++)
7192 memset (&the_ins
, '\0', sizeof (the_ins
));
7193 m68k_ip (&the_ins
, buf
);
7196 printf (_("Error %s in %s\n"), the_ins
.error
, buf
);
7200 printf (_("Opcode(%d.%s): "), the_ins
.numo
, the_ins
.args
);
7201 for (n
= 0; n
< the_ins
.numo
; n
++)
7202 printf (" 0x%x", the_ins
.opcode
[n
] & 0xffff);
7204 print_the_insn (&the_ins
.opcode
[0], stdout
);
7205 (void) putchar ('\n');
7207 for (n
= 0; n
< strlen (the_ins
.args
) / 2; n
++)
7209 if (the_ins
.operands
[n
].error
)
7211 printf ("op%d Error %s in %s\n", n
, the_ins
.operands
[n
].error
, buf
);
7214 printf ("mode %d, reg %d, ", the_ins
.operands
[n
].mode
,
7215 the_ins
.operands
[n
].reg
);
7216 if (the_ins
.operands
[n
].b_const
)
7217 printf ("Constant: '%.*s', ",
7218 1 + the_ins
.operands
[n
].e_const
- the_ins
.operands
[n
].b_const
,
7219 the_ins
.operands
[n
].b_const
);
7220 printf ("ireg %d, isiz %d, imul %d, ", the_ins
.operands
[n
].ireg
,
7221 the_ins
.operands
[n
].isiz
, the_ins
.operands
[n
].imul
);
7222 if (the_ins
.operands
[n
].b_iadd
)
7223 printf ("Iadd: '%.*s',",
7224 1 + the_ins
.operands
[n
].e_iadd
- the_ins
.operands
[n
].b_iadd
,
7225 the_ins
.operands
[n
].b_iadd
);
7234 is_label (char *str
)
7238 while (*str
&& *str
!= ' ')
7240 if (str
[-1] == ':' || str
[1] == '=')
7247 /* Possible states for relaxation:
7249 0 0 branch offset byte (bra, etc)
7253 1 0 indexed offsets byte a0@(32,d4:w:1) etc
7257 2 0 two-offset index word-word a0@(32,d4)@(45) etc
7264 /* We have no need to default values of symbols. */
7267 md_undefined_symbol (char *name ATTRIBUTE_UNUSED
)
7272 /* Round up a section size to the appropriate boundary. */
7274 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
7277 /* For a.out, force the section size to be aligned. If we don't do
7278 this, BFD will align it for us, but it will not write out the
7279 final bytes of the section. This may be a bug in BFD, but it is
7280 easier to fix it here since that is how the other a.out targets
7284 align
= bfd_get_section_alignment (stdoutput
, segment
);
7285 size
= ((size
+ (1 << align
) - 1) & ((valueT
) -1 << align
));
7291 /* Exactly what point is a PC-relative offset relative TO?
7292 On the 68k, it is relative to the address of the first extension
7293 word. The difference between the addresses of the offset and the
7294 first extension word is stored in fx_pcrel_adjust. */
7296 md_pcrel_from (fixS
*fixP
)
7300 /* Because fx_pcrel_adjust is a char, and may be unsigned, we explicitly
7301 sign extend the value here. */
7302 adjust
= ((fixP
->fx_pcrel_adjust
& 0xff) ^ 0x80) - 0x80;
7305 return fixP
->fx_where
+ fixP
->fx_frag
->fr_address
- adjust
;
7310 m68k_elf_final_processing (void)
7312 /* Set file-specific flags if this is a cpu32 processor. */
7313 if (arch_coldfire_fpu (current_architecture
))
7314 elf_elfheader (stdoutput
)->e_flags
|= EF_CFV4E
;
7315 if (cpu_of_arch (current_architecture
) & cpu32
)
7316 elf_elfheader (stdoutput
)->e_flags
|= EF_CPU32
;
7317 else if ((cpu_of_arch (current_architecture
) & m68000up
)
7318 && !(cpu_of_arch (current_architecture
) & m68020up
))
7319 elf_elfheader (stdoutput
)->e_flags
|= EF_M68000
;
7324 tc_m68k_regname_to_dw2regnum (const char *regname
)
7326 unsigned int regnum
;
7327 static const char *const regnames
[] =
7329 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
7330 "a0", "a1", "a2", "a3", "a4", "a5", "a6", "sp",
7331 "fp0", "fp1", "fp2", "fp3", "fp4", "fp5", "fp6", "fp7",
7335 for (regnum
= 0; regnum
< ARRAY_SIZE (regnames
); regnum
++)
7336 if (strcmp (regname
, regnames
[regnum
]) == 0)
7343 tc_m68k_frame_initial_instructions (void)
7345 static int sp_regno
= -1;
7348 sp_regno
= tc_m68k_regname_to_dw2regnum ("sp");
7350 cfi_add_CFA_def_cfa (sp_regno
, -DWARF2_CIE_DATA_ALIGNMENT
);
7351 cfi_add_CFA_offset (DWARF2_DEFAULT_RETURN_COLUMN
, DWARF2_CIE_DATA_ALIGNMENT
);