* config/tc-mips.c (append_insn): Correctly handle mips16 case
[binutils.git] / ld / testsuite / ld-powerpc / tlsexe.d
blob546daf3defd8b5638d4b13660b76ced0cf1edb91
1 #source: tls.s
2 #as: -a64
3 #ld: -melf64ppc tmpdir/libtlslib.so
4 #objdump: -dr
5 #target: powerpc64*-*-*
7 .*: +file format elf64-powerpc
9 Disassembly of section \.text:
11 .* <_start-0x1c>:
12 .* 3d 82 00 00 addis r12,r2,0
13 .* f8 41 00 28 std r2,40\(r1\)
14 .* e9 6c 80 48 ld r11,-32696\(r12\)
15 .* e8 4c 80 50 ld r2,-32688\(r12\)
16 .* 7d 69 03 a6 mtctr r11
17 .* e9 6c 80 58 ld r11,-32680\(r12\)
18 .* 4e 80 04 20 bctr
20 .* <_start>:
21 .* e8 62 80 10 ld r3,-32752\(r2\)
22 .* 60 00 00 00 nop
23 .* 7c 63 6a 14 add r3,r3,r13
24 .* 38 62 80 18 addi r3,r2,-32744
25 .* 4b ff ff d5 bl .*
26 .* e8 41 00 28 ld r2,40\(r1\)
27 .* 3c 6d 00 00 addis r3,r13,0
28 .* 60 00 00 00 nop
29 .* 38 63 90 38 addi r3,r3,-28616
30 .* 3c 6d 00 00 addis r3,r13,0
31 .* 60 00 00 00 nop
32 .* 38 63 10 00 addi r3,r3,4096
33 .* 39 23 80 40 addi r9,r3,-32704
34 .* 3d 23 00 00 addis r9,r3,0
35 .* 81 49 80 48 lwz r10,-32696\(r9\)
36 .* e9 22 80 28 ld r9,-32728\(r2\)
37 .* 7d 49 18 2a ldx r10,r9,r3
38 .* 3d 2d 00 00 addis r9,r13,0
39 .* a1 49 90 58 lhz r10,-28584\(r9\)
40 .* 89 4d 90 60 lbz r10,-28576\(r13\)
41 .* 3d 2d 00 00 addis r9,r13,0
42 .* 99 49 90 68 stb r10,-28568\(r9\)
43 .* 3c 6d 00 00 addis r3,r13,0
44 .* 60 00 00 00 nop
45 .* 38 63 90 00 addi r3,r3,-28672
46 .* 3c 6d 00 00 addis r3,r13,0
47 .* 60 00 00 00 nop
48 .* 38 63 10 00 addi r3,r3,4096
49 .* f9 43 80 08 std r10,-32760\(r3\)
50 .* 3d 23 00 00 addis r9,r3,0
51 .* 91 49 80 10 stw r10,-32752\(r9\)
52 .* e9 22 80 08 ld r9,-32760\(r2\)
53 .* 7d 49 19 2a stdx r10,r9,r3
54 .* 3d 2d 00 00 addis r9,r13,0
55 .* b1 49 90 58 sth r10,-28584\(r9\)
56 .* e9 4d 90 2a lwa r10,-28632\(r13\)
57 .* 3d 2d 00 00 addis r9,r13,0
58 .* a9 49 90 30 lha r10,-28624\(r9\)
59 .* 7d 89 02 a6 mfctr r12
60 .* 78 0b 1f 24 rldicr r11,r0,3,60
61 .* 34 40 80 00 addic\. r2,r0,-32768
62 .* 7d 8b 60 50 subf r12,r11,r12
63 .* 7c 42 fe 76 sradi r2,r2,63
64 .* 78 0b 17 64 rldicr r11,r0,2,61
65 .* 7c 42 58 38 and r2,r2,r11
66 .* 7d 8b 60 50 subf r12,r11,r12
67 .* 7d 8c 12 14 add r12,r12,r2
68 .* 3d 8c 00 01 addis r12,r12,1
69 .* e9 6c 01 c4 ld r11,452\(r12\)
70 .* 39 8c 01 c4 addi r12,r12,452
71 .* e8 4c 00 08 ld r2,8\(r12\)
72 .* 7d 69 03 a6 mtctr r11
73 .* e9 6c 00 10 ld r11,16\(r12\)
74 .* 4e 80 04 20 bctr
75 .* 38 00 00 00 li r0,0
76 .* 4b ff ff bc b .*