include/opcode/ia64.h

   1 /* ia64.h -- Header file for ia64 opcode table
   2    Copyright (C) 1998, 1999, 2000, 2002, 2005, 2006
   3    Free Software Foundation, Inc.
   4    Contributed by David Mosberger-Tang <davidm@hpl.hp.com> */
   5
   6 #ifndef opcode_ia64_h
   7 #define opcode_ia64_h
   8
   9 #include <sys/types.h>
  10
  11 #include "bfd.h"
  12
  13
  14 typedef BFD_HOST_U_64_BIT ia64_insn;
  15
  16 enum ia64_insn_type
  17   {
  18     IA64_TYPE_NIL = 0,  /* illegal type */
  19     IA64_TYPE_A,        /* integer alu (I- or M-unit) */
  20     IA64_TYPE_I,        /* non-alu integer (I-unit) */
  21     IA64_TYPE_M,        /* memory (M-unit) */
  22     IA64_TYPE_B,        /* branch (B-unit) */
  23     IA64_TYPE_F,        /* floating-point (F-unit) */
  24     IA64_TYPE_X,        /* long encoding (X-unit) */
  25     IA64_TYPE_DYN,      /* Dynamic opcode */
  26     IA64_NUM_TYPES
  27   };
  28
  29 enum ia64_unit
  30   {
  31     IA64_UNIT_NIL = 0,  /* illegal unit */
  32     IA64_UNIT_I,        /* integer unit */
  33     IA64_UNIT_M,        /* memory unit */
  34     IA64_UNIT_B,        /* branching unit */
  35     IA64_UNIT_F,        /* floating-point unit */
  36     IA64_UNIT_L,        /* long "unit" */
  37     IA64_UNIT_X,        /* may be integer or branch unit */
  38     IA64_NUM_UNITS
  39   };
  40
  41 /* Changes to this enumeration must be propagated to the operand table in
  42    bfd/cpu-ia64-opc.c
  43  */
  44 enum ia64_opnd
  45   {
  46     IA64_OPND_NIL,      /* no operand---MUST BE FIRST!*/
  47
  48     /* constants */
  49     IA64_OPND_AR_CSD,   /* application register csd (ar.csd) */
  50     IA64_OPND_AR_CCV,   /* application register ccv (ar.ccv) */
  51     IA64_OPND_AR_PFS,   /* application register pfs (ar.pfs) */
  52     IA64_OPND_C1,       /* the constant 1 */
  53     IA64_OPND_C8,       /* the constant 8 */
  54     IA64_OPND_C16,      /* the constant 16 */
  55     IA64_OPND_GR0,      /* gr0 */
  56     IA64_OPND_IP,       /* instruction pointer (ip) */
  57     IA64_OPND_PR,       /* predicate register (pr) */
  58     IA64_OPND_PR_ROT,   /* rotating predicate register (pr.rot) */
  59     IA64_OPND_PSR,      /* processor status register (psr) */
  60     IA64_OPND_PSR_L,    /* processor status register L (psr.l) */
  61     IA64_OPND_PSR_UM,   /* processor status register UM (psr.um) */
  62
  63     /* register operands: */
  64     IA64_OPND_AR3,      /* third application register # (bits 20-26) */
  65     IA64_OPND_B1,       /* branch register # (bits 6-8) */
  66     IA64_OPND_B2,       /* branch register # (bits 13-15) */
  67     IA64_OPND_CR3,      /* third control register # (bits 20-26) */
  68     IA64_OPND_F1,       /* first floating-point register # */
  69     IA64_OPND_F2,       /* second floating-point register # */
  70     IA64_OPND_F3,       /* third floating-point register # */
  71     IA64_OPND_F4,       /* fourth floating-point register # */
  72     IA64_OPND_P1,       /* first predicate # */
  73     IA64_OPND_P2,       /* second predicate # */
  74     IA64_OPND_R1,       /* first register # */
  75     IA64_OPND_R2,       /* second register # */
  76     IA64_OPND_R3,       /* third register # */
  77     IA64_OPND_R3_2,     /* third register # (limited to gr0-gr3) */
  78
  79     /* memory operands: */
  80     IA64_OPND_MR3,      /* memory at addr of third register # */
  81
  82     /* indirect operands: */
  83     IA64_OPND_CPUID_R3, /* cpuid[reg] */
  84     IA64_OPND_DBR_R3,   /* dbr[reg] */
  85     IA64_OPND_DTR_R3,   /* dtr[reg] */
  86     IA64_OPND_ITR_R3,   /* itr[reg] */
  87     IA64_OPND_IBR_R3,   /* ibr[reg] */
  88     IA64_OPND_MSR_R3,   /* msr[reg] */
  89     IA64_OPND_PKR_R3,   /* pkr[reg] */
  90     IA64_OPND_PMC_R3,   /* pmc[reg] */
  91     IA64_OPND_PMD_R3,   /* pmd[reg] */
  92     IA64_OPND_RR_R3,    /* rr[reg] */
  93
  94     /* immediate operands: */
  95     IA64_OPND_CCNT5,    /* 5-bit count (31 - bits 20-24) */
  96     IA64_OPND_CNT2a,    /* 2-bit count (1 + bits 27-28) */
  97     IA64_OPND_CNT2b,    /* 2-bit count (bits 27-28): 1, 2, 3 */
  98     IA64_OPND_CNT2c,    /* 2-bit count (bits 30-31): 0, 7, 15, or 16 */
  99     IA64_OPND_CNT5,     /* 5-bit count (bits 14-18) */
 100     IA64_OPND_CNT6,     /* 6-bit count (bits 27-32) */
 101     IA64_OPND_CPOS6a,   /* 6-bit count (63 - bits 20-25) */
 102     IA64_OPND_CPOS6b,   /* 6-bit count (63 - bits 14-19) */
 103     IA64_OPND_CPOS6c,   /* 6-bit count (63 - bits 31-36) */
 104     IA64_OPND_IMM1,     /* signed 1-bit immediate (bit 36) */
 105     IA64_OPND_IMMU2,    /* unsigned 2-bit immediate (bits 13-14) */
 106     IA64_OPND_IMMU5b,   /* unsigned 5-bit immediate (32 + bits 14-18) */
 107     IA64_OPND_IMMU7a,   /* unsigned 7-bit immediate (bits 13-19) */
 108     IA64_OPND_IMMU7b,   /* unsigned 7-bit immediate (bits 20-26) */
 109     IA64_OPND_SOF,      /* 8-bit stack frame size */
 110     IA64_OPND_SOL,      /* 8-bit size of locals */
 111     IA64_OPND_SOR,      /* 6-bit number of rotating registers (scaled by 8) */
 112     IA64_OPND_IMM8,     /* signed 8-bit immediate (bits 13-19 & 36) */
 113     IA64_OPND_IMM8U4,   /* cmp4*u signed 8-bit immediate (bits 13-19 & 36) */
 114     IA64_OPND_IMM8M1,   /* signed 8-bit immediate -1 (bits 13-19 & 36) */
 115     IA64_OPND_IMM8M1U4, /* cmp4*u signed 8-bit immediate -1 (bits 13-19 & 36)*/
 116     IA64_OPND_IMM8M1U8, /* cmp*u signed 8-bit immediate -1 (bits 13-19 & 36) */
 117     IA64_OPND_IMMU9,    /* unsigned 9-bit immediate (bits 33-34, 20-26) */
 118     IA64_OPND_IMM9a,    /* signed 9-bit immediate (bits 6-12, 27, 36) */
 119     IA64_OPND_IMM9b,    /* signed 9-bit immediate (bits 13-19, 27, 36) */
 120     IA64_OPND_IMM14,    /* signed 14-bit immediate (bits 13-19, 27-32, 36) */
 121     IA64_OPND_IMM17,    /* signed 17-bit immediate (2*bits 6-12, 24-31, 36) */
 122     IA64_OPND_IMMU21,   /* unsigned 21-bit immediate (bits 6-25, 36) */
 123     IA64_OPND_IMM22,    /* signed 22-bit immediate (bits 13-19, 22-36) */
 124     IA64_OPND_IMMU24,   /* unsigned 24-bit immediate (bits 6-26, 31-32, 36) */
 125     IA64_OPND_IMM44,    /* signed 44-bit immediate (2^16*bits 6-32, 36) */
 126     IA64_OPND_IMMU62,   /* unsigned 62-bit immediate */
 127     IA64_OPND_IMMU64,   /* unsigned 64-bit immediate (lotsa bits...) */
 128     IA64_OPND_INC3,     /* signed 3-bit (bits 13-15): +/-1, 4, 8, 16 */
 129     IA64_OPND_LEN4,     /* 4-bit count (bits 27-30 + 1) */
 130     IA64_OPND_LEN6,     /* 6-bit count (bits 27-32 + 1) */
 131     IA64_OPND_MBTYPE4,  /* 4-bit mux type (bits 20-23) */
 132     IA64_OPND_MHTYPE8,  /* 8-bit mux type (bits 20-27) */
 133     IA64_OPND_POS6,     /* 6-bit count (bits 14-19) */
 134     IA64_OPND_TAG13,    /* signed 13-bit tag (ip + 16*bits 6-12, 33-34) */
 135     IA64_OPND_TAG13b,   /* signed 13-bit tag (ip + 16*bits 24-32) */
 136     IA64_OPND_TGT25,    /* signed 25-bit (ip + 16*bits 6-25, 36) */
 137     IA64_OPND_TGT25b,   /* signed 25-bit (ip + 16*bits 6-12, 20-32, 36) */
 138     IA64_OPND_TGT25c,   /* signed 25-bit (ip + 16*bits 13-32, 36) */
 139     IA64_OPND_TGT64,    /* 64-bit (ip + 16*bits 13-32, 36, 2-40(L)) */
 140     IA64_OPND_LDXMOV,   /* any symbol, generates R_IA64_LDXMOV.  */
 141
 142     IA64_OPND_COUNT     /* # of operand types (MUST BE LAST!) */
 143   };
 144
 145 enum ia64_dependency_mode
 146 {
 147   IA64_DV_RAW,
 148   IA64_DV_WAW,
 149   IA64_DV_WAR,
 150 };
 151
 152 enum ia64_dependency_semantics
 153 {
 154   IA64_DVS_NONE,
 155   IA64_DVS_IMPLIED,
 156   IA64_DVS_IMPLIEDF,
 157   IA64_DVS_DATA,
 158   IA64_DVS_INSTR,
 159   IA64_DVS_SPECIFIC,
 160   IA64_DVS_STOP,
 161   IA64_DVS_OTHER,
 162 };
 163
 164 enum ia64_resource_specifier
 165 {
 166   IA64_RS_ANY,
 167   IA64_RS_AR_K,
 168   IA64_RS_AR_UNAT,
 169   IA64_RS_AR, /* 8-15, 20, 22-23, 31, 33-35, 37-39, 41-43, 45-47, 67-111 */
 170   IA64_RS_ARb, /* 48-63, 112-127 */
 171   IA64_RS_BR,
 172   IA64_RS_CFM,
 173   IA64_RS_CPUID,
 174   IA64_RS_CR_IRR,
 175   IA64_RS_CR_LRR,
 176   IA64_RS_CR, /* 3-7,10-15,18,26-63,75-79,82-127 */
 177   IA64_RS_DBR,
 178   IA64_RS_FR,
 179   IA64_RS_FRb,
 180   IA64_RS_GR0,
 181   IA64_RS_GR,
 182   IA64_RS_IBR,
 183   IA64_RS_INSERVICE, /* CR[EOI] or CR[IVR] */
 184   IA64_RS_MSR,
 185   IA64_RS_PKR,
 186   IA64_RS_PMC,
 187   IA64_RS_PMD,
 188   IA64_RS_PR,  /* non-rotating, 1-15 */
 189   IA64_RS_PRr, /* rotating, 16-62 */
 190   IA64_RS_PR63,
 191   IA64_RS_RR,
 192
 193   IA64_RS_ARX, /* ARs not in RS_AR or RS_ARb */
 194   IA64_RS_CRX, /* CRs not in RS_CR */
 195   IA64_RS_PSR, /* PSR bits */
 196   IA64_RS_RSE, /* implementation-specific RSE resources */
 197   IA64_RS_AR_FPSR,
 198 };
 199
 200 enum ia64_rse_resource
 201 {
 202   IA64_RSE_N_STACKED_PHYS,
 203   IA64_RSE_BOF,
 204   IA64_RSE_STORE_REG,
 205   IA64_RSE_LOAD_REG,
 206   IA64_RSE_BSPLOAD,
 207   IA64_RSE_RNATBITINDEX,
 208   IA64_RSE_CFLE,
 209   IA64_RSE_NDIRTY,
 210 };
 211
 212 /* Information about a given resource dependency */
 213 struct ia64_dependency
 214 {
 215   /* Name of the resource */
 216   const char *name;
 217   /* Does this dependency need further specification? */
 218   enum ia64_resource_specifier specifier;
 219   /* Mode of dependency */
 220   enum ia64_dependency_mode mode;
 221   /* Dependency semantics */
 222   enum ia64_dependency_semantics semantics;
 223   /* Register index, if applicable (distinguishes AR, CR, and PSR deps) */
 224 #define REG_NONE (-1)
 225   int regindex;
 226   /* Special info on semantics */
 227   const char *info;
 228 };
 229
 230 /* Two arrays of indexes into the ia64_dependency table.
 231    chks are dependencies to check for conflicts when an opcode is
 232    encountered; regs are dependencies to register (mark as used) when an
 233    opcode is used.  chks correspond to readers (RAW) or writers (WAW or
 234    WAR) of a resource, while regs correspond to writers (RAW or WAW) and
 235    readers (WAR) of a resource.  */
 236 struct ia64_opcode_dependency
 237 {
 238   int nchks;
 239   const unsigned short *chks;
 240   int nregs;
 241   const unsigned short *regs;
 242 };
 243
 244 /* encode/extract the note/index for a dependency */
 245 #define RDEP(N,X) (((N)<<11)|(X))
 246 #define NOTE(X) (((X)>>11)&0x1F)
 247 #define DEP(X) ((X)&0x7FF)
 248
 249 /* A template descriptor describes the execution units that are active
 250    for each of the three slots.  It also specifies the location of
 251    instruction group boundaries that may be present between two slots.  */
 252 struct ia64_templ_desc
 253   {
 254     int group_boundary; /* 0=no boundary, 1=between slot 0 & 1, etc. */
 255     enum ia64_unit exec_unit[3];
 256     const char *name;
 257   };
 258
 259 /* The opcode table is an array of struct ia64_opcode.  */
 260
 261 struct ia64_opcode
 262   {
 263     /* The opcode name.  */
 264     const char *name;
 265
 266     /* The type of the instruction: */
 267     enum ia64_insn_type type;
 268
 269     /* Number of output operands: */
 270     int num_outputs;
 271
 272     /* The opcode itself.  Those bits which will be filled in with
 273        operands are zeroes.  */
 274     ia64_insn opcode;
 275
 276     /* The opcode mask.  This is used by the disassembler.  This is a
 277        mask containing ones indicating those bits which must match the
 278        opcode field, and zeroes indicating those bits which need not
 279        match (and are presumably filled in by operands).  */
 280     ia64_insn mask;
 281
 282     /* An array of operand codes.  Each code is an index into the
 283        operand table.  They appear in the order which the operands must
 284        appear in assembly code, and are terminated by a zero.  */
 285     enum ia64_opnd operands[5];
 286
 287     /* One bit flags for the opcode.  These are primarily used to
 288        indicate specific processors and environments support the
 289        instructions.  The defined values are listed below. */
 290     unsigned int flags;
 291
 292     /* Used by ia64_find_next_opcode (). */
 293     short ent_index;
 294
 295     /* Opcode dependencies. */
 296     const struct ia64_opcode_dependency *dependencies;
 297   };
 298
 299 /* Values defined for the flags field of a struct ia64_opcode.  */
 300
 301 #define IA64_OPCODE_FIRST       (1<<0)  /* must be first in an insn group */
 302 #define IA64_OPCODE_X_IN_MLX    (1<<1)  /* insn is allowed in X slot of MLX */
 303 #define IA64_OPCODE_LAST        (1<<2)  /* must be last in an insn group */
 304 #define IA64_OPCODE_PRIV        (1<<3)  /* privileged instruct */
 305 #define IA64_OPCODE_SLOT2       (1<<4)  /* insn allowed in slot 2 only */
 306 #define IA64_OPCODE_NO_PRED     (1<<5)  /* insn cannot be predicated */
 307 #define IA64_OPCODE_PSEUDO      (1<<6)  /* insn is a pseudo-op */
 308 #define IA64_OPCODE_F2_EQ_F3    (1<<7)  /* constraint: F2 == F3 */
 309 #define IA64_OPCODE_LEN_EQ_64MCNT       (1<<8)  /* constraint: LEN == 64-CNT */
 310 #define IA64_OPCODE_MOD_RRBS    (1<<9)  /* modifies all rrbs in CFM */
 311 #define IA64_OPCODE_POSTINC     (1<<10) /* postincrement MR3 operand */
 312
 313 /* A macro to extract the major opcode from an instruction.  */
 314 #define IA64_OP(i)      (((i) >> 37) & 0xf)
 315
 316 enum ia64_operand_class
 317   {
 318     IA64_OPND_CLASS_CST,        /* constant */
 319     IA64_OPND_CLASS_REG,        /* register */
 320     IA64_OPND_CLASS_IND,        /* indirect register */
 321     IA64_OPND_CLASS_ABS,        /* absolute value */
 322     IA64_OPND_CLASS_REL,        /* IP-relative value */
 323   };
 324
 325 /* The operands table is an array of struct ia64_operand.  */
 326
 327 struct ia64_operand
 328 {
 329   enum ia64_operand_class class;
 330
 331   /* Set VALUE as the operand bits for the operand of type SELF in the
 332      instruction pointed to by CODE.  If an error occurs, *CODE is not
 333      modified and the returned string describes the cause of the
 334      error.  If no error occurs, NULL is returned.  */
 335   const char *(*insert) (const struct ia64_operand *self, ia64_insn value,
 336                          ia64_insn *code);
 337
 338   /* Extract the operand bits for an operand of type SELF from
 339      instruction CODE store them in *VALUE.  If an error occurs, the
 340      cause of the error is described by the string returned.  If no
 341      error occurs, NULL is returned.  */
 342   const char *(*extract) (const struct ia64_operand *self, ia64_insn code,
 343                           ia64_insn *value);
 344
 345   /* A string whose meaning depends on the operand class.  */
 346
 347   const char *str;
 348
 349   struct bit_field
 350     {
 351       /* The number of bits in the operand.  */
 352       int bits;
 353
 354       /* How far the operand is left shifted in the instruction.  */
 355       int shift;
 356     }
 357   field[4];             /* no operand has more than this many bit-fields */
 358
 359   unsigned int flags;
 360
 361   const char *desc;     /* brief description */
 362 };
 363
 364 /* Values defined for the flags field of a struct ia64_operand.  */
 365
 366 /* Disassemble as signed decimal (instead of hex): */
 367 #define IA64_OPND_FLAG_DECIMAL_SIGNED   (1<<0)
 368 /* Disassemble as unsigned decimal (instead of hex): */
 369 #define IA64_OPND_FLAG_DECIMAL_UNSIGNED (1<<1)
 370
 371 extern const struct ia64_templ_desc ia64_templ_desc[16];
 372
 373 /* The tables are sorted by major opcode number and are otherwise in
 374    the order in which the disassembler should consider instructions.  */
 375 extern struct ia64_opcode ia64_opcodes_a[];
 376 extern struct ia64_opcode ia64_opcodes_i[];
 377 extern struct ia64_opcode ia64_opcodes_m[];
 378 extern struct ia64_opcode ia64_opcodes_b[];
 379 extern struct ia64_opcode ia64_opcodes_f[];
 380 extern struct ia64_opcode ia64_opcodes_d[];
 381
 382
 383 extern struct ia64_opcode *ia64_find_opcode (const char *name);
 384 extern struct ia64_opcode *ia64_find_next_opcode (struct ia64_opcode *ent);
 385
 386 extern struct ia64_opcode *ia64_dis_opcode (ia64_insn insn,
 387                                             enum ia64_insn_type type);
 388
 389 extern void ia64_free_opcode (struct ia64_opcode *ent);
 390 extern const struct ia64_dependency *ia64_find_dependency (int index);
 391
 392 /* To avoid circular library dependencies, this array is implemented
 393    in bfd/cpu-ia64-opc.c: */
 394 extern const struct ia64_operand elf64_ia64_operands[IA64_OPND_COUNT];
 395
 396 #endif /* opcode_ia64_h */