1 /* bfin-defs.h ADI Blackfin gas header file
3 Free Software Foundation, Inc.
5 This file is part of GAS, the GNU Assembler.
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to the Free
19 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
26 #define CODE_FRAG_SIZE 4096 /* 1 page. */
29 /* Definition for all status bits. */
69 /* High-Nibble: group code, low nibble: register code. */
80 /* All registers above this value don't
81 belong to a usuable register group. */
82 #define T_NOGROUP 0xa0
85 #define F_REG_ALL 0x1000
86 #define F_REG_HIGH 0x2000 /* Half register: high half. */
88 enum machine_registers
90 REG_R0
= T_REG_R
, REG_R1
, REG_R2
, REG_R3
, REG_R4
, REG_R5
, REG_R6
, REG_R7
,
91 REG_P0
= T_REG_P
, REG_P1
, REG_P2
, REG_P3
, REG_P4
, REG_P5
, REG_SP
, REG_FP
,
92 REG_I0
= T_REG_I
, REG_I1
, REG_I2
, REG_I3
,
93 REG_M0
= T_REG_M
, REG_M1
, REG_M2
, REG_M3
,
94 REG_B0
= T_REG_B
, REG_B1
, REG_B2
, REG_B3
,
95 REG_L0
= T_REG_L
, REG_L1
, REG_L2
, REG_L3
,
96 REG_A0x
= T_REG_A
, REG_A0w
, REG_A1x
, REG_A1w
,
99 REG_LC0
= 0x60, REG_LT0
, REG_LB0
, REG_LC1
, REG_LT1
, REG_LB1
,
100 REG_CYCLES
, REG_CYCLES2
,
101 REG_USP
= 0x70, REG_SEQSTAT
, REG_SYSCFG
,
102 REG_RETI
, REG_RETX
, REG_RETN
, REG_RETE
, REG_EMUDAT
,
104 /* These don't have groups. */
105 REG_sftreset
= T_NOGROUP
, REG_omode
, REG_excause
, REG_emucause
,
106 REG_idle_req
, REG_hwerrcause
,
107 REG_A0
= 0xc0, REG_A1
, REG_CC
,
108 /* Pseudo registers, used only for distinction from symbols. */
109 REG_RL0
, REG_RL1
, REG_RL2
, REG_RL3
,
110 REG_RL4
, REG_RL5
, REG_RL6
, REG_RL7
,
111 REG_RH0
, REG_RH1
, REG_RH2
, REG_RH3
,
112 REG_RH4
, REG_RH5
, REG_RH6
, REG_RH7
,
116 /* Status register flags. */
176 /* Register type checking macros. */
178 #define CODE_MASK 0x07
179 #define CLASS_MASK 0xf0
181 #define REG_SAME(a, b) ((a).regno == (b).regno)
182 #define REG_EQUAL(a, b) (((a).regno & CODE_MASK) == ((b).regno & CODE_MASK))
183 #define REG_CLASS(a) ((a.regno) & 0xf0)
184 #define IS_A1(a) ((a).regno == REG_A1)
185 #define IS_H(a) ((a).regno & F_REG_HIGH ? 1: 0)
186 #define IS_EVEN(r) (r.regno % 2 == 0)
187 #define IS_HCOMPL(a, b) (REG_EQUAL(a, b) && \
188 ((a).regno & F_REG_HIGH) != ((b).regno & F_REG_HIGH))
190 /* register type checking. */
191 #define _TYPECHECK(r, x) (((r).regno & CLASS_MASK) == T_REG_##x)
193 #define IS_DREG(r) _TYPECHECK(r, R)
194 #define IS_DREG_H(r) (_TYPECHECK(r, R) && IS_H(r))
195 #define IS_DREG_L(r) (_TYPECHECK(r, R) && !IS_H(r))
196 #define IS_PREG(r) _TYPECHECK(r, P)
197 #define IS_IREG(r) (((r).regno & 0xf4) == T_REG_I)
198 #define IS_MREG(r) (((r).regno & 0xf4) == T_REG_M)
199 #define IS_BREG(r) (((r).regno & 0xf4) == T_REG_B)
200 #define IS_LREG(r) (((r).regno & 0xf4) == T_REG_L)
201 #define IS_CREG(r) ((r).regno == REG_LC0 || (r).regno == REG_LC1)
202 #define IS_ALLREG(r) ((r).regno < T_NOGROUP)
204 /* Expression value macros. */
224 #define SYMBOL_T symbolS*
226 struct expression_cell
232 /* User Type Definitions. */
236 struct bfin_insn
*next
;
237 struct expression_cell
*exp
;
242 #define INSTR_T struct bfin_insn*
243 #define EXPR_T struct expression_cell*
245 typedef struct expr_node_struct Expr_Node
;
247 extern INSTR_T
gencode (unsigned long x
);
248 extern INSTR_T
conscode (INSTR_T head
, INSTR_T tail
);
249 extern INSTR_T
conctcode (INSTR_T head
, INSTR_T tail
);
250 extern INSTR_T note_reloc
251 (INSTR_T code
, Expr_Node
*, int reloc
,int pcrel
);
252 extern INSTR_T note_reloc1
253 (INSTR_T code
, const char * sym
, int reloc
, int pcrel
);
254 extern INSTR_T note_reloc2
255 (INSTR_T code
, const char *symbol
, int reloc
, int value
, int pcrel
);
257 /* Types of expressions. */
260 Expr_Node_Binop
, /* Binary operator. */
261 Expr_Node_Unop
, /* Unary operator. */
262 Expr_Node_Reloc
, /* Symbol to be relocated. */
263 Expr_Node_GOT_Reloc
, /* Symbol to be relocated using the GOT. */
264 Expr_Node_Constant
/* Constant. */
267 /* Types of operators. */
277 Expr_Op_Type_BAND
, /* Bitwise AND. */
278 Expr_Op_Type_BOR
, /* Bitwise OR. */
279 Expr_Op_Type_BXOR
, /* Bitwise exclusive OR. */
280 Expr_Op_Type_LAND
, /* Logical AND. */
281 Expr_Op_Type_LOR
, /* Logical OR. */
283 Expr_Op_Type_COMP
/* Complement. */
286 /* The value that can be stored ... depends on type. */
289 const char *s_value
; /* if relocation symbol, the text. */
290 int i_value
; /* if constant, the value. */
291 Expr_Op_Type op_value
; /* if operator, the value. */
294 /* The expression node. */
295 struct expr_node_struct
298 Expr_Node_Value value
;
299 Expr_Node
*Left_Child
;
300 Expr_Node
*Right_Child
;
304 /* Operations on the expression node. */
305 Expr_Node
*Expr_Node_Create (Expr_Node_Type type
,
306 Expr_Node_Value value
,
307 Expr_Node
*Left_Child
,
308 Expr_Node
*Right_Child
);
310 /* Generate the reloc structure as a series of instructions. */
311 INSTR_T
Expr_Node_Gen_Reloc (Expr_Node
*head
, int parent_reloc
);
313 #define MKREF(x) mkexpr (0,x)
314 #define ALLOCATE(x) malloc (x)
316 #define NULL_CODE ((INSTR_T) 0)
319 #define EXPR_VALUE(x) (((x)->type == Expr_Node_Constant) ? ((x)->value.i_value) : 0)
322 #define EXPR_SYMBOL(x) ((x)->symbol)
329 typedef struct _register
331 reg_t regno
; /* Register ID as defined in machine_registers. */
336 typedef struct _macfunc
347 typedef struct _opt_mode
365 extern int debug_codeselection
;
367 void error (char *format
, ...);
368 void warn (char *format
, ...);
369 int semantic_error (char *syntax
);
370 void semantic_error_2 (char *syntax
);
372 EXPR_T
mkexpr (int, SYMBOL_T
);
374 /* Defined in bfin-lex.l. */
375 void set_start_state (void);
381 #endif /* BFIN_PARSE_H */