1 /* Assemble Matsushita MN10300 instructions.
2 Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2003, 2004
3 Free Software Foundation, Inc.
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the Free Software
17 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
19 /* This file is formatted at > 80 columns. Attempting to read it on a
20 screeen with less than 80 columns will be difficult. */
22 #include "opcode/mn10300.h"
25 const struct mn10300_operand mn10300_operands
[] = {
29 /* dn register in the first register operand position. */
30 #define DN0 (UNUSED+1)
31 {2, 0, MN10300_OPERAND_DREG
},
33 /* dn register in the second register operand position. */
35 {2, 2, MN10300_OPERAND_DREG
},
37 /* dn register in the third register operand position. */
39 {2, 4, MN10300_OPERAND_DREG
},
41 /* dm register in the first register operand position. */
43 {2, 0, MN10300_OPERAND_DREG
},
45 /* dm register in the second register operand position. */
47 {2, 2, MN10300_OPERAND_DREG
},
49 /* dm register in the third register operand position. */
51 {2, 4, MN10300_OPERAND_DREG
},
53 /* an register in the first register operand position. */
55 {2, 0, MN10300_OPERAND_AREG
},
57 /* an register in the second register operand position. */
59 {2, 2, MN10300_OPERAND_AREG
},
61 /* an register in the third register operand position. */
63 {2, 4, MN10300_OPERAND_AREG
},
65 /* am register in the first register operand position. */
67 {2, 0, MN10300_OPERAND_AREG
},
69 /* am register in the second register operand position. */
71 {2, 2, MN10300_OPERAND_AREG
},
73 /* am register in the third register operand position. */
75 {2, 4, MN10300_OPERAND_AREG
},
77 /* 8 bit unsigned immediate which may promote to a 16bit
78 unsigned immediate. */
80 {8, 0, MN10300_OPERAND_PROMOTE
},
82 /* 16 bit unsigned immediate which may promote to a 32bit
83 unsigned immediate. */
84 #define IMM16 (IMM8+1)
85 {16, 0, MN10300_OPERAND_PROMOTE
},
87 /* 16 bit pc-relative immediate which may promote to a 16bit
88 pc-relative immediate. */
89 #define IMM16_PCREL (IMM16+1)
90 {16, 0, MN10300_OPERAND_PCREL
| MN10300_OPERAND_RELAX
| MN10300_OPERAND_SIGNED
},
92 /* 16bit unsigned displacement in a memory operation which
93 may promote to a 32bit displacement. */
94 #define IMM16_MEM (IMM16_PCREL+1)
95 {16, 0, MN10300_OPERAND_PROMOTE
| MN10300_OPERAND_MEMADDR
},
97 /* 32bit immediate, high 16 bits in the main instruction
98 word, 16bits in the extension word.
100 The "bits" field indicates how many bits are in the
101 main instruction word for MN10300_OPERAND_SPLIT! */
102 #define IMM32 (IMM16_MEM+1)
103 {16, 0, MN10300_OPERAND_SPLIT
},
105 /* 32bit pc-relative offset. */
106 #define IMM32_PCREL (IMM32+1)
107 {16, 0, MN10300_OPERAND_SPLIT
| MN10300_OPERAND_PCREL
},
109 /* 32bit memory offset. */
110 #define IMM32_MEM (IMM32_PCREL+1)
111 {16, 0, MN10300_OPERAND_SPLIT
| MN10300_OPERAND_MEMADDR
},
113 /* 32bit immediate, high 16 bits in the main instruction
114 word, 16bits in the extension word, low 16bits are left
117 The "bits" field indicates how many bits are in the
118 main instruction word for MN10300_OPERAND_SPLIT! */
119 #define IMM32_LOWSHIFT8 (IMM32_MEM+1)
120 {16, 8, MN10300_OPERAND_SPLIT
| MN10300_OPERAND_MEMADDR
},
122 /* 32bit immediate, high 24 bits in the main instruction
123 word, 8 in the extension word.
125 The "bits" field indicates how many bits are in the
126 main instruction word for MN10300_OPERAND_SPLIT! */
127 #define IMM32_HIGH24 (IMM32_LOWSHIFT8+1)
128 {24, 0, MN10300_OPERAND_SPLIT
| MN10300_OPERAND_PCREL
},
130 /* 32bit immediate, high 24 bits in the main instruction
131 word, 8 in the extension word, low 8 bits are left
134 The "bits" field indicates how many bits are in the
135 main instruction word for MN10300_OPERAND_SPLIT! */
136 #define IMM32_HIGH24_LOWSHIFT16 (IMM32_HIGH24+1)
137 {24, 16, MN10300_OPERAND_SPLIT
| MN10300_OPERAND_PCREL
},
140 #define SP (IMM32_HIGH24_LOWSHIFT16+1)
141 {8, 0, MN10300_OPERAND_SP
},
143 /* Processor status word. */
145 {0, 0, MN10300_OPERAND_PSW
},
149 {0, 0, MN10300_OPERAND_MDR
},
151 /* Index register. */
153 {2, 2, MN10300_OPERAND_DREG
},
155 /* 8 bit signed displacement, may promote to 16bit signed displacement. */
157 {8, 0, MN10300_OPERAND_SIGNED
| MN10300_OPERAND_PROMOTE
},
159 /* 16 bit signed displacement, may promote to 32bit displacement. */
161 {16, 0, MN10300_OPERAND_SIGNED
| MN10300_OPERAND_PROMOTE
},
163 /* 8 bit signed displacement that can not promote. */
164 #define SD8N (SD16+1)
165 {8, 0, MN10300_OPERAND_SIGNED
},
167 /* 8 bit pc-relative displacement. */
168 #define SD8N_PCREL (SD8N+1)
169 {8, 0, MN10300_OPERAND_SIGNED
| MN10300_OPERAND_PCREL
| MN10300_OPERAND_RELAX
},
171 /* 8 bit signed displacement shifted left 8 bits in the instruction. */
172 #define SD8N_SHIFT8 (SD8N_PCREL+1)
173 {8, 8, MN10300_OPERAND_SIGNED
},
175 /* 8 bit signed immediate which may promote to 16bit signed immediate. */
176 #define SIMM8 (SD8N_SHIFT8+1)
177 {8, 0, MN10300_OPERAND_SIGNED
| MN10300_OPERAND_PROMOTE
},
179 /* 16 bit signed immediate which may promote to 32bit immediate. */
180 #define SIMM16 (SIMM8+1)
181 {16, 0, MN10300_OPERAND_SIGNED
| MN10300_OPERAND_PROMOTE
},
183 /* Either an open paren or close paren. */
184 #define PAREN (SIMM16+1)
185 {0, 0, MN10300_OPERAND_PAREN
},
187 /* dn register that appears in the first and second register positions. */
188 #define DN01 (PAREN+1)
189 {2, 0, MN10300_OPERAND_DREG
| MN10300_OPERAND_REPEATED
},
191 /* an register that appears in the first and second register positions. */
192 #define AN01 (DN01+1)
193 {2, 0, MN10300_OPERAND_AREG
| MN10300_OPERAND_REPEATED
},
195 /* 16bit pc-relative displacement which may promote to 32bit pc-relative
197 #define D16_SHIFT (AN01+1)
198 {16, 8, MN10300_OPERAND_PCREL
| MN10300_OPERAND_RELAX
| MN10300_OPERAND_SIGNED
},
200 /* 8 bit immediate found in the extension word. */
201 #define IMM8E (D16_SHIFT+1)
202 {8, 0, MN10300_OPERAND_EXTENDED
},
204 /* Register list found in the extension word shifted 8 bits left. */
205 #define REGSE_SHIFT8 (IMM8E+1)
206 {8, 8, MN10300_OPERAND_EXTENDED
| MN10300_OPERAND_REG_LIST
},
208 /* Register list shifted 8 bits left. */
209 #define REGS_SHIFT8 (REGSE_SHIFT8 + 1)
210 {8, 8, MN10300_OPERAND_REG_LIST
},
213 #define REGS (REGS_SHIFT8+1)
214 {8, 0, MN10300_OPERAND_REG_LIST
},
216 /* UStack pointer. */
218 {0, 0, MN10300_OPERAND_USP
},
220 /* SStack pointer. */
222 {0, 0, MN10300_OPERAND_SSP
},
224 /* MStack pointer. */
226 {0, 0, MN10300_OPERAND_MSP
},
230 {0, 0, MN10300_OPERAND_PC
},
232 /* 4 bit immediate for syscall. */
236 /* Processor status word. */
237 #define EPSW (IMM4+1)
238 {0, 0, MN10300_OPERAND_EPSW
},
240 /* rn register in the first register operand position. */
242 {4, 0, MN10300_OPERAND_RREG
},
244 /* rn register in the fourth register operand position. */
246 {4, 4, MN10300_OPERAND_RREG
},
248 /* rm register in the first register operand position. */
250 {4, 0, MN10300_OPERAND_RREG
},
252 /* rm register in the second register operand position. */
254 {4, 2, MN10300_OPERAND_RREG
},
256 /* rm register in the third register operand position. */
258 {4, 4, MN10300_OPERAND_RREG
},
261 {4, 0, MN10300_OPERAND_RREG
| MN10300_OPERAND_REPEATED
},
263 #define XRN0 (RN02+1)
264 {4, 0, MN10300_OPERAND_XRREG
},
266 #define XRM2 (XRN0+1)
267 {4, 4, MN10300_OPERAND_XRREG
},
269 /* + for autoincrement */
270 #define PLUS (XRM2+1)
271 {0, 0, MN10300_OPERAND_PLUS
},
273 #define XRN02 (PLUS+1)
274 {4, 0, MN10300_OPERAND_XRREG
| MN10300_OPERAND_REPEATED
},
277 #define RD0 (XRN02+1)
278 {4, -8, MN10300_OPERAND_RREG
},
281 {4, -4, MN10300_OPERAND_RREG
},
283 /* 8 unsigned displacement in a memory operation which
284 may promote to a 32bit displacement. */
285 #define IMM8_MEM (RD2+1)
286 {8, 0, MN10300_OPERAND_PROMOTE
| MN10300_OPERAND_MEMADDR
},
288 /* Index register. */
289 #define RI (IMM8_MEM+1)
290 {4, 4, MN10300_OPERAND_RREG
},
292 /* 24 bit signed displacement, may promote to 32bit displacement. */
294 {8, 0, MN10300_OPERAND_24BIT
| MN10300_OPERAND_SIGNED
| MN10300_OPERAND_PROMOTE
},
296 /* 24 bit unsigned immediate which may promote to a 32bit
297 unsigned immediate. */
298 #define IMM24 (SD24+1)
299 {8, 0, MN10300_OPERAND_24BIT
| MN10300_OPERAND_PROMOTE
},
301 /* 24 bit signed immediate which may promote to a 32bit
303 #define SIMM24 (IMM24+1)
304 {8, 0, MN10300_OPERAND_24BIT
| MN10300_OPERAND_PROMOTE
| MN10300_OPERAND_SIGNED
},
306 /* 24bit unsigned displacement in a memory operation which
307 may promote to a 32bit displacement. */
308 #define IMM24_MEM (SIMM24+1)
309 {8, 0, MN10300_OPERAND_24BIT
| MN10300_OPERAND_PROMOTE
| MN10300_OPERAND_MEMADDR
},
310 /* 32bit immediate, high 8 bits in the main instruction
311 word, 24 in the extension word.
313 The "bits" field indicates how many bits are in the
314 main instruction word for MN10300_OPERAND_SPLIT! */
315 #define IMM32_HIGH8 (IMM24_MEM+1)
316 {8, 0, MN10300_OPERAND_SPLIT
},
318 /* Similarly, but a memory address. */
319 #define IMM32_HIGH8_MEM (IMM32_HIGH8+1)
320 {8, 0, MN10300_OPERAND_SPLIT
| MN10300_OPERAND_MEMADDR
},
322 /* rm register in the seventh register operand position. */
323 #define RM6 (IMM32_HIGH8_MEM+1)
324 {4, 12, MN10300_OPERAND_RREG
},
326 /* rm register in the fifth register operand position. */
328 {4, 8, MN10300_OPERAND_RREG
},
330 /* 4 bit immediate for dsp instructions. */
331 #define IMM4_2 (RN4+1)
334 /* 4 bit immediate for dsp instructions. */
335 #define SIMM4_2 (IMM4_2+1)
336 {4, 4, MN10300_OPERAND_SIGNED
},
338 /* 4 bit immediate for dsp instructions. */
339 #define SIMM4_6 (SIMM4_2+1)
340 {4, 12, MN10300_OPERAND_SIGNED
},
342 #define FPCR (SIMM4_6+1)
343 {0, 0, MN10300_OPERAND_FPCR
},
345 /* We call f[sd]m registers those whose most significant bit is stored
346 * within the opcode half-word, i.e., in a bit on the left of the 4
347 * least significant bits, and f[sd]n registers those whose most
348 * significant bit is stored at the end of the full word, after the 4
349 * least significant bits. They're not numbered after their position
350 * in the mnemonic asm instruction, but after their position in the
351 * opcode word, i.e., depending on the amount of shift they need.
353 * The additional bit is shifted as follows: for `n' registers, it
354 * will be shifted by (|shift|/4); for `m' registers, it will be
355 * shifted by (8+(8&shift)+(shift&4)/4); for accumulator, whose
356 * specifications are only 3-bits long, the two least-significant bits
357 * are shifted by 16, and the most-significant bit is shifted by -2
358 * (i.e., it's stored in the least significant bit of the full
361 /* fsm register in the first register operand position. */
362 #define FSM0 (FPCR+1)
363 {5, 0, MN10300_OPERAND_FSREG
},
365 /* fsm register in the second register operand position. */
366 #define FSM1 (FSM0+1)
367 {5, 4, MN10300_OPERAND_FSREG
},
369 /* fsm register in the third register operand position. */
370 #define FSM2 (FSM1+1)
371 {5, 8, MN10300_OPERAND_FSREG
},
373 /* fsm register in the fourth register operand position. */
374 #define FSM3 (FSM2+1)
375 {5, 12, MN10300_OPERAND_FSREG
},
377 /* fsn register in the first register operand position. */
378 #define FSN1 (FSM3+1)
379 {5, -4, MN10300_OPERAND_FSREG
},
381 /* fsn register in the second register operand position. */
382 #define FSN2 (FSN1+1)
383 {5, -8, MN10300_OPERAND_FSREG
},
385 /* fsm register in the third register operand position. */
386 #define FSN3 (FSN2+1)
387 {5, -12, MN10300_OPERAND_FSREG
},
389 /* fsm accumulator, in the fourth register operand position. */
390 #define FSACC (FSN3+1)
391 {3, -16, MN10300_OPERAND_FSREG
},
393 /* fdm register in the first register operand position. */
394 #define FDM0 (FSACC+1)
395 {5, 0, MN10300_OPERAND_FDREG
},
397 /* fdm register in the second register operand position. */
398 #define FDM1 (FDM0+1)
399 {5, 4, MN10300_OPERAND_FDREG
},
401 /* fdm register in the third register operand position. */
402 #define FDM2 (FDM1+1)
403 {5, 8, MN10300_OPERAND_FDREG
},
405 /* fdm register in the fourth register operand position. */
406 #define FDM3 (FDM2+1)
407 {5, 12, MN10300_OPERAND_FDREG
},
409 /* fdn register in the first register operand position. */
410 #define FDN1 (FDM3+1)
411 {5, -4, MN10300_OPERAND_FDREG
},
413 /* fdn register in the second register operand position. */
414 #define FDN2 (FDN1+1)
415 {5, -8, MN10300_OPERAND_FDREG
},
417 /* fdn register in the third register operand position. */
418 #define FDN3 (FDN2+1)
419 {5, -12, MN10300_OPERAND_FDREG
},
423 #define MEM(ADDR) PAREN, ADDR, PAREN
424 #define MEMINC(ADDR) PAREN, ADDR, PLUS, PAREN
425 #define MEMINC2(ADDR,INC) PAREN, ADDR, PLUS, INC, PAREN
426 #define MEM2(ADDR1,ADDR2) PAREN, ADDR1, ADDR2, PAREN
430 The format of the opcode table is:
432 NAME OPCODE MASK MATCH_MASK, FORMAT, PROCESSOR { OPERANDS }
434 NAME is the name of the instruction.
435 OPCODE is the instruction opcode.
436 MASK is the opcode mask; this is used to tell the disassembler
437 which bits in the actual opcode must match OPCODE.
438 OPERANDS is the list of operands.
440 The disassembler reads the table in order and prints the first
441 instruction which matches, so this table is sorted to put more
442 specific instructions before more general instructions. It is also
443 sorted by major opcode. */
445 const struct mn10300_opcode mn10300_opcodes
[] = {
446 { "mov", 0x8000, 0xf000, 0, FMT_S1
, 0, {SIMM8
, DN01
}},
447 { "mov", 0x80, 0xf0, 0x3, FMT_S0
, 0, {DM1
, DN0
}},
448 { "mov", 0xf1e0, 0xfff0, 0, FMT_D0
, 0, {DM1
, AN0
}},
449 { "mov", 0xf1d0, 0xfff0, 0, FMT_D0
, 0, {AM1
, DN0
}},
450 { "mov", 0x9000, 0xf000, 0, FMT_S1
, 0, {IMM8
, AN01
}},
451 { "mov", 0x90, 0xf0, 0x3, FMT_S0
, 0, {AM1
, AN0
}},
452 { "mov", 0x3c, 0xfc, 0, FMT_S0
, 0, {SP
, AN0
}},
453 { "mov", 0xf2f0, 0xfff3, 0, FMT_D0
, 0, {AM1
, SP
}},
454 { "mov", 0xf2e4, 0xfffc, 0, FMT_D0
, 0, {PSW
, DN0
}},
455 { "mov", 0xf2f3, 0xfff3, 0, FMT_D0
, 0, {DM1
, PSW
}},
456 { "mov", 0xf2e0, 0xfffc, 0, FMT_D0
, 0, {MDR
, DN0
}},
457 { "mov", 0xf2f2, 0xfff3, 0, FMT_D0
, 0, {DM1
, MDR
}},
458 { "mov", 0x70, 0xf0, 0, FMT_S0
, 0, {MEM(AM0
), DN1
}},
459 { "mov", 0x5800, 0xfcff, 0, FMT_S1
, 0, {MEM(SP
), DN0
}},
460 { "mov", 0x300000, 0xfc0000, 0, FMT_S2
, 0, {MEM(IMM16_MEM
), DN0
}},
461 { "mov", 0xf000, 0xfff0, 0, FMT_D0
, 0, {MEM(AM0
), AN1
}},
462 { "mov", 0x5c00, 0xfcff, 0, FMT_S1
, 0, {MEM(SP
), AN0
}},
463 { "mov", 0xfaa00000, 0xfffc0000, 0, FMT_D2
, 0, {MEM(IMM16_MEM
), AN0
}},
464 { "mov", 0x60, 0xf0, 0, FMT_S0
, 0, {DM1
, MEM(AN0
)}},
465 { "mov", 0x4200, 0xf3ff, 0, FMT_S1
, 0, {DM1
, MEM(SP
)}},
466 { "mov", 0x010000, 0xf30000, 0, FMT_S2
, 0, {DM1
, MEM(IMM16_MEM
)}},
467 { "mov", 0xf010, 0xfff0, 0, FMT_D0
, 0, {AM1
, MEM(AN0
)}},
468 { "mov", 0x4300, 0xf3ff, 0, FMT_S1
, 0, {AM1
, MEM(SP
)}},
469 { "mov", 0xfa800000, 0xfff30000, 0, FMT_D2
, 0, {AM1
, MEM(IMM16_MEM
)}},
470 { "mov", 0x5c00, 0xfc00, 0, FMT_S1
, 0, {MEM2(IMM8
, SP
), AN0
}},
471 { "mov", 0xf80000, 0xfff000, 0, FMT_D1
, 0, {MEM2(SD8
, AM0
), DN1
}},
472 { "mov", 0xfa000000, 0xfff00000, 0, FMT_D2
, 0, {MEM2(SD16
, AM0
), DN1
}},
473 { "mov", 0x5800, 0xfc00, 0, FMT_S1
, 0, {MEM2(IMM8
, SP
), DN0
}},
474 { "mov", 0xfab40000, 0xfffc0000, 0, FMT_D2
, 0, {MEM2(IMM16
, SP
), DN0
}},
475 { "mov", 0xf300, 0xffc0, 0, FMT_D0
, 0, {MEM2(DI
, AM0
), DN2
}},
476 { "mov", 0xf82000, 0xfff000, 0, FMT_D1
, 0, {MEM2(SD8
,AM0
), AN1
}},
477 { "mov", 0xfa200000, 0xfff00000, 0, FMT_D2
, 0, {MEM2(SD16
, AM0
), AN1
}},
478 { "mov", 0xfab00000, 0xfffc0000, 0, FMT_D2
, 0, {MEM2(IMM16
, SP
), AN0
}},
479 { "mov", 0xf380, 0xffc0, 0, FMT_D0
, 0, {MEM2(DI
, AM0
), AN2
}},
480 { "mov", 0x4300, 0xf300, 0, FMT_S1
, 0, {AM1
, MEM2(IMM8
, SP
)}},
481 { "mov", 0xf81000, 0xfff000, 0, FMT_D1
, 0, {DM1
, MEM2(SD8
, AN0
)}},
482 { "mov", 0xfa100000, 0xfff00000, 0, FMT_D2
, 0, {DM1
, MEM2(SD16
, AN0
)}},
483 { "mov", 0x4200, 0xf300, 0, FMT_S1
, 0, {DM1
, MEM2(IMM8
, SP
)}},
484 { "mov", 0xfa910000, 0xfff30000, 0, FMT_D2
, 0, {DM1
, MEM2(IMM16
, SP
)}},
485 { "mov", 0xf340, 0xffc0, 0, FMT_D0
, 0, {DM2
, MEM2(DI
, AN0
)}},
486 { "mov", 0xf83000, 0xfff000, 0, FMT_D1
, 0, {AM1
, MEM2(SD8
, AN0
)}},
487 { "mov", 0xfa300000, 0xfff00000, 0, FMT_D2
, 0, {AM1
, MEM2(SD16
, AN0
)}},
488 { "mov", 0xfa900000, 0xfff30000, 0, FMT_D2
, 0, {AM1
, MEM2(IMM16
, SP
)}},
489 { "mov", 0xf3c0, 0xffc0, 0, FMT_D0
, 0, {AM2
, MEM2(DI
, AN0
)}},
491 { "mov", 0xf020, 0xfffc, 0, FMT_D0
, AM33
, {USP
, AN0
}},
492 { "mov", 0xf024, 0xfffc, 0, FMT_D0
, AM33
, {SSP
, AN0
}},
493 { "mov", 0xf028, 0xfffc, 0, FMT_D0
, AM33
, {MSP
, AN0
}},
494 { "mov", 0xf02c, 0xfffc, 0, FMT_D0
, AM33
, {PC
, AN0
}},
495 { "mov", 0xf030, 0xfff3, 0, FMT_D0
, AM33
, {AN1
, USP
}},
496 { "mov", 0xf031, 0xfff3, 0, FMT_D0
, AM33
, {AN1
, SSP
}},
497 { "mov", 0xf032, 0xfff3, 0, FMT_D0
, AM33
, {AN1
, MSP
}},
498 { "mov", 0xf2ec, 0xfffc, 0, FMT_D0
, AM33
, {EPSW
, DN0
}},
499 { "mov", 0xf2f1, 0xfff3, 0, FMT_D0
, AM33
, {DM1
, EPSW
}},
500 { "mov", 0xf500, 0xffc0, 0, FMT_D0
, AM33
, {AM2
, RN0
}},
501 { "mov", 0xf540, 0xffc0, 0, FMT_D0
, AM33
, {DM2
, RN0
}},
502 { "mov", 0xf580, 0xffc0, 0, FMT_D0
, AM33
, {RM1
, AN0
}},
503 { "mov", 0xf5c0, 0xffc0, 0, FMT_D0
, AM33
, {RM1
, DN0
}},
504 { "mov", 0xf90800, 0xffff00, 0, FMT_D6
, AM33
, {RM2
, RN0
}},
505 { "mov", 0xf9e800, 0xffff00, 0, FMT_D6
, AM33
, {XRM2
, RN0
}},
506 { "mov", 0xf9f800, 0xffff00, 0, FMT_D6
, AM33
, {RM2
, XRN0
}},
507 { "mov", 0xf90a00, 0xffff00, 0, FMT_D6
, AM33
, {MEM(RM0
), RN2
}},
508 { "mov", 0xf98a00, 0xffff0f, 0, FMT_D6
, AM33
, {MEM(SP
), RN2
}},
509 { "mov", 0xf96a00, 0xffff00, 0x12, FMT_D6
, AM33
, {MEMINC(RM0
), RN2
}},
510 { "mov", 0xfb0e0000, 0xffff0f00, 0, FMT_D7
, AM33
, {MEM(IMM8_MEM
), RN2
}},
511 { "mov", 0xfd0e0000, 0xffff0f00, 0, FMT_D8
, AM33
, {MEM(IMM24_MEM
), RN2
}},
512 { "mov", 0xf91a00, 0xffff00, 0, FMT_D6
, AM33
, {RM2
, MEM(RN0
)}},
513 { "mov", 0xf99a00, 0xffff0f, 0, FMT_D6
, AM33
, {RM2
, MEM(SP
)}},
514 { "mov", 0xf97a00, 0xffff00, 0, FMT_D6
, AM33
, {RM2
, MEMINC(RN0
)}},
515 { "mov", 0xfb1e0000, 0xffff0f00, 0, FMT_D7
, AM33
, {RM2
, MEM(IMM8_MEM
)}},
516 { "mov", 0xfd1e0000, 0xffff0f00, 0, FMT_D8
, AM33
, {RM2
, MEM(IMM24_MEM
)}},
517 { "mov", 0xfb0a0000, 0xffff0000, 0, FMT_D7
, AM33
, {MEM2(SD8
, RM0
), RN2
}},
518 { "mov", 0xfd0a0000, 0xffff0000, 0, FMT_D8
, AM33
, {MEM2(SD24
, RM0
), RN2
}},
519 { "mov", 0xfb8e0000, 0xffff000f, 0, FMT_D7
, AM33
, {MEM2(RI
, RM0
), RD2
}},
520 { "mov", 0xfb1a0000, 0xffff0000, 0, FMT_D7
, AM33
, {RM2
, MEM2(SD8
, RN0
)}},
521 { "mov", 0xfd1a0000, 0xffff0000, 0, FMT_D8
, AM33
, {RM2
, MEM2(SD24
, RN0
)}},
522 { "mov", 0xfb8a0000, 0xffff0f00, 0, FMT_D7
, AM33
, {MEM2(IMM8
, SP
), RN2
}},
523 { "mov", 0xfd8a0000, 0xffff0f00, 0, FMT_D8
, AM33
, {MEM2(IMM24
, SP
), RN2
}},
524 { "mov", 0xfb9a0000, 0xffff0f00, 0, FMT_D7
, AM33
, {RM2
, MEM2(IMM8
, SP
)}},
525 { "mov", 0xfd9a0000, 0xffff0f00, 0, FMT_D8
, AM33
, {RM2
, MEM2(IMM24
, SP
)}},
526 { "mov", 0xfb9e0000, 0xffff000f, 0, FMT_D7
, AM33
, {RD2
, MEM2(RI
, RN0
)}},
527 { "mov", 0xfb6a0000, 0xffff0000, 0x22, FMT_D7
, AM33
, {MEMINC2 (RM0
, SIMM8
), RN2
}},
528 { "mov", 0xfb7a0000, 0xffff0000, 0, FMT_D7
, AM33
, {RM2
, MEMINC2 (RN0
, SIMM8
)}},
529 { "mov", 0xfd6a0000, 0xffff0000, 0x22, FMT_D8
, AM33
, {MEMINC2 (RM0
, IMM24
), RN2
}},
530 { "mov", 0xfd7a0000, 0xffff0000, 0, FMT_D8
, AM33
, {RM2
, MEMINC2 (RN0
, IMM24
)}},
531 { "mov", 0xfe6a0000, 0xffff0000, 0x22, FMT_D9
, AM33
, {MEMINC2 (RM0
, IMM32_HIGH8
), RN2
}},
532 { "mov", 0xfe7a0000, 0xffff0000, 0, FMT_D9
, AM33
, {RN2
, MEMINC2 (RM0
, IMM32_HIGH8
)}},
533 /* These must come after most of the other move instructions to avoid matching
534 a symbolic name with IMMxx operands. Ugh. */
535 { "mov", 0x2c0000, 0xfc0000, 0, FMT_S2
, 0, {SIMM16
, DN0
}},
536 { "mov", 0xfccc0000, 0xfffc0000, 0, FMT_D4
, 0, {IMM32
, DN0
}},
537 { "mov", 0x240000, 0xfc0000, 0, FMT_S2
, 0, {IMM16
, AN0
}},
538 { "mov", 0xfcdc0000, 0xfffc0000, 0, FMT_D4
, 0, {IMM32
, AN0
}},
539 { "mov", 0xfca40000, 0xfffc0000, 0, FMT_D4
, 0, {MEM(IMM32_MEM
), DN0
}},
540 { "mov", 0xfca00000, 0xfffc0000, 0, FMT_D4
, 0, {MEM(IMM32_MEM
), AN0
}},
541 { "mov", 0xfc810000, 0xfff30000, 0, FMT_D4
, 0, {DM1
, MEM(IMM32_MEM
)}},
542 { "mov", 0xfc800000, 0xfff30000, 0, FMT_D4
, 0, {AM1
, MEM(IMM32_MEM
)}},
543 { "mov", 0xfc000000, 0xfff00000, 0, FMT_D4
, 0, {MEM2(IMM32
,AM0
), DN1
}},
544 { "mov", 0xfcb40000, 0xfffc0000, 0, FMT_D4
, 0, {MEM2(IMM32
, SP
), DN0
}},
545 { "mov", 0xfc200000, 0xfff00000, 0, FMT_D4
, 0, {MEM2(IMM32
,AM0
), AN1
}},
546 { "mov", 0xfcb00000, 0xfffc0000, 0, FMT_D4
, 0, {MEM2(IMM32
, SP
), AN0
}},
547 { "mov", 0xfc100000, 0xfff00000, 0, FMT_D4
, 0, {DM1
, MEM2(IMM32
,AN0
)}},
548 { "mov", 0xfc910000, 0xfff30000, 0, FMT_D4
, 0, {DM1
, MEM2(IMM32
, SP
)}},
549 { "mov", 0xfc300000, 0xfff00000, 0, FMT_D4
, 0, {AM1
, MEM2(IMM32
,AN0
)}},
550 { "mov", 0xfc900000, 0xfff30000, 0, FMT_D4
, 0, {AM1
, MEM2(IMM32
, SP
)}},
551 /* These non-promoting variants need to come after all the other memory
553 { "mov", 0xf8f000, 0xfffc00, 0, FMT_D1
, AM30
, {MEM2(SD8N
, AM0
), SP
}},
554 { "mov", 0xf8f400, 0xfffc00, 0, FMT_D1
, AM30
, {SP
, MEM2(SD8N
, AN0
)}},
555 /* These are the same as the previous non-promoting versions. The am33
556 does not have restrictions on the offsets used to load/store the stack
558 { "mov", 0xf8f000, 0xfffc00, 0, FMT_D1
, AM33
, {MEM2(SD8
, AM0
), SP
}},
559 { "mov", 0xf8f400, 0xfffc00, 0, FMT_D1
, AM33
, {SP
, MEM2(SD8
, AN0
)}},
560 /* These must come last so that we favor shorter move instructions for
561 loading immediates into d0-d3/a0-a3. */
562 { "mov", 0xfb080000, 0xffff0000, 0, FMT_D7
, AM33
, {SIMM8
, RN02
}},
563 { "mov", 0xfd080000, 0xffff0000, 0, FMT_D8
, AM33
, {SIMM24
, RN02
}},
564 { "mov", 0xfe080000, 0xffff0000, 0, FMT_D9
, AM33
, {IMM32_HIGH8
, RN02
}},
565 { "mov", 0xfbf80000, 0xffff0000, 0, FMT_D7
, AM33
, {IMM8
, XRN02
}},
566 { "mov", 0xfdf80000, 0xffff0000, 0, FMT_D8
, AM33
, {IMM24
, XRN02
}},
567 { "mov", 0xfef80000, 0xffff0000, 0, FMT_D9
, AM33
, {IMM32_HIGH8
, XRN02
}},
568 { "mov", 0xfe0e0000, 0xffff0f00, 0, FMT_D9
, AM33
, {MEM(IMM32_HIGH8_MEM
), RN2
}},
569 { "mov", 0xfe1e0000, 0xffff0f00, 0, FMT_D9
, AM33
, {RM2
, MEM(IMM32_HIGH8_MEM
)}},
570 { "mov", 0xfe0a0000, 0xffff0000, 0, FMT_D9
, AM33
, {MEM2(IMM32_HIGH8
,RM0
), RN2
}},
571 { "mov", 0xfe1a0000, 0xffff0000, 0, FMT_D9
, AM33
, {RM2
, MEM2(IMM32_HIGH8
, RN0
)}},
572 { "mov", 0xfe8a0000, 0xffff0f00, 0, FMT_D9
, AM33
, {MEM2(IMM32_HIGH8
, SP
), RN2
}},
573 { "mov", 0xfe9a0000, 0xffff0f00, 0, FMT_D9
, AM33
, {RM2
, MEM2(IMM32_HIGH8
, SP
)}},
575 { "movu", 0xfb180000, 0xffff0000, 0, FMT_D7
, AM33
, {IMM8
, RN02
}},
576 { "movu", 0xfd180000, 0xffff0000, 0, FMT_D8
, AM33
, {IMM24
, RN02
}},
577 { "movu", 0xfe180000, 0xffff0000, 0, FMT_D9
, AM33
, {IMM32_HIGH8
, RN02
}},
579 { "mcst9", 0xf630, 0xfff0, 0, FMT_D0
, AM33
, {DN01
}},
580 { "mcst48", 0xf660, 0xfff0, 0, FMT_D0
, AM33
, {DN01
}},
581 { "swap", 0xf680, 0xfff0, 0, FMT_D0
, AM33
, {DM1
, DN0
}},
582 { "swap", 0xf9cb00, 0xffff00, 0, FMT_D6
, AM33
, {RM2
, RN0
}},
583 { "swaph", 0xf690, 0xfff0, 0, FMT_D0
, AM33
, {DM1
, DN0
}},
584 { "swaph", 0xf9db00, 0xffff00, 0, FMT_D6
, AM33
, {RM2
, RN0
}},
585 { "getchx", 0xf6c0, 0xfff0, 0, FMT_D0
, AM33
, {DN01
}},
586 { "getclx", 0xf6d0, 0xfff0, 0, FMT_D0
, AM33
, {DN01
}},
587 { "mac", 0xfb0f0000, 0xffff0000, 0xc, FMT_D7
, AM33
, {RM2
, RN0
, RD2
, RD0
}},
588 { "mac", 0xf90b00, 0xffff00, 0, FMT_D6
, AM33
, {RM2
, RN0
}},
589 { "mac", 0xfb0b0000, 0xffff0000, 0, FMT_D7
, AM33
, {SIMM8
, RN02
}},
590 { "mac", 0xfd0b0000, 0xffff0000, 0, FMT_D8
, AM33
, {SIMM24
, RN02
}},
591 { "mac", 0xfe0b0000, 0xffff0000, 0, FMT_D9
, AM33
, {IMM32_HIGH8
, RN02
}},
592 { "macu", 0xfb1f0000, 0xffff0000, 0xc, FMT_D7
, AM33
, {RM2
, RN0
, RD2
, RD0
}},
593 { "macu", 0xf91b00, 0xffff00, 0, FMT_D6
, AM33
, {RM2
, RN0
}},
594 { "macu", 0xfb1b0000, 0xffff0000, 0, FMT_D7
, AM33
, {IMM8
, RN02
}},
595 { "macu", 0xfd1b0000, 0xffff0000, 0, FMT_D8
, AM33
, {IMM24
, RN02
}},
596 { "macu", 0xfe1b0000, 0xffff0000, 0, FMT_D9
, AM33
, {IMM32_HIGH8
, RN02
}},
597 { "macb", 0xfb2f0000, 0xffff000f, 0, FMT_D7
, AM33
, {RM2
, RN0
, RD2
}},
598 { "macb", 0xf92b00, 0xffff00, 0, FMT_D6
, AM33
, {RM2
, RN0
}},
599 { "macb", 0xfb2b0000, 0xffff0000, 0, FMT_D7
, AM33
, {SIMM8
, RN02
}},
600 { "macb", 0xfd2b0000, 0xffff0000, 0, FMT_D8
, AM33
, {SIMM24
, RN02
}},
601 { "macb", 0xfe2b0000, 0xffff0000, 0, FMT_D9
, AM33
, {IMM32_HIGH8
, RN02
}},
602 { "macbu", 0xfb3f0000, 0xffff000f, 0, FMT_D7
, AM33
, {RM2
, RN0
, RD2
}},
603 { "macbu", 0xf93b00, 0xffff00, 0, FMT_D6
, AM33
, {RM2
, RN0
}},
604 { "macbu", 0xfb3b0000, 0xffff0000, 0, FMT_D7
, AM33
, {IMM8
, RN02
}},
605 { "macbu", 0xfd3b0000, 0xffff0000, 0, FMT_D8
, AM33
, {IMM24
, RN02
}},
606 { "macbu", 0xfe3b0000, 0xffff0000, 0, FMT_D9
, AM33
, {IMM32_HIGH8
, RN02
}},
607 { "mach", 0xfb4f0000, 0xffff0000, 0xc, FMT_D7
, AM33
, {RM2
, RN0
, RD2
, RD0
}},
608 { "mach", 0xf94b00, 0xffff00, 0, FMT_D6
, AM33
, {RM2
, RN0
}},
609 { "mach", 0xfb4b0000, 0xffff0000, 0, FMT_D7
, AM33
, {SIMM8
, RN02
}},
610 { "mach", 0xfd4b0000, 0xffff0000, 0, FMT_D8
, AM33
, {SIMM24
, RN02
}},
611 { "mach", 0xfe4b0000, 0xffff0000, 0, FMT_D9
, AM33
, {IMM32_HIGH8
, RN02
}},
612 { "machu", 0xfb5f0000, 0xffff0000, 0xc, FMT_D7
, AM33
, {RM2
, RN0
, RD2
, RD0
}},
613 { "machu", 0xf95b00, 0xffff00, 0, FMT_D6
, AM33
, {RM2
, RN0
}},
614 { "machu", 0xfb5b0000, 0xffff0000, 0, FMT_D7
, AM33
, {IMM8
, RN02
}},
615 { "machu", 0xfd5b0000, 0xffff0000, 0, FMT_D8
, AM33
, {IMM24
, RN02
}},
616 { "machu", 0xfe5b0000, 0xffff0000, 0, FMT_D9
, AM33
, {IMM32_HIGH8
, RN02
}},
617 { "dmach", 0xfb6f0000, 0xffff000f, 0, FMT_D7
, AM33
, {RM2
, RN0
, RD2
}},
618 { "dmach", 0xf96b00, 0xffff00, 0, FMT_D6
, AM33
, {RM2
, RN0
}},
619 { "dmach", 0xfe6b0000, 0xffff0000, 0, FMT_D9
, AM33
, {IMM32_HIGH8
, RN02
}},
620 { "dmachu", 0xfb7f0000, 0xffff000f, 0, FMT_D7
, AM33
, {RM2
, RN0
, RD2
}},
621 { "dmachu", 0xf97b00, 0xffff00, 0, FMT_D6
, AM33
, {RM2
, RN0
}},
622 { "dmachu", 0xfe7b0000, 0xffff0000, 0, FMT_D9
, AM33
, {IMM32_HIGH8
, RN02
}},
623 { "dmulh", 0xfb8f0000, 0xffff0000, 0xc, FMT_D7
, AM33
, {RM2
, RN0
, RD2
, RD0
}},
624 { "dmulh", 0xf98b00, 0xffff00, 0, FMT_D6
, AM33
, {RM2
, RN0
}},
625 { "dmulh", 0xfe8b0000, 0xffff0000, 0, FMT_D9
, AM33
, {IMM32_HIGH8
, RN02
}},
626 { "dmulhu", 0xfb9f0000, 0xffff0000, 0xc, FMT_D7
, AM33
, {RM2
, RN0
, RD2
, RD0
}},
627 { "dmulhu", 0xf99b00, 0xffff00, 0, FMT_D6
, AM33
, {RM2
, RN0
}},
628 { "dmulhu", 0xfe9b0000, 0xffff0000, 0, FMT_D9
, AM33
, {IMM32_HIGH8
, RN02
}},
629 { "mcste", 0xf9bb00, 0xffff00, 0, FMT_D6
, AM33
, {RM2
, RN0
}},
630 { "mcste", 0xfbbb0000, 0xffff0000, 0, FMT_D7
, AM33
, {IMM8
, RN02
}},
631 { "swhw", 0xf9eb00, 0xffff00, 0, FMT_D6
, AM33
, {RM2
, RN0
}},
633 { "movbu", 0xf040, 0xfff0, 0, FMT_D0
, 0, {MEM(AM0
), DN1
}},
634 { "movbu", 0xf84000, 0xfff000, 0, FMT_D1
, 0, {MEM2(SD8
, AM0
), DN1
}},
635 { "movbu", 0xfa400000, 0xfff00000, 0, FMT_D2
, 0, {MEM2(SD16
, AM0
), DN1
}},
636 { "movbu", 0xf8b800, 0xfffcff, 0, FMT_D1
, 0, {MEM(SP
), DN0
}},
637 { "movbu", 0xf8b800, 0xfffc00, 0, FMT_D1
, 0, {MEM2(IMM8
, SP
), DN0
}},
638 { "movbu", 0xfab80000, 0xfffc0000, 0, FMT_D2
, 0, {MEM2(IMM16
, SP
), DN0
}},
639 { "movbu", 0xf400, 0xffc0, 0, FMT_D0
, 0, {MEM2(DI
, AM0
), DN2
}},
640 { "movbu", 0x340000, 0xfc0000, 0, FMT_S2
, 0, {MEM(IMM16_MEM
), DN0
}},
641 { "movbu", 0xf050, 0xfff0, 0, FMT_D0
, 0, {DM1
, MEM(AN0
)}},
642 { "movbu", 0xf85000, 0xfff000, 0, FMT_D1
, 0, {DM1
, MEM2(SD8
, AN0
)}},
643 { "movbu", 0xfa500000, 0xfff00000, 0, FMT_D2
, 0, {DM1
, MEM2(SD16
, AN0
)}},
644 { "movbu", 0xf89200, 0xfff3ff, 0, FMT_D1
, 0, {DM1
, MEM(SP
)}},
645 { "movbu", 0xf89200, 0xfff300, 0, FMT_D1
, 0, {DM1
, MEM2(IMM8
, SP
)}},
646 { "movbu", 0xfa920000, 0xfff30000, 0, FMT_D2
, 0, {DM1
, MEM2(IMM16
, SP
)}},
647 { "movbu", 0xf440, 0xffc0, 0, FMT_D0
, 0, {DM2
, MEM2(DI
, AN0
)}},
648 { "movbu", 0x020000, 0xf30000, 0, FMT_S2
, 0, {DM1
, MEM(IMM16_MEM
)}},
649 { "movbu", 0xf92a00, 0xffff00, 0, FMT_D6
, AM33
, {MEM(RM0
), RN2
}},
650 { "movbu", 0xf93a00, 0xffff00, 0, FMT_D6
, AM33
, {RM2
, MEM(RN0
)}},
651 { "movbu", 0xf9aa00, 0xffff0f, 0, FMT_D6
, AM33
, {MEM(SP
), RN2
}},
652 { "movbu", 0xf9ba00, 0xffff0f, 0, FMT_D6
, AM33
, {RM2
, MEM(SP
)}},
653 { "movbu", 0xfb2a0000, 0xffff0000, 0, FMT_D7
, AM33
, {MEM2(SD8
, RM0
), RN2
}},
654 { "movbu", 0xfd2a0000, 0xffff0000, 0, FMT_D8
, AM33
, {MEM2(SD24
, RM0
), RN2
}},
655 { "movbu", 0xfb3a0000, 0xffff0000, 0, FMT_D7
, AM33
, {RM2
, MEM2(SD8
, RN0
)}},
656 { "movbu", 0xfd3a0000, 0xffff0000, 0, FMT_D8
, AM33
, {RM2
, MEM2(SD24
, RN0
)}},
657 { "movbu", 0xfbaa0000, 0xffff0f00, 0, FMT_D7
, AM33
, {MEM2(IMM8
, SP
), RN2
}},
658 { "movbu", 0xfdaa0000, 0xffff0f00, 0, FMT_D8
, AM33
, {MEM2(IMM24
, SP
), RN2
}},
659 { "movbu", 0xfbba0000, 0xffff0f00, 0, FMT_D7
, AM33
, {RM2
, MEM2(IMM8
, SP
)}},
660 { "movbu", 0xfdba0000, 0xffff0f00, 0, FMT_D8
, AM33
, {RM2
, MEM2(IMM24
, SP
)}},
661 { "movbu", 0xfb2e0000, 0xffff0f00, 0, FMT_D7
, AM33
, {MEM(IMM8_MEM
), RN2
}},
662 { "movbu", 0xfd2e0000, 0xffff0f00, 0, FMT_D8
, AM33
, {MEM(IMM24_MEM
), RN2
}},
663 { "movbu", 0xfb3e0000, 0xffff0f00, 0, FMT_D7
, AM33
, {RM2
, MEM(IMM8_MEM
)}},
664 { "movbu", 0xfd3e0000, 0xffff0f00, 0, FMT_D8
, AM33
, {RM2
, MEM(IMM24_MEM
)}},
665 { "movbu", 0xfbae0000, 0xffff000f, 0, FMT_D7
, AM33
, {MEM2(RI
, RM0
), RD2
}},
666 { "movbu", 0xfbbe0000, 0xffff000f, 0, FMT_D7
, AM33
, {RD2
, MEM2(RI
, RN0
)}},
667 { "movbu", 0xfc400000, 0xfff00000, 0, FMT_D4
, 0, {MEM2(IMM32
,AM0
), DN1
}},
668 { "movbu", 0xfcb80000, 0xfffc0000, 0, FMT_D4
, 0, {MEM2(IMM32
, SP
), DN0
}},
669 { "movbu", 0xfca80000, 0xfffc0000, 0, FMT_D4
, 0, {MEM(IMM32_MEM
), DN0
}},
670 { "movbu", 0xfc500000, 0xfff00000, 0, FMT_D4
, 0, {DM1
, MEM2(IMM32
,AN0
)}},
671 { "movbu", 0xfc920000, 0xfff30000, 0, FMT_D4
, 0, {DM1
, MEM2(IMM32
, SP
)}},
672 { "movbu", 0xfc820000, 0xfff30000, 0, FMT_D4
, 0, {DM1
, MEM(IMM32_MEM
)}},
673 { "movbu", 0xfe2a0000, 0xffff0000, 0, FMT_D9
, AM33
, {MEM2(IMM32_HIGH8
,RM0
), RN2
}},
674 { "movbu", 0xfe3a0000, 0xffff0000, 0, FMT_D9
, AM33
, {RM2
, MEM2(IMM32_HIGH8
, RN0
)}},
675 { "movbu", 0xfeaa0000, 0xffff0f00, 0, FMT_D9
, AM33
, {MEM2(IMM32_HIGH8
,SP
), RN2
}},
676 { "movbu", 0xfeba0000, 0xffff0f00, 0, FMT_D9
, AM33
, {RM2
, MEM2(IMM32_HIGH8
, SP
)}},
677 { "movbu", 0xfe2e0000, 0xffff0f00, 0, FMT_D9
, AM33
, {MEM(IMM32_HIGH8_MEM
), RN2
}},
678 { "movbu", 0xfe3e0000, 0xffff0f00, 0, FMT_D9
, AM33
, {RM2
, MEM(IMM32_HIGH8_MEM
)}},
680 { "movhu", 0xf060, 0xfff0, 0, FMT_D0
, 0, {MEM(AM0
), DN1
}},
681 { "movhu", 0xf86000, 0xfff000, 0, FMT_D1
, 0, {MEM2(SD8
, AM0
), DN1
}},
682 { "movhu", 0xfa600000, 0xfff00000, 0, FMT_D2
, 0, {MEM2(SD16
, AM0
), DN1
}},
683 { "movhu", 0xf8bc00, 0xfffcff, 0, FMT_D1
, 0, {MEM(SP
), DN0
}},
684 { "movhu", 0xf8bc00, 0xfffc00, 0, FMT_D1
, 0, {MEM2(IMM8
, SP
), DN0
}},
685 { "movhu", 0xfabc0000, 0xfffc0000, 0, FMT_D2
, 0, {MEM2(IMM16
, SP
), DN0
}},
686 { "movhu", 0xf480, 0xffc0, 0, FMT_D0
, 0, {MEM2(DI
, AM0
), DN2
}},
687 { "movhu", 0x380000, 0xfc0000, 0, FMT_S2
, 0, {MEM(IMM16_MEM
), DN0
}},
688 { "movhu", 0xf070, 0xfff0, 0, FMT_D0
, 0, {DM1
, MEM(AN0
)}},
689 { "movhu", 0xf87000, 0xfff000, 0, FMT_D1
, 0, {DM1
, MEM2(SD8
, AN0
)}},
690 { "movhu", 0xfa700000, 0xfff00000, 0, FMT_D2
, 0, {DM1
, MEM2(SD16
, AN0
)}},
691 { "movhu", 0xf89300, 0xfff3ff, 0, FMT_D1
, 0, {DM1
, MEM(SP
)}},
692 { "movhu", 0xf89300, 0xfff300, 0, FMT_D1
, 0, {DM1
, MEM2(IMM8
, SP
)}},
693 { "movhu", 0xfa930000, 0xfff30000, 0, FMT_D2
, 0, {DM1
, MEM2(IMM16
, SP
)}},
694 { "movhu", 0xf4c0, 0xffc0, 0, FMT_D0
, 0, {DM2
, MEM2(DI
, AN0
)}},
695 { "movhu", 0x030000, 0xf30000, 0, FMT_S2
, 0, {DM1
, MEM(IMM16_MEM
)}},
696 { "movhu", 0xf94a00, 0xffff00, 0, FMT_D6
, AM33
, {MEM(RM0
), RN2
}},
697 { "movhu", 0xf95a00, 0xffff00, 0, FMT_D6
, AM33
, {RM2
, MEM(RN0
)}},
698 { "movhu", 0xf9ca00, 0xffff0f, 0, FMT_D6
, AM33
, {MEM(SP
), RN2
}},
699 { "movhu", 0xf9da00, 0xffff0f, 0, FMT_D6
, AM33
, {RM2
, MEM(SP
)}},
700 { "movhu", 0xf9ea00, 0xffff00, 0x12, FMT_D6
, AM33
, {MEMINC(RM0
), RN2
}},
701 { "movhu", 0xf9fa00, 0xffff00, 0, FMT_D6
, AM33
, {RM2
, MEMINC(RN0
)}},
702 { "movhu", 0xfb4a0000, 0xffff0000, 0, FMT_D7
, AM33
, {MEM2(SD8
, RM0
), RN2
}},
703 { "movhu", 0xfd4a0000, 0xffff0000, 0, FMT_D8
, AM33
, {MEM2(SD24
, RM0
), RN2
}},
704 { "movhu", 0xfb5a0000, 0xffff0000, 0, FMT_D7
, AM33
, {RM2
, MEM2(SD8
, RN0
)}},
705 { "movhu", 0xfd5a0000, 0xffff0000, 0, FMT_D8
, AM33
, {RM2
, MEM2(SD24
, RN0
)}},
706 { "movhu", 0xfbca0000, 0xffff0f00, 0, FMT_D7
, AM33
, {MEM2(IMM8
, SP
), RN2
}},
707 { "movhu", 0xfdca0000, 0xffff0f00, 0, FMT_D8
, AM33
, {MEM2(IMM24
, SP
), RN2
}},
708 { "movhu", 0xfbda0000, 0xffff0f00, 0, FMT_D7
, AM33
, {RM2
, MEM2(IMM8
, SP
)}},
709 { "movhu", 0xfdda0000, 0xffff0f00, 0, FMT_D8
, AM33
, {RM2
, MEM2(IMM24
, SP
)}},
710 { "movhu", 0xfb4e0000, 0xffff0f00, 0, FMT_D7
, AM33
, {MEM(IMM8_MEM
), RN2
}},
711 { "movhu", 0xfd4e0000, 0xffff0f00, 0, FMT_D8
, AM33
, {MEM(IMM24_MEM
), RN2
}},
712 { "movhu", 0xfbce0000, 0xffff000f, 0, FMT_D7
, AM33
, {MEM2(RI
, RM0
), RD2
}},
713 { "movhu", 0xfbde0000, 0xffff000f, 0, FMT_D7
, AM33
, {RD2
, MEM2(RI
, RN0
)}},
714 { "movhu", 0xfc600000, 0xfff00000, 0, FMT_D4
, 0, {MEM2(IMM32
,AM0
), DN1
}},
715 { "movhu", 0xfcbc0000, 0xfffc0000, 0, FMT_D4
, 0, {MEM2(IMM32
, SP
), DN0
}},
716 { "movhu", 0xfcac0000, 0xfffc0000, 0, FMT_D4
, 0, {MEM(IMM32_MEM
), DN0
}},
717 { "movhu", 0xfc700000, 0xfff00000, 0, FMT_D4
, 0, {DM1
, MEM2(IMM32
,AN0
)}},
718 { "movhu", 0xfc930000, 0xfff30000, 0, FMT_D4
, 0, {DM1
, MEM2(IMM32
, SP
)}},
719 { "movhu", 0xfc830000, 0xfff30000, 0, FMT_D4
, 0, {DM1
, MEM(IMM32_MEM
)}},
720 { "movhu", 0xfe4a0000, 0xffff0000, 0, FMT_D9
, AM33
, {MEM2(IMM32_HIGH8
,RM0
), RN2
}},
721 { "movhu", 0xfe5a0000, 0xffff0000, 0, FMT_D9
, AM33
, {RM2
, MEM2(IMM32_HIGH8
, RN0
)}},
722 { "movhu", 0xfeca0000, 0xffff0f00, 0, FMT_D9
, AM33
, {MEM2(IMM32_HIGH8
, SP
), RN2
}},
723 { "movhu", 0xfeda0000, 0xffff0f00, 0, FMT_D9
, AM33
, {RM2
, MEM2(IMM32_HIGH8
, SP
)}},
724 { "movhu", 0xfe4e0000, 0xffff0f00, 0, FMT_D9
, AM33
, {MEM(IMM32_HIGH8_MEM
), RN2
}},
725 { "movhu", 0xfb5e0000, 0xffff0f00, 0, FMT_D7
, AM33
, {RM2
, MEM(IMM8_MEM
)}},
726 { "movhu", 0xfd5e0000, 0xffff0f00, 0, FMT_D8
, AM33
, {RM2
, MEM(IMM24_MEM
)}},
727 { "movhu", 0xfe5e0000, 0xffff0f00, 0, FMT_D9
, AM33
, {RM2
, MEM(IMM32_HIGH8_MEM
)}},
728 { "movhu", 0xfbea0000, 0xffff0000, 0x22, FMT_D7
, AM33
, {MEMINC2 (RM0
, SIMM8
), RN2
}},
729 { "movhu", 0xfbfa0000, 0xffff0000, 0, FMT_D7
, AM33
, {RM2
, MEMINC2 (RN0
, SIMM8
)}},
730 { "movhu", 0xfdea0000, 0xffff0000, 0x22, FMT_D8
, AM33
, {MEMINC2 (RM0
, IMM24
), RN2
}},
731 { "movhu", 0xfdfa0000, 0xffff0000, 0, FMT_D8
, AM33
, {RM2
, MEMINC2 (RN0
, IMM24
)}},
732 { "movhu", 0xfeea0000, 0xffff0000, 0x22, FMT_D9
, AM33
, {MEMINC2 (RM0
, IMM32_HIGH8
), RN2
}},
733 { "movhu", 0xfefa0000, 0xffff0000, 0, FMT_D9
, AM33
, {RN2
, MEMINC2 (RM0
, IMM32_HIGH8
)}},
735 { "ext", 0xf2d0, 0xfffc, 0, FMT_D0
, 0, {DN0
}},
736 { "ext", 0xf91800, 0xffff00, 0, FMT_D6
, AM33
, {RN02
}},
738 { "extb", 0xf92800, 0xffff00, 0, FMT_D6
, AM33
, {RM2
, RN0
}},
739 { "extb", 0x10, 0xfc, 0, FMT_S0
, 0, {DN0
}},
740 { "extb", 0xf92800, 0xffff00, 0, FMT_D6
, AM33
, {RN02
}},
742 { "extbu", 0xf93800, 0xffff00, 0, FMT_D6
, AM33
, {RM2
, RN0
}},
743 { "extbu", 0x14, 0xfc, 0, FMT_S0
, 0, {DN0
}},
744 { "extbu", 0xf93800, 0xffff00, 0, FMT_D6
, AM33
, {RN02
}},
746 { "exth", 0xf94800, 0xffff00, 0, FMT_D6
, AM33
, {RM2
, RN0
}},
747 { "exth", 0x18, 0xfc, 0, FMT_S0
, 0, {DN0
}},
748 { "exth", 0xf94800, 0xffff00, 0, FMT_D6
, AM33
, {RN02
}},
750 { "exthu", 0xf95800, 0xffff00, 0, FMT_D6
, AM33
, {RM2
, RN0
}},
751 { "exthu", 0x1c, 0xfc, 0, FMT_S0
, 0, {DN0
}},
752 { "exthu", 0xf95800, 0xffff00, 0, FMT_D6
, AM33
, {RN02
}},
754 { "movm", 0xce00, 0xff00, 0, FMT_S1
, 0, {MEM(SP
), REGS
}},
755 { "movm", 0xcf00, 0xff00, 0, FMT_S1
, 0, {REGS
, MEM(SP
)}},
756 { "movm", 0xf8ce00, 0xffff00, 0, FMT_D1
, AM33
, {MEM(USP
), REGS
}},
757 { "movm", 0xf8cf00, 0xffff00, 0, FMT_D1
, AM33
, {REGS
, MEM(USP
)}},
759 { "clr", 0x00, 0xf3, 0, FMT_S0
, 0, {DN1
}},
760 { "clr", 0xf96800, 0xffff00, 0, FMT_D6
, AM33
, {RN02
}},
762 { "add", 0xfb7c0000, 0xffff000f, 0, FMT_D7
, AM33
, {RM2
, RN0
, RD2
}},
763 { "add", 0xe0, 0xf0, 0, FMT_S0
, 0, {DM1
, DN0
}},
764 { "add", 0xf160, 0xfff0, 0, FMT_D0
, 0, {DM1
, AN0
}},
765 { "add", 0xf150, 0xfff0, 0, FMT_D0
, 0, {AM1
, DN0
}},
766 { "add", 0xf170, 0xfff0, 0, FMT_D0
, 0, {AM1
, AN0
}},
767 { "add", 0x2800, 0xfc00, 0, FMT_S1
, 0, {SIMM8
, DN0
}},
768 { "add", 0xfac00000, 0xfffc0000, 0, FMT_D2
, 0, {SIMM16
, DN0
}},
769 { "add", 0x2000, 0xfc00, 0, FMT_S1
, 0, {SIMM8
, AN0
}},
770 { "add", 0xfad00000, 0xfffc0000, 0, FMT_D2
, 0, {SIMM16
, AN0
}},
771 { "add", 0xf8fe00, 0xffff00, 0, FMT_D1
, 0, {SIMM8
, SP
}},
772 { "add", 0xfafe0000, 0xffff0000, 0, FMT_D2
, 0, {SIMM16
, SP
}},
773 { "add", 0xf97800, 0xffff00, 0, FMT_D6
, AM33
, {RM2
, RN0
}},
774 { "add", 0xfcc00000, 0xfffc0000, 0, FMT_D4
, 0, {IMM32
, DN0
}},
775 { "add", 0xfcd00000, 0xfffc0000, 0, FMT_D4
, 0, {IMM32
, AN0
}},
776 { "add", 0xfcfe0000, 0xffff0000, 0, FMT_D4
, 0, {IMM32
, SP
}},
777 { "add", 0xfb780000, 0xffff0000, 0, FMT_D7
, AM33
, {SIMM8
, RN02
}},
778 { "add", 0xfd780000, 0xffff0000, 0, FMT_D8
, AM33
, {SIMM24
, RN02
}},
779 { "add", 0xfe780000, 0xffff0000, 0, FMT_D9
, AM33
, {IMM32_HIGH8
, RN02
}},
781 { "addc", 0xfb8c0000, 0xffff000f, 0, FMT_D7
, AM33
, {RM2
, RN0
, RD2
}},
782 { "addc", 0xf140, 0xfff0, 0, FMT_D0
, 0, {DM1
, DN0
}},
783 { "addc", 0xf98800, 0xffff00, 0, FMT_D6
, AM33
, {RM2
, RN0
}},
784 { "addc", 0xfb880000, 0xffff0000, 0, FMT_D7
, AM33
, {SIMM8
, RN02
}},
785 { "addc", 0xfd880000, 0xffff0000, 0, FMT_D8
, AM33
, {SIMM24
, RN02
}},
786 { "addc", 0xfe880000, 0xffff0000, 0, FMT_D9
, AM33
, {IMM32_HIGH8
, RN02
}},
788 { "sub", 0xfb9c0000, 0xffff000f, 0, FMT_D7
, AM33
, {RM2
, RN0
, RD2
}},
789 { "sub", 0xf100, 0xfff0, 0, FMT_D0
, 0, {DM1
, DN0
}},
790 { "sub", 0xf120, 0xfff0, 0, FMT_D0
, 0, {DM1
, AN0
}},
791 { "sub", 0xf110, 0xfff0, 0, FMT_D0
, 0, {AM1
, DN0
}},
792 { "sub", 0xf130, 0xfff0, 0, FMT_D0
, 0, {AM1
, AN0
}},
793 { "sub", 0xf99800, 0xffff00, 0, FMT_D6
, AM33
, {RM2
, RN0
}},
794 { "sub", 0xfcc40000, 0xfffc0000, 0, FMT_D4
, 0, {IMM32
, DN0
}},
795 { "sub", 0xfcd40000, 0xfffc0000, 0, FMT_D4
, 0, {IMM32
, AN0
}},
796 { "sub", 0xfb980000, 0xffff0000, 0, FMT_D7
, AM33
, {SIMM8
, RN02
}},
797 { "sub", 0xfd980000, 0xffff0000, 0, FMT_D8
, AM33
, {SIMM24
, RN02
}},
798 { "sub", 0xfe980000, 0xffff0000, 0, FMT_D9
, AM33
, {IMM32_HIGH8
, RN02
}},
800 { "subc", 0xfbac0000, 0xffff000f, 0, FMT_D7
, AM33
, {RM2
, RN0
, RD2
}},
801 { "subc", 0xf180, 0xfff0, 0, FMT_D0
, 0, {DM1
, DN0
}},
802 { "subc", 0xf9a800, 0xffff00, 0, FMT_D6
, AM33
, {RM2
, RN0
}},
803 { "subc", 0xfba80000, 0xffff0000, 0, FMT_D7
, AM33
, {SIMM8
, RN02
}},
804 { "subc", 0xfda80000, 0xffff0000, 0, FMT_D8
, AM33
, {SIMM24
, RN02
}},
805 { "subc", 0xfea80000, 0xffff0000, 0, FMT_D9
, AM33
, {IMM32_HIGH8
, RN02
}},
807 { "mul", 0xfbad0000, 0xffff0000, 0xc, FMT_D7
, AM33
, {RM2
, RN0
, RD2
, RD0
}},
808 { "mul", 0xf240, 0xfff0, 0, FMT_D0
, 0, {DM1
, DN0
}},
809 { "mul", 0xf9a900, 0xffff00, 0, FMT_D6
, AM33
, {RM2
, RN0
}},
810 { "mul", 0xfba90000, 0xffff0000, 0, FMT_D7
, AM33
, {SIMM8
, RN02
}},
811 { "mul", 0xfda90000, 0xffff0000, 0, FMT_D8
, AM33
, {SIMM24
, RN02
}},
812 { "mul", 0xfea90000, 0xffff0000, 0, FMT_D9
, AM33
, {IMM32_HIGH8
, RN02
}},
814 { "mulu", 0xfbbd0000, 0xffff0000, 0xc, FMT_D7
, AM33
, {RM2
, RN0
, RD2
, RD0
}},
815 { "mulu", 0xf250, 0xfff0, 0, FMT_D0
, 0, {DM1
, DN0
}},
816 { "mulu", 0xf9b900, 0xffff00, 0, FMT_D6
, AM33
, {RM2
, RN0
}},
817 { "mulu", 0xfbb90000, 0xffff0000, 0, FMT_D7
, AM33
, {IMM8
, RN02
}},
818 { "mulu", 0xfdb90000, 0xffff0000, 0, FMT_D8
, AM33
, {IMM24
, RN02
}},
819 { "mulu", 0xfeb90000, 0xffff0000, 0, FMT_D9
, AM33
, {IMM32_HIGH8
, RN02
}},
821 { "div", 0xf260, 0xfff0, 0, FMT_D0
, 0, {DM1
, DN0
}},
822 { "div", 0xf9c900, 0xffff00, 0, FMT_D6
, AM33
, {RM2
, RN0
}},
824 { "divu", 0xf270, 0xfff0, 0, FMT_D0
, 0, {DM1
, DN0
}},
825 { "divu", 0xf9d900, 0xffff00, 0, FMT_D6
, AM33
, {RM2
, RN0
}},
827 { "inc", 0x40, 0xf3, 0, FMT_S0
, 0, {DN1
}},
828 { "inc", 0x41, 0xf3, 0, FMT_S0
, 0, {AN1
}},
829 { "inc", 0xf9b800, 0xffff00, 0, FMT_D6
, AM33
, {RN02
}},
831 { "inc4", 0x50, 0xfc, 0, FMT_S0
, 0, {AN0
}},
832 { "inc4", 0xf9c800, 0xffff00, 0, FMT_D6
, AM33
, {RN02
}},
834 { "cmp", 0xa000, 0xf000, 0, FMT_S1
, 0, {SIMM8
, DN01
}},
835 { "cmp", 0xa0, 0xf0, 0x3, FMT_S0
, 0, {DM1
, DN0
}},
836 { "cmp", 0xf1a0, 0xfff0, 0, FMT_D0
, 0, {DM1
, AN0
}},
837 { "cmp", 0xf190, 0xfff0, 0, FMT_D0
, 0, {AM1
, DN0
}},
838 { "cmp", 0xb000, 0xf000, 0, FMT_S1
, 0, {IMM8
, AN01
}},
839 { "cmp", 0xb0, 0xf0, 0x3, FMT_S0
, 0, {AM1
, AN0
}},
840 { "cmp", 0xfac80000, 0xfffc0000, 0, FMT_D2
, 0, {SIMM16
, DN0
}},
841 { "cmp", 0xfad80000, 0xfffc0000, 0, FMT_D2
, 0, {IMM16
, AN0
}},
842 { "cmp", 0xf9d800, 0xffff00, 0, FMT_D6
, AM33
, {RM2
, RN0
}},
843 { "cmp", 0xfcc80000, 0xfffc0000, 0, FMT_D4
, 0, {IMM32
, DN0
}},
844 { "cmp", 0xfcd80000, 0xfffc0000, 0, FMT_D4
, 0, {IMM32
, AN0
}},
845 { "cmp", 0xfbd80000, 0xffff0000, 0, FMT_D7
, AM33
, {SIMM8
, RN02
}},
846 { "cmp", 0xfdd80000, 0xffff0000, 0, FMT_D8
, AM33
, {SIMM24
, RN02
}},
847 { "cmp", 0xfed80000, 0xffff0000, 0, FMT_D9
, AM33
, {IMM32_HIGH8
, RN02
}},
849 { "and", 0xfb0d0000, 0xffff000f, 0, FMT_D7
, AM33
, {RM2
, RN0
, RD2
}},
850 { "and", 0xf200, 0xfff0, 0, FMT_D0
, 0, {DM1
, DN0
}},
851 { "and", 0xf8e000, 0xfffc00, 0, FMT_D1
, 0, {IMM8
, DN0
}},
852 { "and", 0xfae00000, 0xfffc0000, 0, FMT_D2
, 0, {IMM16
, DN0
}},
853 { "and", 0xfafc0000, 0xffff0000, 0, FMT_D2
, 0, {IMM16
, PSW
}},
854 { "and", 0xfcfc0000, 0xffff0000, 0, FMT_D4
, AM33
, {IMM32
, EPSW
}},
855 { "and", 0xf90900, 0xffff00, 0, FMT_D6
, AM33
, {RM2
, RN0
}},
856 { "and", 0xfce00000, 0xfffc0000, 0, FMT_D4
, 0, {IMM32
, DN0
}},
857 { "and", 0xfb090000, 0xffff0000, 0, FMT_D7
, AM33
, {IMM8
, RN02
}},
858 { "and", 0xfd090000, 0xffff0000, 0, FMT_D8
, AM33
, {IMM24
, RN02
}},
859 { "and", 0xfe090000, 0xffff0000, 0, FMT_D9
, AM33
, {IMM32_HIGH8
, RN02
}},
861 { "or", 0xfb1d0000, 0xffff000f, 0, FMT_D7
, AM33
, {RM2
, RN0
, RD2
}},
862 { "or", 0xf210, 0xfff0, 0, FMT_D0
, 0, {DM1
, DN0
}},
863 { "or", 0xf8e400, 0xfffc00, 0, FMT_D1
, 0, {IMM8
, DN0
}},
864 { "or", 0xfae40000, 0xfffc0000, 0, FMT_D2
, 0, {IMM16
, DN0
}},
865 { "or", 0xfafd0000, 0xffff0000, 0, FMT_D2
, 0, {IMM16
, PSW
}},
866 { "or", 0xfcfd0000, 0xffff0000, 0, FMT_D4
, AM33
, {IMM32
, EPSW
}},
867 { "or", 0xf91900, 0xffff00, 0, FMT_D6
, AM33
, {RM2
, RN0
}},
868 { "or", 0xfce40000, 0xfffc0000, 0, FMT_D4
, 0, {IMM32
, DN0
}},
869 { "or", 0xfb190000, 0xffff0000, 0, FMT_D7
, AM33
, {IMM8
, RN02
}},
870 { "or", 0xfd190000, 0xffff0000, 0, FMT_D8
, AM33
, {IMM24
, RN02
}},
871 { "or", 0xfe190000, 0xffff0000, 0, FMT_D9
, AM33
, {IMM32_HIGH8
, RN02
}},
873 { "xor", 0xfb2d0000, 0xffff000f, 0, FMT_D7
, AM33
, {RM2
, RN0
, RD2
}},
874 { "xor", 0xf220, 0xfff0, 0, FMT_D0
, 0, {DM1
, DN0
}},
875 { "xor", 0xfae80000, 0xfffc0000, 0, FMT_D2
, 0, {IMM16
, DN0
}},
876 { "xor", 0xf92900, 0xffff00, 0, FMT_D6
, AM33
, {RM2
, RN0
}},
877 { "xor", 0xfce80000, 0xfffc0000, 0, FMT_D4
, 0, {IMM32
, DN0
}},
878 { "xor", 0xfb290000, 0xffff0000, 0, FMT_D7
, AM33
, {IMM8
, RN02
}},
879 { "xor", 0xfd290000, 0xffff0000, 0, FMT_D8
, AM33
, {IMM24
, RN02
}},
880 { "xor", 0xfe290000, 0xffff0000, 0, FMT_D9
, AM33
, {IMM32_HIGH8
, RN02
}},
882 { "not", 0xf230, 0xfffc, 0, FMT_D0
, 0, {DN0
}},
883 { "not", 0xf93900, 0xffff00, 0, FMT_D6
, AM33
, {RN02
}},
885 { "btst", 0xf8ec00, 0xfffc00, 0, FMT_D1
, 0, {IMM8
, DN0
}},
886 { "btst", 0xfaec0000, 0xfffc0000, 0, FMT_D2
, 0, {IMM16
, DN0
}},
887 { "btst", 0xfcec0000, 0xfffc0000, 0, FMT_D4
, 0, {IMM32
, DN0
}},
888 /* Place these before the ones with IMM8E and SD8N_SHIFT8 since we want the
889 them to match last since they do not promote. */
890 { "btst", 0xfbe90000, 0xffff0000, 0, FMT_D7
, AM33
, {IMM8
, RN02
}},
891 { "btst", 0xfde90000, 0xffff0000, 0, FMT_D8
, AM33
, {IMM24
, RN02
}},
892 { "btst", 0xfee90000, 0xffff0000, 0, FMT_D9
, AM33
, {IMM32_HIGH8
, RN02
}},
893 { "btst", 0xfe820000, 0xffff0000, 0, FMT_D3
, AM33_2
, {IMM8E
, MEM(IMM16_MEM
)}},
894 { "btst", 0xfe020000, 0xffff0000, 0, FMT_D5
, 0, {IMM8E
, MEM(IMM32_LOWSHIFT8
)}},
895 { "btst", 0xfaf80000, 0xfffc0000, 0, FMT_D2
, 0, {IMM8
, MEM2(SD8N_SHIFT8
, AN0
)}},
897 { "bset", 0xf080, 0xfff0, 0, FMT_D0
, 0, {DM1
, MEM(AN0
)}},
898 { "bset", 0xfe800000, 0xffff0000, 0, FMT_D3
, AM33_2
, {IMM8E
, MEM(IMM16_MEM
)}},
899 { "bset", 0xfe000000, 0xffff0000, 0, FMT_D5
, 0, {IMM8E
, MEM(IMM32_LOWSHIFT8
)}},
900 { "bset", 0xfaf00000, 0xfffc0000, 0, FMT_D2
, 0, {IMM8
, MEM2(SD8N_SHIFT8
, AN0
)}},
902 { "bclr", 0xf090, 0xfff0, 0, FMT_D0
, 0, {DM1
, MEM(AN0
)}},
903 { "bclr", 0xfe810000, 0xffff0000, 0, FMT_D3
, AM33_2
, {IMM8E
, MEM(IMM16_MEM
)}},
904 { "bclr", 0xfe010000, 0xffff0000, 0, FMT_D5
, 0, {IMM8E
, MEM(IMM32_LOWSHIFT8
)}},
905 { "bclr", 0xfaf40000, 0xfffc0000, 0, FMT_D2
, 0, {IMM8
, MEM2(SD8N_SHIFT8
,AN0
)}},
907 { "asr", 0xfb4d0000, 0xffff000f, 0, FMT_D7
, AM33
, {RM2
, RN0
, RD2
}},
908 { "asr", 0xf2b0, 0xfff0, 0, FMT_D0
, 0, {DM1
, DN0
}},
909 { "asr", 0xf8c800, 0xfffc00, 0, FMT_D1
, 0, {IMM8
, DN0
}},
910 { "asr", 0xf94900, 0xffff00, 0, FMT_D6
, AM33
, {RM2
, RN0
}},
911 { "asr", 0xfb490000, 0xffff0000, 0, FMT_D7
, AM33
, {IMM8
, RN02
}},
912 { "asr", 0xfd490000, 0xffff0000, 0, FMT_D8
, AM33
, {IMM24
, RN02
}},
913 { "asr", 0xfe490000, 0xffff0000, 0, FMT_D9
, AM33
, {IMM32_HIGH8
, RN02
}},
914 { "asr", 0xf8c801, 0xfffcff, 0, FMT_D1
, 0, {DN0
}},
915 { "asr", 0xfb490001, 0xffff00ff, 0, FMT_D7
, AM33
, {RN02
}},
917 { "lsr", 0xfb5d0000, 0xffff000f, 0, FMT_D7
, AM33
, {RM2
, RN0
, RD2
}},
918 { "lsr", 0xf2a0, 0xfff0, 0, FMT_D0
, 0, {DM1
, DN0
}},
919 { "lsr", 0xf8c400, 0xfffc00, 0, FMT_D1
, 0, {IMM8
, DN0
}},
920 { "lsr", 0xf95900, 0xffff00, 0, FMT_D6
, AM33
, {RM2
, RN0
}},
921 { "lsr", 0xfb590000, 0xffff0000, 0, FMT_D7
, AM33
, {IMM8
, RN02
}},
922 { "lsr", 0xfd590000, 0xffff0000, 0, FMT_D8
, AM33
, {IMM24
, RN02
}},
923 { "lsr", 0xfe590000, 0xffff0000, 0, FMT_D9
, AM33
, {IMM32_HIGH8
, RN02
}},
924 { "lsr", 0xf8c401, 0xfffcff, 0, FMT_D1
, 0, {DN0
}},
925 { "lsr", 0xfb590001, 0xffff00ff, 0, FMT_D7
, AM33
, {RN02
}},
927 { "asl", 0xfb6d0000, 0xffff000f, 0, FMT_D7
, AM33
, {RM2
, RN0
, RD2
}},
928 { "asl", 0xf290, 0xfff0, 0, FMT_D0
, 0, {DM1
, DN0
}},
929 { "asl", 0xf8c000, 0xfffc00, 0, FMT_D1
, 0, {IMM8
, DN0
}},
930 { "asl", 0xf96900, 0xffff00, 0, FMT_D6
, AM33
, {RM2
, RN0
}},
931 { "asl", 0xfb690000, 0xffff0000, 0, FMT_D7
, AM33
, {SIMM8
, RN02
}},
932 { "asl", 0xfd690000, 0xffff0000, 0, FMT_D8
, AM33
, {IMM24
, RN02
}},
933 { "asl", 0xfe690000, 0xffff0000, 0, FMT_D9
, AM33
, {IMM32_HIGH8
, RN02
}},
934 { "asl", 0xf8c001, 0xfffcff, 0, FMT_D1
, 0, {DN0
}},
935 { "asl", 0xfb690001, 0xffff00ff, 0, FMT_D7
, AM33
, {RN02
}},
937 { "asl2", 0x54, 0xfc, 0, FMT_S0
, 0, {DN0
}},
938 { "asl2", 0xf97900, 0xffff00, 0, FMT_D6
, AM33
, {RN02
}},
940 { "ror", 0xf284, 0xfffc, 0, FMT_D0
, 0, {DN0
}},
941 { "ror", 0xf98900, 0xffff00, 0, FMT_D6
, AM33
, {RN02
}},
943 { "rol", 0xf280, 0xfffc, 0, FMT_D0
, 0, {DN0
}},
944 { "rol", 0xf99900, 0xffff00, 0, FMT_D6
, AM33
, {RN02
}},
946 { "beq", 0xc800, 0xff00, 0, FMT_S1
, 0, {SD8N_PCREL
}},
947 { "bne", 0xc900, 0xff00, 0, FMT_S1
, 0, {SD8N_PCREL
}},
948 { "bgt", 0xc100, 0xff00, 0, FMT_S1
, 0, {SD8N_PCREL
}},
949 { "bge", 0xc200, 0xff00, 0, FMT_S1
, 0, {SD8N_PCREL
}},
950 { "ble", 0xc300, 0xff00, 0, FMT_S1
, 0, {SD8N_PCREL
}},
951 { "blt", 0xc000, 0xff00, 0, FMT_S1
, 0, {SD8N_PCREL
}},
952 { "bhi", 0xc500, 0xff00, 0, FMT_S1
, 0, {SD8N_PCREL
}},
953 { "bcc", 0xc600, 0xff00, 0, FMT_S1
, 0, {SD8N_PCREL
}},
954 { "bls", 0xc700, 0xff00, 0, FMT_S1
, 0, {SD8N_PCREL
}},
955 { "bcs", 0xc400, 0xff00, 0, FMT_S1
, 0, {SD8N_PCREL
}},
956 { "bvc", 0xf8e800, 0xffff00, 0, FMT_D1
, 0, {SD8N_PCREL
}},
957 { "bvs", 0xf8e900, 0xffff00, 0, FMT_D1
, 0, {SD8N_PCREL
}},
958 { "bnc", 0xf8ea00, 0xffff00, 0, FMT_D1
, 0, {SD8N_PCREL
}},
959 { "bns", 0xf8eb00, 0xffff00, 0, FMT_D1
, 0, {SD8N_PCREL
}},
960 { "bra", 0xca00, 0xff00, 0, FMT_S1
, 0, {SD8N_PCREL
}},
962 { "leq", 0xd8, 0xff, 0, FMT_S0
, 0, {UNUSED
}},
963 { "lne", 0xd9, 0xff, 0, FMT_S0
, 0, {UNUSED
}},
964 { "lgt", 0xd1, 0xff, 0, FMT_S0
, 0, {UNUSED
}},
965 { "lge", 0xd2, 0xff, 0, FMT_S0
, 0, {UNUSED
}},
966 { "lle", 0xd3, 0xff, 0, FMT_S0
, 0, {UNUSED
}},
967 { "llt", 0xd0, 0xff, 0, FMT_S0
, 0, {UNUSED
}},
968 { "lhi", 0xd5, 0xff, 0, FMT_S0
, 0, {UNUSED
}},
969 { "lcc", 0xd6, 0xff, 0, FMT_S0
, 0, {UNUSED
}},
970 { "lls", 0xd7, 0xff, 0, FMT_S0
, 0, {UNUSED
}},
971 { "lcs", 0xd4, 0xff, 0, FMT_S0
, 0, {UNUSED
}},
972 { "lra", 0xda, 0xff, 0, FMT_S0
, 0, {UNUSED
}},
973 { "setlb", 0xdb, 0xff, 0, FMT_S0
, 0, {UNUSED
}},
975 { "fbeq", 0xf8d000, 0xffff00, 0, FMT_D1
, AM33_2
, {SD8N_PCREL
}},
976 { "fbne", 0xf8d100, 0xffff00, 0, FMT_D1
, AM33_2
, {SD8N_PCREL
}},
977 { "fbgt", 0xf8d200, 0xffff00, 0, FMT_D1
, AM33_2
, {SD8N_PCREL
}},
978 { "fbge", 0xf8d300, 0xffff00, 0, FMT_D1
, AM33_2
, {SD8N_PCREL
}},
979 { "fblt", 0xf8d400, 0xffff00, 0, FMT_D1
, AM33_2
, {SD8N_PCREL
}},
980 { "fble", 0xf8d500, 0xffff00, 0, FMT_D1
, AM33_2
, {SD8N_PCREL
}},
981 { "fbuo", 0xf8d600, 0xffff00, 0, FMT_D1
, AM33_2
, {SD8N_PCREL
}},
982 { "fblg", 0xf8d700, 0xffff00, 0, FMT_D1
, AM33_2
, {SD8N_PCREL
}},
983 { "fbleg", 0xf8d800, 0xffff00, 0, FMT_D1
, AM33_2
, {SD8N_PCREL
}},
984 { "fbug", 0xf8d900, 0xffff00, 0, FMT_D1
, AM33_2
, {SD8N_PCREL
}},
985 { "fbuge", 0xf8da00, 0xffff00, 0, FMT_D1
, AM33_2
, {SD8N_PCREL
}},
986 { "fbul", 0xf8db00, 0xffff00, 0, FMT_D1
, AM33_2
, {SD8N_PCREL
}},
987 { "fbule", 0xf8dc00, 0xffff00, 0, FMT_D1
, AM33_2
, {SD8N_PCREL
}},
988 { "fbue", 0xf8dd00, 0xffff00, 0, FMT_D1
, AM33_2
, {SD8N_PCREL
}},
990 { "fleq", 0xf0d0, 0xffff, 0, FMT_D0
, AM33_2
, {UNUSED
}},
991 { "flne", 0xf0d1, 0xffff, 0, FMT_D0
, AM33_2
, {UNUSED
}},
992 { "flgt", 0xf0d2, 0xffff, 0, FMT_D0
, AM33_2
, {UNUSED
}},
993 { "flge", 0xf0d3, 0xffff, 0, FMT_D0
, AM33_2
, {UNUSED
}},
994 { "fllt", 0xf0d4, 0xffff, 0, FMT_D0
, AM33_2
, {UNUSED
}},
995 { "flle", 0xf0d5, 0xffff, 0, FMT_D0
, AM33_2
, {UNUSED
}},
996 { "fluo", 0xf0d6, 0xffff, 0, FMT_D0
, AM33_2
, {UNUSED
}},
997 { "fllg", 0xf0d7, 0xffff, 0, FMT_D0
, AM33_2
, {UNUSED
}},
998 { "flleg", 0xf0d8, 0xffff, 0, FMT_D0
, AM33_2
, {UNUSED
}},
999 { "flug", 0xf0d9, 0xffff, 0, FMT_D0
, AM33_2
, {UNUSED
}},
1000 { "fluge", 0xf0da, 0xffff, 0, FMT_D0
, AM33_2
, {UNUSED
}},
1001 { "flul", 0xf0db, 0xffff, 0, FMT_D0
, AM33_2
, {UNUSED
}},
1002 { "flule", 0xf0dc, 0xffff, 0, FMT_D0
, AM33_2
, {UNUSED
}},
1003 { "flue", 0xf0dd, 0xffff, 0, FMT_D0
, AM33_2
, {UNUSED
}},
1005 { "jmp", 0xf0f4, 0xfffc, 0, FMT_D0
, 0, {PAREN
,AN0
,PAREN
}},
1006 { "jmp", 0xcc0000, 0xff0000, 0, FMT_S2
, 0, {IMM16_PCREL
}},
1007 { "jmp", 0xdc000000, 0xff000000, 0, FMT_S4
, 0, {IMM32_HIGH24
}},
1008 { "call", 0xcd000000, 0xff000000, 0, FMT_S4
, 0, {D16_SHIFT
,REGS
,IMM8E
}},
1009 { "call", 0xdd000000, 0xff000000, 0, FMT_S6
, 0, {IMM32_HIGH24_LOWSHIFT16
, REGSE_SHIFT8
,IMM8E
}},
1010 { "calls", 0xf0f0, 0xfffc, 0, FMT_D0
, 0, {PAREN
,AN0
,PAREN
}},
1011 { "calls", 0xfaff0000, 0xffff0000, 0, FMT_D2
, 0, {IMM16_PCREL
}},
1012 { "calls", 0xfcff0000, 0xffff0000, 0, FMT_D4
, 0, {IMM32_PCREL
}},
1014 { "ret", 0xdf0000, 0xff0000, 0, FMT_S2
, 0, {REGS_SHIFT8
, IMM8
}},
1015 { "retf", 0xde0000, 0xff0000, 0, FMT_S2
, 0, {REGS_SHIFT8
, IMM8
}},
1016 { "rets", 0xf0fc, 0xffff, 0, FMT_D0
, 0, {UNUSED
}},
1017 { "rti", 0xf0fd, 0xffff, 0, FMT_D0
, 0, {UNUSED
}},
1018 { "trap", 0xf0fe, 0xffff, 0, FMT_D0
, 0, {UNUSED
}},
1019 { "rtm", 0xf0ff, 0xffff, 0, FMT_D0
, 0, {UNUSED
}},
1020 { "nop", 0xcb, 0xff, 0, FMT_S0
, 0, {UNUSED
}},
1022 { "dcpf", 0xf9a600, 0xffff0f, 0, FMT_D6
, AM33_2
, {MEM (RM2
)}},
1023 { "dcpf", 0xf9a700, 0xffffff, 0, FMT_D6
, AM33_2
, {MEM (SP
)}},
1024 { "dcpf", 0xfba60000, 0xffff00ff, 0, FMT_D7
, AM33_2
, {MEM2 (RI
,RM0
)}},
1025 { "dcpf", 0xfba70000, 0xffff0f00, 0, FMT_D7
, AM33_2
, {MEM2 (SD8
,RM2
)}},
1026 { "dcpf", 0xfda70000, 0xffff0f00, 0, FMT_D8
, AM33_2
, {MEM2 (SD24
,RM2
)}},
1027 { "dcpf", 0xfe460000, 0xffff0f00, 0, FMT_D9
, AM33_2
, {MEM2 (IMM32_HIGH8
,RM2
)}},
1029 { "fmov", 0xf92000, 0xfffe00, 0, FMT_D6
, AM33_2
, {MEM (RM2
), FSM0
}},
1030 { "fmov", 0xf92200, 0xfffe00, 0, FMT_D6
, AM33_2
, {MEMINC (RM2
), FSM0
}},
1031 { "fmov", 0xf92400, 0xfffef0, 0, FMT_D6
, AM33_2
, {MEM (SP
), FSM0
}},
1032 { "fmov", 0xf92600, 0xfffe00, 0, FMT_D6
, AM33_2
, {RM2
, FSM0
}},
1033 { "fmov", 0xf93000, 0xfffd00, 0, FMT_D6
, AM33_2
, {FSM1
, MEM (RM0
)}},
1034 { "fmov", 0xf93100, 0xfffd00, 0, FMT_D6
, AM33_2
, {FSM1
, MEMINC (RM0
)}},
1035 { "fmov", 0xf93400, 0xfffd0f, 0, FMT_D6
, AM33_2
, {FSM1
, MEM (SP
)}},
1036 { "fmov", 0xf93500, 0xfffd00, 0, FMT_D6
, AM33_2
, {FSM1
, RM0
}},
1037 { "fmov", 0xf94000, 0xfffc00, 0, FMT_D6
, AM33_2
, {FSM1
, FSM0
}},
1038 { "fmov", 0xf9a000, 0xfffe01, 0, FMT_D6
, AM33_2
, {MEM (RM2
), FDM0
}},
1039 { "fmov", 0xf9a200, 0xfffe01, 0, FMT_D6
, AM33_2
, {MEMINC (RM2
), FDM0
}},
1040 { "fmov", 0xf9a400, 0xfffef1, 0, FMT_D6
, AM33_2
, {MEM (SP
), FDM0
}},
1041 { "fmov", 0xf9b000, 0xfffd10, 0, FMT_D6
, AM33_2
, {FDM1
, MEM (RM0
)}},
1042 { "fmov", 0xf9b100, 0xfffd10, 0, FMT_D6
, AM33_2
, {FDM1
, MEMINC (RM0
)}},
1043 { "fmov", 0xf9b400, 0xfffd1f, 0, FMT_D6
, AM33_2
, {FDM1
, MEM (SP
)}},
1044 { "fmov", 0xf9b500, 0xffff0f, 0, FMT_D6
, AM33_2
, {RM2
, FPCR
}},
1045 { "fmov", 0xf9b700, 0xfffff0, 0, FMT_D6
, AM33_2
, {FPCR
, RM0
}},
1046 { "fmov", 0xf9c000, 0xfffc11, 0, FMT_D6
, AM33_2
, {FDM1
, FDM0
}},
1047 { "fmov", 0xfb200000, 0xfffe0000, 0, FMT_D7
, AM33_2
, {MEM2 (SD8
, RM2
), FSM2
}},
1048 { "fmov", 0xfb220000, 0xfffe0000, 0, FMT_D7
, AM33_2
, {MEMINC2 (RM2
, SIMM8
), FSM2
}},
1049 { "fmov", 0xfb240000, 0xfffef000, 0, FMT_D7
, AM33_2
, {MEM2 (IMM8
, SP
), FSM2
}},
1050 { "fmov", 0xfb270000, 0xffff000d, 0, FMT_D7
, AM33_2
, {MEM2 (RI
, RM0
), FSN1
}},
1051 { "fmov", 0xfb300000, 0xfffd0000, 0, FMT_D7
, AM33_2
, {FSM3
, MEM2 (SD8
, RM0
)}},
1052 { "fmov", 0xfb310000, 0xfffd0000, 0, FMT_D7
, AM33_2
, {FSM3
, MEMINC2 (RM0
, SIMM8
)}},
1053 { "fmov", 0xfb340000, 0xfffd0f00, 0, FMT_D7
, AM33_2
, {FSM3
, MEM2 (IMM8
, SP
)}},
1054 { "fmov", 0xfb370000, 0xffff000d, 0, FMT_D7
, AM33_2
, {FSN1
, MEM2(RI
, RM0
)}},
1055 /* FIXME: the spec doesn't say the fd register must be even for the
1056 * next two insns. Assuming it was a mistake in the spec. */
1057 { "fmov", 0xfb470000, 0xffff001d, 0, FMT_D7
, AM33_2
, {MEM2 (RI
, RM0
), FDN1
}},
1058 { "fmov", 0xfb570000, 0xffff001d, 0, FMT_D7
, AM33_2
, {FDN1
, MEM2(RI
, RM0
)}},
1060 { "fmov", 0xfba00000, 0xfffe0100, 0, FMT_D7
, AM33_2
, {MEM2 (SD8
, RM2
), FDM2
}},
1061 { "fmov", 0xfba20000, 0xfffe0100, 0, FMT_D7
, AM33_2
, {MEMINC2 (RM2
, SIMM8
), FDM2
}},
1062 { "fmov", 0xfba40000, 0xfffef100, 0, FMT_D7
, AM33_2
, {MEM2 (IMM8
, SP
), FDM2
}},
1063 { "fmov", 0xfbb00000, 0xfffd1000, 0, FMT_D7
, AM33_2
, {FDM3
, MEM2 (SD8
, RM0
)}},
1064 { "fmov", 0xfbb10000, 0xfffd1000, 0, FMT_D7
, AM33_2
, {FDM3
, MEMINC2 (RM0
, SIMM8
)}},
1065 { "fmov", 0xfbb40000, 0xfffd1f00, 0, FMT_D7
, AM33_2
, {FDM3
, MEM2 (IMM8
, SP
)}},
1066 { "fmov", 0xfd200000, 0xfffe0000, 0, FMT_D8
, AM33_2
, {MEM2 (SIMM24
, RM2
), FSM2
}},
1067 { "fmov", 0xfd220000, 0xfffe0000, 0, FMT_D8
, AM33_2
, {MEMINC2 (RM2
, SIMM24
), FSM2
}},
1068 { "fmov", 0xfd240000, 0xfffef000, 0, FMT_D8
, AM33_2
, {MEM2 (IMM24
, SP
), FSM2
}},
1069 { "fmov", 0xfd300000, 0xfffd0000, 0, FMT_D8
, AM33_2
, {FSM3
, MEM2 (SIMM24
, RM0
)}},
1070 { "fmov", 0xfd310000, 0xfffd0000, 0, FMT_D8
, AM33_2
, {FSM3
, MEMINC2 (RM0
, SIMM24
)}},
1071 { "fmov", 0xfd340000, 0xfffd0f00, 0, FMT_D8
, AM33_2
, {FSM3
, MEM2 (IMM24
, SP
)}},
1072 { "fmov", 0xfda00000, 0xfffe0100, 0, FMT_D8
, AM33_2
, {MEM2 (SIMM24
, RM2
), FDM2
}},
1073 { "fmov", 0xfda20000, 0xfffe0100, 0, FMT_D8
, AM33_2
, {MEMINC2 (RM2
, SIMM24
), FDM2
}},
1074 { "fmov", 0xfda40000, 0xfffef100, 0, FMT_D8
, AM33_2
, {MEM2 (IMM24
, SP
), FDM2
}},
1075 { "fmov", 0xfdb00000, 0xfffd1000, 0, FMT_D8
, AM33_2
, {FDM3
, MEM2 (SIMM24
, RM0
)}},
1076 { "fmov", 0xfdb10000, 0xfffd1000, 0, FMT_D8
, AM33_2
, {FDM3
, MEMINC2 (RM0
, SIMM24
)}},
1077 { "fmov", 0xfdb40000, 0xfffd1f00, 0, FMT_D8
, AM33_2
, {FDM3
, MEM2 (IMM24
, SP
)}},
1078 { "fmov", 0xfdb50000, 0xffff0000, 0, FMT_D4
, AM33_2
, {IMM32
, FPCR
}},
1079 { "fmov", 0xfe200000, 0xfffe0000, 0, FMT_D9
, AM33_2
, {MEM2 (IMM32_HIGH8
, RM2
), FSM2
}},
1080 { "fmov", 0xfe220000, 0xfffe0000, 0, FMT_D9
, AM33_2
, {MEMINC2 (RM2
, IMM32_HIGH8
), FSM2
}},
1081 { "fmov", 0xfe240000, 0xfffef000, 0, FMT_D9
, AM33_2
, {MEM2 (IMM32_HIGH8
, SP
), FSM2
}},
1082 { "fmov", 0xfe260000, 0xfffef000, 0, FMT_D9
, AM33_2
, {IMM32_HIGH8
, FSM2
}},
1083 { "fmov", 0xfe300000, 0xfffd0000, 0, FMT_D9
, AM33_2
, {FSM3
, MEM2 (IMM32_HIGH8
, RM0
)}},
1084 { "fmov", 0xfe310000, 0xfffd0000, 0, FMT_D9
, AM33_2
, {FSM3
, MEMINC2 (RM0
, IMM32_HIGH8
)}},
1085 { "fmov", 0xfe340000, 0xfffd0f00, 0, FMT_D9
, AM33_2
, {FSM3
, MEM2 (IMM32_HIGH8
, SP
)}},
1086 { "fmov", 0xfe400000, 0xfffe0100, 0, FMT_D9
, AM33_2
, {MEM2 (IMM32_HIGH8
, RM2
), FDM2
}},
1087 { "fmov", 0xfe420000, 0xfffe0100, 0, FMT_D9
, AM33_2
, {MEMINC2 (RM2
, IMM32_HIGH8
), FDM2
}},
1088 { "fmov", 0xfe440000, 0xfffef100, 0, FMT_D9
, AM33_2
, {MEM2 (IMM32_HIGH8
, SP
), FDM2
}},
1089 { "fmov", 0xfe500000, 0xfffd1000, 0, FMT_D9
, AM33_2
, {FDM3
, MEM2 (IMM32_HIGH8
, RM0
)}},
1090 { "fmov", 0xfe510000, 0xfffd1000, 0, FMT_D9
, AM33_2
, {FDM3
, MEMINC2 (RM0
, IMM32_HIGH8
)}},
1091 { "fmov", 0xfe540000, 0xfffd1f00, 0, FMT_D9
, AM33_2
, {FDM3
, MEM2 (IMM32_HIGH8
, SP
)}},
1093 /* FIXME: these are documented in the instruction bitmap, but not in
1094 * the instruction manual. */
1095 { "ftoi", 0xfb400000, 0xffff0f05, 0, FMT_D10
,AM33_2
, {FSN3
, FSN1
}},
1096 { "itof", 0xfb420000, 0xffff0f05, 0, FMT_D10
,AM33_2
, {FSN3
, FSN1
}},
1097 { "ftod", 0xfb520000, 0xffff0f15, 0, FMT_D10
,AM33_2
, {FSN3
, FDN1
}},
1098 { "dtof", 0xfb560000, 0xffff1f05, 0, FMT_D10
,AM33_2
, {FDN3
, FSN1
}},
1101 { "fabs", 0xfb440000, 0xffff0f05, 0, FMT_D10
,AM33_2
, {FSN3
, FSN1
}},
1102 { "fabs", 0xfbc40000, 0xffff1f15, 0, FMT_D10
,AM33_2
, {FDN3
, FDN1
}},
1103 { "fabs", 0xf94400, 0xfffef0, 0, FMT_D6
, AM33_2
, {FSM0
}},
1104 { "fabs", 0xf9c400, 0xfffef1, 0, FMT_D6
, AM33_2
, {FDM0
}},
1106 { "fneg", 0xfb460000, 0xffff0f05, 0, FMT_D10
,AM33_2
, {FSN3
, FSN1
}},
1107 { "fneg", 0xfbc60000, 0xffff1f15, 0, FMT_D10
,AM33_2
, {FDN3
, FDN1
}},
1108 { "fneg", 0xf94600, 0xfffef0, 0, FMT_D6
, AM33_2
, {FSM0
}},
1109 { "fneg", 0xf9c600, 0xfffef1, 0, FMT_D6
, AM33_2
, {FDM0
}},
1111 { "frsqrt", 0xfb500000, 0xffff0f05, 0, FMT_D10
,AM33_2
, {FSN3
, FSN1
}},
1112 { "frsqrt", 0xfbd00000, 0xffff1f15, 0, FMT_D10
,AM33_2
, {FDN3
, FDN1
}},
1113 { "frsqrt", 0xf95000, 0xfffef0, 0, FMT_D6
, AM33_2
, {FSM0
}},
1114 { "frsqrt", 0xf9d000, 0xfffef1, 0, FMT_D6
, AM33_2
, {FDM0
}},
1116 /* FIXME: this is documented in the instruction bitmap, but not in
1117 * the instruction manual. */
1118 { "fsqrt", 0xfb540000, 0xffff0f05, 0, FMT_D10
,AM33_2
, {FSN3
, FSN1
}},
1119 { "fsqrt", 0xfbd40000, 0xffff1f15, 0, FMT_D10
,AM33_2
, {FDN3
, FDN1
}},
1120 { "fsqrt", 0xf95200, 0xfffef0, 0, FMT_D6
, AM33_2
, {FSM0
}},
1121 { "fsqrt", 0xf9d200, 0xfffef1, 0, FMT_D6
, AM33_2
, {FDM0
}},
1124 { "fcmp", 0xf95400, 0xfffc00, 0, FMT_D6
, AM33_2
, {FSM1
, FSM0
}},
1125 { "fcmp", 0xf9d400, 0xfffc11, 0, FMT_D6
, AM33_2
, {FDM1
, FDM0
}},
1126 { "fcmp", 0xfe350000, 0xfffd0f00, 0, FMT_D9
, AM33_2
, {IMM32_HIGH8
, FSM3
}},
1128 { "fadd", 0xfb600000, 0xffff0001, 0, FMT_D10
,AM33_2
, {FSN3
, FSN2
, FSN1
}},
1129 { "fadd", 0xfbe00000, 0xffff1111, 0, FMT_D10
,AM33_2
, {FDN3
, FDN2
, FDN1
}},
1130 { "fadd", 0xf96000, 0xfffc00, 0, FMT_D6
, AM33_2
, {FSM1
, FSM0
}},
1131 { "fadd", 0xf9e000, 0xfffc11, 0, FMT_D6
, AM33_2
, {FDM1
, FDM0
}},
1132 { "fadd", 0xfe600000, 0xfffc0000, 0, FMT_D9
, AM33_2
, {IMM32_HIGH8
, FSM3
, FSM2
}},
1134 { "fsub", 0xfb640000, 0xffff0001, 0, FMT_D10
,AM33_2
, {FSN3
, FSN2
, FSN1
}},
1135 { "fsub", 0xfbe40000, 0xffff1111, 0, FMT_D10
,AM33_2
, {FDN3
, FDN2
, FDN1
}},
1136 { "fsub", 0xf96400, 0xfffc00, 0, FMT_D6
, AM33_2
, {FSM1
, FSM0
}},
1137 { "fsub", 0xf9e400, 0xfffc11, 0, FMT_D6
, AM33_2
, {FDM1
, FDM0
}},
1138 { "fsub", 0xfe640000, 0xfffc0000, 0, FMT_D9
, AM33_2
, {IMM32_HIGH8
, FSM3
, FSM2
}},
1140 { "fmul", 0xfb700000, 0xffff0001, 0, FMT_D10
,AM33_2
, {FSN3
, FSN2
, FSN1
}},
1141 { "fmul", 0xfbf00000, 0xffff1111, 0, FMT_D10
,AM33_2
, {FDN3
, FDN2
, FDN1
}},
1142 { "fmul", 0xf97000, 0xfffc00, 0, FMT_D6
, AM33_2
, {FSM1
, FSM0
}},
1143 { "fmul", 0xf9f000, 0xfffc11, 0, FMT_D6
, AM33_2
, {FDM1
, FDM0
}},
1144 { "fmul", 0xfe700000, 0xfffc0000, 0, FMT_D9
, AM33_2
, {IMM32_HIGH8
, FSM3
, FSM2
}},
1146 { "fdiv", 0xfb740000, 0xffff0001, 0, FMT_D10
,AM33_2
, {FSN3
, FSN2
, FSN1
}},
1147 { "fdiv", 0xfbf40000, 0xffff1111, 0, FMT_D10
,AM33_2
, {FDN3
, FDN2
, FDN1
}},
1148 { "fdiv", 0xf97400, 0xfffc00, 0, FMT_D6
, AM33_2
, {FSM1
, FSM0
}},
1149 { "fdiv", 0xf9f400, 0xfffc11, 0, FMT_D6
, AM33_2
, {FDM1
, FDM0
}},
1150 { "fdiv", 0xfe740000, 0xfffc0000, 0, FMT_D9
, AM33_2
, {IMM32_HIGH8
, FSM3
, FSM2
}},
1152 { "fmadd", 0xfb800000, 0xfffc0000, 0, FMT_D10
,AM33_2
, {FSN3
, FSN2
, FSN1
, FSACC
}},
1153 { "fmsub", 0xfb840000, 0xfffc0000, 0, FMT_D10
,AM33_2
, {FSN3
, FSN2
, FSN1
, FSACC
}},
1154 { "fnmadd", 0xfb900000, 0xfffc0000, 0, FMT_D10
,AM33_2
, {FSN3
, FSN2
, FSN1
, FSACC
}},
1155 { "fnmsub", 0xfb940000, 0xfffc0000, 0, FMT_D10
,AM33_2
, {FSN3
, FSN2
, FSN1
, FSACC
}},
1157 /* UDF instructions. */
1158 { "udf00", 0xf600, 0xfff0, 0, FMT_D0
, 0, {DM1
, DN0
}},
1159 { "udf00", 0xf90000, 0xfffc00, 0, FMT_D1
, 0, {SIMM8
, DN0
}},
1160 { "udf00", 0xfb000000, 0xfffc0000, 0, FMT_D2
, 0, {SIMM16
, DN0
}},
1161 { "udf00", 0xfd000000, 0xfffc0000, 0, FMT_D4
, 0, {IMM32
, DN0
}},
1162 { "udf01", 0xf610, 0xfff0, 0, FMT_D0
, 0, {DM1
, DN0
}},
1163 { "udf01", 0xf91000, 0xfffc00, 0, FMT_D1
, 0, {SIMM8
, DN0
}},
1164 { "udf01", 0xfb100000, 0xfffc0000, 0, FMT_D2
, 0, {SIMM16
, DN0
}},
1165 { "udf01", 0xfd100000, 0xfffc0000, 0, FMT_D4
, 0, {IMM32
, DN0
}},
1166 { "udf02", 0xf620, 0xfff0, 0, FMT_D0
, 0, {DM1
, DN0
}},
1167 { "udf02", 0xf92000, 0xfffc00, 0, FMT_D1
, 0, {SIMM8
, DN0
}},
1168 { "udf02", 0xfb200000, 0xfffc0000, 0, FMT_D2
, 0, {SIMM16
, DN0
}},
1169 { "udf02", 0xfd200000, 0xfffc0000, 0, FMT_D4
, 0, {IMM32
, DN0
}},
1170 { "udf03", 0xf630, 0xfff0, 0, FMT_D0
, 0, {DM1
, DN0
}},
1171 { "udf03", 0xf93000, 0xfffc00, 0, FMT_D1
, 0, {SIMM8
, DN0
}},
1172 { "udf03", 0xfb300000, 0xfffc0000, 0, FMT_D2
, 0, {SIMM16
, DN0
}},
1173 { "udf03", 0xfd300000, 0xfffc0000, 0, FMT_D4
, 0, {IMM32
, DN0
}},
1174 { "udf04", 0xf640, 0xfff0, 0, FMT_D0
, 0, {DM1
, DN0
}},
1175 { "udf04", 0xf94000, 0xfffc00, 0, FMT_D1
, 0, {SIMM8
, DN0
}},
1176 { "udf04", 0xfb400000, 0xfffc0000, 0, FMT_D2
, 0, {SIMM16
, DN0
}},
1177 { "udf04", 0xfd400000, 0xfffc0000, 0, FMT_D4
, 0, {IMM32
, DN0
}},
1178 { "udf05", 0xf650, 0xfff0, 0, FMT_D0
, 0, {DM1
, DN0
}},
1179 { "udf05", 0xf95000, 0xfffc00, 0, FMT_D1
, 0, {SIMM8
, DN0
}},
1180 { "udf05", 0xfb500000, 0xfffc0000, 0, FMT_D2
, 0, {SIMM16
, DN0
}},
1181 { "udf05", 0xfd500000, 0xfffc0000, 0, FMT_D4
, 0, {IMM32
, DN0
}},
1182 { "udf06", 0xf660, 0xfff0, 0, FMT_D0
, 0, {DM1
, DN0
}},
1183 { "udf06", 0xf96000, 0xfffc00, 0, FMT_D1
, 0, {SIMM8
, DN0
}},
1184 { "udf06", 0xfb600000, 0xfffc0000, 0, FMT_D2
, 0, {SIMM16
, DN0
}},
1185 { "udf06", 0xfd600000, 0xfffc0000, 0, FMT_D4
, 0, {IMM32
, DN0
}},
1186 { "udf07", 0xf670, 0xfff0, 0, FMT_D0
, 0, {DM1
, DN0
}},
1187 { "udf07", 0xf97000, 0xfffc00, 0, FMT_D1
, 0, {SIMM8
, DN0
}},
1188 { "udf07", 0xfb700000, 0xfffc0000, 0, FMT_D2
, 0, {SIMM16
, DN0
}},
1189 { "udf07", 0xfd700000, 0xfffc0000, 0, FMT_D4
, 0, {IMM32
, DN0
}},
1190 { "udf08", 0xf680, 0xfff0, 0, FMT_D0
, 0, {DM1
, DN0
}},
1191 { "udf08", 0xf98000, 0xfffc00, 0, FMT_D1
, 0, {SIMM8
, DN0
}},
1192 { "udf08", 0xfb800000, 0xfffc0000, 0, FMT_D2
, 0, {SIMM16
, DN0
}},
1193 { "udf08", 0xfd800000, 0xfffc0000, 0, FMT_D4
, 0, {IMM32
, DN0
}},
1194 { "udf09", 0xf690, 0xfff0, 0, FMT_D0
, 0, {DM1
, DN0
}},
1195 { "udf09", 0xf99000, 0xfffc00, 0, FMT_D1
, 0, {SIMM8
, DN0
}},
1196 { "udf09", 0xfb900000, 0xfffc0000, 0, FMT_D2
, 0, {SIMM16
, DN0
}},
1197 { "udf09", 0xfd900000, 0xfffc0000, 0, FMT_D4
, 0, {IMM32
, DN0
}},
1198 { "udf10", 0xf6a0, 0xfff0, 0, FMT_D0
, 0, {DM1
, DN0
}},
1199 { "udf10", 0xf9a000, 0xfffc00, 0, FMT_D1
, 0, {SIMM8
, DN0
}},
1200 { "udf10", 0xfba00000, 0xfffc0000, 0, FMT_D2
, 0, {SIMM16
, DN0
}},
1201 { "udf10", 0xfda00000, 0xfffc0000, 0, FMT_D4
, 0, {IMM32
, DN0
}},
1202 { "udf11", 0xf6b0, 0xfff0, 0, FMT_D0
, 0, {DM1
, DN0
}},
1203 { "udf11", 0xf9b000, 0xfffc00, 0, FMT_D1
, 0, {SIMM8
, DN0
}},
1204 { "udf11", 0xfbb00000, 0xfffc0000, 0, FMT_D2
, 0, {SIMM16
, DN0
}},
1205 { "udf11", 0xfdb00000, 0xfffc0000, 0, FMT_D4
, 0, {IMM32
, DN0
}},
1206 { "udf12", 0xf6c0, 0xfff0, 0, FMT_D0
, 0, {DM1
, DN0
}},
1207 { "udf12", 0xf9c000, 0xfffc00, 0, FMT_D1
, 0, {SIMM8
, DN0
}},
1208 { "udf12", 0xfbc00000, 0xfffc0000, 0, FMT_D2
, 0, {SIMM16
, DN0
}},
1209 { "udf12", 0xfdc00000, 0xfffc0000, 0, FMT_D4
, 0, {IMM32
, DN0
}},
1210 { "udf13", 0xf6d0, 0xfff0, 0, FMT_D0
, 0, {DM1
, DN0
}},
1211 { "udf13", 0xf9d000, 0xfffc00, 0, FMT_D1
, 0, {SIMM8
, DN0
}},
1212 { "udf13", 0xfbd00000, 0xfffc0000, 0, FMT_D2
, 0, {SIMM16
, DN0
}},
1213 { "udf13", 0xfdd00000, 0xfffc0000, 0, FMT_D4
, 0, {IMM32
, DN0
}},
1214 { "udf14", 0xf6e0, 0xfff0, 0, FMT_D0
, 0, {DM1
, DN0
}},
1215 { "udf14", 0xf9e000, 0xfffc00, 0, FMT_D1
, 0, {SIMM8
, DN0
}},
1216 { "udf14", 0xfbe00000, 0xfffc0000, 0, FMT_D2
, 0, {SIMM16
, DN0
}},
1217 { "udf14", 0xfde00000, 0xfffc0000, 0, FMT_D4
, 0, {IMM32
, DN0
}},
1218 { "udf15", 0xf6f0, 0xfff0, 0, FMT_D0
, 0, {DM1
, DN0
}},
1219 { "udf15", 0xf9f000, 0xfffc00, 0, FMT_D1
, 0, {SIMM8
, DN0
}},
1220 { "udf15", 0xfbf00000, 0xfffc0000, 0, FMT_D2
, 0, {SIMM16
, DN0
}},
1221 { "udf15", 0xfdf00000, 0xfffc0000, 0, FMT_D4
, 0, {IMM32
, DN0
}},
1222 { "udf20", 0xf500, 0xfff0, 0, FMT_D0
, 0, {DM1
, DN0
}},
1223 { "udf21", 0xf510, 0xfff0, 0, FMT_D0
, 0, {DM1
, DN0
}},
1224 { "udf22", 0xf520, 0xfff0, 0, FMT_D0
, 0, {DM1
, DN0
}},
1225 { "udf23", 0xf530, 0xfff0, 0, FMT_D0
, 0, {DM1
, DN0
}},
1226 { "udf24", 0xf540, 0xfff0, 0, FMT_D0
, 0, {DM1
, DN0
}},
1227 { "udf25", 0xf550, 0xfff0, 0, FMT_D0
, 0, {DM1
, DN0
}},
1228 { "udf26", 0xf560, 0xfff0, 0, FMT_D0
, 0, {DM1
, DN0
}},
1229 { "udf27", 0xf570, 0xfff0, 0, FMT_D0
, 0, {DM1
, DN0
}},
1230 { "udf28", 0xf580, 0xfff0, 0, FMT_D0
, 0, {DM1
, DN0
}},
1231 { "udf29", 0xf590, 0xfff0, 0, FMT_D0
, 0, {DM1
, DN0
}},
1232 { "udf30", 0xf5a0, 0xfff0, 0, FMT_D0
, 0, {DM1
, DN0
}},
1233 { "udf31", 0xf5b0, 0xfff0, 0, FMT_D0
, 0, {DM1
, DN0
}},
1234 { "udf32", 0xf5c0, 0xfff0, 0, FMT_D0
, 0, {DM1
, DN0
}},
1235 { "udf33", 0xf5d0, 0xfff0, 0, FMT_D0
, 0, {DM1
, DN0
}},
1236 { "udf34", 0xf5e0, 0xfff0, 0, FMT_D0
, 0, {DM1
, DN0
}},
1237 { "udf35", 0xf5f0, 0xfff0, 0, FMT_D0
, 0, {DM1
, DN0
}},
1238 { "udfu00", 0xf90400, 0xfffc00, 0, FMT_D1
, 0, {IMM8
, DN0
}},
1239 { "udfu00", 0xfb040000, 0xfffc0000, 0, FMT_D2
, 0, {IMM16
, DN0
}},
1240 { "udfu00", 0xfd040000, 0xfffc0000, 0, FMT_D4
, 0, {IMM32
, DN0
}},
1241 { "udfu01", 0xf91400, 0xfffc00, 0, FMT_D1
, 0, {IMM8
, DN0
}},
1242 { "udfu01", 0xfb140000, 0xfffc0000, 0, FMT_D2
, 0, {IMM16
, DN0
}},
1243 { "udfu01", 0xfd140000, 0xfffc0000, 0, FMT_D4
, 0, {IMM32
, DN0
}},
1244 { "udfu02", 0xf92400, 0xfffc00, 0, FMT_D1
, 0, {IMM8
, DN0
}},
1245 { "udfu02", 0xfb240000, 0xfffc0000, 0, FMT_D2
, 0, {IMM16
, DN0
}},
1246 { "udfu02", 0xfd240000, 0xfffc0000, 0, FMT_D4
, 0, {IMM32
, DN0
}},
1247 { "udfu03", 0xf93400, 0xfffc00, 0, FMT_D1
, 0, {IMM8
, DN0
}},
1248 { "udfu03", 0xfb340000, 0xfffc0000, 0, FMT_D2
, 0, {IMM16
, DN0
}},
1249 { "udfu03", 0xfd340000, 0xfffc0000, 0, FMT_D4
, 0, {IMM32
, DN0
}},
1250 { "udfu04", 0xf94400, 0xfffc00, 0, FMT_D1
, 0, {IMM8
, DN0
}},
1251 { "udfu04", 0xfb440000, 0xfffc0000, 0, FMT_D2
, 0, {IMM16
, DN0
}},
1252 { "udfu04", 0xfd440000, 0xfffc0000, 0, FMT_D4
, 0, {IMM32
, DN0
}},
1253 { "udfu05", 0xf95400, 0xfffc00, 0, FMT_D1
, 0, {IMM8
, DN0
}},
1254 { "udfu05", 0xfb540000, 0xfffc0000, 0, FMT_D2
, 0, {IMM16
, DN0
}},
1255 { "udfu05", 0xfd540000, 0xfffc0000, 0, FMT_D4
, 0, {IMM32
, DN0
}},
1256 { "udfu06", 0xf96400, 0xfffc00, 0, FMT_D1
, 0, {IMM8
, DN0
}},
1257 { "udfu06", 0xfb640000, 0xfffc0000, 0, FMT_D2
, 0, {IMM16
, DN0
}},
1258 { "udfu06", 0xfd640000, 0xfffc0000, 0, FMT_D4
, 0, {IMM32
, DN0
}},
1259 { "udfu07", 0xf97400, 0xfffc00, 0, FMT_D1
, 0, {IMM8
, DN0
}},
1260 { "udfu07", 0xfb740000, 0xfffc0000, 0, FMT_D2
, 0, {IMM16
, DN0
}},
1261 { "udfu07", 0xfd740000, 0xfffc0000, 0, FMT_D4
, 0, {IMM32
, DN0
}},
1262 { "udfu08", 0xf98400, 0xfffc00, 0, FMT_D1
, 0, {IMM8
, DN0
}},
1263 { "udfu08", 0xfb840000, 0xfffc0000, 0, FMT_D2
, 0, {IMM16
, DN0
}},
1264 { "udfu08", 0xfd840000, 0xfffc0000, 0, FMT_D4
, 0, {IMM32
, DN0
}},
1265 { "udfu09", 0xf99400, 0xfffc00, 0, FMT_D1
, 0, {IMM8
, DN0
}},
1266 { "udfu09", 0xfb940000, 0xfffc0000, 0, FMT_D2
, 0, {IMM16
, DN0
}},
1267 { "udfu09", 0xfd940000, 0xfffc0000, 0, FMT_D4
, 0, {IMM32
, DN0
}},
1268 { "udfu10", 0xf9a400, 0xfffc00, 0, FMT_D1
, 0, {IMM8
, DN0
}},
1269 { "udfu10", 0xfba40000, 0xfffc0000, 0, FMT_D2
, 0, {IMM16
, DN0
}},
1270 { "udfu10", 0xfda40000, 0xfffc0000, 0, FMT_D4
, 0, {IMM32
, DN0
}},
1271 { "udfu11", 0xf9b400, 0xfffc00, 0, FMT_D1
, 0, {IMM8
, DN0
}},
1272 { "udfu11", 0xfbb40000, 0xfffc0000, 0, FMT_D2
, 0, {IMM16
, DN0
}},
1273 { "udfu11", 0xfdb40000, 0xfffc0000, 0, FMT_D4
, 0, {IMM32
, DN0
}},
1274 { "udfu12", 0xf9c400, 0xfffc00, 0, FMT_D1
, 0, {IMM8
, DN0
}},
1275 { "udfu12", 0xfbc40000, 0xfffc0000, 0, FMT_D2
, 0, {IMM16
, DN0
}},
1276 { "udfu12", 0xfdc40000, 0xfffc0000, 0, FMT_D4
, 0, {IMM32
, DN0
}},
1277 { "udfu13", 0xf9d400, 0xfffc00, 0, FMT_D1
, 0, {IMM8
, DN0
}},
1278 { "udfu13", 0xfbd40000, 0xfffc0000, 0, FMT_D2
, 0, {IMM16
, DN0
}},
1279 { "udfu13", 0xfdd40000, 0xfffc0000, 0, FMT_D4
, 0, {IMM32
, DN0
}},
1280 { "udfu14", 0xf9e400, 0xfffc00, 0, FMT_D1
, 0, {IMM8
, DN0
}},
1281 { "udfu14", 0xfbe40000, 0xfffc0000, 0, FMT_D2
, 0, {IMM16
, DN0
}},
1282 { "udfu14", 0xfde40000, 0xfffc0000, 0, FMT_D4
, 0, {IMM32
, DN0
}},
1283 { "udfu15", 0xf9f400, 0xfffc00, 0, FMT_D1
, 0, {IMM8
, DN0
}},
1284 { "udfu15", 0xfbf40000, 0xfffc0000, 0, FMT_D2
, 0, {IMM16
, DN0
}},
1285 { "udfu15", 0xfdf40000, 0xfffc0000, 0, FMT_D4
, 0, {IMM32
, DN0
}},
1287 { "putx", 0xf500, 0xfff0, 0, FMT_D0
, AM30
, {DN01
}},
1288 { "getx", 0xf6f0, 0xfff0, 0, FMT_D0
, AM30
, {DN01
}},
1289 { "mulq", 0xf600, 0xfff0, 0, FMT_D0
, AM30
, {DM1
, DN0
}},
1290 { "mulq", 0xf90000, 0xfffc00, 0, FMT_D1
, AM30
, {SIMM8
, DN0
}},
1291 { "mulq", 0xfb000000, 0xfffc0000, 0, FMT_D2
, AM30
, {SIMM16
, DN0
}},
1292 { "mulq", 0xfd000000, 0xfffc0000, 0, FMT_D4
, AM30
, {IMM32
, DN0
}},
1293 { "mulqu", 0xf610, 0xfff0, 0, FMT_D0
, AM30
, {DM1
, DN0
}},
1294 { "mulqu", 0xf91400, 0xfffc00, 0, FMT_D1
, AM30
, {SIMM8
, DN0
}},
1295 { "mulqu", 0xfb140000, 0xfffc0000, 0, FMT_D2
, AM30
, {SIMM16
, DN0
}},
1296 { "mulqu", 0xfd140000, 0xfffc0000, 0, FMT_D4
, AM30
, {IMM32
, DN0
}},
1297 { "sat16", 0xf640, 0xfff0, 0, FMT_D0
, AM30
, {DM1
, DN0
}},
1298 { "sat16", 0xf9ab00, 0xffff00, 0, FMT_D6
, AM33
, {RM2
, RN0
}},
1300 { "sat24", 0xf650, 0xfff0, 0, FMT_D0
, AM30
, {DM1
, DN0
}},
1301 { "sat24", 0xfbaf0000, 0xffff00ff, 0, FMT_D7
, AM33
, {RM2
, RN0
}},
1303 { "bsch", 0xfbff0000, 0xffff000f, 0, FMT_D7
, AM33
, {RM2
, RN0
, RD2
}},
1304 { "bsch", 0xf670, 0xfff0, 0, FMT_D0
, AM30
, {DM1
, DN0
}},
1305 { "bsch", 0xf9fb00, 0xffff00, 0, FMT_D6
, AM33
, {RM2
, RN0
}},
1307 /* Extension. We need some instruction to trigger "emulated syscalls"
1308 for our simulator. */
1309 { "syscall", 0xf0e0, 0xfff0, 0, FMT_D0
, AM33
, {IMM4
}},
1310 { "syscall", 0xf0c0, 0xffff, 0, FMT_D0
, 0, {UNUSED
}},
1312 /* Extension. When talking to the simulator, gdb requires some instruction
1313 that will trigger a "breakpoint" (really just an instruction that isn't
1314 otherwise used by the tools. This instruction must be the same size
1315 as the smallest instruction on the target machine. In the case of the
1316 mn10x00 the "break" instruction must be one byte. 0xff is available on
1317 both mn10x00 architectures. */
1318 { "break", 0xff, 0xff, 0, FMT_S0
, 0, {UNUSED
}},
1320 { "add_add", 0xf7000000, 0xffff0000, 0xa, FMT_D10
, AM33
, {RM6
, RN4
, RM2
, RN0
}},
1321 { "add_add", 0xf7100000, 0xffff0000, 0xa, FMT_D10
, AM33
, {RM6
, RN4
, SIMM4_2
, RN0
}},
1322 { "add_add", 0xf7040000, 0xffff0000, 0xa, FMT_D10
, AM33
, {SIMM4_6
, RN4
, RM2
, RN0
}},
1323 { "add_add", 0xf7140000, 0xffff0000, 0xa, FMT_D10
, AM33
, {SIMM4_6
, RN4
, SIMM4_2
, RN0
}},
1324 { "add_sub", 0xf7200000, 0xffff0000, 0xa, FMT_D10
, AM33
, {RM6
, RN4
, RM2
, RN0
}},
1325 { "add_sub", 0xf7300000, 0xffff0000, 0xa, FMT_D10
, AM33
, {RM6
, RN4
, SIMM4_2
, RN0
}},
1326 { "add_sub", 0xf7240000, 0xffff0000, 0xa, FMT_D10
, AM33
, {SIMM4_6
, RN4
, RM2
, RN0
}},
1327 { "add_sub", 0xf7340000, 0xffff0000, 0xa, FMT_D10
, AM33
, {SIMM4_6
, RN4
, SIMM4_2
, RN0
}},
1328 { "add_cmp", 0xf7400000, 0xffff0000, 0x0, FMT_D10
, AM33
, {RM6
, RN4
, RM2
, RN0
}},
1329 { "add_cmp", 0xf7500000, 0xffff0000, 0x0, FMT_D10
, AM33
, {RM6
, RN4
, SIMM4_2
, RN0
}},
1330 { "add_cmp", 0xf7440000, 0xffff0000, 0x0, FMT_D10
, AM33
, {SIMM4_6
, RN4
, RM2
, RN0
}},
1331 { "add_cmp", 0xf7540000, 0xffff0000, 0x0, FMT_D10
, AM33
, {SIMM4_6
, RN4
, SIMM4_2
, RN0
}},
1332 { "add_mov", 0xf7600000, 0xffff0000, 0xa, FMT_D10
, AM33
, {RM6
, RN4
, RM2
, RN0
}},
1333 { "add_mov", 0xf7700000, 0xffff0000, 0xa, FMT_D10
, AM33
, {RM6
, RN4
, SIMM4_2
, RN0
}},
1334 { "add_mov", 0xf7640000, 0xffff0000, 0xa, FMT_D10
, AM33
, {SIMM4_6
, RN4
, RM2
, RN0
}},
1335 { "add_mov", 0xf7740000, 0xffff0000, 0xa, FMT_D10
, AM33
, {SIMM4_6
, RN4
, SIMM4_2
, RN0
}},
1336 { "add_asr", 0xf7800000, 0xffff0000, 0xa, FMT_D10
, AM33
, {RM6
, RN4
, RM2
, RN0
}},
1337 { "add_asr", 0xf7900000, 0xffff0000, 0xa, FMT_D10
, AM33
, {RM6
, RN4
, IMM4_2
, RN0
}},
1338 { "add_asr", 0xf7840000, 0xffff0000, 0xa, FMT_D10
, AM33
, {SIMM4_6
, RN4
, RM2
, RN0
}},
1339 { "add_asr", 0xf7940000, 0xffff0000, 0xa, FMT_D10
, AM33
, {SIMM4_6
, RN4
, IMM4_2
, RN0
}},
1340 { "add_lsr", 0xf7a00000, 0xffff0000, 0xa, FMT_D10
, AM33
, {RM6
, RN4
, RM2
, RN0
}},
1341 { "add_lsr", 0xf7b00000, 0xffff0000, 0xa, FMT_D10
, AM33
, {RM6
, RN4
, IMM4_2
, RN0
}},
1342 { "add_lsr", 0xf7a40000, 0xffff0000, 0xa, FMT_D10
, AM33
, {SIMM4_6
, RN4
, RM2
, RN0
}},
1343 { "add_lsr", 0xf7b40000, 0xffff0000, 0xa, FMT_D10
, AM33
, {SIMM4_6
, RN4
, IMM4_2
, RN0
}},
1344 { "add_asl", 0xf7c00000, 0xffff0000, 0xa, FMT_D10
, AM33
, {RM6
, RN4
, RM2
, RN0
}},
1345 { "add_asl", 0xf7d00000, 0xffff0000, 0xa, FMT_D10
, AM33
, {RM6
, RN4
, IMM4_2
, RN0
}},
1346 { "add_asl", 0xf7c40000, 0xffff0000, 0xa, FMT_D10
, AM33
, {SIMM4_6
, RN4
, RM2
, RN0
}},
1347 { "add_asl", 0xf7d40000, 0xffff0000, 0xa, FMT_D10
, AM33
, {SIMM4_6
, RN4
, IMM4_2
, RN0
}},
1348 { "cmp_add", 0xf7010000, 0xffff0000, 0x0, FMT_D10
, AM33
, {RM6
, RN4
, RM2
, RN0
}},
1349 { "cmp_add", 0xf7110000, 0xffff0000, 0x0, FMT_D10
, AM33
, {RM6
, RN4
, SIMM4_2
, RN0
}},
1350 { "cmp_add", 0xf7050000, 0xffff0000, 0x0, FMT_D10
, AM33
, {SIMM4_6
, RN4
, RM2
, RN0
}},
1351 { "cmp_add", 0xf7150000, 0xffff0000, 0x0, FMT_D10
, AM33
, {SIMM4_6
, RN4
, SIMM4_2
, RN0
}},
1352 { "cmp_sub", 0xf7210000, 0xffff0000, 0x0, FMT_D10
, AM33
, {RM6
, RN4
, RM2
, RN0
}},
1353 { "cmp_sub", 0xf7310000, 0xffff0000, 0x0, FMT_D10
, AM33
, {RM6
, RN4
, SIMM4_2
, RN0
}},
1354 { "cmp_sub", 0xf7250000, 0xffff0000, 0x0, FMT_D10
, AM33
, {SIMM4_6
, RN4
, RM2
, RN0
}},
1355 { "cmp_sub", 0xf7350000, 0xffff0000, 0x0, FMT_D10
, AM33
, {SIMM4_6
, RN4
, SIMM4_2
, RN0
}},
1356 { "cmp_mov", 0xf7610000, 0xffff0000, 0x0, FMT_D10
, AM33
, {RM6
, RN4
, RM2
, RN0
}},
1357 { "cmp_mov", 0xf7710000, 0xffff0000, 0x0, FMT_D10
, AM33
, {RM6
, RN4
, SIMM4_2
, RN0
}},
1358 { "cmp_mov", 0xf7650000, 0xffff0000, 0x0, FMT_D10
, AM33
, {SIMM4_6
, RN4
, RM2
, RN0
}},
1359 { "cmp_mov", 0xf7750000, 0xffff0000, 0x0, FMT_D10
, AM33
, {SIMM4_6
, RN4
, SIMM4_2
, RN0
}},
1360 { "cmp_asr", 0xf7810000, 0xffff0000, 0x0, FMT_D10
, AM33
, {RM6
, RN4
, RM2
, RN0
}},
1361 { "cmp_asr", 0xf7910000, 0xffff0000, 0x0, FMT_D10
, AM33
, {RM6
, RN4
, IMM4_2
, RN0
}},
1362 { "cmp_asr", 0xf7850000, 0xffff0000, 0x0, FMT_D10
, AM33
, {SIMM4_6
, RN4
, RM2
, RN0
}},
1363 { "cmp_asr", 0xf7950000, 0xffff0000, 0x0, FMT_D10
, AM33
, {SIMM4_6
, RN4
, IMM4_2
, RN0
}},
1364 { "cmp_lsr", 0xf7a10000, 0xffff0000, 0x0, FMT_D10
, AM33
, {RM6
, RN4
, RM2
, RN0
}},
1365 { "cmp_lsr", 0xf7b10000, 0xffff0000, 0x0, FMT_D10
, AM33
, {RM6
, RN4
, IMM4_2
, RN0
}},
1366 { "cmp_lsr", 0xf7a50000, 0xffff0000, 0x0, FMT_D10
, AM33
, {SIMM4_6
, RN4
, RM2
, RN0
}},
1367 { "cmp_lsr", 0xf7b50000, 0xffff0000, 0x0, FMT_D10
, AM33
, {SIMM4_6
, RN4
, IMM4_2
, RN0
}},
1368 { "cmp_asl", 0xf7c10000, 0xffff0000, 0x0, FMT_D10
, AM33
, {RM6
, RN4
, RM2
, RN0
}},
1369 { "cmp_asl", 0xf7d10000, 0xffff0000, 0x0, FMT_D10
, AM33
, {RM6
, RN4
, IMM4_2
, RN0
}},
1370 { "cmp_asl", 0xf7c50000, 0xffff0000, 0x0, FMT_D10
, AM33
, {SIMM4_6
, RN4
, RM2
, RN0
}},
1371 { "cmp_asl", 0xf7d50000, 0xffff0000, 0x0, FMT_D10
, AM33
, {SIMM4_6
, RN4
, IMM4_2
, RN0
}},
1372 { "sub_add", 0xf7020000, 0xffff0000, 0xa, FMT_D10
, AM33
, {RM6
, RN4
, RM2
, RN0
}},
1373 { "sub_add", 0xf7120000, 0xffff0000, 0xa, FMT_D10
, AM33
, {RM6
, RN4
, SIMM4_2
, RN0
}},
1374 { "sub_add", 0xf7060000, 0xffff0000, 0xa, FMT_D10
, AM33
, {SIMM4_6
, RN4
, RM2
, RN0
}},
1375 { "sub_add", 0xf7160000, 0xffff0000, 0xa, FMT_D10
, AM33
, {SIMM4_6
, RN4
, SIMM4_2
, RN0
}},
1376 { "sub_sub", 0xf7220000, 0xffff0000, 0xa, FMT_D10
, AM33
, {RM6
, RN4
, RM2
, RN0
}},
1377 { "sub_sub", 0xf7320000, 0xffff0000, 0xa, FMT_D10
, AM33
, {RM6
, RN4
, SIMM4_2
, RN0
}},
1378 { "sub_sub", 0xf7260000, 0xffff0000, 0xa, FMT_D10
, AM33
, {SIMM4_6
, RN4
, RM2
, RN0
}},
1379 { "sub_sub", 0xf7360000, 0xffff0000, 0xa, FMT_D10
, AM33
, {SIMM4_6
, RN4
, SIMM4_2
, RN0
}},
1380 { "sub_cmp", 0xf7420000, 0xffff0000, 0x0, FMT_D10
, AM33
, {RM6
, RN4
, RM2
, RN0
}},
1381 { "sub_cmp", 0xf7520000, 0xffff0000, 0x0, FMT_D10
, AM33
, {RM6
, RN4
, SIMM4_2
, RN0
}},
1382 { "sub_cmp", 0xf7460000, 0xffff0000, 0x0, FMT_D10
, AM33
, {SIMM4_6
, RN4
, RM2
, RN0
}},
1383 { "sub_cmp", 0xf7560000, 0xffff0000, 0x0, FMT_D10
, AM33
, {SIMM4_6
, RN4
, SIMM4_2
, RN0
}},
1384 { "sub_mov", 0xf7620000, 0xffff0000, 0xa, FMT_D10
, AM33
, {RM6
, RN4
, RM2
, RN0
}},
1385 { "sub_mov", 0xf7720000, 0xffff0000, 0xa, FMT_D10
, AM33
, {RM6
, RN4
, SIMM4_2
, RN0
}},
1386 { "sub_mov", 0xf7660000, 0xffff0000, 0xa, FMT_D10
, AM33
, {SIMM4_6
, RN4
, RM2
, RN0
}},
1387 { "sub_mov", 0xf7760000, 0xffff0000, 0xa, FMT_D10
, AM33
, {SIMM4_6
, RN4
, SIMM4_2
, RN0
}},
1388 { "sub_asr", 0xf7820000, 0xffff0000, 0xa, FMT_D10
, AM33
, {RM6
, RN4
, RM2
, RN0
}},
1389 { "sub_asr", 0xf7920000, 0xffff0000, 0xa, FMT_D10
, AM33
, {RM6
, RN4
, IMM4_2
, RN0
}},
1390 { "sub_asr", 0xf7860000, 0xffff0000, 0xa, FMT_D10
, AM33
, {SIMM4_6
, RN4
, RM2
, RN0
}},
1391 { "sub_asr", 0xf7960000, 0xffff0000, 0xa, FMT_D10
, AM33
, {SIMM4_6
, RN4
, IMM4_2
, RN0
}},
1392 { "sub_lsr", 0xf7a20000, 0xffff0000, 0xa, FMT_D10
, AM33
, {RM6
, RN4
, RM2
, RN0
}},
1393 { "sub_lsr", 0xf7b20000, 0xffff0000, 0xa, FMT_D10
, AM33
, {RM6
, RN4
, IMM4_2
, RN0
}},
1394 { "sub_lsr", 0xf7a60000, 0xffff0000, 0xa, FMT_D10
, AM33
, {SIMM4_6
, RN4
, RM2
, RN0
}},
1395 { "sub_lsr", 0xf7b60000, 0xffff0000, 0xa, FMT_D10
, AM33
, {SIMM4_6
, RN4
, IMM4_2
, RN0
}},
1396 { "sub_asl", 0xf7c20000, 0xffff0000, 0xa, FMT_D10
, AM33
, {RM6
, RN4
, RM2
, RN0
}},
1397 { "sub_asl", 0xf7d20000, 0xffff0000, 0xa, FMT_D10
, AM33
, {RM6
, RN4
, IMM4_2
, RN0
}},
1398 { "sub_asl", 0xf7c60000, 0xffff0000, 0xa, FMT_D10
, AM33
, {SIMM4_6
, RN4
, RM2
, RN0
}},
1399 { "sub_asl", 0xf7d60000, 0xffff0000, 0xa, FMT_D10
, AM33
, {SIMM4_6
, RN4
, IMM4_2
, RN0
}},
1400 { "mov_add", 0xf7030000, 0xffff0000, 0xa, FMT_D10
, AM33
, {RM6
, RN4
, RM2
, RN0
}},
1401 { "mov_add", 0xf7130000, 0xffff0000, 0xa, FMT_D10
, AM33
, {RM6
, RN4
, SIMM4_2
, RN0
}},
1402 { "mov_add", 0xf7070000, 0xffff0000, 0xa, FMT_D10
, AM33
, {SIMM4_6
, RN4
, RM2
, RN0
}},
1403 { "mov_add", 0xf7170000, 0xffff0000, 0xa, FMT_D10
, AM33
, {SIMM4_6
, RN4
, SIMM4_2
, RN0
}},
1404 { "mov_sub", 0xf7230000, 0xffff0000, 0xa, FMT_D10
, AM33
, {RM6
, RN4
, RM2
, RN0
}},
1405 { "mov_sub", 0xf7330000, 0xffff0000, 0xa, FMT_D10
, AM33
, {RM6
, RN4
, SIMM4_2
, RN0
}},
1406 { "mov_sub", 0xf7270000, 0xffff0000, 0xa, FMT_D10
, AM33
, {SIMM4_6
, RN4
, RM2
, RN0
}},
1407 { "mov_sub", 0xf7370000, 0xffff0000, 0xa, FMT_D10
, AM33
, {SIMM4_6
, RN4
, SIMM4_2
, RN0
}},
1408 { "mov_cmp", 0xf7430000, 0xffff0000, 0x0, FMT_D10
, AM33
, {RM6
, RN4
, RM2
, RN0
}},
1409 { "mov_cmp", 0xf7530000, 0xffff0000, 0x0, FMT_D10
, AM33
, {RM6
, RN4
, SIMM4_2
, RN0
}},
1410 { "mov_cmp", 0xf7470000, 0xffff0000, 0x0, FMT_D10
, AM33
, {SIMM4_6
, RN4
, RM2
, RN0
}},
1411 { "mov_cmp", 0xf7570000, 0xffff0000, 0x0, FMT_D10
, AM33
, {SIMM4_6
, RN4
, SIMM4_2
, RN0
}},
1412 { "mov_mov", 0xf7630000, 0xffff0000, 0xa, FMT_D10
, AM33
, {RM6
, RN4
, RM2
, RN0
}},
1413 { "mov_mov", 0xf7730000, 0xffff0000, 0xa, FMT_D10
, AM33
, {RM6
, RN4
, SIMM4_2
, RN0
}},
1414 { "mov_mov", 0xf7670000, 0xffff0000, 0xa, FMT_D10
, AM33
, {SIMM4_6
, RN4
, RM2
, RN0
}},
1415 { "mov_mov", 0xf7770000, 0xffff0000, 0xa, FMT_D10
, AM33
, {SIMM4_6
, RN4
, SIMM4_2
, RN0
}},
1416 { "mov_asr", 0xf7830000, 0xffff0000, 0xa, FMT_D10
, AM33
, {RM6
, RN4
, RM2
, RN0
}},
1417 { "mov_asr", 0xf7930000, 0xffff0000, 0xa, FMT_D10
, AM33
, {RM6
, RN4
, IMM4_2
, RN0
}},
1418 { "mov_asr", 0xf7870000, 0xffff0000, 0xa, FMT_D10
, AM33
, {SIMM4_6
, RN4
, RM2
, RN0
}},
1419 { "mov_asr", 0xf7970000, 0xffff0000, 0xa, FMT_D10
, AM33
, {SIMM4_6
, RN4
, IMM4_2
, RN0
}},
1420 { "mov_lsr", 0xf7a30000, 0xffff0000, 0xa, FMT_D10
, AM33
, {RM6
, RN4
, RM2
, RN0
}},
1421 { "mov_lsr", 0xf7b30000, 0xffff0000, 0xa, FMT_D10
, AM33
, {RM6
, RN4
, IMM4_2
, RN0
}},
1422 { "mov_lsr", 0xf7a70000, 0xffff0000, 0xa, FMT_D10
, AM33
, {SIMM4_6
, RN4
, RM2
, RN0
}},
1423 { "mov_lsr", 0xf7b70000, 0xffff0000, 0xa, FMT_D10
, AM33
, {SIMM4_6
, RN4
, IMM4_2
, RN0
}},
1424 { "mov_asl", 0xf7c30000, 0xffff0000, 0xa, FMT_D10
, AM33
, {RM6
, RN4
, RM2
, RN0
}},
1425 { "mov_asl", 0xf7d30000, 0xffff0000, 0xa, FMT_D10
, AM33
, {RM6
, RN4
, IMM4_2
, RN0
}},
1426 { "mov_asl", 0xf7c70000, 0xffff0000, 0xa, FMT_D10
, AM33
, {SIMM4_6
, RN4
, RM2
, RN0
}},
1427 { "mov_asl", 0xf7d70000, 0xffff0000, 0xa, FMT_D10
, AM33
, {SIMM4_6
, RN4
, IMM4_2
, RN0
}},
1428 { "and_add", 0xf7080000, 0xffff0000, 0xa, FMT_D10
, AM33
, {RM6
, RN4
, RM2
, RN0
}},
1429 { "and_add", 0xf7180000, 0xffff0000, 0xa, FMT_D10
, AM33
, {RM6
, RN4
, SIMM4_2
, RN0
}},
1430 { "and_sub", 0xf7280000, 0xffff0000, 0xa, FMT_D10
, AM33
, {RM6
, RN4
, RM2
, RN0
}},
1431 { "and_sub", 0xf7380000, 0xffff0000, 0xa, FMT_D10
, AM33
, {RM6
, RN4
, SIMM4_2
, RN0
}},
1432 { "and_cmp", 0xf7480000, 0xffff0000, 0x0, FMT_D10
, AM33
, {RM6
, RN4
, RM2
, RN0
}},
1433 { "and_cmp", 0xf7580000, 0xffff0000, 0x0, FMT_D10
, AM33
, {RM6
, RN4
, SIMM4_2
, RN0
}},
1434 { "and_mov", 0xf7680000, 0xffff0000, 0xa, FMT_D10
, AM33
, {RM6
, RN4
, RM2
, RN0
}},
1435 { "and_mov", 0xf7780000, 0xffff0000, 0xa, FMT_D10
, AM33
, {RM6
, RN4
, SIMM4_2
, RN0
}},
1436 { "and_asr", 0xf7880000, 0xffff0000, 0xa, FMT_D10
, AM33
, {RM6
, RN4
, RM2
, RN0
}},
1437 { "and_asr", 0xf7980000, 0xffff0000, 0xa, FMT_D10
, AM33
, {RM6
, RN4
, IMM4_2
, RN0
}},
1438 { "and_lsr", 0xf7a80000, 0xffff0000, 0xa, FMT_D10
, AM33
, {RM6
, RN4
, RM2
, RN0
}},
1439 { "and_lsr", 0xf7b80000, 0xffff0000, 0xa, FMT_D10
, AM33
, {RM6
, RN4
, IMM4_2
, RN0
}},
1440 { "and_asl", 0xf7c80000, 0xffff0000, 0xa, FMT_D10
, AM33
, {RM6
, RN4
, RM2
, RN0
}},
1441 { "and_asl", 0xf7d80000, 0xffff0000, 0xa, FMT_D10
, AM33
, {RM6
, RN4
, IMM4_2
, RN0
}},
1442 { "dmach_add", 0xf7090000, 0xffff0000, 0x0, FMT_D10
, AM33
, {RM6
, RN4
, RM2
, RN0
}},
1443 { "dmach_add", 0xf7190000, 0xffff0000, 0x0, FMT_D10
, AM33
, {RM6
, RN4
, SIMM4_2
, RN0
}},
1444 { "dmach_sub", 0xf7290000, 0xffff0000, 0x0, FMT_D10
, AM33
, {RM6
, RN4
, RM2
, RN0
}},
1445 { "dmach_sub", 0xf7390000, 0xffff0000, 0x0, FMT_D10
, AM33
, {RM6
, RN4
, SIMM4_2
, RN0
}},
1446 { "dmach_cmp", 0xf7490000, 0xffff0000, 0x0, FMT_D10
, AM33
, {RM6
, RN4
, RM2
, RN0
}},
1447 { "dmach_cmp", 0xf7590000, 0xffff0000, 0x0, FMT_D10
, AM33
, {RM6
, RN4
, SIMM4_2
, RN0
}},
1448 { "dmach_mov", 0xf7690000, 0xffff0000, 0x0, FMT_D10
, AM33
, {RM6
, RN4
, RM2
, RN0
}},
1449 { "dmach_mov", 0xf7790000, 0xffff0000, 0x0, FMT_D10
, AM33
, {RM6
, RN4
, SIMM4_2
, RN0
}},
1450 { "dmach_asr", 0xf7890000, 0xffff0000, 0x0, FMT_D10
, AM33
, {RM6
, RN4
, RM2
, RN0
}},
1451 { "dmach_asr", 0xf7990000, 0xffff0000, 0x0, FMT_D10
, AM33
, {RM6
, RN4
, IMM4_2
, RN0
}},
1452 { "dmach_lsr", 0xf7a90000, 0xffff0000, 0x0, FMT_D10
, AM33
, {RM6
, RN4
, RM2
, RN0
}},
1453 { "dmach_lsr", 0xf7b90000, 0xffff0000, 0x0, FMT_D10
, AM33
, {RM6
, RN4
, IMM4_2
, RN0
}},
1454 { "dmach_asl", 0xf7c90000, 0xffff0000, 0x0, FMT_D10
, AM33
, {RM6
, RN4
, RM2
, RN0
}},
1455 { "dmach_asl", 0xf7d90000, 0xffff0000, 0x0, FMT_D10
, AM33
, {RM6
, RN4
, IMM4_2
, RN0
}},
1456 { "xor_add", 0xf70a0000, 0xffff0000, 0xa, FMT_D10
, AM33
, {RM6
, RN4
, RM2
, RN0
}},
1457 { "xor_add", 0xf71a0000, 0xffff0000, 0xa, FMT_D10
, AM33
, {RM6
, RN4
, SIMM4_2
, RN0
}},
1458 { "xor_sub", 0xf72a0000, 0xffff0000, 0xa, FMT_D10
, AM33
, {RM6
, RN4
, RM2
, RN0
}},
1459 { "xor_sub", 0xf73a0000, 0xffff0000, 0xa, FMT_D10
, AM33
, {RM6
, RN4
, SIMM4_2
, RN0
}},
1460 { "xor_cmp", 0xf74a0000, 0xffff0000, 0x0, FMT_D10
, AM33
, {RM6
, RN4
, RM2
, RN0
}},
1461 { "xor_cmp", 0xf75a0000, 0xffff0000, 0x0, FMT_D10
, AM33
, {RM6
, RN4
, SIMM4_2
, RN0
}},
1462 { "xor_mov", 0xf76a0000, 0xffff0000, 0xa, FMT_D10
, AM33
, {RM6
, RN4
, RM2
, RN0
}},
1463 { "xor_mov", 0xf77a0000, 0xffff0000, 0xa, FMT_D10
, AM33
, {RM6
, RN4
, SIMM4_2
, RN0
}},
1464 { "xor_asr", 0xf78a0000, 0xffff0000, 0xa, FMT_D10
, AM33
, {RM6
, RN4
, RM2
, RN0
}},
1465 { "xor_asr", 0xf79a0000, 0xffff0000, 0xa, FMT_D10
, AM33
, {RM6
, RN4
, IMM4_2
, RN0
}},
1466 { "xor_lsr", 0xf7aa0000, 0xffff0000, 0xa, FMT_D10
, AM33
, {RM6
, RN4
, RM2
, RN0
}},
1467 { "xor_lsr", 0xf7ba0000, 0xffff0000, 0xa, FMT_D10
, AM33
, {RM6
, RN4
, IMM4_2
, RN0
}},
1468 { "xor_asl", 0xf7ca0000, 0xffff0000, 0xa, FMT_D10
, AM33
, {RM6
, RN4
, RM2
, RN0
}},
1469 { "xor_asl", 0xf7da0000, 0xffff0000, 0xa, FMT_D10
, AM33
, {RM6
, RN4
, IMM4_2
, RN0
}},
1470 { "swhw_add", 0xf70b0000, 0xffff0000, 0xa, FMT_D10
, AM33
, {RM6
, RN4
, RM2
, RN0
}},
1471 { "swhw_add", 0xf71b0000, 0xffff0000, 0xa, FMT_D10
, AM33
, {RM6
, RN4
, SIMM4_2
, RN0
}},
1472 { "swhw_sub", 0xf72b0000, 0xffff0000, 0xa, FMT_D10
, AM33
, {RM6
, RN4
, RM2
, RN0
}},
1473 { "swhw_sub", 0xf73b0000, 0xffff0000, 0xa, FMT_D10
, AM33
, {RM6
, RN4
, SIMM4_2
, RN0
}},
1474 { "swhw_cmp", 0xf74b0000, 0xffff0000, 0x0, FMT_D10
, AM33
, {RM6
, RN4
, RM2
, RN0
}},
1475 { "swhw_cmp", 0xf75b0000, 0xffff0000, 0x0, FMT_D10
, AM33
, {RM6
, RN4
, SIMM4_2
, RN0
}},
1476 { "swhw_mov", 0xf76b0000, 0xffff0000, 0xa, FMT_D10
, AM33
, {RM6
, RN4
, RM2
, RN0
}},
1477 { "swhw_mov", 0xf77b0000, 0xffff0000, 0xa, FMT_D10
, AM33
, {RM6
, RN4
, SIMM4_2
, RN0
}},
1478 { "swhw_asr", 0xf78b0000, 0xffff0000, 0xa, FMT_D10
, AM33
, {RM6
, RN4
, RM2
, RN0
}},
1479 { "swhw_asr", 0xf79b0000, 0xffff0000, 0xa, FMT_D10
, AM33
, {RM6
, RN4
, IMM4_2
, RN0
}},
1480 { "swhw_lsr", 0xf7ab0000, 0xffff0000, 0xa, FMT_D10
, AM33
, {RM6
, RN4
, RM2
, RN0
}},
1481 { "swhw_lsr", 0xf7bb0000, 0xffff0000, 0xa, FMT_D10
, AM33
, {RM6
, RN4
, IMM4_2
, RN0
}},
1482 { "swhw_asl", 0xf7cb0000, 0xffff0000, 0xa, FMT_D10
, AM33
, {RM6
, RN4
, RM2
, RN0
}},
1483 { "swhw_asl", 0xf7db0000, 0xffff0000, 0xa, FMT_D10
, AM33
, {RM6
, RN4
, IMM4_2
, RN0
}},
1484 { "or_add", 0xf70c0000, 0xffff0000, 0xa, FMT_D10
, AM33
, {RM6
, RN4
, RM2
, RN0
}},
1485 { "or_add", 0xf71c0000, 0xffff0000, 0xa, FMT_D10
, AM33
, {RM6
, RN4
, SIMM4_2
, RN0
}},
1486 { "or_sub", 0xf72c0000, 0xffff0000, 0xa, FMT_D10
, AM33
, {RM6
, RN4
, RM2
, RN0
}},
1487 { "or_sub", 0xf73c0000, 0xffff0000, 0xa, FMT_D10
, AM33
, {RM6
, RN4
, SIMM4_2
, RN0
}},
1488 { "or_cmp", 0xf74c0000, 0xffff0000, 0x0, FMT_D10
, AM33
, {RM6
, RN4
, RM2
, RN0
}},
1489 { "or_cmp", 0xf75c0000, 0xffff0000, 0x0, FMT_D10
, AM33
, {RM6
, RN4
, SIMM4_2
, RN0
}},
1490 { "or_mov", 0xf76c0000, 0xffff0000, 0xa, FMT_D10
, AM33
, {RM6
, RN4
, RM2
, RN0
}},
1491 { "or_mov", 0xf77c0000, 0xffff0000, 0xa, FMT_D10
, AM33
, {RM6
, RN4
, SIMM4_2
, RN0
}},
1492 { "or_asr", 0xf78c0000, 0xffff0000, 0xa, FMT_D10
, AM33
, {RM6
, RN4
, RM2
, RN0
}},
1493 { "or_asr", 0xf79c0000, 0xffff0000, 0xa, FMT_D10
, AM33
, {RM6
, RN4
, IMM4_2
, RN0
}},
1494 { "or_lsr", 0xf7ac0000, 0xffff0000, 0xa, FMT_D10
, AM33
, {RM6
, RN4
, RM2
, RN0
}},
1495 { "or_lsr", 0xf7bc0000, 0xffff0000, 0xa, FMT_D10
, AM33
, {RM6
, RN4
, IMM4_2
, RN0
}},
1496 { "or_asl", 0xf7cc0000, 0xffff0000, 0xa, FMT_D10
, AM33
, {RM6
, RN4
, RM2
, RN0
}},
1497 { "or_asl", 0xf7dc0000, 0xffff0000, 0xa, FMT_D10
, AM33
, {RM6
, RN4
, IMM4_2
, RN0
}},
1498 { "sat16_add", 0xf70d0000, 0xffff0000, 0xa, FMT_D10
, AM33
, {RM6
, RN4
, RM2
, RN0
}},
1499 { "sat16_add", 0xf71d0000, 0xffff0000, 0xa, FMT_D10
, AM33
, {RM6
, RN4
, SIMM4_2
, RN0
}},
1500 { "sat16_sub", 0xf72d0000, 0xffff0000, 0xa, FMT_D10
, AM33
, {RM6
, RN4
, RM2
, RN0
}},
1501 { "sat16_sub", 0xf73d0000, 0xffff0000, 0xa, FMT_D10
, AM33
, {RM6
, RN4
, SIMM4_2
, RN0
}},
1502 { "sat16_cmp", 0xf74d0000, 0xffff0000, 0x0, FMT_D10
, AM33
, {RM6
, RN4
, RM2
, RN0
}},
1503 { "sat16_cmp", 0xf75d0000, 0xffff0000, 0x0, FMT_D10
, AM33
, {RM6
, RN4
, SIMM4_2
, RN0
}},
1504 { "sat16_mov", 0xf76d0000, 0xffff0000, 0xa, FMT_D10
, AM33
, {RM6
, RN4
, RM2
, RN0
}},
1505 { "sat16_mov", 0xf77d0000, 0xffff0000, 0xa, FMT_D10
, AM33
, {RM6
, RN4
, SIMM4_2
, RN0
}},
1506 { "sat16_asr", 0xf78d0000, 0xffff0000, 0xa, FMT_D10
, AM33
, {RM6
, RN4
, RM2
, RN0
}},
1507 { "sat16_asr", 0xf79d0000, 0xffff0000, 0xa, FMT_D10
, AM33
, {RM6
, RN4
, IMM4_2
, RN0
}},
1508 { "sat16_lsr", 0xf7ad0000, 0xffff0000, 0xa, FMT_D10
, AM33
, {RM6
, RN4
, RM2
, RN0
}},
1509 { "sat16_lsr", 0xf7bd0000, 0xffff0000, 0xa, FMT_D10
, AM33
, {RM6
, RN4
, IMM4_2
, RN0
}},
1510 { "sat16_asl", 0xf7cd0000, 0xffff0000, 0xa, FMT_D10
, AM33
, {RM6
, RN4
, RM2
, RN0
}},
1511 { "sat16_asl", 0xf7dd0000, 0xffff0000, 0xa, FMT_D10
, AM33
, {RM6
, RN4
, IMM4_2
, RN0
}},
1512 /* Ugh. Synthetic instructions. */
1513 { "add_and", 0xf7080000, 0xffff0000, 0xa, FMT_D10
, AM33
, {RM2
, RN0
, RM6
, RN4
}},
1514 { "add_and", 0xf7180000, 0xffff0000, 0xa, FMT_D10
, AM33
, {SIMM4_2
, RN0
, RM6
, RN4
}},
1515 { "add_dmach", 0xf7090000, 0xffff0000, 0x0, FMT_D10
, AM33
, {RM2
, RN0
, RM6
, RN4
}},
1516 { "add_dmach", 0xf7190000, 0xffff0000, 0x0, FMT_D10
, AM33
, {SIMM4_2
, RN0
, RM6
, RN4
}},
1517 { "add_or", 0xf70c0000, 0xffff0000, 0xa, FMT_D10
, AM33
, {RM2
, RN0
, RM6
, RN4
}},
1518 { "add_or", 0xf71c0000, 0xffff0000, 0xa, FMT_D10
, AM33
, {SIMM4_2
, RN0
, RM6
, RN4
}},
1519 { "add_sat16", 0xf70d0000, 0xffff0000, 0xa, FMT_D10
, AM33
, {RM2
, RN0
, RM6
, RN4
}},
1520 { "add_sat16", 0xf71d0000, 0xffff0000, 0xa, FMT_D10
, AM33
, {SIMM4_2
, RN0
, RM6
, RN4
}},
1521 { "add_swhw", 0xf70b0000, 0xffff0000, 0xa, FMT_D10
, AM33
, {RM2
, RN0
, RM6
, RN4
}},
1522 { "add_swhw", 0xf71b0000, 0xffff0000, 0xa, FMT_D10
, AM33
, {SIMM4_2
, RN0
, RM6
, RN4
}},
1523 { "add_xor", 0xf70a0000, 0xffff0000, 0xa, FMT_D10
, AM33
, {RM2
, RN0
, RM6
, RN4
}},
1524 { "add_xor", 0xf71a0000, 0xffff0000, 0xa, FMT_D10
, AM33
, {SIMM4_2
, RN0
, RM6
, RN4
}},
1525 { "asl_add", 0xf7c00000, 0xffff0000, 0xa, FMT_D10
, AM33
, {RM2
, RN0
, RM6
, RN4
}},
1526 { "asl_add", 0xf7d00000, 0xffff0000, 0xa, FMT_D10
, AM33
, {IMM4_2
, RN0
, RM6
, RN4
}},
1527 { "asl_add", 0xf7c40000, 0xffff0000, 0xa, FMT_D10
, AM33
, {RM2
, RN0
, SIMM4_6
, RN4
}},
1528 { "asl_add", 0xf7d40000, 0xffff0000, 0xa, FMT_D10
, AM33
, {IMM4_2
, RN0
, SIMM4_6
, RN4
}},
1529 { "asl_and", 0xf7c80000, 0xffff0000, 0xa, FMT_D10
, AM33
, {RM2
, RN0
, RM6
, RN4
}},
1530 { "asl_and", 0xf7d80000, 0xffff0000, 0xa, FMT_D10
, AM33
, {IMM4_2
, RN0
, RM6
, RN4
}},
1531 { "asl_cmp", 0xf7c10000, 0xffff0000, 0x0, FMT_D10
, AM33
, {RM2
, RN0
, RM6
, RN4
}},
1532 { "asl_cmp", 0xf7d10000, 0xffff0000, 0x0, FMT_D10
, AM33
, {IMM4_2
, RN0
, RM6
, RN4
, }},
1533 { "asl_cmp", 0xf7c50000, 0xffff0000, 0x0, FMT_D10
, AM33
, {RM2
, RN0
, SIMM4_6
, RN4
}},
1534 { "asl_cmp", 0xf7d50000, 0xffff0000, 0x0, FMT_D10
, AM33
, {IMM4_2
, RN0
, SIMM4_6
, RN4
}},
1535 { "asl_dmach", 0xf7c90000, 0xffff0000, 0x0, FMT_D10
, AM33
, {RM2
, RN0
, RM6
, RN4
}},
1536 { "asl_dmach", 0xf7d90000, 0xffff0000, 0x0, FMT_D10
, AM33
, {IMM4_2
, RN0
, RM6
, RN4
}},
1537 { "asl_mov", 0xf7c30000, 0xffff0000, 0xa, FMT_D10
, AM33
, {RM2
, RN0
, RM6
, RN4
}},
1538 { "asl_mov", 0xf7d30000, 0xffff0000, 0xa, FMT_D10
, AM33
, {IMM4_2
, RN0
, RM6
, RN4
}},
1539 { "asl_mov", 0xf7c70000, 0xffff0000, 0xa, FMT_D10
, AM33
, {RM2
, RN0
, SIMM4_6
, RN4
}},
1540 { "asl_mov", 0xf7d70000, 0xffff0000, 0xa, FMT_D10
, AM33
, {IMM4_2
, RN0
, SIMM4_6
, RN4
}},
1541 { "asl_or", 0xf7cc0000, 0xffff0000, 0xa, FMT_D10
, AM33
, {RM2
, RN0
, RM6
, RN4
}},
1542 { "asl_or", 0xf7dc0000, 0xffff0000, 0xa, FMT_D10
, AM33
, {IMM4_2
, RN0
, RM6
, RN4
}},
1543 { "asl_sat16", 0xf7cd0000, 0xffff0000, 0xa, FMT_D10
, AM33
, {RM2
, RN0
, RM6
, RN4
}},
1544 { "asl_sat16", 0xf7dd0000, 0xffff0000, 0xa, FMT_D10
, AM33
, {IMM4_2
, RN0
, RM6
, RN4
}},
1545 { "asl_sub", 0xf7c20000, 0xffff0000, 0xa, FMT_D10
, AM33
, {RM2
, RN0
, RM6
, RN4
}},
1546 { "asl_sub", 0xf7d20000, 0xffff0000, 0xa, FMT_D10
, AM33
, {IMM4_2
, RN0
, RM6
, RN4
}},
1547 { "asl_sub", 0xf7c60000, 0xffff0000, 0xa, FMT_D10
, AM33
, {RM2
, RN0
, SIMM4_6
, RN4
}},
1548 { "asl_sub", 0xf7d60000, 0xffff0000, 0xa, FMT_D10
, AM33
, {IMM4_2
, RN0
, SIMM4_6
, RN4
}},
1549 { "asl_swhw", 0xf7cb0000, 0xffff0000, 0xa, FMT_D10
, AM33
, {RM2
, RN0
, RM6
, RN4
}},
1550 { "asl_swhw", 0xf7db0000, 0xffff0000, 0xa, FMT_D10
, AM33
, {IMM4_2
, RN0
, RM6
, RN4
}},
1551 { "asl_xor", 0xf7ca0000, 0xffff0000, 0xa, FMT_D10
, AM33
, {RM2
, RN0
, RM6
, RN4
}},
1552 { "asl_xor", 0xf7da0000, 0xffff0000, 0xa, FMT_D10
, AM33
, {IMM4_2
, RN0
, RM6
, RN4
}},
1553 { "asr_add", 0xf7800000, 0xffff0000, 0xa, FMT_D10
, AM33
, {RM2
, RN0
, RM6
, RN4
}},
1554 { "asr_add", 0xf7900000, 0xffff0000, 0xa, FMT_D10
, AM33
, {IMM4_2
, RN0
, RM6
, RN4
}},
1555 { "asr_add", 0xf7840000, 0xffff0000, 0xa, FMT_D10
, AM33
, {RM2
, RN0
, SIMM4_6
, RN4
}},
1556 { "asr_add", 0xf7940000, 0xffff0000, 0xa, FMT_D10
, AM33
, {IMM4_2
, RN0
, SIMM4_6
, RN4
}},
1557 { "asr_and", 0xf7880000, 0xffff0000, 0xa, FMT_D10
, AM33
, {RM2
, RN0
, RM6
, RN4
}},
1558 { "asr_and", 0xf7980000, 0xffff0000, 0xa, FMT_D10
, AM33
, {IMM4_2
, RN0
, RM6
, RN4
}},
1559 { "asr_cmp", 0xf7810000, 0xffff0000, 0x0, FMT_D10
, AM33
, {RM2
, RN0
, RM6
, RN4
}},
1560 { "asr_cmp", 0xf7910000, 0xffff0000, 0x0, FMT_D10
, AM33
, {IMM4_2
, RN0
, RM6
, RN4
, }},
1561 { "asr_cmp", 0xf7850000, 0xffff0000, 0x0, FMT_D10
, AM33
, {RM2
, RN0
, SIMM4_6
, RN4
}},
1562 { "asr_cmp", 0xf7950000, 0xffff0000, 0x0, FMT_D10
, AM33
, {IMM4_2
, RN0
, SIMM4_6
, RN4
}},
1563 { "asr_dmach", 0xf7890000, 0xffff0000, 0x0, FMT_D10
, AM33
, {RM2
, RN0
, RM6
, RN4
}},
1564 { "asr_dmach", 0xf7990000, 0xffff0000, 0x0, FMT_D10
, AM33
, {IMM4_2
, RN0
, RM6
, RN4
}},
1565 { "asr_mov", 0xf7830000, 0xffff0000, 0xa, FMT_D10
, AM33
, {RM2
, RN0
, RM6
, RN4
}},
1566 { "asr_mov", 0xf7930000, 0xffff0000, 0xa, FMT_D10
, AM33
, {IMM4_2
, RN0
, RM6
, RN4
}},
1567 { "asr_mov", 0xf7870000, 0xffff0000, 0xa, FMT_D10
, AM33
, {RM2
, RN0
, SIMM4_6
, RN4
}},
1568 { "asr_mov", 0xf7970000, 0xffff0000, 0xa, FMT_D10
, AM33
, {IMM4_2
, RN0
, SIMM4_6
, RN4
}},
1569 { "asr_or", 0xf78c0000, 0xffff0000, 0xa, FMT_D10
, AM33
, {RM2
, RN0
, RM6
, RN4
}},
1570 { "asr_or", 0xf79c0000, 0xffff0000, 0xa, FMT_D10
, AM33
, {IMM4_2
, RN0
, RM6
, RN4
}},
1571 { "asr_sat16", 0xf78d0000, 0xffff0000, 0xa, FMT_D10
, AM33
, {RM2
, RN0
, RM6
, RN4
}},
1572 { "asr_sat16", 0xf79d0000, 0xffff0000, 0xa, FMT_D10
, AM33
, {IMM4_2
, RN0
, RM6
, RN4
}},
1573 { "asr_sub", 0xf7820000, 0xffff0000, 0xa, FMT_D10
, AM33
, {RM2
, RN0
, RM6
, RN4
}},
1574 { "asr_sub", 0xf7920000, 0xffff0000, 0xa, FMT_D10
, AM33
, {IMM4_2
, RN0
, RM6
, RN4
}},
1575 { "asr_sub", 0xf7860000, 0xffff0000, 0xa, FMT_D10
, AM33
, {RM2
, RN0
, SIMM4_6
, RN4
}},
1576 { "asr_sub", 0xf7960000, 0xffff0000, 0xa, FMT_D10
, AM33
, {IMM4_2
, RN0
, SIMM4_6
, RN4
}},
1577 { "asr_swhw", 0xf78b0000, 0xffff0000, 0xa, FMT_D10
, AM33
, {RM2
, RN0
, RM6
, RN4
}},
1578 { "asr_swhw", 0xf79b0000, 0xffff0000, 0xa, FMT_D10
, AM33
, {IMM4_2
, RN0
, RM6
, RN4
}},
1579 { "asr_xor", 0xf78a0000, 0xffff0000, 0xa, FMT_D10
, AM33
, {RM2
, RN0
, RM6
, RN4
}},
1580 { "asr_xor", 0xf79a0000, 0xffff0000, 0xa, FMT_D10
, AM33
, {IMM4_2
, RN0
, RM6
, RN4
}},
1581 { "cmp_and", 0xf7480000, 0xffff0000, 0x0, FMT_D10
, AM33
, {RM2
, RN0
, RM6
, RN4
}},
1582 { "cmp_and", 0xf7580000, 0xffff0000, 0x0, FMT_D10
, AM33
, {SIMM4_2
, RN0
, RM6
, RN4
}},
1583 { "cmp_dmach", 0xf7490000, 0xffff0000, 0x0, FMT_D10
, AM33
, {RM2
, RN0
, RM6
, RN4
}},
1584 { "cmp_dmach", 0xf7590000, 0xffff0000, 0x0, FMT_D10
, AM33
, {SIMM4_2
, RN0
, RM6
, RN4
}},
1585 { "cmp_or", 0xf74c0000, 0xffff0000, 0x0, FMT_D10
, AM33
, {RM2
, RN0
, RM6
, RN4
}},
1586 { "cmp_or", 0xf75c0000, 0xffff0000, 0x0, FMT_D10
, AM33
, {SIMM4_2
, RN0
, RM6
, RN4
}},
1587 { "cmp_sat16", 0xf74d0000, 0xffff0000, 0x0, FMT_D10
, AM33
, {RM2
, RN0
, RM6
, RN4
}},
1588 { "cmp_sat16", 0xf75d0000, 0xffff0000, 0x0, FMT_D10
, AM33
, {SIMM4_2
, RN0
, RM6
, RN4
}},
1589 { "cmp_swhw", 0xf74b0000, 0xffff0000, 0x0, FMT_D10
, AM33
, {RM2
, RN0
, RM6
, RN4
}},
1590 { "cmp_swhw", 0xf75b0000, 0xffff0000, 0x0, FMT_D10
, AM33
, {SIMM4_2
, RN0
, RM6
, RN4
}},
1591 { "cmp_xor", 0xf74a0000, 0xffff0000, 0x0, FMT_D10
, AM33
, {RM2
, RN0
, RM6
, RN4
}},
1592 { "cmp_xor", 0xf75a0000, 0xffff0000, 0x0, FMT_D10
, AM33
, {SIMM4_2
, RN0
, RM6
, RN4
}},
1593 { "lsr_add", 0xf7a00000, 0xffff0000, 0xa, FMT_D10
, AM33
, {RM2
, RN0
, RM6
, RN4
}},
1594 { "lsr_add", 0xf7b00000, 0xffff0000, 0xa, FMT_D10
, AM33
, {IMM4_2
, RN0
, RM6
, RN4
}},
1595 { "lsr_add", 0xf7a40000, 0xffff0000, 0xa, FMT_D10
, AM33
, {RM2
, RN0
, SIMM4_6
, RN4
}},
1596 { "lsr_add", 0xf7b40000, 0xffff0000, 0xa, FMT_D10
, AM33
, {IMM4_2
, RN0
, SIMM4_6
, RN4
}},
1597 { "lsr_and", 0xf7a80000, 0xffff0000, 0xa, FMT_D10
, AM33
, {RM2
, RN0
, RM6
, RN4
}},
1598 { "lsr_and", 0xf7b80000, 0xffff0000, 0xa, FMT_D10
, AM33
, {IMM4_2
, RN0
, RM6
, RN4
}},
1599 { "lsr_cmp", 0xf7a10000, 0xffff0000, 0x0, FMT_D10
, AM33
, {RM2
, RN0
, RM6
, RN4
}},
1600 { "lsr_cmp", 0xf7b10000, 0xffff0000, 0x0, FMT_D10
, AM33
, {IMM4_2
, RN0
, RM6
, RN4
, }},
1601 { "lsr_cmp", 0xf7a50000, 0xffff0000, 0x0, FMT_D10
, AM33
, {RM2
, RN0
, SIMM4_6
, RN4
}},
1602 { "lsr_cmp", 0xf7b50000, 0xffff0000, 0x0, FMT_D10
, AM33
, {IMM4_2
, RN0
, SIMM4_6
, RN4
}},
1603 { "lsr_dmach", 0xf7a90000, 0xffff0000, 0x0, FMT_D10
, AM33
, {RM2
, RN0
, RM6
, RN4
}},
1604 { "lsr_dmach", 0xf7b90000, 0xffff0000, 0x0, FMT_D10
, AM33
, {IMM4_2
, RN0
, RM6
, RN4
}},
1605 { "lsr_mov", 0xf7a30000, 0xffff0000, 0xa, FMT_D10
, AM33
, {RM2
, RN0
, RM6
, RN4
}},
1606 { "lsr_mov", 0xf7b30000, 0xffff0000, 0xa, FMT_D10
, AM33
, {IMM4_2
, RN0
, RM6
, RN4
}},
1607 { "lsr_mov", 0xf7a70000, 0xffff0000, 0xa, FMT_D10
, AM33
, {RM2
, RN0
, SIMM4_6
, RN4
}},
1608 { "lsr_mov", 0xf7b70000, 0xffff0000, 0xa, FMT_D10
, AM33
, {IMM4_2
, RN0
, SIMM4_6
, RN4
}},
1609 { "lsr_or", 0xf7ac0000, 0xffff0000, 0xa, FMT_D10
, AM33
, {RM2
, RN0
, RM6
, RN4
}},
1610 { "lsr_or", 0xf7bc0000, 0xffff0000, 0xa, FMT_D10
, AM33
, {IMM4_2
, RN0
, RM6
, RN4
}},
1611 { "lsr_sat16", 0xf7ad0000, 0xffff0000, 0xa, FMT_D10
, AM33
, {RM2
, RN0
, RM6
, RN4
}},
1612 { "lsr_sat16", 0xf7bd0000, 0xffff0000, 0xa, FMT_D10
, AM33
, {IMM4_2
, RN0
, RM6
, RN4
}},
1613 { "lsr_sub", 0xf7a20000, 0xffff0000, 0xa, FMT_D10
, AM33
, {RM2
, RN0
, RM6
, RN4
}},
1614 { "lsr_sub", 0xf7b20000, 0xffff0000, 0xa, FMT_D10
, AM33
, {IMM4_2
, RN0
, RM6
, RN4
}},
1615 { "lsr_sub", 0xf7a60000, 0xffff0000, 0xa, FMT_D10
, AM33
, {RM2
, RN0
, SIMM4_6
, RN4
}},
1616 { "lsr_sub", 0xf7b60000, 0xffff0000, 0xa, FMT_D10
, AM33
, {IMM4_2
, RN0
, SIMM4_6
, RN4
}},
1617 { "lsr_swhw", 0xf7ab0000, 0xffff0000, 0xa, FMT_D10
, AM33
, {RM2
, RN0
, RM6
, RN4
}},
1618 { "lsr_swhw", 0xf7bb0000, 0xffff0000, 0xa, FMT_D10
, AM33
, {IMM4_2
, RN0
, RM6
, RN4
}},
1619 { "lsr_xor", 0xf7aa0000, 0xffff0000, 0xa, FMT_D10
, AM33
, {RM2
, RN0
, RM6
, RN4
}},
1620 { "lsr_xor", 0xf7ba0000, 0xffff0000, 0xa, FMT_D10
, AM33
, {IMM4_2
, RN0
, RM6
, RN4
}},
1621 { "mov_and", 0xf7680000, 0xffff0000, 0xa, FMT_D10
, AM33
, {RM2
, RN0
, RM6
, RN4
}},
1622 { "mov_and", 0xf7780000, 0xffff0000, 0xa, FMT_D10
, AM33
, {SIMM4_2
, RN0
, RM6
, RN4
}},
1623 { "mov_dmach", 0xf7690000, 0xffff0000, 0x0, FMT_D10
, AM33
, {RM2
, RN0
, RM6
, RN4
}},
1624 { "mov_dmach", 0xf7790000, 0xffff0000, 0x0, FMT_D10
, AM33
, {SIMM4_2
, RN0
, RM6
, RN4
}},
1625 { "mov_or", 0xf76c0000, 0xffff0000, 0xa, FMT_D10
, AM33
, {RM2
, RN0
, RM6
, RN4
}},
1626 { "mov_or", 0xf77c0000, 0xffff0000, 0xa, FMT_D10
, AM33
, {SIMM4_2
, RN0
, RM6
, RN4
}},
1627 { "mov_sat16", 0xf76d0000, 0xffff0000, 0xa, FMT_D10
, AM33
, {RM2
, RN0
, RM6
, RN4
}},
1628 { "mov_sat16", 0xf77d0000, 0xffff0000, 0xa, FMT_D10
, AM33
, {SIMM4_2
, RN0
, RM6
, RN4
}},
1629 { "mov_swhw", 0xf76b0000, 0xffff0000, 0xa, FMT_D10
, AM33
, {RM2
, RN0
, RM6
, RN4
}},
1630 { "mov_swhw", 0xf77b0000, 0xffff0000, 0xa, FMT_D10
, AM33
, {SIMM4_2
, RN0
, RM6
, RN4
}},
1631 { "mov_xor", 0xf76a0000, 0xffff0000, 0xa, FMT_D10
, AM33
, {RM2
, RN0
, RM6
, RN4
}},
1632 { "mov_xor", 0xf77a0000, 0xffff0000, 0xa, FMT_D10
, AM33
, {SIMM4_2
, RN0
, RM6
, RN4
}},
1633 { "sub_and", 0xf7280000, 0xffff0000, 0xa, FMT_D10
, AM33
, {RM2
, RN0
, RM6
, RN4
}},
1634 { "sub_and", 0xf7380000, 0xffff0000, 0xa, FMT_D10
, AM33
, {SIMM4_2
, RN0
, RM6
, RN4
}},
1635 { "sub_dmach", 0xf7290000, 0xffff0000, 0x0, FMT_D10
, AM33
, {RM2
, RN0
, RM6
, RN4
}},
1636 { "sub_dmach", 0xf7390000, 0xffff0000, 0x0, FMT_D10
, AM33
, {SIMM4_2
, RN0
, RM6
, RN4
}},
1637 { "sub_or", 0xf72c0000, 0xffff0000, 0xa, FMT_D10
, AM33
, {RM2
, RN0
, RM6
, RN4
}},
1638 { "sub_or", 0xf73c0000, 0xffff0000, 0xa, FMT_D10
, AM33
, {SIMM4_2
, RN0
, RM6
, RN4
}},
1639 { "sub_sat16", 0xf72d0000, 0xffff0000, 0xa, FMT_D10
, AM33
, {RM2
, RN0
, RM6
, RN4
}},
1640 { "sub_sat16", 0xf73d0000, 0xffff0000, 0xa, FMT_D10
, AM33
, {SIMM4_2
, RN0
, RM6
, RN4
}},
1641 { "sub_swhw", 0xf72b0000, 0xffff0000, 0xa, FMT_D10
, AM33
, {RM2
, RN0
, RM6
, RN4
}},
1642 { "sub_swhw", 0xf73b0000, 0xffff0000, 0xa, FMT_D10
, AM33
, {SIMM4_2
, RN0
, RM6
, RN4
}},
1643 { "sub_xor", 0xf72a0000, 0xffff0000, 0xa, FMT_D10
, AM33
, {RM2
, RN0
, RM6
, RN4
}},
1644 { "sub_xor", 0xf73a0000, 0xffff0000, 0xa, FMT_D10
, AM33
, {SIMM4_2
, RN0
, RM6
, RN4
}},
1645 { "mov_llt", 0xf7e00000, 0xffff000f, 0x22, FMT_D10
, AM33
, {MEMINC2 (RN4
,SIMM4_2
), RM6
}},
1646 { "mov_lgt", 0xf7e00001, 0xffff000f, 0x22, FMT_D10
, AM33
, {MEMINC2 (RN4
,SIMM4_2
), RM6
}},
1647 { "mov_lge", 0xf7e00002, 0xffff000f, 0x22, FMT_D10
, AM33
, {MEMINC2 (RN4
,SIMM4_2
), RM6
}},
1648 { "mov_lle", 0xf7e00003, 0xffff000f, 0x22, FMT_D10
, AM33
, {MEMINC2 (RN4
,SIMM4_2
), RM6
}},
1649 { "mov_lcs", 0xf7e00004, 0xffff000f, 0x22, FMT_D10
, AM33
, {MEMINC2 (RN4
,SIMM4_2
), RM6
}},
1650 { "mov_lhi", 0xf7e00005, 0xffff000f, 0x22, FMT_D10
, AM33
, {MEMINC2 (RN4
,SIMM4_2
), RM6
}},
1651 { "mov_lcc", 0xf7e00006, 0xffff000f, 0x22, FMT_D10
, AM33
, {MEMINC2 (RN4
,SIMM4_2
), RM6
}},
1652 { "mov_lls", 0xf7e00007, 0xffff000f, 0x22, FMT_D10
, AM33
, {MEMINC2 (RN4
,SIMM4_2
), RM6
}},
1653 { "mov_leq", 0xf7e00008, 0xffff000f, 0x22, FMT_D10
, AM33
, {MEMINC2 (RN4
,SIMM4_2
), RM6
}},
1654 { "mov_lne", 0xf7e00009, 0xffff000f, 0x22, FMT_D10
, AM33
, {MEMINC2 (RN4
,SIMM4_2
), RM6
}},
1655 { "mov_lra", 0xf7e0000a, 0xffff000f, 0x22, FMT_D10
, AM33
, {MEMINC2 (RN4
,SIMM4_2
), RM6
}},
1656 { "llt_mov", 0xf7e00000, 0xffff000f, 0x22, FMT_D10
, AM33
, {MEMINC2 (RN4
,SIMM4_2
), RM6
}},
1657 { "lgt_mov", 0xf7e00001, 0xffff000f, 0x22, FMT_D10
, AM33
, {MEMINC2 (RN4
,SIMM4_2
), RM6
}},
1658 { "lge_mov", 0xf7e00002, 0xffff000f, 0x22, FMT_D10
, AM33
, {MEMINC2 (RN4
,SIMM4_2
), RM6
}},
1659 { "lle_mov", 0xf7e00003, 0xffff000f, 0x22, FMT_D10
, AM33
, {MEMINC2 (RN4
,SIMM4_2
), RM6
}},
1660 { "lcs_mov", 0xf7e00004, 0xffff000f, 0x22, FMT_D10
, AM33
, {MEMINC2 (RN4
,SIMM4_2
), RM6
}},
1661 { "lhi_mov", 0xf7e00005, 0xffff000f, 0x22, FMT_D10
, AM33
, {MEMINC2 (RN4
,SIMM4_2
), RM6
}},
1662 { "lcc_mov", 0xf7e00006, 0xffff000f, 0x22, FMT_D10
, AM33
, {MEMINC2 (RN4
,SIMM4_2
), RM6
}},
1663 { "lls_mov", 0xf7e00007, 0xffff000f, 0x22, FMT_D10
, AM33
, {MEMINC2 (RN4
,SIMM4_2
), RM6
}},
1664 { "leq_mov", 0xf7e00008, 0xffff000f, 0x22, FMT_D10
, AM33
, {MEMINC2 (RN4
,SIMM4_2
), RM6
}},
1665 { "lne_mov", 0xf7e00009, 0xffff000f, 0x22, FMT_D10
, AM33
, {MEMINC2 (RN4
,SIMM4_2
), RM6
}},
1666 { "lra_mov", 0xf7e0000a, 0xffff000f, 0x22, FMT_D10
, AM33
, {MEMINC2 (RN4
,SIMM4_2
), RM6
}},
1668 { 0, 0, 0, 0, 0, 0, {0}},
1672 const int mn10300_num_opcodes
=
1673 sizeof (mn10300_opcodes
) / sizeof (mn10300_opcodes
[0]);
