| blob | 62a0b8d64a6f7b2657be92116978cf7a3c7f11b1 |
1 /* 32-bit ELF support for ARM
2 Copyright 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007,
3 2008, 2009, 2010, 2011 Free Software Foundation, Inc.
5 This file is part of BFD, the Binary File Descriptor library.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
20 MA 02110-1301, USA. */
23 #include <limits.h>
32 /* Return the relocation section associated with NAME. HTAB is the
33 bfd's elf32_arm_link_hash_entry. */
34 #define RELOC_SECTION(HTAB, NAME) \
37 /* Return size of a relocation entry. HTAB is the bfd's
38 elf32_arm_link_hash_entry. */
39 #define RELOC_SIZE(HTAB) \
40 ((HTAB)->use_rel \
41 ? sizeof (Elf32_External_Rel) \
42 : sizeof (Elf32_External_Rela))
44 /* Return function to swap relocations in. HTAB is the bfd's
45 elf32_arm_link_hash_entry. */
46 #define SWAP_RELOC_IN(HTAB) \
47 ((HTAB)->use_rel \
48 ? bfd_elf32_swap_reloc_in \
49 : bfd_elf32_swap_reloca_in)
51 /* Return function to swap relocations out. HTAB is the bfd's
52 elf32_arm_link_hash_entry. */
53 #define SWAP_RELOC_OUT(HTAB) \
54 ((HTAB)->use_rel \
55 ? bfd_elf32_swap_reloc_out \
56 : bfd_elf32_swap_reloca_out)
58 #define elf_info_to_howto 0
59 #define elf_info_to_howto_rel elf32_arm_info_to_howto
61 #define ARM_ELF_ABI_VERSION 0
62 #define ARM_ELF_OS_ABI_VERSION ELFOSABI_ARM
69 /* Note: code such as elf32_arm_reloc_type_lookup expect to use e.g.
70 R_ARM_PC24 as an index into this, and find the R_ARM_PC24 HOWTO
71 in that slot. */
74 {
75 /* No relocation. */
104 /* 32 bit absolute */
119 /* standard 32bit pc-relative reloc */
134 /* 8 bit absolute - R_ARM_LDR_PC_G0 in AAELF */
149 /* 16 bit absolute */
164 /* 12 bit absolute */
193 /* 8 bit absolute */
292 /* BLX instruction for the ARM. */
307 /* BLX instruction for the Thumb. */
322 /* Dynamic TLS relocations. */
366 /* Relocs used in ARM Linux */
830 /* These are declared as 13-bit signed relocations because we can
831 address -4095 .. 4095(base) by altering ADDW to SUBW or vice
832 versa. */
889 /* Group relocations. */
1269 /* End of group relocations. */
1483 /* GNU extension to record C++ vtable member usage */
1498 /* GNU extension to record C++ vtable hierarchy */
1541 /* TLS relocations */
1654 /* 112-127 private relocations. */
1672 /* R_ARM_ME_TOO, obsolete. */
1688 };
1690 /* 160 onwards: */
1692 {
1706 };
1708 /* 249-255 extended, currently unused, relocations: */
1710 {
1766 };
1770 {
1782 }
1784 static void
1787 {
1792 }
1794 struct elf32_arm_reloc_map
1795 {
1796 bfd_reloc_code_real_type bfd_reloc_val;
1798 };
1800 /* All entries in this list must also be present in elf32_arm_howto_table. */
1802 {
1889 };
1893 bfd_reloc_code_real_type code)
1894 {
1902 }
1907 {
1926 }
1928 /* Support for core dump NOTE sections. */
1930 static bfd_boolean
1932 {
1937 {
1942 /* pr_cursig */
1945 /* pr_pid */
1948 /* pr_reg */
1953 }
1955 /* Make a ".reg/999" section. */
1958 }
1960 static bfd_boolean
1962 {
1964 {
1975 }
1977 /* Note that for some reason, a spurious space is tacked
1978 onto the end of the args in some (at least one anyway)
1979 implementations, so strip it off if it exists. */
1980 {
1986 }
1989 }
1994 {
1996 {
2001 {
2013 }
2016 {
2035 }
2036 }
2037 }
2039 #define TARGET_LITTLE_SYM bfd_elf32_littlearm_vec
2041 #define TARGET_BIG_SYM bfd_elf32_bigarm_vec
2044 #define elf_backend_grok_prstatus elf32_arm_nabi_grok_prstatus
2045 #define elf_backend_grok_psinfo elf32_arm_nabi_grok_psinfo
2046 #define elf_backend_write_core_note elf32_arm_nabi_write_core_note
2051 /* In lieu of proper flags, assume all EABIv4 or later objects are
2052 interworkable. */
2053 #define INTERWORK_FLAG(abfd) \
2054 (EF_ARM_EABI_VERSION (elf_elfheader (abfd)->e_flags) >= EF_ARM_EABI_VER4 \
2055 || (elf_elfheader (abfd)->e_flags & EF_ARM_INTERWORK) \
2056 || ((abfd)->flags & BFD_LINKER_CREATED))
2058 /* The linker script knows the section names for placement.
2059 The entry_names are used to do simple name mangling on the stubs.
2060 Given a function name, and its type, the stub can be found. The
2061 name can be changed. The only requirement is the %s be present. */
2076 /* The name of the dynamic interpreter. This is put in the .interp
2077 section. */
2081 {
2085 };
2088 {
2096 + dl_tlsdesc_lazy_resolver(GOT) */
2098 };
2100 #ifdef FOUR_WORD_PLT
2102 /* The first entry in a procedure linkage table looks like
2103 this. It is set up so that any shared library function that is
2104 called before the relocation has been set up calls the dynamic
2105 linker first. */
2107 {
2112 };
2114 /* Subsequent entries in a procedure linkage table look like
2115 this. */
2117 {
2122 };
2124 #else
2126 /* The first entry in a procedure linkage table looks like
2127 this. It is set up so that any shared library function that is
2128 called before the relocation has been set up calls the dynamic
2129 linker first. */
2131 {
2137 };
2139 /* Subsequent entries in a procedure linkage table look like
2140 this. */
2142 {
2146 };
2148 #endif
2150 /* The format of the first entry in the procedure linkage table
2151 for a VxWorks executable. */
2153 {
2158 };
2160 /* The format of subsequent entries in a VxWorks executable. */
2162 {
2169 };
2171 /* The format of entries in a VxWorks shared library. */
2173 {
2180 };
2182 /* An initial stub used if the PLT entry is referenced from Thumb code. */
2183 #define PLT_THUMB_STUB_SIZE 4
2185 {
2188 };
2190 /* The entries in a PLT when using a DLL-based target with multiple
2191 address spaces. */
2193 {
2196 };
2198 #define ARM_MAX_FWD_BRANCH_OFFSET ((((1 << 23) - 1) << 2) + 8)
2199 #define ARM_MAX_BWD_BRANCH_OFFSET ((-((1 << 23) << 2)) + 8)
2200 #define THM_MAX_FWD_BRANCH_OFFSET ((1 << 22) -2 + 4)
2201 #define THM_MAX_BWD_BRANCH_OFFSET (-(1 << 22) + 4)
2202 #define THM2_MAX_FWD_BRANCH_OFFSET (((1 << 24) - 2) + 4)
2203 #define THM2_MAX_BWD_BRANCH_OFFSET (-(1 << 24) + 4)
2205 enum stub_insn_type
2206 {
2208 THUMB32_TYPE,
2209 ARM_TYPE,
2210 DATA_TYPE
2211 };
2213 #define THUMB16_INSN(X) {(X), THUMB16_TYPE, R_ARM_NONE, 0}
2214 /* A bit of a hack. A Thumb conditional branch, in which the proper condition
2215 is inserted in arm_build_one_stub(). */
2216 #define THUMB16_BCOND_INSN(X) {(X), THUMB16_TYPE, R_ARM_NONE, 1}
2217 #define THUMB32_INSN(X) {(X), THUMB32_TYPE, R_ARM_NONE, 0}
2218 #define THUMB32_B_INSN(X, Z) {(X), THUMB32_TYPE, R_ARM_THM_JUMP24, (Z)}
2219 #define ARM_INSN(X) {(X), ARM_TYPE, R_ARM_NONE, 0}
2220 #define ARM_REL_INSN(X, Z) {(X), ARM_TYPE, R_ARM_JUMP24, (Z)}
2221 #define DATA_WORD(X,Y,Z) {(X), DATA_TYPE, (Y), (Z)}
2224 {
2225 bfd_vma data;
2231 /* Arm/Thumb -> Arm/Thumb long branch stub. On V5T and above, use blx
2232 to reach the stub if necessary. */
2234 {
2237 };
2239 /* V4T Arm -> Thumb long branch stub. Used on V4T where blx is not
2240 available. */
2242 {
2246 };
2248 /* Thumb -> Thumb long branch stub. Used on M-profile architectures. */
2250 {
2258 };
2260 /* V4T Thumb -> Thumb long branch stub. Using the stack is not
2261 allowed. */
2263 {
2269 };
2271 /* V4T Thumb -> ARM long branch stub. Used on V4T where blx is not
2272 available. */
2274 {
2279 };
2281 /* V4T Thumb -> ARM short branch stub. Shorter variant of the above
2282 one, when the destination is close enough. */
2284 {
2288 };
2290 /* ARM/Thumb -> ARM long branch stub, PIC. On V5T and above, use
2291 blx to reach the stub if necessary. */
2293 {
2297 };
2299 /* ARM/Thumb -> Thumb long branch stub, PIC. On V5T and above, use
2300 blx to reach the stub if necessary. We can not add into pc;
2301 it is not guaranteed to mode switch (different in ARMv6 and
2302 ARMv7). */
2304 {
2309 };
2311 /* V4T ARM -> ARM long branch stub, PIC. */
2313 {
2318 };
2320 /* V4T Thumb -> ARM long branch stub, PIC. */
2322 {
2328 };
2330 /* Thumb -> Thumb long branch stub, PIC. Used on M-profile
2331 architectures. */
2333 {
2341 };
2343 /* V4T Thumb -> Thumb long branch stub, PIC. Using the stack is not
2344 allowed. */
2346 {
2353 };
2355 /* Thumb2/ARM -> TLS trampoline. Lowest common denominator, which is a
2356 long PIC stub. We can use r1 as a scratch -- and cannot use ip. */
2358 {
2362 };
2364 /* V4T Thumb -> TLS trampoline. lowest common denominator, which is a
2365 long PIC stub. We can use r1 as a scratch -- and cannot use ip. */
2367 {
2373 };
2375 /* Cortex-A8 erratum-workaround stubs. */
2377 /* Stub used for conditional branches (which may be beyond +/-1MB away, so we
2378 can't use a conditional branch to reach this stub). */
2381 {
2385 };
2387 /* Stub used for b.w and bl.w instructions. */
2390 {
2392 };
2395 {
2397 };
2399 /* Stub used for Thumb-2 blx.w instructions. We modified the original blx.w
2400 instruction (which switches to ARM mode) to point to this stub. Jump to the
2401 real destination using an ARM-mode branch. */
2404 {
2406 };
2408 /* For each section group there can be a specially created linker section
2409 to hold the stubs for that group. The name of the stub section is based
2410 upon the name of another section within that group with the suffix below
2411 applied.
2413 PR 13049: STUB_SUFFIX used to be ".stub", but this allowed the user to
2414 create what appeared to be a linker stub section when it actually
2415 contained user code/data. For example, consider this fragment:
2417 const char * stubborn_problems[] = { "np" };
2419 If this is compiled with "-fPIC -fdata-sections" then gcc produces a
2420 section called:
2422 .data.rel.local.stubborn_problems
2424 This then causes problems in arm32_arm_build_stubs() as it triggers:
2426 // Ignore non-stub sections.
2427 if (!strstr (stub_sec->name, STUB_SUFFIX))
2428 continue;
2430 And so the section would be ignored instead of being processed. Hence
2431 the change in definition of STUB_SUFFIX to a name that cannot be a valid
2432 C identifier. */
2435 /* One entry per long/short branch stub defined above. */
2436 #define DEF_STUBS \
2437 DEF_STUB(long_branch_any_any) \
2438 DEF_STUB(long_branch_v4t_arm_thumb) \
2439 DEF_STUB(long_branch_thumb_only) \
2440 DEF_STUB(long_branch_v4t_thumb_thumb) \
2441 DEF_STUB(long_branch_v4t_thumb_arm) \
2442 DEF_STUB(short_branch_v4t_thumb_arm) \
2443 DEF_STUB(long_branch_any_arm_pic) \
2444 DEF_STUB(long_branch_any_thumb_pic) \
2445 DEF_STUB(long_branch_v4t_thumb_thumb_pic) \
2446 DEF_STUB(long_branch_v4t_arm_thumb_pic) \
2447 DEF_STUB(long_branch_v4t_thumb_arm_pic) \
2448 DEF_STUB(long_branch_thumb_only_pic) \
2449 DEF_STUB(long_branch_any_tls_pic) \
2450 DEF_STUB(long_branch_v4t_thumb_tls_pic) \
2451 DEF_STUB(a8_veneer_b_cond) \
2452 DEF_STUB(a8_veneer_b) \
2453 DEF_STUB(a8_veneer_bl) \
2454 DEF_STUB(a8_veneer_blx)
2456 #define DEF_STUB(x) arm_stub_##x,
2458 arm_stub_none,
2459 DEF_STUBS
2460 /* Note the first a8_veneer type */
2461 arm_stub_a8_veneer_lwm = arm_stub_a8_veneer_b_cond
2462 };
2463 #undef DEF_STUB
2466 {
2471 #define DEF_STUB(x) {elf32_arm_stub_##x, ARRAY_SIZE(elf32_arm_stub_##x)},
2474 DEF_STUBS
2475 };
2477 struct elf32_arm_stub_hash_entry
2478 {
2479 /* Base hash table entry structure. */
2482 /* The stub section. */
2485 /* Offset within stub_sec of the beginning of this stub. */
2486 bfd_vma stub_offset;
2488 /* Given the symbol's value and its section we can determine its final
2489 value when building the stubs (so the stub knows where to jump). */
2490 bfd_vma target_value;
2493 /* Offset to apply to relocation referencing target_value. */
2494 bfd_vma target_addend;
2496 /* The instruction which caused this stub to be generated (only valid for
2497 Cortex-A8 erratum workaround stubs at present). */
2500 /* The stub type. */
2502 /* Its encoding size in bytes. */
2504 /* Its template. */
2506 /* The size of the template (number of entries). */
2509 /* The symbol table entry, if any, that this was derived from. */
2512 /* Type of branch. */
2515 /* Where this stub is being called from, or, in the case of combined
2516 stub sections, the first input section in the group. */
2519 /* The name for the local symbol at the start of this stub. The
2520 stub name in the hash table has to be unique; this does not, so
2521 it can be friendlier. */
2523 };
2525 /* Used to build a map of a section. This is required for mixed-endian
2526 code/data. */
2529 {
2530 bfd_vma vma;
2532 }
2533 elf32_arm_section_map;
2535 /* Information about a VFP11 erratum veneer, or a branch to such a veneer. */
2538 {
2539 VFP11_ERRATUM_BRANCH_TO_ARM_VENEER,
2540 VFP11_ERRATUM_BRANCH_TO_THUMB_VENEER,
2541 VFP11_ERRATUM_ARM_VENEER,
2542 VFP11_ERRATUM_THUMB_VENEER
2543 }
2544 elf32_vfp11_erratum_type;
2547 {
2549 bfd_vma vma;
2550 union
2551 {
2552 struct
2553 {
2557 struct
2558 {
2563 elf32_vfp11_erratum_type type;
2564 }
2565 elf32_vfp11_erratum_list;
2568 {
2569 DELETE_EXIDX_ENTRY,
2570 INSERT_EXIDX_CANTUNWIND_AT_END
2571 }
2572 arm_unwind_edit_type;
2574 /* A (sorted) list of edits to apply to an unwind table. */
2576 {
2577 arm_unwind_edit_type type;
2578 /* Note: we sometimes want to insert an unwind entry corresponding to a
2579 section different from the one we're currently writing out, so record the
2580 (text) section this edit relates to here. */
2584 }
2585 arm_unwind_table_edit;
2588 {
2589 /* Information about mapping symbols. */
2594 /* Information about CPU errata. */
2597 /* Information about unwind tables. */
2598 union
2599 {
2600 /* Unwind info attached to a text section. */
2601 struct
2602 {
2606 /* Unwind info attached to an .ARM.exidx section. */
2607 struct
2608 {
2613 }
2614 _arm_elf_section_data;
2616 #define elf32_arm_section_data(sec) \
2617 ((_arm_elf_section_data *) elf_section_data (sec))
2619 /* A fix which might be required for Cortex-A8 Thumb-2 branch/TLB erratum.
2620 These fixes are subject to a relaxation procedure (in elf32_arm_size_stubs),
2621 so may be created multiple times: we use an array of these entries whilst
2622 relaxing which we can refresh easily, then create stubs for each potentially
2623 erratum-triggering instruction once we've settled on a solution. */
2628 bfd_vma offset;
2629 bfd_vma addend;
2634 };
2636 /* A table of relocs applied to branches which might trigger Cortex-A8
2637 erratum. */
2640 bfd_vma from;
2641 bfd_vma destination;
2646 bfd_boolean non_a8_stub;
2647 };
2649 /* The size of the thread control block. */
2650 #define TCB_SIZE 8
2652 /* ARM-specific information about a PLT entry, over and above the usual
2653 gotplt_union. */
2655 /* We reference count Thumb references to a PLT entry separately,
2656 so that we can emit the Thumb trampoline only if needed. */
2657 bfd_signed_vma thumb_refcount;
2659 /* Some references from Thumb code may be eliminated by BL->BLX
2660 conversion, so record them separately. */
2661 bfd_signed_vma maybe_thumb_refcount;
2663 /* How many of the recorded PLT accesses were from non-call relocations.
2664 This information is useful when deciding whether anything takes the
2665 address of an STT_GNU_IFUNC PLT. A value of 0 means that all
2666 non-call references to the function should resolve directly to the
2667 real runtime target. */
2670 /* Since PLT entries have variable size if the Thumb prologue is
2671 used, we need to record the index into .got.plt instead of
2672 recomputing it from the PLT offset. */
2673 bfd_signed_vma got_offset;
2674 };
2676 /* Information about an .iplt entry for a local STT_GNU_IFUNC symbol. */
2678 /* The information that is usually found in the generic ELF part of
2679 the hash table entry. */
2682 /* The information that is usually found in the ARM-specific part of
2683 the hash table entry. */
2686 /* A list of all potential dynamic relocations against this symbol. */
2688 };
2690 struct elf_arm_obj_tdata
2691 {
2694 /* tls_type for each local got entry. */
2697 /* GOTPLT entries for TLS descriptors. */
2700 /* Information for local symbols that need entries in .iplt. */
2703 /* Zero to warn when linking objects with incompatible enum sizes. */
2706 /* Zero to warn when linking objects with incompatible wchar_t sizes. */
2708 };
2710 #define elf_arm_tdata(bfd) \
2711 ((struct elf_arm_obj_tdata *) (bfd)->tdata.any)
2713 #define elf32_arm_local_got_tls_type(bfd) \
2714 (elf_arm_tdata (bfd)->local_got_tls_type)
2716 #define elf32_arm_local_tlsdesc_gotent(bfd) \
2717 (elf_arm_tdata (bfd)->local_tlsdesc_gotent)
2719 #define elf32_arm_local_iplt(bfd) \
2720 (elf_arm_tdata (bfd)->local_iplt)
2722 #define is_arm_elf(bfd) \
2723 (bfd_get_flavour (bfd) == bfd_target_elf_flavour \
2724 && elf_tdata (bfd) != NULL \
2725 && elf_object_id (bfd) == ARM_ELF_DATA)
2727 static bfd_boolean
2729 {
2731 ARM_ELF_DATA);
2732 }
2734 #define elf32_arm_hash_entry(ent) ((struct elf32_arm_link_hash_entry *)(ent))
2736 /* Arm ELF linker hash entry. */
2737 struct elf32_arm_link_hash_entry
2738 {
2741 /* Track dynamic relocs copied for this symbol. */
2744 /* ARM-specific PLT information. */
2747 #define GOT_UNKNOWN 0
2748 #define GOT_NORMAL 1
2749 #define GOT_TLS_GD 2
2750 #define GOT_TLS_IE 4
2751 #define GOT_TLS_GDESC 8
2752 #define GOT_TLS_GD_ANY_P(type) ((type & GOT_TLS_GD) || (type & GOT_TLS_GDESC))
2755 /* True if the symbol's PLT entry is in .iplt rather than .plt. */
2760 /* Offset of the GOTPLT entry reserved for the TLS descriptor,
2761 starting at the end of the jump table. */
2762 bfd_vma tlsdesc_got;
2764 /* The symbol marking the real symbol location for exported thumb
2765 symbols with Arm stubs. */
2768 /* A pointer to the most recently used stub hash entry against this
2769 symbol. */
2771 };
2773 /* Traverse an arm ELF linker hash table. */
2774 #define elf32_arm_link_hash_traverse(table, func, info) \
2775 (elf_link_hash_traverse \
2776 (&(table)->root, \
2777 (bfd_boolean (*) (struct elf_link_hash_entry *, void *)) (func), \
2778 (info)))
2780 /* Get the ARM elf linker hash table from a link_info structure. */
2781 #define elf32_arm_hash_table(info) \
2782 (elf_hash_table_id ((struct elf_link_hash_table *) ((info)->hash)) \
2783 == ARM_ELF_DATA ? ((struct elf32_arm_link_hash_table *) ((info)->hash)) : NULL)
2785 #define arm_stub_hash_lookup(table, string, create, copy) \
2786 ((struct elf32_arm_stub_hash_entry *) \
2787 bfd_hash_lookup ((table), (string), (create), (copy)))
2789 /* Array to keep track of which stub sections have been created, and
2790 information on stub grouping. */
2791 struct map_stub
2792 {
2793 /* This is the section to which stubs in the group will be
2794 attached. */
2796 /* The stub section. */
2798 };
2800 #define elf32_arm_compute_jump_table_size(htab) \
2801 ((htab)->next_tls_desc_index * 4)
2803 /* ARM ELF linker hash table. */
2804 struct elf32_arm_link_hash_table
2805 {
2806 /* The main hash table. */
2809 /* The size in bytes of the section containing the Thumb-to-ARM glue. */
2810 bfd_size_type thumb_glue_size;
2812 /* The size in bytes of the section containing the ARM-to-Thumb glue. */
2813 bfd_size_type arm_glue_size;
2815 /* The size in bytes of section containing the ARMv4 BX veneers. */
2816 bfd_size_type bx_glue_size;
2818 /* Offsets of ARMv4 BX veneers. Bit1 set if present, and Bit0 set when
2819 veneer has been populated. */
2822 /* The size in bytes of the section containing glue for VFP11 erratum
2823 veneers. */
2824 bfd_size_type vfp11_erratum_glue_size;
2826 /* A table of fix locations for Cortex-A8 Thumb-2 branch/TLB erratum. This
2827 holds Cortex-A8 erratum fix locations between elf32_arm_size_stubs() and
2828 elf32_arm_write_section(). */
2832 /* An arbitrary input BFD chosen to hold the glue sections. */
2835 /* Nonzero to output a BE8 image. */
2838 /* Zero if R_ARM_TARGET1 means R_ARM_ABS32.
2839 Nonzero if R_ARM_TARGET1 means R_ARM_REL32. */
2842 /* The relocation to use for R_ARM_TARGET2 relocations. */
2845 /* 0 = Ignore R_ARM_V4BX.
2846 1 = Convert BX to MOV PC.
2847 2 = Generate v4 interworing stubs. */
2850 /* Whether we should fix the Cortex-A8 Thumb-2 branch/TLB erratum. */
2853 /* Whether we should fix the ARM1176 BLX immediate issue. */
2856 /* Nonzero if the ARM/Thumb BLX instructions are available for use. */
2859 /* What sort of code sequences we should look for which may trigger the
2860 VFP11 denorm erratum. */
2861 bfd_arm_vfp11_fix vfp11_fix;
2863 /* Global counter for the number of fixes we have emitted. */
2866 /* Nonzero to force PIC branch veneers. */
2869 /* The number of bytes in the initial entry in the PLT. */
2870 bfd_size_type plt_header_size;
2872 /* The number of bytes in the subsequent PLT etries. */
2873 bfd_size_type plt_entry_size;
2875 /* True if the target system is VxWorks. */
2878 /* True if the target system is Symbian OS. */
2881 /* True if the target uses REL relocations. */
2884 /* The index of the next unused R_ARM_TLS_DESC slot in .rel.plt. */
2885 bfd_vma next_tls_desc_index;
2887 /* How many R_ARM_TLS_DESC relocations were generated so far. */
2888 bfd_vma num_tls_desc;
2890 /* Short-cuts to get to dynamic linker sections. */
2894 /* The (unloaded but important) VxWorks .rela.plt.unloaded section. */
2897 /* The offset into splt of the PLT entry for the TLS descriptor
2898 resolver. Special values are 0, if not necessary (or not found
2899 to be necessary yet), and -1 if needed but not determined
2900 yet. */
2901 bfd_vma dt_tlsdesc_plt;
2903 /* The offset into sgot of the GOT entry used by the PLT entry
2904 above. */
2905 bfd_vma dt_tlsdesc_got;
2907 /* Offset in .plt section of tls_arm_trampoline. */
2908 bfd_vma tls_trampoline;
2910 /* Data for R_ARM_TLS_LDM32 relocations. */
2911 union
2912 {
2913 bfd_signed_vma refcount;
2914 bfd_vma offset;
2917 /* Small local sym cache. */
2920 /* For convenience in allocate_dynrelocs. */
2923 /* The amount of space used by the reserved portion of the sgotplt
2924 section, plus whatever space is used by the jump slots. */
2925 bfd_vma sgotplt_jump_table_size;
2927 /* The stub hash table. */
2930 /* Linker stub bfd. */
2933 /* Linker call-backs. */
2937 /* Array to keep track of which stub sections have been created, and
2938 information on stub grouping. */
2941 /* Number of elements in stub_group. */
2944 /* Assorted information used by elf32_arm_size_stubs. */
2948 };
2950 /* Create an entry in an ARM ELF linker hash table. */
2956 {
2960 /* Allocate the structure if it has not already been allocated by a
2961 subclass. */
2968 /* Call the allocation method of the superclass. */
2973 {
2985 }
2988 }
2990 /* Ensure that we have allocated bookkeeping structures for ABFD's local
2991 symbols. */
2993 static bfd_boolean
2995 {
2997 {
2998 bfd_size_type num_syms;
2999 bfd_size_type size;
3021 }
3023 }
3025 /* Return the .iplt information for local symbol R_SYMNDX, which belongs
3026 to input bfd ABFD. Create the information if it doesn't already exist.
3027 Return null if an allocation fails. */
3031 {
3042 }
3044 /* Try to obtain PLT information for the symbol with index R_SYMNDX
3045 in ABFD's symbol table. If the symbol is global, H points to its
3046 hash table entry, otherwise H is null.
3048 Return true if the symbol does have PLT information. When returning
3049 true, point *ROOT_PLT at the target-independent reference count/offset
3050 union and *ARM_PLT at the ARM-specific information. */
3052 static bfd_boolean
3056 {
3060 {
3064 }
3076 }
3078 /* Return true if the PLT described by ARM_PLT requires a Thumb stub
3079 before it. */
3081 static bfd_boolean
3084 {
3090 }
3092 /* Return a pointer to the head of the dynamic reloc list that should
3093 be used for local symbol ISYM, which is symbol number R_SYMNDX in
3094 ABFD's symbol table. Return null if an error occurs. */
3099 {
3101 {
3108 }
3109 else
3110 {
3111 /* Track dynamic relocs needed for local syms too.
3112 We really need local syms available to do this
3113 easily. Oh well. */
3123 }
3124 }
3126 /* Initialize an entry in the stub hash table. */
3132 {
3133 /* Allocate the structure if it has not already been allocated by a
3134 subclass. */
3136 {
3141 }
3143 /* Call the allocation method of the superclass. */
3146 {
3149 /* Initialize the local fields. */
3164 }
3167 }
3169 /* Create .got, .gotplt, and .rel(a).got sections in DYNOBJ, and set up
3170 shortcuts to them in our hash table. */
3172 static bfd_boolean
3174 {
3181 /* BPABI objects never have a GOT, or associated sections. */
3189 }
3191 /* Create the .iplt, .rel(a).iplt and .igot.plt sections. */
3193 static bfd_boolean
3195 {
3200 flagword flags;
3208 {
3215 }
3218 {
3225 }
3228 {
3234 }
3236 }
3238 /* Create .plt, .rel(a).plt, .got, .got.plt, .rel(a).got, .dynbss, and
3239 .rel(a).bss sections in DYNOBJ, and set up shortcuts to them in our
3240 hash table. */
3242 static bfd_boolean
3244 {
3263 {
3268 {
3270 htab->plt_entry_size
3272 }
3273 else
3274 {
3275 htab->plt_header_size
3277 htab->plt_entry_size
3279 }
3280 }
3289 }
3291 /* Copy the extra info we tack onto an elf_link_hash_entry. */
3293 static void
3297 {
3304 {
3306 {
3310 /* Add reloc counts against the indirect sym to the direct sym
3311 list. Merge any entries against the same section. */
3313 {
3318 {
3323 }
3326 }
3328 }
3332 }
3335 {
3336 /* Copy over PLT info. */
3344 /* We should only allocate a function to .iplt once the final
3345 symbol information is known. */
3349 {
3352 }
3353 }
3356 }
3358 /* Create an ARM elf linker hash table. */
3362 {
3371 elf32_arm_link_hash_newfunc,
3373 ARM_ELF_DATA))
3374 {
3377 }
3400 #ifdef FOUR_WORD_PLT
3403 #else
3406 #endif
3426 {
3429 }
3432 }
3434 /* Free the derived linker hash table. */
3436 static void
3438 {
3444 }
3446 /* Determine if we're dealing with a Thumb only architecture. */
3448 static bfd_boolean
3450 {
3452 Tag_CPU_arch);
3462 Tag_CPU_arch_profile);
3465 }
3467 /* Determine if we're dealing with a Thumb-2 object. */
3469 static bfd_boolean
3471 {
3473 Tag_CPU_arch);
3475 }
3477 /* Determine what kind of NOPs are available. */
3479 static bfd_boolean
3481 {
3483 Tag_CPU_arch);
3488 }
3490 static bfd_boolean
3492 {
3494 Tag_CPU_arch);
3497 }
3499 static bfd_boolean
3501 {
3503 {
3517 }
3518 }
3520 /* Determine the type of stub needed, if any, for a call. */
3522 static enum elf32_arm_stub_type
3529 bfd_vma destination,
3533 {
3534 bfd_vma location;
3535 bfd_signed_vma branch_offset;
3557 /* Determine where the call point is. */
3564 /* For TLS call relocs, it is the caller's responsibility to provide
3565 the address of the appropriate trampoline. */
3571 {
3576 else
3579 {
3582 /* Note when dealing with PLT entries: the main PLT stub is in
3583 ARM mode, so if the branch is in Thumb mode, another
3584 Thumb->ARM stub will be inserted later just before the ARM
3585 PLT stub. We don't take this extra distance into account
3586 here, because if a long branch stub is needed, we'll add a
3587 Thumb->Arm one and branch directly to the ARM PLT entry
3588 because it avoids spreading offset corrections in several
3589 places. */
3596 }
3597 }
3598 /* Calls to STT_GNU_IFUNC symbols should go through a PLT. */
3605 {
3606 /* Handle cases where:
3607 - this call goes too far (different Thumb/Thumb2 max
3608 distance)
3609 - it's a Thumb->Arm call and blx is not available, or it's a
3610 Thumb->Arm branch (not bl). A stub is needed in this case,
3611 but only if this call is not through a PLT entry. Indeed,
3612 PLT stubs handle mode switching already.
3613 */
3617 || (thumb2
3625 {
3627 {
3628 /* Thumb to thumb. */
3630 {
3632 /* PIC stubs. */
3635 /* V5T and above. Stub starts with ARM code, so
3636 we must be able to switch mode before
3637 reaching it, which is only possible for 'bl'
3638 (ie R_ARM_THM_CALL relocation). */
3639 ? arm_stub_long_branch_any_thumb_pic
3640 /* On V4T, use Thumb code only. */
3643 /* non-PIC stubs. */
3646 /* V5T and above. */
3647 ? arm_stub_long_branch_any_any
3648 /* V4T. */
3650 }
3651 else
3652 {
3654 /* PIC stub. */
3655 ? arm_stub_long_branch_thumb_only_pic
3656 /* non-PIC stub. */
3658 }
3659 }
3660 else
3661 {
3662 /* Thumb to arm. */
3666 {
3671 }
3673 stub_type =
3675 /* PIC stubs. */
3677 /* TLS PIC stubs */
3681 /* V5T PIC and above. */
3682 ? arm_stub_long_branch_any_arm_pic
3683 /* V4T PIC stub. */
3686 /* non-PIC stubs. */
3688 /* V5T and above. */
3689 ? arm_stub_long_branch_any_any
3690 /* V4T. */
3693 /* Handle v4t short branches. */
3698 }
3699 }
3700 }
3705 {
3707 {
3708 /* Arm to thumb. */
3713 {
3718 }
3720 /* We have an extra 2-bytes reach because of
3721 the mode change (bit 24 (H) of BLX encoding). */
3727 {
3729 /* PIC stubs. */
3731 /* V5T and above. */
3732 ? arm_stub_long_branch_any_thumb_pic
3733 /* V4T stub. */
3736 /* non-PIC stubs. */
3738 /* V5T and above. */
3739 ? arm_stub_long_branch_any_any
3740 /* V4T. */
3742 }
3743 }
3744 else
3745 {
3746 /* Arm to arm. */
3749 {
3750 stub_type =
3752 /* PIC stubs. */
3754 /* TLS PIC Stub */
3755 ? arm_stub_long_branch_any_tls_pic
3757 /* non-PIC stubs. */
3759 }
3760 }
3761 }
3763 /* If a stub is needed, record the actual destination type. */
3768 }
3770 /* Build a name for an entry in the stub hash table. */
3778 {
3780 bfd_size_type len;
3783 {
3792 }
3793 else
3794 {
3806 }
3809 }
3811 /* Look up an entry in the stub hash. Stub entries are cached because
3812 creating the stub name takes a bit of time. */
3821 {
3829 /* If this input section is part of a group of sections sharing one
3830 stub section, then use the id of the first section in the group.
3831 Stub names need to include a section id, as there may well be
3832 more than one stub used to reach say, printf, and we need to
3833 distinguish between them. */
3840 {
3842 }
3843 else
3844 {
3857 }
3860 }
3862 /* Find or create a stub section. Returns a pointer to the stub section, and
3863 the section to which the stub section will be attached (in *LINK_SEC_P).
3864 LINK_SEC_P may be NULL. */
3869 {
3878 {
3881 {
3883 bfd_size_type len;
3898 }
3900 }
3906 }
3908 /* Add a new stub entry to the stub hash. Not all fields of the new
3909 stub entry are initialised. */
3915 {
3924 /* Enter this entry into the linker stub hash table. */
3928 {
3931 stub_name);
3933 }
3940 }
3942 /* Store an Arm insn into an output section not processed by
3943 elf32_arm_write_section. */
3945 static void
3948 {
3951 else
3953 }
3955 /* Store a 16-bit Thumb insn into an output section not processed by
3956 elf32_arm_write_section. */
3958 static void
3961 {
3964 else
3966 }
3968 /* If it's possible to change R_TYPE to a more efficient access
3969 model, return the new reloc type. */
3971 static unsigned
3974 {
3980 /* We do not support relaxations for Old TLS models. */
3982 {
3989 }
3992 }
3994 static bfd_reloc_status_type elf32_arm_final_link_relocate
4000 static unsigned int
4002 {
4004 {
4029 }
4030 }
4032 static bfd_boolean
4035 {
4036 #define MAXRELOCS 2
4043 bfd_vma sym_value;
4052 /* Massage our args to the form they really have. */
4064 /* We have to do less-strictly-aligned fixes last. */
4067 /* Make a note of the offset within the stubs for this entry. */
4073 /* This is the address of the stub destination. */
4083 {
4085 {
4087 {
4090 {
4091 /* We've borrowed the reloc_addend field to mean we should
4092 insert a condition code into this (Thumb-1 branch)
4093 instruction. See THUMB16_BCOND_INSN. */
4096 }
4099 }
4109 {
4112 }
4119 /* Handle cases where the target is encoded within the
4120 instruction. */
4122 {
4125 }
4139 }
4140 }
4144 /* Stub size has already been computed in arm_size_one_stub. Check
4145 consistency. */
4148 /* Destination is Thumb. Force bit 0 to 1 to reflect this. */
4152 /* Assume there is at least one and at most MAXRELOCS entries to relocate
4153 in each stub. */
4161 {
4162 Elf_Internal_Rela rel;
4163 bfd_boolean unresolved_reloc;
4165 enum arm_st_branch_type branch_type
4176 /* The first relocation in the elf32_arm_stub_a8_veneer_b_cond[]
4177 template should refer back to the instruction after the original
4178 branch. */
4181 /* There may be unintended consequences if this is not true. */
4184 /* Note: _bfd_final_link_relocate doesn't handle these relocations
4185 properly. We should probably use this function unconditionally,
4186 rather than only for certain relocations listed in the enclosing
4187 conditional, for the sake of consistency. */
4194 }
4195 else
4196 {
4197 Elf_Internal_Rela rel;
4198 bfd_boolean unresolved_reloc;
4215 }
4218 #undef MAXRELOCS
4219 }
4221 /* Calculate the template, template size and instruction size for a stub.
4222 Return value is the instruction size. */
4224 static unsigned int
4228 {
4243 {
4245 {
4259 }
4260 }
4263 }
4265 /* As above, but don't actually build the stub. Just bump offset so
4266 we know stub section sizes. */
4268 static bfd_boolean
4271 {
4276 /* Massage our args to the form they really have. */
4293 }
4295 /* External entry points for sizing and building linker stubs. */
4297 /* Set up various things so that we can make a list of input sections
4298 for each output section included in the link. Returns -1 on error,
4299 0 when no stubs will be needed, and 1 on success. */
4301 int
4304 {
4310 bfd_size_type amt;
4318 /* Count the number of input BFDs and find the top input section id. */
4322 {
4327 {
4330 }
4331 }
4340 /* We can't use output_bfd->section_count here to find the top output
4341 section index as some sections may have been removed, and
4342 _bfd_strip_section_from_output doesn't renumber the indices. */
4346 {
4349 }
4358 /* For sections we aren't interested in, mark their entries with a
4359 value we can check later. */
4361 do
4368 {
4371 }
4374 }
4376 /* The linker repeatedly calls this function for each input section,
4377 in the order that input sections are linked into output sections.
4378 Build lists of input sections to determine groupings between which
4379 we may insert linker stubs. */
4381 void
4384 {
4391 {
4395 {
4396 /* Steal the link_sec pointer for our list. */
4397 #define PREV_SEC(sec) (htab->stub_group[(sec)->id].link_sec)
4398 /* This happens to make the list in reverse order,
4399 which we reverse later. */
4402 }
4403 }
4404 }
4406 /* See whether we can group stub sections together. Grouping stub
4407 sections may result in fewer stubs. More importantly, we need to
4408 put all .init* and .fini* stubs at the end of the .init or
4409 .fini output sections respectively, because glibc splits the
4410 _init and _fini functions into multiple parts. Putting a stub in
4411 the middle of a function is not a good idea. */
4413 static void
4415 bfd_size_type stub_group_size,
4416 bfd_boolean stubs_always_after_branch)
4417 {
4420 do
4421 {
4428 /* Reverse the list: we must avoid placing stubs at the
4429 beginning of the section because the beginning of the text
4430 section may be required for an interrupt vector in bare metal
4431 code. */
4432 #define NEXT_SEC PREV_SEC
4435 {
4436 /* Pop from tail. */
4440 /* Push on head. */
4443 }
4446 {
4450 bfd_vma end_of_next;
4454 {
4458 /* End of NEXT is too far from start, so stop. */
4460 /* Add NEXT to the group. */
4462 }
4464 /* OK, the size from the start to the start of CURR is less
4465 than stub_group_size and thus can be handled by one stub
4466 section. (Or the head section is itself larger than
4467 stub_group_size, in which case we may be toast.)
4468 We should really be keeping track of the total size of
4469 stubs added here, as stubs contribute to the final output
4470 section size. */
4471 do
4472 {
4474 /* Set up this stub group. */
4476 }
4479 /* But wait, there's more! Input sections up to stub_group_size
4480 bytes after the stub section can be handled by it too. */
4482 {
4486 {
4489 /* End of NEXT is too far from stubs, so stop. */
4491 /* Add NEXT to the stub group. */
4495 }
4496 }
4498 }
4499 }
4503 #undef PREV_SEC
4504 #undef NEXT_SEC
4505 }
4507 /* Comparison function for sorting/searching relocations relating to Cortex-A8
4508 erratum fix. */
4510 static int
4512 {
4520 else
4522 }
4527 /* Helper function to scan code for sequences which might trigger the Cortex-A8
4528 branch/TLB erratum. Fill in the table described by A8_FIXES_P,
4529 NUM_A8_FIXES_P, A8_FIX_TABLE_SIZE_P. Returns true if an error occurs, false
4530 otherwise. */
4532 static bfd_boolean
4542 {
4555 {
4559 bfd_vma base_vma;
4578 {
4589 /* Span is entirely within a single 4KB region: skip scanning. */
4594 /* Scan for 32-bit Thumb-2 branches which span two 4K regions, where:
4596 * The opcode is BLX.W, BL.W, B.W, Bcc.W
4597 * The branch target is in the same 4KB region as the
4598 first half of the branch.
4599 * The instruction before the branch is a 32-bit
4600 length non-branch instruction. */
4602 {
4611 {
4612 /* Load the rest of the insn (in manual-friendly order). */
4615 /* Encoding T4: B<c>.W. */
4617 /* Encoding T1: BL<c>.W. */
4619 /* Encoding T2: BLX<c>.W. */
4621 /* Encoding T3: B<c>.W (not permitted in IT block). */
4624 }
4629 && insn_32bit
4630 && is_32bit_branch
4631 && last_was_32bit
4633 {
4637 bfd_vma target;
4649 {
4653 /* We don't care about the error returned from this
4654 function, only if there is glue or not. */
4661 /* Keep a simpler condition, for the sake of clarity. */
4667 {
4671 else
4673 }
4674 }
4676 /* Check if we have an offending branch instruction. */
4679 /* We've already made a stub for this instruction, e.g.
4680 it's a long branch or a Thumb->ARM stub. Assume that
4681 stub will suffice to work around the A8 erratum (see
4682 setting of always_after_branch above). */
4683 ;
4685 {
4694 }
4696 {
4716 }
4719 {
4722 /* The original instruction is a BL, but the target is
4723 an ARM instruction. If we were not making a stub,
4724 the BL would have been converted to a BLX. Use the
4725 BLX stub instead in that case. */
4728 {
4732 }
4733 /* Conversely, if the original instruction was
4734 BLX but the target is Thumb mode, use the BL
4735 stub. */
4738 {
4742 }
4747 /* If we found a relocation, use the proper destination,
4748 not the offset in the (unrelocated) instruction.
4749 Note this is always done if we switched the stub type
4750 above. */
4752 offset =
4755 /* If the stub will use a Thumb-mode branch to a
4756 PLT target, redirect it to the preceding Thumb
4757 entry point. */
4763 /* The BLX stub is ARM-mode code. Adjust the offset to
4764 take the different PC value (+8 instead of +4) into
4765 account. */
4770 {
4774 {
4780 }
4783 {
4784 /* If we're doing a subsequent scan,
4785 check if we've found the same fix as
4786 before, and try and reuse the stub
4787 name. */
4791 {
4795 }
4796 }
4799 {
4803 }
4815 num_a8_fixes++;
4816 }
4817 }
4818 }
4823 }
4824 }
4828 }
4835 }
4837 /* Determine and set the size of the stub section for a final link.
4839 The basic idea here is to examine all the relocations looking for
4840 PC-relative calls to a target that is unreachable with a "bl"
4841 instruction. */
4843 bfd_boolean
4847 bfd_signed_vma group_size,
4850 {
4851 bfd_size_type stub_group_size;
4852 bfd_boolean stubs_always_after_branch;
4863 {
4868 }
4870 /* Propagate mach to stub bfd, because it may not have been
4871 finalized when we created stub_bfd. */
4875 /* Stash our params away. */
4881 /* The Cortex-A8 erratum fix depends on stubs not being in the same 4K page
4882 as the first half of a 32-bit branch straddling two 4K pages. This is a
4883 crude way of enforcing that. */
4889 else
4893 {
4894 /* Default values. */
4895 /* Thumb branch range is +-4MB has to be used as the default
4896 maximum size (a given section can contain both ARM and Thumb
4897 code, so the worst case has to be taken into account).
4899 This value is 24K less than that, which allows for 2025
4900 12-byte stubs. If we exceed that, then we will fail to link.
4901 The user will have to relink with an explicit group size
4902 option. */
4904 }
4908 /* If we're applying the cortex A8 fix, we need to determine the
4909 program header size now, because we cannot change it later --
4910 that could alter section placements. Notice the A8 erratum fix
4911 ends up requiring the section addresses to remain unchanged
4912 modulo the page size. That's something we cannot represent
4913 inside BFD, and we don't want to force the section alignment to
4914 be the page size. */
4919 {
4930 {
4937 /* We'll need the symbol table in a second. */
4942 /* Walk over each section attached to the input bfd. */
4946 {
4949 /* If there aren't any relocs, then there's nothing more
4950 to do. */
4956 /* If this section is a link-once section that will be
4957 discarded, then don't create any stubs. */
4962 /* Get the relocs. */
4963 internal_relocs
4969 /* Now examine each relocation. */
4973 {
4978 bfd_vma sym_value;
4979 bfd_vma destination;
4992 {
4994 error_ret_free_internal:
4998 }
5002 hash = elf32_arm_hash_entry
5006 /* Only look for stubs on branch instructions, or
5007 non-relaxed TLSCALL */
5020 : (elf32_arm_local_got_tls_type
5025 /* Now determine the call target, its name, value,
5026 section. */
5034 {
5035 /* A non-relaxed TLS call. The target is the
5036 plt-resident trampoline and nothing to do
5037 with the symbol. */
5044 }
5046 {
5047 /* It's a local symbol. */
5051 {
5052 local_syms
5055 local_syms
5061 }
5070 else
5071 sym_sec =
5075 /* This is an undefined symbol. It can never
5076 be resolved. */
5086 sym_name
5090 }
5091 else
5092 {
5093 /* It's an external symbol. */
5101 {
5108 /* For a destination in a shared library,
5109 use the PLT stub as target address to
5110 decide whether a branch stub is
5111 needed. */
5116 {
5120 destination = (sym_value
5123 }
5128 }
5131 {
5132 /* For a shared library, use the PLT stub as
5133 target address to decide whether a long
5134 branch stub is needed.
5135 For absolute code, they cannot be handled. */
5143 {
5147 destination = (sym_value
5150 }
5151 else
5153 }
5154 else
5155 {
5158 }
5162 }
5164 do
5165 {
5166 /* Determine what (if any) linker stub is needed. */
5174 /* Support for grouping stub sections. */
5177 /* Get the name of this stub. */
5183 /* We've either created a stub for this reloc already,
5184 or we are about to. */
5187 stub_entry = arm_stub_hash_lookup
5191 {
5192 /* The proper stub has already been created. */
5196 }
5199 htab);
5201 {
5204 }
5219 {
5222 }
5224 /* For historical reasons, use the existing names for
5225 ARM-to-Thumb and Thumb-to-ARM stubs. */
5236 else
5238 sym_name);
5241 }
5244 /* Look for relocations which might trigger Cortex-A8
5245 erratum. */
5251 {
5257 {
5258 /* Found a candidate. Note we haven't checked the
5259 destination is within 4K here: if we do so (and
5260 don't create an entry in a8_relocs) we can't tell
5261 that a branch should have been relocated when
5262 scanning later. */
5264 {
5270 }
5280 num_a8_relocs++;
5281 }
5282 }
5283 }
5285 /* We're done with the internal relocs, free them. */
5288 }
5291 {
5292 /* Sort relocs which might apply to Cortex-A8 erratum. */
5297 /* Scan for branches which might trigger Cortex-A8 erratum. */
5304 }
5305 }
5313 /* OK, we've added some stubs. Find out the new size of the
5314 stub sections. */
5318 {
5319 /* Ignore non-stub sections. */
5324 }
5328 /* Add Cortex-A8 erratum veneers to stub section sizes too. */
5331 {
5338 stub_sec->size
5340 NULL);
5341 }
5344 /* Ask the linker to do its stuff. */
5346 }
5348 /* Add stubs for Cortex-A8 erratum fixes now. */
5350 {
5352 {
5365 {
5368 stub_name);
5370 }
5389 }
5391 /* Stash the Cortex-A8 erratum fix array for use later in
5392 elf32_arm_write_section(). */
5395 }
5396 else
5397 {
5400 }
5403 error_ret_free_local:
5405 }
5407 /* Build all the stubs associated with the current output file. The
5408 stubs are kept in a hash table attached to the main linker hash
5409 table. We also set up the .plt entries for statically linked PIC
5410 functions here. This function is called via arm_elf_finish in the
5411 linker. */
5413 bfd_boolean
5415 {
5427 {
5428 bfd_size_type size;
5430 /* Ignore non-stub sections. */
5434 /* Allocate memory to hold the linker stubs. */
5440 }
5442 /* Build the stubs as directed by the stub hash table. */
5446 {
5447 /* Place the cortex a8 stubs last. */
5450 }
5453 }
5455 /* Locate the Thumb encoded calling stub for NAME. */
5461 {
5466 /* We need a pointer to the armelf specific hash table. */
5478 hash = elf_link_hash_lookup
5489 }
5491 /* Locate the ARM encoded calling stub for NAME. */
5497 {
5502 /* We need a pointer to the elfarm specific hash table. */
5514 myh = elf_link_hash_lookup
5525 }
5527 /* ARM->Thumb glue (static images):
5529 .arm
5530 __func_from_arm:
5531 ldr r12, __func_addr
5532 bx r12
5533 __func_addr:
5534 .word func @ behave as if you saw a ARM_32 reloc.
5536 (v5t static images)
5537 .arm
5538 __func_from_arm:
5539 ldr pc, __func_addr
5540 __func_addr:
5541 .word func @ behave as if you saw a ARM_32 reloc.
5543 (relocatable images)
5544 .arm
5545 __func_from_arm:
5546 ldr r12, __func_offset
5547 add r12, r12, pc
5548 bx r12
5549 __func_offset:
5550 .word func - . */
5552 #define ARM2THUMB_STATIC_GLUE_SIZE 12
5557 #define ARM2THUMB_V5_STATIC_GLUE_SIZE 8
5561 #define ARM2THUMB_PIC_GLUE_SIZE 16
5566 /* Thumb->ARM: Thumb->(non-interworking aware) ARM
5568 .thumb .thumb
5569 .align 2 .align 2
5570 __func_from_thumb: __func_from_thumb:
5571 bx pc push {r6, lr}
5572 nop ldr r6, __func_addr
5573 .arm mov lr, pc
5574 b func bx r6
5575 .arm
5576 ;; back_to_thumb
5577 ldmia r13! {r6, lr}
5578 bx lr
5579 __func_addr:
5580 .word func */
5582 #define THUMB2ARM_GLUE_SIZE 8
5587 #define VFP11_ERRATUM_VENEER_SIZE 8
5589 #define ARM_BX_VENEER_SIZE 12
5594 #ifndef ELFARM_NABI_C_INCLUDED
5595 static void
5597 {
5602 {
5603 /* Do not include empty glue sections in the output. */
5605 {
5609 }
5611 }
5622 }
5624 bfd_boolean
5626 {
5634 ARM2THUMB_GLUE_SECTION_NAME);
5638 THUMB2ARM_GLUE_SECTION_NAME);
5642 VFP11_ERRATUM_VENEER_SECTION_NAME);
5646 ARM_BX_GLUE_SECTION_NAME);
5649 }
5651 /* Allocate space and symbols for calling a Thumb function from Arm mode.
5652 returns the symbol identifying the stub. */
5657 {
5664 bfd_vma val;
5665 bfd_size_type size;
5671 s = bfd_get_section_by_name
5683 myh = elf_link_hash_lookup
5687 {
5688 /* We've already seen this guy. */
5691 }
5693 /* The only trick here is using hash_table->arm_glue_size as the value.
5694 Even though the section isn't allocated yet, this is where we will be
5695 putting it. The +1 on the value marks that the stub has not been
5696 output yet - not that it is a Thumb function. */
5714 else
5721 }
5723 /* Allocate space for ARMv4 BX veneers. */
5725 static void
5727 {
5733 bfd_vma val;
5735 /* BX PC does not need a veneer. */
5743 /* Check if this veneer has already been allocated. */
5747 s = bfd_get_section_by_name
5752 /* Add symbol for veneer. */
5760 myh = elf_link_hash_lookup
5778 }
5781 /* Add an entry to the code/data map for section SEC. */
5783 static void
5785 {
5790 {
5795 }
5800 {
5805 }
5808 {
5811 }
5812 }
5815 /* Record information about a VFP11 denorm-erratum veneer. Only ARM-mode
5816 veneers are handled for now. */
5818 static bfd_vma
5824 {
5830 bfd_vma val;
5838 s = bfd_get_section_by_name
5853 myh = elf_link_hash_lookup
5868 /* Link veneer back to calling location. */
5882 /* A symbol for the return from the veneer. */
5886 myh = elf_link_hash_lookup
5903 /* Generate a mapping symbol for the veneer section, and explicitly add an
5904 entry for that symbol to the code/data map for the section. */
5906 {
5908 /* FIXME: Creates an ARM symbol. Thumb mode will need attention if it
5909 ever requires this erratum fix. */
5919 /* The elf32_arm_init_maps function only cares about symbols from input
5920 BFDs. We must make a note of this generated mapping symbol
5921 ourselves so that code byteswapping works properly in
5922 elf32_arm_write_section. */
5924 }
5930 /* The offset of the veneer. */
5932 }
5934 #define ARM_GLUE_SECTION_FLAGS \
5935 (SEC_ALLOC | SEC_LOAD | SEC_HAS_CONTENTS | SEC_IN_MEMORY | SEC_CODE \
5936 | SEC_READONLY | SEC_LINKER_CREATED)
5938 /* Create a fake section for use by the ARM backend of the linker. */
5940 static bfd_boolean
5942 {
5947 /* Already made. */
5956 /* Set the gc mark to prevent the section from being removed by garbage
5957 collection, despite the fact that no relocs refer to this section. */
5961 }
5963 /* Add the glue sections to ABFD. This function is called from the
5964 linker scripts in ld/emultempl/{armelf}.em. */
5966 bfd_boolean
5969 {
5970 /* If we are only performing a partial
5971 link do not bother adding the glue. */
5979 }
5981 /* Select a BFD to be used to hold the sections used by the glue code.
5982 This function is called from the linker scripts in ld/emultempl/
5983 {armelf/pe}.em. */
5985 bfd_boolean
5987 {
5990 /* If we are only performing a partial link
5991 do not bother getting a bfd to hold the glue. */
5995 /* Make sure we don't attach the glue sections to a dynamic object. */
6004 /* Save the bfd for later use. */
6008 }
6010 static void
6012 {
6016 Tag_CPU_arch);
6019 {
6022 }
6023 else
6024 {
6027 }
6028 }
6030 bfd_boolean
6033 {
6042 /* If we are only performing a partial link do not bother
6043 to construct any glue. */
6047 /* Here we have a bfd that is to be included on the link. We have a
6048 hook to do reloc rummaging, before section sizes are nailed down. */
6055 {
6057 abfd);
6059 }
6061 /* PR 5398: If we have not decided to include any loadable sections in
6062 the output then we will not have a glue owner bfd. This is OK, it
6063 just means that there is nothing else for us to do here. */
6067 /* Rummage around all the relocs and map the glue vectors. */
6074 {
6083 /* Load the relocs. */
6084 internal_relocs
6092 {
6101 /* These are the only relocation types we care about. */
6106 /* Get the section contents if we haven't done so already. */
6108 {
6109 /* Get cached copy if it exists. */
6112 else
6113 {
6114 /* Go get them off disk. */
6117 }
6118 }
6121 {
6127 }
6129 /* If the relocation is not against a symbol it cannot concern us. */
6132 /* We don't care about local symbols. */
6136 /* This is an external symbol. */
6141 /* If the relocation is against a static symbol it must be within
6142 the current section and so cannot be a cross ARM/Thumb relocation. */
6146 /* If the call will go through a PLT entry then we do not need
6147 glue. */
6152 {
6154 /* This one is a call from arm code. We need to look up
6155 the target of the call. If it is a thumb target, we
6156 insert glue. */
6163 }
6164 }
6175 }
6179 error_return:
6188 }
6189 #endif
6192 /* Initialise maps of ARM/Thumb/data for input BFDs. */
6194 void
6196 {
6201 /* PR 7093: Make sure that we are dealing with an arm elf binary. */
6211 /* Obtain a buffer full of symbols for this BFD. The hdr->sh_info field
6212 should contain the number of local symbols, which should come before any
6213 global symbols. Mapping symbols are always local. */
6215 NULL);
6217 /* No internal symbols read? Skip this BFD. */
6222 {
6229 {
6234 BFD_ARM_SPECIAL_SYM_TYPE_MAP))
6236 }
6237 }
6238 }
6241 /* Auto-select enabling of Cortex-A8 erratum fix if the user didn't explicitly
6242 say what they wanted. */
6244 void
6246 {
6254 {
6255 /* Turn on Cortex-A8 erratum workaround for ARMv7-A. */
6260 else
6262 }
6263 }
6266 void
6268 {
6274 /* We assume that ARMv7+ does not need the VFP11 denorm erratum fix. */
6276 {
6278 {
6285 /* Give a warning, but do as the user requests anyway. */
6288 }
6289 }
6291 /* For earlier architectures, we might need the workaround, but do not
6292 enable it by default. If users is running with broken hardware, they
6293 must enable the erratum fix explicitly. */
6295 }
6298 enum bfd_arm_vfp11_pipe
6299 {
6300 VFP11_FMAC,
6301 VFP11_LS,
6302 VFP11_DS,
6303 VFP11_BAD
6304 };
6306 /* Return a VFP register number. This is encoded as RX:X for single-precision
6307 registers, or X:RX for double-precision registers, where RX is the group of
6308 four bits in the instruction encoding and X is the single extension bit.
6309 RX and X fields are specified using their lowest (starting) bit. The return
6310 value is:
6312 0...31: single-precision registers s0...s31
6313 32...63: double-precision registers d0...d31.
6315 Although X should be zero for VFP11 (encoding d0...d15 only), we might
6316 encounter VFP3 instructions, so we allow the full range for DP registers. */
6318 static unsigned int
6321 {
6324 else
6326 }
6328 /* Set bits in *WMASK according to a register number REG as encoded by
6329 bfd_arm_vfp11_regno(). Ignore d16-d31. */
6331 static void
6333 {
6338 }
6340 /* Return TRUE if WMASK overwrites anything in REGS. */
6342 static bfd_boolean
6344 {
6348 {
6361 }
6364 }
6366 /* In this function, we're interested in two things: finding input registers
6367 for VFP data-processing instructions, and finding the set of registers which
6368 arbitrary VFP instructions may write to. We use a 32-bit unsigned int to
6369 hold the written set, so FLDM etc. are easy to deal with (we're only
6370 interested in 32 SP registers or 16 dp registers, due to the VFP version
6371 implemented by the chip in question). DP registers are marked by setting
6372 both SP registers in the write mask). */
6374 static enum bfd_arm_vfp11_pipe
6377 {
6382 {
6392 {
6414 vfp_binop:
6422 {
6427 {
6441 /* These instructions will not bounce due to underflow. */
6447 /* fsqrt cannot underflow, but it can (perhaps) overwrite
6448 registers to cause the erratum in previous instructions. */
6454 {
6459 /* Only FCVTSD can underflow. */
6466 }
6471 }
6472 }
6477 }
6478 }
6479 /* Two-register transfer. */
6481 {
6485 {
6488 else
6489 {
6492 }
6493 }
6496 }
6498 {
6503 {
6510 {
6518 }
6528 }
6531 }
6532 /* Single-register transfer. Note L==0. */
6534 {
6539 {
6542 /* Mark fmdhr and fmdlr as writing to the whole of the DP
6543 destination register. I don't know if this is exactly right,
6544 but it is the conservative choice. */
6550 }
6553 }
6556 }
6562 /* Look for potentially-troublesome code sequences which might trigger the
6563 VFP11 denormal/antidependency erratum. See, e.g., the ARM1136 errata sheet
6564 (available from ARM) for details of the erratum. A short version is
6565 described in ld.texinfo. */
6567 bfd_boolean
6569 {
6580 /* We use a simple FSM to match troublesome VFP11 instruction sequences.
6581 The states transition as follows:
6583 0 -> 1 (vector) or 0 -> 2 (scalar)
6584 A VFP FMAC-pipeline instruction has been seen. Fill
6585 regs[0]..regs[numregs-1] with its input operands. Remember this
6586 instruction in 'first_fmac'.
6588 1 -> 2
6589 Any instruction, except for a VFP instruction which overwrites
6590 regs[*].
6592 1 -> 3 [ -> 0 ] or
6593 2 -> 3 [ -> 0 ]
6594 A VFP instruction has been seen which overwrites any of regs[*].
6595 We must make a veneer! Reset state to 0 before examining next
6596 instruction.
6598 2 -> 0
6599 If we fail to match anything in state 2, reset to state 0 and reset
6600 the instruction pointer to the instruction after 'first_fmac'.
6602 If the VFP11 vector mode is in use, there must be at least two unrelated
6603 instructions between anti-dependent VFP11 instructions to properly avoid
6604 triggering the erratum, hence the use of the extra state 1. */
6606 /* If we are only performing a partial link do not bother
6607 to construct any glue. */
6611 /* Skip if this bfd does not correspond to an ELF image. */
6615 /* We should have chosen a fix type by the time we get here. */
6621 /* Skip this BFD if it corresponds to an executable or dynamic object. */
6626 {
6630 /* If we don't have executable progbits, we're not interested in this
6631 section. Also skip if section is to be excluded. */
6651 elf32_arm_compare_mapping);
6654 {
6660 /* FIXME: Only ARM mode is supported at present. We may need to
6661 support Thumb-2 mode also at some point. */
6666 {
6681 {
6685 /* I'm assuming the VFP11 erratum can trigger with denorm
6686 operands on either the FMAC or the DS pipeline. This might
6687 lead to slightly overenthusiastic veneer insertion. */
6689 {
6693 }
6697 {
6700 other_regs,
6704 numregs))
6706 else
6708 }
6712 {
6715 other_regs,
6719 numregs))
6721 else
6722 {
6725 }
6726 }
6731 }
6734 {
6743 {
6750 }
6753 first_fmac);
6761 }
6764 }
6765 }
6771 }
6775 error_return:
6781 }
6783 /* Find virtual-memory addresses for VFP11 erratum veneers and return locations
6784 after sections have been laid out, using specially-named symbols. */
6786 void
6789 {
6797 /* Skip if this bfd does not correspond to an ELF image. */
6809 {
6814 {
6816 bfd_vma vma;
6819 {
6822 /* Find veneer symbol. */
6826 myh = elf_link_hash_lookup
6842 /* Find return location. */
6846 myh = elf_link_hash_lookup
6862 }
6863 }
6864 }
6867 }
6870 /* Set target relocation values needed during linking. */
6872 void
6879 bfd_arm_vfp11_fix vfp11_fix,
6883 {
6897 else
6898 {
6900 target2_type);
6901 }
6912 }
6914 /* Replace the target offset of a Thumb bl or b.w instruction. */
6916 static void
6918 {
6919 bfd_vma upper;
6920 bfd_vma lower;
6937 }
6939 /* Thumb code calling an ARM function. */
6941 static int
6949 bfd_vma offset,
6950 bfd_signed_vma addend,
6951 bfd_vma val,
6953 {
6955 bfd_vma my_offset;
6971 THUMB2ARM_GLUE_SECTION_NAME);
6978 {
6982 {
6989 }
7000 ret_offset =
7001 /* Address of destination of the stub. */
7004 /* Offset from the start of the current section
7005 to the start of the stubs. */
7007 /* Offset of the start of this stub from the start of the stubs. */
7008 + my_offset
7009 /* Address of the start of the current section. */
7011 /* The branch instruction is 4 bytes into the stub. */
7013 /* ARM branches work from the pc of the instruction + 8. */
7019 }
7023 /* Now go back and fix up the original BL insn to point to here. */
7024 ret_offset =
7025 /* Address of where the stub is located. */
7027 /* Address of where the BL is located. */
7030 /* Addend in the relocation. */
7031 - addend
7032 /* Biassing for PC-relative addressing. */
7038 }
7040 /* Populate an Arm to Thumb stub. Returns the stub symbol. */
7048 bfd_vma val,
7051 {
7052 bfd_vma my_offset;
7068 {
7072 {
7077 }
7084 {
7085 /* For relocatable objects we can't use absolute addresses,
7086 so construct the address from a relative offset. */
7087 /* TODO: If the offset is small it's probably worth
7088 constructing the address with adds. */
7095 /* Adjust the offset by 4 for the position of the add,
7096 and 8 for the pipeline offset. */
7103 }
7105 {
7109 /* It's a thumb address. Add the low order bit. */
7112 }
7113 else
7114 {
7121 /* It's a thumb address. Add the low order bit. */
7126 }
7127 }
7132 }
7134 /* Arm code calling a Thumb function. */
7136 static int
7144 bfd_vma offset,
7145 bfd_signed_vma addend,
7146 bfd_vma val,
7148 {
7150 bfd_vma my_offset;
7161 ARM2THUMB_GLUE_SECTION_NAME);
7175 /* Somehow these are both 4 too far, so subtract 8. */
7177 + my_offset
7189 }
7191 /* Populate Arm stub for an exported Thumb function. */
7193 static bfd_boolean
7195 {
7202 bfd_vma val;
7206 /* Allocate stubs for exported Thumb functions on v4t. */
7215 ARM2THUMB_GLUE_SECTION_NAME);
7233 }
7235 /* Populate ARMv4 BX veneers. Returns the absolute adress of the veneer. */
7237 static bfd_vma
7239 {
7241 bfd_vma glue_addr;
7250 ARM_BX_GLUE_SECTION_NAME);
7260 {
7266 }
7269 }
7271 /* Generate Arm stubs for exported Thumb symbols. */
7272 static void
7275 {
7279 /* Ignore this if we are not called by the ELF backend linker. */
7286 /* If blx is available then exported Thumb symbols are OK and there is
7287 nothing to do. */
7292 link_info);
7293 }
7295 /* Reserve space for COUNT dynamic relocations in relocation selection
7296 SRELOC. */
7298 static void
7300 bfd_size_type count)
7301 {
7309 }
7311 /* Reserve space for COUNT R_ARM_IRELATIVE relocations. If the link is
7312 dynamic, the relocations should go in SRELOC, otherwise they should
7313 go in the special .rel.iplt section. */
7315 static void
7317 bfd_size_type count)
7318 {
7324 else
7325 {
7328 }
7329 }
7331 /* Add relocation REL to the end of relocation section SRELOC. */
7333 static void
7336 {
7351 }
7353 /* Allocate room for a PLT entry described by ROOT_PLT and ARM_PLT.
7354 IS_IPLT_ENTRY says whether the entry belongs to .iplt rather than
7355 to .plt. */
7357 static void
7359 bfd_boolean is_iplt_entry,
7362 {
7370 {
7374 /* Allocate room for an R_ARM_IRELATIVE relocation in .rel.iplt. */
7376 }
7377 else
7378 {
7382 /* Allocate room for an R_JUMP_SLOT relocation in .rel.plt. */
7385 /* If this is the first .plt entry, make room for the special
7386 first entry. */
7389 }
7391 /* Allocate the PLT entry itself, including any leading Thumb stub. */
7398 {
7399 /* We also need to make an entry in the .got.plt section, which
7400 will be placed in the .got section by the linker script. */
7403 }
7404 }
7406 /* Fill in a PLT entry and its associated GOT slot. If DYNINDX == -1,
7407 the entry lives in .iplt and resolves to (*SYM_VALUE)().
7408 Otherwise, DYNINDX is the index of the symbol in the dynamic
7409 symbol table and SYM_VALUE is undefined.
7411 ROOT_PLT points to the offset of the PLT entry from the start of its
7412 section (.iplt or .plt). ARM_PLT points to the symbol's ARM-specific
7413 bookkeeping information. */
7415 static void
7420 {
7426 bfd_vma plt_index;
7427 Elf_Internal_Rela rel;
7428 bfd_vma plt_header_size;
7429 bfd_vma got_header_size;
7433 /* Pick the appropriate sections and sizes. */
7435 {
7440 /* There are no reserved entries in .igot.plt, and no special
7441 first entry in .iplt. */
7444 }
7445 else
7446 {
7453 }
7456 /* Fill in the entry in the procedure linkage table. */
7458 {
7467 /* Fill in the entry in the .rel.plt section. */
7473 /* Get the index in the procedure linkage table which
7474 corresponds to this symbol. This is the index of this symbol
7475 in all the symbols for which we are making plt entries. The
7476 first entry in the procedure linkage table is reserved. */
7479 }
7480 else
7481 {
7488 /* Get the offset into the .(i)got.plt table of the entry that
7489 corresponds to this function. */
7492 /* Get the index in the procedure linkage table which
7493 corresponds to this symbol. This is the index of this symbol
7494 in all the symbols for which we are making plt entries.
7495 After the reserved .got.plt entries, all symbols appear in
7496 the same order as in .plt. */
7499 /* Calculate the address of the GOT entry. */
7504 /* ...and the address of the PLT entry. */
7511 {
7513 bfd_vma val;
7516 {
7524 else
7526 }
7527 }
7529 {
7531 bfd_vma val;
7534 {
7544 else
7546 }
7551 /* Create the .rela.plt.unloaded R_ARM_ABS32 relocation
7552 referencing the GOT for this PLT entry. */
7559 /* Create the R_ARM_ABS32 relocation referencing the
7560 beginning of the PLT for this GOT entry. */
7565 }
7566 else
7567 {
7568 /* Calculate the displacement between the PLT slot and the
7569 entry in the GOT. The eight-byte offset accounts for the
7570 value produced by adding to pc in the first instruction
7571 of the PLT stub. */
7577 {
7582 }
7596 #ifdef FOUR_WORD_PLT
7598 #endif
7599 }
7601 /* Fill in the entry in the .rel(a).(i)plt section. */
7605 {
7606 /* .igot.plt entries use IRELATIVE relocations against SYM_VALUE.
7607 The dynamic linker or static executable then calls SYM_VALUE
7608 to determine the correct run-time value of the .igot.plt entry. */
7611 }
7612 else
7613 {
7617 }
7619 /* Fill in the entry in the global offset table. */
7622 }
7626 }
7628 /* Some relocations map to different relocations depending on the
7629 target. Return the real relocation. */
7631 static int
7634 {
7636 {
7640 else
7648 }
7649 }
7651 /* Return the base VMA address which should be subtracted from real addresses
7652 when resolving @dtpoff relocation.
7653 This is PT_TLS segment p_vaddr. */
7655 static bfd_vma
7657 {
7658 /* If tls_sec is NULL, we should have signalled an error already. */
7662 }
7664 /* Return the relocation value for @tpoff relocation
7665 if STT_TLS virtual address is ADDRESS. */
7667 static bfd_vma
7669 {
7671 bfd_vma base;
7673 /* If tls_sec is NULL, we should have signalled an error already. */
7678 }
7680 /* Perform an R_ARM_ABS12 relocation on the field pointed to by DATA.
7681 VALUE is the relocation value. */
7683 static bfd_reloc_status_type
7685 {
7692 }
7694 /* Handle TLS relaxations. Relaxing is possible for symbols that use
7695 R_ARM_GOTDESC, R_ARM_{,THM_}TLS_CALL or
7696 R_ARM_{,THM_}TLS_DESCSEQ relocations, during a static link.
7698 Return bfd_reloc_ok if we're done, bfd_reloc_continue if the caller
7699 is to then call final_link_relocate. Return other values in the
7700 case of error.
7702 FIXME:When --emit-relocs is in effect, we'll emit relocs describing
7703 the pre-relaxed code. It would be nice if the relocs were updated
7704 to match the optimization. */
7706 static bfd_reloc_status_type
7710 {
7714 {
7721 else
7722 {
7726 else
7728 }
7733 /* Thumb insn. */
7736 {
7738 /* nop */
7740 }
7742 {
7744 /* nop */
7746 else
7747 /* ldr rx,[ry] */
7749 }
7751 {
7753 /* nop */
7755 else
7756 /* mov r0, rx */
7759 }
7760 else
7761 {
7763 /* It's a 32 bit instruction, fetch the rest of it for
7764 error generation. */
7771 }
7775 /* arm insn. */
7778 {
7780 /* mov rx, ry */
7783 }
7785 {
7787 /* nop */
7789 else
7790 /* ldr rx,[ry] */
7793 }
7795 {
7797 /* nop */
7799 else
7800 /* mov r0, rx */
7803 }
7804 else
7805 {
7810 }
7814 /* GD->IE relaxation, turn the instruction into 'nop' or
7815 'ldr r0, [pc,r0]' */
7821 /* GD->IE relaxation */
7823 /* add r0,pc; ldr r0, [r0] */
7826 /* nop.w */
7828 else
7829 /* nop; nop */
7835 }
7837 }
7839 /* For a given value of n, calculate the value of G_n as required to
7840 deal with group relocations. We return it in the form of an
7841 encoded constant-and-rotation, together with the final residual. If n is
7842 specified as less than zero, then final_residual is filled with the
7843 input value and no further action is performed. */
7845 static bfd_vma
7847 {
7849 bfd_vma g_n;
7854 {
7857 /* Calculate which part of the value to mask. */
7860 else
7861 {
7864 /* Determine the most significant bit in the residual and
7865 align the resulting value to a 2-bit boundary. */
7870 /* The desired shift is now (msb - 6), or zero, whichever
7871 is the greater. */
7875 }
7877 /* Calculate g_n in 32-bit as well as encoded constant+rotation form. */
7882 /* Calculate the residual for the next time around. */
7884 }
7889 }
7891 /* Given an ARM instruction, determine whether it is an ADD or a SUB.
7892 Returns 1 if it is an ADD, -1 if it is a SUB, and 0 otherwise. */
7894 static int
7896 {
7906 }
7908 /* Perform a relocation as part of a final link. */
7910 static bfd_reloc_status_type
7917 bfd_vma value,
7926 {
7936 bfd_vma addend;
7937 bfd_signed_vma signed_addend;
7939 bfd_vma dynreloc_value;
7944 bfd_vma plt_offset;
7945 bfd_vma gotplt_offset;
7946 bfd_boolean has_iplt_entry;
7954 /* Some relocation types map to different relocations depending on the
7955 target. We pick the right one here. */
7958 /* It is possible to have linker relaxations on some TLS access
7959 models. Update our information here. */
7965 /* If the start address has been set, then set the EF_ARM_HASENTRY
7966 flag. Setting this more than once is redundant, but the cost is
7967 not too high, and it keeps the code simple.
7969 The test is done here, rather than somewhere else, because the
7970 start address is only set just before the final link commences.
7972 Note - if the user deliberately sets a start address of 0, the
7973 flag will not be set. */
7984 else
7990 {
7994 {
7998 }
7999 else
8001 }
8002 else
8005 /* Record the symbol information that should be used in dynamic
8006 relocations. */
8012 /* Find out whether the symbol has a PLT. Set ST_VALUE, BRANCH_TYPE and
8013 VALUE appropriately for relocations that we resolve at link time. */
8017 {
8022 {
8026 /* Populate .iplt entries here, because not all of them will
8027 be seen by finish_dynamic_symbol. The lower bit is set if
8028 we have already populated the entry. */
8030 plt_offset--;
8031 else
8032 {
8036 }
8038 /* Static relocations always resolve to the .iplt entry. */
8045 /* If there are non-call relocations that resolve to the .iplt
8046 entry, then all dynamic ones must too. */
8048 {
8051 }
8052 }
8053 else
8054 /* We populate the .plt entry in finish_dynamic_symbol. */
8056 }
8057 else
8058 {
8062 }
8065 {
8067 /* We don't need to find a value for this symbol. It's just a
8068 marker. */
8086 /* Handle relocations which should use the PLT entry. ABS32/REL32
8087 will use the symbol's value, which may point to a PLT entry, but we
8088 don't need to handle that here. If we created a PLT entry, all
8089 branches in this object should go to it, except if the PLT is too
8090 far away, in which case a long branch stub should be inserted. */
8097 {
8098 /* If we've created a .plt section, and assigned a PLT entry
8099 to this function, it must either be a STT_GNU_IFUNC reference
8100 or not be known to bind locally. In other cases, we should
8101 have cleared the PLT entry by now. */
8111 }
8113 /* When generating a shared object or relocatable executable, these
8114 relocations are copied into the output file to be resolved at
8115 run time. */
8132 {
8133 Elf_Internal_Rela outrel;
8139 {
8145 }
8169 else
8170 {
8173 /* This symbol is local, or marked to become local. */
8176 {
8179 /* On Symbian OS, the data segment and text segement
8180 can be relocated independently. Therefore, we
8181 must indicate the segment to which this
8182 relocation is relative. The BPABI allows us to
8183 use any symbol in the right segment; we just use
8184 the section symbol as it is convenient. (We
8185 cannot use the symbol given by "h" directly as it
8186 will not appear in the dynamic symbol table.)
8188 Note that the dynamic linker ignores the section
8189 symbol value, so we don't subtract osec->vma
8190 from the emitted reloc addend. */
8193 else
8197 {
8203 else
8206 }
8208 }
8209 else
8210 /* On SVR4-ish systems, the dynamic loader cannot
8211 relocate the text and data segments independently,
8212 so the symbol does not matter. */
8215 /* We have an STT_GNU_IFUNC symbol that doesn't resolve
8216 to the .iplt entry. Instead, every non-call reference
8217 must use an R_ARM_IRELATIVE relocation to obtain the
8218 correct run-time address. */
8220 else
8224 else
8226 }
8230 /* If this reloc is against an external symbol, we do not want to
8231 fiddle with the addend. Otherwise, we need to include the symbol
8232 value so that it becomes an addend for the dynamic reloc. */
8239 }
8241 {
8250 {
8254 {
8255 /* Check for Arm calling Arm function. */
8256 /* FIXME: Should we translate the instruction into a BL
8257 instruction instead ? */
8261 input_bfd,
8263 }
8265 {
8266 /* Check for Arm calling Thumb function. */
8268 {
8273 error_message))
8275 else
8277 }
8278 }
8280 /* Check if a stub has to be inserted because the
8281 destination is too far or we are changing mode. */
8285 {
8296 {
8297 /* The target is out of reach, so redirect the
8298 branch to the local stub for this function. */
8302 stub_type);
8303 {
8311 }
8312 }
8313 else
8314 {
8315 /* If the call goes through a PLT entry, make sure to
8316 check distance to the right destination address. */
8318 {
8323 /* The PLT entry is in ARM mode, regardless of the
8324 target function. */
8326 }
8327 }
8328 }
8330 /* The ARM ELF ABI says that this reloc is computed as: S - P + A
8331 where:
8332 S is the address of the symbol in the relocation.
8333 P is address of the instruction being relocated.
8334 A is the addend (extracted from the instruction) in bytes.
8336 S is held in 'value'.
8337 P is the base address of the section containing the
8338 instruction plus the offset of the reloc into that
8339 section, ie:
8340 (input_section->output_section->vma +
8341 input_section->output_offset +
8342 rel->r_offset).
8343 A is the addend, converted into bytes, ie:
8344 (signed_addend * 4)
8346 Note: None of these operations have knowledge of the pipeline
8347 size of the processor, thus it is up to the assembler to
8348 encode this information into the addend. */
8354 else
8355 /* RELA addends do not have to be adjusted by howto->size. */
8361 /* A branch to an undefined weak symbol is turned into a jump to
8362 the next instruction unless a PLT entry will be created.
8363 Do the same for local undefined symbols (but not for STN_UNDEF).
8364 The jump to the next instruction is optimized as a NOP depending
8365 on the architecture. */
8369 {
8374 else
8376 }
8377 else
8378 {
8379 /* Perform a signed range check. */
8390 {
8391 /* Set the H bit in the BLX instruction. */
8393 {
8396 else
8398 }
8400 /* Select the correct instruction (BL or BLX). */
8401 /* Only if we are not handling a BL to a stub. In this
8402 case, mode switching is performed by the stub. */
8406 {
8409 }
8410 }
8411 }
8412 }
8444 {
8445 /* Check for overflow. */
8448 }
8454 }
8462 /* There is no way to tell whether the user intended to use a signed or
8463 unsigned addend. When checking for overflow we accept either,
8464 as specified by the AAELF. */
8474 /* See comment for R_ARM_ABS8. */
8482 /* Support ldr and str instructions for the thumb. */
8484 {
8485 /* Need to refetch addend. */
8487 /* ??? Need to determine shift amount from operand size. */
8489 }
8492 /* ??? Isn't value unsigned? */
8496 /* ??? Value needs to be properly shifted into place first. */
8502 /* Corresponds to: addw.w reg, pc, #offset (and similarly for subw). */
8503 {
8504 bfd_vma insn;
8505 bfd_signed_vma relocation;
8511 {
8516 }
8538 }
8541 /* PR 10073: This reloc is not generated by the GNU toolchain,
8542 but it is supported for compatibility with third party libraries
8543 generated by other compilers, specifically the ARM/IAR. */
8544 {
8545 bfd_vma insn;
8546 bfd_signed_vma relocation;
8560 /* We do not check for overflow of this reloc. Although strictly
8561 speaking this is incorrect, it appears to be necessary in order
8562 to work with IAR generated relocs. Since GCC and GAS do not
8563 generate R_ARM_THM_PC8 relocs, the lack of a check should not be
8564 a problem for them. */
8572 }
8575 /* Corresponds to: ldr.w reg, [pc, #offset]. */
8576 {
8577 bfd_vma insn;
8578 bfd_signed_vma relocation;
8584 {
8588 }
8608 }
8613 /* Thumb BL (branch long instruction). */
8614 {
8615 bfd_vma relocation;
8616 bfd_vma reloc_sign;
8620 bfd_signed_vma reloc_signed_max;
8621 bfd_signed_vma reloc_signed_min;
8622 bfd_vma check;
8623 bfd_signed_vma signed_check;
8627 /* A branch to an undefined weak symbol is turned into a jump to
8628 the next instruction unless a PLT entry will be created.
8629 The jump to the next instruction is optimized as a NOP.W for
8630 Thumb-2 enabled architectures. */
8633 {
8635 {
8638 }
8639 else
8640 {
8643 }
8645 }
8647 /* Fetch the addend. We use the Thumb-2 encoding (backwards compatible
8648 with Thumb-1) involving the J1 and J2 bits. */
8650 {
8660 /* Sign extend. */
8664 }
8667 {
8668 /* Check for Thumb to Thumb call. */
8669 /* FIXME: Should we translate the instruction into a BL
8670 instruction instead ? */
8674 input_bfd,
8676 }
8677 else
8678 {
8679 /* If it is not a call to Thumb, assume call to Arm.
8680 If it is a call relative to a section name, then it is not a
8681 function call at all, but rather a long jump. Calls through
8682 the PLT do not require stubs. */
8684 {
8686 {
8687 /* Convert BL to BLX. */
8689 }
8692 {
8696 error_message))
8698 else
8700 }
8701 }
8705 {
8706 /* Make sure this is a BL. */
8708 }
8709 }
8713 {
8714 /* Check if a stub has to be inserted because the destination
8715 is too far. */
8727 {
8728 /* The target is out of reach or we are changing modes, so
8729 redirect the branch to the local stub for this
8730 function. */
8734 stub_type);
8736 {
8743 }
8745 /* If this call becomes a call to Arm, force BLX. */
8747 {
8752 }
8753 }
8754 }
8756 /* Handle calls via the PLT. */
8758 {
8764 {
8765 /* If the Thumb BLX instruction is available, convert
8766 the BL to a BLX instruction to call the ARM-mode
8767 PLT entry. */
8770 }
8771 else
8772 {
8773 /* Target the Thumb stub before the ARM PLT entry. */
8776 }
8778 }
8788 /* If this is a signed value, the rightshift just dropped
8789 leading 1 bits (assuming twos complement). */
8792 else
8795 /* Calculate the permissable maximum and minimum values for
8796 this relocation according to whether we're relocating for
8797 Thumb-2 or not. */
8804 /* Assumes two's complement. */
8809 /* For a BLX instruction, make sure that the relocation is rounded up
8810 to a word boundary. This follows the semantics of the instruction
8811 which specifies that bit 1 of the target address will come from bit
8812 1 of the base address. */
8815 /* Put RELOCATION back into the insn. Assumes two's complement.
8816 We use the Thumb-2 encoding, which is safe even if dealing with
8817 a Thumb-1 instruction by virtue of our overflow check above. */
8827 /* Put the relocated value back in the object file: */
8832 }
8836 /* Thumb32 conditional branch instruction. */
8837 {
8838 bfd_vma relocation;
8844 bfd_signed_vma signed_check;
8846 /* Need to refetch the addend, reconstruct the top three bits,
8847 and squish the two 11 bit pieces together. */
8849 {
8863 }
8865 /* Handle calls via the PLT. */
8867 {
8871 /* Target the Thumb stub before the ARM PLT entry. */
8874 }
8876 /* ??? Should handle interworking? GCC might someday try to
8877 use this for tail calls. */
8888 /* Put RELOCATION back into the insn. */
8889 {
8898 }
8900 /* Put the relocated value back in the object file: */
8905 }
8910 /* Thumb B (branch) instruction). */
8911 {
8912 bfd_signed_vma relocation;
8915 bfd_signed_vma signed_check;
8917 /* CZB cannot jump backward. */
8922 {
8923 /* Need to refetch addend. */
8926 {
8930 }
8931 else
8933 /* The value in the insn has been right shifted. We need to
8934 undo this, so that we can perform the address calculation
8935 in terms of bytes. */
8937 }
8949 else
8955 /* Assumes two's complement. */
8960 }
8965 {
8966 bfd_vma insn;
8967 bfd_vma relocation;
8971 {
8972 /* Extract the addend. */
8975 }
8985 }
8993 /* Relocation is relative to the start of the
8994 global offset table. */
9000 /* If we are addressing a Thumb function, we need to adjust the
9001 address by one, so that attempts to call the function pointer will
9002 correctly interpret it as Thumb code. */
9006 /* Note that sgot->output_offset is not involved in this
9007 calculation. We always want the start of .got. If we
9008 define _GLOBAL_OFFSET_TABLE in a different way, as is
9009 permitted by the ABI, we might have to change this
9010 calculation. */
9017 /* Use global offset table as symbol value. */
9031 /* Relocation is to the entry for this symbol in the
9032 global offset table. */
9039 {
9040 /* We have a relocation against a locally-binding STT_GNU_IFUNC
9041 symbol, and the relocation resolves directly to the runtime
9042 target rather than to the .iplt entry. This means that any
9043 .got entry would be the same value as the .igot.plt entry,
9044 so there's no point creating both. */
9047 }
9049 {
9050 bfd_vma off;
9055 {
9056 /* We have already processsed one GOT relocation against
9057 this symbol. */
9062 }
9063 else
9064 {
9065 Elf_Internal_Rela outrel;
9068 {
9069 /* If the symbol doesn't resolve locally in a static
9070 object, we have an undefined reference. If the
9071 symbol doesn't resolve locally in a dynamic object,
9072 it should be resolved by the dynamic linker. */
9074 {
9077 }
9078 else
9081 }
9082 else
9083 {
9088 else
9091 }
9093 /* The GOT entry is initialized to zero by default.
9094 See if we should install a different value. */
9097 {
9101 }
9104 {
9109 }
9111 }
9113 }
9114 else
9115 {
9116 bfd_vma off;
9123 /* The offset must always be a multiple of 4. We use the
9124 least significant bit to record whether we have already
9125 generated the necessary reloc. */
9128 else
9129 {
9134 {
9135 Elf_Internal_Rela outrel;
9143 else
9146 }
9149 }
9152 }
9168 {
9169 bfd_vma off;
9178 else
9179 {
9180 /* If we don't know the module number, create a relocation
9181 for it. */
9183 {
9184 Elf_Internal_Rela outrel;
9199 }
9200 else
9204 }
9212 }
9221 {
9229 {
9230 bfd_boolean dyn;
9235 {
9238 }
9242 }
9243 else
9244 {
9249 }
9251 /* Linker relaxations happens from one of the
9252 R_ARM_{GOTDESC,CALL,DESCSEQ} relocations to IE or LE. */
9260 else
9261 {
9263 Elf_Internal_Rela outrel;
9266 /* The GOT entries have not been initialized yet. Do it
9267 now, and emit any relocations. If both an IE GOT and a
9268 GD GOT are necessary, we emit the GD first. */
9274 {
9277 }
9280 {
9283 /* We should have relaxed, unless this is an undefined
9284 weak symbol. */
9293 + offplt
9305 /* For globals, the first word in the relocation gets
9306 the relocation index and the top bit set, or zero,
9307 if we're binding now. For locals, it gets the
9308 symbol's offset in the tls section. */
9316 /* Second word in the relocation is always zero. */
9320 }
9322 {
9324 {
9340 else
9341 {
9344 R_ARM_TLS_DTPOFF32);
9353 }
9354 }
9355 else
9356 {
9357 /* If we are not emitting relocations for a
9358 general dynamic reference, then we must be in a
9359 static link or an executable link with the
9360 symbol binding locally. Mark it as belonging
9361 to module 1, the executable. */
9366 }
9369 }
9372 {
9374 {
9377 else
9389 }
9390 else
9394 }
9398 else
9400 }
9409 {
9410 bfd_signed_vma offset;
9411 /* TLS stubs are arm mode. The original symbol is a
9412 data object, so branch_type is bogus. */
9414 enum elf32_arm_stub_type stub_type
9422 {
9424 = elf32_arm_get_stub_entry
9430 }
9431 else
9437 {
9446 }
9447 else
9448 {
9449 /* Thumb blx encodes the offset in a complicated
9450 fashion. */
9455 input_section->output_offset
9460 {
9462 }
9463 else
9464 {
9466 /* Round up the offset to a word boundary */
9468 }
9480 }
9481 }
9482 /* These relocations needs special care, as besides the fact
9483 they point somewhere in .gotplt, the addend must be
9484 adjusted accordingly depending on the type of instruction
9485 we refer to */
9487 {
9496 {
9503 /* bl/blx */
9506 /* add */
9508 else
9509 {
9515 }
9516 }
9517 else
9518 {
9522 {
9538 }
9539 }
9547 }
9548 else
9557 }
9561 {
9567 }
9568 else
9577 {
9580 /* Ensure that we have a BX instruction. */
9584 {
9585 /* Branch to veneer. */
9586 bfd_vma glue_addr;
9593 }
9594 else
9595 {
9596 /* Preserve Rm (lowest four bits) and the condition code
9597 (highest four bits). Other bits encode MOV PC,Rm. */
9599 }
9602 }
9609 /* Until we properly support segment-base-relative addressing then
9610 we assume the segment base to be zero, as for the group relocations.
9611 Thus R_ARM_MOVW_BREL_NC has the same semantics as R_ARM_MOVW_ABS_NC
9612 and R_ARM_MOVT_BREL has the same semantics as R_ARM_MOVT_ABS. */
9616 {
9620 {
9623 }
9645 }
9652 /* Until we properly support segment-base-relative addressing then
9653 we assume the segment base to be zero, as for the above relocations.
9654 Thus R_ARM_THM_MOVW_BREL_NC has the same semantics as
9655 R_ARM_THM_MOVW_ABS_NC and R_ARM_THM_MOVT_BREL has the same semantics
9656 as R_ARM_THM_MOVT_ABS. */
9660 {
9661 bfd_vma insn;
9667 {
9673 }
9699 }
9712 {
9716 /* sb should be the origin of the *segment* containing the symbol.
9717 It is not clear how to obtain this OS-dependent value, so we
9718 make an arbitrary choice of zero. */
9720 bfd_vma residual;
9721 bfd_vma g_n;
9722 bfd_signed_vma signed_value;
9725 /* Determine which group of bits to select. */
9727 {
9749 }
9751 /* If REL, extract the addend from the insn. If RELA, it will
9752 have already been fetched for us. */
9754 {
9761 else
9762 {
9763 /* Compensate for the fact that in the instruction, the
9764 rotation is stored in multiples of 2 bits. */
9767 /* Rotate "constant" right by "rotation" bits. */
9770 }
9772 /* Determine if the instruction is an ADD or a SUB.
9773 (For REL, this determines the sign of the addend.) */
9776 {
9782 }
9785 }
9787 /* Compute the value (X) to go in the place. */
9793 /* PC relative. */
9795 else
9796 /* Section base relative. */
9799 /* If the target symbol is a Thumb function, then set the
9800 Thumb bit in the address. */
9804 /* Calculate the value of the relevant G_n, in encoded
9805 constant-with-rotation format. */
9809 /* Check for overflow if required. */
9816 {
9822 }
9824 /* Mask out the value and the ADD/SUB part of the opcode; take care
9825 not to destroy the S bit. */
9828 /* Set the opcode according to whether the value to go in the
9829 place is negative. */
9832 else
9835 /* Encode the offset. */
9839 }
9848 {
9853 bfd_vma residual;
9854 bfd_signed_vma signed_value;
9857 /* Determine which groups of bits to calculate. */
9859 {
9877 }
9879 /* If REL, extract the addend from the insn. If RELA, it will
9880 have already been fetched for us. */
9882 {
9885 }
9887 /* Compute the value (X) to go in the place. */
9891 /* PC relative. */
9893 else
9894 /* Section base relative. */
9897 /* Calculate the value of the relevant G_{n-1} to obtain
9898 the residual at that stage. */
9901 /* Check for overflow. */
9903 {
9909 }
9911 /* Mask out the value and U bit. */
9914 /* Set the U bit if the value to go in the place is non-negative. */
9918 /* Encode the offset. */
9922 }
9931 {
9936 bfd_vma residual;
9937 bfd_signed_vma signed_value;
9940 /* Determine which groups of bits to calculate. */
9942 {
9960 }
9962 /* If REL, extract the addend from the insn. If RELA, it will
9963 have already been fetched for us. */
9965 {
9968 }
9970 /* Compute the value (X) to go in the place. */
9974 /* PC relative. */
9976 else
9977 /* Section base relative. */
9980 /* Calculate the value of the relevant G_{n-1} to obtain
9981 the residual at that stage. */
9984 /* Check for overflow. */
9986 {
9992 }
9994 /* Mask out the value and U bit. */
9997 /* Set the U bit if the value to go in the place is non-negative. */
10001 /* Encode the offset. */
10005 }
10014 {
10019 bfd_vma residual;
10020 bfd_signed_vma signed_value;
10023 /* Determine which groups of bits to calculate. */
10025 {
10043 }
10045 /* If REL, extract the addend from the insn. If RELA, it will
10046 have already been fetched for us. */
10048 {
10051 }
10053 /* Compute the value (X) to go in the place. */
10057 /* PC relative. */
10059 else
10060 /* Section base relative. */
10063 /* Calculate the value of the relevant G_{n-1} to obtain
10064 the residual at that stage. */
10067 /* Check for overflow. (The absolute value to go in the place must be
10068 divisible by four and, after having been divided by four, must
10069 fit in eight bits.) */
10071 {
10077 }
10079 /* Mask out the value and U bit. */
10082 /* Set the U bit if the value to go in the place is non-negative. */
10086 /* Encode the offset. */
10090 }
10095 }
10096 }
10098 /* Add INCREMENT to the reloc (of type HOWTO) at ADDRESS. */
10099 static void
10103 bfd_signed_vma increment)
10104 {
10105 bfd_signed_vma addend;
10109 {
10127 }
10128 else
10129 {
10130 bfd_vma contents;
10134 /* Get the (signed) value from the instruction. */
10137 {
10138 bfd_signed_vma mask;
10143 }
10145 /* Add in the increment, (which is a byte value). */
10147 {
10159 /* Should we check for overflow here ? */
10161 /* Drop any undesired bits. */
10164 }
10169 }
10170 }
10172 #define IS_ARM_TLS_RELOC(R_TYPE) \
10173 ((R_TYPE) == R_ARM_TLS_GD32 \
10174 || (R_TYPE) == R_ARM_TLS_LDO32 \
10175 || (R_TYPE) == R_ARM_TLS_LDM32 \
10176 || (R_TYPE) == R_ARM_TLS_DTPOFF32 \
10177 || (R_TYPE) == R_ARM_TLS_DTPMOD32 \
10178 || (R_TYPE) == R_ARM_TLS_TPOFF32 \
10179 || (R_TYPE) == R_ARM_TLS_LE32 \
10180 || (R_TYPE) == R_ARM_TLS_IE32 \
10181 || IS_ARM_TLS_GNU_RELOC (R_TYPE))
10183 /* Specific set of relocations for the gnu tls dialect. */
10184 #define IS_ARM_TLS_GNU_RELOC(R_TYPE) \
10185 ((R_TYPE) == R_ARM_TLS_GOTDESC \
10186 || (R_TYPE) == R_ARM_TLS_CALL \
10187 || (R_TYPE) == R_ARM_THM_TLS_CALL \
10188 || (R_TYPE) == R_ARM_TLS_DESCSEQ \
10189 || (R_TYPE) == R_ARM_THM_TLS_DESCSEQ)
10191 /* Relocate an ARM ELF section. */
10193 static bfd_boolean
10202 {
10220 {
10227 bfd_vma relocation;
10228 bfd_reloc_status_type r;
10229 arelent bfd_reloc;
10250 {
10255 /* An object file might have a reference to a local
10256 undefined symbol. This is a daft object file, but we
10257 should at least do something about it. V4BX & NONE
10258 relocations do not use the symbol and are explicitly
10259 allowed to use the undefined symbol, so allow those.
10260 Likewise for relocations against STN_UNDEF. */
10266 {
10273 }
10276 {
10283 {
10288 {
10310 {
10316 }
10320 /* Get the (signed) value from the instruction. */
10323 {
10324 bfd_signed_vma mask;
10329 }
10331 }
10334 addend =
10339 /* Cases here must match those in the preceding
10340 switch statement. */
10342 {
10365 }
10366 }
10367 }
10368 else
10370 }
10371 else
10372 {
10373 bfd_boolean warned;
10381 }
10388 {
10389 /* This is a relocatable link. We don't have to change
10390 anything, unless the reloc is against a section symbol,
10391 in which case we have to adjust according to where the
10392 section symbol winds up in the output section. */
10394 {
10398 else
10400 }
10402 }
10406 else
10407 {
10408 name = (bfd_elf_string_from_elf_section
10412 }
10420 {
10425 input_bfd,
10426 input_section,
10429 name);
10430 }
10432 /* We call elf32_arm_final_link_relocate unless we're completely
10433 done, i.e., the relaxation produced the final output we want,
10434 and we won't let anybody mess with it. Also, we have to do
10435 addend adjustments in case of a R_ARM_TLS_GOTDESC relocation
10436 both in relaxed and non-relaxed cases */
10442 {
10445 /* This may have been marked unresolved because it came from
10446 a shared library. But we've just dealt with that. */
10448 }
10449 else
10460 /* Dynamic relocs are not propagated for SEC_DEBUGGING sections
10461 because such sections are not SEC_ALLOC and thus ld.so will
10462 not process them. */
10468 {
10471 input_bfd,
10472 input_section,
10477 }
10480 {
10482 {
10484 /* If the overflowing reloc was to an undefined symbol,
10485 we have already printed one error message and there
10486 is no point complaining again. */
10512 /* error_message should already be set. */
10517 /* Fall through. */
10519 common_error:
10526 }
10527 }
10528 }
10531 }
10533 /* Add a new unwind edit to the list described by HEAD, TAIL. If TINDEX is zero,
10534 adds the edit to the start of the list. (The list must be built in order of
10535 ascending TINDEX: the function's callers are primarily responsible for
10536 maintaining that condition). */
10538 static void
10541 arm_unwind_edit_type type,
10544 {
10553 {
10563 }
10564 else
10565 {
10572 }
10573 }
10577 /* Increase the size of EXIDX_SEC by ADJUST bytes. ADJUST mau be negative. */
10578 static void
10580 {
10588 /* Adjust size of output section. */
10590 }
10592 /* Insert an EXIDX_CANTUNWIND marker at the end of a section. */
10593 static void
10595 {
10605 }
10607 /* Scan .ARM.exidx tables, and create a list describing edits which should be
10608 made to those tables, such that:
10610 1. Regions without unwind data are marked with EXIDX_CANTUNWIND entries.
10611 2. Duplicate entries are merged together (EXIDX_CANTUNWIND, or unwind
10612 codes which have been inlined into the index).
10614 If MERGE_EXIDX_ENTRIES is false, duplicate entries are not merged.
10616 The edits are applied when the tables are written
10617 (in elf32_arm_write_section).
10618 */
10620 bfd_boolean
10624 bfd_boolean merge_exidx_entries)
10625 {
10632 /* Walk over all EXIDX sections, and create backlinks from the corrsponding
10633 text sections. */
10635 {
10639 {
10647 {
10648 Elf_Internal_Shdr *linked_hdr
10656 /* Link this .ARM.exidx section back from the text section it
10657 describes. */
10659 }
10660 }
10661 }
10663 /* Walk all text sections in order of increasing VMA. Eilminate duplicate
10664 index table entries (EXIDX_CANTUNWIND and inlined unwind opcodes),
10665 and add EXIDX_CANTUNWIND entries for sections with no unwind table data. */
10668 {
10675 bfd_vma j;
10686 {
10687 /* Section has no unwind data. */
10691 /* Ignore zero sized sections. */
10698 }
10700 /* Skip /DISCARD/ sections. */
10717 /* An error? */
10721 {
10726 /* An EXIDX_CANTUNWIND entry. */
10728 {
10732 }
10733 /* Inlined unwinding data. Merge if equal to previous. */
10735 {
10741 }
10742 /* Normal table entry. In theory we could merge these too,
10743 but duplicate entries are likely to be much less common. */
10744 else
10748 {
10753 }
10756 }
10758 /* Free contents if we allocated it ourselves. */
10762 /* Record edits to be applied later (in elf32_arm_write_section). */
10771 }
10773 /* Add terminating CANTUNWIND entry. */
10778 }
10780 static bfd_boolean
10783 {
10799 }
10801 static bfd_boolean
10803 {
10810 /* Invoke the regular ELF backend linker to do all the work. */
10814 /* Process stub sections (eg BE8 encoding, ...). */
10818 {
10820 /* Only process it once, in its link_sec slot. */
10822 {
10828 }
10829 }
10831 /* Write out any glue sections now that we have created all the
10832 stubs. */
10834 {
10837 ARM2THUMB_GLUE_SECTION_NAME))
10842 THUMB2ARM_GLUE_SECTION_NAME))
10847 VFP11_ERRATUM_VENEER_SECTION_NAME))
10852 ARM_BX_GLUE_SECTION_NAME))
10854 }
10857 }
10859 /* Set the right machine number. */
10861 static bfd_boolean
10863 {
10874 else
10878 }
10880 /* Function to keep ARM specific flags in the ELF header. */
10882 static bfd_boolean
10884 {
10887 {
10889 {
10892 (_("Warning: Not setting interworking flag of %B since it has already been specified as non-interworking"),
10893 abfd);
10894 else
10895 _bfd_error_handler
10897 abfd);
10898 }
10899 }
10900 else
10901 {
10904 }
10907 }
10909 /* Copy backend specific data from one object module to another. */
10911 static bfd_boolean
10913 {
10914 flagword in_flags;
10915 flagword out_flags;
10926 {
10927 /* Cannot mix APCS26 and APCS32 code. */
10931 /* Cannot mix float APCS and non-float APCS code. */
10935 /* If the src and dest have different interworking flags
10936 then turn off the interworking bit. */
10938 {
10940 _bfd_error_handler
10941 (_("Warning: Clearing the interworking flag of %B because non-interworking code in %B has been linked with it"),
10945 }
10947 /* Likewise for PIC, though don't warn for this case. */
10950 }
10955 /* Also copy the EI_OSABI field. */
10959 /* Copy object attributes. */
10963 }
10965 /* Values for Tag_ABI_PCS_R9_use. */
10966 enum
10967 {
10968 AEABI_R9_V6,
10969 AEABI_R9_SB,
10970 AEABI_R9_TLS,
10971 AEABI_R9_unused
10972 };
10974 /* Values for Tag_ABI_PCS_RW_data. */
10975 enum
10976 {
10977 AEABI_PCS_RW_data_absolute,
10978 AEABI_PCS_RW_data_PCrel,
10979 AEABI_PCS_RW_data_SBrel,
10980 AEABI_PCS_RW_data_unused
10981 };
10983 /* Values for Tag_ABI_enum_size. */
10984 enum
10985 {
10986 AEABI_enum_unused,
10987 AEABI_enum_short,
10988 AEABI_enum_wide,
10989 AEABI_enum_forced_wide
10990 };
10992 /* Determine whether an object attribute tag takes an integer, a
10993 string or both. */
10995 static int
10997 {
11006 else
11008 }
11010 /* The ABI defines that Tag_conformance should be emitted first, and that
11011 Tag_nodefaults should be second (if either is defined). This sets those
11012 two positions, and bumps up the position of all the remaining tags to
11013 compensate. */
11014 static int
11016 {
11026 }
11028 /* Attribute numbers >=64 (mod 128) can be safely ignored. */
11029 static bfd_boolean
11031 {
11033 {
11034 _bfd_error_handler
11039 }
11040 else
11041 {
11042 _bfd_error_handler
11046 }
11047 }
11049 /* Read the architecture from the Tag_also_compatible_with attribute, if any.
11050 Returns -1 if no architecture could be read. */
11052 static int
11054 {
11058 /* Note: the tag and its argument below are uleb128 values, though
11059 currently-defined values fit in one byte for each. */
11066 /* This tag is "safely ignorable", so don't complain if it looks funny. */
11068 }
11070 /* Set, or unset, the architecture of the Tag_also_compatible_with attribute.
11071 The tag is removed if ARCH is -1. */
11073 static void
11075 {
11080 {
11083 }
11085 /* Note: the tag and its argument below are uleb128 values, though
11086 currently-defined values fit in one byte for each. */
11092 }
11094 /* Combine two values for Tag_CPU_arch, taking secondary compatibility tags
11095 into account. */
11097 static int
11100 {
11101 #define T(X) TAG_CPU_ARCH_##X
11104 {
11114 };
11116 {
11127 };
11129 {
11141 };
11143 {
11156 };
11158 {
11172 };
11174 {
11189 };
11191 {
11207 };
11209 {
11210 v6t2,
11211 v6k,
11212 v7,
11213 v6_m,
11214 v6s_m,
11215 v7e_m,
11216 /* Pseudo-architecture. */
11217 v4t_plus_v6_m
11218 };
11220 /* Check we've not got a higher architecture than we know about. */
11223 {
11226 }
11228 /* Override old tag if we have a Tag_also_compatible_with on the output. */
11234 /* And override the new tag if we have a Tag_also_compatible_with on the
11235 input. */
11244 /* Architectures before V6KZ add features monotonically. */
11250 /* Use Tag_CPU_arch == V4T and Tag_also_compatible_with (Tag_CPU_arch V6_M)
11251 as the canonical version. */
11253 {
11256 }
11257 else
11261 {
11265 }
11268 #undef T
11269 }
11271 /* Merge EABI object attributes from IBFD into OBFD. Raise an error if there
11272 are conflicting attributes. */
11274 static bfd_boolean
11276 {
11279 /* Some tags have 0 = don't care, 1 = strong requirement,
11280 2 = weak requirement. */
11285 /* Skip the linker stubs file. This preserves previous behavior
11286 of accepting unknown attributes in the first input file - but
11287 is that a bug? */
11292 {
11293 /* This is the first object. Copy the attributes. */
11298 /* Use the Tag_null value to indicate the attributes have been
11299 initialized. */
11302 /* We do not output objects with Tag_MPextension_use_legacy - we move
11303 the attribute's value to Tag_MPextension_use. */
11305 {
11309 {
11310 _bfd_error_handler
11314 }
11320 }
11323 }
11327 /* This needs to happen before Tag_ABI_FP_number_model is merged. */
11329 {
11330 /* Ignore mismatches if the object doesn't use floating point. */
11334 {
11335 _bfd_error_handler
11340 }
11341 }
11344 {
11345 /* Merge this attribute with existing attributes. */
11347 {
11350 /* These are merged after Tag_CPU_arch. */
11355 /* Use the first value seen. */
11359 {
11363 /* These aren't real CPU names, but we can't guess
11364 that from the architecture version alone. */
11377 "ARM v6S-M"
11378 };
11380 /* Merge Tag_CPU_arch and Tag_also_compatible_with. */
11386 secondary_compat);
11389 /* Merge Tag_CPU_name and Tag_CPU_raw_name. */
11393 {
11394 /* The output architecture has been changed to match the
11395 input architecture. Use the input names. */
11402 }
11403 else
11404 {
11407 }
11409 /* If we still don't have a value for Tag_CPU_name,
11410 make one up now. Tag_CPU_raw_name remains blank. */
11415 }
11422 /* ??? Do Advanced_SIMD (NEON) and WMMX conflict? */
11431 /* Use the largest value specified. */
11438 /* Use the smallest value specified. */
11447 {
11448 /* This error message should be enabled once all non-conformant
11449 binaries in the toolchain have had the attributes set
11450 properly.
11451 _bfd_error_handler
11452 (_("error: %B: 8-byte data alignment conflicts with %B"),
11453 obfd, ibfd);
11454 result = FALSE; */
11455 }
11456 /* Fall through. */
11459 /* Use the "greatest" from the sequence 0, 2, 1, or the largest
11460 value if greater than 2 (for future-proofing). */
11468 /* The virtualization tag effectively stores two bits of
11469 information: the intended use of TrustZone (in bit 0), and the
11470 intended use of Virtualization (in bit 1). */
11475 {
11478 else
11479 {
11480 _bfd_error_handler
11485 }
11486 }
11491 {
11492 /* 0 will merge with anything.
11493 'A' and 'S' merge to 'A'.
11494 'R' and 'S' merge to 'R'.
11495 'M' and 'A|R|S' is an error. */
11504 else
11505 {
11506 _bfd_error_handler
11508 ibfd,
11512 }
11513 }
11516 {
11517 /* Tag_ABI_HardFP_use is handled along with Tag_FP_arch since
11518 the meaning of Tag_ABI_HardFP_use depends on Tag_FP_arch
11519 when it's 0. It might mean absence of FP hardware if
11520 Tag_FP_arch is zero, otherwise it is effectively SP + DP. */
11522 static const struct
11523 {
11527 {
11535 };
11540 /* If the output has no requirement about FP hardware,
11541 follow the requirement of the input. */
11543 {
11549 }
11550 /* If the input has no requirement about FP hardware, do
11551 nothing. */
11553 {
11556 }
11558 /* Both the input and the output have nonzero Tag_FP_arch.
11559 So Tag_ABI_HardFP_use is (SP & DP) when it's zero. */
11561 /* If both the input and the output have zero Tag_ABI_HardFP_use,
11562 do nothing. */
11565 ;
11566 /* If the input and the output have different Tag_ABI_HardFP_use,
11567 the combination of them is 3 (SP & DP). */
11572 /* Now we can handle Tag_FP_arch. */
11574 /* Values greater than 6 aren't defined, so just pick the
11575 biggest */
11577 {
11580 }
11581 /* The output uses the superset of input features
11582 (ISA version) and registers. */
11589 /* This assumes all possible supersets are also a valid
11590 options. */
11592 {
11596 }
11598 }
11604 {
11605 /* It's sometimes ok to mix different configs, so this is only
11606 a warning. */
11607 _bfd_error_handler
11609 }
11615 {
11616 _bfd_error_handler
11619 }
11627 {
11628 _bfd_error_handler
11630 ibfd);
11632 }
11633 /* Use the smallest value specified. */
11640 {
11641 _bfd_error_handler
11642 (_("warning: %B uses %u-byte wchar_t yet the output is to use %u-byte wchar_t; use of wchar_t values across objects may fail"),
11644 }
11650 {
11653 {
11654 /* The existing object is compatible with anything.
11655 Use whatever requirements the new object has. */
11657 }
11661 {
11672 _bfd_error_handler
11673 (_("warning: %B uses %s enums yet the output is to use %s enums; use of enum values across objects may fail"),
11675 }
11676 }
11679 /* Aready done. */
11683 {
11684 _bfd_error_handler
11688 }
11691 /* Merged in target-independent code. */
11694 /* This is handled along with Tag_FP_arch. */
11698 {
11700 {
11701 _bfd_error_handler
11705 }
11706 }
11712 /* This tag is set to zero if we can use UDIV and SDIV in Thumb
11713 mode on a v7-M or v7-R CPU; to one if we can not use UDIV or
11714 SDIV at all; and to two if we can use UDIV or SDIV on a v7-A
11715 CPU. We will merge as follows: If the input attribute's value
11716 is one then the output attribute's value remains unchanged. If
11717 the input attribute's value is zero or two then if the output
11718 attribute's value is one the output value is set to the input
11719 value, otherwise the output value must be the same as the
11720 inputs. */
11722 {
11724 {
11725 _bfd_error_handler
11729 }
11730 }
11738 /* We don't output objects with Tag_MPextension_use_legacy - we
11739 move the value to Tag_MPextension_use. */
11741 {
11743 {
11744 _bfd_error_handler
11747 ibfd);
11749 }
11750 }
11758 /* This tag is set if it exists, but the value is unused (and is
11759 typically zero). We don't actually need to do anything here -
11760 the merge happens automatically when the type flags are merged
11761 below. */
11764 /* Already done in Tag_CPU_arch. */
11767 /* Keep the attribute if it matches. Throw it away otherwise.
11768 No attribute means no claim to conform. */
11775 result
11777 }
11779 /* If out_attr was copied from in_attr then it won't have a type yet. */
11782 }
11784 /* Merge Tag_compatibility attributes and any common GNU ones. */
11788 /* Check for any attributes not known on ARM. */
11792 }
11795 /* Return TRUE if the two EABI versions are incompatible. */
11797 static bfd_boolean
11799 {
11800 /* v4 and v5 are the same spec before and after it was released,
11801 so allow mixing them. */
11807 }
11809 /* Merge backend specific data from an object file to the output
11810 object file when linking. */
11812 static bfd_boolean
11815 /* Display the flags field. */
11817 static bfd_boolean
11819 {
11825 /* Print normal ELF private data. */
11829 /* Ignore init flag - it may not be set, despite the flags field
11830 containing valid data. */
11832 /* xgettext:c-format */
11836 {
11838 /* The following flag bits are GNU extensions and not part of the
11839 official ARM ELF extended ABI. Hence they are only decoded if
11840 the EABI version is not set. */
11846 else
11853 else
11882 else
11893 else
11916 eabi:
11929 }
11947 }
11949 static int
11951 {
11953 {
11958 /* If the symbol is not an object, return the STT_ARM_16BIT flag.
11959 This allows us to distinguish between data used by Thumb instructions
11960 and non-data (which is probably code) inside Thumb regions of an
11961 executable. */
11968 }
11971 }
11979 {
11982 {
11986 }
11989 }
11991 /* Update the got entry reference counts for the section being removed. */
11993 static bfd_boolean
11998 {
12022 {
12027 bfd_boolean call_reloc_p;
12028 bfd_boolean may_become_dynamic_p;
12029 bfd_boolean may_need_local_target_p;
12035 {
12040 }
12050 {
12056 {
12059 }
12061 {
12064 }
12085 {
12088 }
12089 /* Fall through. */
12102 /* Should the interworking branches be here also? */
12105 {
12108 {
12111 }
12112 else
12114 }
12115 else
12121 }
12125 {
12138 }
12141 {
12147 else
12148 {
12158 }
12161 {
12162 /* Everything must go for SEC. */
12165 }
12166 }
12167 }
12170 }
12172 /* Look through the relocs for a section during the first phase. */
12174 static bfd_boolean
12177 {
12185 bfd_boolean call_reloc_p;
12186 bfd_boolean may_become_dynamic_p;
12187 bfd_boolean may_need_local_target_p;
12201 /* Create dynamic sections for relocatable executables so that we can
12202 copy relocations. */
12205 {
12208 }
12223 {
12235 /* PR 9934: It is possible to have relocations that do not
12236 refer to symbols, thus it is also possible to have an
12237 object file containing relocations but no symbol table. */
12239 {
12241 r_symndx);
12243 }
12248 {
12250 {
12251 /* A local symbol. */
12256 }
12257 else
12258 {
12263 }
12264 }
12272 /* Could be done earlier, if h were already available. */
12275 {
12285 /* This symbol requires a global offset table entry. */
12286 {
12290 {
12301 }
12304 {
12307 }
12308 else
12309 {
12310 /* This is a global offset table entry for a local symbol. */
12315 }
12317 /* If a variable is accessed with both tls methods, two
12318 slots may be created. */
12323 /* We will already have issued an error message if there
12324 is a TLS/non-TLS mismatch, based on the symbol
12325 type. So just combine any TLS types needed. */
12330 /* If the symbol is accessed in both IE and GDESC
12331 method, we're able to relax. Turn off the GDESC flag,
12332 without messing up with any other kind of tls types
12333 that may be involved */
12338 {
12341 else
12343 }
12344 }
12345 /* Fall through. */
12350 /* Fall through. */
12372 /* VxWorks uses dynamic R_ARM_ABS12 relocations for
12373 ldr __GOTT_INDEX__ offsets. */
12375 {
12378 }
12379 /* Fall through. */
12386 {
12388 (_("%B: relocation %s against `%s' can not be used when making a shared object; recompile with -fPIC"),
12393 }
12395 /* Fall through. */
12405 /* Should the interworking branches be listed here? */
12408 {
12411 {
12412 /* In shared libraries and relocatable executables,
12413 we treat local relative references as calls;
12414 see the related SYMBOL_CALLS_LOCAL code in
12415 allocate_dynrelocs. */
12418 }
12419 else
12420 /* We are creating a shared library or relocatable
12421 executable, and this is a reloc against a global symbol,
12422 or a non-PC-relative reloc against a local symbol.
12423 We may need to copy the reloc into the output. */
12425 }
12426 else
12430 /* This relocation describes the C++ object vtable hierarchy.
12431 Reconstruct it for later use during GC. */
12437 /* This relocation describes which C++ vtable entries are actually
12438 used. Record for later use during GC. */
12445 }
12448 {
12450 /* We may need a .plt entry if the function this reloc
12451 refers to is in a different object, regardless of the
12452 symbol's type. We can't tell for sure yet, because
12453 something later might force the symbol local. */
12456 /* If this reloc is in a read-only section, we might
12457 need a copy reloc. We can't check reliably at this
12458 stage whether the section is read-only, as input
12459 sections have not yet been mapped to output sections.
12460 Tentatively set the flag for now, and correct in
12461 adjust_dynamic_symbol. */
12463 }
12467 {
12473 {
12476 }
12477 else
12478 {
12484 }
12486 /* If the symbol is a function that doesn't bind locally,
12487 this relocation will need a PLT entry. */
12493 /* It's too early to use htab->use_blx here, so we have to
12494 record possible blx references separately from
12495 relocs that definitely need a thumb stub. */
12503 }
12506 {
12509 /* Create a reloc section in dynobj. */
12511 {
12512 sreloc = _bfd_elf_make_dynamic_reloc_section
12518 /* BPABI objects never have dynamic relocations mapped. */
12520 {
12521 flagword flags;
12526 }
12527 }
12529 /* If this is a global symbol, count the number of
12530 relocations we need for this symbol. */
12533 else
12534 {
12538 }
12542 {
12553 }
12558 }
12559 }
12562 }
12564 /* Unwinding tables are not referenced directly. This pass marks them as
12565 required if the corresponding code section is marked. */
12567 static bfd_boolean
12569 elf_gc_mark_hook_fn gc_mark_hook)
12570 {
12573 bfd_boolean again;
12577 /* Marking EH data may cause additional code sections to be marked,
12578 requiring multiple passes. */
12581 {
12584 {
12592 {
12601 {
12605 }
12606 }
12607 }
12608 }
12611 }
12613 /* Treat mapping symbols as special target symbols. */
12615 static bfd_boolean
12617 {
12619 BFD_ARM_SPECIAL_SYM_TYPE_ANY);
12620 }
12622 /* This is a copy of elf_find_function() from elf.c except that
12623 ARM mapping symbols are ignored when looking for function names
12624 and STT_ARM_TFUNC is considered to a function type. */
12626 static bfd_boolean
12630 bfd_vma offset,
12633 {
12640 {
12646 {
12655 /* Skip mapping symbols. */
12658 BFD_ARM_SPECIAL_SYM_TYPE_ANY))
12660 /* Fall through. */
12664 {
12667 }
12669 }
12670 }
12681 }
12684 /* Find the nearest line to a particular section and offset, for error
12685 reporting. This code is a duplicate of the code in elf.c, except
12686 that it uses arm_elf_find_function. */
12688 static bfd_boolean
12692 bfd_vma offset,
12696 {
12699 /* We skip _bfd_dwarf1_find_nearest_line since no known ARM toolchain uses it. */
12706 {
12710 functionname_ptr);
12713 }
12733 }
12735 static bfd_boolean
12740 {
12741 bfd_boolean found;
12746 }
12748 /* Adjust a symbol defined by a dynamic object and referenced by a
12749 regular object. The current definition is in some section of the
12750 dynamic object, but we're not including those sections. We have to
12751 change the definition to something the rest of the link can
12752 understand. */
12754 static bfd_boolean
12757 {
12769 /* Make sure we know what is going on here. */
12780 /* If this is a function, put it in the procedure linkage table. We
12781 will fill in the contents of the procedure linkage table later,
12782 when we know the address of the .got section. */
12784 {
12785 /* Calls to STT_GNU_IFUNC symbols always use a PLT, even if the
12786 symbol binds locally. */
12792 {
12793 /* This case can occur if we saw a PLT32 reloc in an input
12794 file, but the symbol was never referred to by a dynamic
12795 object, or if all references were garbage collected. In
12796 such a case, we don't actually need to build a procedure
12797 linkage table, and we can just do a PC24 reloc instead. */
12803 }
12806 }
12807 else
12808 {
12809 /* It's possible that we incorrectly decided a .plt reloc was
12810 needed for an R_ARM_PC24 or similar reloc to a non-function sym
12811 in check_relocs. We can't decide accurately between function
12812 and non-function syms in check-relocs; Objects loaded later in
12813 the link may change h->type. So fix it now. */
12818 }
12820 /* If this is a weak symbol, and there is a real definition, the
12821 processor independent code will have arranged for us to see the
12822 real definition first, and we can just use the same value. */
12824 {
12830 }
12832 /* If there are no non-GOT references, we do not need a copy
12833 relocation. */
12837 /* This is a reference to a symbol defined by a dynamic object which
12838 is not a function. */
12840 /* If we are creating a shared library, we must presume that the
12841 only references to the symbol are via the global offset table.
12842 For such cases we need not do anything here; the relocations will
12843 be handled correctly by relocate_section. Relocatable executables
12844 can reference data in shared objects directly, so we don't need to
12845 do anything here. */
12850 {
12854 }
12856 /* We must allocate the symbol in our .dynbss section, which will
12857 become part of the .bss section of the executable. There will be
12858 an entry for this symbol in the .dynsym section. The dynamic
12859 object will contain position independent code, so all references
12860 from the dynamic object to this symbol will go through the global
12861 offset table. The dynamic linker will use the .dynsym entry to
12862 determine the address it must put in the global offset table, so
12863 both the dynamic object and the regular object will refer to the
12864 same memory location for the variable. */
12868 /* We must generate a R_ARM_COPY reloc to tell the dynamic linker to
12869 copy the initial value out of the dynamic object and into the
12870 runtime process image. We need to remember the offset into the
12871 .rel(a).bss section we are going to use. */
12873 {
12879 }
12882 }
12884 /* Allocate space in .plt, .got and associated reloc sections for
12885 dynamic relocs. */
12887 static bfd_boolean
12889 {
12907 {
12908 /* Make sure this symbol is output as a dynamic symbol.
12909 Undefined weak syms won't yet be marked as dynamic. */
12912 {
12915 }
12917 /* If the call in the PLT entry binds locally, the associated
12918 GOT entry should use an R_ARM_IRELATIVE relocation instead of
12919 the usual R_ARM_JUMP_SLOT. Put it in the .iplt section rather
12920 than the .plt section. */
12922 {
12926 /* All non-call references can be resolved directly.
12927 This means that they can (and in some cases, must)
12928 resolve directly to the run-time target, rather than
12929 to the PLT. That in turns means that any .got entry
12930 would be equal to the .igot.plt entry, so there's
12931 no point having both. */
12933 }
12938 {
12941 /* If this symbol is not defined in a regular file, and we are
12942 not generating a shared library, then set the symbol to this
12943 location in the .plt. This is required to make function
12944 pointers compare as equal between the normal executable and
12945 the shared library. */
12948 {
12952 /* Make sure the function is not marked as Thumb, in case
12953 it is the target of an ABS32 relocation, which will
12954 point to the PLT entry. */
12956 }
12960 /* VxWorks executables have a second set of relocations for
12961 each PLT entry. They go in a separate relocation section,
12962 which is processed by the kernel loader. */
12964 {
12965 /* There is a relocation for the initial PLT entry:
12966 an R_ARM_32 relocation for _GLOBAL_OFFSET_TABLE_. */
12970 /* There are two extra relocations for each subsequent
12971 PLT entry: an R_ARM_32 relocation for the GOT entry,
12972 and an R_ARM_32 relocation for the PLT entry. */
12974 }
12975 }
12976 else
12977 {
12980 }
12981 }
12982 else
12983 {
12986 }
12992 {
12994 bfd_boolean dyn;
12998 /* Make sure this symbol is output as a dynamic symbol.
12999 Undefined weak syms won't yet be marked as dynamic. */
13002 {
13005 }
13008 {
13016 /* Non-TLS symbols need one GOT slot. */
13018 else
13019 {
13021 {
13022 /* R_ARM_TLS_DESC needs 2 GOT slots. */
13023 eh->tlsdesc_got
13028 /* plt.got_offset needs to know there's a TLS_DESC
13029 reloc in the middle of .got.plt. */
13031 }
13034 {
13035 /* R_ARM_TLS_GD32 needs 2 consecutive GOT slots. If
13036 the symbol is both GD and GDESC, got.offset may
13037 have been overwritten. */
13040 }
13043 /* R_ARM_TLS_IE32 needs one GOT slot. */
13045 }
13059 {
13067 {
13069 /* GDESC needs a trampoline to jump to. */
13071 }
13073 /* Only GD needs it. GDESC just emits one relocation per
13074 2 entries. */
13077 }
13079 {
13081 /* Reserve room for the GOT entry's R_ARM_GLOB_DAT relocation. */
13083 }
13086 /* No non-call references resolve the STT_GNU_IFUNC's PLT entry;
13087 they all resolve dynamically instead. Reserve room for the
13088 GOT entry's R_ARM_IRELATIVE relocation. */
13091 /* Reserve room for the GOT entry's R_ARM_RELATIVE relocation. */
13093 }
13094 }
13095 else
13098 /* Allocate stubs for exported Thumb functions on v4t. */
13103 {
13110 /* Create a new symbol to regist the real location of the function. */
13124 /* Point the symbol at the stub. */
13129 }
13134 /* In the shared -Bsymbolic case, discard space allocated for
13135 dynamic pc-relative relocs against symbols which turn out to be
13136 defined in regular objects. For the normal shared case, discard
13137 space for pc-relative relocs that have become local due to symbol
13138 visibility changes. */
13141 {
13142 /* The only relocs that use pc_count are R_ARM_REL32 and
13143 R_ARM_REL32_NOI, which will appear on something like
13144 ".long foo - .". We want calls to protected symbols to resolve
13145 directly to the function rather than going via the plt. If people
13146 want function pointer comparisons to work as expected then they
13147 should avoid writing assembly like ".long foo - .". */
13149 {
13153 {
13158 else
13160 }
13161 }
13164 {
13168 {
13171 else
13173 }
13174 }
13176 /* Also discard relocs on undefined weak syms with non-default
13177 visibility. */
13180 {
13184 /* Make sure undefined weak symbols are output as a dynamic
13185 symbol in PIEs. */
13188 {
13191 }
13192 }
13196 {
13197 /* Output absolute symbols so that we can create relocations
13198 against them. For normal symbols we output a relocation
13199 against the section that contains them. */
13202 }
13204 }
13205 else
13206 {
13207 /* For the non-shared case, discard space for relocs against
13208 symbols which turn out to need copy relocs or are not
13209 dynamic. */
13217 {
13218 /* Make sure this symbol is output as a dynamic symbol.
13219 Undefined weak syms won't yet be marked as dynamic. */
13222 {
13225 }
13227 /* If that succeeded, we know we'll be keeping all the
13228 relocs. */
13231 }
13235 keep: ;
13236 }
13238 /* Finally, allocate space. */
13240 {
13246 else
13248 }
13251 }
13253 /* Find any dynamic relocs that apply to read-only sections. */
13255 static bfd_boolean
13257 {
13263 {
13267 {
13272 /* Not an error, just cut short the traversal. */
13274 }
13275 }
13277 }
13279 void
13282 {
13290 }
13292 /* Set the sizes of the dynamic sections. */
13294 static bfd_boolean
13297 {
13300 bfd_boolean plt;
13301 bfd_boolean relocs;
13314 {
13315 /* Set the contents of the .interp section to the interpreter. */
13317 {
13322 }
13323 }
13325 /* Set up .got offsets for local syms, and space for local dynamic
13326 relocs. */
13328 {
13334 bfd_size_type locsymcount;
13344 {
13349 {
13352 {
13353 /* Input section has been discarded, either because
13354 it is a copy of a linkonce section or due to
13355 linker script /DISCARD/, so we'll be discarding
13356 the relocs too. */
13357 }
13361 {
13362 /* Relocations in vxworks .tls_vars sections are
13363 handled specially by the loader. */
13364 }
13366 {
13371 }
13372 }
13373 }
13391 {
13395 {
13399 {
13404 /* All references to the PLT are calls, so all
13405 non-call references can resolve directly to the
13406 run-time target. This means that the .got entry
13407 would be the same as the .igot.plt entry, so there's
13408 no point creating both. */
13410 }
13411 else
13412 {
13415 }
13418 {
13424 else
13426 }
13427 }
13429 {
13434 /* TLS_GD relocs need an 8-byte structure in the GOT. */
13437 {
13442 /* plt.got_offset needs to know there's a TLS_DESC
13443 reloc in the middle of .got.plt. */
13445 }
13450 {
13451 /* If the symbol is both GD and GDESC, *local_got
13452 may have been overwritten. */
13455 }
13461 /* If all references to an STT_GNU_IFUNC PLT are calls,
13462 then all non-call references, including this GOT entry,
13463 resolve directly to the run-time target. */
13473 {
13476 }
13477 }
13478 else
13480 }
13481 }
13484 {
13485 /* Allocate two GOT entries and one dynamic relocation (if necessary)
13486 for R_ARM_TLS_LDM32 relocations. */
13491 }
13492 else
13495 /* Allocate global sym .plt and .got entries, and space for global
13496 sym dynamic relocs. */
13499 /* Here we rummage through the found bfds to collect glue information. */
13501 {
13505 /* Initialise mapping tables for code/data. */
13510 /* xgettext:c-format */
13513 }
13515 /* Allocate space for the glue sections now that we've sized them. */
13518 /* For every jump slot reserved in the sgotplt, reloc_count is
13519 incremented. However, when we reserve space for TLS descriptors,
13520 it's not incremented, so in order to compute the space reserved
13521 for them, it suffices to multiply the reloc count by the jump
13522 slot size. */
13527 {
13534 /* If we're not using lazy TLS relocations, don't generate the
13535 PLT and GOT entries they require. */
13537 {
13543 }
13544 }
13546 /* The check_relocs and adjust_dynamic_symbol entry points have
13547 determined the sizes of the various dynamic sections. Allocate
13548 memory for them. */
13552 {
13558 /* It's OK to base decisions on the section name, because none
13559 of the dynobj section names depend upon the input files. */
13563 {
13564 /* Remember whether there is a PLT. */
13566 }
13568 {
13570 {
13571 /* Remember whether there are any reloc sections other
13572 than .rel(a).plt and .rela.plt.unloaded. */
13576 /* We use the reloc_count field as a counter if we need
13577 to copy relocs into the output file. */
13579 }
13580 }
13586 {
13587 /* It's not one of our sections, so don't allocate space. */
13589 }
13592 {
13593 /* If we don't need this section, strip it from the
13594 output file. This is mostly to handle .rel(a).bss and
13595 .rel(a).plt. We must create both sections in
13596 create_dynamic_sections, because they must be created
13597 before the linker maps input sections to output
13598 sections. The linker does that before
13599 adjust_dynamic_symbol is called, and it is that
13600 function which decides whether anything needs to go
13601 into these sections. */
13604 }
13609 /* Allocate memory for the section contents. */
13613 }
13616 {
13617 /* Add some entries to the .dynamic section. We fill in the
13618 values later, in elf32_arm_finish_dynamic_sections, but we
13619 must add the entries now so that we get the correct size for
13620 the .dynamic section. The DT_DEBUG entry is filled in by the
13621 dynamic linker and used by the debugger. */
13622 #define add_dynamic_entry(TAG, VAL) \
13623 _bfd_elf_add_dynamic_entry (info, TAG, VAL)
13626 {
13629 }
13632 {
13644 }
13647 {
13649 {
13654 }
13655 else
13656 {
13661 }
13662 }
13664 /* If any dynamic relocs apply to a read-only section,
13665 then we need a DT_TEXTREL entry. */
13668 info);
13671 {
13674 }
13678 }
13679 #undef add_dynamic_entry
13682 }
13684 /* Size sections even though they're not dynamic. We use it to setup
13685 _TLS_MODULE_BASE_, if needed. */
13687 static bfd_boolean
13690 {
13699 {
13702 tlsbase = elf_link_hash_lookup
13706 {
13722 }
13723 }
13725 }
13727 /* Finish up dynamic symbol handling. We set the contents of various
13728 dynamic sections here. */
13730 static bfd_boolean
13735 {
13746 {
13748 {
13752 }
13755 {
13756 /* Mark the symbol as undefined, rather than as defined in
13757 the .plt section. Leave the value alone. */
13759 /* If the symbol is weak, we do need to clear the value.
13760 Otherwise, the PLT entry would provide a definition for
13761 the symbol even if the symbol wasn't defined anywhere,
13762 and so the symbol would never be NULL. */
13765 }
13767 {
13768 /* At least one non-call relocation references this .iplt entry,
13769 so the .iplt entry is the function's canonical address. */
13777 }
13778 }
13781 {
13783 Elf_Internal_Rela rel;
13785 /* This symbol needs a copy reloc. Set it up. */
13799 }
13801 /* Mark _DYNAMIC and _GLOBAL_OFFSET_TABLE_ as absolute. On VxWorks,
13802 the _GLOBAL_OFFSET_TABLE_ symbol is not absolute: it is relative
13803 to the ".got" section. */
13809 }
13811 static void
13815 {
13819 {
13822 /* Emit mov pc,rx if bx is not permitted. */
13826 }
13827 }
13829 /* Finish up the dynamic sections. */
13831 static bfd_boolean
13833 {
13846 /* A broken linker script might have discarded the dynamic sections.
13847 Catch this here so that we do not seg-fault later on. */
13853 {
13865 {
13866 Elf_Internal_Dyn dyn;
13873 {
13906 get_vma:
13911 else
13912 /* In the BPABI, tags in the PT_DYNAMIC section point
13913 at the file offset, not the memory address, for the
13914 convenience of the post linker. */
13919 get_vma_if_bpabi:
13934 {
13935 /* My reading of the SVR4 ABI indicates that the
13936 procedure linkage table relocs (DT_JMPREL) should be
13937 included in the overall relocs (DT_REL). This is
13938 what Solaris does. However, UnixWare can not handle
13939 that case. Therefore, we override the DT_RELSZ entry
13940 here to make it not include the JMPREL relocs. Since
13941 the linker script arranges for .rel(a).plt to follow all
13942 other relocation sections, we don't have to worry
13943 about changing the DT_REL entry. */
13949 }
13950 /* Fall through. */
13954 /* In the BPABI, the DT_REL tag must point at the file
13955 offset, not the VMA, of the first relocation
13956 section. So, we use code similar to that in
13957 elflink.c, but do not check for SHF_ALLOC on the
13958 relcoation section, since relocations sections are
13959 never allocated under the BPABI. The comments above
13960 about Unixware notwithstanding, we include all of the
13961 relocations here. */
13963 {
13969 {
13970 Elf_Internal_Shdr *hdr
13973 {
13980 }
13981 }
13983 }
14000 /* Set the bottom bit of DT_INIT/FINI if the
14001 corresponding function is Thumb. */
14007 get_sym:
14008 /* If it wasn't set by elf_bfd_final_link
14009 then there is nothing to adjust. */
14011 {
14017 {
14020 }
14021 }
14023 }
14024 }
14026 /* Fill in the first entry in the procedure linkage table. */
14028 {
14032 /* Calculate the addresses of the GOT and PLT. */
14037 {
14038 /* The VxWorks GOT is relocated by the dynamic linker.
14039 Therefore, we must emit relocations rather than simply
14040 computing the values now. */
14041 Elf_Internal_Rela rel;
14052 /* Generate a relocation for _GLOBAL_OFFSET_TABLE_. */
14058 }
14059 else
14060 {
14073 #ifdef FOUR_WORD_PLT
14074 /* The displacement value goes in the otherwise-unused
14075 last word of the second entry. */
14077 #else
14079 #endif
14080 }
14081 }
14083 /* UnixWare sets the entsize of .plt to 4, although that doesn't
14084 really seem like the right value. */
14089 {
14090 bfd_vma got_address
14094 bfd_vma plt_address
14110 }
14113 {
14117 #ifdef FOUR_WORD_PLT
14120 #endif
14121 }
14124 {
14125 /* Correct the .rel(a).plt.unloaded relocations. They will have
14126 incorrect symbol indexes. */
14135 {
14136 Elf_Internal_Rela rel;
14147 }
14148 }
14149 }
14151 /* Fill in the first three entries in the global offset table. */
14153 {
14155 {
14158 else
14164 }
14167 }
14170 }
14172 static void
14173 elf32_arm_post_process_headers (bfd * abfd, struct bfd_link_info * link_info ATTRIBUTE_UNUSED)
14174 {
14182 else
14187 {
14191 }
14192 }
14194 static enum elf_reloc_type_class
14196 {
14198 {
14207 }
14208 }
14210 static void
14212 {
14214 }
14216 /* Return TRUE if this is an unwinding table entry. */
14218 static bfd_boolean
14220 {
14223 }
14226 /* Set the type and flags for an ARM section. We do this by
14227 the section name, which is a hack, but ought to work. */
14229 static bfd_boolean
14231 {
14237 {
14240 }
14242 }
14244 /* Handle an ARM specific section when reading an object file. This is
14245 called when bfd_section_from_shdr finds a section with an unknown
14246 type. */
14248 static bfd_boolean
14253 {
14254 /* There ought to be a place to keep ELF backend specific flags, but
14255 at the moment there isn't one. We just keep track of the
14256 sections by their name, instead. Fortunately, the ABI gives
14257 names for all the ARM specific sections, so we will probably get
14258 away with this. */
14260 {
14268 }
14274 }
14278 {
14281 else
14283 }
14286 {
14295 enum map_symbol_type
14296 {
14297 ARM_MAP_ARM,
14298 ARM_MAP_THUMB,
14299 ARM_MAP_DATA
14300 };
14303 /* Output a single mapping symbol. */
14305 static bfd_boolean
14308 bfd_vma offset)
14309 {
14311 Elf_Internal_Sym sym;
14323 }
14325 /* Output mapping symbols for the PLT entry described by ROOT_PLT and ARM_PLT.
14326 IS_IPLT_ENTRY_P says whether the PLT is in .iplt rather than .plt. */
14328 static bfd_boolean
14330 bfd_boolean is_iplt_entry_p,
14333 {
14345 {
14348 }
14349 else
14350 {
14353 }
14359 {
14364 }
14366 {
14375 }
14376 else
14377 {
14378 bfd_boolean thumb_stub_p;
14382 {
14385 }
14386 #ifdef FOUR_WORD_PLT
14391 #else
14392 /* A three-word PLT with no Thumb thunk contains only Arm code,
14393 so only need to output a mapping symbol for the first PLT entry and
14394 entries with thumb thunks. */
14396 {
14399 }
14400 #endif
14401 }
14404 }
14406 /* Output mapping symbols for PLT entries associated with H. */
14408 static bfd_boolean
14410 {
14418 /* When warning symbols are created, they **replace** the "real"
14419 entry in the hash table, thus we never get to see the real
14420 symbol in a hash traversal. So look at it now. */
14426 }
14428 /* Output a single local symbol for a generated stub. */
14430 static bfd_boolean
14433 {
14434 Elf_Internal_Sym sym;
14445 }
14447 static bfd_boolean
14450 {
14453 bfd_vma addr;
14462 /* Massage our args to the form they really have. */
14468 /* Ensure this stub is attached to the current section being
14469 processed. */
14478 {
14492 }
14497 {
14499 {
14516 }
14519 {
14523 }
14526 {
14543 }
14544 }
14547 }
14549 /* Output mapping symbols for linker generated sections,
14550 and for those data-only sections that do not have a
14551 $d. */
14553 static bfd_boolean
14558 Elf_Internal_Sym *,
14559 asection *,
14561 {
14562 output_arch_syminfo osi;
14564 bfd_vma offset;
14565 bfd_size_type size;
14578 /* Add a $d mapping symbol to data-only sections that
14579 don't have any mapping symbol. This may result in (harmless) redundant
14580 mapping symbols. */
14584 {
14589 {
14594 == SEC_HAS_CONTENTS
14599 {
14604 }
14605 }
14606 }
14608 /* ARM->Thumb glue. */
14610 {
14612 ARM2THUMB_GLUE_SECTION_NAME);
14621 else
14625 {
14628 }
14629 }
14631 /* Thumb->ARM glue. */
14633 {
14635 THUMB2ARM_GLUE_SECTION_NAME);
14642 {
14645 }
14646 }
14648 /* ARMv4 BX veneers. */
14650 {
14652 ARM_BX_GLUE_SECTION_NAME);
14658 }
14660 /* Long calls stubs. */
14662 {
14668 {
14669 /* Ignore non-stub sections. */
14679 }
14680 }
14682 /* Finally, output mapping symbols for the PLT. */
14684 {
14689 /* Output mapping symbols for the plt header. SymbianOS does not have a
14690 plt header. */
14692 {
14693 /* VxWorks shared libraries have no PLT header. */
14695 {
14700 }
14701 }
14703 {
14706 #ifndef FOUR_WORD_PLT
14709 #endif
14710 }
14711 }
14714 {
14719 {
14725 {
14733 }
14734 }
14735 }
14737 {
14738 /* Mapping symbols for the lazy tls trampoline. */
14745 }
14747 {
14748 /* Mapping symbols for the tls trampoline. */
14751 #ifdef FOUR_WORD_PLT
14755 #endif
14756 }
14759 }
14761 /* Allocate target specific section data. */
14763 static bfd_boolean
14765 {
14767 {
14775 }
14778 }
14781 /* Used to order a list of mapping symbols by address. */
14783 static int
14785 {
14794 /* Ensure results do not depend on the host qsort for objects with
14795 multiple mapping symbols at the same address by sorting on type
14796 after vma. */
14800 else
14802 }
14804 /* Add OFFSET to lower 31 bits of ADDR, leaving other bits unmodified. */
14806 static unsigned long
14808 {
14810 }
14812 /* Copy an .ARM.exidx table entry, adding OFFSET to (applied) PREL31
14813 relocations. */
14815 static void
14817 {
14821 /* High bit of first word is supposed to be zero. */
14825 /* If the high bit of the first word is clear, and the bit pattern is not 0x1
14826 (EXIDX_CANTUNWIND), this is an offset to an .ARM.extab entry. */
14832 }
14834 /* Data for make_branch_to_a8_stub(). */
14839 };
14842 /* Helper to insert branches to Cortex-A8 erratum stubs in the right
14843 places for a particular section. */
14845 static bfd_boolean
14848 {
14854 bfd_signed_vma branch_offset;
14883 /* We attempt to avoid this condition by setting stubs_always_after_branch
14884 in elf32_arm_size_stubs if we've enabled the Cortex-A8 erratum workaround.
14885 This check is just to be on the safe side... */
14887 {
14891 }
14894 {
14905 {
14910 jump24:
14912 {
14913 /* There's not much we can do apart from complain if this
14914 happens. */
14918 }
14920 /* i1 = not(j1 eor s), so:
14921 not i1 = j1 eor s
14922 j1 = (not i1) eor s. */
14934 }
14940 }
14946 }
14948 /* Do code byteswapping. Return FALSE afterwards so that the section is
14949 written out as normal. */
14951 static bfd_boolean
14956 {
14962 bfd_vma ptr;
14963 bfd_vma end;
14965 bfd_byte tmp;
14971 /* If this section has not been allocated an _arm_elf_section_data
14972 structure then we cannot record anything. */
14982 {
14987 {
14991 {
14993 {
14994 bfd_vma branch_to_veneer;
14995 /* Original condition code of instruction, plus bit mask for
14996 ARM B instruction. */
15000 /* The instruction is before the label. */
15003 /* Above offset included in -4 below. */
15017 }
15021 {
15022 bfd_vma branch_from_veneer;
15025 /* Take size of veneer into account. */
15034 /* Original instruction. */
15041 /* Branch back to insn after original insn. */
15047 }
15052 }
15053 }
15054 }
15057 {
15058 arm_unwind_table_edit *edit_node
15060 /* Now, sec->size is the size of the section we will write. The original
15061 size (before we merged duplicate entries and inserted EXIDX_CANTUNWIND
15062 markers) was sec->rawsize. (This isn't the case if we perform no
15063 edits, then rawsize will be zero and we should use size). */
15070 {
15072 {
15076 {
15079 out_index++;
15080 in_index++;
15081 }
15085 {
15087 {
15089 in_index++;
15094 {
15102 /* Note: this is meant to be equivalent to an
15103 R_ARM_PREL31 relocation. These synthetic
15104 EXIDX_CANTUNWIND markers are not relocated by the
15105 usual BFD method. */
15109 /* First address we can't unwind. */
15113 /* Code for EXIDX_CANTUNWIND. */
15117 out_index++;
15119 }
15121 }
15124 }
15125 }
15126 else
15127 {
15128 /* No more edits, copy remaining entries verbatim. */
15131 out_index++;
15132 in_index++;
15133 }
15134 }
15138 edited_contents,
15142 }
15144 /* Fix code to point to Cortex-A8 erratum stubs. */
15146 {
15154 }
15160 {
15165 {
15168 else
15172 {
15174 /* Byte swap code words. */
15176 {
15184 }
15188 /* Byte swap code halfwords. */
15190 {
15195 }
15199 /* Leave data alone. */
15201 }
15203 }
15204 }
15212 }
15214 /* Mangle thumb function symbols as we read them in. */
15216 static bfd_boolean
15221 {
15225 /* New EABI objects mark thumb function symbols by setting the low bit of
15226 the address. */
15229 {
15231 {
15234 }
15235 else
15237 }
15239 {
15242 }
15245 else
15249 }
15252 /* Mangle thumb function symbols as we write them out. */
15254 static void
15259 {
15260 Elf_Internal_Sym newsym;
15262 /* We convert STT_ARM_TFUNC symbols into STT_FUNC with the low bit
15263 of the address set, as per the new EABI. We do this unconditionally
15264 because objcopy does not set the elf header flags until after
15265 it writes out the symbol table. */
15267 {
15272 {
15273 /* Do this only for defined symbols. At link type, the static
15274 linker will simulate the work of dynamic linker of resolving
15275 symbols and will carry over the thumbness of found symbols to
15276 the output symbol table. It's not clear how it happens, but
15277 the thumbness of undefined symbols can well be different at
15278 runtime, and writing '1' for them will be confusing for users
15279 and possibly for dynamic linker itself.
15280 */
15282 }
15285 }
15287 }
15289 /* Add the PT_ARM_EXIDX program header. */
15291 static bfd_boolean
15294 {
15300 {
15301 /* If there is already a PT_ARM_EXIDX header, then we do not
15302 want to add another one. This situation arises when running
15303 "strip"; the input binary already has the header. */
15308 {
15319 }
15320 }
15323 }
15325 /* We may add a PT_ARM_EXIDX program header. */
15327 static int
15330 {
15336 else
15338 }
15340 /* Hook called by the linker routine which adds symbols from an object
15341 file. */
15343 static bfd_boolean
15347 {
15359 }
15361 /* We use this to override swap_symbol_in and swap_symbol_out. */
15363 {
15376 bfd_elf32_write_out_phdrs,
15377 bfd_elf32_write_shdrs_and_ehdr,
15378 bfd_elf32_checksum_contents,
15379 bfd_elf32_write_relocs,
15380 elf32_arm_swap_symbol_in,
15381 elf32_arm_swap_symbol_out,
15382 bfd_elf32_slurp_reloc_table,
15383 bfd_elf32_slurp_symbol_table,
15384 bfd_elf32_swap_dyn_in,
15385 bfd_elf32_swap_dyn_out,
15386 bfd_elf32_swap_reloc_in,
15387 bfd_elf32_swap_reloc_out,
15388 bfd_elf32_swap_reloca_in,
15389 bfd_elf32_swap_reloca_out
15390 };
15392 #define ELF_ARCH bfd_arch_arm
15393 #define ELF_TARGET_ID ARM_ELF_DATA
15394 #define ELF_MACHINE_CODE EM_ARM
15395 #ifdef __QNXTARGET__
15396 #define ELF_MAXPAGESIZE 0x1000
15397 #else
15398 #define ELF_MAXPAGESIZE 0x8000
15399 #endif
15400 #define ELF_MINPAGESIZE 0x1000
15401 #define ELF_COMMONPAGESIZE 0x1000
15403 #define bfd_elf32_mkobject elf32_arm_mkobject
15405 #define bfd_elf32_bfd_copy_private_bfd_data elf32_arm_copy_private_bfd_data
15406 #define bfd_elf32_bfd_merge_private_bfd_data elf32_arm_merge_private_bfd_data
15407 #define bfd_elf32_bfd_set_private_flags elf32_arm_set_private_flags
15408 #define bfd_elf32_bfd_print_private_bfd_data elf32_arm_print_private_bfd_data
15409 #define bfd_elf32_bfd_link_hash_table_create elf32_arm_link_hash_table_create
15410 #define bfd_elf32_bfd_link_hash_table_free elf32_arm_hash_table_free
15411 #define bfd_elf32_bfd_reloc_type_lookup elf32_arm_reloc_type_lookup
15412 #define bfd_elf32_bfd_reloc_name_lookup elf32_arm_reloc_name_lookup
15413 #define bfd_elf32_find_nearest_line elf32_arm_find_nearest_line
15414 #define bfd_elf32_find_inliner_info elf32_arm_find_inliner_info
15415 #define bfd_elf32_new_section_hook elf32_arm_new_section_hook
15416 #define bfd_elf32_bfd_is_target_special_symbol elf32_arm_is_target_special_symbol
15417 #define bfd_elf32_bfd_final_link elf32_arm_final_link
15419 #define elf_backend_get_symbol_type elf32_arm_get_symbol_type
15420 #define elf_backend_gc_mark_hook elf32_arm_gc_mark_hook
15421 #define elf_backend_gc_mark_extra_sections elf32_arm_gc_mark_extra_sections
15422 #define elf_backend_gc_sweep_hook elf32_arm_gc_sweep_hook
15423 #define elf_backend_check_relocs elf32_arm_check_relocs
15424 #define elf_backend_relocate_section elf32_arm_relocate_section
15425 #define elf_backend_write_section elf32_arm_write_section
15426 #define elf_backend_adjust_dynamic_symbol elf32_arm_adjust_dynamic_symbol
15427 #define elf_backend_create_dynamic_sections elf32_arm_create_dynamic_sections
15428 #define elf_backend_finish_dynamic_symbol elf32_arm_finish_dynamic_symbol
15429 #define elf_backend_finish_dynamic_sections elf32_arm_finish_dynamic_sections
15430 #define elf_backend_size_dynamic_sections elf32_arm_size_dynamic_sections
15431 #define elf_backend_always_size_sections elf32_arm_always_size_sections
15432 #define elf_backend_init_index_section _bfd_elf_init_2_index_sections
15433 #define elf_backend_post_process_headers elf32_arm_post_process_headers
15434 #define elf_backend_reloc_type_class elf32_arm_reloc_type_class
15435 #define elf_backend_object_p elf32_arm_object_p
15436 #define elf_backend_fake_sections elf32_arm_fake_sections
15437 #define elf_backend_section_from_shdr elf32_arm_section_from_shdr
15438 #define elf_backend_final_write_processing elf32_arm_final_write_processing
15439 #define elf_backend_copy_indirect_symbol elf32_arm_copy_indirect_symbol
15440 #define elf_backend_size_info elf32_arm_size_info
15441 #define elf_backend_modify_segment_map elf32_arm_modify_segment_map
15442 #define elf_backend_additional_program_headers elf32_arm_additional_program_headers
15443 #define elf_backend_output_arch_local_syms elf32_arm_output_arch_local_syms
15444 #define elf_backend_begin_write_processing elf32_arm_begin_write_processing
15445 #define elf_backend_add_symbol_hook elf32_arm_add_symbol_hook
15447 #define elf_backend_can_refcount 1
15448 #define elf_backend_can_gc_sections 1
15449 #define elf_backend_plt_readonly 1
15450 #define elf_backend_want_got_plt 1
15451 #define elf_backend_want_plt_sym 0
15452 #define elf_backend_may_use_rel_p 1
15453 #define elf_backend_may_use_rela_p 0
15454 #define elf_backend_default_use_rela_p 0
15456 #define elf_backend_got_header_size 12
15458 #undef elf_backend_obj_attrs_vendor
15460 #undef elf_backend_obj_attrs_section
15462 #undef elf_backend_obj_attrs_arg_type
15463 #define elf_backend_obj_attrs_arg_type elf32_arm_obj_attrs_arg_type
15464 #undef elf_backend_obj_attrs_section_type
15465 #define elf_backend_obj_attrs_section_type SHT_ARM_ATTRIBUTES
15466 #define elf_backend_obj_attrs_order elf32_arm_obj_attrs_order
15467 #define elf_backend_obj_attrs_handle_unknown elf32_arm_obj_attrs_handle_unknown
15471 /* VxWorks Targets. */
15473 #undef TARGET_LITTLE_SYM
15474 #define TARGET_LITTLE_SYM bfd_elf32_littlearm_vxworks_vec
15475 #undef TARGET_LITTLE_NAME
15477 #undef TARGET_BIG_SYM
15478 #define TARGET_BIG_SYM bfd_elf32_bigarm_vxworks_vec
15479 #undef TARGET_BIG_NAME
15482 /* Like elf32_arm_link_hash_table_create -- but overrides
15483 appropriately for VxWorks. */
15487 {
15492 {
15497 }
15499 }
15501 static void
15503 {
15506 }
15508 #undef elf32_bed
15509 #define elf32_bed elf32_arm_vxworks_bed
15511 #undef bfd_elf32_bfd_link_hash_table_create
15512 #define bfd_elf32_bfd_link_hash_table_create elf32_arm_vxworks_link_hash_table_create
15513 #undef elf_backend_final_write_processing
15514 #define elf_backend_final_write_processing elf32_arm_vxworks_final_write_processing
15515 #undef elf_backend_emit_relocs
15516 #define elf_backend_emit_relocs elf_vxworks_emit_relocs
15518 #undef elf_backend_may_use_rel_p
15519 #define elf_backend_may_use_rel_p 0
15520 #undef elf_backend_may_use_rela_p
15521 #define elf_backend_may_use_rela_p 1
15522 #undef elf_backend_default_use_rela_p
15523 #define elf_backend_default_use_rela_p 1
15524 #undef elf_backend_want_plt_sym
15525 #define elf_backend_want_plt_sym 1
15526 #undef ELF_MAXPAGESIZE
15527 #define ELF_MAXPAGESIZE 0x1000
15532 /* Merge backend specific data from an object file to the output
15533 object file when linking. */
15535 static bfd_boolean
15537 {
15538 flagword out_flags;
15539 flagword in_flags;
15543 /* Check if we have the same endianness. */
15553 /* The input BFD must have had its flags initialised. */
15554 /* The following seems bogus to me -- The flags are initialized in
15555 the assembler but I don't think an elf_flags_init field is
15556 written into the object. */
15557 /* BFD_ASSERT (elf_flags_init (ibfd)); */
15562 /* In theory there is no reason why we couldn't handle this. However
15563 in practice it isn't even close to working and there is no real
15564 reason to want it. */
15568 {
15570 ibfd);
15572 }
15575 {
15576 /* If the input is the default architecture and had the default
15577 flags then do not bother setting the flags for the output
15578 architecture, instead allow future merges to do this. If no
15579 future merges ever set these flags then they will retain their
15580 uninitialised values, which surprise surprise, correspond
15581 to the default values. */
15594 }
15596 /* Determine what should happen if the input ARM architecture
15597 does not match the output ARM architecture. */
15601 /* Identical flags must be compatible. */
15605 /* Check to see if the input BFD actually contains any sections. If
15606 not, its flags may not have been initialised either, but it
15607 cannot actually cause any incompatiblity. Do not short-circuit
15608 dynamic objects; their section list may be emptied by
15609 elf_link_add_object_symbols.
15611 Also check to see if there are no code sections in the input.
15612 In this case there is no need to check for code specific flags.
15613 XXX - do we need to worry about floating-point format compatability
15614 in data sections ? */
15616 {
15621 {
15622 /* Ignore synthetic glue sections. */
15625 {
15633 }
15634 }
15638 }
15640 /* Complain about various flag mismatches. */
15643 {
15644 _bfd_error_handler
15650 }
15652 /* Not sure what needs to be checked for EABI versions >= 1. */
15653 /* VxWorks libraries do not use these flags. */
15657 {
15659 {
15660 _bfd_error_handler
15666 }
15669 {
15671 _bfd_error_handler
15672 (_("error: %B passes floats in float registers, whereas %B passes them in integer registers"),
15674 else
15675 _bfd_error_handler
15676 (_("error: %B passes floats in integer registers, whereas %B passes them in float registers"),
15680 }
15683 {
15685 _bfd_error_handler
15688 else
15689 _bfd_error_handler
15694 }
15697 {
15699 _bfd_error_handler
15702 else
15703 _bfd_error_handler
15708 }
15710 #ifdef EF_ARM_SOFT_FLOAT
15712 {
15713 /* We can allow interworking between code that is VFP format
15714 layout, and uses either soft float or integer regs for
15715 passing floating point arguments and results. We already
15716 know that the APCS_FLOAT flags match; similarly for VFP
15717 flags. */
15720 {
15722 _bfd_error_handler
15725 else
15726 _bfd_error_handler
15731 }
15732 }
15733 #endif
15735 /* Interworking mismatch is only a warning. */
15737 {
15739 {
15740 _bfd_error_handler
15743 }
15744 else
15745 {
15746 _bfd_error_handler
15749 }
15750 }
15751 }
15754 }
15757 /* Symbian OS Targets. */
15759 #undef TARGET_LITTLE_SYM
15760 #define TARGET_LITTLE_SYM bfd_elf32_littlearm_symbian_vec
15761 #undef TARGET_LITTLE_NAME
15763 #undef TARGET_BIG_SYM
15764 #define TARGET_BIG_SYM bfd_elf32_bigarm_symbian_vec
15765 #undef TARGET_BIG_NAME
15768 /* Like elf32_arm_link_hash_table_create -- but overrides
15769 appropriately for Symbian OS. */
15773 {
15778 {
15781 /* There is no PLT header for Symbian OS. */
15783 /* The PLT entries are each one instruction and one word. */
15786 /* Symbian uses armv5t or above, so use_blx is always true. */
15789 }
15791 }
15793 static const struct bfd_elf_special_section
15794 elf32_arm_symbian_special_sections[] =
15795 {
15796 /* In a BPABI executable, the dynamic linking sections do not go in
15797 the loadable read-only segment. The post-linker may wish to
15798 refer to these sections, but they are not part of the final
15799 program image. */
15805 /* These sections do not need to be writable as the SymbianOS
15806 postlinker will arrange things so that no dynamic relocation is
15807 required. */
15812 };
15814 static void
15817 {
15818 /* BPABI objects are never loaded directly by an OS kernel; they are
15819 processed by a postlinker first, into an OS-specific format. If
15820 the D_PAGED bit is set on the file, BFD will align segments on
15821 page boundaries, so that an OS can directly map the file. With
15822 BPABI objects, that just results in wasted space. In addition,
15823 because we clear the D_PAGED bit, map_sections_to_segments will
15824 recognize that the program headers should not be mapped into any
15825 loadable segment. */
15828 }
15830 static bfd_boolean
15833 {
15837 /* BPABI shared libraries and executables should have a PT_DYNAMIC
15838 segment. However, because the .dynamic section is not marked
15839 with SEC_LOAD, the generic ELF code will not create such a
15840 segment. */
15843 {
15849 {
15853 }
15854 }
15856 /* Also call the generic arm routine. */
15858 }
15860 /* Return address for Ith PLT stub in section PLT, for relocation REL
15861 or (bfd_vma) -1 if it should not be included. */
15863 static bfd_vma
15866 {
15868 }
15871 #undef elf32_bed
15872 #define elf32_bed elf32_arm_symbian_bed
15874 /* The dynamic sections are not allocated on SymbianOS; the postlinker
15875 will process them and then discard them. */
15876 #undef ELF_DYNAMIC_SEC_FLAGS
15877 #define ELF_DYNAMIC_SEC_FLAGS \
15878 (SEC_HAS_CONTENTS | SEC_IN_MEMORY | SEC_LINKER_CREATED)
15880 #undef elf_backend_emit_relocs
15882 #undef bfd_elf32_bfd_link_hash_table_create
15883 #define bfd_elf32_bfd_link_hash_table_create elf32_arm_symbian_link_hash_table_create
15884 #undef elf_backend_special_sections
15885 #define elf_backend_special_sections elf32_arm_symbian_special_sections
15886 #undef elf_backend_begin_write_processing
15887 #define elf_backend_begin_write_processing elf32_arm_symbian_begin_write_processing
15888 #undef elf_backend_final_write_processing
15889 #define elf_backend_final_write_processing elf32_arm_final_write_processing
15891 #undef elf_backend_modify_segment_map
15892 #define elf_backend_modify_segment_map elf32_arm_symbian_modify_segment_map
15894 /* There is no .got section for BPABI objects, and hence no header. */
15895 #undef elf_backend_got_header_size
15896 #define elf_backend_got_header_size 0
15898 /* Similarly, there is no .got.plt section. */
15899 #undef elf_backend_want_got_plt
15900 #define elf_backend_want_got_plt 0
15902 #undef elf_backend_plt_sym_val
15903 #define elf_backend_plt_sym_val elf32_arm_symbian_plt_sym_val
15905 #undef elf_backend_may_use_rel_p
15906 #define elf_backend_may_use_rel_p 1
15907 #undef elf_backend_may_use_rela_p
15908 #define elf_backend_may_use_rela_p 0
15909 #undef elf_backend_default_use_rela_p
15910 #define elf_backend_default_use_rela_p 0
15911 #undef elf_backend_want_plt_sym
15912 #define elf_backend_want_plt_sym 0
15913 #undef ELF_MAXPAGESIZE
15914 #define ELF_MAXPAGESIZE 0x8000