opcodes/i386-opc.h

   1 /* Declarations for Intel 80386 opcode table
   2    Copyright 2007
   3    Free Software Foundation, Inc.
   4
   5    This file is part of the GNU opcodes library.
   6
   7    This library is free software; you can redistribute it and/or modify
   8    it under the terms of the GNU General Public License as published by
   9    the Free Software Foundation; either version 3, or (at your option)
  10    any later version.
  11
  12    It is distributed in the hope that it will be useful, but WITHOUT
  13    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  14    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  15    License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with GAS; see the file COPYING.  If not, write to the Free
  19    Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
  20    02110-1301, USA.  */
  21
  22 #include "opcode/i386.h"
  23 #ifdef HAVE_LIMITS_H
  24 #include <limits.h>
  25 #endif
  26
  27 #ifndef CHAR_BIT
  28 #define CHAR_BIT 8
  29 #endif
  30
  31 /* Position of cpu flags bitfiled.  */
  32
  33 /* i186 or better required */
  34 #define Cpu186          0
  35 /* i286 or better required */
  36 #define Cpu286          (Cpu186 + 1)
  37 /* i386 or better required */
  38 #define Cpu386          (Cpu286 + 1)
  39 /* i486 or better required */
  40 #define Cpu486          (Cpu386 + 1)
  41 /* i585 or better required */
  42 #define Cpu586          (Cpu486 + 1)
  43 /* i686 or better required */
  44 #define Cpu686          (Cpu586 + 1)
  45 /* Pentium4 or better required */
  46 #define CpuP4           (Cpu686 + 1)
  47 /* AMD K6 or better required*/
  48 #define CpuK6           (CpuP4 + 1)
  49 /* AMD K8 or better required */
  50 #define CpuK8           (CpuK6 + 1)
  51 /* MMX support required */
  52 #define CpuMMX          (CpuK8 + 1)
  53 /* extended MMX support (with SSE or 3DNow!Ext) required */
  54 #define CpuMMX2         (CpuMMX + 1)
  55 /* SSE support required */
  56 #define CpuSSE          (CpuMMX2 + 1)
  57 /* SSE2 support required */
  58 #define CpuSSE2         (CpuSSE + 1)
  59 /* 3dnow! support required */
  60 #define Cpu3dnow        (CpuSSE2 + 1)
  61 /* 3dnow! Extensions support required */
  62 #define Cpu3dnowA       (Cpu3dnow + 1)
  63 /* SSE3 support required */
  64 #define CpuSSE3         (Cpu3dnowA + 1)
  65 /* VIA PadLock required */
  66 #define CpuPadLock      (CpuSSE3 + 1)
  67 /* AMD Secure Virtual Machine Ext-s required */
  68 #define CpuSVME         (CpuPadLock + 1)
  69 /* VMX Instructions required */
  70 #define CpuVMX          (CpuSVME + 1)
  71 /* SMX Instructions required */
  72 #define CpuSMX          (CpuVMX + 1)
  73 /* SSSE3 support required */
  74 #define CpuSSSE3        (CpuSMX + 1)
  75 /* SSE4a support required */
  76 #define CpuSSE4a        (CpuSSSE3 + 1)
  77 /* ABM New Instructions required */
  78 #define CpuABM          (CpuSSE4a + 1)
  79 /* SSE4.1 support required */
  80 #define CpuSSE4_1       (CpuABM + 1)
  81 /* SSE4.2 support required */
  82 #define CpuSSE4_2       (CpuSSE4_1 + 1)
  83 /* SSE5 support required */
  84 #define CpuSSE5         (CpuSSE4_2 + 1)
  85 /* 64bit support available, used by -march= in assembler.  */
  86 #define CpuLM           (CpuSSE5 + 1)
  87 /* 64bit support required  */
  88 #define Cpu64           (CpuLM + 1)
  89 /* Not supported in the 64bit mode  */
  90 #define CpuNo64         (Cpu64 + 1)
  91 /* The last bitfield in i386_cpu_flags.  */
  92 #define CpuMax          CpuNo64
  93
  94 #define CpuNumOfUints \
  95   (CpuMax / sizeof (unsigned int) / CHAR_BIT + 1)
  96 #define CpuNumOfBits \
  97   (CpuNumOfUints * sizeof (unsigned int) * CHAR_BIT)
  98
  99 /* If you get a compiler error for zero width of the unused field,
 100    comment it out.  */
 101 #define CpuUnused       (CpuMax + 1)
 102
 103 /* We can check if an instruction is available with array instead
 104    of bitfield. */
 105 typedef union i386_cpu_flags
 106 {
 107   struct
 108     {
 109       unsigned int cpui186:1;
 110       unsigned int cpui286:1;
 111       unsigned int cpui386:1;
 112       unsigned int cpui486:1;
 113       unsigned int cpui586:1;
 114       unsigned int cpui686:1;
 115       unsigned int cpup4:1;
 116       unsigned int cpuk6:1;
 117       unsigned int cpuk8:1;
 118       unsigned int cpummx:1;
 119       unsigned int cpummx2:1;
 120       unsigned int cpusse:1;
 121       unsigned int cpusse2:1;
 122       unsigned int cpua3dnow:1;
 123       unsigned int cpua3dnowa:1;
 124       unsigned int cpusse3:1;
 125       unsigned int cpupadlock:1;
 126       unsigned int cpusvme:1;
 127       unsigned int cpuvmx:1;
 128       unsigned int cpusmx:1;
 129       unsigned int cpussse3:1;
 130       unsigned int cpusse4a:1;
 131       unsigned int cpuabm:1;
 132       unsigned int cpusse4_1:1;
 133       unsigned int cpusse4_2:1;
 134       unsigned int cpusse5:1;
 135       unsigned int cpulm:1;
 136       unsigned int cpu64:1;
 137       unsigned int cpuno64:1;
 138 #ifdef CpuUnused
 139       unsigned int unused:(CpuNumOfBits - CpuUnused);
 140 #endif
 141     } bitfield;
 142   unsigned int array[CpuNumOfUints];
 143 } i386_cpu_flags;
 144
 145 /* Position of opcode_modifier bits.  */
 146
 147 /* has direction bit. */
 148 #define D                       0
 149 /* set if operands can be words or dwords encoded the canonical way */
 150 #define W                       (D + 1)
 151 /* insn has a modrm byte. */
 152 #define Modrm                   (W + 1)
 153 /* register is in low 3 bits of opcode */
 154 #define ShortForm               (Modrm + 1)
 155 /* special case for jump insns.  */
 156 #define Jump                    (ShortForm + 1)
 157 /* call and jump */
 158 #define JumpDword               (Jump + 1)
 159 /* loop and jecxz */
 160 #define JumpByte                (JumpDword + 1)
 161 /* special case for intersegment leaps/calls */
 162 #define JumpInterSegment        (JumpByte + 1)
 163 /* FP insn memory format bit, sized by 0x4 */
 164 #define FloatMF                 (JumpInterSegment + 1)
 165 /* src/dest swap for floats. */
 166 #define FloatR                  (FloatMF + 1)
 167 /* has float insn direction bit. */
 168 #define FloatD                  (FloatR + 1)
 169 /* needs size prefix if in 32-bit mode */
 170 #define Size16                  (FloatD + 1)
 171 /* needs size prefix if in 16-bit mode */
 172 #define Size32                  (Size16 + 1)
 173 /* needs size prefix if in 64-bit mode */
 174 #define Size64                  (Size32 + 1)
 175 /* instruction ignores operand size prefix */
 176 #define IgnoreSize              (Size64 + 1)
 177 /* default insn size depends on mode */
 178 #define DefaultSize             (IgnoreSize + 1)
 179 /* b suffix on instruction illegal */
 180 #define No_bSuf                 (DefaultSize + 1)
 181 /* w suffix on instruction illegal */
 182 #define No_wSuf                 (No_bSuf + 1)
 183 /* l suffix on instruction illegal */
 184 #define No_lSuf                 (No_wSuf + 1)
 185 /* s suffix on instruction illegal */
 186 #define No_sSuf                 (No_lSuf + 1)
 187 /* q suffix on instruction illegal */
 188 #define No_qSuf                 (No_sSuf + 1)
 189 /* long double suffix on instruction illegal */
 190 #define No_ldSuf                (No_qSuf + 1)
 191 /* instruction needs FWAIT */
 192 #define FWait                   (No_ldSuf + 1)
 193 /* quick test for string instructions */
 194 #define IsString                (FWait + 1)
 195 /* fake an extra reg operand for clr, imul and special register
 196    processing for some instructions.  */
 197 #define RegKludge               (IsString + 1)
 198 /* The first operand must be xmm0 */
 199 #define FirstXmm0               (RegKludge + 1)
 200 /* BYTE is OK in Intel syntax. */
 201 #define ByteOkIntel             (FirstXmm0 + 1)
 202 /* Convert to DWORD */
 203 #define ToDword                 (ByteOkIntel + 1)
 204 /* Convert to QWORD */
 205 #define ToQword                 (ToDword + 1)
 206 /* Address prefix changes operand 0 */
 207 #define AddrPrefixOp0           (ToQword + 1)
 208 /* opcode is a prefix */
 209 #define IsPrefix                (AddrPrefixOp0 + 1)
 210 /* instruction has extension in 8 bit imm */
 211 #define ImmExt                  (IsPrefix + 1)
 212 /* instruction don't need Rex64 prefix.  */
 213 #define NoRex64                 (ImmExt + 1)
 214 /* instruction require Rex64 prefix.  */
 215 #define Rex64                   (NoRex64 + 1)
 216 /* deprecated fp insn, gets a warning */
 217 #define Ugh                     (Rex64 + 1)
 218 #define Drex                    (Ugh + 1)
 219 /* instruction needs DREX with multiple encodings for memory ops */
 220 #define Drexv                   (Drex + 1)
 221 /* special DREX for comparisons */
 222 #define Drexc                   (Drexv + 1)
 223 /* The last bitfield in i386_opcode_modifier.  */
 224 #define Opcode_Modifier_Max     Drexc
 225
 226 typedef struct i386_opcode_modifier
 227 {
 228   unsigned int d:1;
 229   unsigned int w:1;
 230   unsigned int modrm:1;
 231   unsigned int shortform:1;
 232   unsigned int jump:1;
 233   unsigned int jumpdword:1;
 234   unsigned int jumpbyte:1;
 235   unsigned int jumpintersegment:1;
 236   unsigned int floatmf:1;
 237   unsigned int floatr:1;
 238   unsigned int floatd:1;
 239   unsigned int size16:1;
 240   unsigned int size32:1;
 241   unsigned int size64:1;
 242   unsigned int ignoresize:1;
 243   unsigned int defaultsize:1;
 244   unsigned int no_bsuf:1;
 245   unsigned int no_wsuf:1;
 246   unsigned int no_lsuf:1;
 247   unsigned int no_ssuf:1;
 248   unsigned int no_qsuf:1;
 249   unsigned int no_ldsuf:1;
 250   unsigned int fwait:1;
 251   unsigned int isstring:1;
 252   unsigned int regkludge:1;
 253   unsigned int firstxmm0:1;
 254   unsigned int byteokintel:1;
 255   unsigned int todword:1;
 256   unsigned int toqword:1;
 257   unsigned int addrprefixop0:1;
 258   unsigned int isprefix:1;
 259   unsigned int immext:1;
 260   unsigned int norex64:1;
 261   unsigned int rex64:1;
 262   unsigned int ugh:1;
 263   unsigned int drex:1;
 264   unsigned int drexv:1;
 265   unsigned int drexc:1;
 266 } i386_opcode_modifier;
 267
 268 /* Position of operand_type bits.  */
 269
 270 /* Registers  */
 271
 272 /* 8 bit reg */
 273 #define Reg8                    0
 274 /* 16 bit reg */
 275 #define Reg16                   (Reg8 + 1)
 276 /* 32 bit reg */
 277 #define Reg32                   (Reg16 + 1)
 278 /* 64 bit reg */
 279 #define Reg64                   (Reg32 + 1)
 280
 281 /* immediate */
 282
 283 /* 8 bit immediate */
 284 #define Imm8                    (Reg64 + 1)
 285 /* 8 bit immediate sign extended */
 286 #define Imm8S                   (Imm8 + 1)
 287 /* 16 bit immediate */
 288 #define Imm16                   (Imm8S + 1)
 289 /* 32 bit immediate */
 290 #define Imm32                   (Imm16 + 1)
 291 /* 32 bit immediate sign extended */
 292 #define Imm32S                  (Imm32 + 1)
 293 /* 64 bit immediate */
 294 #define Imm64                   (Imm32S + 1)
 295 /* 1 bit immediate */
 296 #define Imm1                    (Imm64 + 1)
 297
 298 /* memory */
 299
 300 #define BaseIndex               (Imm1 + 1)
 301 /* Disp8,16,32 are used in different ways, depending on the
 302    instruction.  For jumps, they specify the size of the PC relative
 303    displacement, for baseindex type instructions, they specify the
 304    size of the offset relative to the base register, and for memory
 305    offset instructions such as `mov 1234,%al' they specify the size of
 306    the offset relative to the segment base.  */
 307 /* 8 bit displacement */
 308 #define Disp8                   (BaseIndex + 1)
 309 /* 16 bit displacement */
 310 #define Disp16                  (Disp8 + 1)
 311 /* 32 bit displacement */
 312 #define Disp32                  (Disp16 + 1)
 313 /* 32 bit signed displacement */
 314 #define Disp32S                 (Disp32 + 1)
 315 /* 64 bit displacement */
 316 #define Disp64                  (Disp32S + 1)
 317
 318 /* specials */
 319
 320 /* register to hold in/out port addr = dx */
 321 #define InOutPortReg            (Disp64 + 1)
 322 /* register to hold shift count = cl */
 323 #define ShiftCount              (InOutPortReg + 1)
 324 /* Control register */
 325 #define Control                 (ShiftCount + 1)
 326 /* Debug register */
 327 #define Debug                   (Control + 1)
 328 /* Test register */
 329 #define Test                    (Debug + 1)
 330 /* Float register */
 331 #define FloatReg                (Test + 1)
 332 /* Float stack top %st(0) */
 333 #define FloatAcc                (FloatReg + 1)
 334 /* 2 bit segment register */
 335 #define SReg2                   (FloatAcc + 1)
 336 /* 3 bit segment register */
 337 #define SReg3                   (SReg2 + 1)
 338 /* Accumulator %al or %ax or %eax */
 339 #define Acc                     (SReg3 + 1)
 340 #define JumpAbsolute            (Acc + 1)
 341 /* MMX register */
 342 #define RegMMX                  (JumpAbsolute + 1)
 343 /* XMM registers in PIII */
 344 #define RegXMM                  (RegMMX + 1)
 345 /* String insn operand with fixed es segment */
 346 #define EsSeg                   (RegXMM + 1)
 347
 348 /* RegMem is for instructions with a modrm byte where the register
 349    destination operand should be encoded in the mod and regmem fields.
 350    Normally, it will be encoded in the reg field. We add a RegMem
 351    flag to the destination register operand to indicate that it should
 352    be encoded in the regmem field.  */
 353 #define RegMem                  (EsSeg + 1)
 354
 355 /* The last bitfield in i386_operand_type.  */
 356 #define OTMax                   RegMem
 357
 358 #define OTNumOfUints \
 359   (OTMax / sizeof (unsigned int) / CHAR_BIT + 1)
 360 #define OTNumOfBits \
 361   (OTNumOfUints * sizeof (unsigned int) * CHAR_BIT)
 362
 363 /* If you get a compiler error for zero width of the unused field,
 364    comment it out.  */
 365 #if 0
 366 #define OTUnused                (OTMax + 1)
 367 #endif
 368
 369 typedef union i386_operand_type
 370 {
 371   struct
 372     {
 373       unsigned int reg8:1;
 374       unsigned int reg16:1;
 375       unsigned int reg32:1;
 376       unsigned int reg64:1;
 377       unsigned int imm8:1;
 378       unsigned int imm8s:1;
 379       unsigned int imm16:1;
 380       unsigned int imm32:1;
 381       unsigned int imm32s:1;
 382       unsigned int imm64:1;
 383       unsigned int imm1:1;
 384       unsigned int baseindex:1;
 385       unsigned int disp8:1;
 386       unsigned int disp16:1;
 387       unsigned int disp32:1;
 388       unsigned int disp32s:1;
 389       unsigned int disp64:1;
 390       unsigned int inoutportreg:1;
 391       unsigned int shiftcount:1;
 392       unsigned int control:1;
 393       unsigned int debug:1;
 394       unsigned int test:1;
 395       unsigned int floatreg:1;
 396       unsigned int floatacc:1;
 397       unsigned int sreg2:1;
 398       unsigned int sreg3:1;
 399       unsigned int acc:1;
 400       unsigned int jumpabsolute:1;
 401       unsigned int regmmx:1;
 402       unsigned int regxmm:1;
 403       unsigned int esseg:1;
 404       unsigned int regmem:1;
 405 #ifdef OTUnused
 406       unsigned int unused:(OTNumOfBits - OTUnused);
 407 #endif
 408     } bitfield;
 409   unsigned int array[OTNumOfUints];
 410 } i386_operand_type;
 411
 412 typedef struct template
 413 {
 414   /* instruction name sans width suffix ("mov" for movl insns) */
 415   char *name;
 416
 417   /* how many operands */
 418   unsigned int operands;
 419
 420   /* base_opcode is the fundamental opcode byte without optional
 421      prefix(es).  */
 422   unsigned int base_opcode;
 423 #define Opcode_D        0x2 /* Direction bit:
 424                                set if Reg --> Regmem;
 425                                unset if Regmem --> Reg. */
 426 #define Opcode_FloatR   0x8 /* Bit to swap src/dest for float insns. */
 427 #define Opcode_FloatD 0x400 /* Direction bit for float insns. */
 428
 429   /* extension_opcode is the 3 bit extension for group <n> insns.
 430      This field is also used to store the 8-bit opcode suffix for the
 431      AMD 3DNow! instructions.
 432      If this template has no extension opcode (the usual case) use None
 433      Instructions with Drex use this to specify 2 bits for OC */
 434   unsigned int extension_opcode;
 435 #define None 0xffff             /* If no extension_opcode is possible.  */
 436
 437   /* Opcode length.  */
 438   unsigned char opcode_length;
 439
 440   /* cpu feature flags */
 441   i386_cpu_flags cpu_flags;
 442
 443   /* the bits in opcode_modifier are used to generate the final opcode from
 444      the base_opcode.  These bits also are used to detect alternate forms of
 445      the same instruction */
 446   i386_opcode_modifier opcode_modifier;
 447
 448   /* operand_types[i] describes the type of operand i.  This is made
 449      by OR'ing together all of the possible type masks.  (e.g.
 450      'operand_types[i] = Reg|Imm' specifies that operand i can be
 451      either a register or an immediate operand.  */
 452   i386_operand_type operand_types[MAX_OPERANDS];
 453 }
 454 template;
 455
 456 extern const template i386_optab[];
 457
 458 /* these are for register name --> number & type hash lookup */
 459 typedef struct
 460 {
 461   char *reg_name;
 462   i386_operand_type reg_type;
 463   unsigned int reg_flags;
 464 #define RegRex      0x1  /* Extended register.  */
 465 #define RegRex64    0x2  /* Extended 8 bit register.  */
 466   unsigned int reg_num;
 467 #define RegRip  ((unsigned int ) ~0)
 468 #define RegEip  (RegRip - 1)
 469 /* EIZ and RIZ are fake index registers.  */
 470 #define RegEiz  (RegEip - 1)
 471 #define RegRiz  (RegEiz - 1)
 472 }
 473 reg_entry;
 474
 475 /* Entries in i386_regtab.  */
 476 #define REGNAM_AL 1
 477 #define REGNAM_AX 25
 478 #define REGNAM_EAX 41
 479
 480 extern const reg_entry i386_regtab[];
 481 extern const unsigned int i386_regtab_size;
 482
 483 typedef struct
 484 {
 485   char *seg_name;
 486   unsigned int seg_prefix;
 487 }
 488 seg_entry;
 489
 490 extern const seg_entry cs;
 491 extern const seg_entry ds;
 492 extern const seg_entry ss;
 493 extern const seg_entry es;
 494 extern const seg_entry fs;
 495 extern const seg_entry gs;