include/opcode/arc.h

   1 /* Opcode table for the ARC.
   2    Copyright 1994, 1995, 1997, 2001 Free Software Foundation, Inc.
   3    Contributed by Doug Evans (dje@cygnus.com).
   4
   5    This file is part of GAS, the GNU Assembler, GDB, the GNU debugger, and
   6    the GNU Binutils.
   7
   8    GAS/GDB is free software; you can redistribute it and/or modify
   9    it under the terms of the GNU General Public License as published by
  10    the Free Software Foundation; either version 2, or (at your option)
  11    any later version.
  12
  13    GAS/GDB is distributed in the hope that it will be useful,
  14    but WITHOUT ANY WARRANTY; without even the implied warranty of
  15    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16    GNU General Public License for more details.
  17
  18    You should have received a copy of the GNU General Public License
  19    along with GAS or GDB; see the file COPYING. If not, write to
  20    the Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
  21
  22
  23 /* List of the various cpu types.
  24    The tables currently use bit masks to say whether the instruction or
  25    whatever is supported by a particular cpu.  This lets us have one entry
  26    apply to several cpus.
  27
  28    The `base' cpu must be 0. The cpu type is treated independently of
  29    endianness. The complete `mach' number includes endianness.
  30    These values are internal to opcodes/bfd/binutils/gas.  */
  31 #define ARC_MACH_5 0
  32 #define ARC_MACH_6 1
  33 #define ARC_MACH_7 2
  34 #define ARC_MACH_8 4
  35
  36 /* Additional cpu values can be inserted here and ARC_MACH_BIG moved down.  */
  37 #define ARC_MACH_BIG 16
  38
  39 /* Mask of number of bits necessary to record cpu type.  */
  40 #define ARC_MACH_CPU_MASK (ARC_MACH_BIG - 1)
  41
  42 /* Mask of number of bits necessary to record cpu type + endianness.  */
  43 #define ARC_MACH_MASK ((ARC_MACH_BIG << 1) - 1)
  44
  45 /* Type to denote an ARC instruction (at least a 32 bit unsigned int).  */
  46
  47 typedef unsigned int arc_insn;
  48
  49 struct arc_opcode {
  50   char *syntax;              /* syntax of insn  */
  51   unsigned long mask, value; /* recognize insn if (op&mask) == value  */
  52   int flags;                 /* various flag bits  */
  53
  54 /* Values for `flags'.  */
  55
  56 /* Return CPU number, given flag bits.  */
  57 #define ARC_OPCODE_CPU(bits) ((bits) & ARC_MACH_CPU_MASK)
  58
  59 /* Return MACH number, given flag bits.  */
  60 #define ARC_OPCODE_MACH(bits) ((bits) & ARC_MACH_MASK)
  61
  62 /* First opcode flag bit available after machine mask.  */
  63 #define ARC_OPCODE_FLAG_START (ARC_MACH_MASK + 1)
  64
  65 /* This insn is a conditional branch.  */
  66 #define ARC_OPCODE_COND_BRANCH (ARC_OPCODE_FLAG_START)
  67 #define SYNTAX_3OP             (ARC_OPCODE_COND_BRANCH << 1)
  68 #define SYNTAX_LENGTH          (SYNTAX_3OP                 )
  69 #define SYNTAX_2OP             (SYNTAX_3OP             << 1)
  70 #define OP1_MUST_BE_IMM        (SYNTAX_2OP             << 1)
  71 #define OP1_IMM_IMPLIED        (OP1_MUST_BE_IMM        << 1)
  72 #define SYNTAX_VALID           (OP1_IMM_IMPLIED        << 1)
  73
  74 #define I(x) (((x) & 31) << 27)
  75 #define A(x) (((x) & ARC_MASK_REG) << ARC_SHIFT_REGA)
  76 #define B(x) (((x) & ARC_MASK_REG) << ARC_SHIFT_REGB)
  77 #define C(x) (((x) & ARC_MASK_REG) << ARC_SHIFT_REGC)
  78 #define R(x,b,m) (((x) & (m)) << (b)) /* value X, mask M, at bit B */
  79
  80 /* These values are used to optimize assembly and disassembly.  Each insn
  81    is on a list of related insns (same first letter for assembly, same
  82    insn code for disassembly).  */
  83
  84   struct arc_opcode *next_asm;  /* Next instr to try during assembly.  */
  85   struct arc_opcode *next_dis;  /* Next instr to try during disassembly.  */
  86
  87 /* Macros to create the hash values for the lists.  */
  88 #define ARC_HASH_OPCODE(string) \
  89   ((string)[0] >= 'a' && (string)[0] <= 'z' ? (string)[0] - 'a' : 26)
  90 #define ARC_HASH_ICODE(insn) \
  91   ((unsigned int) (insn) >> 27)
  92
  93  /* Macros to access `next_asm', `next_dis' so users needn't care about the
  94     underlying mechanism.  */
  95 #define ARC_OPCODE_NEXT_ASM(op) ((op)->next_asm)
  96 #define ARC_OPCODE_NEXT_DIS(op) ((op)->next_dis)
  97 };
  98
  99 /* this is an "insert at front" linked list per Metaware spec
 100    that new definitions override older ones.  */
 101 struct arc_opcode *arc_ext_opcodes;
 102
 103 struct arc_operand_value {
 104   char *name;          /* eg: "eq"  */
 105   short value;         /* eg: 1  */
 106   unsigned char type;  /* index into `arc_operands'  */
 107   unsigned char flags; /* various flag bits  */
 108
 109 /* Values for `flags'.  */
 110
 111 /* Return CPU number, given flag bits.  */
 112 #define ARC_OPVAL_CPU(bits) ((bits) & ARC_MACH_CPU_MASK)
 113 /* Return MACH number, given flag bits.  */
 114 #define ARC_OPVAL_MACH(bits) ((bits) & ARC_MACH_MASK)
 115 };
 116
 117 struct arc_ext_operand_value {
 118   struct arc_ext_operand_value *next;
 119   struct arc_operand_value operand;
 120 } *arc_ext_operands;
 121
 122 struct arc_operand {
 123 /* One of the insn format chars.  */
 124   unsigned char fmt;
 125
 126 /* The number of bits in the operand (may be unused for a modifier).  */
 127   unsigned char bits;
 128
 129 /* How far the operand is left shifted in the instruction, or
 130    the modifier's flag bit (may be unused for a modifier.  */
 131   unsigned char shift;
 132
 133 /* Various flag bits.  */
 134   int flags;
 135
 136 /* Values for `flags'.  */
 137
 138 /* This operand is a suffix to the opcode.  */
 139 #define ARC_OPERAND_SUFFIX 1
 140
 141 /* This operand is a relative branch displacement.  The disassembler
 142    prints these symbolically if possible.  */
 143 #define ARC_OPERAND_RELATIVE_BRANCH 2
 144
 145 /* This operand is an absolute branch address.  The disassembler
 146    prints these symbolically if possible.  */
 147 #define ARC_OPERAND_ABSOLUTE_BRANCH 4
 148
 149 /* This operand is an address.  The disassembler
 150    prints these symbolically if possible.  */
 151 #define ARC_OPERAND_ADDRESS 8
 152
 153 /* This operand is a long immediate value.  */
 154 #define ARC_OPERAND_LIMM 0x10
 155
 156 /* This operand takes signed values.  */
 157 #define ARC_OPERAND_SIGNED 0x20
 158
 159 /* This operand takes signed values, but also accepts a full positive
 160    range of values.  That is, if bits is 16, it takes any value from
 161    -0x8000 to 0xffff.  */
 162 #define ARC_OPERAND_SIGNOPT 0x40
 163
 164 /* This operand should be regarded as a negative number for the
 165    purposes of overflow checking (i.e., the normal most negative
 166    number is disallowed and one more than the normal most positive
 167    number is allowed).  This flag will only be set for a signed
 168    operand.  */
 169 #define ARC_OPERAND_NEGATIVE 0x80
 170
 171 /* This operand doesn't really exist.  The program uses these operands
 172    in special ways.  */
 173 #define ARC_OPERAND_FAKE 0x100
 174
 175 /* separate flags operand for j and jl instructions  */
 176 #define ARC_OPERAND_JUMPFLAGS 0x200
 177
 178 /* allow warnings and errors to be issued after call to insert_xxxxxx  */
 179 #define ARC_OPERAND_WARN  0x400
 180 #define ARC_OPERAND_ERROR 0x800
 181
 182 /* this is a load operand */
 183 #define ARC_OPERAND_LOAD  0x8000
 184
 185 /* this is a store operand */
 186 #define ARC_OPERAND_STORE 0x10000
 187
 188 /* Modifier values.  */
 189 /* A dot is required before a suffix.  Eg: .le  */
 190 #define ARC_MOD_DOT 0x1000
 191
 192 /* A normal register is allowed (not used, but here for completeness).  */
 193 #define ARC_MOD_REG 0x2000
 194
 195 /* An auxiliary register name is expected.  */
 196 #define ARC_MOD_AUXREG 0x4000
 197
 198 /* Sum of all ARC_MOD_XXX bits.  */
 199 #define ARC_MOD_BITS 0x7000
 200
 201 /* Non-zero if the operand type is really a modifier.  */
 202 #define ARC_MOD_P(X) ((X) & ARC_MOD_BITS)
 203
 204 /* enforce read/write only register restrictions  */
 205 #define ARC_REGISTER_READONLY    0x01
 206 #define ARC_REGISTER_WRITEONLY   0x02
 207 #define ARC_REGISTER_NOSHORT_CUT 0x04
 208
 209 /* Insertion function.  This is used by the assembler.  To insert an
 210    operand value into an instruction, check this field.
 211
 212    If it is NULL, execute
 213    i |= (p & ((1 << o->bits) - 1)) << o->shift;
 214    (I is the instruction which we are filling in, O is a pointer to
 215    this structure, and OP is the opcode value; this assumes twos
 216    complement arithmetic).
 217
 218    If this field is not NULL, then simply call it with the
 219    instruction and the operand value.  It will return the new value
 220    of the instruction.  If the ERRMSG argument is not NULL, then if
 221    the operand value is illegal, *ERRMSG will be set to a warning
 222    string (the operand will be inserted in any case).  If the
 223    operand value is legal, *ERRMSG will be unchanged.
 224
 225    REG is non-NULL when inserting a register value.  */
 226
 227   arc_insn (*insert) PARAMS ((arc_insn insn,
 228                               const struct arc_operand *operand, int mods,
 229                               const struct arc_operand_value *reg, long value,
 230                               const char **errmsg));
 231
 232 /* Extraction function.  This is used by the disassembler.  To
 233    extract this operand type from an instruction, check this field.
 234
 235    If it is NULL, compute
 236      op = ((i) >> o->shift) & ((1 << o->bits) - 1);
 237      if ((o->flags & ARC_OPERAND_SIGNED) != 0
 238           && (op & (1 << (o->bits - 1))) != 0)
 239        op -= 1 << o->bits;
 240    (I is the instruction, O is a pointer to this structure, and OP
 241    is the result; this assumes twos complement arithmetic).
 242
 243    If this field is not NULL, then simply call it with the
 244    instruction value.  It will return the value of the operand.  If
 245    the INVALID argument is not NULL, *INVALID will be set to
 246    non-zero if this operand type can not actually be extracted from
 247    this operand (i.e., the instruction does not match).  If the
 248    operand is valid, *INVALID will not be changed.
 249
 250    INSN is a pointer to an array of two `arc_insn's.  The first element is
 251    the insn, the second is the limm if present.
 252
 253    Operands that have a printable form like registers and suffixes have
 254    their struct arc_operand_value pointer stored in OPVAL.  */
 255
 256   long (*extract) PARAMS ((arc_insn *insn,
 257                            const struct arc_operand *operand,
 258                            int mods, const struct arc_operand_value **opval,
 259                            int *invalid));
 260 };
 261
 262 /* Bits that say what version of cpu we have. These should be passed to
 263    arc_init_opcode_tables. At present, all there is is the cpu type.  */
 264
 265 /* CPU number, given value passed to `arc_init_opcode_tables'.  */
 266 #define ARC_HAVE_CPU(bits) ((bits) & ARC_MACH_CPU_MASK)
 267 /* MACH number, given value passed to `arc_init_opcode_tables'.  */
 268 #define ARC_HAVE_MACH(bits) ((bits) & ARC_MACH_MASK)
 269
 270 /* Special register values:  */
 271 #define ARC_REG_SHIMM_UPDATE 61
 272 #define ARC_REG_SHIMM 63
 273 #define ARC_REG_LIMM 62
 274
 275 /* Non-zero if REG is a constant marker.  */
 276 #define ARC_REG_CONSTANT_P(REG) ((REG) >= 61)
 277
 278 /* Positions and masks of various fields:  */
 279 #define ARC_SHIFT_REGA 21
 280 #define ARC_SHIFT_REGB 15
 281 #define ARC_SHIFT_REGC 9
 282 #define ARC_MASK_REG 63
 283
 284 /* Delay slot types.  */
 285 #define ARC_DELAY_NONE 0   /* no delay slot */
 286 #define ARC_DELAY_NORMAL 1 /* delay slot in both cases */
 287 #define ARC_DELAY_JUMP 2   /* delay slot only if branch taken */
 288
 289 /* Non-zero if X will fit in a signed 9 bit field.  */
 290 #define ARC_SHIMM_CONST_P(x) ((long) (x) >= -256 && (long) (x) <= 255)
 291
 292 extern const struct arc_operand arc_operands[];
 293 extern const int arc_operand_count;
 294 extern struct arc_opcode arc_opcodes[];
 295 extern const int arc_opcodes_count;
 296 extern const struct arc_operand_value arc_suffixes[];
 297 extern const int arc_suffixes_count;
 298 extern const struct arc_operand_value arc_reg_names[];
 299 extern const int arc_reg_names_count;
 300 extern unsigned char arc_operand_map[];
 301
 302 /* Utility fns in arc-opc.c.  */
 303 int arc_get_opcode_mach PARAMS ((int, int));
 304
 305 /* `arc_opcode_init_tables' must be called before `arc_xxx_supported'.  */
 306 void arc_opcode_init_tables PARAMS ((int));
 307 void arc_opcode_init_insert PARAMS ((void));
 308 void arc_opcode_init_extract PARAMS ((void));
 309 const struct arc_opcode *arc_opcode_lookup_asm PARAMS ((const char *));
 310 const struct arc_opcode *arc_opcode_lookup_dis PARAMS ((unsigned int));
 311 int arc_opcode_limm_p PARAMS ((long *));
 312 const struct arc_operand_value *arc_opcode_lookup_suffix
 313   PARAMS ((const struct arc_operand *type, int value));
 314 int arc_opcode_supported PARAMS ((const struct arc_opcode *));
 315 int arc_opval_supported PARAMS ((const struct arc_operand_value *));
 316 int arc_limm_fixup_adjust PARAMS ((arc_insn));
 317 int arc_insn_is_j PARAMS ((arc_insn));
 318 int arc_insn_not_jl PARAMS ((arc_insn));
 319 int arc_operand_type PARAMS ((int));
 320 struct arc_operand_value *get_ext_suffix PARAMS ((char *));
 321 int arc_get_noshortcut_flag PARAMS ((void));