opcodes/ppc-opc.c

   1 /* ppc-opc.c -- PowerPC opcode list
   2    Copyright (c) 1994, 95, 96, 97, 98, 99, 2000 Free Software Foundation, Inc.
   3    Written by Ian Lance Taylor, Cygnus Support
   4
   5 This file is part of GDB, GAS, and the GNU binutils.
   6
   7 GDB, GAS, and the GNU binutils are free software; you can redistribute
   8 them and/or modify them under the terms of the GNU General Public
   9 License as published by the Free Software Foundation; either version
  10 2, or (at your option) any later version.
  11
  12 GDB, GAS, and the GNU binutils are distributed in the hope that they
  13 will be useful, but WITHOUT ANY WARRANTY; without even the implied
  14 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
  15 the GNU General Public License for more details.
  16
  17 You should have received a copy of the GNU General Public License
  18 along with this file; see the file COPYING.  If not, write to the Free
  19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
  20 02111-1307, USA.  */
  21
  22 #include <stdio.h>
  23 #include "sysdep.h"
  24 #include "opcode/ppc.h"
  25 #include "opintl.h"
  26
  27 /* This file holds the PowerPC opcode table.  The opcode table
  28    includes almost all of the extended instruction mnemonics.  This
  29    permits the disassembler to use them, and simplifies the assembler
  30    logic, at the cost of increasing the table size.  The table is
  31    strictly constant data, so the compiler should be able to put it in
  32    the .text section.
  33
  34    This file also holds the operand table.  All knowledge about
  35    inserting operands into instructions and vice-versa is kept in this
  36    file.  */
  37 \f
  38 /* Local insertion and extraction functions.  */
  39
  40 static unsigned long insert_bat PARAMS ((unsigned long, long, const char **));
  41 static long extract_bat PARAMS ((unsigned long, int *));
  42 static unsigned long insert_bba PARAMS ((unsigned long, long, const char **));
  43 static long extract_bba PARAMS ((unsigned long, int *));
  44 static unsigned long insert_bd PARAMS ((unsigned long, long, const char **));
  45 static long extract_bd PARAMS ((unsigned long, int *));
  46 static unsigned long insert_bdm PARAMS ((unsigned long, long, const char **));
  47 static long extract_bdm PARAMS ((unsigned long, int *));
  48 static unsigned long insert_bdp PARAMS ((unsigned long, long, const char **));
  49 static long extract_bdp PARAMS ((unsigned long, int *));
  50 static int valid_bo PARAMS ((long));
  51 static unsigned long insert_bo PARAMS ((unsigned long, long, const char **));
  52 static long extract_bo PARAMS ((unsigned long, int *));
  53 static unsigned long insert_boe PARAMS ((unsigned long, long, const char **));
  54 static long extract_boe PARAMS ((unsigned long, int *));
  55 static unsigned long insert_ds PARAMS ((unsigned long, long, const char **));
  56 static long extract_ds PARAMS ((unsigned long, int *));
  57 static unsigned long insert_li PARAMS ((unsigned long, long, const char **));
  58 static long extract_li PARAMS ((unsigned long, int *));
  59 static unsigned long insert_mbe PARAMS ((unsigned long, long, const char **));
  60 static long extract_mbe PARAMS ((unsigned long, int *));
  61 static unsigned long insert_mb6 PARAMS ((unsigned long, long, const char **));
  62 static long extract_mb6 PARAMS ((unsigned long, int *));
  63 static unsigned long insert_nb PARAMS ((unsigned long, long, const char **));
  64 static long extract_nb PARAMS ((unsigned long, int *));
  65 static unsigned long insert_nsi PARAMS ((unsigned long, long, const char **));
  66 static long extract_nsi PARAMS ((unsigned long, int *));
  67 static unsigned long insert_ral PARAMS ((unsigned long, long, const char **));
  68 static unsigned long insert_ram PARAMS ((unsigned long, long, const char **));
  69 static unsigned long insert_ras PARAMS ((unsigned long, long, const char **));
  70 static unsigned long insert_rbs PARAMS ((unsigned long, long, const char **));
  71 static long extract_rbs PARAMS ((unsigned long, int *));
  72 static unsigned long insert_sh6 PARAMS ((unsigned long, long, const char **));
  73 static long extract_sh6 PARAMS ((unsigned long, int *));
  74 static unsigned long insert_spr PARAMS ((unsigned long, long, const char **));
  75 static long extract_spr PARAMS ((unsigned long, int *));
  76 static unsigned long insert_tbr PARAMS ((unsigned long, long, const char **));
  77 static long extract_tbr PARAMS ((unsigned long, int *));
  78 \f
  79 /* The operands table.
  80
  81    The fields are bits, shift, insert, extract, flags.
  82
  83    We used to put parens around the various additions, like the one
  84    for BA just below.  However, that caused trouble with feeble
  85    compilers with a limit on depth of a parenthesized expression, like
  86    (reportedly) the compiler in Microsoft Developer Studio 5.  So we
  87    omit the parens, since the macros are never used in a context where
  88    the addition will be ambiguous.  */
  89
  90 const struct powerpc_operand powerpc_operands[] =
  91 {
  92   /* The zero index is used to indicate the end of the list of
  93      operands.  */
  94 #define UNUSED 0
  95   { 0, 0, 0, 0, 0 },
  96
  97   /* The BA field in an XL form instruction.  */
  98 #define BA UNUSED + 1
  99 #define BA_MASK (0x1f << 16)
 100   { 5, 16, 0, 0, PPC_OPERAND_CR },
 101
 102   /* The BA field in an XL form instruction when it must be the same
 103      as the BT field in the same instruction.  */
 104 #define BAT BA + 1
 105   { 5, 16, insert_bat, extract_bat, PPC_OPERAND_FAKE },
 106
 107   /* The BB field in an XL form instruction.  */
 108 #define BB BAT + 1
 109 #define BB_MASK (0x1f << 11)
 110   { 5, 11, 0, 0, PPC_OPERAND_CR },
 111
 112   /* The BB field in an XL form instruction when it must be the same
 113      as the BA field in the same instruction.  */
 114 #define BBA BB + 1
 115   { 5, 11, insert_bba, extract_bba, PPC_OPERAND_FAKE },
 116
 117   /* The BD field in a B form instruction.  The lower two bits are
 118      forced to zero.  */
 119 #define BD BBA + 1
 120   { 16, 0, insert_bd, extract_bd, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
 121
 122   /* The BD field in a B form instruction when absolute addressing is
 123      used.  */
 124 #define BDA BD + 1
 125   { 16, 0, insert_bd, extract_bd, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
 126
 127   /* The BD field in a B form instruction when the - modifier is used.
 128      This sets the y bit of the BO field appropriately.  */
 129 #define BDM BDA + 1
 130   { 16, 0, insert_bdm, extract_bdm,
 131       PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
 132
 133   /* The BD field in a B form instruction when the - modifier is used
 134      and absolute address is used.  */
 135 #define BDMA BDM + 1
 136   { 16, 0, insert_bdm, extract_bdm,
 137       PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
 138
 139   /* The BD field in a B form instruction when the + modifier is used.
 140      This sets the y bit of the BO field appropriately.  */
 141 #define BDP BDMA + 1
 142   { 16, 0, insert_bdp, extract_bdp,
 143       PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
 144
 145   /* The BD field in a B form instruction when the + modifier is used
 146      and absolute addressing is used.  */
 147 #define BDPA BDP + 1
 148   { 16, 0, insert_bdp, extract_bdp,
 149       PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
 150
 151   /* The BF field in an X or XL form instruction.  */
 152 #define BF BDPA + 1
 153   { 3, 23, 0, 0, PPC_OPERAND_CR },
 154
 155   /* An optional BF field.  This is used for comparison instructions,
 156      in which an omitted BF field is taken as zero.  */
 157 #define OBF BF + 1
 158   { 3, 23, 0, 0, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL },
 159
 160   /* The BFA field in an X or XL form instruction.  */
 161 #define BFA OBF + 1
 162   { 3, 18, 0, 0, PPC_OPERAND_CR },
 163
 164   /* The BI field in a B form or XL form instruction.  */
 165 #define BI BFA + 1
 166 #define BI_MASK (0x1f << 16)
 167   { 5, 16, 0, 0, PPC_OPERAND_CR },
 168
 169   /* The BO field in a B form instruction.  Certain values are
 170      illegal.  */
 171 #define BO BI + 1
 172 #define BO_MASK (0x1f << 21)
 173   { 5, 21, insert_bo, extract_bo, 0 },
 174
 175   /* The BO field in a B form instruction when the + or - modifier is
 176      used.  This is like the BO field, but it must be even.  */
 177 #define BOE BO + 1
 178   { 5, 21, insert_boe, extract_boe, 0 },
 179
 180   /* The BT field in an X or XL form instruction.  */
 181 #define BT BOE + 1
 182   { 5, 21, 0, 0, PPC_OPERAND_CR },
 183
 184   /* The condition register number portion of the BI field in a B form
 185      or XL form instruction.  This is used for the extended
 186      conditional branch mnemonics, which set the lower two bits of the
 187      BI field.  This field is optional.  */
 188 #define CR BT + 1
 189   { 3, 18, 0, 0, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL },
 190
 191   /* The D field in a D form instruction.  This is a displacement off
 192      a register, and implies that the next operand is a register in
 193      parentheses.  */
 194 #define D CR + 1
 195   { 16, 0, 0, 0, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
 196
 197   /* The DS field in a DS form instruction.  This is like D, but the
 198      lower two bits are forced to zero.  */
 199 #define DS D + 1
 200   { 16, 0, insert_ds, extract_ds, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
 201
 202   /* The E field in a wrteei instruction.  */
 203 #define E DS + 1
 204   { 1, 15, 0, 0, 0 },
 205
 206   /* The FL1 field in a POWER SC form instruction.  */
 207 #define FL1 E + 1
 208   { 4, 12, 0, 0, 0 },
 209
 210   /* The FL2 field in a POWER SC form instruction.  */
 211 #define FL2 FL1 + 1
 212   { 3, 2, 0, 0, 0 },
 213
 214   /* The FLM field in an XFL form instruction.  */
 215 #define FLM FL2 + 1
 216   { 8, 17, 0, 0, 0 },
 217
 218   /* The FRA field in an X or A form instruction.  */
 219 #define FRA FLM + 1
 220 #define FRA_MASK (0x1f << 16)
 221   { 5, 16, 0, 0, PPC_OPERAND_FPR },
 222
 223   /* The FRB field in an X or A form instruction.  */
 224 #define FRB FRA + 1
 225 #define FRB_MASK (0x1f << 11)
 226   { 5, 11, 0, 0, PPC_OPERAND_FPR },
 227
 228   /* The FRC field in an A form instruction.  */
 229 #define FRC FRB + 1
 230 #define FRC_MASK (0x1f << 6)
 231   { 5, 6, 0, 0, PPC_OPERAND_FPR },
 232
 233   /* The FRS field in an X form instruction or the FRT field in a D, X
 234      or A form instruction.  */
 235 #define FRS FRC + 1
 236 #define FRT FRS
 237   { 5, 21, 0, 0, PPC_OPERAND_FPR },
 238
 239   /* The FXM field in an XFX instruction.  */
 240 #define FXM FRS + 1
 241 #define FXM_MASK (0xff << 12)
 242   { 8, 12, 0, 0, 0 },
 243
 244   /* The L field in a D or X form instruction.  */
 245 #define L FXM + 1
 246   { 1, 21, 0, 0, PPC_OPERAND_OPTIONAL },
 247
 248   /* The LEV field in a POWER SC form instruction.  */
 249 #define LEV L + 1
 250   { 7, 5, 0, 0, 0 },
 251
 252   /* The LI field in an I form instruction.  The lower two bits are
 253      forced to zero.  */
 254 #define LI LEV + 1
 255   { 26, 0, insert_li, extract_li, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
 256
 257   /* The LI field in an I form instruction when used as an absolute
 258      address.  */
 259 #define LIA LI + 1
 260   { 26, 0, insert_li, extract_li, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
 261
 262   /* The MB field in an M form instruction.  */
 263 #define MB LIA + 1
 264 #define MB_MASK (0x1f << 6)
 265   { 5, 6, 0, 0, 0 },
 266
 267   /* The ME field in an M form instruction.  */
 268 #define ME MB + 1
 269 #define ME_MASK (0x1f << 1)
 270   { 5, 1, 0, 0, 0 },
 271
 272   /* The MB and ME fields in an M form instruction expressed a single
 273      operand which is a bitmask indicating which bits to select.  This
 274      is a two operand form using PPC_OPERAND_NEXT.  See the
 275      description in opcode/ppc.h for what this means.  */
 276 #define MBE ME + 1
 277   { 5, 6, 0, 0, PPC_OPERAND_OPTIONAL | PPC_OPERAND_NEXT },
 278   { 32, 0, insert_mbe, extract_mbe, 0 },
 279
 280   /* The MB or ME field in an MD or MDS form instruction.  The high
 281      bit is wrapped to the low end.  */
 282 #define MB6 MBE + 2
 283 #define ME6 MB6
 284 #define MB6_MASK (0x3f << 5)
 285   { 6, 5, insert_mb6, extract_mb6, 0 },
 286
 287   /* The NB field in an X form instruction.  The value 32 is stored as
 288      0.  */
 289 #define NB MB6 + 1
 290   { 6, 11, insert_nb, extract_nb, 0 },
 291
 292   /* The NSI field in a D form instruction.  This is the same as the
 293      SI field, only negated.  */
 294 #define NSI NB + 1
 295   { 16, 0, insert_nsi, extract_nsi,
 296       PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED },
 297
 298   /* The RA field in an D, DS, X, XO, M, or MDS form instruction.  */
 299 #define RA NSI + 1
 300 #define RA_MASK (0x1f << 16)
 301   { 5, 16, 0, 0, PPC_OPERAND_GPR },
 302
 303   /* The RA field in a D or X form instruction which is an updating
 304      load, which means that the RA field may not be zero and may not
 305      equal the RT field.  */
 306 #define RAL RA + 1
 307   { 5, 16, insert_ral, 0, PPC_OPERAND_GPR },
 308
 309   /* The RA field in an lmw instruction, which has special value
 310      restrictions.  */
 311 #define RAM RAL + 1
 312   { 5, 16, insert_ram, 0, PPC_OPERAND_GPR },
 313
 314   /* The RA field in a D or X form instruction which is an updating
 315      store or an updating floating point load, which means that the RA
 316      field may not be zero.  */
 317 #define RAS RAM + 1
 318   { 5, 16, insert_ras, 0, PPC_OPERAND_GPR },
 319
 320   /* The RB field in an X, XO, M, or MDS form instruction.  */
 321 #define RB RAS + 1
 322 #define RB_MASK (0x1f << 11)
 323   { 5, 11, 0, 0, PPC_OPERAND_GPR },
 324
 325   /* The RB field in an X form instruction when it must be the same as
 326      the RS field in the instruction.  This is used for extended
 327      mnemonics like mr.  */
 328 #define RBS RB + 1
 329   { 5, 1, insert_rbs, extract_rbs, PPC_OPERAND_FAKE },
 330
 331   /* The RS field in a D, DS, X, XFX, XS, M, MD or MDS form
 332      instruction or the RT field in a D, DS, X, XFX or XO form
 333      instruction.  */
 334 #define RS RBS + 1
 335 #define RT RS
 336 #define RT_MASK (0x1f << 21)
 337   { 5, 21, 0, 0, PPC_OPERAND_GPR },
 338
 339   /* The SH field in an X or M form instruction.  */
 340 #define SH RS + 1
 341 #define SH_MASK (0x1f << 11)
 342   { 5, 11, 0, 0, 0 },
 343
 344   /* The SH field in an MD form instruction.  This is split.  */
 345 #define SH6 SH + 1
 346 #define SH6_MASK ((0x1f << 11) | (1 << 1))
 347   { 6, 1, insert_sh6, extract_sh6, 0 },
 348
 349   /* The SI field in a D form instruction.  */
 350 #define SI SH6 + 1
 351   { 16, 0, 0, 0, PPC_OPERAND_SIGNED },
 352
 353   /* The SI field in a D form instruction when we accept a wide range
 354      of positive values.  */
 355 #define SISIGNOPT SI + 1
 356   { 16, 0, 0, 0, PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT },
 357
 358   /* The SPR field in an XFX form instruction.  This is flipped--the
 359      lower 5 bits are stored in the upper 5 and vice- versa.  */
 360 #define SPR SISIGNOPT + 1
 361 #define SPR_MASK (0x3ff << 11)
 362   { 10, 11, insert_spr, extract_spr, 0 },
 363
 364   /* The BAT index number in an XFX form m[ft]ibat[lu] instruction.  */
 365 #define SPRBAT SPR + 1
 366 #define SPRBAT_MASK (0x3 << 17)
 367   { 2, 17, 0, 0, 0 },
 368
 369   /* The SPRG register number in an XFX form m[ft]sprg instruction.  */
 370 #define SPRG SPRBAT + 1
 371 #define SPRG_MASK (0x3 << 16)
 372   { 2, 16, 0, 0, 0 },
 373
 374   /* The SR field in an X form instruction.  */
 375 #define SR SPRG + 1
 376   { 4, 16, 0, 0, 0 },
 377
 378   /* The SV field in a POWER SC form instruction.  */
 379 #define SV SR + 1
 380   { 14, 2, 0, 0, 0 },
 381
 382   /* The TBR field in an XFX form instruction.  This is like the SPR
 383      field, but it is optional.  */
 384 #define TBR SV + 1
 385   { 10, 11, insert_tbr, extract_tbr, PPC_OPERAND_OPTIONAL },
 386
 387   /* The TO field in a D or X form instruction.  */
 388 #define TO TBR + 1
 389 #define TO_MASK (0x1f << 21)
 390   { 5, 21, 0, 0, 0 },
 391
 392   /* The U field in an X form instruction.  */
 393 #define U TO + 1
 394   { 4, 12, 0, 0, 0 },
 395
 396   /* The UI field in a D form instruction.  */
 397 #define UI U + 1
 398   { 16, 0, 0, 0, 0 },
 399
 400   /* The VA field in a VA, VX or VXR form instruction. */
 401 #define VA UI + 1
 402 #define VA_MASK (0x1f << 16)
 403   {5, 16, 0, 0, PPC_OPERAND_VR},
 404
 405   /* The VB field in a VA, VX or VXR form instruction. */
 406 #define VB VA + 1
 407 #define VB_MASK (0x1f << 11)
 408   {5, 11, 0, 0, PPC_OPERAND_VR},
 409
 410   /* The VC field in a VA form instruction. */
 411 #define VC VB + 1
 412 #define VC_MASK (0x1f << 6)
 413   {5, 6, 0, 0, PPC_OPERAND_VR},
 414
 415   /* The VD or VS field in a VA, VX, VXR or X form instruction. */
 416 #define VD VC + 1
 417 #define VS VD
 418 #define VD_MASK (0x1f << 21)
 419   {5, 21, 0, 0, PPC_OPERAND_VR},
 420
 421   /* The SIMM field in a VX form instruction. */
 422 #define SIMM VD + 1
 423   { 5, 16, 0, 0, PPC_OPERAND_SIGNED},
 424
 425   /* The UIMM field in a VX form instruction. */
 426 #define UIMM SIMM + 1
 427   { 5, 16, 0, 0, 0 },
 428
 429   /* The SHB field in a VA form instruction. */
 430 #define SHB UIMM + 1
 431   { 4, 6, 0, 0, 0 },
 432 };
 433
 434 /* The functions used to insert and extract complicated operands.  */
 435
 436 /* The BA field in an XL form instruction when it must be the same as
 437    the BT field in the same instruction.  This operand is marked FAKE.
 438    The insertion function just copies the BT field into the BA field,
 439    and the extraction function just checks that the fields are the
 440    same.  */
 441
 442 /*ARGSUSED*/
 443 static unsigned long
 444 insert_bat (insn, value, errmsg)
 445      unsigned long insn;
 446      long value ATTRIBUTE_UNUSED;
 447      const char **errmsg ATTRIBUTE_UNUSED;
 448 {
 449   return insn | (((insn >> 21) & 0x1f) << 16);
 450 }
 451
 452 static long
 453 extract_bat (insn, invalid)
 454      unsigned long insn;
 455      int *invalid;
 456 {
 457   if (invalid != (int *) NULL
 458       && ((insn >> 21) & 0x1f) != ((insn >> 16) & 0x1f))
 459     *invalid = 1;
 460   return 0;
 461 }
 462
 463 /* The BB field in an XL form instruction when it must be the same as
 464    the BA field in the same instruction.  This operand is marked FAKE.
 465    The insertion function just copies the BA field into the BB field,
 466    and the extraction function just checks that the fields are the
 467    same.  */
 468
 469 /*ARGSUSED*/
 470 static unsigned long
 471 insert_bba (insn, value, errmsg)
 472      unsigned long insn;
 473      long value ATTRIBUTE_UNUSED;
 474      const char **errmsg ATTRIBUTE_UNUSED;
 475 {
 476   return insn | (((insn >> 16) & 0x1f) << 11);
 477 }
 478
 479 static long
 480 extract_bba (insn, invalid)
 481      unsigned long insn;
 482      int *invalid;
 483 {
 484   if (invalid != (int *) NULL
 485       && ((insn >> 16) & 0x1f) != ((insn >> 11) & 0x1f))
 486     *invalid = 1;
 487   return 0;
 488 }
 489
 490 /* The BD field in a B form instruction.  The lower two bits are
 491    forced to zero.  */
 492
 493 /*ARGSUSED*/
 494 static unsigned long
 495 insert_bd (insn, value, errmsg)
 496      unsigned long insn;
 497      long value;
 498      const char **errmsg ATTRIBUTE_UNUSED;
 499 {
 500   return insn | (value & 0xfffc);
 501 }
 502
 503 /*ARGSUSED*/
 504 static long
 505 extract_bd (insn, invalid)
 506      unsigned long insn;
 507      int *invalid ATTRIBUTE_UNUSED;
 508 {
 509   if ((insn & 0x8000) != 0)
 510     return (insn & 0xfffc) - 0x10000;
 511   else
 512     return insn & 0xfffc;
 513 }
 514
 515 /* The BD field in a B form instruction when the - modifier is used.
 516    This modifier means that the branch is not expected to be taken.
 517    We must set the y bit of the BO field to 1 if the offset is
 518    negative.  When extracting, we require that the y bit be 1 and that
 519    the offset be positive, since if the y bit is 0 we just want to
 520    print the normal form of the instruction.  */
 521
 522 /*ARGSUSED*/
 523 static unsigned long
 524 insert_bdm (insn, value, errmsg)
 525      unsigned long insn;
 526      long value;
 527      const char **errmsg ATTRIBUTE_UNUSED;
 528 {
 529   if ((value & 0x8000) != 0)
 530     insn |= 1 << 21;
 531   return insn | (value & 0xfffc);
 532 }
 533
 534 static long
 535 extract_bdm (insn, invalid)
 536      unsigned long insn;
 537      int *invalid;
 538 {
 539   if (invalid != (int *) NULL
 540       && ((insn & (1 << 21)) == 0
 541           || (insn & (1 << 15)) == 0))
 542     *invalid = 1;
 543   if ((insn & 0x8000) != 0)
 544     return (insn & 0xfffc) - 0x10000;
 545   else
 546     return insn & 0xfffc;
 547 }
 548
 549 /* The BD field in a B form instruction when the + modifier is used.
 550    This is like BDM, above, except that the branch is expected to be
 551    taken.  */
 552
 553 /*ARGSUSED*/
 554 static unsigned long
 555 insert_bdp (insn, value, errmsg)
 556      unsigned long insn;
 557      long value;
 558      const char **errmsg ATTRIBUTE_UNUSED;
 559 {
 560   if ((value & 0x8000) == 0)
 561     insn |= 1 << 21;
 562   return insn | (value & 0xfffc);
 563 }
 564
 565 static long
 566 extract_bdp (insn, invalid)
 567      unsigned long insn;
 568      int *invalid;
 569 {
 570   if (invalid != (int *) NULL
 571       && ((insn & (1 << 21)) == 0
 572           || (insn & (1 << 15)) != 0))
 573     *invalid = 1;
 574   if ((insn & 0x8000) != 0)
 575     return (insn & 0xfffc) - 0x10000;
 576   else
 577     return insn & 0xfffc;
 578 }
 579
 580 /* Check for legal values of a BO field.  */
 581
 582 static int
 583 valid_bo (value)
 584      long value;
 585 {
 586   /* Certain encodings have bits that are required to be zero.  These
 587      are (z must be zero, y may be anything):
 588          001zy
 589          011zy
 590          1z00y
 591          1z01y
 592          1z1zz
 593      */
 594   switch (value & 0x14)
 595     {
 596     default:
 597     case 0:
 598       return 1;
 599     case 0x4:
 600       return (value & 0x2) == 0;
 601     case 0x10:
 602       return (value & 0x8) == 0;
 603     case 0x14:
 604       return value == 0x14;
 605     }
 606 }
 607
 608 /* The BO field in a B form instruction.  Warn about attempts to set
 609    the field to an illegal value.  */
 610
 611 static unsigned long
 612 insert_bo (insn, value, errmsg)
 613      unsigned long insn;
 614      long value;
 615      const char **errmsg;
 616 {
 617   if (errmsg != (const char **) NULL
 618       && ! valid_bo (value))
 619     *errmsg = _("invalid conditional option");
 620   return insn | ((value & 0x1f) << 21);
 621 }
 622
 623 static long
 624 extract_bo (insn, invalid)
 625      unsigned long insn;
 626      int *invalid;
 627 {
 628   long value;
 629
 630   value = (insn >> 21) & 0x1f;
 631   if (invalid != (int *) NULL
 632       && ! valid_bo (value))
 633     *invalid = 1;
 634   return value;
 635 }
 636
 637 /* The BO field in a B form instruction when the + or - modifier is
 638    used.  This is like the BO field, but it must be even.  When
 639    extracting it, we force it to be even.  */
 640
 641 static unsigned long
 642 insert_boe (insn, value, errmsg)
 643      unsigned long insn;
 644      long value;
 645      const char **errmsg;
 646 {
 647   if (errmsg != (const char **) NULL)
 648     {
 649       if (! valid_bo (value))
 650         *errmsg = _("invalid conditional option");
 651       else if ((value & 1) != 0)
 652         *errmsg = _("attempt to set y bit when using + or - modifier");
 653     }
 654   return insn | ((value & 0x1f) << 21);
 655 }
 656
 657 static long
 658 extract_boe (insn, invalid)
 659      unsigned long insn;
 660      int *invalid;
 661 {
 662   long value;
 663
 664   value = (insn >> 21) & 0x1f;
 665   if (invalid != (int *) NULL
 666       && ! valid_bo (value))
 667     *invalid = 1;
 668   return value & 0x1e;
 669 }
 670
 671 /* The DS field in a DS form instruction.  This is like D, but the
 672    lower two bits are forced to zero.  */
 673
 674 /*ARGSUSED*/
 675 static unsigned long
 676 insert_ds (insn, value, errmsg)
 677      unsigned long insn;
 678      long value;
 679      const char **errmsg ATTRIBUTE_UNUSED;
 680 {
 681   return insn | (value & 0xfffc);
 682 }
 683
 684 /*ARGSUSED*/
 685 static long
 686 extract_ds (insn, invalid)
 687      unsigned long insn;
 688      int *invalid ATTRIBUTE_UNUSED;
 689 {
 690   if ((insn & 0x8000) != 0)
 691     return (insn & 0xfffc) - 0x10000;
 692   else
 693     return insn & 0xfffc;
 694 }
 695
 696 /* The LI field in an I form instruction.  The lower two bits are
 697    forced to zero.  */
 698
 699 /*ARGSUSED*/
 700 static unsigned long
 701 insert_li (insn, value, errmsg)
 702      unsigned long insn;
 703      long value;
 704      const char **errmsg;
 705 {
 706   if ((value & 3) != 0 && errmsg != (const char **) NULL)
 707     *errmsg = _("ignoring least significant bits in branch offset");
 708   return insn | (value & 0x3fffffc);
 709 }
 710
 711 /*ARGSUSED*/
 712 static long
 713 extract_li (insn, invalid)
 714      unsigned long insn;
 715      int *invalid ATTRIBUTE_UNUSED;
 716 {
 717   if ((insn & 0x2000000) != 0)
 718     return (insn & 0x3fffffc) - 0x4000000;
 719   else
 720     return insn & 0x3fffffc;
 721 }
 722
 723 /* The MB and ME fields in an M form instruction expressed as a single
 724    operand which is itself a bitmask.  The extraction function always
 725    marks it as invalid, since we never want to recognize an
 726    instruction which uses a field of this type.  */
 727
 728 static unsigned long
 729 insert_mbe (insn, value, errmsg)
 730      unsigned long insn;
 731      long value;
 732      const char **errmsg;
 733 {
 734   unsigned long uval, mask;
 735   int mb, me, mx, count, last;
 736
 737   uval = value;
 738
 739   if (uval == 0)
 740     {
 741       if (errmsg != (const char **) NULL)
 742         *errmsg = _("illegal bitmask");
 743       return insn;
 744     }
 745
 746   mb = 0;
 747   me = 32;
 748   if ((uval & 1) != 0)
 749     last = 1;
 750   else
 751     last = 0;
 752   count = 0;
 753
 754   /* mb: location of last 0->1 transition */
 755   /* me: location of last 1->0 transition */
 756   /* count: # transitions */
 757
 758   for (mx = 0, mask = 1 << 31; mx < 32; ++mx, mask >>= 1)
 759     {
 760       if ((uval & mask) && !last)
 761         {
 762           ++count;
 763           mb = mx;
 764           last = 1;
 765         }
 766       else if (!(uval & mask) && last)
 767         {
 768           ++count;
 769           me = mx;
 770           last = 0;
 771         }
 772     }
 773   if (me == 0)
 774     me = 32;
 775
 776   if (count != 2 && (count != 0 || ! last))
 777     {
 778       if (errmsg != (const char **) NULL)
 779         *errmsg = _("illegal bitmask");
 780     }
 781
 782   return insn | (mb << 6) | ((me - 1) << 1);
 783 }
 784
 785 static long
 786 extract_mbe (insn, invalid)
 787      unsigned long insn;
 788      int *invalid;
 789 {
 790   long ret;
 791   int mb, me;
 792   int i;
 793
 794   if (invalid != (int *) NULL)
 795     *invalid = 1;
 796
 797   mb = (insn >> 6) & 0x1f;
 798   me = (insn >> 1) & 0x1f;
 799   if (mb < me + 1)
 800     {
 801       ret = 0;
 802       for (i = mb; i <= me; i++)
 803         ret |= (long) 1 << (31 - i);
 804     }
 805   else if (mb == me + 1)
 806     ret = ~0;
 807   else /* (mb > me + 1) */
 808     {
 809       ret = ~ (long) 0;
 810       for (i = me + 1; i < mb; i++)
 811         ret &= ~ ((long) 1 << (31 - i));
 812     }
 813   return ret;
 814 }
 815
 816 /* The MB or ME field in an MD or MDS form instruction.  The high bit
 817    is wrapped to the low end.  */
 818
 819 /*ARGSUSED*/
 820 static unsigned long
 821 insert_mb6 (insn, value, errmsg)
 822      unsigned long insn;
 823      long value;
 824      const char **errmsg ATTRIBUTE_UNUSED;
 825 {
 826   return insn | ((value & 0x1f) << 6) | (value & 0x20);
 827 }
 828
 829 /*ARGSUSED*/
 830 static long
 831 extract_mb6 (insn, invalid)
 832      unsigned long insn;
 833      int *invalid ATTRIBUTE_UNUSED;
 834 {
 835   return ((insn >> 6) & 0x1f) | (insn & 0x20);
 836 }
 837
 838 /* The NB field in an X form instruction.  The value 32 is stored as
 839    0.  */
 840
 841 static unsigned long
 842 insert_nb (insn, value, errmsg)
 843      unsigned long insn;
 844      long value;
 845      const char **errmsg;
 846 {
 847   if (value < 0 || value > 32)
 848     *errmsg = _("value out of range");
 849   if (value == 32)
 850     value = 0;
 851   return insn | ((value & 0x1f) << 11);
 852 }
 853
 854 /*ARGSUSED*/
 855 static long
 856 extract_nb (insn, invalid)
 857      unsigned long insn;
 858      int *invalid ATTRIBUTE_UNUSED;
 859 {
 860   long ret;
 861
 862   ret = (insn >> 11) & 0x1f;
 863   if (ret == 0)
 864     ret = 32;
 865   return ret;
 866 }
 867
 868 /* The NSI field in a D form instruction.  This is the same as the SI
 869    field, only negated.  The extraction function always marks it as
 870    invalid, since we never want to recognize an instruction which uses
 871    a field of this type.  */
 872
 873 /*ARGSUSED*/
 874 static unsigned long
 875 insert_nsi (insn, value, errmsg)
 876      unsigned long insn;
 877      long value;
 878      const char **errmsg ATTRIBUTE_UNUSED;
 879 {
 880   return insn | ((- value) & 0xffff);
 881 }
 882
 883 static long
 884 extract_nsi (insn, invalid)
 885      unsigned long insn;
 886      int *invalid;
 887 {
 888   if (invalid != (int *) NULL)
 889     *invalid = 1;
 890   if ((insn & 0x8000) != 0)
 891     return - ((long)(insn & 0xffff) - 0x10000);
 892   else
 893     return - (long)(insn & 0xffff);
 894 }
 895
 896 /* The RA field in a D or X form instruction which is an updating
 897    load, which means that the RA field may not be zero and may not
 898    equal the RT field.  */
 899
 900 static unsigned long
 901 insert_ral (insn, value, errmsg)
 902      unsigned long insn;
 903      long value;
 904      const char **errmsg;
 905 {
 906   if (value == 0
 907       || (unsigned long) value == ((insn >> 21) & 0x1f))
 908     *errmsg = "invalid register operand when updating";
 909   return insn | ((value & 0x1f) << 16);
 910 }
 911
 912 /* The RA field in an lmw instruction, which has special value
 913    restrictions.  */
 914
 915 static unsigned long
 916 insert_ram (insn, value, errmsg)
 917      unsigned long insn;
 918      long value;
 919      const char **errmsg;
 920 {
 921   if ((unsigned long) value >= ((insn >> 21) & 0x1f))
 922     *errmsg = _("index register in load range");
 923   return insn | ((value & 0x1f) << 16);
 924 }
 925
 926 /* The RA field in a D or X form instruction which is an updating
 927    store or an updating floating point load, which means that the RA
 928    field may not be zero.  */
 929
 930 static unsigned long
 931 insert_ras (insn, value, errmsg)
 932      unsigned long insn;
 933      long value;
 934      const char **errmsg;
 935 {
 936   if (value == 0)
 937     *errmsg = _("invalid register operand when updating");
 938   return insn | ((value & 0x1f) << 16);
 939 }
 940
 941 /* The RB field in an X form instruction when it must be the same as
 942    the RS field in the instruction.  This is used for extended
 943    mnemonics like mr.  This operand is marked FAKE.  The insertion
 944    function just copies the BT field into the BA field, and the
 945    extraction function just checks that the fields are the same.  */
 946
 947 /*ARGSUSED*/
 948 static unsigned long
 949 insert_rbs (insn, value, errmsg)
 950      unsigned long insn;
 951      long value ATTRIBUTE_UNUSED;
 952      const char **errmsg ATTRIBUTE_UNUSED;
 953 {
 954   return insn | (((insn >> 21) & 0x1f) << 11);
 955 }
 956
 957 static long
 958 extract_rbs (insn, invalid)
 959      unsigned long insn;
 960      int *invalid;
 961 {
 962   if (invalid != (int *) NULL
 963       && ((insn >> 21) & 0x1f) != ((insn >> 11) & 0x1f))
 964     *invalid = 1;
 965   return 0;
 966 }
 967
 968 /* The SH field in an MD form instruction.  This is split.  */
 969
 970 /*ARGSUSED*/
 971 static unsigned long
 972 insert_sh6 (insn, value, errmsg)
 973      unsigned long insn;
 974      long value;
 975      const char **errmsg ATTRIBUTE_UNUSED;
 976 {
 977   return insn | ((value & 0x1f) << 11) | ((value & 0x20) >> 4);
 978 }
 979
 980 /*ARGSUSED*/
 981 static long
 982 extract_sh6 (insn, invalid)
 983      unsigned long insn;
 984      int *invalid ATTRIBUTE_UNUSED;
 985 {
 986   return ((insn >> 11) & 0x1f) | ((insn << 4) & 0x20);
 987 }
 988
 989 /* The SPR field in an XFX form instruction.  This is flipped--the
 990    lower 5 bits are stored in the upper 5 and vice- versa.  */
 991
 992 static unsigned long
 993 insert_spr (insn, value, errmsg)
 994      unsigned long insn;
 995      long value;
 996      const char **errmsg ATTRIBUTE_UNUSED;
 997 {
 998   return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6);
 999 }
1000
1001 static long
1002 extract_spr (insn, invalid)
1003      unsigned long insn;
1004      int *invalid ATTRIBUTE_UNUSED;
1005 {
1006   return ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0);
1007 }
1008
1009 /* The TBR field in an XFX instruction.  This is just like SPR, but it
1010    is optional.  When TBR is omitted, it must be inserted as 268 (the
1011    magic number of the TB register).  These functions treat 0
1012    (indicating an omitted optional operand) as 268.  This means that
1013    ``mftb 4,0'' is not handled correctly.  This does not matter very
1014    much, since the architecture manual does not define mftb as
1015    accepting any values other than 268 or 269.  */
1016
1017 #define TB (268)
1018
1019 static unsigned long
1020 insert_tbr (insn, value, errmsg)
1021      unsigned long insn;
1022      long value;
1023      const char **errmsg ATTRIBUTE_UNUSED;
1024 {
1025   if (value == 0)
1026     value = TB;
1027   return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6);
1028 }
1029
1030 static long
1031 extract_tbr (insn, invalid)
1032      unsigned long insn;
1033      int *invalid ATTRIBUTE_UNUSED;
1034 {
1035   long ret;
1036
1037   ret = ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0);
1038   if (ret == TB)
1039     ret = 0;
1040   return ret;
1041 }
1042 \f
1043 /* Macros used to form opcodes.  */
1044
1045 /* The main opcode.  */
1046 #define OP(x) ((((unsigned long)(x)) & 0x3f) << 26)
1047 #define OP_MASK OP (0x3f)
1048
1049 /* The main opcode combined with a trap code in the TO field of a D
1050    form instruction.  Used for extended mnemonics for the trap
1051    instructions.  */
1052 #define OPTO(x,to) (OP (x) | ((((unsigned long)(to)) & 0x1f) << 21))
1053 #define OPTO_MASK (OP_MASK | TO_MASK)
1054
1055 /* The main opcode combined with a comparison size bit in the L field
1056    of a D form or X form instruction.  Used for extended mnemonics for
1057    the comparison instructions.  */
1058 #define OPL(x,l) (OP (x) | ((((unsigned long)(l)) & 1) << 21))
1059 #define OPL_MASK OPL (0x3f,1)
1060
1061 /* An A form instruction.  */
1062 #define A(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1) | (((unsigned long)(rc)) & 1))
1063 #define A_MASK A (0x3f, 0x1f, 1)
1064
1065 /* An A_MASK with the FRB field fixed.  */
1066 #define AFRB_MASK (A_MASK | FRB_MASK)
1067
1068 /* An A_MASK with the FRC field fixed.  */
1069 #define AFRC_MASK (A_MASK | FRC_MASK)
1070
1071 /* An A_MASK with the FRA and FRC fields fixed.  */
1072 #define AFRAFRC_MASK (A_MASK | FRA_MASK | FRC_MASK)
1073
1074 /* A B form instruction.  */
1075 #define B(op, aa, lk) (OP (op) | ((((unsigned long)(aa)) & 1) << 1) | ((lk) & 1))
1076 #define B_MASK B (0x3f, 1, 1)
1077
1078 /* A B form instruction setting the BO field.  */
1079 #define BBO(op, bo, aa, lk) (B ((op), (aa), (lk)) | ((((unsigned long)(bo)) & 0x1f) << 21))
1080 #define BBO_MASK BBO (0x3f, 0x1f, 1, 1)
1081
1082 /* A BBO_MASK with the y bit of the BO field removed.  This permits
1083    matching a conditional branch regardless of the setting of the y
1084    bit.  */
1085 #define Y_MASK (((unsigned long)1) << 21)
1086 #define BBOY_MASK (BBO_MASK &~ Y_MASK)
1087
1088 /* A B form instruction setting the BO field and the condition bits of
1089    the BI field.  */
1090 #define BBOCB(op, bo, cb, aa, lk) \
1091   (BBO ((op), (bo), (aa), (lk)) | ((((unsigned long)(cb)) & 0x3) << 16))
1092 #define BBOCB_MASK BBOCB (0x3f, 0x1f, 0x3, 1, 1)
1093
1094 /* A BBOCB_MASK with the y bit of the BO field removed.  */
1095 #define BBOYCB_MASK (BBOCB_MASK &~ Y_MASK)
1096
1097 /* A BBOYCB_MASK in which the BI field is fixed.  */
1098 #define BBOYBI_MASK (BBOYCB_MASK | BI_MASK)
1099
1100 /* The main opcode mask with the RA field clear.  */
1101 #define DRA_MASK (OP_MASK | RA_MASK)
1102
1103 /* A DS form instruction.  */
1104 #define DSO(op, xop) (OP (op) | ((xop) & 0x3))
1105 #define DS_MASK DSO (0x3f, 3)
1106
1107 /* An M form instruction.  */
1108 #define M(op, rc) (OP (op) | ((rc) & 1))
1109 #define M_MASK M (0x3f, 1)
1110
1111 /* An M form instruction with the ME field specified.  */
1112 #define MME(op, me, rc) (M ((op), (rc)) | ((((unsigned long)(me)) & 0x1f) << 1))
1113
1114 /* An M_MASK with the MB and ME fields fixed.  */
1115 #define MMBME_MASK (M_MASK | MB_MASK | ME_MASK)
1116
1117 /* An M_MASK with the SH and ME fields fixed.  */
1118 #define MSHME_MASK (M_MASK | SH_MASK | ME_MASK)
1119
1120 /* An MD form instruction.  */
1121 #define MD(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x7) << 2) | ((rc) & 1))
1122 #define MD_MASK MD (0x3f, 0x7, 1)
1123
1124 /* An MD_MASK with the MB field fixed.  */
1125 #define MDMB_MASK (MD_MASK | MB6_MASK)
1126
1127 /* An MD_MASK with the SH field fixed.  */
1128 #define MDSH_MASK (MD_MASK | SH6_MASK)
1129
1130 /* An MDS form instruction.  */
1131 #define MDS(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0xf) << 1) | ((rc) & 1))
1132 #define MDS_MASK MDS (0x3f, 0xf, 1)
1133
1134 /* An MDS_MASK with the MB field fixed.  */
1135 #define MDSMB_MASK (MDS_MASK | MB6_MASK)
1136
1137 /* An SC form instruction.  */
1138 #define SC(op, sa, lk) (OP (op) | ((((unsigned long)(sa)) & 1) << 1) | ((lk) & 1))
1139 #define SC_MASK (OP_MASK | (((unsigned long)0x3ff) << 16) | (((unsigned long)1) << 1) | 1)
1140
1141 /* An VX form instruction. */
1142 #define VX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7ff))
1143
1144 /* The mask for an VX form instruction. */
1145 #define VX_MASK VX(0x3f, 0x7ff)
1146
1147 /* An VA form instruction. */
1148 #define VXA(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x07f))
1149
1150 /* The mask for an VA form instruction. */
1151 #define VXA_MASK VXA(0x3f, 0x7f)
1152
1153 /* An VXR form instruction. */
1154 #define VXR(op, xop, rc) (OP (op) | (((rc) & 1) << 10) | (((unsigned long)(xop)) & 0x3ff))
1155
1156 /* The mask for a VXR form instruction. */
1157 #define VXR_MASK VXR(0x3f, 0x3ff, 1)
1158
1159 /* An X form instruction.  */
1160 #define X(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1))
1161
1162 /* An X form instruction with the RC bit specified.  */
1163 #define XRC(op, xop, rc) (X ((op), (xop)) | ((rc) & 1))
1164
1165 /* The mask for an X form instruction.  */
1166 #define X_MASK XRC (0x3f, 0x3ff, 1)
1167
1168 /* An X_MASK with the RA field fixed.  */
1169 #define XRA_MASK (X_MASK | RA_MASK)
1170
1171 /* An X_MASK with the RB field fixed.  */
1172 #define XRB_MASK (X_MASK | RB_MASK)
1173
1174 /* An X_MASK with the RT field fixed.  */
1175 #define XRT_MASK (X_MASK | RT_MASK)
1176
1177 /* An X_MASK with the RA and RB fields fixed.  */
1178 #define XRARB_MASK (X_MASK | RA_MASK | RB_MASK)
1179
1180 /* An X_MASK with the RT and RA fields fixed.  */
1181 #define XRTRA_MASK (X_MASK | RT_MASK | RA_MASK)
1182
1183 /* An X form comparison instruction.  */
1184 #define XCMPL(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 1) << 21))
1185
1186 /* The mask for an X form comparison instruction.  */
1187 #define XCMP_MASK (X_MASK | (((unsigned long)1) << 22))
1188
1189 /* The mask for an X form comparison instruction with the L field
1190    fixed.  */
1191 #define XCMPL_MASK (XCMP_MASK | (((unsigned long)1) << 21))
1192
1193 /* An X form trap instruction with the TO field specified.  */
1194 #define XTO(op, xop, to) (X ((op), (xop)) | ((((unsigned long)(to)) & 0x1f) << 21))
1195 #define XTO_MASK (X_MASK | TO_MASK)
1196
1197 /* An X form tlb instruction with the SH field specified.  */
1198 #define XTLB(op, xop, sh) (X ((op), (xop)) | ((((unsigned long)(sh)) & 0x1f) << 11))
1199 #define XTLB_MASK (X_MASK | SH_MASK)
1200
1201 /* An XFL form instruction.  */
1202 #define XFL(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1) | (((unsigned long)(rc)) & 1))
1203 #define XFL_MASK (XFL (0x3f, 0x3ff, 1) | (((unsigned long)1) << 25) | (((unsigned long)1) << 16))
1204
1205 /* An XL form instruction with the LK field set to 0.  */
1206 #define XL(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1))
1207
1208 /* An XL form instruction which uses the LK field.  */
1209 #define XLLK(op, xop, lk) (XL ((op), (xop)) | ((lk) & 1))
1210
1211 /* The mask for an XL form instruction.  */
1212 #define XL_MASK XLLK (0x3f, 0x3ff, 1)
1213
1214 /* An XL form instruction which explicitly sets the BO field.  */
1215 #define XLO(op, bo, xop, lk) \
1216   (XLLK ((op), (xop), (lk)) | ((((unsigned long)(bo)) & 0x1f) << 21))
1217 #define XLO_MASK (XL_MASK | BO_MASK)
1218
1219 /* An XL form instruction which explicitly sets the y bit of the BO
1220    field.  */
1221 #define XLYLK(op, xop, y, lk) (XLLK ((op), (xop), (lk)) | ((((unsigned long)(y)) & 1) << 21))
1222 #define XLYLK_MASK (XL_MASK | Y_MASK)
1223
1224 /* An XL form instruction which sets the BO field and the condition
1225    bits of the BI field.  */
1226 #define XLOCB(op, bo, cb, xop, lk) \
1227   (XLO ((op), (bo), (xop), (lk)) | ((((unsigned long)(cb)) & 3) << 16))
1228 #define XLOCB_MASK XLOCB (0x3f, 0x1f, 0x3, 0x3ff, 1)
1229
1230 /* An XL_MASK or XLYLK_MASK or XLOCB_MASK with the BB field fixed.  */
1231 #define XLBB_MASK (XL_MASK | BB_MASK)
1232 #define XLYBB_MASK (XLYLK_MASK | BB_MASK)
1233 #define XLBOCBBB_MASK (XLOCB_MASK | BB_MASK)
1234
1235 /* An XL_MASK with the BO and BB fields fixed.  */
1236 #define XLBOBB_MASK (XL_MASK | BO_MASK | BB_MASK)
1237
1238 /* An XL_MASK with the BO, BI and BB fields fixed.  */
1239 #define XLBOBIBB_MASK (XL_MASK | BO_MASK | BI_MASK | BB_MASK)
1240
1241 /* An XO form instruction.  */
1242 #define XO(op, xop, oe, rc) \
1243   (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 1) | ((((unsigned long)(oe)) & 1) << 10) | (((unsigned long)(rc)) & 1))
1244 #define XO_MASK XO (0x3f, 0x1ff, 1, 1)
1245
1246 /* An XO_MASK with the RB field fixed.  */
1247 #define XORB_MASK (XO_MASK | RB_MASK)
1248
1249 /* An XS form instruction.  */
1250 #define XS(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 2) | (((unsigned long)(rc)) & 1))
1251 #define XS_MASK XS (0x3f, 0x1ff, 1)
1252
1253 /* A mask for the FXM version of an XFX form instruction.  */
1254 #define XFXFXM_MASK (X_MASK | (((unsigned long)1) << 20) | (((unsigned long)1) << 11))
1255
1256 /* An XFX form instruction with the FXM field filled in.  */
1257 #define XFXM(op, xop, fxm) \
1258   (X ((op), (xop)) | ((((unsigned long)(fxm)) & 0xff) << 12))
1259
1260 /* An XFX form instruction with the SPR field filled in.  */
1261 #define XSPR(op, xop, spr) \
1262   (X ((op), (xop)) | ((((unsigned long)(spr)) & 0x1f) << 16) | ((((unsigned long)(spr)) & 0x3e0) << 6))
1263 #define XSPR_MASK (X_MASK | SPR_MASK)
1264
1265 /* An XFX form instruction with the SPR field filled in except for the
1266    SPRBAT field.  */
1267 #define XSPRBAT_MASK (XSPR_MASK &~ SPRBAT_MASK)
1268
1269 /* An XFX form instruction with the SPR field filled in except for the
1270    SPRG field.  */
1271 #define XSPRG_MASK (XSPR_MASK &~ SPRG_MASK)
1272
1273 /* An X form instruction with everything filled in except the E field.  */
1274 #define XE_MASK (0xffff7fff)
1275
1276 /* The BO encodings used in extended conditional branch mnemonics.  */
1277 #define BODNZF  (0x0)
1278 #define BODNZFP (0x1)
1279 #define BODZF   (0x2)
1280 #define BODZFP  (0x3)
1281 #define BOF     (0x4)
1282 #define BOFP    (0x5)
1283 #define BODNZT  (0x8)
1284 #define BODNZTP (0x9)
1285 #define BODZT   (0xa)
1286 #define BODZTP  (0xb)
1287 #define BOT     (0xc)
1288 #define BOTP    (0xd)
1289 #define BODNZ   (0x10)
1290 #define BODNZP  (0x11)
1291 #define BODZ    (0x12)
1292 #define BODZP   (0x13)
1293 #define BOU     (0x14)
1294
1295 /* The BI condition bit encodings used in extended conditional branch
1296    mnemonics.  */
1297 #define CBLT    (0)
1298 #define CBGT    (1)
1299 #define CBEQ    (2)
1300 #define CBSO    (3)
1301
1302 /* The TO encodings used in extended trap mnemonics.  */
1303 #define TOLGT   (0x1)
1304 #define TOLLT   (0x2)
1305 #define TOEQ    (0x4)
1306 #define TOLGE   (0x5)
1307 #define TOLNL   (0x5)
1308 #define TOLLE   (0x6)
1309 #define TOLNG   (0x6)
1310 #define TOGT    (0x8)
1311 #define TOGE    (0xc)
1312 #define TONL    (0xc)
1313 #define TOLT    (0x10)
1314 #define TOLE    (0x14)
1315 #define TONG    (0x14)
1316 #define TONE    (0x18)
1317 #define TOU     (0x1f)
1318 \f
1319 /* Smaller names for the flags so each entry in the opcodes table will
1320    fit on a single line.  */
1321 #undef  PPC
1322 #define PPC     PPC_OPCODE_PPC | PPC_OPCODE_ANY
1323 #define PPCCOM  PPC_OPCODE_PPC | PPC_OPCODE_COMMON | PPC_OPCODE_ANY
1324 #define PPC32   PPC_OPCODE_PPC | PPC_OPCODE_32 | PPC_OPCODE_ANY
1325 #define PPC64   PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_ANY
1326 #define PPCONLY PPC_OPCODE_PPC
1327 #define PPC403  PPC
1328 #define PPC405  PPC403
1329 #define PPC750  PPC
1330 #define PPC860  PPC
1331 #define PPCVEC  PPC_OPCODE_ALTIVEC | PPC_OPCODE_ANY
1332 #define POWER   PPC_OPCODE_POWER | PPC_OPCODE_ANY
1333 #define POWER2  PPC_OPCODE_POWER | PPC_OPCODE_POWER2 | PPC_OPCODE_ANY
1334 #define PPCPWR2 PPC_OPCODE_PPC | PPC_OPCODE_POWER | PPC_OPCODE_POWER2 | PPC_OPCODE_ANY
1335 #define POWER32 PPC_OPCODE_POWER | PPC_OPCODE_ANY | PPC_OPCODE_32
1336 #define COM     PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON | PPC_OPCODE_ANY
1337 #define COM32   PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON | PPC_OPCODE_ANY | PPC_OPCODE_32
1338 #define M601    PPC_OPCODE_POWER | PPC_OPCODE_601 | PPC_OPCODE_ANY
1339 #define PWRCOM  PPC_OPCODE_POWER | PPC_OPCODE_601 | PPC_OPCODE_COMMON | PPC_OPCODE_ANY
1340 #define MFDEC1  PPC_OPCODE_POWER
1341 #define MFDEC2  PPC_OPCODE_PPC | PPC_OPCODE_601
1342 \f
1343 /* The opcode table.
1344
1345    The format of the opcode table is:
1346
1347    NAME      OPCODE     MASK            FLAGS           { OPERANDS }
1348
1349    NAME is the name of the instruction.
1350    OPCODE is the instruction opcode.
1351    MASK is the opcode mask; this is used to tell the disassembler
1352      which bits in the actual opcode must match OPCODE.
1353    FLAGS are flags indicated what processors support the instruction.
1354    OPERANDS is the list of operands.
1355
1356    The disassembler reads the table in order and prints the first
1357    instruction which matches, so this table is sorted to put more
1358    specific instructions before more general instructions.  It is also
1359    sorted by major opcode.  */
1360
1361 const struct powerpc_opcode powerpc_opcodes[] = {
1362 { "tdlgti",  OPTO(2,TOLGT), OPTO_MASK,  PPC64,          { RA, SI } },
1363 { "tdllti",  OPTO(2,TOLLT), OPTO_MASK,  PPC64,          { RA, SI } },
1364 { "tdeqi",   OPTO(2,TOEQ), OPTO_MASK,   PPC64,          { RA, SI } },
1365 { "tdlgei",  OPTO(2,TOLGE), OPTO_MASK,  PPC64,          { RA, SI } },
1366 { "tdlnli",  OPTO(2,TOLNL), OPTO_MASK,  PPC64,          { RA, SI } },
1367 { "tdllei",  OPTO(2,TOLLE), OPTO_MASK,  PPC64,          { RA, SI } },
1368 { "tdlngi",  OPTO(2,TOLNG), OPTO_MASK,  PPC64,          { RA, SI } },
1369 { "tdgti",   OPTO(2,TOGT), OPTO_MASK,   PPC64,          { RA, SI } },
1370 { "tdgei",   OPTO(2,TOGE), OPTO_MASK,   PPC64,          { RA, SI } },
1371 { "tdnli",   OPTO(2,TONL), OPTO_MASK,   PPC64,          { RA, SI } },
1372 { "tdlti",   OPTO(2,TOLT), OPTO_MASK,   PPC64,          { RA, SI } },
1373 { "tdlei",   OPTO(2,TOLE), OPTO_MASK,   PPC64,          { RA, SI } },
1374 { "tdngi",   OPTO(2,TONG), OPTO_MASK,   PPC64,          { RA, SI } },
1375 { "tdnei",   OPTO(2,TONE), OPTO_MASK,   PPC64,          { RA, SI } },
1376 { "tdi",     OP(2),     OP_MASK,        PPC64,          { TO, RA, SI } },
1377
1378 { "twlgti",  OPTO(3,TOLGT), OPTO_MASK,  PPCCOM,         { RA, SI } },
1379 { "tlgti",   OPTO(3,TOLGT), OPTO_MASK,  PWRCOM,         { RA, SI } },
1380 { "twllti",  OPTO(3,TOLLT), OPTO_MASK,  PPCCOM,         { RA, SI } },
1381 { "tllti",   OPTO(3,TOLLT), OPTO_MASK,  PWRCOM,         { RA, SI } },
1382 { "tweqi",   OPTO(3,TOEQ), OPTO_MASK,   PPCCOM,         { RA, SI } },
1383 { "teqi",    OPTO(3,TOEQ), OPTO_MASK,   PWRCOM,         { RA, SI } },
1384 { "twlgei",  OPTO(3,TOLGE), OPTO_MASK,  PPCCOM,         { RA, SI } },
1385 { "tlgei",   OPTO(3,TOLGE), OPTO_MASK,  PWRCOM,         { RA, SI } },
1386 { "twlnli",  OPTO(3,TOLNL), OPTO_MASK,  PPCCOM,         { RA, SI } },
1387 { "tlnli",   OPTO(3,TOLNL), OPTO_MASK,  PWRCOM,         { RA, SI } },
1388 { "twllei",  OPTO(3,TOLLE), OPTO_MASK,  PPCCOM,         { RA, SI } },
1389 { "tllei",   OPTO(3,TOLLE), OPTO_MASK,  PWRCOM,         { RA, SI } },
1390 { "twlngi",  OPTO(3,TOLNG), OPTO_MASK,  PPCCOM,         { RA, SI } },
1391 { "tlngi",   OPTO(3,TOLNG), OPTO_MASK,  PWRCOM,         { RA, SI } },
1392 { "twgti",   OPTO(3,TOGT), OPTO_MASK,   PPCCOM,         { RA, SI } },
1393 { "tgti",    OPTO(3,TOGT), OPTO_MASK,   PWRCOM,         { RA, SI } },
1394 { "twgei",   OPTO(3,TOGE), OPTO_MASK,   PPCCOM,         { RA, SI } },
1395 { "tgei",    OPTO(3,TOGE), OPTO_MASK,   PWRCOM,         { RA, SI } },
1396 { "twnli",   OPTO(3,TONL), OPTO_MASK,   PPCCOM,         { RA, SI } },
1397 { "tnli",    OPTO(3,TONL), OPTO_MASK,   PWRCOM,         { RA, SI } },
1398 { "twlti",   OPTO(3,TOLT), OPTO_MASK,   PPCCOM,         { RA, SI } },
1399 { "tlti",    OPTO(3,TOLT), OPTO_MASK,   PWRCOM,         { RA, SI } },
1400 { "twlei",   OPTO(3,TOLE), OPTO_MASK,   PPCCOM,         { RA, SI } },
1401 { "tlei",    OPTO(3,TOLE), OPTO_MASK,   PWRCOM,         { RA, SI } },
1402 { "twngi",   OPTO(3,TONG), OPTO_MASK,   PPCCOM,         { RA, SI } },
1403 { "tngi",    OPTO(3,TONG), OPTO_MASK,   PWRCOM,         { RA, SI } },
1404 { "twnei",   OPTO(3,TONE), OPTO_MASK,   PPCCOM,         { RA, SI } },
1405 { "tnei",    OPTO(3,TONE), OPTO_MASK,   PWRCOM,         { RA, SI } },
1406 { "twi",     OP(3),     OP_MASK,        PPCCOM,         { TO, RA, SI } },
1407 { "ti",      OP(3),     OP_MASK,        PWRCOM,         { TO, RA, SI } },
1408
1409 { "macchw",     XO(4,172,0,0), XO_MASK, PPC405,         { RT, RA, RB } },
1410 { "macchw.",    XO(4,172,0,1), XO_MASK, PPC405,         { RT, RA, RB } },
1411 { "macchwo",    XO(4,172,1,0), XO_MASK, PPC405,         { RT, RA, RB } },
1412 { "macchwo.",   XO(4,172,1,1), XO_MASK, PPC405,         { RT, RA, RB } },
1413 { "macchws",    XO(4,236,0,0), XO_MASK, PPC405,         { RT, RA, RB } },
1414 { "macchws.",   XO(4,236,0,1), XO_MASK, PPC405,         { RT, RA, RB } },
1415 { "macchwso",   XO(4,236,1,0), XO_MASK, PPC405,         { RT, RA, RB } },
1416 { "macchwso.",  XO(4,236,1,1), XO_MASK, PPC405,         { RT, RA, RB } },
1417 { "macchwsu",   XO(4,204,0,0), XO_MASK, PPC405,         { RT, RA, RB } },
1418 { "macchwsu.",  XO(4,204,0,1), XO_MASK, PPC405,         { RT, RA, RB } },
1419 { "macchwsuo",  XO(4,204,1,0), XO_MASK, PPC405,         { RT, RA, RB } },
1420 { "macchwsuo.", XO(4,204,1,1), XO_MASK, PPC405,         { RT, RA, RB } },
1421 { "macchwu",    XO(4,140,0,0), XO_MASK, PPC405,         { RT, RA, RB } },
1422 { "macchwu.",   XO(4,140,0,1), XO_MASK, PPC405,         { RT, RA, RB } },
1423 { "macchwuo",   XO(4,140,1,0), XO_MASK, PPC405,         { RT, RA, RB } },
1424 { "macchwuo.",  XO(4,140,1,1), XO_MASK, PPC405,         { RT, RA, RB } },
1425 { "machhw",     XO(4,44,0,0),  XO_MASK, PPC405,         { RT, RA, RB } },
1426 { "machhw.",    XO(4,44,0,1),  XO_MASK, PPC405,         { RT, RA, RB } },
1427 { "machhwo",    XO(4,44,1,0),  XO_MASK, PPC405,         { RT, RA, RB } },
1428 { "machhwo.",   XO(4,44,1,1),  XO_MASK, PPC405,         { RT, RA, RB } },
1429 { "machhws",    XO(4,108,0,0), XO_MASK, PPC405,         { RT, RA, RB } },
1430 { "machhws.",   XO(4,108,0,1), XO_MASK, PPC405,         { RT, RA, RB } },
1431 { "machhwso",   XO(4,108,1,0), XO_MASK, PPC405,         { RT, RA, RB } },
1432 { "machhwso.",  XO(4,108,1,1), XO_MASK, PPC405,         { RT, RA, RB } },
1433 { "machhwsu",   XO(4,76,0,0),  XO_MASK, PPC405,         { RT, RA, RB } },
1434 { "machhwsu.",  XO(4,76,0,1),  XO_MASK, PPC405,         { RT, RA, RB } },
1435 { "machhwsuo",  XO(4,76,1,0),  XO_MASK, PPC405,         { RT, RA, RB } },
1436 { "machhwsuo.", XO(4,76,1,1),  XO_MASK, PPC405,         { RT, RA, RB } },
1437 { "machhwu",    XO(4,12,0,0),  XO_MASK, PPC405,         { RT, RA, RB } },
1438 { "machhwu.",   XO(4,12,0,1),  XO_MASK, PPC405,         { RT, RA, RB } },
1439 { "machhwuo",   XO(4,12,1,0),  XO_MASK, PPC405,         { RT, RA, RB } },
1440 { "machhwuo.",  XO(4,12,1,1),  XO_MASK, PPC405,         { RT, RA, RB } },
1441 { "maclhw",     XO(4,428,0,0), XO_MASK, PPC405,         { RT, RA, RB } },
1442 { "maclhw.",    XO(4,428,0,1), XO_MASK, PPC405,         { RT, RA, RB } },
1443 { "maclhwo",    XO(4,428,1,0), XO_MASK, PPC405,         { RT, RA, RB } },
1444 { "maclhwo.",   XO(4,428,1,1), XO_MASK, PPC405,         { RT, RA, RB } },
1445 { "maclhws",    XO(4,492,0,0), XO_MASK, PPC405,         { RT, RA, RB } },
1446 { "maclhws.",   XO(4,492,0,1), XO_MASK, PPC405,         { RT, RA, RB } },
1447 { "maclhwso",   XO(4,492,1,0), XO_MASK, PPC405,         { RT, RA, RB } },
1448 { "maclhwso.",  XO(4,492,1,1), XO_MASK, PPC405,         { RT, RA, RB } },
1449 { "maclhwsu",   XO(4,460,0,0), XO_MASK, PPC405,         { RT, RA, RB } },
1450 { "maclhwsu.",  XO(4,460,0,1), XO_MASK, PPC405,         { RT, RA, RB } },
1451 { "maclhwsuo",  XO(4,460,1,0), XO_MASK, PPC405,         { RT, RA, RB } },
1452 { "maclhwsuo.", XO(4,460,1,1), XO_MASK, PPC405,         { RT, RA, RB } },
1453 { "maclhwu",    XO(4,396,0,0), XO_MASK, PPC405,         { RT, RA, RB } },
1454 { "maclhwu.",   XO(4,396,0,1), XO_MASK, PPC405,         { RT, RA, RB } },
1455 { "maclhwuo",   XO(4,396,1,0), XO_MASK, PPC405,         { RT, RA, RB } },
1456 { "maclhwuo.",  XO(4,396,1,1), XO_MASK, PPC405,         { RT, RA, RB } },
1457 { "mulchw",     XRC(4,168,0),  X_MASK,  PPC405,         { RT, RA, RB } },
1458 { "mulchw.",    XRC(4,168,1),  X_MASK,  PPC405,         { RT, RA, RB } },
1459 { "mulchwu",    XRC(4,136,0),  X_MASK,  PPC405,         { RT, RA, RB } },
1460 { "mulchwu.",   XRC(4,136,1),  X_MASK,  PPC405,         { RT, RA, RB } },
1461 { "mulhhw",     XRC(4,40,0),   X_MASK,  PPC405,         { RT, RA, RB } },
1462 { "mulhhw.",    XRC(4,40,1),   X_MASK,  PPC405,         { RT, RA, RB } },
1463 { "mulhhwu",    XRC(4,8,0),    X_MASK,  PPC405,         { RT, RA, RB } },
1464 { "mulhhwu.",   XRC(4,8,1),    X_MASK,  PPC405,         { RT, RA, RB } },
1465 { "mullhw",     XRC(4,424,0),  X_MASK,  PPC405,         { RT, RA, RB } },
1466 { "mullhw.",    XRC(4,424,1),  X_MASK,  PPC405,         { RT, RA, RB } },
1467 { "mullhwu",    XRC(4,392,0),  X_MASK,  PPC405,         { RT, RA, RB } },
1468 { "mullhwu.",   XRC(4,392,1),  X_MASK,  PPC405,         { RT, RA, RB } },
1469 { "nmacchw",    XO(4,174,0,0), XO_MASK, PPC405,         { RT, RA, RB } },
1470 { "nmacchw.",   XO(4,174,0,1), XO_MASK, PPC405,         { RT, RA, RB } },
1471 { "nmacchwo",   XO(4,174,1,0), XO_MASK, PPC405,         { RT, RA, RB } },
1472 { "nmacchwo.",  XO(4,174,1,1), XO_MASK, PPC405,         { RT, RA, RB } },
1473 { "nmacchws",   XO(4,238,0,0), XO_MASK, PPC405,         { RT, RA, RB } },
1474 { "nmacchws.",  XO(4,238,0,1), XO_MASK, PPC405,         { RT, RA, RB } },
1475 { "nmacchwso",  XO(4,238,1,0), XO_MASK, PPC405,         { RT, RA, RB } },
1476 { "nmacchwso.", XO(4,238,1,1), XO_MASK, PPC405,         { RT, RA, RB } },
1477 { "nmachhw",    XO(4,46,0,0),  XO_MASK, PPC405,         { RT, RA, RB } },
1478 { "nmachhw.",   XO(4,46,0,1),  XO_MASK, PPC405,         { RT, RA, RB } },
1479 { "nmachhwo",   XO(4,46,1,0),  XO_MASK, PPC405,         { RT, RA, RB } },
1480 { "nmachhwo.",  XO(4,46,1,1),  XO_MASK, PPC405,         { RT, RA, RB } },
1481 { "nmachhws",   XO(4,110,0,0), XO_MASK, PPC405,         { RT, RA, RB } },
1482 { "nmachhws.",  XO(4,110,0,1), XO_MASK, PPC405,         { RT, RA, RB } },
1483 { "nmachhwso",  XO(4,110,1,0), XO_MASK, PPC405,         { RT, RA, RB } },
1484 { "nmachhwso.", XO(4,110,1,1), XO_MASK, PPC405,         { RT, RA, RB } },
1485 { "nmaclhw",    XO(4,430,0,0), XO_MASK, PPC405,         { RT, RA, RB } },
1486 { "nmaclhw.",   XO(4,430,0,1), XO_MASK, PPC405,         { RT, RA, RB } },
1487 { "nmaclhwo",   XO(4,430,1,0), XO_MASK, PPC405,         { RT, RA, RB } },
1488 { "nmaclhwo.",  XO(4,430,1,1), XO_MASK, PPC405,         { RT, RA, RB } },
1489 { "nmaclhws",   XO(4,494,0,0), XO_MASK, PPC405,         { RT, RA, RB } },
1490 { "nmaclhws.",  XO(4,494,0,1), XO_MASK, PPC405,         { RT, RA, RB } },
1491 { "nmaclhwso",  XO(4,494,1,0), XO_MASK, PPC405,         { RT, RA, RB } },
1492 { "nmaclhwso.", XO(4,494,1,1), XO_MASK, PPC405,         { RT, RA, RB } },
1493 { "mfvscr",  VX(4, 1540), VX_MASK,      PPCVEC,         { VD } },
1494 { "mtvscr",  VX(4, 1604), VX_MASK,      PPCVEC,         { VD } },
1495 { "vaddcuw", VX(4,  384), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1496 { "vaddfp",  VX(4,   10), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1497 { "vaddsbs", VX(4,  768), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1498 { "vaddshs", VX(4,  832), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1499 { "vaddsws", VX(4,  896), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1500 { "vaddubm", VX(4,    0), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1501 { "vaddubs", VX(4,  512), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1502 { "vadduhm", VX(4,   64), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1503 { "vadduhs", VX(4,  576), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1504 { "vadduwm", VX(4,  128), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1505 { "vadduws", VX(4,  640), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1506 { "vand",    VX(4, 1028), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1507 { "vandc",   VX(4, 1092), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1508 { "vavgsb",  VX(4, 1282), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1509 { "vavgsh",  VX(4, 1346), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1510 { "vavgsw",  VX(4, 1410), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1511 { "vavgub",  VX(4, 1026), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1512 { "vavguh",  VX(4, 1090), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1513 { "vavguw",  VX(4, 1154), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1514 { "vcfsx",   VX(4,  842), VX_MASK,      PPCVEC,         { VD, VB, UIMM } },
1515 { "vcfux",   VX(4,  778), VX_MASK,      PPCVEC,         { VD, VB, UIMM } },
1516 { "vcmpbfp",   VXR(4, 966, 0), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1517 { "vcmpbfp.",  VXR(4, 966, 1), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1518 { "vcmpeqfp",  VXR(4, 198, 0), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1519 { "vcmpeqfp.", VXR(4, 198, 1), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1520 { "vcmpequb",  VXR(4,   6, 0), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1521 { "vcmpequb.", VXR(4,   6, 1), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1522 { "vcmpequh",  VXR(4,  70, 0), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1523 { "vcmpequh.", VXR(4,  70, 1), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1524 { "vcmpequw",  VXR(4, 134, 0), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1525 { "vcmpequw.", VXR(4, 134, 1), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1526 { "vcmpgefp",  VXR(4, 454, 0), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1527 { "vcmpgefp.", VXR(4, 454, 1), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1528 { "vcmpgtfp",  VXR(4, 710, 0), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1529 { "vcmpgtfp.", VXR(4, 710, 1), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1530 { "vcmpgtsb",  VXR(4, 774, 0), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1531 { "vcmpgtsb.", VXR(4, 774, 1), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1532 { "vcmpgtsh",  VXR(4, 838, 0), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1533 { "vcmpgtsh.", VXR(4, 838, 1), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1534 { "vcmpgtsw",  VXR(4, 902, 0), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1535 { "vcmpgtsw.", VXR(4, 902, 1), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1536 { "vcmpgtub",  VXR(4, 518, 0), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1537 { "vcmpgtub.", VXR(4, 518, 1), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1538 { "vcmpgtuh",  VXR(4, 582, 0), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1539 { "vcmpgtuh.", VXR(4, 582, 1), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1540 { "vcmpgtuw",  VXR(4, 646, 0), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1541 { "vcmpgtuw.", VXR(4, 646, 1), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1542 { "vctsxs",    VX(4,  970), VX_MASK,    PPCVEC,         { VD, VB, UIMM } },
1543 { "vctuxs",    VX(4,  906), VX_MASK,    PPCVEC,         { VD, VB, UIMM } },
1544 { "vexptefp",  VX(4,  394), VX_MASK,    PPCVEC,         { VD, VB } },
1545 { "vlogefp",   VX(4,  458), VX_MASK,    PPCVEC,         { VD, VB } },
1546 { "vmaddfp",   VXA(4,  46), VXA_MASK,   PPCVEC,         { VD, VA, VB, VC } },
1547 { "vmaxfp",    VX(4, 1034), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1548 { "vmaxsb",    VX(4,  258), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1549 { "vmaxsh",    VX(4,  322), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1550 { "vmaxsw",    VX(4,  386), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1551 { "vmaxub",    VX(4,    2), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1552 { "vmaxuh",    VX(4,   66), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1553 { "vmaxuw",    VX(4,  130), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1554 { "vmhaddshs", VXA(4,  32), VXA_MASK,   PPCVEC,         { VD, VA, VB, VC } },
1555 { "vmhraddshs", VXA(4, 33), VXA_MASK,   PPCVEC,         { VD, VA, VB, VC } },
1556 { "vminfp",    VX(4, 1098), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1557 { "vminsb",    VX(4,  770), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1558 { "vminsh",    VX(4,  834), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1559 { "vminsw",    VX(4,  898), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1560 { "vminub",    VX(4,  514), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1561 { "vminuh",    VX(4,  578), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1562 { "vminuw",    VX(4,  642), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1563 { "vmladduhm", VXA(4,  34), VXA_MASK,   PPCVEC,         { VD, VA, VB, VC } },
1564 { "vmrghb",    VX(4,   12), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1565 { "vmrghh",    VX(4,   76), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1566 { "vmrghw",    VX(4,  140), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1567 { "vmrglb",    VX(4,  268), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1568 { "vmrglh",    VX(4,  332), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1569 { "vmrglw",    VX(4,  396), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1570 { "vmsummbm",  VXA(4,  37), VXA_MASK,   PPCVEC,         { VD, VA, VB, VC } },
1571 { "vmsumshm",  VXA(4,  40), VXA_MASK,   PPCVEC,         { VD, VA, VB, VC } },
1572 { "vmsumshs",  VXA(4,  41), VXA_MASK,   PPCVEC,         { VD, VA, VB, VC } },
1573 { "vmsumubm",  VXA(4,  36), VXA_MASK,   PPCVEC,         { VD, VA, VB, VC } },
1574 { "vmsumuhm",  VXA(4,  38), VXA_MASK,   PPCVEC,         { VD, VA, VB, VC } },
1575 { "vmsumuhs",  VXA(4,  39), VXA_MASK,   PPCVEC,         { VD, VA, VB, VC } },
1576 { "vmulesb",   VX(4,  776), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1577 { "vmulesh",   VX(4,  840), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1578 { "vmuleub",   VX(4,  520), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1579 { "vmuleuh",   VX(4,  584), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1580 { "vmulosb",   VX(4,  264), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1581 { "vmulosh",   VX(4,  328), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1582 { "vmuloub",   VX(4,    8), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1583 { "vmulouh",   VX(4,   72), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1584 { "vnmsubfp",  VXA(4,  47), VXA_MASK,   PPCVEC,         { VD, VA, VC, VB } },
1585 { "vnor",      VX(4, 1284), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1586 { "vor",       VX(4, 1156), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1587 { "vperm",     VXA(4,  43), VXA_MASK,   PPCVEC,         { VD, VA, VB, VC } },
1588 { "vpkpx",     VX(4,  782), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1589 { "vpkshss",   VX(4,  398), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1590 { "vpkshus",   VX(4,  270), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1591 { "vpkswss",   VX(4,  462), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1592 { "vpkswus",   VX(4,  334), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1593 { "vpkuhum",   VX(4,   14), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1594 { "vpkuhus",   VX(4,  142), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1595 { "vpkuwum",   VX(4,   78), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1596 { "vpkuwus",   VX(4,  206), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1597 { "vrefp",     VX(4,  266), VX_MASK,    PPCVEC,         { VD, VB } },
1598 { "vrfim",     VX(4,  714), VX_MASK,    PPCVEC,         { VD, VB } },
1599 { "vrfin",     VX(4,  522), VX_MASK,    PPCVEC,         { VD, VB } },
1600 { "vrfip",     VX(4,  650), VX_MASK,    PPCVEC,         { VD, VB } },
1601 { "vrfiz",     VX(4,  586), VX_MASK,    PPCVEC,         { VD, VB } },
1602 { "vrlb",      VX(4,    4), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1603 { "vrlh",      VX(4,   68), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1604 { "vrlw",      VX(4,  132), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1605 { "vrsqrtefp", VX(4,  330), VX_MASK,    PPCVEC,         { VD, VB } },
1606 { "vsel",      VXA(4,  42), VXA_MASK,   PPCVEC,         { VD, VA, VB, VC } },
1607 { "vsl",       VX(4,  452), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1608 { "vslb",      VX(4,  260), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1609 { "vsldoi",    VXA(4,  44), VXA_MASK,   PPCVEC,         { VD, VA, VB, SHB } },
1610 { "vslh",      VX(4,  324), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1611 { "vslo",      VX(4, 1036), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1612 { "vslw",      VX(4,  388), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1613 { "vspltb",    VX(4,  524), VX_MASK,    PPCVEC,         { VD, VB, UIMM } },
1614 { "vsplth",    VX(4,  588), VX_MASK,    PPCVEC,         { VD, VB, UIMM } },
1615 { "vspltisb",  VX(4,  780), VX_MASK,    PPCVEC,         { VD, SIMM } },
1616 { "vspltish",  VX(4,  844), VX_MASK,    PPCVEC,         { VD, SIMM } },
1617 { "vspltisw",  VX(4,  908), VX_MASK,    PPCVEC,         { VD, SIMM } },
1618 { "vspltw",    VX(4,  652), VX_MASK,    PPCVEC,         { VD, VB, UIMM } },
1619 { "vsr",       VX(4,  708), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1620 { "vsrab",     VX(4,  772), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1621 { "vsrah",     VX(4,  836), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1622 { "vsraw",     VX(4,  900), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1623 { "vsrb",      VX(4,  516), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1624 { "vsrh",      VX(4,  580), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1625 { "vsro",      VX(4, 1100), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1626 { "vsrw",      VX(4,  644), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1627 { "vsubcuw",   VX(4, 1408), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1628 { "vsubfp",    VX(4,   74), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1629 { "vsubsbs",   VX(4, 1792), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1630 { "vsubshs",   VX(4, 1856), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1631 { "vsubsws",   VX(4, 1920), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1632 { "vsububm",   VX(4, 1024), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1633 { "vsububs",   VX(4, 1536), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1634 { "vsubuhm",   VX(4, 1088), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1635 { "vsubuhs",   VX(4, 1600), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1636 { "vsubuwm",   VX(4, 1152), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1637 { "vsubuws",   VX(4, 1664), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1638 { "vsumsws",   VX(4, 1928), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1639 { "vsum2sws",  VX(4, 1672), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1640 { "vsum4sbs",  VX(4, 1800), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1641 { "vsum4shs",  VX(4, 1608), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1642 { "vsum4ubs",  VX(4, 1544), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1643 { "vupkhpx",   VX(4,  846), VX_MASK,    PPCVEC,         { VD, VB } },
1644 { "vupkhsb",   VX(4,  526), VX_MASK,    PPCVEC,         { VD, VB } },
1645 { "vupkhsh",   VX(4,  590), VX_MASK,    PPCVEC,         { VD, VB } },
1646 { "vupklpx",   VX(4,  974), VX_MASK,    PPCVEC,         { VD, VB } },
1647 { "vupklsb",   VX(4,  654), VX_MASK,    PPCVEC,         { VD, VB } },
1648 { "vupklsh",   VX(4,  718), VX_MASK,    PPCVEC,         { VD, VB } },
1649 { "vxor",      VX(4, 1220), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1650
1651 { "mulli",   OP(7),     OP_MASK,        PPCCOM,         { RT, RA, SI } },
1652 { "muli",    OP(7),     OP_MASK,        PWRCOM,         { RT, RA, SI } },
1653
1654 { "subfic",  OP(8),     OP_MASK,        PPCCOM,         { RT, RA, SI } },
1655 { "sfi",     OP(8),     OP_MASK,        PWRCOM,         { RT, RA, SI } },
1656
1657 { "dozi",    OP(9),     OP_MASK,        M601,           { RT, RA, SI } },
1658
1659 { "cmplwi",  OPL(10,0), OPL_MASK,       PPCCOM,         { OBF, RA, UI } },
1660 { "cmpldi",  OPL(10,1), OPL_MASK,       PPC64,          { OBF, RA, UI } },
1661 { "cmpli",   OP(10),    OP_MASK,        PPCONLY,        { BF, L, RA, UI } },
1662 { "cmpli",   OP(10),    OP_MASK,        PWRCOM,         { BF, RA, UI } },
1663
1664 { "cmpwi",   OPL(11,0), OPL_MASK,       PPCCOM,         { OBF, RA, SI } },
1665 { "cmpdi",   OPL(11,1), OPL_MASK,       PPC64,          { OBF, RA, SI } },
1666 { "cmpi",    OP(11),    OP_MASK,        PPCONLY,        { BF, L, RA, SI } },
1667 { "cmpi",    OP(11),    OP_MASK,        PWRCOM,         { BF, RA, SI } },
1668
1669 { "addic",   OP(12),    OP_MASK,        PPCCOM,         { RT, RA, SI } },
1670 { "ai",      OP(12),    OP_MASK,        PWRCOM,         { RT, RA, SI } },
1671 { "subic",   OP(12),    OP_MASK,        PPCCOM,         { RT, RA, NSI } },
1672
1673 { "addic.",  OP(13),    OP_MASK,        PPCCOM,         { RT, RA, SI } },
1674 { "ai.",     OP(13),    OP_MASK,        PWRCOM,         { RT, RA, SI } },
1675 { "subic.",  OP(13),    OP_MASK,        PPCCOM,         { RT, RA, NSI } },
1676
1677 { "li",      OP(14),    DRA_MASK,       PPCCOM,         { RT, SI } },
1678 { "lil",     OP(14),    DRA_MASK,       PWRCOM,         { RT, SI } },
1679 { "addi",    OP(14),    OP_MASK,        PPCCOM,         { RT, RA, SI } },
1680 { "cal",     OP(14),    OP_MASK,        PWRCOM,         { RT, D, RA } },
1681 { "subi",    OP(14),    OP_MASK,        PPCCOM,         { RT, RA, NSI } },
1682 { "la",      OP(14),    OP_MASK,        PPCCOM,         { RT, D, RA } },
1683
1684 { "lis",     OP(15),    DRA_MASK,       PPCCOM,         { RT, SISIGNOPT } },
1685 { "liu",     OP(15),    DRA_MASK,       PWRCOM,         { RT, SISIGNOPT } },
1686 { "addis",   OP(15),    OP_MASK,        PPCCOM,         { RT,RA,SISIGNOPT } },
1687 { "cau",     OP(15),    OP_MASK,        PWRCOM,         { RT,RA,SISIGNOPT } },
1688 { "subis",   OP(15),    OP_MASK,        PPCCOM,         { RT, RA, NSI } },
1689
1690 { "bdnz-",   BBO(16,BODNZ,0,0), BBOYBI_MASK, PPCCOM,    { BDM } },
1691 { "bdnz+",   BBO(16,BODNZ,0,0), BBOYBI_MASK, PPCCOM,    { BDP } },
1692 { "bdnz",    BBO(16,BODNZ,0,0), BBOYBI_MASK, PPCCOM,    { BD } },
1693 { "bdn",     BBO(16,BODNZ,0,0), BBOYBI_MASK, PWRCOM,    { BD } },
1694 { "bdnzl-",  BBO(16,BODNZ,0,1), BBOYBI_MASK, PPCCOM,    { BDM } },
1695 { "bdnzl+",  BBO(16,BODNZ,0,1), BBOYBI_MASK, PPCCOM,    { BDP } },
1696 { "bdnzl",   BBO(16,BODNZ,0,1), BBOYBI_MASK, PPCCOM,    { BD } },
1697 { "bdnl",    BBO(16,BODNZ,0,1), BBOYBI_MASK, PWRCOM,    { BD } },
1698 { "bdnza-",  BBO(16,BODNZ,1,0), BBOYBI_MASK, PPCCOM,    { BDMA } },
1699 { "bdnza+",  BBO(16,BODNZ,1,0), BBOYBI_MASK, PPCCOM,    { BDPA } },
1700 { "bdnza",   BBO(16,BODNZ,1,0), BBOYBI_MASK, PPCCOM,    { BDA } },
1701 { "bdna",    BBO(16,BODNZ,1,0), BBOYBI_MASK, PWRCOM,    { BDA } },
1702 { "bdnzla-", BBO(16,BODNZ,1,1), BBOYBI_MASK, PPCCOM,    { BDMA } },
1703 { "bdnzla+", BBO(16,BODNZ,1,1), BBOYBI_MASK, PPCCOM,    { BDPA } },
1704 { "bdnzla",  BBO(16,BODNZ,1,1), BBOYBI_MASK, PPCCOM,    { BDA } },
1705 { "bdnla",   BBO(16,BODNZ,1,1), BBOYBI_MASK, PWRCOM,    { BDA } },
1706 { "bdz-",    BBO(16,BODZ,0,0),  BBOYBI_MASK, PPCCOM,    { BDM } },
1707 { "bdz+",    BBO(16,BODZ,0,0),  BBOYBI_MASK, PPCCOM,    { BDP } },
1708 { "bdz",     BBO(16,BODZ,0,0),  BBOYBI_MASK, COM,       { BD } },
1709 { "bdzl-",   BBO(16,BODZ,0,1),  BBOYBI_MASK, PPCCOM,    { BDM } },
1710 { "bdzl+",   BBO(16,BODZ,0,1),  BBOYBI_MASK, PPCCOM,    { BDP } },
1711 { "bdzl",    BBO(16,BODZ,0,1),  BBOYBI_MASK, COM,       { BD } },
1712 { "bdza-",   BBO(16,BODZ,1,0),  BBOYBI_MASK, PPCCOM,    { BDMA } },
1713 { "bdza+",   BBO(16,BODZ,1,0),  BBOYBI_MASK, PPCCOM,    { BDPA } },
1714 { "bdza",    BBO(16,BODZ,1,0),  BBOYBI_MASK, COM,       { BDA } },
1715 { "bdzla-",  BBO(16,BODZ,1,1),  BBOYBI_MASK, PPCCOM,    { BDMA } },
1716 { "bdzla+",  BBO(16,BODZ,1,1),  BBOYBI_MASK, PPCCOM,    { BDPA } },
1717 { "bdzla",   BBO(16,BODZ,1,1),  BBOYBI_MASK, COM,       { BDA } },
1718 { "blt-",    BBOCB(16,BOT,CBLT,0,0), BBOYCB_MASK, PPCCOM,       { CR, BDM } },
1719 { "blt+",    BBOCB(16,BOT,CBLT,0,0), BBOYCB_MASK, PPCCOM,       { CR, BDP } },
1720 { "blt",     BBOCB(16,BOT,CBLT,0,0), BBOYCB_MASK, COM,          { CR, BD } },
1721 { "bltl-",   BBOCB(16,BOT,CBLT,0,1), BBOYCB_MASK, PPCCOM,       { CR, BDM } },
1722 { "bltl+",   BBOCB(16,BOT,CBLT,0,1), BBOYCB_MASK, PPCCOM,       { CR, BDP } },
1723 { "bltl",    BBOCB(16,BOT,CBLT,0,1), BBOYCB_MASK, COM,          { CR, BD } },
1724 { "blta-",   BBOCB(16,BOT,CBLT,1,0), BBOYCB_MASK, PPCCOM,       { CR, BDMA } },
1725 { "blta+",   BBOCB(16,BOT,CBLT,1,0), BBOYCB_MASK, PPCCOM,       { CR, BDPA } },
1726 { "blta",    BBOCB(16,BOT,CBLT,1,0), BBOYCB_MASK, COM,          { CR, BDA } },
1727 { "bltla-",  BBOCB(16,BOT,CBLT,1,1), BBOYCB_MASK, PPCCOM,       { CR, BDMA } },
1728 { "bltla+",  BBOCB(16,BOT,CBLT,1,1), BBOYCB_MASK, PPCCOM,       { CR, BDPA } },
1729 { "bltla",   BBOCB(16,BOT,CBLT,1,1), BBOYCB_MASK, COM,          { CR, BDA } },
1730 { "bgt-",    BBOCB(16,BOT,CBGT,0,0), BBOYCB_MASK, PPCCOM,       { CR, BDM } },
1731 { "bgt+",    BBOCB(16,BOT,CBGT,0,0), BBOYCB_MASK, PPCCOM,       { CR, BDP } },
1732 { "bgt",     BBOCB(16,BOT,CBGT,0,0), BBOYCB_MASK, COM,          { CR, BD } },
1733 { "bgtl-",   BBOCB(16,BOT,CBGT,0,1), BBOYCB_MASK, PPCCOM,       { CR, BDM } },
1734 { "bgtl+",   BBOCB(16,BOT,CBGT,0,1), BBOYCB_MASK, PPCCOM,       { CR, BDP } },
1735 { "bgtl",    BBOCB(16,BOT,CBGT,0,1), BBOYCB_MASK, COM,          { CR, BD } },
1736 { "bgta-",   BBOCB(16,BOT,CBGT,1,0), BBOYCB_MASK, PPCCOM,       { CR, BDMA } },
1737 { "bgta+",   BBOCB(16,BOT,CBGT,1,0), BBOYCB_MASK, PPCCOM,       { CR, BDPA } },
1738 { "bgta",    BBOCB(16,BOT,CBGT,1,0), BBOYCB_MASK, COM,          { CR, BDA } },
1739 { "bgtla-",  BBOCB(16,BOT,CBGT,1,1), BBOYCB_MASK, PPCCOM,       { CR, BDMA } },
1740 { "bgtla+",  BBOCB(16,BOT,CBGT,1,1), BBOYCB_MASK, PPCCOM,       { CR, BDPA } },
1741 { "bgtla",   BBOCB(16,BOT,CBGT,1,1), BBOYCB_MASK, COM,          { CR, BDA } },
1742 { "beq-",    BBOCB(16,BOT,CBEQ,0,0), BBOYCB_MASK, PPCCOM,       { CR, BDM } },
1743 { "beq+",    BBOCB(16,BOT,CBEQ,0,0), BBOYCB_MASK, PPCCOM,       { CR, BDP } },
1744 { "beq",     BBOCB(16,BOT,CBEQ,0,0), BBOYCB_MASK, COM,          { CR, BD } },
1745 { "beql-",   BBOCB(16,BOT,CBEQ,0,1), BBOYCB_MASK, PPCCOM,       { CR, BDM } },
1746 { "beql+",   BBOCB(16,BOT,CBEQ,0,1), BBOYCB_MASK, PPCCOM,       { CR, BDP } },
1747 { "beql",    BBOCB(16,BOT,CBEQ,0,1), BBOYCB_MASK, COM,          { CR, BD } },
1748 { "beqa-",   BBOCB(16,BOT,CBEQ,1,0), BBOYCB_MASK, PPCCOM,       { CR, BDMA } },
1749 { "beqa+",   BBOCB(16,BOT,CBEQ,1,0), BBOYCB_MASK, PPCCOM,       { CR, BDPA } },
1750 { "beqa",    BBOCB(16,BOT,CBEQ,1,0), BBOYCB_MASK, COM,          { CR, BDA } },
1751 { "beqla-",  BBOCB(16,BOT,CBEQ,1,1), BBOYCB_MASK, PPCCOM,       { CR, BDMA } },
1752 { "beqla+",  BBOCB(16,BOT,CBEQ,1,1), BBOYCB_MASK, PPCCOM,       { CR, BDPA } },
1753 { "beqla",   BBOCB(16,BOT,CBEQ,1,1), BBOYCB_MASK, COM,          { CR, BDA } },
1754 { "bso-",    BBOCB(16,BOT,CBSO,0,0), BBOYCB_MASK, PPCCOM,       { CR, BDM } },
1755 { "bso+",    BBOCB(16,BOT,CBSO,0,0), BBOYCB_MASK, PPCCOM,       { CR, BDP } },
1756 { "bso",     BBOCB(16,BOT,CBSO,0,0), BBOYCB_MASK, COM,          { CR, BD } },
1757 { "bsol-",   BBOCB(16,BOT,CBSO,0,1), BBOYCB_MASK, PPCCOM,       { CR, BDM } },
1758 { "bsol+",   BBOCB(16,BOT,CBSO,0,1), BBOYCB_MASK, PPCCOM,       { CR, BDP } },
1759 { "bsol",    BBOCB(16,BOT,CBSO,0,1), BBOYCB_MASK, COM,          { CR, BD } },
1760 { "bsoa-",   BBOCB(16,BOT,CBSO,1,0), BBOYCB_MASK, PPCCOM,       { CR, BDMA } },
1761 { "bsoa+",   BBOCB(16,BOT,CBSO,1,0), BBOYCB_MASK, PPCCOM,       { CR, BDPA } },
1762 { "bsoa",    BBOCB(16,BOT,CBSO,1,0), BBOYCB_MASK, COM,          { CR, BDA } },
1763 { "bsola-",  BBOCB(16,BOT,CBSO,1,1), BBOYCB_MASK, PPCCOM,       { CR, BDMA } },
1764 { "bsola+",  BBOCB(16,BOT,CBSO,1,1), BBOYCB_MASK, PPCCOM,       { CR, BDPA } },
1765 { "bsola",   BBOCB(16,BOT,CBSO,1,1), BBOYCB_MASK, COM,          { CR, BDA } },
1766 { "bun-",    BBOCB(16,BOT,CBSO,0,0), BBOYCB_MASK, PPCCOM,       { CR, BDM } },
1767 { "bun+",    BBOCB(16,BOT,CBSO,0,0), BBOYCB_MASK, PPCCOM,       { CR, BDP } },
1768 { "bun",     BBOCB(16,BOT,CBSO,0,0), BBOYCB_MASK, PPCCOM,       { CR, BD } },
1769 { "bunl-",   BBOCB(16,BOT,CBSO,0,1), BBOYCB_MASK, PPCCOM,       { CR, BDM } },
1770 { "bunl+",   BBOCB(16,BOT,CBSO,0,1), BBOYCB_MASK, PPCCOM,       { CR, BDP } },
1771 { "bunl",    BBOCB(16,BOT,CBSO,0,1), BBOYCB_MASK, PPCCOM,       { CR, BD } },
1772 { "buna-",   BBOCB(16,BOT,CBSO,1,0), BBOYCB_MASK, PPCCOM,       { CR, BDMA } },
1773 { "buna+",   BBOCB(16,BOT,CBSO,1,0), BBOYCB_MASK, PPCCOM,       { CR, BDPA } },
1774 { "buna",    BBOCB(16,BOT,CBSO,1,0), BBOYCB_MASK, PPCCOM,       { CR, BDA } },
1775 { "bunla-",  BBOCB(16,BOT,CBSO,1,1), BBOYCB_MASK, PPCCOM,       { CR, BDMA } },
1776 { "bunla+",  BBOCB(16,BOT,CBSO,1,1), BBOYCB_MASK, PPCCOM,       { CR, BDPA } },
1777 { "bunla",   BBOCB(16,BOT,CBSO,1,1), BBOYCB_MASK, PPCCOM,       { CR, BDA } },
1778 { "bge-",    BBOCB(16,BOF,CBLT,0,0), BBOYCB_MASK, PPCCOM,       { CR, BDM } },
1779 { "bge+",    BBOCB(16,BOF,CBLT,0,0), BBOYCB_MASK, PPCCOM,       { CR, BDP } },
1780 { "bge",     BBOCB(16,BOF,CBLT,0,0), BBOYCB_MASK, COM,          { CR, BD } },
1781 { "bgel-",   BBOCB(16,BOF,CBLT,0,1), BBOYCB_MASK, PPCCOM,       { CR, BDM } },
1782 { "bgel+",   BBOCB(16,BOF,CBLT,0,1), BBOYCB_MASK, PPCCOM,       { CR, BDP } },
1783 { "bgel",    BBOCB(16,BOF,CBLT,0,1), BBOYCB_MASK, COM,          { CR, BD } },
1784 { "bgea-",   BBOCB(16,BOF,CBLT,1,0), BBOYCB_MASK, PPCCOM,       { CR, BDMA } },
1785 { "bgea+",   BBOCB(16,BOF,CBLT,1,0), BBOYCB_MASK, PPCCOM,       { CR, BDPA } },
1786 { "bgea",    BBOCB(16,BOF,CBLT,1,0), BBOYCB_MASK, COM,          { CR, BDA } },
1787 { "bgela-",  BBOCB(16,BOF,CBLT,1,1), BBOYCB_MASK, PPCCOM,       { CR, BDMA } },
1788 { "bgela+",  BBOCB(16,BOF,CBLT,1,1), BBOYCB_MASK, PPCCOM,       { CR, BDPA } },
1789 { "bgela",   BBOCB(16,BOF,CBLT,1,1), BBOYCB_MASK, COM,          { CR, BDA } },
1790 { "bnl-",    BBOCB(16,BOF,CBLT,0,0), BBOYCB_MASK, PPCCOM,       { CR, BDM } },
1791 { "bnl+",    BBOCB(16,BOF,CBLT,0,0), BBOYCB_MASK, PPCCOM,       { CR, BDP } },
1792 { "bnl",     BBOCB(16,BOF,CBLT,0,0), BBOYCB_MASK, COM,          { CR, BD } },
1793 { "bnll-",   BBOCB(16,BOF,CBLT,0,1), BBOYCB_MASK, PPCCOM,       { CR, BDM } },
1794 { "bnll+",   BBOCB(16,BOF,CBLT,0,1), BBOYCB_MASK, PPCCOM,       { CR, BDP } },
1795 { "bnll",    BBOCB(16,BOF,CBLT,0,1), BBOYCB_MASK, COM,          { CR, BD } },
1796 { "bnla-",   BBOCB(16,BOF,CBLT,1,0), BBOYCB_MASK, PPCCOM,       { CR, BDMA } },
1797 { "bnla+",   BBOCB(16,BOF,CBLT,1,0), BBOYCB_MASK, PPCCOM,       { CR, BDPA } },
1798 { "bnla",    BBOCB(16,BOF,CBLT,1,0), BBOYCB_MASK, COM,          { CR, BDA } },
1799 { "bnlla-",  BBOCB(16,BOF,CBLT,1,1), BBOYCB_MASK, PPCCOM,       { CR, BDMA } },
1800 { "bnlla+",  BBOCB(16,BOF,CBLT,1,1), BBOYCB_MASK, PPCCOM,       { CR, BDPA } },
1801 { "bnlla",   BBOCB(16,BOF,CBLT,1,1), BBOYCB_MASK, COM,          { CR, BDA } },
1802 { "ble-",    BBOCB(16,BOF,CBGT,0,0), BBOYCB_MASK, PPCCOM,       { CR, BDM } },
1803 { "ble+",    BBOCB(16,BOF,CBGT,0,0), BBOYCB_MASK, PPCCOM,       { CR, BDP } },
1804 { "ble",     BBOCB(16,BOF,CBGT,0,0), BBOYCB_MASK, COM,          { CR, BD } },
1805 { "blel-",   BBOCB(16,BOF,CBGT,0,1), BBOYCB_MASK, PPCCOM,       { CR, BDM } },
1806 { "blel+",   BBOCB(16,BOF,CBGT,0,1), BBOYCB_MASK, PPCCOM,       { CR, BDP } },
1807 { "blel",    BBOCB(16,BOF,CBGT,0,1), BBOYCB_MASK, COM,          { CR, BD } },
1808 { "blea-",   BBOCB(16,BOF,CBGT,1,0), BBOYCB_MASK, PPCCOM,       { CR, BDMA } },
1809 { "blea+",   BBOCB(16,BOF,CBGT,1,0), BBOYCB_MASK, PPCCOM,       { CR, BDPA } },
1810 { "blea",    BBOCB(16,BOF,CBGT,1,0), BBOYCB_MASK, COM,          { CR, BDA } },
1811 { "blela-",  BBOCB(16,BOF,CBGT,1,1), BBOYCB_MASK, PPCCOM,       { CR, BDMA } },
1812 { "blela+",  BBOCB(16,BOF,CBGT,1,1), BBOYCB_MASK, PPCCOM,       { CR, BDPA } },
1813 { "blela",   BBOCB(16,BOF,CBGT,1,1), BBOYCB_MASK, COM,          { CR, BDA } },
1814 { "bng-",    BBOCB(16,BOF,CBGT,0,0), BBOYCB_MASK, PPCCOM,       { CR, BDM } },
1815 { "bng+",    BBOCB(16,BOF,CBGT,0,0), BBOYCB_MASK, PPCCOM,       { CR, BDP } },
1816 { "bng",     BBOCB(16,BOF,CBGT,0,0), BBOYCB_MASK, COM,          { CR, BD } },
1817 { "bngl-",   BBOCB(16,BOF,CBGT,0,1), BBOYCB_MASK, PPCCOM,       { CR, BDM } },
1818 { "bngl+",   BBOCB(16,BOF,CBGT,0,1), BBOYCB_MASK, PPCCOM,       { CR, BDP } },
1819 { "bngl",    BBOCB(16,BOF,CBGT,0,1), BBOYCB_MASK, COM,          { CR, BD } },
1820 { "bnga-",   BBOCB(16,BOF,CBGT,1,0), BBOYCB_MASK, PPCCOM,       { CR, BDMA } },
1821 { "bnga+",   BBOCB(16,BOF,CBGT,1,0), BBOYCB_MASK, PPCCOM,       { CR, BDPA } },
1822 { "bnga",    BBOCB(16,BOF,CBGT,1,0), BBOYCB_MASK, COM,          { CR, BDA } },
1823 { "bngla-",  BBOCB(16,BOF,CBGT,1,1), BBOYCB_MASK, PPCCOM,       { CR, BDMA } },
1824 { "bngla+",  BBOCB(16,BOF,CBGT,1,1), BBOYCB_MASK, PPCCOM,       { CR, BDPA } },
1825 { "bngla",   BBOCB(16,BOF,CBGT,1,1), BBOYCB_MASK, COM,          { CR, BDA } },
1826 { "bne-",    BBOCB(16,BOF,CBEQ,0,0), BBOYCB_MASK, PPCCOM,       { CR, BDM } },
1827 { "bne+",    BBOCB(16,BOF,CBEQ,0,0), BBOYCB_MASK, PPCCOM,       { CR, BDP } },
1828 { "bne",     BBOCB(16,BOF,CBEQ,0,0), BBOYCB_MASK, COM,          { CR, BD } },
1829 { "bnel-",   BBOCB(16,BOF,CBEQ,0,1), BBOYCB_MASK, PPCCOM,       { CR, BDM } },
1830 { "bnel+",   BBOCB(16,BOF,CBEQ,0,1), BBOYCB_MASK, PPCCOM,       { CR, BDP } },
1831 { "bnel",    BBOCB(16,BOF,CBEQ,0,1), BBOYCB_MASK, COM,          { CR, BD } },
1832 { "bnea-",   BBOCB(16,BOF,CBEQ,1,0), BBOYCB_MASK, PPCCOM,       { CR, BDMA } },
1833 { "bnea+",   BBOCB(16,BOF,CBEQ,1,0), BBOYCB_MASK, PPCCOM,       { CR, BDPA } },
1834 { "bnea",    BBOCB(16,BOF,CBEQ,1,0), BBOYCB_MASK, COM,          { CR, BDA } },
1835 { "bnela-",  BBOCB(16,BOF,CBEQ,1,1), BBOYCB_MASK, PPCCOM,       { CR, BDMA } },
1836 { "bnela+",  BBOCB(16,BOF,CBEQ,1,1), BBOYCB_MASK, PPCCOM,       { CR, BDPA } },
1837 { "bnela",   BBOCB(16,BOF,CBEQ,1,1), BBOYCB_MASK, COM,          { CR, BDA } },
1838 { "bns-",    BBOCB(16,BOF,CBSO,0,0), BBOYCB_MASK, PPCCOM,       { CR, BDM } },
1839 { "bns+",    BBOCB(16,BOF,CBSO,0,0), BBOYCB_MASK, PPCCOM,       { CR, BDP } },
1840 { "bns",     BBOCB(16,BOF,CBSO,0,0), BBOYCB_MASK, COM,          { CR, BD } },
1841 { "bnsl-",   BBOCB(16,BOF,CBSO,0,1), BBOYCB_MASK, PPCCOM,       { CR, BDM } },
1842 { "bnsl+",   BBOCB(16,BOF,CBSO,0,1), BBOYCB_MASK, PPCCOM,       { CR, BDP } },
1843 { "bnsl",    BBOCB(16,BOF,CBSO,0,1), BBOYCB_MASK, COM,          { CR, BD } },
1844 { "bnsa-",   BBOCB(16,BOF,CBSO,1,0), BBOYCB_MASK, PPCCOM,       { CR, BDMA } },
1845 { "bnsa+",   BBOCB(16,BOF,CBSO,1,0), BBOYCB_MASK, PPCCOM,       { CR, BDPA } },
1846 { "bnsa",    BBOCB(16,BOF,CBSO,1,0), BBOYCB_MASK, COM,          { CR, BDA } },
1847 { "bnsla-",  BBOCB(16,BOF,CBSO,1,1), BBOYCB_MASK, PPCCOM,       { CR, BDMA } },
1848 { "bnsla+",  BBOCB(16,BOF,CBSO,1,1), BBOYCB_MASK, PPCCOM,       { CR, BDPA } },
1849 { "bnsla",   BBOCB(16,BOF,CBSO,1,1), BBOYCB_MASK, COM,          { CR, BDA } },
1850 { "bnu-",    BBOCB(16,BOF,CBSO,0,0), BBOYCB_MASK, PPCCOM,       { CR, BDM } },
1851 { "bnu+",    BBOCB(16,BOF,CBSO,0,0), BBOYCB_MASK, PPCCOM,       { CR, BDP } },
1852 { "bnu",     BBOCB(16,BOF,CBSO,0,0), BBOYCB_MASK, PPCCOM,       { CR, BD } },
1853 { "bnul-",   BBOCB(16,BOF,CBSO,0,1), BBOYCB_MASK, PPCCOM,       { CR, BDM } },
1854 { "bnul+",   BBOCB(16,BOF,CBSO,0,1), BBOYCB_MASK, PPCCOM,       { CR, BDP } },
1855 { "bnul",    BBOCB(16,BOF,CBSO,0,1), BBOYCB_MASK, PPCCOM,       { CR, BD } },
1856 { "bnua-",   BBOCB(16,BOF,CBSO,1,0), BBOYCB_MASK, PPCCOM,       { CR, BDMA } },
1857 { "bnua+",   BBOCB(16,BOF,CBSO,1,0), BBOYCB_MASK, PPCCOM,       { CR, BDPA } },
1858 { "bnua",    BBOCB(16,BOF,CBSO,1,0), BBOYCB_MASK, PPCCOM,       { CR, BDA } },
1859 { "bnula-",  BBOCB(16,BOF,CBSO,1,1), BBOYCB_MASK, PPCCOM,       { CR, BDMA } },
1860 { "bnula+",  BBOCB(16,BOF,CBSO,1,1), BBOYCB_MASK, PPCCOM,       { CR, BDPA } },
1861 { "bnula",   BBOCB(16,BOF,CBSO,1,1), BBOYCB_MASK, PPCCOM,       { CR, BDA } },
1862 { "bdnzt-",  BBO(16,BODNZT,0,0), BBOY_MASK, PPCCOM,     { BI, BDM } },
1863 { "bdnzt+",  BBO(16,BODNZT,0,0), BBOY_MASK, PPCCOM,     { BI, BDP } },
1864 { "bdnzt",   BBO(16,BODNZT,0,0), BBOY_MASK, PPCCOM,     { BI, BD } },
1865 { "bdnztl-", BBO(16,BODNZT,0,1), BBOY_MASK, PPCCOM,     { BI, BDM } },
1866 { "bdnztl+", BBO(16,BODNZT,0,1), BBOY_MASK, PPCCOM,     { BI, BDP } },
1867 { "bdnztl",  BBO(16,BODNZT,0,1), BBOY_MASK, PPCCOM,     { BI, BD } },
1868 { "bdnzta-", BBO(16,BODNZT,1,0), BBOY_MASK, PPCCOM,     { BI, BDMA } },
1869 { "bdnzta+", BBO(16,BODNZT,1,0), BBOY_MASK, PPCCOM,     { BI, BDPA } },
1870 { "bdnzta",  BBO(16,BODNZT,1,0), BBOY_MASK, PPCCOM,     { BI, BDA } },
1871 { "bdnztla-",BBO(16,BODNZT,1,1), BBOY_MASK, PPCCOM,     { BI, BDMA } },
1872 { "bdnztla+",BBO(16,BODNZT,1,1), BBOY_MASK, PPCCOM,     { BI, BDPA } },
1873 { "bdnztla", BBO(16,BODNZT,1,1), BBOY_MASK, PPCCOM,     { BI, BDA } },
1874 { "bdnzf-",  BBO(16,BODNZF,0,0), BBOY_MASK, PPCCOM,     { BI, BDM } },
1875 { "bdnzf+",  BBO(16,BODNZF,0,0), BBOY_MASK, PPCCOM,     { BI, BDP } },
1876 { "bdnzf",   BBO(16,BODNZF,0,0), BBOY_MASK, PPCCOM,     { BI, BD } },
1877 { "bdnzfl-", BBO(16,BODNZF,0,1), BBOY_MASK, PPCCOM,     { BI, BDM } },
1878 { "bdnzfl+", BBO(16,BODNZF,0,1), BBOY_MASK, PPCCOM,     { BI, BDP } },
1879 { "bdnzfl",  BBO(16,BODNZF,0,1), BBOY_MASK, PPCCOM,     { BI, BD } },
1880 { "bdnzfa-", BBO(16,BODNZF,1,0), BBOY_MASK, PPCCOM,     { BI, BDMA } },
1881 { "bdnzfa+", BBO(16,BODNZF,1,0), BBOY_MASK, PPCCOM,     { BI, BDPA } },
1882 { "bdnzfa",  BBO(16,BODNZF,1,0), BBOY_MASK, PPCCOM,     { BI, BDA } },
1883 { "bdnzfla-",BBO(16,BODNZF,1,1), BBOY_MASK, PPCCOM,     { BI, BDMA } },
1884 { "bdnzfla+",BBO(16,BODNZF,1,1), BBOY_MASK, PPCCOM,     { BI, BDPA } },
1885 { "bdnzfla", BBO(16,BODNZF,1,1), BBOY_MASK, PPCCOM,     { BI, BDA } },
1886 { "bt-",     BBO(16,BOT,0,0), BBOY_MASK, PPCCOM,        { BI, BDM } },
1887 { "bt+",     BBO(16,BOT,0,0), BBOY_MASK, PPCCOM,        { BI, BDP } },
1888 { "bt",      BBO(16,BOT,0,0), BBOY_MASK, PPCCOM,        { BI, BD } },
1889 { "bbt",     BBO(16,BOT,0,0), BBOY_MASK, PWRCOM,        { BI, BD } },
1890 { "btl-",    BBO(16,BOT,0,1), BBOY_MASK, PPCCOM,        { BI, BDM } },
1891 { "btl+",    BBO(16,BOT,0,1), BBOY_MASK, PPCCOM,        { BI, BDP } },
1892 { "btl",     BBO(16,BOT,0,1), BBOY_MASK, PPCCOM,        { BI, BD } },
1893 { "bbtl",    BBO(16,BOT,0,1), BBOY_MASK, PWRCOM,        { BI, BD } },
1894 { "bta-",    BBO(16,BOT,1,0), BBOY_MASK, PPCCOM,        { BI, BDMA } },
1895 { "bta+",    BBO(16,BOT,1,0), BBOY_MASK, PPCCOM,        { BI, BDPA } },
1896 { "bta",     BBO(16,BOT,1,0), BBOY_MASK, PPCCOM,        { BI, BDA } },
1897 { "bbta",    BBO(16,BOT,1,0), BBOY_MASK, PWRCOM,        { BI, BDA } },
1898 { "btla-",   BBO(16,BOT,1,1), BBOY_MASK, PPCCOM,        { BI, BDMA } },
1899 { "btla+",   BBO(16,BOT,1,1), BBOY_MASK, PPCCOM,        { BI, BDPA } },
1900 { "btla",    BBO(16,BOT,1,1), BBOY_MASK, PPCCOM,        { BI, BDA } },
1901 { "bbtla",   BBO(16,BOT,1,1), BBOY_MASK, PWRCOM,        { BI, BDA } },
1902 { "bf-",     BBO(16,BOF,0,0), BBOY_MASK, PPCCOM,        { BI, BDM } },
1903 { "bf+",     BBO(16,BOF,0,0), BBOY_MASK, PPCCOM,        { BI, BDP } },
1904 { "bf",      BBO(16,BOF,0,0), BBOY_MASK, PPCCOM,        { BI, BD } },
1905 { "bbf",     BBO(16,BOF,0,0), BBOY_MASK, PWRCOM,        { BI, BD } },
1906 { "bfl-",    BBO(16,BOF,0,1), BBOY_MASK, PPCCOM,        { BI, BDM } },
1907 { "bfl+",    BBO(16,BOF,0,1), BBOY_MASK, PPCCOM,        { BI, BDP } },
1908 { "bfl",     BBO(16,BOF,0,1), BBOY_MASK, PPCCOM,        { BI, BD } },
1909 { "bbfl",    BBO(16,BOF,0,1), BBOY_MASK, PWRCOM,        { BI, BD } },
1910 { "bfa-",    BBO(16,BOF,1,0), BBOY_MASK, PPCCOM,        { BI, BDMA } },
1911 { "bfa+",    BBO(16,BOF,1,0), BBOY_MASK, PPCCOM,        { BI, BDPA } },
1912 { "bfa",     BBO(16,BOF,1,0), BBOY_MASK, PPCCOM,        { BI, BDA } },
1913 { "bbfa",    BBO(16,BOF,1,0), BBOY_MASK, PWRCOM,        { BI, BDA } },
1914 { "bfla-",   BBO(16,BOF,1,1), BBOY_MASK, PPCCOM,        { BI, BDMA } },
1915 { "bfla+",   BBO(16,BOF,1,1), BBOY_MASK, PPCCOM,        { BI, BDPA } },
1916 { "bfla",    BBO(16,BOF,1,1), BBOY_MASK, PPCCOM,        { BI, BDA } },
1917 { "bbfla",   BBO(16,BOF,1,1), BBOY_MASK, PWRCOM,        { BI, BDA } },
1918 { "bdzt-",   BBO(16,BODZT,0,0), BBOY_MASK, PPCCOM,      { BI, BDM } },
1919 { "bdzt+",   BBO(16,BODZT,0,0), BBOY_MASK, PPCCOM,      { BI, BDP } },
1920 { "bdzt",    BBO(16,BODZT,0,0), BBOY_MASK, PPCCOM,      { BI, BD } },
1921 { "bdztl-",  BBO(16,BODZT,0,1), BBOY_MASK, PPCCOM,      { BI, BDM } },
1922 { "bdztl+",  BBO(16,BODZT,0,1), BBOY_MASK, PPCCOM,      { BI, BDP } },
1923 { "bdztl",   BBO(16,BODZT,0,1), BBOY_MASK, PPCCOM,      { BI, BD } },
1924 { "bdzta-",  BBO(16,BODZT,1,0), BBOY_MASK, PPCCOM,      { BI, BDMA } },
1925 { "bdzta+",  BBO(16,BODZT,1,0), BBOY_MASK, PPCCOM,      { BI, BDPA } },
1926 { "bdzta",   BBO(16,BODZT,1,0), BBOY_MASK, PPCCOM,      { BI, BDA } },
1927 { "bdztla-", BBO(16,BODZT,1,1), BBOY_MASK, PPCCOM,      { BI, BDMA } },
1928 { "bdztla+", BBO(16,BODZT,1,1), BBOY_MASK, PPCCOM,      { BI, BDPA } },
1929 { "bdztla",  BBO(16,BODZT,1,1), BBOY_MASK, PPCCOM,      { BI, BDA } },
1930 { "bdzf-",   BBO(16,BODZF,0,0), BBOY_MASK, PPCCOM,      { BI, BDM } },
1931 { "bdzf+",   BBO(16,BODZF,0,0), BBOY_MASK, PPCCOM,      { BI, BDP } },
1932 { "bdzf",    BBO(16,BODZF,0,0), BBOY_MASK, PPCCOM,      { BI, BD } },
1933 { "bdzfl-",  BBO(16,BODZF,0,1), BBOY_MASK, PPCCOM,      { BI, BDM } },
1934 { "bdzfl+",  BBO(16,BODZF,0,1), BBOY_MASK, PPCCOM,      { BI, BDP } },
1935 { "bdzfl",   BBO(16,BODZF,0,1), BBOY_MASK, PPCCOM,      { BI, BD } },
1936 { "bdzfa-",  BBO(16,BODZF,1,0), BBOY_MASK, PPCCOM,      { BI, BDMA } },
1937 { "bdzfa+",  BBO(16,BODZF,1,0), BBOY_MASK, PPCCOM,      { BI, BDPA } },
1938 { "bdzfa",   BBO(16,BODZF,1,0), BBOY_MASK, PPCCOM,      { BI, BDA } },
1939 { "bdzfla-", BBO(16,BODZF,1,1), BBOY_MASK, PPCCOM,      { BI, BDMA } },
1940 { "bdzfla+", BBO(16,BODZF,1,1), BBOY_MASK, PPCCOM,      { BI, BDPA } },
1941 { "bdzfla",  BBO(16,BODZF,1,1), BBOY_MASK, PPCCOM,      { BI, BDA } },
1942 { "bc-",     B(16,0,0), B_MASK,         PPCCOM,         { BOE, BI, BDM } },
1943 { "bc+",     B(16,0,0), B_MASK,         PPCCOM,         { BOE, BI, BDP } },
1944 { "bc",      B(16,0,0), B_MASK,         COM,            { BO, BI, BD } },
1945 { "bcl-",    B(16,0,1), B_MASK,         PPCCOM,         { BOE, BI, BDM } },
1946 { "bcl+",    B(16,0,1), B_MASK,         PPCCOM,         { BOE, BI, BDP } },
1947 { "bcl",     B(16,0,1), B_MASK,         COM,            { BO, BI, BD } },
1948 { "bca-",    B(16,1,0), B_MASK,         PPCCOM,         { BOE, BI, BDMA } },
1949 { "bca+",    B(16,1,0), B_MASK,         PPCCOM,         { BOE, BI, BDPA } },
1950 { "bca",     B(16,1,0), B_MASK,         COM,            { BO, BI, BDA } },
1951 { "bcla-",   B(16,1,1), B_MASK,         PPCCOM,         { BOE, BI, BDMA } },
1952 { "bcla+",   B(16,1,1), B_MASK,         PPCCOM,         { BOE, BI, BDPA } },
1953 { "bcla",    B(16,1,1), B_MASK,         COM,            { BO, BI, BDA } },
1954
1955 { "sc",      SC(17,1,0), 0xffffffff,    PPC,            { 0 } },
1956 { "svc",     SC(17,0,0), SC_MASK,       POWER,          { LEV, FL1, FL2 } },
1957 { "svcl",    SC(17,0,1), SC_MASK,       POWER,          { LEV, FL1, FL2 } },
1958 { "svca",    SC(17,1,0), SC_MASK,       PWRCOM,         { SV } },
1959 { "svcla",   SC(17,1,1), SC_MASK,       POWER,          { SV } },
1960
1961 { "b",       B(18,0,0), B_MASK,         COM,    { LI } },
1962 { "bl",      B(18,0,1), B_MASK,         COM,    { LI } },
1963 { "ba",      B(18,1,0), B_MASK,         COM,    { LIA } },
1964 { "bla",     B(18,1,1), B_MASK,         COM,    { LIA } },
1965
1966 { "mcrf",    XL(19,0),  XLBB_MASK|(3<<21)|(3<<16), COM, { BF, BFA } },
1967
1968 { "blr",     XLO(19,BOU,16,0), XLBOBIBB_MASK, PPCCOM,   { 0 } },
1969 { "br",      XLO(19,BOU,16,0), XLBOBIBB_MASK, PWRCOM,   { 0 } },
1970 { "blrl",    XLO(19,BOU,16,1), XLBOBIBB_MASK, PPCCOM,   { 0 } },
1971 { "brl",     XLO(19,BOU,16,1), XLBOBIBB_MASK, PWRCOM,   { 0 } },
1972 { "bdnzlr",  XLO(19,BODNZ,16,0), XLBOBIBB_MASK, PPCCOM, { 0 } },
1973 { "bdnzlr-", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, PPCCOM, { 0 } },
1974 { "bdnzlr+", XLO(19,BODNZP,16,0), XLBOBIBB_MASK, PPCCOM,        { 0 } },
1975 { "bdnzlrl", XLO(19,BODNZ,16,1), XLBOBIBB_MASK, PPCCOM, { 0 } },
1976 { "bdnzlrl-",XLO(19,BODNZ,16,1), XLBOBIBB_MASK, PPCCOM, { 0 } },
1977 { "bdnzlrl+",XLO(19,BODNZP,16,1), XLBOBIBB_MASK, PPCCOM,        { 0 } },
1978 { "bdzlr",   XLO(19,BODZ,16,0), XLBOBIBB_MASK, PPCCOM,  { 0 } },
1979 { "bdzlr-",  XLO(19,BODZ,16,0), XLBOBIBB_MASK, PPCCOM,  { 0 } },
1980 { "bdzlr+",  XLO(19,BODZP,16,0), XLBOBIBB_MASK, PPCCOM, { 0 } },
1981 { "bdzlrl",  XLO(19,BODZ,16,1), XLBOBIBB_MASK, PPCCOM,  { 0 } },
1982 { "bdzlrl-", XLO(19,BODZ,16,1), XLBOBIBB_MASK, PPCCOM,  { 0 } },
1983 { "bdzlrl+", XLO(19,BODZP,16,1), XLBOBIBB_MASK, PPCCOM, { 0 } },
1984 { "bltlr",   XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
1985 { "bltlr-",  XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
1986 { "bltlr+",  XLOCB(19,BOTP,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
1987 { "bltr",    XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
1988 { "bltlrl",  XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
1989 { "bltlrl-", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
1990 { "bltlrl+", XLOCB(19,BOTP,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
1991 { "bltrl",   XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
1992 { "bgtlr",   XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
1993 { "bgtlr-",  XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
1994 { "bgtlr+",  XLOCB(19,BOTP,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
1995 { "bgtr",    XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
1996 { "bgtlrl",  XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
1997 { "bgtlrl-", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
1998 { "bgtlrl+", XLOCB(19,BOTP,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
1999 { "bgtrl",   XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2000 { "beqlr",   XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2001 { "beqlr-",  XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2002 { "beqlr+",  XLOCB(19,BOTP,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2003 { "beqr",    XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2004 { "beqlrl",  XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2005 { "beqlrl-", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2006 { "beqlrl+", XLOCB(19,BOTP,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2007 { "beqrl",   XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2008 { "bsolr",   XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2009 { "bsolr-",  XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2010 { "bsolr+",  XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2011 { "bsor",    XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2012 { "bsolrl",  XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2013 { "bsolrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2014 { "bsolrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2015 { "bsorl",   XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2016 { "bunlr",   XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2017 { "bunlr-",  XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2018 { "bunlr+",  XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2019 { "bunlrl",  XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2020 { "bunlrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2021 { "bunlrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2022 { "bgelr",   XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2023 { "bgelr-",  XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2024 { "bgelr+",  XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2025 { "bger",    XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2026 { "bgelrl",  XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2027 { "bgelrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2028 { "bgelrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2029 { "bgerl",   XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2030 { "bnllr",   XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2031 { "bnllr-",  XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2032 { "bnllr+",  XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2033 { "bnlr",    XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2034 { "bnllrl",  XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2035 { "bnllrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2036 { "bnllrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2037 { "bnlrl",   XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2038 { "blelr",   XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2039 { "blelr-",  XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2040 { "blelr+",  XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2041 { "bler",    XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2042 { "blelrl",  XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2043 { "blelrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2044 { "blelrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2045 { "blerl",   XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2046 { "bnglr",   XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2047 { "bnglr-",  XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2048 { "bnglr+",  XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2049 { "bngr",    XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2050 { "bnglrl",  XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2051 { "bnglrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2052 { "bnglrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2053 { "bngrl",   XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2054 { "bnelr",   XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2055 { "bnelr-",  XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2056 { "bnelr+",  XLOCB(19,BOFP,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2057 { "bner",    XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2058 { "bnelrl",  XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2059 { "bnelrl-", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2060 { "bnelrl+", XLOCB(19,BOFP,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2061 { "bnerl",   XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2062 { "bnslr",   XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2063 { "bnslr-",  XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2064 { "bnslr+",  XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2065 { "bnsr",    XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2066 { "bnslrl",  XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2067 { "bnslrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2068 { "bnslrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2069 { "bnsrl",   XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2070 { "bnulr",   XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2071 { "bnulr-",  XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2072 { "bnulr+",  XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2073 { "bnulrl",  XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2074 { "bnulrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2075 { "bnulrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2076 { "btlr",    XLO(19,BOT,16,0), XLBOBB_MASK, PPCCOM,     { BI } },
2077 { "btlr-",   XLO(19,BOT,16,0), XLBOBB_MASK, PPCCOM,     { BI } },
2078 { "btlr+",   XLO(19,BOTP,16,0), XLBOBB_MASK, PPCCOM,    { BI } },
2079 { "bbtr",    XLO(19,BOT,16,0), XLBOBB_MASK, PWRCOM,     { BI } },
2080 { "btlrl",   XLO(19,BOT,16,1), XLBOBB_MASK, PPCCOM,     { BI } },
2081 { "btlrl-",  XLO(19,BOT,16,1), XLBOBB_MASK, PPCCOM,     { BI } },
2082 { "btlrl+",  XLO(19,BOTP,16,1), XLBOBB_MASK, PPCCOM,    { BI } },
2083 { "bbtrl",   XLO(19,BOT,16,1), XLBOBB_MASK, PWRCOM,     { BI } },
2084 { "bflr",    XLO(19,BOF,16,0), XLBOBB_MASK, PPCCOM,     { BI } },
2085 { "bflr-",   XLO(19,BOF,16,0), XLBOBB_MASK, PPCCOM,     { BI } },
2086 { "bflr+",   XLO(19,BOFP,16,0), XLBOBB_MASK, PPCCOM,    { BI } },
2087 { "bbfr",    XLO(19,BOF,16,0), XLBOBB_MASK, PWRCOM,     { BI } },
2088 { "bflrl",   XLO(19,BOF,16,1), XLBOBB_MASK, PPCCOM,     { BI } },
2089 { "bflrl-",  XLO(19,BOF,16,1), XLBOBB_MASK, PPCCOM,     { BI } },
2090 { "bflrl+",  XLO(19,BOFP,16,1), XLBOBB_MASK, PPCCOM,    { BI } },
2091 { "bbfrl",   XLO(19,BOF,16,1), XLBOBB_MASK, PWRCOM,     { BI } },
2092 { "bdnztlr", XLO(19,BODNZT,16,0), XLBOBB_MASK, PPCCOM,  { BI } },
2093 { "bdnztlr-",XLO(19,BODNZT,16,0), XLBOBB_MASK, PPCCOM,  { BI } },
2094 { "bdnztlr+",XLO(19,BODNZTP,16,0), XLBOBB_MASK, PPCCOM, { BI } },
2095 { "bdnztlrl",XLO(19,BODNZT,16,1), XLBOBB_MASK, PPCCOM,  { BI } },
2096 { "bdnztlrl-",XLO(19,BODNZT,16,1), XLBOBB_MASK, PPCCOM, { BI } },
2097 { "bdnztlrl+",XLO(19,BODNZTP,16,1), XLBOBB_MASK, PPCCOM,{ BI } },
2098 { "bdnzflr", XLO(19,BODNZF,16,0), XLBOBB_MASK, PPCCOM,  { BI } },
2099 { "bdnzflr-",XLO(19,BODNZF,16,0), XLBOBB_MASK, PPCCOM,  { BI } },
2100 { "bdnzflr+",XLO(19,BODNZFP,16,0), XLBOBB_MASK, PPCCOM, { BI } },
2101 { "bdnzflrl",XLO(19,BODNZF,16,1), XLBOBB_MASK, PPCCOM,  { BI } },
2102 { "bdnzflrl-",XLO(19,BODNZF,16,1), XLBOBB_MASK, PPCCOM, { BI } },
2103 { "bdnzflrl+",XLO(19,BODNZFP,16,1), XLBOBB_MASK, PPCCOM,{ BI } },
2104 { "bdztlr",  XLO(19,BODZT,16,0), XLBOBB_MASK, PPCCOM,   { BI } },
2105 { "bdztlr-", XLO(19,BODZT,16,0), XLBOBB_MASK, PPCCOM,   { BI } },
2106 { "bdztlr+", XLO(19,BODZTP,16,0), XLBOBB_MASK, PPCCOM,  { BI } },
2107 { "bdztlrl", XLO(19,BODZT,16,1), XLBOBB_MASK, PPCCOM,   { BI } },
2108 { "bdztlrl-",XLO(19,BODZT,16,1), XLBOBB_MASK, PPCCOM,   { BI } },
2109 { "bdztlrl+",XLO(19,BODZTP,16,1), XLBOBB_MASK, PPCCOM,  { BI } },
2110 { "bdzflr",  XLO(19,BODZF,16,0), XLBOBB_MASK, PPCCOM,   { BI } },
2111 { "bdzflr-", XLO(19,BODZF,16,0), XLBOBB_MASK, PPCCOM,   { BI } },
2112 { "bdzflr+", XLO(19,BODZFP,16,0), XLBOBB_MASK, PPCCOM,  { BI } },
2113 { "bdzflrl", XLO(19,BODZF,16,1), XLBOBB_MASK, PPCCOM,   { BI } },
2114 { "bdzflrl-",XLO(19,BODZF,16,1), XLBOBB_MASK, PPCCOM,   { BI } },
2115 { "bdzflrl+",XLO(19,BODZFP,16,1), XLBOBB_MASK, PPCCOM,  { BI } },
2116 { "bclr",    XLLK(19,16,0), XLYBB_MASK, PPCCOM,         { BO, BI } },
2117 { "bclrl",   XLLK(19,16,1), XLYBB_MASK, PPCCOM,         { BO, BI } },
2118 { "bclr+",   XLYLK(19,16,1,0), XLYBB_MASK, PPCCOM,      { BOE, BI } },
2119 { "bclrl+",  XLYLK(19,16,1,1), XLYBB_MASK, PPCCOM,      { BOE, BI } },
2120 { "bclr-",   XLYLK(19,16,0,0), XLYBB_MASK, PPCCOM,      { BOE, BI } },
2121 { "bclrl-",  XLYLK(19,16,0,1), XLYBB_MASK, PPCCOM,      { BOE, BI } },
2122 { "bcr",     XLLK(19,16,0), XLBB_MASK,  PWRCOM,         { BO, BI } },
2123 { "bcrl",    XLLK(19,16,1), XLBB_MASK,  PWRCOM,         { BO, BI } },
2124
2125 { "rfid",    XL(19,18), 0xffffffff,     PPC64,          { 0 } },
2126
2127 { "crnot",   XL(19,33), XL_MASK,        PPCCOM,         { BT, BA, BBA } },
2128 { "crnor",   XL(19,33), XL_MASK,        COM,            { BT, BA, BB } },
2129
2130 { "rfi",     XL(19,50), 0xffffffff,     COM,            { 0 } },
2131 { "rfci",    XL(19,51), 0xffffffff,     PPC403,         { 0 } },
2132
2133 { "rfsvc",   XL(19,82), 0xffffffff,     POWER,          { 0 } },
2134
2135 { "crandc",  XL(19,129), XL_MASK,       COM,            { BT, BA, BB } },
2136
2137 { "isync",   XL(19,150), 0xffffffff,    PPCCOM,         { 0 } },
2138 { "ics",     XL(19,150), 0xffffffff,    PWRCOM,         { 0 } },
2139
2140 { "crclr",   XL(19,193), XL_MASK,       PPCCOM,         { BT, BAT, BBA } },
2141 { "crxor",   XL(19,193), XL_MASK,       COM,            { BT, BA, BB } },
2142
2143 { "crnand",  XL(19,225), XL_MASK,       COM,            { BT, BA, BB } },
2144
2145 { "crand",   XL(19,257), XL_MASK,       COM,            { BT, BA, BB } },
2146
2147 { "crset",   XL(19,289), XL_MASK,       PPCCOM,         { BT, BAT, BBA } },
2148 { "creqv",   XL(19,289), XL_MASK,       COM,            { BT, BA, BB } },
2149
2150 { "crorc",   XL(19,417), XL_MASK,       COM,            { BT, BA, BB } },
2151
2152 { "crmove",  XL(19,449), XL_MASK,       PPCCOM,         { BT, BA, BBA } },
2153 { "cror",    XL(19,449), XL_MASK,       COM,            { BT, BA, BB } },
2154
2155 { "bctr",    XLO(19,BOU,528,0), XLBOBIBB_MASK, COM,     { 0 } },
2156 { "bctrl",   XLO(19,BOU,528,1), XLBOBIBB_MASK, COM,     { 0 } },
2157 { "bltctr",  XLOCB(19,BOT,CBLT,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2158 { "bltctr-", XLOCB(19,BOT,CBLT,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2159 { "bltctr+", XLOCB(19,BOTP,CBLT,528,0), XLBOCBBB_MASK, PPCCOM,  { CR } },
2160 { "bltctrl", XLOCB(19,BOT,CBLT,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2161 { "bltctrl-",XLOCB(19,BOT,CBLT,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2162 { "bltctrl+",XLOCB(19,BOTP,CBLT,528,1), XLBOCBBB_MASK, PPCCOM,  { CR } },
2163 { "bgtctr",  XLOCB(19,BOT,CBGT,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2164 { "bgtctr-", XLOCB(19,BOT,CBGT,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2165 { "bgtctr+", XLOCB(19,BOTP,CBGT,528,0), XLBOCBBB_MASK, PPCCOM,  { CR } },
2166 { "bgtctrl", XLOCB(19,BOT,CBGT,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2167 { "bgtctrl-",XLOCB(19,BOT,CBGT,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2168 { "bgtctrl+",XLOCB(19,BOTP,CBGT,528,1), XLBOCBBB_MASK, PPCCOM,  { CR } },
2169 { "beqctr",  XLOCB(19,BOT,CBEQ,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2170 { "beqctr-", XLOCB(19,BOT,CBEQ,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2171 { "beqctr+", XLOCB(19,BOTP,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM,  { CR } },
2172 { "beqctrl", XLOCB(19,BOT,CBEQ,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2173 { "beqctrl-",XLOCB(19,BOT,CBEQ,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2174 { "beqctrl+",XLOCB(19,BOTP,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM,  { CR } },
2175 { "bsoctr",  XLOCB(19,BOT,CBSO,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2176 { "bsoctr-", XLOCB(19,BOT,CBSO,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2177 { "bsoctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, PPCCOM,  { CR } },
2178 { "bsoctrl", XLOCB(19,BOT,CBSO,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2179 { "bsoctrl-",XLOCB(19,BOT,CBSO,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2180 { "bsoctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, PPCCOM,  { CR } },
2181 { "bunctr",  XLOCB(19,BOT,CBSO,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2182 { "bunctr-", XLOCB(19,BOT,CBSO,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2183 { "bunctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, PPCCOM,  { CR } },
2184 { "bunctrl", XLOCB(19,BOT,CBSO,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2185 { "bunctrl-",XLOCB(19,BOT,CBSO,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2186 { "bunctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, PPCCOM,  { CR } },
2187 { "bgectr",  XLOCB(19,BOF,CBLT,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2188 { "bgectr-", XLOCB(19,BOF,CBLT,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2189 { "bgectr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, PPCCOM,  { CR } },
2190 { "bgectrl", XLOCB(19,BOF,CBLT,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2191 { "bgectrl-",XLOCB(19,BOF,CBLT,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2192 { "bgectrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, PPCCOM,  { CR } },
2193 { "bnlctr",  XLOCB(19,BOF,CBLT,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2194 { "bnlctr-", XLOCB(19,BOF,CBLT,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2195 { "bnlctr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, PPCCOM,  { CR } },
2196 { "bnlctrl", XLOCB(19,BOF,CBLT,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2197 { "bnlctrl-",XLOCB(19,BOF,CBLT,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2198 { "bnlctrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, PPCCOM,  { CR } },
2199 { "blectr",  XLOCB(19,BOF,CBGT,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2200 { "blectr-", XLOCB(19,BOF,CBGT,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2201 { "blectr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, PPCCOM,  { CR } },
2202 { "blectrl", XLOCB(19,BOF,CBGT,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2203 { "blectrl-",XLOCB(19,BOF,CBGT,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2204 { "blectrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, PPCCOM,  { CR } },
2205 { "bngctr",  XLOCB(19,BOF,CBGT,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2206 { "bngctr-", XLOCB(19,BOF,CBGT,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2207 { "bngctr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, PPCCOM,  { CR } },
2208 { "bngctrl", XLOCB(19,BOF,CBGT,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2209 { "bngctrl-",XLOCB(19,BOF,CBGT,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2210 { "bngctrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, PPCCOM,  { CR } },
2211 { "bnectr",  XLOCB(19,BOF,CBEQ,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2212 { "bnectr-", XLOCB(19,BOF,CBEQ,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2213 { "bnectr+", XLOCB(19,BOFP,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM,  { CR } },
2214 { "bnectrl", XLOCB(19,BOF,CBEQ,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2215 { "bnectrl-",XLOCB(19,BOF,CBEQ,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2216 { "bnectrl+",XLOCB(19,BOFP,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM,  { CR } },
2217 { "bnsctr",  XLOCB(19,BOF,CBSO,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2218 { "bnsctr-", XLOCB(19,BOF,CBSO,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2219 { "bnsctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, PPCCOM,  { CR } },
2220 { "bnsctrl", XLOCB(19,BOF,CBSO,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2221 { "bnsctrl-",XLOCB(19,BOF,CBSO,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2222 { "bnsctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, PPCCOM,  { CR } },
2223 { "bnuctr",  XLOCB(19,BOF,CBSO,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2224 { "bnuctr-", XLOCB(19,BOF,CBSO,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2225 { "bnuctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, PPCCOM,  { CR } },
2226 { "bnuctrl", XLOCB(19,BOF,CBSO,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2227 { "bnuctrl-",XLOCB(19,BOF,CBSO,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2228 { "bnuctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, PPCCOM,  { CR } },
2229 { "btctr",   XLO(19,BOT,528,0),  XLBOBB_MASK, PPCCOM,   { BI } },
2230 { "btctr-",  XLO(19,BOT,528,0),  XLBOBB_MASK, PPCCOM,   { BI } },
2231 { "btctr+",  XLO(19,BOTP,528,0), XLBOBB_MASK, PPCCOM,   { BI } },
2232 { "btctrl",  XLO(19,BOT,528,1),  XLBOBB_MASK, PPCCOM,   { BI } },
2233 { "btctrl-", XLO(19,BOT,528,1),  XLBOBB_MASK, PPCCOM,   { BI } },
2234 { "btctrl+", XLO(19,BOTP,528,1), XLBOBB_MASK, PPCCOM,   { BI } },
2235 { "bfctr",   XLO(19,BOF,528,0),  XLBOBB_MASK, PPCCOM,   { BI } },
2236 { "bfctr-",  XLO(19,BOF,528,0),  XLBOBB_MASK, PPCCOM,   { BI } },
2237 { "bfctr+",  XLO(19,BOFP,528,0), XLBOBB_MASK, PPCCOM,   { BI } },
2238 { "bfctrl",  XLO(19,BOF,528,1),  XLBOBB_MASK, PPCCOM,   { BI } },
2239 { "bfctrl-", XLO(19,BOF,528,1),  XLBOBB_MASK, PPCCOM,   { BI } },
2240 { "bfctrl+", XLO(19,BOFP,528,1), XLBOBB_MASK, PPCCOM,   { BI } },
2241 { "bcctr",   XLLK(19,528,0),     XLYBB_MASK,  PPCCOM,   { BO, BI } },
2242 { "bcctr-",  XLYLK(19,528,0,0),  XLYBB_MASK,  PPCCOM,   { BOE, BI } },
2243 { "bcctr+",  XLYLK(19,528,1,0),  XLYBB_MASK,  PPCCOM,   { BOE, BI } },
2244 { "bcctrl",  XLLK(19,528,1),     XLYBB_MASK,  PPCCOM,   { BO, BI } },
2245 { "bcctrl-", XLYLK(19,528,0,1),  XLYBB_MASK,  PPCCOM,   { BOE, BI } },
2246 { "bcctrl+", XLYLK(19,528,1,1),  XLYBB_MASK,  PPCCOM,   { BOE, BI } },
2247 { "bcc",     XLLK(19,528,0),     XLBB_MASK,   PWRCOM,   { BO, BI } },
2248 { "bccl",    XLLK(19,528,1),     XLBB_MASK,   PWRCOM,   { BO, BI } },
2249
2250 { "rlwimi",  M(20,0),   M_MASK,         PPCCOM,         { RA,RS,SH,MBE,ME } },
2251 { "rlimi",   M(20,0),   M_MASK,         PWRCOM,         { RA,RS,SH,MBE,ME } },
2252
2253 { "rlwimi.", M(20,1),   M_MASK,         PPCCOM,         { RA,RS,SH,MBE,ME } },
2254 { "rlimi.",  M(20,1),   M_MASK,         PWRCOM,         { RA,RS,SH,MBE,ME } },
2255
2256 { "rotlwi",  MME(21,31,0), MMBME_MASK,  PPCCOM,         { RA, RS, SH } },
2257 { "clrlwi",  MME(21,31,0), MSHME_MASK,  PPCCOM,         { RA, RS, MB } },
2258 { "rlwinm",  M(21,0),   M_MASK,         PPCCOM,         { RA,RS,SH,MBE,ME } },
2259 { "rlinm",   M(21,0),   M_MASK,         PWRCOM,         { RA,RS,SH,MBE,ME } },
2260 { "rotlwi.", MME(21,31,1), MMBME_MASK,  PPCCOM,         { RA,RS,SH } },
2261 { "clrlwi.", MME(21,31,1), MSHME_MASK,  PPCCOM,         { RA, RS, MB } },
2262 { "rlwinm.", M(21,1),   M_MASK,         PPCCOM,         { RA,RS,SH,MBE,ME } },
2263 { "rlinm.",  M(21,1),   M_MASK,         PWRCOM,         { RA,RS,SH,MBE,ME } },
2264
2265 { "rlmi",    M(22,0),   M_MASK,         M601,           { RA,RS,RB,MBE,ME } },
2266 { "rlmi.",   M(22,1),   M_MASK,         M601,           { RA,RS,RB,MBE,ME } },
2267
2268 { "rotlw",   MME(23,31,0), MMBME_MASK,  PPCCOM,         { RA, RS, RB } },
2269 { "rlwnm",   M(23,0),   M_MASK,         PPCCOM,         { RA,RS,RB,MBE,ME } },
2270 { "rlnm",    M(23,0),   M_MASK,         PWRCOM,         { RA,RS,RB,MBE,ME } },
2271 { "rotlw.",  MME(23,31,1), MMBME_MASK,  PPCCOM,         { RA, RS, RB } },
2272 { "rlwnm.",  M(23,1),   M_MASK,         PPCCOM,         { RA,RS,RB,MBE,ME } },
2273 { "rlnm.",   M(23,1),   M_MASK,         PWRCOM,         { RA,RS,RB,MBE,ME } },
2274
2275 { "nop",     OP(24),    0xffffffff,     PPCCOM,         { 0 } },
2276 { "ori",     OP(24),    OP_MASK,        PPCCOM,         { RA, RS, UI } },
2277 { "oril",    OP(24),    OP_MASK,        PWRCOM,         { RA, RS, UI } },
2278
2279 { "oris",    OP(25),    OP_MASK,        PPCCOM,         { RA, RS, UI } },
2280 { "oriu",    OP(25),    OP_MASK,        PWRCOM,         { RA, RS, UI } },
2281
2282 { "xori",    OP(26),    OP_MASK,        PPCCOM,         { RA, RS, UI } },
2283 { "xoril",   OP(26),    OP_MASK,        PWRCOM,         { RA, RS, UI } },
2284
2285 { "xoris",   OP(27),    OP_MASK,        PPCCOM,         { RA, RS, UI } },
2286 { "xoriu",   OP(27),    OP_MASK,        PWRCOM,         { RA, RS, UI } },
2287
2288 { "andi.",   OP(28),    OP_MASK,        PPCCOM,         { RA, RS, UI } },
2289 { "andil.",  OP(28),    OP_MASK,        PWRCOM,         { RA, RS, UI } },
2290
2291 { "andis.",  OP(29),    OP_MASK,        PPCCOM,         { RA, RS, UI } },
2292 { "andiu.",  OP(29),    OP_MASK,        PWRCOM,         { RA, RS, UI } },
2293
2294 { "rotldi",  MD(30,0,0), MDMB_MASK,     PPC64,          { RA, RS, SH6 } },
2295 { "clrldi",  MD(30,0,0), MDSH_MASK,     PPC64,          { RA, RS, MB6 } },
2296 { "rldicl",  MD(30,0,0), MD_MASK,       PPC64,          { RA, RS, SH6, MB6 } },
2297 { "rotldi.", MD(30,0,1), MDMB_MASK,     PPC64,          { RA, RS, SH6 } },
2298 { "clrldi.", MD(30,0,1), MDSH_MASK,     PPC64,          { RA, RS, MB6 } },
2299 { "rldicl.", MD(30,0,1), MD_MASK,       PPC64,          { RA, RS, SH6, MB6 } },
2300
2301 { "rldicr",  MD(30,1,0), MD_MASK,       PPC64,          { RA, RS, SH6, ME6 } },
2302 { "rldicr.", MD(30,1,1), MD_MASK,       PPC64,          { RA, RS, SH6, ME6 } },
2303
2304 { "rldic",   MD(30,2,0), MD_MASK,       PPC64,          { RA, RS, SH6, MB6 } },
2305 { "rldic.",  MD(30,2,1), MD_MASK,       PPC64,          { RA, RS, SH6, MB6 } },
2306
2307 { "rldimi",  MD(30,3,0), MD_MASK,       PPC64,          { RA, RS, SH6, MB6 } },
2308 { "rldimi.", MD(30,3,1), MD_MASK,       PPC64,          { RA, RS, SH6, MB6 } },
2309
2310 { "rotld",   MDS(30,8,0), MDSMB_MASK,   PPC64,          { RA, RS, RB } },
2311 { "rldcl",   MDS(30,8,0), MDS_MASK,     PPC64,          { RA, RS, RB, MB6 } },
2312 { "rotld.",  MDS(30,8,1), MDSMB_MASK,   PPC64,          { RA, RS, RB } },
2313 { "rldcl.",  MDS(30,8,1), MDS_MASK,     PPC64,          { RA, RS, RB, MB6 } },
2314
2315 { "rldcr",   MDS(30,9,0), MDS_MASK,     PPC64,          { RA, RS, RB, ME6 } },
2316 { "rldcr.",  MDS(30,9,1), MDS_MASK,     PPC64,          { RA, RS, RB, ME6 } },
2317
2318 { "cmpw",    XCMPL(31,0,0), XCMPL_MASK, PPCCOM,         { OBF, RA, RB } },
2319 { "cmpd",    XCMPL(31,0,1), XCMPL_MASK, PPC64,          { OBF, RA, RB } },
2320 { "cmp",     X(31,0),   XCMP_MASK,      PPCONLY,        { BF, L, RA, RB } },
2321 { "cmp",     X(31,0),   XCMPL_MASK,     PWRCOM,         { BF, RA, RB } },
2322
2323 { "twlgt",   XTO(31,4,TOLGT), XTO_MASK, PPCCOM,         { RA, RB } },
2324 { "tlgt",    XTO(31,4,TOLGT), XTO_MASK, PWRCOM,         { RA, RB } },
2325 { "twllt",   XTO(31,4,TOLLT), XTO_MASK, PPCCOM,         { RA, RB } },
2326 { "tllt",    XTO(31,4,TOLLT), XTO_MASK, PWRCOM,         { RA, RB } },
2327 { "tweq",    XTO(31,4,TOEQ), XTO_MASK,  PPCCOM,         { RA, RB } },
2328 { "teq",     XTO(31,4,TOEQ), XTO_MASK,  PWRCOM,         { RA, RB } },
2329 { "twlge",   XTO(31,4,TOLGE), XTO_MASK, PPCCOM,         { RA, RB } },
2330 { "tlge",    XTO(31,4,TOLGE), XTO_MASK, PWRCOM,         { RA, RB } },
2331 { "twlnl",   XTO(31,4,TOLNL), XTO_MASK, PPCCOM,         { RA, RB } },
2332 { "tlnl",    XTO(31,4,TOLNL), XTO_MASK, PWRCOM,         { RA, RB } },
2333 { "twlle",   XTO(31,4,TOLLE), XTO_MASK, PPCCOM,         { RA, RB } },
2334 { "tlle",    XTO(31,4,TOLLE), XTO_MASK, PWRCOM,         { RA, RB } },
2335 { "twlng",   XTO(31,4,TOLNG), XTO_MASK, PPCCOM,         { RA, RB } },
2336 { "tlng",    XTO(31,4,TOLNG), XTO_MASK, PWRCOM,         { RA, RB } },
2337 { "twgt",    XTO(31,4,TOGT), XTO_MASK,  PPCCOM,         { RA, RB } },
2338 { "tgt",     XTO(31,4,TOGT), XTO_MASK,  PWRCOM,         { RA, RB } },
2339 { "twge",    XTO(31,4,TOGE), XTO_MASK,  PPCCOM,         { RA, RB } },
2340 { "tge",     XTO(31,4,TOGE), XTO_MASK,  PWRCOM,         { RA, RB } },
2341 { "twnl",    XTO(31,4,TONL), XTO_MASK,  PPCCOM,         { RA, RB } },
2342 { "tnl",     XTO(31,4,TONL), XTO_MASK,  PWRCOM,         { RA, RB } },
2343 { "twlt",    XTO(31,4,TOLT), XTO_MASK,  PPCCOM,         { RA, RB } },
2344 { "tlt",     XTO(31,4,TOLT), XTO_MASK,  PWRCOM,         { RA, RB } },
2345 { "twle",    XTO(31,4,TOLE), XTO_MASK,  PPCCOM,         { RA, RB } },
2346 { "tle",     XTO(31,4,TOLE), XTO_MASK,  PWRCOM,         { RA, RB } },
2347 { "twng",    XTO(31,4,TONG), XTO_MASK,  PPCCOM,         { RA, RB } },
2348 { "tng",     XTO(31,4,TONG), XTO_MASK,  PWRCOM,         { RA, RB } },
2349 { "twne",    XTO(31,4,TONE), XTO_MASK,  PPCCOM,         { RA, RB } },
2350 { "tne",     XTO(31,4,TONE), XTO_MASK,  PWRCOM,         { RA, RB } },
2351 { "trap",    XTO(31,4,TOU), 0xffffffff, PPCCOM,         { 0 } },
2352 { "tw",      X(31,4),   X_MASK,         PPCCOM,         { TO, RA, RB } },
2353 { "t",       X(31,4),   X_MASK,         PWRCOM,         { TO, RA, RB } },
2354
2355 { "subfc",   XO(31,8,0,0), XO_MASK,     PPCCOM,         { RT, RA, RB } },
2356 { "sf",      XO(31,8,0,0), XO_MASK,     PWRCOM,         { RT, RA, RB } },
2357 { "subc",    XO(31,8,0,0), XO_MASK,     PPC,            { RT, RB, RA } },
2358 { "subfc.",  XO(31,8,0,1), XO_MASK,     PPCCOM,         { RT, RA, RB } },
2359 { "sf.",     XO(31,8,0,1), XO_MASK,     PWRCOM,         { RT, RA, RB } },
2360 { "subc.",   XO(31,8,0,1), XO_MASK,     PPCCOM,         { RT, RB, RA } },
2361 { "subfco",  XO(31,8,1,0), XO_MASK,     PPCCOM,         { RT, RA, RB } },
2362 { "sfo",     XO(31,8,1,0), XO_MASK,     PWRCOM,         { RT, RA, RB } },
2363 { "subco",   XO(31,8,1,0), XO_MASK,     PPC,            { RT, RB, RA } },
2364 { "subfco.", XO(31,8,1,1), XO_MASK,     PPCCOM,         { RT, RA, RB } },
2365 { "sfo.",    XO(31,8,1,1), XO_MASK,     PWRCOM,         { RT, RA, RB } },
2366 { "subco.",  XO(31,8,1,1), XO_MASK,     PPC,            { RT, RB, RA } },
2367
2368 { "mulhdu",  XO(31,9,0,0), XO_MASK,     PPC64,          { RT, RA, RB } },
2369 { "mulhdu.", XO(31,9,0,1), XO_MASK,     PPC64,          { RT, RA, RB } },
2370
2371 { "addc",    XO(31,10,0,0), XO_MASK,    PPCCOM,         { RT, RA, RB } },
2372 { "a",       XO(31,10,0,0), XO_MASK,    PWRCOM,         { RT, RA, RB } },
2373 { "addc.",   XO(31,10,0,1), XO_MASK,    PPCCOM,         { RT, RA, RB } },
2374 { "a.",      XO(31,10,0,1), XO_MASK,    PWRCOM,         { RT, RA, RB } },
2375 { "addco",   XO(31,10,1,0), XO_MASK,    PPCCOM,         { RT, RA, RB } },
2376 { "ao",      XO(31,10,1,0), XO_MASK,    PWRCOM,         { RT, RA, RB } },
2377 { "addco.",  XO(31,10,1,1), XO_MASK,    PPCCOM,         { RT, RA, RB } },
2378 { "ao.",     XO(31,10,1,1), XO_MASK,    PWRCOM,         { RT, RA, RB } },
2379
2380 { "mulhwu",  XO(31,11,0,0), XO_MASK,    PPC,            { RT, RA, RB } },
2381 { "mulhwu.", XO(31,11,0,1), XO_MASK,    PPC,            { RT, RA, RB } },
2382
2383 { "mfcr",    X(31,19),  XRARB_MASK,     COM,            { RT } },
2384
2385 { "lwarx",   X(31,20),  X_MASK,         PPC,            { RT, RA, RB } },
2386
2387 { "ldx",     X(31,21),  X_MASK,         PPC64,          { RT, RA, RB } },
2388
2389 { "lwzx",    X(31,23),  X_MASK,         PPCCOM,         { RT, RA, RB } },
2390 { "lx",      X(31,23),  X_MASK,         PWRCOM,         { RT, RA, RB } },
2391
2392 { "slw",     XRC(31,24,0), X_MASK,      PPCCOM,         { RA, RS, RB } },
2393 { "sl",      XRC(31,24,0), X_MASK,      PWRCOM,         { RA, RS, RB } },
2394 { "slw.",    XRC(31,24,1), X_MASK,      PPCCOM,         { RA, RS, RB } },
2395 { "sl.",     XRC(31,24,1), X_MASK,      PWRCOM,         { RA, RS, RB } },
2396
2397 { "cntlzw",  XRC(31,26,0), XRB_MASK,    PPCCOM,         { RA, RS } },
2398 { "cntlz",   XRC(31,26,0), XRB_MASK,    PWRCOM,         { RA, RS } },
2399 { "cntlzw.", XRC(31,26,1), XRB_MASK,    PPCCOM,         { RA, RS } },
2400 { "cntlz.",  XRC(31,26,1), XRB_MASK,    PWRCOM,         { RA, RS } },
2401
2402 { "sld",     XRC(31,27,0), X_MASK,      PPC64,          { RA, RS, RB } },
2403 { "sld.",    XRC(31,27,1), X_MASK,      PPC64,          { RA, RS, RB } },
2404
2405 { "and",     XRC(31,28,0), X_MASK,      COM,            { RA, RS, RB } },
2406 { "and.",    XRC(31,28,1), X_MASK,      COM,            { RA, RS, RB } },
2407
2408 { "maskg",   XRC(31,29,0), X_MASK,      M601,           { RA, RS, RB } },
2409 { "maskg.",  XRC(31,29,1), X_MASK,      M601,           { RA, RS, RB } },
2410
2411 { "cmplw",   XCMPL(31,32,0), XCMPL_MASK, PPCCOM,        { OBF, RA, RB } },
2412 { "cmpld",   XCMPL(31,32,1), XCMPL_MASK, PPC64,         { OBF, RA, RB } },
2413 { "cmpl",    X(31,32),  XCMP_MASK,       PPCONLY,       { BF, L, RA, RB } },
2414 { "cmpl",    X(31,32),  XCMPL_MASK,      PWRCOM,        { BF, RA, RB } },
2415
2416 { "subf",    XO(31,40,0,0), XO_MASK,    PPC,            { RT, RA, RB } },
2417 { "sub",     XO(31,40,0,0), XO_MASK,    PPC,            { RT, RB, RA } },
2418 { "subf.",   XO(31,40,0,1), XO_MASK,    PPC,            { RT, RA, RB } },
2419 { "sub.",    XO(31,40,0,1), XO_MASK,    PPC,            { RT, RB, RA } },
2420 { "subfo",   XO(31,40,1,0), XO_MASK,    PPC,            { RT, RA, RB } },
2421 { "subo",    XO(31,40,1,0), XO_MASK,    PPC,            { RT, RB, RA } },
2422 { "subfo.",  XO(31,40,1,1), XO_MASK,    PPC,            { RT, RA, RB } },
2423 { "subo.",   XO(31,40,1,1), XO_MASK,    PPC,            { RT, RB, RA } },
2424
2425 { "ldux",    X(31,53),  X_MASK,         PPC64,          { RT, RAL, RB } },
2426
2427 { "dcbst",   X(31,54),  XRT_MASK,       PPC,            { RA, RB } },
2428
2429 { "lwzux",   X(31,55),  X_MASK,         PPCCOM,         { RT, RAL, RB } },
2430 { "lux",     X(31,55),  X_MASK,         PWRCOM,         { RT, RA, RB } },
2431
2432 { "cntlzd",  XRC(31,58,0), XRB_MASK,    PPC64,          { RA, RS } },
2433 { "cntlzd.", XRC(31,58,1), XRB_MASK,    PPC64,          { RA, RS } },
2434
2435 { "andc",    XRC(31,60,0), X_MASK,      COM,    { RA, RS, RB } },
2436 { "andc.",   XRC(31,60,1), X_MASK,      COM,    { RA, RS, RB } },
2437
2438 { "tdlgt",   XTO(31,68,TOLGT), XTO_MASK, PPC64,         { RA, RB } },
2439 { "tdllt",   XTO(31,68,TOLLT), XTO_MASK, PPC64,         { RA, RB } },
2440 { "tdeq",    XTO(31,68,TOEQ), XTO_MASK,  PPC64,         { RA, RB } },
2441 { "tdlge",   XTO(31,68,TOLGE), XTO_MASK, PPC64,         { RA, RB } },
2442 { "tdlnl",   XTO(31,68,TOLNL), XTO_MASK, PPC64,         { RA, RB } },
2443 { "tdlle",   XTO(31,68,TOLLE), XTO_MASK, PPC64,         { RA, RB } },
2444 { "tdlng",   XTO(31,68,TOLNG), XTO_MASK, PPC64,         { RA, RB } },
2445 { "tdgt",    XTO(31,68,TOGT), XTO_MASK,  PPC64,         { RA, RB } },
2446 { "tdge",    XTO(31,68,TOGE), XTO_MASK,  PPC64,         { RA, RB } },
2447 { "tdnl",    XTO(31,68,TONL), XTO_MASK,  PPC64,         { RA, RB } },
2448 { "tdlt",    XTO(31,68,TOLT), XTO_MASK,  PPC64,         { RA, RB } },
2449 { "tdle",    XTO(31,68,TOLE), XTO_MASK,  PPC64,         { RA, RB } },
2450 { "tdng",    XTO(31,68,TONG), XTO_MASK,  PPC64,         { RA, RB } },
2451 { "tdne",    XTO(31,68,TONE), XTO_MASK,  PPC64,         { RA, RB } },
2452 { "td",      X(31,68),  X_MASK,          PPC64,         { TO, RA, RB } },
2453
2454 { "mulhd",   XO(31,73,0,0), XO_MASK,     PPC64,         { RT, RA, RB } },
2455 { "mulhd.",  XO(31,73,0,1), XO_MASK,     PPC64,         { RT, RA, RB } },
2456
2457 { "mulhw",   XO(31,75,0,0), XO_MASK,    PPC,            { RT, RA, RB } },
2458 { "mulhw.",  XO(31,75,0,1), XO_MASK,    PPC,            { RT, RA, RB } },
2459
2460 { "mtsrd",   X(31,82),  XRB_MASK|(1<<20), PPC64,        { SR, RS } },
2461
2462 { "mfmsr",   X(31,83),  XRARB_MASK,     COM,            { RT } },
2463
2464 { "ldarx",   X(31,84),  X_MASK,         PPC64,          { RT, RA, RB } },
2465
2466 { "dcbf",    X(31,86),  XRT_MASK,       PPC,            { RA, RB } },
2467
2468 { "lbzx",    X(31,87),  X_MASK,         COM,            { RT, RA, RB } },
2469
2470 { "neg",     XO(31,104,0,0), XORB_MASK, COM,            { RT, RA } },
2471 { "neg.",    XO(31,104,0,1), XORB_MASK, COM,            { RT, RA } },
2472 { "nego",    XO(31,104,1,0), XORB_MASK, COM,            { RT, RA } },
2473 { "nego.",   XO(31,104,1,1), XORB_MASK, COM,            { RT, RA } },
2474
2475 { "mul",     XO(31,107,0,0), XO_MASK,   M601,           { RT, RA, RB } },
2476 { "mul.",    XO(31,107,0,1), XO_MASK,   M601,           { RT, RA, RB } },
2477 { "mulo",    XO(31,107,1,0), XO_MASK,   M601,           { RT, RA, RB } },
2478 { "mulo.",   XO(31,107,1,1), XO_MASK,   M601,           { RT, RA, RB } },
2479
2480 { "mtsrdin", X(31,114), XRA_MASK,       PPC64,          { RS, RB } },
2481
2482 { "clf",     X(31,118), XRB_MASK,       POWER,          { RT, RA } },
2483
2484 { "lbzux",   X(31,119), X_MASK,         COM,            { RT, RAL, RB } },
2485
2486 { "not",     XRC(31,124,0), X_MASK,     COM,            { RA, RS, RBS } },
2487 { "nor",     XRC(31,124,0), X_MASK,     COM,            { RA, RS, RB } },
2488 { "not.",    XRC(31,124,1), X_MASK,     COM,            { RA, RS, RBS } },
2489 { "nor.",    XRC(31,124,1), X_MASK,     COM,            { RA, RS, RB } },
2490
2491 { "wrtee",   X(31,131), XRARB_MASK,     PPC403,         { RS } },
2492
2493 { "subfe",   XO(31,136,0,0), XO_MASK,   PPCCOM,         { RT, RA, RB } },
2494 { "sfe",     XO(31,136,0,0), XO_MASK,   PWRCOM,         { RT, RA, RB } },
2495 { "subfe.",  XO(31,136,0,1), XO_MASK,   PPCCOM,         { RT, RA, RB } },
2496 { "sfe.",    XO(31,136,0,1), XO_MASK,   PWRCOM,         { RT, RA, RB } },
2497 { "subfeo",  XO(31,136,1,0), XO_MASK,   PPCCOM,         { RT, RA, RB } },
2498 { "sfeo",    XO(31,136,1,0), XO_MASK,   PWRCOM,         { RT, RA, RB } },
2499 { "subfeo.", XO(31,136,1,1), XO_MASK,   PPCCOM,         { RT, RA, RB } },
2500 { "sfeo.",   XO(31,136,1,1), XO_MASK,   PWRCOM,         { RT, RA, RB } },
2501
2502 { "adde",    XO(31,138,0,0), XO_MASK,   PPCCOM,         { RT, RA, RB } },
2503 { "ae",      XO(31,138,0,0), XO_MASK,   PWRCOM,         { RT, RA, RB } },
2504 { "adde.",   XO(31,138,0,1), XO_MASK,   PPCCOM,         { RT, RA, RB } },
2505 { "ae.",     XO(31,138,0,1), XO_MASK,   PWRCOM,         { RT, RA, RB } },
2506 { "addeo",   XO(31,138,1,0), XO_MASK,   PPCCOM,         { RT, RA, RB } },
2507 { "aeo",     XO(31,138,1,0), XO_MASK,   PWRCOM,         { RT, RA, RB } },
2508 { "addeo.",  XO(31,138,1,1), XO_MASK,   PPCCOM,         { RT, RA, RB } },
2509 { "aeo.",    XO(31,138,1,1), XO_MASK,   PWRCOM,         { RT, RA, RB } },
2510
2511 { "mtcr",    XFXM(31,144,0xff), XFXFXM_MASK|FXM_MASK, COM,      { RS }},
2512 { "mtcrf",   X(31,144), XFXFXM_MASK,    COM,            { FXM, RS } },
2513
2514 { "mtmsr",   X(31,146), XRARB_MASK,     COM,            { RS } },
2515
2516 { "stdx",    X(31,149), X_MASK,         PPC64,          { RS, RA, RB } },
2517
2518 { "stwcx.",  XRC(31,150,1), X_MASK,     PPC,            { RS, RA, RB } },
2519
2520 { "stwx",    X(31,151), X_MASK,         PPCCOM,         { RS, RA, RB } },
2521 { "stx",     X(31,151), X_MASK,         PWRCOM,         { RS, RA, RB } },
2522
2523 { "slq",     XRC(31,152,0), X_MASK,     M601,           { RA, RS, RB } },
2524 { "slq.",    XRC(31,152,1), X_MASK,     M601,           { RA, RS, RB } },
2525
2526 { "sle",     XRC(31,153,0), X_MASK,     M601,           { RA, RS, RB } },
2527 { "sle.",    XRC(31,153,1), X_MASK,     M601,           { RA, RS, RB } },
2528
2529 { "wrteei",  X(31,163), XE_MASK,        PPC403,         { E } },
2530
2531 { "mtmsrd",  X(31,178), XRARB_MASK,     PPC64,          { RS } },
2532
2533 { "stdux",   X(31,181), X_MASK,         PPC64,          { RS, RAS, RB } },
2534
2535 { "stwux",   X(31,183), X_MASK,         PPCCOM,         { RS, RAS, RB } },
2536 { "stux",    X(31,183), X_MASK,         PWRCOM,         { RS, RA, RB } },
2537
2538 { "sliq",    XRC(31,184,0), X_MASK,     M601,           { RA, RS, SH } },
2539 { "sliq.",   XRC(31,184,1), X_MASK,     M601,           { RA, RS, SH } },
2540
2541 { "subfze",  XO(31,200,0,0), XORB_MASK, PPCCOM,         { RT, RA } },
2542 { "sfze",    XO(31,200,0,0), XORB_MASK, PWRCOM,         { RT, RA } },
2543 { "subfze.", XO(31,200,0,1), XORB_MASK, PPCCOM,         { RT, RA } },
2544 { "sfze.",   XO(31,200,0,1), XORB_MASK, PWRCOM,         { RT, RA } },
2545 { "subfzeo", XO(31,200,1,0), XORB_MASK, PPCCOM,         { RT, RA } },
2546 { "sfzeo",   XO(31,200,1,0), XORB_MASK, PWRCOM,         { RT, RA } },
2547 { "subfzeo.",XO(31,200,1,1), XORB_MASK, PPCCOM,         { RT, RA } },
2548 { "sfzeo.",  XO(31,200,1,1), XORB_MASK, PWRCOM,         { RT, RA } },
2549
2550 { "addze",   XO(31,202,0,0), XORB_MASK, PPCCOM,         { RT, RA } },
2551 { "aze",     XO(31,202,0,0), XORB_MASK, PWRCOM,         { RT, RA } },
2552 { "addze.",  XO(31,202,0,1), XORB_MASK, PPCCOM,         { RT, RA } },
2553 { "aze.",    XO(31,202,0,1), XORB_MASK, PWRCOM,         { RT, RA } },
2554 { "addzeo",  XO(31,202,1,0), XORB_MASK, PPCCOM,         { RT, RA } },
2555 { "azeo",    XO(31,202,1,0), XORB_MASK, PWRCOM,         { RT, RA } },
2556 { "addzeo.", XO(31,202,1,1), XORB_MASK, PPCCOM,         { RT, RA } },
2557 { "azeo.",   XO(31,202,1,1), XORB_MASK, PWRCOM,         { RT, RA } },
2558
2559 { "mtsr",    X(31,210), XRB_MASK|(1<<20), COM32,        { SR, RS } },
2560
2561 { "stdcx.",  XRC(31,214,1), X_MASK,     PPC64,          { RS, RA, RB } },
2562
2563 { "stbx",    X(31,215), X_MASK,         COM,    { RS, RA, RB } },
2564
2565 { "sllq",    XRC(31,216,0), X_MASK,     M601,           { RA, RS, RB } },
2566 { "sllq.",   XRC(31,216,1), X_MASK,     M601,           { RA, RS, RB } },
2567
2568 { "sleq",    XRC(31,217,0), X_MASK,     M601,           { RA, RS, RB } },
2569 { "sleq.",   XRC(31,217,1), X_MASK,     M601,           { RA, RS, RB } },
2570
2571 { "subfme",  XO(31,232,0,0), XORB_MASK, PPCCOM,         { RT, RA } },
2572 { "sfme",    XO(31,232,0,0), XORB_MASK, PWRCOM,         { RT, RA } },
2573 { "subfme.", XO(31,232,0,1), XORB_MASK, PPCCOM,         { RT, RA } },
2574 { "sfme.",   XO(31,232,0,1), XORB_MASK, PWRCOM,         { RT, RA } },
2575 { "subfmeo", XO(31,232,1,0), XORB_MASK, PPCCOM,         { RT, RA } },
2576 { "sfmeo",   XO(31,232,1,0), XORB_MASK, PWRCOM,         { RT, RA } },
2577 { "subfmeo.",XO(31,232,1,1), XORB_MASK, PPCCOM,         { RT, RA } },
2578 { "sfmeo.",  XO(31,232,1,1), XORB_MASK, PWRCOM,         { RT, RA } },
2579
2580 { "mulld",   XO(31,233,0,0), XO_MASK,   PPC64,          { RT, RA, RB } },
2581 { "mulld.",  XO(31,233,0,1), XO_MASK,   PPC64,          { RT, RA, RB } },
2582 { "mulldo",  XO(31,233,1,0), XO_MASK,   PPC64,          { RT, RA, RB } },
2583 { "mulldo.", XO(31,233,1,1), XO_MASK,   PPC64,          { RT, RA, RB } },
2584
2585 { "addme",   XO(31,234,0,0), XORB_MASK, PPCCOM,         { RT, RA } },
2586 { "ame",     XO(31,234,0,0), XORB_MASK, PWRCOM,         { RT, RA } },
2587 { "addme.",  XO(31,234,0,1), XORB_MASK, PPCCOM,         { RT, RA } },
2588 { "ame.",    XO(31,234,0,1), XORB_MASK, PWRCOM,         { RT, RA } },
2589 { "addmeo",  XO(31,234,1,0), XORB_MASK, PPCCOM,         { RT, RA } },
2590 { "ameo",    XO(31,234,1,0), XORB_MASK, PWRCOM,         { RT, RA } },
2591 { "addmeo.", XO(31,234,1,1), XORB_MASK, PPCCOM,         { RT, RA } },
2592 { "ameo.",   XO(31,234,1,1), XORB_MASK, PWRCOM,         { RT, RA } },
2593
2594 { "mullw",   XO(31,235,0,0), XO_MASK,   PPCCOM,         { RT, RA, RB } },
2595 { "muls",    XO(31,235,0,0), XO_MASK,   PWRCOM,         { RT, RA, RB } },
2596 { "mullw.",  XO(31,235,0,1), XO_MASK,   PPCCOM,         { RT, RA, RB } },
2597 { "muls.",   XO(31,235,0,1), XO_MASK,   PWRCOM,         { RT, RA, RB } },
2598 { "mullwo",  XO(31,235,1,0), XO_MASK,   PPCCOM,         { RT, RA, RB } },
2599 { "mulso",   XO(31,235,1,0), XO_MASK,   PWRCOM,         { RT, RA, RB } },
2600 { "mullwo.", XO(31,235,1,1), XO_MASK,   PPCCOM,         { RT, RA, RB } },
2601 { "mulso.",  XO(31,235,1,1), XO_MASK,   PWRCOM,         { RT, RA, RB } },
2602
2603 { "mtsrin",  X(31,242), XRA_MASK,       PPC32,          { RS, RB } },
2604 { "mtsri",   X(31,242), XRA_MASK,       POWER32,        { RS, RB } },
2605
2606 { "dcbtst",  X(31,246), XRT_MASK,       PPC,            { RA, RB } },
2607
2608 { "stbux",   X(31,247), X_MASK,         COM,            { RS, RAS, RB } },
2609
2610 { "slliq",   XRC(31,248,0), X_MASK,     M601,           { RA, RS, SH } },
2611 { "slliq.",  XRC(31,248,1), X_MASK,     M601,           { RA, RS, SH } },
2612
2613 { "doz",     XO(31,264,0,0), XO_MASK,   M601,           { RT, RA, RB } },
2614 { "doz.",    XO(31,264,0,1), XO_MASK,   M601,           { RT, RA, RB } },
2615 { "dozo",    XO(31,264,1,0), XO_MASK,   M601,           { RT, RA, RB } },
2616 { "dozo.",   XO(31,264,1,1), XO_MASK,   M601,           { RT, RA, RB } },
2617
2618 { "add",     XO(31,266,0,0), XO_MASK,   PPCCOM,         { RT, RA, RB } },
2619 { "cax",     XO(31,266,0,0), XO_MASK,   PWRCOM,         { RT, RA, RB } },
2620 { "add.",    XO(31,266,0,1), XO_MASK,   PPCCOM,         { RT, RA, RB } },
2621 { "cax.",    XO(31,266,0,1), XO_MASK,   PWRCOM,         { RT, RA, RB } },
2622 { "addo",    XO(31,266,1,0), XO_MASK,   PPCCOM,         { RT, RA, RB } },
2623 { "caxo",    XO(31,266,1,0), XO_MASK,   PWRCOM,         { RT, RA, RB } },
2624 { "addo.",   XO(31,266,1,1), XO_MASK,   PPCCOM,         { RT, RA, RB } },
2625 { "caxo.",   XO(31,266,1,1), XO_MASK,   PWRCOM,         { RT, RA, RB } },
2626
2627 { "lscbx",   XRC(31,277,0), X_MASK,     M601,           { RT, RA, RB } },
2628 { "lscbx.",  XRC(31,277,1), X_MASK,     M601,           { RT, RA, RB } },
2629
2630 { "dcbt",    X(31,278), XRT_MASK,       PPC,            { RA, RB } },
2631
2632 { "lhzx",    X(31,279), X_MASK,         COM,            { RT, RA, RB } },
2633
2634 { "icbt",    X(31,262), XRT_MASK,       PPC403,         { RA, RB } },
2635
2636 { "eqv",     XRC(31,284,0), X_MASK,     COM,            { RA, RS, RB } },
2637 { "eqv.",    XRC(31,284,1), X_MASK,     COM,            { RA, RS, RB } },
2638
2639 { "tlbie",   X(31,306), XRTRA_MASK,     PPC,            { RB } },
2640 { "tlbi",    X(31,306), XRT_MASK,       POWER,          { RA, RB } },
2641
2642 { "eciwx",   X(31,310), X_MASK,         PPC,            { RT, RA, RB } },
2643
2644 { "lhzux",   X(31,311), X_MASK,         COM,            { RT, RAL, RB } },
2645
2646 { "xor",     XRC(31,316,0), X_MASK,     COM,            { RA, RS, RB } },
2647 { "xor.",    XRC(31,316,1), X_MASK,     COM,            { RA, RS, RB } },
2648
2649 { "mfexisr", XSPR(31,323,64), XSPR_MASK, PPC403,        { RT } },
2650 { "mfexier", XSPR(31,323,66), XSPR_MASK, PPC403,        { RT } },
2651 { "mfbr0",   XSPR(31,323,128), XSPR_MASK, PPC403,       { RT } },
2652 { "mfbr1",   XSPR(31,323,129), XSPR_MASK, PPC403,       { RT } },
2653 { "mfbr2",   XSPR(31,323,130), XSPR_MASK, PPC403,       { RT } },
2654 { "mfbr3",   XSPR(31,323,131), XSPR_MASK, PPC403,       { RT } },
2655 { "mfbr4",   XSPR(31,323,132), XSPR_MASK, PPC403,       { RT } },
2656 { "mfbr5",   XSPR(31,323,133), XSPR_MASK, PPC403,       { RT } },
2657 { "mfbr6",   XSPR(31,323,134), XSPR_MASK, PPC403,       { RT } },
2658 { "mfbr7",   XSPR(31,323,135), XSPR_MASK, PPC403,       { RT } },
2659 { "mfbear",  XSPR(31,323,144), XSPR_MASK, PPC403,       { RT } },
2660 { "mfbesr",  XSPR(31,323,145), XSPR_MASK, PPC403,       { RT } },
2661 { "mfiocr",  XSPR(31,323,160), XSPR_MASK, PPC403,       { RT } },
2662 { "mfdmacr0", XSPR(31,323,192), XSPR_MASK, PPC403,      { RT } },
2663 { "mfdmact0", XSPR(31,323,193), XSPR_MASK, PPC403,      { RT } },
2664 { "mfdmada0", XSPR(31,323,194), XSPR_MASK, PPC403,      { RT } },
2665 { "mfdmasa0", XSPR(31,323,195), XSPR_MASK, PPC403,      { RT } },
2666 { "mfdmacc0", XSPR(31,323,196), XSPR_MASK, PPC403,      { RT } },
2667 { "mfdmacr1", XSPR(31,323,200), XSPR_MASK, PPC403,      { RT } },
2668 { "mfdmact1", XSPR(31,323,201), XSPR_MASK, PPC403,      { RT } },
2669 { "mfdmada1", XSPR(31,323,202), XSPR_MASK, PPC403,      { RT } },
2670 { "mfdmasa1", XSPR(31,323,203), XSPR_MASK, PPC403,      { RT } },
2671 { "mfdmacc1", XSPR(31,323,204), XSPR_MASK, PPC403,      { RT } },
2672 { "mfdmacr2", XSPR(31,323,208), XSPR_MASK, PPC403,      { RT } },
2673 { "mfdmact2", XSPR(31,323,209), XSPR_MASK, PPC403,      { RT } },
2674 { "mfdmada2", XSPR(31,323,210), XSPR_MASK, PPC403,      { RT } },
2675 { "mfdmasa2", XSPR(31,323,211), XSPR_MASK, PPC403,      { RT } },
2676 { "mfdmacc2", XSPR(31,323,212), XSPR_MASK, PPC403,      { RT } },
2677 { "mfdmacr3", XSPR(31,323,216), XSPR_MASK, PPC403,      { RT } },
2678 { "mfdmact3", XSPR(31,323,217), XSPR_MASK, PPC403,      { RT } },
2679 { "mfdmada3", XSPR(31,323,218), XSPR_MASK, PPC403,      { RT } },
2680 { "mfdmasa3", XSPR(31,323,219), XSPR_MASK, PPC403,      { RT } },
2681 { "mfdmacc3", XSPR(31,323,220), XSPR_MASK, PPC403,      { RT } },
2682 { "mfdmasr", XSPR(31,323,224), XSPR_MASK, PPC403,       { RT } },
2683 { "mfdcr",   X(31,323), X_MASK,         PPC403,         { RT, SPR } },
2684
2685 { "div",     XO(31,331,0,0), XO_MASK,   M601,           { RT, RA, RB } },
2686 { "div.",    XO(31,331,0,1), XO_MASK,   M601,           { RT, RA, RB } },
2687 { "divo",    XO(31,331,1,0), XO_MASK,   M601,           { RT, RA, RB } },
2688 { "divo.",   XO(31,331,1,1), XO_MASK,   M601,           { RT, RA, RB } },
2689
2690 { "mfmq",     XSPR(31,339,0),   XSPR_MASK, M601,        { RT } },
2691 { "mfxer",    XSPR(31,339,1),   XSPR_MASK, COM,         { RT } },
2692 { "mfrtcu",   XSPR(31,339,4),   XSPR_MASK, COM,         { RT } },
2693 { "mfrtcl",   XSPR(31,339,5),   XSPR_MASK, COM,         { RT } },
2694 { "mfdec",    XSPR(31,339,6),   XSPR_MASK, MFDEC1,      { RT } },
2695 { "mflr",     XSPR(31,339,8),   XSPR_MASK, COM,         { RT } },
2696 { "mfctr",    XSPR(31,339,9),   XSPR_MASK, COM,         { RT } },
2697 { "mftid",    XSPR(31,339,17),  XSPR_MASK, POWER,       { RT } },
2698 { "mfdsisr",  XSPR(31,339,18),  XSPR_MASK, COM,         { RT } },
2699 { "mfdar",    XSPR(31,339,19),  XSPR_MASK, COM,         { RT } },
2700 { "mfdec",    XSPR(31,339,22),  XSPR_MASK, MFDEC2,      { RT } },
2701 { "mfsdr0",   XSPR(31,339,24),  XSPR_MASK, POWER,       { RT } },
2702 { "mfsdr1",   XSPR(31,339,25),  XSPR_MASK, COM,         { RT } },
2703 { "mfsrr0",   XSPR(31,339,26),  XSPR_MASK, COM,         { RT } },
2704 { "mfsrr1",   XSPR(31,339,27),  XSPR_MASK, COM,         { RT } },
2705 { "mfcmpa",   XSPR(31,339,144), XSPR_MASK, PPC860,      { RT } },
2706 { "mfcmpb",   XSPR(31,339,145), XSPR_MASK, PPC860,      { RT } },
2707 { "mfcmpc",   XSPR(31,339,146), XSPR_MASK, PPC860,      { RT } },
2708 { "mfcmpd",   XSPR(31,339,147), XSPR_MASK, PPC860,      { RT } },
2709 { "mficr",    XSPR(31,339,148), XSPR_MASK, PPC860,      { RT } },
2710 { "mfder",    XSPR(31,339,149), XSPR_MASK, PPC860,      { RT } },
2711 { "mfcounta", XSPR(31,339,150), XSPR_MASK, PPC860,      { RT } },
2712 { "mfcountb", XSPR(31,339,151), XSPR_MASK, PPC860,      { RT } },
2713 { "mfcmpe",   XSPR(31,339,152), XSPR_MASK, PPC860,      { RT } },
2714 { "mfcmpf",   XSPR(31,339,153), XSPR_MASK, PPC860,      { RT } },
2715 { "mfcmpg",   XSPR(31,339,154), XSPR_MASK, PPC860,      { RT } },
2716 { "mfcmph",   XSPR(31,339,155), XSPR_MASK, PPC860,      { RT } },
2717 { "mflctrl1", XSPR(31,339,156), XSPR_MASK, PPC860,      { RT } },
2718 { "mflctrl2", XSPR(31,339,157), XSPR_MASK, PPC860,      { RT } },
2719 { "mfictrl",  XSPR(31,339,158), XSPR_MASK, PPC860,      { RT } },
2720 { "mfbar",    XSPR(31,339,159), XSPR_MASK, PPC860,      { RT } },
2721 { "mfsprg4",  XSPR(31,339,260), XSPR_MASK, PPC405,      { RT } },
2722 { "mfsprg5",  XSPR(31,339,261), XSPR_MASK, PPC405,      { RT } },
2723 { "mfsprg6",  XSPR(31,339,262), XSPR_MASK, PPC405,      { RT } },
2724 { "mfsprg7",  XSPR(31,339,263), XSPR_MASK, PPC405,      { RT } },
2725 { "mfsprg",   XSPR(31,339,272), XSPRG_MASK, PPC,        { RT, SPRG } },
2726 { "mfsprg0",  XSPR(31,339,272), XSPR_MASK, PPC,         { RT } },
2727 { "mfsprg1",  XSPR(31,339,273), XSPR_MASK, PPC,         { RT } },
2728 { "mfsprg2",  XSPR(31,339,274), XSPR_MASK, PPC,         { RT } },
2729 { "mfsprg3",  XSPR(31,339,275), XSPR_MASK, PPC,         { RT } },
2730 { "mfasr",    XSPR(31,339,280), XSPR_MASK, PPC64,       { RT } },
2731 { "mfear",    XSPR(31,339,282), XSPR_MASK, PPC,         { RT } },
2732 { "mfpvr",    XSPR(31,339,287), XSPR_MASK, PPC,         { RT } },
2733 { "mfibatu",  XSPR(31,339,528), XSPRBAT_MASK, PPC,      { RT, SPRBAT } },
2734 { "mfibatl",  XSPR(31,339,529), XSPRBAT_MASK, PPC,      { RT, SPRBAT } },
2735 { "mfdbatu",  XSPR(31,339,536), XSPRBAT_MASK, PPC,      { RT, SPRBAT } },
2736 { "mfdbatl",  XSPR(31,339,537), XSPRBAT_MASK, PPC,      { RT, SPRBAT } },
2737 { "mfic_cst", XSPR(31,339,560), XSPR_MASK, PPC860,      { RT } },
2738 { "mfic_adr", XSPR(31,339,561), XSPR_MASK, PPC860,      { RT } },
2739 { "mfic_dat", XSPR(31,339,562), XSPR_MASK, PPC860,      { RT } },
2740 { "mfdc_cst", XSPR(31,339,568), XSPR_MASK, PPC860,      { RT } },
2741 { "mfdc_adr", XSPR(31,339,569), XSPR_MASK, PPC860,      { RT } },
2742 { "mfdc_dat", XSPR(31,339,570), XSPR_MASK, PPC860,      { RT } },
2743 { "mfdpdr",   XSPR(31,339,630), XSPR_MASK, PPC860,      { RT } },
2744 { "mfdpir",   XSPR(31,339,631), XSPR_MASK, PPC860,      { RT } },
2745 { "mfimmr",   XSPR(31,339,638), XSPR_MASK, PPC860,      { RT } },
2746 { "mfmi_ctr", XSPR(31,339,784), XSPR_MASK, PPC860,      { RT } },
2747 { "mfmi_ap",  XSPR(31,339,786), XSPR_MASK, PPC860,      { RT } },
2748 { "mfmi_epn", XSPR(31,339,787), XSPR_MASK, PPC860,      { RT } },
2749 { "mfmi_twc", XSPR(31,339,789), XSPR_MASK, PPC860,      { RT } },
2750 { "mfmi_rpn", XSPR(31,339,790), XSPR_MASK, PPC860,      { RT } },
2751 { "mfmd_ctr", XSPR(31,339,792), XSPR_MASK, PPC860,      { RT } },
2752 { "mfm_casid",XSPR(31,339,793), XSPR_MASK, PPC860,      { RT } },
2753 { "mfmd_ap",  XSPR(31,339,794), XSPR_MASK, PPC860,      { RT } },
2754 { "mfmd_epn", XSPR(31,339,795), XSPR_MASK, PPC860,      { RT } },
2755 { "mfmd_twb", XSPR(31,339,796), XSPR_MASK, PPC860,      { RT } },
2756 { "mfmd_twc", XSPR(31,339,797), XSPR_MASK, PPC860,      { RT } },
2757 { "mfmd_rpn", XSPR(31,339,798), XSPR_MASK, PPC860,      { RT } },
2758 { "mfm_tw",   XSPR(31,339,799), XSPR_MASK, PPC860,      { RT } },
2759 { "mfmi_dbcam",XSPR(31,339,816), XSPR_MASK, PPC860,     { RT } },
2760 { "mfmi_dbram0",XSPR(31,339,817), XSPR_MASK, PPC860,    { RT } },
2761 { "mfmi_dbram1",XSPR(31,339,818), XSPR_MASK, PPC860,    { RT } },
2762 { "mfmd_dbcam", XSPR(31,339,824), XSPR_MASK, PPC860,    { RT } },
2763 { "mfmd_dbram0",XSPR(31,339,825), XSPR_MASK, PPC860,    { RT } },
2764 { "mfmd_dbram1",XSPR(31,339,826), XSPR_MASK, PPC860,    { RT } },
2765 { "mfzpr",      XSPR(31,339,944), XSPR_MASK, PPC403,    { RT } },
2766 { "mfpid",      XSPR(31,339,945), XSPR_MASK, PPC403,    { RT } },
2767 { "mfccr0",     XSPR(31,339,947), XSPR_MASK, PPC405,    { RT } },
2768 { "mficdbdr",   XSPR(31,339,979), XSPR_MASK, PPC403,    { RT } },
2769 { "mfummcr0",   XSPR(31,339,936),  XSPR_MASK, PPC750,   { RT } },
2770 { "mfupmc1",    XSPR(31,339,937),  XSPR_MASK, PPC750,   { RT } },
2771 { "mfupmc2",    XSPR(31,339,938),  XSPR_MASK, PPC750,   { RT } },
2772 { "mfusia",     XSPR(31,339,939),  XSPR_MASK, PPC750,   { RT } },
2773 { "mfummcr1",   XSPR(31,339,940),  XSPR_MASK, PPC750,   { RT } },
2774 { "mfupmc3",    XSPR(31,339,941),  XSPR_MASK, PPC750,   { RT } },
2775 { "mfupmc4",    XSPR(31,339,942),  XSPR_MASK, PPC750,   { RT } },
2776 { "mfiac3",     XSPR(31,339,948),  XSPR_MASK, PPC405,   { RT } },
2777 { "mfiac4",     XSPR(31,339,949),  XSPR_MASK, PPC405,   { RT } },
2778 { "mfdvc1",     XSPR(31,339,950),  XSPR_MASK, PPC405,   { RT } },
2779 { "mfdvc2",     XSPR(31,339,951),  XSPR_MASK, PPC405,   { RT } },
2780 { "mfmmcr0",    XSPR(31,339,952),  XSPR_MASK, PPC750,   { RT } },
2781 { "mfpmc1",     XSPR(31,339,953),  XSPR_MASK, PPC750,   { RT } },
2782 { "mfsgr",      XSPR(31,339,953),  XSPR_MASK, PPC403,   { RT } },
2783 { "mfpmc2",     XSPR(31,339,954),  XSPR_MASK, PPC750,   { RT } },
2784 { "mfdcwr",     XSPR(31,339,954),  XSPR_MASK, PPC403,   { RT } },
2785 { "mfsia",      XSPR(31,339,955),  XSPR_MASK, PPC750,   { RT } },
2786 { "mfsler",     XSPR(31,339,955),  XSPR_MASK, PPC405,   { RT } },
2787 { "mfmmcr1",    XSPR(31,339,956),  XSPR_MASK, PPC750,   { RT } },
2788 { "mfsu0r",     XSPR(31,339,956),  XSPR_MASK, PPC405,   { RT } },
2789 { "mfpmc3",     XSPR(31,339,957),  XSPR_MASK, PPC750,   { RT } },
2790 { "mfdbcr1",    XSPR(31,339,957),  XSPR_MASK, PPC405,   { RT } },
2791 { "mfpmc4",     XSPR(31,339,958),  XSPR_MASK, PPC750,   { RT } },
2792 { "mfesr",   XSPR(31,339,980), XSPR_MASK, PPC403,       { RT } },
2793 { "mfdear",  XSPR(31,339,981), XSPR_MASK, PPC403,       { RT } },
2794 { "mfevpr",  XSPR(31,339,982), XSPR_MASK, PPC403,       { RT } },
2795 { "mfcdbcr", XSPR(31,339,983), XSPR_MASK, PPC403,       { RT } },
2796 { "mftsr",   XSPR(31,339,984), XSPR_MASK, PPC403,       { RT } },
2797 { "mftcr",   XSPR(31,339,986), XSPR_MASK, PPC403,       { RT } },
2798 { "mfpit",   XSPR(31,339,987), XSPR_MASK, PPC403,       { RT } },
2799 { "mftbhi",  XSPR(31,339,988), XSPR_MASK, PPC403,       { RT } },
2800 { "mftblo",  XSPR(31,339,989), XSPR_MASK, PPC403,       { RT } },
2801 { "mfsrr2",  XSPR(31,339,990), XSPR_MASK, PPC403,       { RT } },
2802 { "mfsrr3",  XSPR(31,339,991), XSPR_MASK, PPC403,       { RT } },
2803 { "mfdbsr",  XSPR(31,339,1008), XSPR_MASK, PPC403,      { RT } },
2804 { "mfdbcr0", XSPR(31,339,1010), XSPR_MASK, PPC405,      { RT } },
2805 { "mfiac1",  XSPR(31,339,1012), XSPR_MASK, PPC403,      { RT } },
2806 { "mfiac2",  XSPR(31,339,1013), XSPR_MASK, PPC403,      { RT } },
2807 { "mfdac1",  XSPR(31,339,1014), XSPR_MASK, PPC403,      { RT } },
2808 { "mfdac2",  XSPR(31,339,1015), XSPR_MASK, PPC403,      { RT } },
2809 { "mfdccr",  XSPR(31,339,1018), XSPR_MASK, PPC403,      { RT } },
2810 { "mficcr",  XSPR(31,339,1019), XSPR_MASK, PPC403,      { RT } },
2811 { "mfpbl1",  XSPR(31,339,1020), XSPR_MASK, PPC403,      { RT } },
2812 { "mfpbu1",  XSPR(31,339,1021), XSPR_MASK, PPC403,      { RT } },
2813 { "mfpbl2",  XSPR(31,339,1022), XSPR_MASK, PPC403,      { RT } },
2814 { "mfpbu2",  XSPR(31,339,1023), XSPR_MASK, PPC403,      { RT } },
2815 { "mfl2cr",     XSPR(31,339,1017), XSPR_MASK, PPC750,   { RT } },
2816 { "mfictc",     XSPR(31,339,1019), XSPR_MASK, PPC750,   { RT } },
2817 { "mfthrm1",    XSPR(31,339,1020), XSPR_MASK, PPC750,   { RT } },
2818 { "mfthrm2",    XSPR(31,339,1021), XSPR_MASK, PPC750,   { RT } },
2819 { "mfthrm3",    XSPR(31,339,1022), XSPR_MASK, PPC750,   { RT } },
2820 { "mfspr",   X(31,339), X_MASK,         COM,            { RT, SPR } },
2821
2822 { "lwax",    X(31,341), X_MASK,         PPC64,          { RT, RA, RB } },
2823
2824 { "lhax",    X(31,343), X_MASK,         COM,            { RT, RA, RB } },
2825
2826 { "dccci",   X(31,454), XRT_MASK,       PPC403,         { RA, RB } },
2827
2828 { "abs",     XO(31,360,0,0), XORB_MASK, M601,           { RT, RA } },
2829 { "abs.",    XO(31,360,0,1), XORB_MASK, M601,           { RT, RA } },
2830 { "abso",    XO(31,360,1,0), XORB_MASK, M601,           { RT, RA } },
2831 { "abso.",   XO(31,360,1,1), XORB_MASK, M601,           { RT, RA } },
2832
2833 { "divs",    XO(31,363,0,0), XO_MASK,   M601,           { RT, RA, RB } },
2834 { "divs.",   XO(31,363,0,1), XO_MASK,   M601,           { RT, RA, RB } },
2835 { "divso",   XO(31,363,1,0), XO_MASK,   M601,           { RT, RA, RB } },
2836 { "divso.",  XO(31,363,1,1), XO_MASK,   M601,           { RT, RA, RB } },
2837
2838 { "tlbia",   X(31,370), 0xffffffff,     PPC,            { 0 } },
2839
2840 { "mftbl",   XSPR(31,371,268), XSPR_MASK, PPC,          { RT } },
2841 { "mftbu",   XSPR(31,371,269), XSPR_MASK, PPC,          { RT } },
2842 { "mftb",    X(31,371), X_MASK,         PPC,            { RT, TBR } },
2843
2844 { "lwaux",   X(31,373), X_MASK,         PPC64,          { RT, RAL, RB } },
2845
2846 { "lhaux",   X(31,375), X_MASK,         COM,            { RT, RAL, RB } },
2847
2848 { "sthx",    X(31,407), X_MASK,         COM,            { RS, RA, RB } },
2849
2850 { "lfqx",    X(31,791), X_MASK,         POWER2,         { FRT, RA, RB } },
2851
2852 { "lfqux",   X(31,823), X_MASK,         POWER2,         { FRT, RA, RB } },
2853
2854 { "stfqx",   X(31,919), X_MASK,         POWER2,         { FRS, RA, RB } },
2855
2856 { "stfqux",  X(31,951), X_MASK,         POWER2,         { FRS, RA, RB } },
2857
2858 { "orc",     XRC(31,412,0), X_MASK,     COM,            { RA, RS, RB } },
2859 { "orc.",    XRC(31,412,1), X_MASK,     COM,            { RA, RS, RB } },
2860
2861 { "sradi",   XS(31,413,0), XS_MASK,     PPC64,          { RA, RS, SH6 } },
2862 { "sradi.",  XS(31,413,1), XS_MASK,     PPC64,          { RA, RS, SH6 } },
2863
2864 { "slbie",   X(31,434), XRTRA_MASK,     PPC64,          { RB } },
2865
2866 { "ecowx",   X(31,438), X_MASK,         PPC,            { RT, RA, RB } },
2867
2868 { "sthux",   X(31,439), X_MASK,         COM,            { RS, RAS, RB } },
2869
2870 { "mr",      XRC(31,444,0), X_MASK,     COM,            { RA, RS, RBS } },
2871 { "or",      XRC(31,444,0), X_MASK,     COM,            { RA, RS, RB } },
2872 { "mr.",     XRC(31,444,1), X_MASK,     COM,            { RA, RS, RBS } },
2873 { "or.",     XRC(31,444,1), X_MASK,     COM,            { RA, RS, RB } },
2874
2875 { "mtexisr", XSPR(31,451,64), XSPR_MASK, PPC403,        { RT } },
2876 { "mtexier", XSPR(31,451,66), XSPR_MASK, PPC403,        { RT } },
2877 { "mtbr0",   XSPR(31,451,128), XSPR_MASK, PPC403,       { RT } },
2878 { "mtbr1",   XSPR(31,451,129), XSPR_MASK, PPC403,       { RT } },
2879 { "mtbr2",   XSPR(31,451,130), XSPR_MASK, PPC403,       { RT } },
2880 { "mtbr3",   XSPR(31,451,131), XSPR_MASK, PPC403,       { RT } },
2881 { "mtbr4",   XSPR(31,451,132), XSPR_MASK, PPC403,       { RT } },
2882 { "mtbr5",   XSPR(31,451,133), XSPR_MASK, PPC403,       { RT } },
2883 { "mtbr6",   XSPR(31,451,134), XSPR_MASK, PPC403,       { RT } },
2884 { "mtbr7",   XSPR(31,451,135), XSPR_MASK, PPC403,       { RT } },
2885 { "mtbear",  XSPR(31,451,144), XSPR_MASK, PPC403,       { RT } },
2886 { "mtbesr",  XSPR(31,451,145), XSPR_MASK, PPC403,       { RT } },
2887 { "mtiocr",  XSPR(31,451,160), XSPR_MASK, PPC403,       { RT } },
2888 { "mtdmacr0", XSPR(31,451,192), XSPR_MASK, PPC403,      { RT } },
2889 { "mtdmact0", XSPR(31,451,193), XSPR_MASK, PPC403,      { RT } },
2890 { "mtdmada0", XSPR(31,451,194), XSPR_MASK, PPC403,      { RT } },
2891 { "mtdmasa0", XSPR(31,451,195), XSPR_MASK, PPC403,      { RT } },
2892 { "mtdmacc0", XSPR(31,451,196), XSPR_MASK, PPC403,      { RT } },
2893 { "mtdmacr1", XSPR(31,451,200), XSPR_MASK, PPC403,      { RT } },
2894 { "mtdmact1", XSPR(31,451,201), XSPR_MASK, PPC403,      { RT } },
2895 { "mtdmada1", XSPR(31,451,202), XSPR_MASK, PPC403,      { RT } },
2896 { "mtdmasa1", XSPR(31,451,203), XSPR_MASK, PPC403,      { RT } },
2897 { "mtdmacc1", XSPR(31,451,204), XSPR_MASK, PPC403,      { RT } },
2898 { "mtdmacr2", XSPR(31,451,208), XSPR_MASK, PPC403,      { RT } },
2899 { "mtdmact2", XSPR(31,451,209), XSPR_MASK, PPC403,      { RT } },
2900 { "mtdmada2", XSPR(31,451,210), XSPR_MASK, PPC403,      { RT } },
2901 { "mtdmasa2", XSPR(31,451,211), XSPR_MASK, PPC403,      { RT } },
2902 { "mtdmacc2", XSPR(31,451,212), XSPR_MASK, PPC403,      { RT } },
2903 { "mtdmacr3", XSPR(31,451,216), XSPR_MASK, PPC403,      { RT } },
2904 { "mtdmact3", XSPR(31,451,217), XSPR_MASK, PPC403,      { RT } },
2905 { "mtdmada3", XSPR(31,451,218), XSPR_MASK, PPC403,      { RT } },
2906 { "mtdmasa3", XSPR(31,451,219), XSPR_MASK, PPC403,      { RT } },
2907 { "mtdmacc3", XSPR(31,451,220), XSPR_MASK, PPC403,      { RT } },
2908 { "mtdmasr", XSPR(31,451,224), XSPR_MASK, PPC403,       { RT } },
2909 { "mtummcr0",   XSPR(31,451,936),  XSPR_MASK, PPC750,   { RT } },
2910 { "mtupmc1",    XSPR(31,451,937),  XSPR_MASK, PPC750,   { RT } },
2911 { "mtupmc2",    XSPR(31,451,938),  XSPR_MASK, PPC750,   { RT } },
2912 { "mtusia",     XSPR(31,451,939),  XSPR_MASK, PPC750,   { RT } },
2913 { "mtummcr1",   XSPR(31,451,940),  XSPR_MASK, PPC750,   { RT } },
2914 { "mtupmc3",    XSPR(31,451,941),  XSPR_MASK, PPC750,   { RT } },
2915 { "mtupmc4",    XSPR(31,451,942),  XSPR_MASK, PPC750,   { RT } },
2916 { "mtmmcr0",    XSPR(31,451,952),  XSPR_MASK, PPC750,   { RT } },
2917 { "mtpmc1",     XSPR(31,451,953),  XSPR_MASK, PPC750,   { RT } },
2918 { "mtpmc2",     XSPR(31,451,954),  XSPR_MASK, PPC750,   { RT } },
2919 { "mtsia",      XSPR(31,451,955),  XSPR_MASK, PPC750,   { RT } },
2920 { "mtmmcr1",    XSPR(31,451,956),  XSPR_MASK, PPC750,   { RT } },
2921 { "mtpmc3",     XSPR(31,451,957),  XSPR_MASK, PPC750,   { RT } },
2922 { "mtpmc4",     XSPR(31,451,958),  XSPR_MASK, PPC750,   { RT } },
2923 { "mtl2cr",     XSPR(31,451,1017), XSPR_MASK, PPC750,   { RT } },
2924 { "mtictc",     XSPR(31,451,1019), XSPR_MASK, PPC750,   { RT } },
2925 { "mtthrm1",    XSPR(31,451,1020), XSPR_MASK, PPC750,   { RT } },
2926 { "mtthrm2",    XSPR(31,451,1021), XSPR_MASK, PPC750,   { RT } },
2927 { "mtthrm3",    XSPR(31,451,1022), XSPR_MASK, PPC750,   { RT } },
2928 { "mtdcr",   X(31,451), X_MASK,         PPC403,         { SPR, RS } },
2929
2930 { "divdu",   XO(31,457,0,0), XO_MASK,   PPC64,          { RT, RA, RB } },
2931 { "divdu.",  XO(31,457,0,1), XO_MASK,   PPC64,          { RT, RA, RB } },
2932 { "divduo",  XO(31,457,1,0), XO_MASK,   PPC64,          { RT, RA, RB } },
2933 { "divduo.", XO(31,457,1,1), XO_MASK,   PPC64,          { RT, RA, RB } },
2934
2935 { "divwu",   XO(31,459,0,0), XO_MASK,   PPC,            { RT, RA, RB } },
2936 { "divwu.",  XO(31,459,0,1), XO_MASK,   PPC,            { RT, RA, RB } },
2937 { "divwuo",  XO(31,459,1,0), XO_MASK,   PPC,            { RT, RA, RB } },
2938 { "divwuo.", XO(31,459,1,1), XO_MASK,   PPC,            { RT, RA, RB } },
2939
2940 { "mtmq",    XSPR(31,467,0),   XSPR_MASK,    M601,      { RS } },
2941 { "mtxer",   XSPR(31,467,1),   XSPR_MASK,    COM,       { RS } },
2942 { "mtlr",    XSPR(31,467,8),   XSPR_MASK,    COM,       { RS } },
2943 { "mtctr",   XSPR(31,467,9),   XSPR_MASK,    COM,       { RS } },
2944 { "mttid",   XSPR(31,467,17),  XSPR_MASK,    POWER,     { RS } },
2945 { "mtdsisr", XSPR(31,467,18),  XSPR_MASK,    COM,       { RS } },
2946 { "mtdar",   XSPR(31,467,19),  XSPR_MASK,    COM,       { RS } },
2947 { "mtrtcu",  XSPR(31,467,20),  XSPR_MASK,    COM,       { RS } },
2948 { "mtrtcl",  XSPR(31,467,21),  XSPR_MASK,    COM,       { RS } },
2949 { "mtdec",   XSPR(31,467,22),  XSPR_MASK,    COM,       { RS } },
2950 { "mtsdr0",  XSPR(31,467,24),  XSPR_MASK,    POWER,     { RS } },
2951 { "mtsdr1",  XSPR(31,467,25),  XSPR_MASK,    COM,       { RS } },
2952 { "mtsrr0",  XSPR(31,467,26),  XSPR_MASK,    COM,       { RS } },
2953 { "mtsrr1",  XSPR(31,467,27),  XSPR_MASK,    COM,       { RS } },
2954 { "mtcmpa",   XSPR(31,467,144), XSPR_MASK, PPC860,      { RT } },
2955 { "mtcmpb",   XSPR(31,467,145), XSPR_MASK, PPC860,      { RT } },
2956 { "mtcmpc",   XSPR(31,467,146), XSPR_MASK, PPC860,      { RT } },
2957 { "mtcmpd",   XSPR(31,467,147), XSPR_MASK, PPC860,      { RT } },
2958 { "mticr",    XSPR(31,467,148), XSPR_MASK, PPC860,      { RT } },
2959 { "mtder",    XSPR(31,467,149), XSPR_MASK, PPC860,      { RT } },
2960 { "mtcounta", XSPR(31,467,150), XSPR_MASK, PPC860,      { RT } },
2961 { "mtcountb", XSPR(31,467,151), XSPR_MASK, PPC860,      { RT } },
2962 { "mtcmpe",   XSPR(31,467,152), XSPR_MASK, PPC860,      { RT } },
2963 { "mtcmpf",   XSPR(31,467,153), XSPR_MASK, PPC860,      { RT } },
2964 { "mtcmpg",   XSPR(31,467,154), XSPR_MASK, PPC860,      { RT } },
2965 { "mtcmph",   XSPR(31,467,155), XSPR_MASK, PPC860,      { RT } },
2966 { "mtlctrl1", XSPR(31,467,156), XSPR_MASK, PPC860,      { RT } },
2967 { "mtlctrl2", XSPR(31,467,157), XSPR_MASK, PPC860,      { RT } },
2968 { "mtictrl",  XSPR(31,467,158), XSPR_MASK, PPC860,      { RT } },
2969 { "mtbar",    XSPR(31,467,159), XSPR_MASK, PPC860,      { RT } },
2970 { "mtsprg",  XSPR(31,467,272), XSPRG_MASK,   PPC,       { SPRG, RS } },
2971 { "mtsprg0", XSPR(31,467,272), XSPR_MASK,    PPC,       { RT } },
2972 { "mtsprg1", XSPR(31,467,273), XSPR_MASK,    PPC,       { RT } },
2973 { "mtsprg2", XSPR(31,467,274), XSPR_MASK,    PPC,       { RT } },
2974 { "mtsprg3", XSPR(31,467,275), XSPR_MASK,    PPC,       { RT } },
2975 { "mtsprg4", XSPR(31,467,276), XSPR_MASK,    PPC405,    { RT } },
2976 { "mtsprg5", XSPR(31,467,277), XSPR_MASK,    PPC405,    { RT } },
2977 { "mtsprg6", XSPR(31,467,278), XSPR_MASK,    PPC405,    { RT } },
2978 { "mtsprg7", XSPR(31,467,279), XSPR_MASK,    PPC405,    { RT } },
2979 { "mtasr",   XSPR(31,467,280), XSPR_MASK,    PPC64,     { RS } },
2980 { "mtear",   XSPR(31,467,282), XSPR_MASK,    PPC,       { RS } },
2981 { "mttbl",   XSPR(31,467,284), XSPR_MASK,    PPC,       { RS } },
2982 { "mttbu",   XSPR(31,467,285), XSPR_MASK,    PPC,       { RS } },
2983 { "mtibatu", XSPR(31,467,528), XSPRBAT_MASK, PPC,       { SPRBAT, RS } },
2984 { "mtibatl", XSPR(31,467,529), XSPRBAT_MASK, PPC,       { SPRBAT, RS } },
2985 { "mtdbatu", XSPR(31,467,536), XSPRBAT_MASK, PPC,       { SPRBAT, RS } },
2986 { "mtdbatl", XSPR(31,467,537), XSPRBAT_MASK, PPC,       { SPRBAT, RS } },
2987 { "mtzpr",   XSPR(31,467,944), XSPR_MASK, PPC403,       { RT } },
2988 { "mtpid",   XSPR(31,467,945), XSPR_MASK, PPC403,       { RT } },
2989 { "mtccr0",  XSPR(31,467,947), XSPR_MASK, PPC405,       { RT } },
2990 { "mtiac3",  XSPR(31,467,948), XSPR_MASK, PPC405,       { RT } },
2991 { "mtiac4",  XSPR(31,467,949), XSPR_MASK, PPC405,       { RT } },
2992 { "mtdvc1",  XSPR(31,467,950), XSPR_MASK, PPC405,       { RT } },
2993 { "mtdvc2",  XSPR(31,467,951), XSPR_MASK, PPC405,       { RT } },
2994 { "mtsgr",   XSPR(31,467,953), XSPR_MASK, PPC403,       { RT } },
2995 { "mtdcwr",  XSPR(31,467,954), XSPR_MASK, PPC403,       { RT } },
2996 { "mtsler",  XSPR(31,467,955), XSPR_MASK, PPC405,       { RT } },
2997 { "mtsu0r",  XSPR(31,467,956), XSPR_MASK, PPC405,       { RT } },
2998 { "mtdbcr1", XSPR(31,467,957), XSPR_MASK, PPC405,       { RT } },
2999 { "mticdbdr",XSPR(31,467,979), XSPR_MASK, PPC403,       { RT } },
3000 { "mtesr",   XSPR(31,467,980), XSPR_MASK, PPC403,       { RT } },
3001 { "mtdear",  XSPR(31,467,981), XSPR_MASK, PPC403,       { RT } },
3002 { "mtevpr",  XSPR(31,467,982), XSPR_MASK, PPC403,       { RT } },
3003 { "mtcdbcr", XSPR(31,467,983), XSPR_MASK, PPC403,       { RT } },
3004 { "mttsr",   XSPR(31,467,984), XSPR_MASK, PPC403,       { RT } },
3005 { "mttcr",   XSPR(31,467,986), XSPR_MASK, PPC403,       { RT } },
3006 { "mtpit",   XSPR(31,467,987), XSPR_MASK, PPC403,       { RT } },
3007 { "mttbhi",  XSPR(31,467,988), XSPR_MASK, PPC403,       { RT } },
3008 { "mttblo",  XSPR(31,467,989), XSPR_MASK, PPC403,       { RT } },
3009 { "mtsrr2",  XSPR(31,467,990), XSPR_MASK, PPC403,       { RT } },
3010 { "mtsrr3",  XSPR(31,467,991), XSPR_MASK, PPC403,       { RT } },
3011 { "mtdbsr",  XSPR(31,467,1008), XSPR_MASK, PPC403,      { RT } },
3012 { "mtdbcr0", XSPR(31,467,1010), XSPR_MASK, PPC405,      { RT } },
3013 { "mtiac1",  XSPR(31,467,1012), XSPR_MASK, PPC403,      { RT } },
3014 { "mtiac2",  XSPR(31,467,1013), XSPR_MASK, PPC403,      { RT } },
3015 { "mtdac1",  XSPR(31,467,1014), XSPR_MASK, PPC403,      { RT } },
3016 { "mtdac2",  XSPR(31,467,1015), XSPR_MASK, PPC403,      { RT } },
3017 { "mtdccr",  XSPR(31,467,1018), XSPR_MASK, PPC403,      { RT } },
3018 { "mticcr",  XSPR(31,467,1019), XSPR_MASK, PPC403,      { RT } },
3019 { "mtpbl1",  XSPR(31,467,1020), XSPR_MASK, PPC403,      { RT } },
3020 { "mtpbu1",  XSPR(31,467,1021), XSPR_MASK, PPC403,      { RT } },
3021 { "mtpbl2",  XSPR(31,467,1022), XSPR_MASK, PPC403,      { RT } },
3022 { "mtpbu2",  XSPR(31,467,1023), XSPR_MASK, PPC403,      { RT } },
3023 { "mtspr",   X(31,467),        X_MASK,       COM,       { SPR, RS } },
3024
3025 { "dcbi",    X(31,470), XRT_MASK,       PPC,            { RA, RB } },
3026
3027 { "nand",    XRC(31,476,0), X_MASK,     COM,            { RA, RS, RB } },
3028 { "nand.",   XRC(31,476,1), X_MASK,     COM,            { RA, RS, RB } },
3029
3030 { "dcread",  X(31,486), X_MASK,         PPC403,         { RT, RA, RB }},
3031
3032 { "nabs",    XO(31,488,0,0), XORB_MASK, M601,           { RT, RA } },
3033 { "nabs.",   XO(31,488,0,1), XORB_MASK, M601,           { RT, RA } },
3034 { "nabso",   XO(31,488,1,0), XORB_MASK, M601,           { RT, RA } },
3035 { "nabso.",  XO(31,488,1,1), XORB_MASK, M601,           { RT, RA } },
3036
3037 { "divd",    XO(31,489,0,0), XO_MASK,   PPC64,          { RT, RA, RB } },
3038 { "divd.",   XO(31,489,0,1), XO_MASK,   PPC64,          { RT, RA, RB } },
3039 { "divdo",   XO(31,489,1,0), XO_MASK,   PPC64,          { RT, RA, RB } },
3040 { "divdo.",  XO(31,489,1,1), XO_MASK,   PPC64,          { RT, RA, RB } },
3041
3042 { "divw",    XO(31,491,0,0), XO_MASK,   PPC,            { RT, RA, RB } },
3043 { "divw.",   XO(31,491,0,1), XO_MASK,   PPC,            { RT, RA, RB } },
3044 { "divwo",   XO(31,491,1,0), XO_MASK,   PPC,            { RT, RA, RB } },
3045 { "divwo.",  XO(31,491,1,1), XO_MASK,   PPC,            { RT, RA, RB } },
3046
3047 { "slbia",   X(31,498), 0xffffffff,     PPC64,          { 0 } },
3048
3049 { "cli",     X(31,502), XRB_MASK,       POWER,          { RT, RA } },
3050
3051 { "mcrxr",   X(31,512), XRARB_MASK|(3<<21), COM,        { BF } },
3052
3053 { "clcs",    X(31,531), XRB_MASK,       M601,           { RT, RA } },
3054
3055 { "lswx",    X(31,533), X_MASK,         PPCCOM,         { RT, RA, RB } },
3056 { "lsx",     X(31,533), X_MASK,         PWRCOM,         { RT, RA, RB } },
3057
3058 { "lwbrx",   X(31,534), X_MASK,         PPCCOM,         { RT, RA, RB } },
3059 { "lbrx",    X(31,534), X_MASK,         PWRCOM,         { RT, RA, RB } },
3060
3061 { "lfsx",    X(31,535), X_MASK,         COM,            { FRT, RA, RB } },
3062
3063 { "srw",     XRC(31,536,0), X_MASK,     PPCCOM,         { RA, RS, RB } },
3064 { "sr",      XRC(31,536,0), X_MASK,     PWRCOM,         { RA, RS, RB } },
3065 { "srw.",    XRC(31,536,1), X_MASK,     PPCCOM,         { RA, RS, RB } },
3066 { "sr.",     XRC(31,536,1), X_MASK,     PWRCOM,         { RA, RS, RB } },
3067
3068 { "rrib",    XRC(31,537,0), X_MASK,     M601,           { RA, RS, RB } },
3069 { "rrib.",   XRC(31,537,1), X_MASK,     M601,           { RA, RS, RB } },
3070
3071 { "srd",     XRC(31,539,0), X_MASK,     PPC64,          { RA, RS, RB } },
3072 { "srd.",    XRC(31,539,1), X_MASK,     PPC64,          { RA, RS, RB } },
3073
3074 { "maskir",  XRC(31,541,0), X_MASK,     M601,           { RA, RS, RB } },
3075 { "maskir.", XRC(31,541,1), X_MASK,     M601,           { RA, RS, RB } },
3076
3077 { "tlbsync", X(31,566), 0xffffffff,     PPC,            { 0 } },
3078
3079 { "lfsux",   X(31,567), X_MASK,         COM,            { FRT, RAS, RB } },
3080
3081 { "mfsr",    X(31,595), XRB_MASK|(1<<20), COM32,        { RT, SR } },
3082
3083 { "lswi",    X(31,597), X_MASK,         PPCCOM,         { RT, RA, NB } },
3084 { "lsi",     X(31,597), X_MASK,         PWRCOM,         { RT, RA, NB } },
3085
3086 { "sync",    X(31,598), 0xffffffff,     PPCCOM,         { 0 } },
3087 { "dcs",     X(31,598), 0xffffffff,     PWRCOM,         { 0 } },
3088
3089 { "lfdx",    X(31,599), X_MASK,         COM,            { FRT, RA, RB } },
3090
3091 { "mfsri",   X(31,627), X_MASK,         PWRCOM,         { RT, RA, RB } },
3092
3093 { "dclst",   X(31,630), XRB_MASK,       PWRCOM,         { RS, RA } },
3094
3095 { "lfdux",   X(31,631), X_MASK,         COM,            { FRT, RAS, RB } },
3096
3097 { "mfsrin",  X(31,659), XRA_MASK,       PPC32,          { RT, RB } },
3098
3099 { "stswx",   X(31,661), X_MASK,         PPCCOM,         { RS, RA, RB } },
3100 { "stsx",    X(31,661), X_MASK,         PWRCOM,         { RS, RA, RB } },
3101
3102 { "stwbrx",  X(31,662), X_MASK,         PPCCOM,         { RS, RA, RB } },
3103 { "stbrx",   X(31,662), X_MASK,         PWRCOM,         { RS, RA, RB } },
3104
3105 { "stfsx",   X(31,663), X_MASK,         COM,            { FRS, RA, RB } },
3106
3107 { "srq",     XRC(31,664,0), X_MASK,     M601,           { RA, RS, RB } },
3108 { "srq.",    XRC(31,664,1), X_MASK,     M601,           { RA, RS, RB } },
3109
3110 { "sre",     XRC(31,665,0), X_MASK,     M601,           { RA, RS, RB } },
3111 { "sre.",    XRC(31,665,1), X_MASK,     M601,           { RA, RS, RB } },
3112
3113 { "stfsux",  X(31,695), X_MASK,         COM,            { FRS, RAS, RB } },
3114
3115 { "sriq",    XRC(31,696,0), X_MASK,     M601,           { RA, RS, SH } },
3116 { "sriq.",   XRC(31,696,1), X_MASK,     M601,           { RA, RS, SH } },
3117
3118 { "stswi",   X(31,725), X_MASK,         PPCCOM,         { RS, RA, NB } },
3119 { "stsi",    X(31,725), X_MASK,         PWRCOM,         { RS, RA, NB } },
3120
3121 { "stfdx",   X(31,727), X_MASK,         COM,            { FRS, RA, RB } },
3122
3123 { "srlq",    XRC(31,728,0), X_MASK,     M601,           { RA, RS, RB } },
3124 { "srlq.",   XRC(31,728,1), X_MASK,     M601,           { RA, RS, RB } },
3125
3126 { "sreq",    XRC(31,729,0), X_MASK,     M601,           { RA, RS, RB } },
3127 { "sreq.",   XRC(31,729,1), X_MASK,     M601,           { RA, RS, RB } },
3128
3129 { "dcba",    X(31,758), XRT_MASK,       PPC405,         { RA, RB } },
3130
3131 { "stfdux",  X(31,759), X_MASK,         COM,            { FRS, RAS, RB } },
3132
3133 { "srliq",   XRC(31,760,0), X_MASK,     M601,           { RA, RS, SH } },
3134 { "srliq.",  XRC(31,760,1), X_MASK,     M601,           { RA, RS, SH } },
3135
3136 { "lhbrx",   X(31,790), X_MASK,         COM,            { RT, RA, RB } },
3137
3138 { "sraw",    XRC(31,792,0), X_MASK,     PPCCOM,         { RA, RS, RB } },
3139 { "sra",     XRC(31,792,0), X_MASK,     PWRCOM,         { RA, RS, RB } },
3140 { "sraw.",   XRC(31,792,1), X_MASK,     PPCCOM,         { RA, RS, RB } },
3141 { "sra.",    XRC(31,792,1), X_MASK,     PWRCOM,         { RA, RS, RB } },
3142
3143 { "srad",    XRC(31,794,0), X_MASK,     PPC64,          { RA, RS, RB } },
3144 { "srad.",   XRC(31,794,1), X_MASK,     PPC64,          { RA, RS, RB } },
3145
3146 { "rac",     X(31,818), X_MASK,         PWRCOM,         { RT, RA, RB } },
3147
3148 { "srawi",   XRC(31,824,0), X_MASK,     PPCCOM,         { RA, RS, SH } },
3149 { "srai",    XRC(31,824,0), X_MASK,     PWRCOM,         { RA, RS, SH } },
3150 { "srawi.",  XRC(31,824,1), X_MASK,     PPCCOM,         { RA, RS, SH } },
3151 { "srai.",   XRC(31,824,1), X_MASK,     PWRCOM,         { RA, RS, SH } },
3152
3153 { "eieio",   X(31,854), 0xffffffff,     PPC,            { 0 } },
3154
3155 { "tlbsx",   XRC(31,914,0), X_MASK, PPC403,     { RT, RA, RB } },
3156 { "tlbsx.",  XRC(31,914,1), X_MASK, PPC403,     { RT, RA, RB } },
3157
3158 { "sthbrx",  X(31,918), X_MASK,         COM,            { RS, RA, RB } },
3159
3160 { "sraq",    XRC(31,920,0), X_MASK,     M601,           { RA, RS, RB } },
3161 { "sraq.",   XRC(31,920,1), X_MASK,     M601,           { RA, RS, RB } },
3162
3163 { "srea",    XRC(31,921,0), X_MASK,     M601,           { RA, RS, RB } },
3164 { "srea.",   XRC(31,921,1), X_MASK,     M601,           { RA, RS, RB } },
3165
3166 { "extsh",   XRC(31,922,0), XRB_MASK,   PPCCOM,         { RA, RS } },
3167 { "exts",    XRC(31,922,0), XRB_MASK,   PWRCOM,         { RA, RS } },
3168 { "extsh.",  XRC(31,922,1), XRB_MASK,   PPCCOM,         { RA, RS } },
3169 { "exts.",   XRC(31,922,1), XRB_MASK,   PWRCOM,         { RA, RS } },
3170
3171 { "tlbrehi", XTLB(31,946,0), XTLB_MASK, PPC403,         { RT, RA } },
3172 { "tlbrelo", XTLB(31,946,1), XTLB_MASK, PPC403,         { RT, RA } },
3173 { "tlbre",   X(31,946), X_MASK,         PPC403,         { RT, RA, SH } },
3174
3175 { "sraiq",   XRC(31,952,0), X_MASK,     M601,           { RA, RS, SH } },
3176 { "sraiq.",  XRC(31,952,1), X_MASK,     M601,           { RA, RS, SH } },
3177
3178 { "extsb",   XRC(31,954,0), XRB_MASK,   PPC,            { RA, RS} },
3179 { "extsb.",  XRC(31,954,1), XRB_MASK,   PPC,            { RA, RS} },
3180
3181 { "iccci",   X(31,966), XRT_MASK,       PPC403,         { RA, RB } },
3182
3183 { "tlbld",   X(31,978), XRTRA_MASK,     PPC,            { RB } },
3184
3185 { "tlbwehi", XTLB(31,978,0), XTLB_MASK, PPC403,         { RT, RA } },
3186 { "tlbwelo", XTLB(31,978,1), XTLB_MASK, PPC403,         { RT, RA } },
3187 { "tlbwe",   X(31,978), X_MASK,         PPC403,         { RS, RA, SH } },
3188
3189 { "icbi",    X(31,982), XRT_MASK,       PPC,            { RA, RB } },
3190
3191 { "stfiwx",  X(31,983), X_MASK,         PPC,            { FRS, RA, RB } },
3192
3193 { "extsw",   XRC(31,986,0), XRB_MASK,   PPC,            { RA, RS } },
3194 { "extsw.",  XRC(31,986,1), XRB_MASK,   PPC,            { RA, RS } },
3195
3196 { "icread",  X(31,998), XRT_MASK,       PPC403,         { RA, RB } },
3197
3198 { "tlbli",   X(31,1010), XRTRA_MASK,    PPC,            { RB } },
3199
3200 { "dcbz",    X(31,1014), XRT_MASK,      PPC,            { RA, RB } },
3201 { "dclz",    X(31,1014), XRT_MASK,      PPC,            { RA, RB } },
3202
3203 { "lvebx",   X(31,   7), X_MASK,        PPCVEC,         { VD, RA, RB } },
3204 { "lvehx",   X(31,  39), X_MASK,        PPCVEC,         { VD, RA, RB } },
3205 { "lvewx",   X(31,  71), X_MASK,        PPCVEC,         { VD, RA, RB } },
3206 { "lvsl",    X(31,   6), X_MASK,        PPCVEC,         { VD, RA, RB } },
3207 { "lvsr",    X(31,  38), X_MASK,        PPCVEC,         { VD, RA, RB } },
3208 { "lvx",     X(31, 103), X_MASK,        PPCVEC,         { VD, RA, RB } },
3209 { "lvxl",    X(31, 359), X_MASK,        PPCVEC,         { VD, RA, RB } },
3210 { "stvebx",  X(31, 135), X_MASK,        PPCVEC,         { VS, RA, RB } },
3211 { "stvehx",  X(31, 167), X_MASK,        PPCVEC,         { VS, RA, RB } },
3212 { "stvewx",  X(31, 199), X_MASK,        PPCVEC,         { VS, RA, RB } },
3213 { "stvx",    X(31, 231), X_MASK,        PPCVEC,         { VS, RA, RB } },
3214 { "stvxl",   X(31, 487), X_MASK,        PPCVEC,         { VS, RA, RB } },
3215
3216 { "lwz",     OP(32),    OP_MASK,        PPCCOM,         { RT, D, RA } },
3217 { "l",       OP(32),    OP_MASK,        PWRCOM,         { RT, D, RA } },
3218
3219 { "lwzu",    OP(33),    OP_MASK,        PPCCOM,         { RT, D, RAL } },
3220 { "lu",      OP(33),    OP_MASK,        PWRCOM,         { RT, D, RA } },
3221
3222 { "lbz",     OP(34),    OP_MASK,        COM,            { RT, D, RA } },
3223
3224 { "lbzu",    OP(35),    OP_MASK,        COM,            { RT, D, RAL } },
3225
3226 { "stw",     OP(36),    OP_MASK,        PPCCOM,         { RS, D, RA } },
3227 { "st",      OP(36),    OP_MASK,        PWRCOM,         { RS, D, RA } },
3228
3229 { "stwu",    OP(37),    OP_MASK,        PPCCOM,         { RS, D, RAS } },
3230 { "stu",     OP(37),    OP_MASK,        PWRCOM,         { RS, D, RA } },
3231
3232 { "stb",     OP(38),    OP_MASK,        COM,            { RS, D, RA } },
3233
3234 { "stbu",    OP(39),    OP_MASK,        COM,            { RS, D, RAS } },
3235
3236 { "lhz",     OP(40),    OP_MASK,        COM,            { RT, D, RA } },
3237
3238 { "lhzu",    OP(41),    OP_MASK,        COM,            { RT, D, RAL } },
3239
3240 { "lha",     OP(42),    OP_MASK,        COM,            { RT, D, RA } },
3241
3242 { "lhau",    OP(43),    OP_MASK,        COM,            { RT, D, RAL } },
3243
3244 { "sth",     OP(44),    OP_MASK,        COM,            { RS, D, RA } },
3245
3246 { "sthu",    OP(45),    OP_MASK,        COM,            { RS, D, RAS } },
3247
3248 { "lmw",     OP(46),    OP_MASK,        PPCCOM,         { RT, D, RAM } },
3249 { "lm",      OP(46),    OP_MASK,        PWRCOM,         { RT, D, RA } },
3250
3251 { "stmw",    OP(47),    OP_MASK,        PPCCOM,         { RS, D, RA } },
3252 { "stm",     OP(47),    OP_MASK,        PWRCOM,         { RS, D, RA } },
3253
3254 { "lfs",     OP(48),    OP_MASK,        COM,            { FRT, D, RA } },
3255
3256 { "lfsu",    OP(49),    OP_MASK,        COM,            { FRT, D, RAS } },
3257
3258 { "lfd",     OP(50),    OP_MASK,        COM,            { FRT, D, RA } },
3259
3260 { "lfdu",    OP(51),    OP_MASK,        COM,            { FRT, D, RAS } },
3261
3262 { "stfs",    OP(52),    OP_MASK,        COM,            { FRS, D, RA } },
3263
3264 { "stfsu",   OP(53),    OP_MASK,        COM,            { FRS, D, RAS } },
3265
3266 { "stfd",    OP(54),    OP_MASK,        COM,            { FRS, D, RA } },
3267
3268 { "stfdu",   OP(55),    OP_MASK,        COM,            { FRS, D, RAS } },
3269
3270 { "lfq",     OP(56),    OP_MASK,        POWER2,         { FRT, D, RA } },
3271
3272 { "lfqu",    OP(57),    OP_MASK,        POWER2,         { FRT, D, RA } },
3273
3274 { "ld",      DSO(58,0), DS_MASK,        PPC64,          { RT, DS, RA } },
3275
3276 { "ldu",     DSO(58,1), DS_MASK,        PPC64,          { RT, DS, RAL } },
3277
3278 { "lwa",     DSO(58,2), DS_MASK,        PPC64,          { RT, DS, RA } },
3279
3280 { "fdivs",   A(59,18,0), AFRC_MASK,     PPC,            { FRT, FRA, FRB } },
3281 { "fdivs.",  A(59,18,1), AFRC_MASK,     PPC,            { FRT, FRA, FRB } },
3282
3283 { "fsubs",   A(59,20,0), AFRC_MASK,     PPC,            { FRT, FRA, FRB } },
3284 { "fsubs.",  A(59,20,1), AFRC_MASK,     PPC,            { FRT, FRA, FRB } },
3285
3286 { "fadds",   A(59,21,0), AFRC_MASK,     PPC,            { FRT, FRA, FRB } },
3287 { "fadds.",  A(59,21,1), AFRC_MASK,     PPC,            { FRT, FRA, FRB } },
3288
3289 { "fsqrts",  A(59,22,0), AFRAFRC_MASK,  PPC,            { FRT, FRB } },
3290 { "fsqrts.", A(59,22,1), AFRAFRC_MASK,  PPC,            { FRT, FRB } },
3291
3292 { "fres",    A(59,24,0), AFRAFRC_MASK,  PPC,            { FRT, FRB } },
3293 { "fres.",   A(59,24,1), AFRAFRC_MASK,  PPC,            { FRT, FRB } },
3294
3295 { "fmuls",   A(59,25,0), AFRB_MASK,     PPC,            { FRT, FRA, FRC } },
3296 { "fmuls.",  A(59,25,1), AFRB_MASK,     PPC,            { FRT, FRA, FRC } },
3297
3298 { "fmsubs",  A(59,28,0), A_MASK,        PPC,            { FRT,FRA,FRC,FRB } },
3299 { "fmsubs.", A(59,28,1), A_MASK,        PPC,            { FRT,FRA,FRC,FRB } },
3300
3301 { "fmadds",  A(59,29,0), A_MASK,        PPC,            { FRT,FRA,FRC,FRB } },
3302 { "fmadds.", A(59,29,1), A_MASK,        PPC,            { FRT,FRA,FRC,FRB } },
3303
3304 { "fnmsubs", A(59,30,0), A_MASK,        PPC,            { FRT,FRA,FRC,FRB } },
3305 { "fnmsubs.",A(59,30,1), A_MASK,        PPC,            { FRT,FRA,FRC,FRB } },
3306
3307 { "fnmadds", A(59,31,0), A_MASK,        PPC,            { FRT,FRA,FRC,FRB } },
3308 { "fnmadds.",A(59,31,1), A_MASK,        PPC,            { FRT,FRA,FRC,FRB } },
3309
3310 { "stfq",    OP(60),    OP_MASK,        POWER2,         { FRS, D, RA } },
3311
3312 { "stfqu",   OP(61),    OP_MASK,        POWER2,         { FRS, D, RA } },
3313
3314 { "std",     DSO(62,0), DS_MASK,        PPC64,          { RS, DS, RA } },
3315
3316 { "stdu",    DSO(62,1), DS_MASK,        PPC64,          { RS, DS, RAS } },
3317
3318 { "fcmpu",   X(63,0),   X_MASK|(3<<21), COM,            { BF, FRA, FRB } },
3319
3320 { "frsp",    XRC(63,12,0), XRA_MASK,    COM,            { FRT, FRB } },
3321 { "frsp.",   XRC(63,12,1), XRA_MASK,    COM,            { FRT, FRB } },
3322
3323 { "fctiw",   XRC(63,14,0), XRA_MASK,    PPCCOM,         { FRT, FRB } },
3324 { "fcir",    XRC(63,14,0), XRA_MASK,    POWER2,         { FRT, FRB } },
3325 { "fctiw.",  XRC(63,14,1), XRA_MASK,    PPCCOM,         { FRT, FRB } },
3326 { "fcir.",   XRC(63,14,1), XRA_MASK,    POWER2,         { FRT, FRB } },
3327
3328 { "fctiwz",  XRC(63,15,0), XRA_MASK,    PPCCOM,         { FRT, FRB } },
3329 { "fcirz",   XRC(63,15,0), XRA_MASK,    POWER2,         { FRT, FRB } },
3330 { "fctiwz.", XRC(63,15,1), XRA_MASK,    PPCCOM,         { FRT, FRB } },
3331 { "fcirz.",  XRC(63,15,1), XRA_MASK,    POWER2,         { FRT, FRB } },
3332
3333 { "fdiv",    A(63,18,0), AFRC_MASK,     PPCCOM,         { FRT, FRA, FRB } },
3334 { "fd",      A(63,18,0), AFRC_MASK,     PWRCOM,         { FRT, FRA, FRB } },
3335 { "fdiv.",   A(63,18,1), AFRC_MASK,     PPCCOM,         { FRT, FRA, FRB } },
3336 { "fd.",     A(63,18,1), AFRC_MASK,     PWRCOM,         { FRT, FRA, FRB } },
3337
3338 { "fsub",    A(63,20,0), AFRC_MASK,     PPCCOM,         { FRT, FRA, FRB } },
3339 { "fs",      A(63,20,0), AFRC_MASK,     PWRCOM,         { FRT, FRA, FRB } },
3340 { "fsub.",   A(63,20,1), AFRC_MASK,     PPCCOM,         { FRT, FRA, FRB } },
3341 { "fs.",     A(63,20,1), AFRC_MASK,     PWRCOM,         { FRT, FRA, FRB } },
3342
3343 { "fadd",    A(63,21,0), AFRC_MASK,     PPCCOM,         { FRT, FRA, FRB } },
3344 { "fa",      A(63,21,0), AFRC_MASK,     PWRCOM,         { FRT, FRA, FRB } },
3345 { "fadd.",   A(63,21,1), AFRC_MASK,     PPCCOM,         { FRT, FRA, FRB } },
3346 { "fa.",     A(63,21,1), AFRC_MASK,     PWRCOM,         { FRT, FRA, FRB } },
3347
3348 { "fsqrt",   A(63,22,0), AFRAFRC_MASK,  PPCPWR2,        { FRT, FRB } },
3349 { "fsqrt.",  A(63,22,1), AFRAFRC_MASK,  PPCPWR2,        { FRT, FRB } },
3350
3351 { "fsel",    A(63,23,0), A_MASK,        PPC,            { FRT,FRA,FRC,FRB } },
3352 { "fsel.",   A(63,23,1), A_MASK,        PPC,            { FRT,FRA,FRC,FRB } },
3353
3354 { "fmul",    A(63,25,0), AFRB_MASK,     PPCCOM,         { FRT, FRA, FRC } },
3355 { "fm",      A(63,25,0), AFRB_MASK,     PWRCOM,         { FRT, FRA, FRC } },
3356 { "fmul.",   A(63,25,1), AFRB_MASK,     PPCCOM,         { FRT, FRA, FRC } },
3357 { "fm.",     A(63,25,1), AFRB_MASK,     PWRCOM,         { FRT, FRA, FRC } },
3358
3359 { "frsqrte", A(63,26,0), AFRAFRC_MASK,  PPC,            { FRT, FRB } },
3360 { "frsqrte.",A(63,26,1), AFRAFRC_MASK,  PPC,            { FRT, FRB } },
3361
3362 { "fmsub",   A(63,28,0), A_MASK,        PPCCOM,         { FRT,FRA,FRC,FRB } },
3363 { "fms",     A(63,28,0), A_MASK,        PWRCOM,         { FRT,FRA,FRC,FRB } },
3364 { "fmsub.",  A(63,28,1), A_MASK,        PPCCOM,         { FRT,FRA,FRC,FRB } },
3365 { "fms.",    A(63,28,1), A_MASK,        PWRCOM,         { FRT,FRA,FRC,FRB } },
3366
3367 { "fmadd",   A(63,29,0), A_MASK,        PPCCOM,         { FRT,FRA,FRC,FRB } },
3368 { "fma",     A(63,29,0), A_MASK,        PWRCOM,         { FRT,FRA,FRC,FRB } },
3369 { "fmadd.",  A(63,29,1), A_MASK,        PPCCOM,         { FRT,FRA,FRC,FRB } },
3370 { "fma.",    A(63,29,1), A_MASK,        PWRCOM,         { FRT,FRA,FRC,FRB } },
3371
3372 { "fnmsub",  A(63,30,0), A_MASK,        PPCCOM,         { FRT,FRA,FRC,FRB } },
3373 { "fnms",    A(63,30,0), A_MASK,        PWRCOM,         { FRT,FRA,FRC,FRB } },
3374 { "fnmsub.", A(63,30,1), A_MASK,        PPCCOM,         { FRT,FRA,FRC,FRB } },
3375 { "fnms.",   A(63,30,1), A_MASK,        PWRCOM,         { FRT,FRA,FRC,FRB } },
3376
3377 { "fnmadd",  A(63,31,0), A_MASK,        PPCCOM,         { FRT,FRA,FRC,FRB } },
3378 { "fnma",    A(63,31,0), A_MASK,        PWRCOM,         { FRT,FRA,FRC,FRB } },
3379 { "fnmadd.", A(63,31,1), A_MASK,        PPCCOM,         { FRT,FRA,FRC,FRB } },
3380 { "fnma.",   A(63,31,1), A_MASK,        PWRCOM,         { FRT,FRA,FRC,FRB } },
3381
3382 { "fcmpo",   X(63,32),  X_MASK|(3<<21), COM,            { BF, FRA, FRB } },
3383
3384 { "mtfsb1",  XRC(63,38,0), XRARB_MASK,  COM,            { BT } },
3385 { "mtfsb1.", XRC(63,38,1), XRARB_MASK,  COM,            { BT } },
3386
3387 { "fneg",    XRC(63,40,0), XRA_MASK,    COM,            { FRT, FRB } },
3388 { "fneg.",   XRC(63,40,1), XRA_MASK,    COM,            { FRT, FRB } },
3389
3390 { "mcrfs",   X(63,64),  XRB_MASK|(3<<21)|(3<<16), COM,  { BF, BFA } },
3391
3392 { "mtfsb0",  XRC(63,70,0), XRARB_MASK,  COM,            { BT } },
3393 { "mtfsb0.", XRC(63,70,1), XRARB_MASK,  COM,            { BT } },
3394
3395 { "fmr",     XRC(63,72,0), XRA_MASK,    COM,            { FRT, FRB } },
3396 { "fmr.",    XRC(63,72,1), XRA_MASK,    COM,            { FRT, FRB } },
3397
3398 { "mtfsfi",  XRC(63,134,0), XRA_MASK|(3<<21)|(1<<11), COM, { BF, U } },
3399 { "mtfsfi.", XRC(63,134,1), XRA_MASK|(3<<21)|(1<<11), COM, { BF, U } },
3400
3401 { "fnabs",   XRC(63,136,0), XRA_MASK,   COM,            { FRT, FRB } },
3402 { "fnabs.",  XRC(63,136,1), XRA_MASK,   COM,            { FRT, FRB } },
3403
3404 { "fabs",    XRC(63,264,0), XRA_MASK,   COM,            { FRT, FRB } },
3405 { "fabs.",   XRC(63,264,1), XRA_MASK,   COM,            { FRT, FRB } },
3406
3407 { "mffs",    XRC(63,583,0), XRARB_MASK, COM,            { FRT } },
3408 { "mffs.",   XRC(63,583,1), XRARB_MASK, COM,            { FRT } },
3409
3410 { "mtfsf",   XFL(63,711,0), XFL_MASK,   COM,            { FLM, FRB } },
3411 { "mtfsf.",  XFL(63,711,1), XFL_MASK,   COM,            { FLM, FRB } },
3412
3413 { "fctid",   XRC(63,814,0), XRA_MASK,   PPC64,          { FRT, FRB } },
3414 { "fctid.",  XRC(63,814,1), XRA_MASK,   PPC64,          { FRT, FRB } },
3415
3416 { "fctidz",  XRC(63,815,0), XRA_MASK,   PPC64,          { FRT, FRB } },
3417 { "fctidz.", XRC(63,815,1), XRA_MASK,   PPC64,          { FRT, FRB } },
3418
3419 { "fcfid",   XRC(63,846,0), XRA_MASK,   PPC64,          { FRT, FRB } },
3420 { "fcfid.",  XRC(63,846,1), XRA_MASK,   PPC64,          { FRT, FRB } },
3421
3422 };
3423
3424 const int powerpc_num_opcodes =
3425   sizeof (powerpc_opcodes) / sizeof (powerpc_opcodes[0]);
3426 \f
3427 /* The macro table.  This is only used by the assembler.  */
3428
3429 /* The expressions of the form (-x ! 31) & (x | 31) have the value 0
3430    when x=0; 32-x when x is between 1 and 31; are negative if x is
3431    negative; and are 32 or more otherwise.  This is what you want
3432    when, for instance, you are emulating a right shift by a
3433    rotate-left-and-mask, because the underlying instructions support
3434    shifts of size 0 but not shifts of size 32.  By comparison, when
3435    extracting x bits from some word you want to use just 32-x, because
3436    the underlying instructions don't support extracting 0 bits but do
3437    support extracting the whole word (32 bits in this case).  */
3438
3439 const struct powerpc_macro powerpc_macros[] = {
3440 { "extldi",  4,   PPC64,        "rldicr %0,%1,%3,(%2)-1" },
3441 { "extldi.", 4,   PPC64,        "rldicr. %0,%1,%3,(%2)-1" },
3442 { "extrdi",  4,   PPC64,        "rldicl %0,%1,(%2)+(%3),64-(%2)" },
3443 { "extrdi.", 4,   PPC64,        "rldicl. %0,%1,(%2)+(%3),64-(%2)" },
3444 { "insrdi",  4,   PPC64,        "rldimi %0,%1,64-((%2)+(%3)),%3" },
3445 { "insrdi.", 4,   PPC64,        "rldimi. %0,%1,64-((%2)+(%3)),%3" },
3446 { "rotrdi",  3,   PPC64,        "rldicl %0,%1,(-(%2)!63)&((%2)|63),0" },
3447 { "rotrdi.", 3,   PPC64,        "rldicl. %0,%1,(-(%2)!63)&((%2)|63),0" },
3448 { "sldi",    3,   PPC64,        "rldicr %0,%1,%2,63-(%2)" },
3449 { "sldi.",   3,   PPC64,        "rldicr. %0,%1,%2,63-(%2)" },
3450 { "srdi",    3,   PPC64,        "rldicl %0,%1,(-(%2)!63)&((%2)|63),%2" },
3451 { "srdi.",   3,   PPC64,        "rldicl. %0,%1,(-(%2)!63)&((%2)|63),%2" },
3452 { "clrrdi",  3,   PPC64,        "rldicr %0,%1,0,63-(%2)" },
3453 { "clrrdi.", 3,   PPC64,        "rldicr. %0,%1,0,63-(%2)" },
3454 { "clrlsldi",4,   PPC64,        "rldic %0,%1,%3,(%2)-(%3)" },
3455 { "clrlsldi.",4,  PPC64,        "rldic. %0,%1,%3,(%2)-(%3)" },
3456
3457 { "extlwi",  4,   PPCCOM,       "rlwinm %0,%1,%3,0,(%2)-1" },
3458 { "extlwi.", 4,   PPCCOM,       "rlwinm. %0,%1,%3,0,(%2)-1" },
3459 { "extrwi",  4,   PPCCOM,       "rlwinm %0,%1,(%2)+(%3),32-(%2),31" },
3460 { "extrwi.", 4,   PPCCOM,       "rlwinm. %0,%1,(%2)+(%3),32-(%2),31" },
3461 { "inslwi",  4,   PPCCOM,       "rlwimi %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1" },
3462 { "inslwi.", 4,   PPCCOM,       "rlwimi. %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1"},
3463 { "insrwi",  4,   PPCCOM,       "rlwimi %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1" },
3464 { "insrwi.", 4,   PPCCOM,       "rlwimi. %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1"},
3465 { "rotrwi",  3,   PPCCOM,       "rlwinm %0,%1,(-(%2)!31)&((%2)|31),0,31" },
3466 { "rotrwi.", 3,   PPCCOM,       "rlwinm. %0,%1,(-(%2)!31)&((%2)|31),0,31" },
3467 { "slwi",    3,   PPCCOM,       "rlwinm %0,%1,%2,0,31-(%2)" },
3468 { "sli",     3,   PWRCOM,       "rlinm %0,%1,%2,0,31-(%2)" },
3469 { "slwi.",   3,   PPCCOM,       "rlwinm. %0,%1,%2,0,31-(%2)" },
3470 { "sli.",    3,   PWRCOM,       "rlinm. %0,%1,%2,0,31-(%2)" },
3471 { "srwi",    3,   PPCCOM,       "rlwinm %0,%1,(-(%2)!31)&((%2)|31),%2,31" },
3472 { "sri",     3,   PWRCOM,       "rlinm %0,%1,(-(%2)!31)&((%2)|31),%2,31" },
3473 { "srwi.",   3,   PPCCOM,       "rlwinm. %0,%1,(-(%2)!31)&((%2)|31),%2,31" },
3474 { "sri.",    3,   PWRCOM,       "rlinm. %0,%1,(-(%2)!31)&((%2)|31),%2,31" },
3475 { "clrrwi",  3,   PPCCOM,       "rlwinm %0,%1,0,0,31-(%2)" },
3476 { "clrrwi.", 3,   PPCCOM,       "rlwinm. %0,%1,0,0,31-(%2)" },
3477 { "clrlslwi",4,   PPCCOM,       "rlwinm %0,%1,%3,(%2)-(%3),31-(%3)" },
3478 { "clrlslwi.",4,  PPCCOM,       "rlwinm. %0,%1,%3,(%2)-(%3),31-(%3)" },
3479
3480 };
3481
3482 const int powerpc_num_macros =
3483   sizeof (powerpc_macros) / sizeof (powerpc_macros[0]);