opcodes/iq2000-dis.c

   1 /* Disassembler interface for targets using CGEN. -*- C -*-
   2    CGEN: Cpu tools GENerator
   3
   4 THIS FILE IS MACHINE GENERATED WITH CGEN.
   5 - the resultant file is machine generated, cgen-dis.in isn't
   6
   7 Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002
   8 Free Software Foundation, Inc.
   9
  10 This file is part of the GNU Binutils and GDB, the GNU debugger.
  11
  12 This program is free software; you can redistribute it and/or modify
  13 it under the terms of the GNU General Public License as published by
  14 the Free Software Foundation; either version 2, or (at your option)
  15 any later version.
  16
  17 This program is distributed in the hope that it will be useful,
  18 but WITHOUT ANY WARRANTY; without even the implied warranty of
  19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  20 GNU General Public License for more details.
  21
  22 You should have received a copy of the GNU General Public License
  23 along with this program; if not, write to the Free Software Foundation, Inc.,
  24 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
  25
  26 /* ??? Eventually more and more of this stuff can go to cpu-independent files.
  27    Keep that in mind.  */
  28
  29 #include "sysdep.h"
  30 #include <stdio.h>
  31 #include "ansidecl.h"
  32 #include "dis-asm.h"
  33 #include "bfd.h"
  34 #include "symcat.h"
  35 #include "libiberty.h"
  36 #include "iq2000-desc.h"
  37 #include "iq2000-opc.h"
  38 #include "opintl.h"
  39
  40 /* Default text to print if an instruction isn't recognized.  */
  41 #define UNKNOWN_INSN_MSG _("*unknown*")
  42
  43 static void print_normal
  44      PARAMS ((CGEN_CPU_DESC, PTR, long, unsigned int, bfd_vma, int));
  45 static void print_address
  46      PARAMS ((CGEN_CPU_DESC, PTR, bfd_vma, unsigned int, bfd_vma, int));
  47 static void print_keyword
  48      PARAMS ((CGEN_CPU_DESC, PTR, CGEN_KEYWORD *, long, unsigned int));
  49 static void print_insn_normal
  50      PARAMS ((CGEN_CPU_DESC, PTR, const CGEN_INSN *, CGEN_FIELDS *,
  51               bfd_vma, int));
  52 static int print_insn
  53      PARAMS ((CGEN_CPU_DESC, bfd_vma,  disassemble_info *, char *, unsigned));
  54 static int default_print_insn
  55      PARAMS ((CGEN_CPU_DESC, bfd_vma, disassemble_info *));
  56 static int read_insn
  57      PARAMS ((CGEN_CPU_DESC, bfd_vma, disassemble_info *, char *, int,
  58               CGEN_EXTRACT_INFO *, unsigned long *));
  59 \f
  60 /* -- disassembler routines inserted here */
  61
  62
  63 void iq2000_cgen_print_operand
  64   PARAMS ((CGEN_CPU_DESC, int, PTR, CGEN_FIELDS *,
  65            void const *, bfd_vma, int));
  66
  67 /* Main entry point for printing operands.
  68    XINFO is a `void *' and not a `disassemble_info *' to not put a requirement
  69    of dis-asm.h on cgen.h.
  70
  71    This function is basically just a big switch statement.  Earlier versions
  72    used tables to look up the function to use, but
  73    - if the table contains both assembler and disassembler functions then
  74      the disassembler contains much of the assembler and vice-versa,
  75    - there's a lot of inlining possibilities as things grow,
  76    - using a switch statement avoids the function call overhead.
  77
  78    This function could be moved into `print_insn_normal', but keeping it
  79    separate makes clear the interface between `print_insn_normal' and each of
  80    the handlers.  */
  81
  82 void
  83 iq2000_cgen_print_operand (cd, opindex, xinfo, fields, attrs, pc, length)
  84      CGEN_CPU_DESC cd;
  85      int opindex;
  86      PTR xinfo;
  87      CGEN_FIELDS *fields;
  88      void const *attrs ATTRIBUTE_UNUSED;
  89      bfd_vma pc;
  90      int length;
  91 {
  92  disassemble_info *info = (disassemble_info *) xinfo;
  93
  94   switch (opindex)
  95     {
  96     case IQ2000_OPERAND_BASE :
  97       print_keyword (cd, info, & iq2000_cgen_opval_gr_names, fields->f_rs, 0);
  98       break;
  99     case IQ2000_OPERAND_BASEOFF :
 100       print_address (cd, info, fields->f_imm, 0, pc, length);
 101       break;
 102     case IQ2000_OPERAND_BITNUM :
 103       print_normal (cd, info, fields->f_rt, 0, pc, length);
 104       break;
 105     case IQ2000_OPERAND_BYTECOUNT :
 106       print_normal (cd, info, fields->f_bytecount, 0, pc, length);
 107       break;
 108     case IQ2000_OPERAND_CAM_Y :
 109       print_normal (cd, info, fields->f_cam_y, 0, pc, length);
 110       break;
 111     case IQ2000_OPERAND_CAM_Z :
 112       print_normal (cd, info, fields->f_cam_z, 0, pc, length);
 113       break;
 114     case IQ2000_OPERAND_CM_3FUNC :
 115       print_normal (cd, info, fields->f_cm_3func, 0, pc, length);
 116       break;
 117     case IQ2000_OPERAND_CM_3Z :
 118       print_normal (cd, info, fields->f_cm_3z, 0, pc, length);
 119       break;
 120     case IQ2000_OPERAND_CM_4FUNC :
 121       print_normal (cd, info, fields->f_cm_4func, 0, pc, length);
 122       break;
 123     case IQ2000_OPERAND_CM_4Z :
 124       print_normal (cd, info, fields->f_cm_4z, 0, pc, length);
 125       break;
 126     case IQ2000_OPERAND_COUNT :
 127       print_normal (cd, info, fields->f_count, 0, pc, length);
 128       break;
 129     case IQ2000_OPERAND_EXECODE :
 130       print_normal (cd, info, fields->f_excode, 0, pc, length);
 131       break;
 132     case IQ2000_OPERAND_F_INDEX :
 133       print_normal (cd, info, fields->f_index, 0, pc, length);
 134       break;
 135     case IQ2000_OPERAND_HI16 :
 136       print_normal (cd, info, fields->f_imm, 0, pc, length);
 137       break;
 138     case IQ2000_OPERAND_IMM :
 139       print_normal (cd, info, fields->f_imm, 0, pc, length);
 140       break;
 141     case IQ2000_OPERAND_JMPTARG :
 142       print_address (cd, info, fields->f_jtarg, 0|(1<<CGEN_OPERAND_ABS_ADDR), pc, length);
 143       break;
 144     case IQ2000_OPERAND_JMPTARGQ10 :
 145       print_address (cd, info, fields->f_jtargq10, 0|(1<<CGEN_OPERAND_ABS_ADDR), pc, length);
 146       break;
 147     case IQ2000_OPERAND_LO16 :
 148       print_normal (cd, info, fields->f_imm, 0, pc, length);
 149       break;
 150     case IQ2000_OPERAND_MASK :
 151       print_normal (cd, info, fields->f_mask, 0, pc, length);
 152       break;
 153     case IQ2000_OPERAND_MASKL :
 154       print_normal (cd, info, fields->f_maskl, 0, pc, length);
 155       break;
 156     case IQ2000_OPERAND_MASKQ10 :
 157       print_normal (cd, info, fields->f_maskq10, 0, pc, length);
 158       break;
 159     case IQ2000_OPERAND_MASKR :
 160       print_normal (cd, info, fields->f_rs, 0, pc, length);
 161       break;
 162     case IQ2000_OPERAND_MLO16 :
 163       print_normal (cd, info, fields->f_imm, 0, pc, length);
 164       break;
 165     case IQ2000_OPERAND_OFFSET :
 166       print_address (cd, info, fields->f_offset, 0|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length);
 167       break;
 168     case IQ2000_OPERAND_RD :
 169       print_keyword (cd, info, & iq2000_cgen_opval_gr_names, fields->f_rd, 0);
 170       break;
 171     case IQ2000_OPERAND_RD_RS :
 172       print_keyword (cd, info, & iq2000_cgen_opval_gr_names, fields->f_rd_rs, 0|(1<<CGEN_OPERAND_VIRTUAL));
 173       break;
 174     case IQ2000_OPERAND_RD_RT :
 175       print_keyword (cd, info, & iq2000_cgen_opval_gr_names, fields->f_rd_rt, 0|(1<<CGEN_OPERAND_VIRTUAL));
 176       break;
 177     case IQ2000_OPERAND_RS :
 178       print_keyword (cd, info, & iq2000_cgen_opval_gr_names, fields->f_rs, 0);
 179       break;
 180     case IQ2000_OPERAND_RT :
 181       print_keyword (cd, info, & iq2000_cgen_opval_gr_names, fields->f_rt, 0);
 182       break;
 183     case IQ2000_OPERAND_RT_RS :
 184       print_keyword (cd, info, & iq2000_cgen_opval_gr_names, fields->f_rt_rs, 0|(1<<CGEN_OPERAND_VIRTUAL));
 185       break;
 186     case IQ2000_OPERAND_SHAMT :
 187       print_normal (cd, info, fields->f_shamt, 0, pc, length);
 188       break;
 189
 190     default :
 191       /* xgettext:c-format */
 192       fprintf (stderr, _("Unrecognized field %d while printing insn.\n"),
 193                opindex);
 194     abort ();
 195   }
 196 }
 197
 198 cgen_print_fn * const iq2000_cgen_print_handlers[] =
 199 {
 200   print_insn_normal,
 201 };
 202
 203
 204 void
 205 iq2000_cgen_init_dis (cd)
 206      CGEN_CPU_DESC cd;
 207 {
 208   iq2000_cgen_init_opcode_table (cd);
 209   iq2000_cgen_init_ibld_table (cd);
 210   cd->print_handlers = & iq2000_cgen_print_handlers[0];
 211   cd->print_operand = iq2000_cgen_print_operand;
 212 }
 213
 214 \f
 215 /* Default print handler.  */
 216
 217 static void
 218 print_normal (cd, dis_info, value, attrs, pc, length)
 219      CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
 220      PTR dis_info;
 221      long value;
 222      unsigned int attrs;
 223      bfd_vma pc ATTRIBUTE_UNUSED;
 224      int length ATTRIBUTE_UNUSED;
 225 {
 226   disassemble_info *info = (disassemble_info *) dis_info;
 227
 228 #ifdef CGEN_PRINT_NORMAL
 229   CGEN_PRINT_NORMAL (cd, info, value, attrs, pc, length);
 230 #endif
 231
 232   /* Print the operand as directed by the attributes.  */
 233   if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY))
 234     ; /* nothing to do */
 235   else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED))
 236     (*info->fprintf_func) (info->stream, "%ld", value);
 237   else
 238     (*info->fprintf_func) (info->stream, "0x%lx", value);
 239 }
 240
 241 /* Default address handler.  */
 242
 243 static void
 244 print_address (cd, dis_info, value, attrs, pc, length)
 245      CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
 246      PTR dis_info;
 247      bfd_vma value;
 248      unsigned int attrs;
 249      bfd_vma pc ATTRIBUTE_UNUSED;
 250      int length ATTRIBUTE_UNUSED;
 251 {
 252   disassemble_info *info = (disassemble_info *) dis_info;
 253
 254 #ifdef CGEN_PRINT_ADDRESS
 255   CGEN_PRINT_ADDRESS (cd, info, value, attrs, pc, length);
 256 #endif
 257
 258   /* Print the operand as directed by the attributes.  */
 259   if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY))
 260     ; /* nothing to do */
 261   else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_PCREL_ADDR))
 262     (*info->print_address_func) (value, info);
 263   else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_ABS_ADDR))
 264     (*info->print_address_func) (value, info);
 265   else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED))
 266     (*info->fprintf_func) (info->stream, "%ld", (long) value);
 267   else
 268     (*info->fprintf_func) (info->stream, "0x%lx", (long) value);
 269 }
 270
 271 /* Keyword print handler.  */
 272
 273 static void
 274 print_keyword (cd, dis_info, keyword_table, value, attrs)
 275      CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
 276      PTR dis_info;
 277      CGEN_KEYWORD *keyword_table;
 278      long value;
 279      unsigned int attrs ATTRIBUTE_UNUSED;
 280 {
 281   disassemble_info *info = (disassemble_info *) dis_info;
 282   const CGEN_KEYWORD_ENTRY *ke;
 283
 284   ke = cgen_keyword_lookup_value (keyword_table, value);
 285   if (ke != NULL)
 286     (*info->fprintf_func) (info->stream, "%s", ke->name);
 287   else
 288     (*info->fprintf_func) (info->stream, "???");
 289 }
 290 \f
 291 /* Default insn printer.
 292
 293    DIS_INFO is defined as `PTR' so the disassembler needn't know anything
 294    about disassemble_info.  */
 295
 296 static void
 297 print_insn_normal (cd, dis_info, insn, fields, pc, length)
 298      CGEN_CPU_DESC cd;
 299      PTR dis_info;
 300      const CGEN_INSN *insn;
 301      CGEN_FIELDS *fields;
 302      bfd_vma pc;
 303      int length;
 304 {
 305   const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn);
 306   disassemble_info *info = (disassemble_info *) dis_info;
 307   const CGEN_SYNTAX_CHAR_TYPE *syn;
 308
 309   CGEN_INIT_PRINT (cd);
 310
 311   for (syn = CGEN_SYNTAX_STRING (syntax); *syn; ++syn)
 312     {
 313       if (CGEN_SYNTAX_MNEMONIC_P (*syn))
 314         {
 315           (*info->fprintf_func) (info->stream, "%s", CGEN_INSN_MNEMONIC (insn));
 316           continue;
 317         }
 318       if (CGEN_SYNTAX_CHAR_P (*syn))
 319         {
 320           (*info->fprintf_func) (info->stream, "%c", CGEN_SYNTAX_CHAR (*syn));
 321           continue;
 322         }
 323
 324       /* We have an operand.  */
 325       iq2000_cgen_print_operand (cd, CGEN_SYNTAX_FIELD (*syn), info,
 326                                  fields, CGEN_INSN_ATTRS (insn), pc, length);
 327     }
 328 }
 329 \f
 330 /* Subroutine of print_insn. Reads an insn into the given buffers and updates
 331    the extract info.
 332    Returns 0 if all is well, non-zero otherwise.  */
 333
 334 static int
 335 read_insn (cd, pc, info, buf, buflen, ex_info, insn_value)
 336      CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
 337      bfd_vma pc;
 338      disassemble_info *info;
 339      char *buf;
 340      int buflen;
 341      CGEN_EXTRACT_INFO *ex_info;
 342      unsigned long *insn_value;
 343 {
 344   int status = (*info->read_memory_func) (pc, buf, buflen, info);
 345   if (status != 0)
 346     {
 347       (*info->memory_error_func) (status, pc, info);
 348       return -1;
 349     }
 350
 351   ex_info->dis_info = info;
 352   ex_info->valid = (1 << buflen) - 1;
 353   ex_info->insn_bytes = buf;
 354
 355   *insn_value = bfd_get_bits (buf, buflen * 8, info->endian == BFD_ENDIAN_BIG);
 356   return 0;
 357 }
 358
 359 /* Utility to print an insn.
 360    BUF is the base part of the insn, target byte order, BUFLEN bytes long.
 361    The result is the size of the insn in bytes or zero for an unknown insn
 362    or -1 if an error occurs fetching data (memory_error_func will have
 363    been called).  */
 364
 365 static int
 366 print_insn (cd, pc, info, buf, buflen)
 367      CGEN_CPU_DESC cd;
 368      bfd_vma pc;
 369      disassemble_info *info;
 370      char *buf;
 371      unsigned int buflen;
 372 {
 373   CGEN_INSN_INT insn_value;
 374   const CGEN_INSN_LIST *insn_list;
 375   CGEN_EXTRACT_INFO ex_info;
 376   int basesize;
 377
 378   /* Extract base part of instruction, just in case CGEN_DIS_* uses it. */
 379   basesize = cd->base_insn_bitsize < buflen * 8 ?
 380                                      cd->base_insn_bitsize : buflen * 8;
 381   insn_value = cgen_get_insn_value (cd, buf, basesize);
 382
 383
 384   /* Fill in ex_info fields like read_insn would.  Don't actually call
 385      read_insn, since the incoming buffer is already read (and possibly
 386      modified a la m32r).  */
 387   ex_info.valid = (1 << buflen) - 1;
 388   ex_info.dis_info = info;
 389   ex_info.insn_bytes = buf;
 390
 391   /* The instructions are stored in hash lists.
 392      Pick the first one and keep trying until we find the right one.  */
 393
 394   insn_list = CGEN_DIS_LOOKUP_INSN (cd, buf, insn_value);
 395   while (insn_list != NULL)
 396     {
 397       const CGEN_INSN *insn = insn_list->insn;
 398       CGEN_FIELDS fields;
 399       int length;
 400       unsigned long insn_value_cropped;
 401
 402 #ifdef CGEN_VALIDATE_INSN_SUPPORTED
 403       /* Not needed as insn shouldn't be in hash lists if not supported.  */
 404       /* Supported by this cpu?  */
 405       if (! iq2000_cgen_insn_supported (cd, insn))
 406         {
 407           insn_list = CGEN_DIS_NEXT_INSN (insn_list);
 408           continue;
 409         }
 410 #endif
 411
 412       /* Basic bit mask must be correct.  */
 413       /* ??? May wish to allow target to defer this check until the extract
 414          handler.  */
 415
 416       /* Base size may exceed this instruction's size.  Extract the
 417          relevant part from the buffer. */
 418       if ((unsigned) (CGEN_INSN_BITSIZE (insn) / 8) < buflen &&
 419           (unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long))
 420         insn_value_cropped = bfd_get_bits (buf, CGEN_INSN_BITSIZE (insn),
 421                                            info->endian == BFD_ENDIAN_BIG);
 422       else
 423         insn_value_cropped = insn_value;
 424
 425       if ((insn_value_cropped & CGEN_INSN_BASE_MASK (insn))
 426           == CGEN_INSN_BASE_VALUE (insn))
 427         {
 428           /* Printing is handled in two passes.  The first pass parses the
 429              machine insn and extracts the fields.  The second pass prints
 430              them.  */
 431
 432           /* Make sure the entire insn is loaded into insn_value, if it
 433              can fit.  */
 434           if (((unsigned) CGEN_INSN_BITSIZE (insn) > cd->base_insn_bitsize) &&
 435               (unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long))
 436             {
 437               unsigned long full_insn_value;
 438               int rc = read_insn (cd, pc, info, buf,
 439                                   CGEN_INSN_BITSIZE (insn) / 8,
 440                                   & ex_info, & full_insn_value);
 441               if (rc != 0)
 442                 return rc;
 443               length = CGEN_EXTRACT_FN (cd, insn)
 444                 (cd, insn, &ex_info, full_insn_value, &fields, pc);
 445             }
 446           else
 447             length = CGEN_EXTRACT_FN (cd, insn)
 448               (cd, insn, &ex_info, insn_value_cropped, &fields, pc);
 449
 450           /* length < 0 -> error */
 451           if (length < 0)
 452             return length;
 453           if (length > 0)
 454             {
 455               CGEN_PRINT_FN (cd, insn) (cd, info, insn, &fields, pc, length);
 456               /* length is in bits, result is in bytes */
 457               return length / 8;
 458             }
 459         }
 460
 461       insn_list = CGEN_DIS_NEXT_INSN (insn_list);
 462     }
 463
 464   return 0;
 465 }
 466
 467 /* Default value for CGEN_PRINT_INSN.
 468    The result is the size of the insn in bytes or zero for an unknown insn
 469    or -1 if an error occured fetching bytes.  */
 470
 471 #ifndef CGEN_PRINT_INSN
 472 #define CGEN_PRINT_INSN default_print_insn
 473 #endif
 474
 475 static int
 476 default_print_insn (cd, pc, info)
 477      CGEN_CPU_DESC cd;
 478      bfd_vma pc;
 479      disassemble_info *info;
 480 {
 481   char buf[CGEN_MAX_INSN_SIZE];
 482   int buflen;
 483   int status;
 484
 485   /* Attempt to read the base part of the insn.  */
 486   buflen = cd->base_insn_bitsize / 8;
 487   status = (*info->read_memory_func) (pc, buf, buflen, info);
 488
 489   /* Try again with the minimum part, if min < base.  */
 490   if (status != 0 && (cd->min_insn_bitsize < cd->base_insn_bitsize))
 491     {
 492       buflen = cd->min_insn_bitsize / 8;
 493       status = (*info->read_memory_func) (pc, buf, buflen, info);
 494     }
 495
 496   if (status != 0)
 497     {
 498       (*info->memory_error_func) (status, pc, info);
 499       return -1;
 500     }
 501
 502   return print_insn (cd, pc, info, buf, buflen);
 503 }
 504
 505 /* Main entry point.
 506    Print one instruction from PC on INFO->STREAM.
 507    Return the size of the instruction (in bytes).  */
 508
 509 typedef struct cpu_desc_list {
 510   struct cpu_desc_list *next;
 511   int isa;
 512   int mach;
 513   int endian;
 514   CGEN_CPU_DESC cd;
 515 } cpu_desc_list;
 516
 517 int
 518 print_insn_iq2000 (pc, info)
 519      bfd_vma pc;
 520      disassemble_info *info;
 521 {
 522   static cpu_desc_list *cd_list = 0;
 523   cpu_desc_list *cl = 0;
 524   static CGEN_CPU_DESC cd = 0;
 525   static int prev_isa;
 526   static int prev_mach;
 527   static int prev_endian;
 528   int length;
 529   int isa,mach;
 530   int endian = (info->endian == BFD_ENDIAN_BIG
 531                 ? CGEN_ENDIAN_BIG
 532                 : CGEN_ENDIAN_LITTLE);
 533   enum bfd_architecture arch;
 534
 535   /* ??? gdb will set mach but leave the architecture as "unknown" */
 536 #ifndef CGEN_BFD_ARCH
 537 #define CGEN_BFD_ARCH bfd_arch_iq2000
 538 #endif
 539   arch = info->arch;
 540   if (arch == bfd_arch_unknown)
 541     arch = CGEN_BFD_ARCH;
 542
 543   /* There's no standard way to compute the machine or isa number
 544      so we leave it to the target.  */
 545 #ifdef CGEN_COMPUTE_MACH
 546   mach = CGEN_COMPUTE_MACH (info);
 547 #else
 548   mach = info->mach;
 549 #endif
 550
 551 #ifdef CGEN_COMPUTE_ISA
 552   isa = CGEN_COMPUTE_ISA (info);
 553 #else
 554   isa = info->insn_sets;
 555 #endif
 556
 557   /* If we've switched cpu's, try to find a handle we've used before */
 558   if (cd
 559       && (isa != prev_isa
 560           || mach != prev_mach
 561           || endian != prev_endian))
 562     {
 563       cd = 0;
 564       for (cl = cd_list; cl; cl = cl->next)
 565         {
 566           if (cl->isa == isa &&
 567               cl->mach == mach &&
 568               cl->endian == endian)
 569             {
 570               cd = cl->cd;
 571               break;
 572             }
 573         }
 574     }
 575
 576   /* If we haven't initialized yet, initialize the opcode table.  */
 577   if (! cd)
 578     {
 579       const bfd_arch_info_type *arch_type = bfd_lookup_arch (arch, mach);
 580       const char *mach_name;
 581
 582       if (!arch_type)
 583         abort ();
 584       mach_name = arch_type->printable_name;
 585
 586       prev_isa = isa;
 587       prev_mach = mach;
 588       prev_endian = endian;
 589       cd = iq2000_cgen_cpu_open (CGEN_CPU_OPEN_ISAS, prev_isa,
 590                                  CGEN_CPU_OPEN_BFDMACH, mach_name,
 591                                  CGEN_CPU_OPEN_ENDIAN, prev_endian,
 592                                  CGEN_CPU_OPEN_END);
 593       if (!cd)
 594         abort ();
 595
 596       /* save this away for future reference */
 597       cl = xmalloc (sizeof (struct cpu_desc_list));
 598       cl->cd = cd;
 599       cl->isa = isa;
 600       cl->mach = mach;
 601       cl->endian = endian;
 602       cl->next = cd_list;
 603       cd_list = cl;
 604
 605       iq2000_cgen_init_dis (cd);
 606     }
 607
 608   /* We try to have as much common code as possible.
 609      But at this point some targets need to take over.  */
 610   /* ??? Some targets may need a hook elsewhere.  Try to avoid this,
 611      but if not possible try to move this hook elsewhere rather than
 612      have two hooks.  */
 613   length = CGEN_PRINT_INSN (cd, pc, info);
 614   if (length > 0)
 615     return length;
 616   if (length < 0)
 617     return -1;
 618
 619   (*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG);
 620   return cd->default_insn_bitsize / 8;
 621 }