opcodes/i386-opc.h

   1 /* Declarations for Intel 80386 opcode table
   2    Copyright 2007, 2008, 2009
   3    Free Software Foundation, Inc.
   4
   5    This file is part of the GNU opcodes library.
   6
   7    This library is free software; you can redistribute it and/or modify
   8    it under the terms of the GNU General Public License as published by
   9    the Free Software Foundation; either version 3, or (at your option)
  10    any later version.
  11
  12    It is distributed in the hope that it will be useful, but WITHOUT
  13    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  14    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  15    License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with GAS; see the file COPYING.  If not, write to the Free
  19    Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
  20    02110-1301, USA.  */
  21
  22 #include "opcode/i386.h"
  23 #ifdef HAVE_LIMITS_H
  24 #include <limits.h>
  25 #endif
  26
  27 #ifndef CHAR_BIT
  28 #define CHAR_BIT 8
  29 #endif
  30
  31 /* Position of cpu flags bitfiled.  */
  32
  33 enum
  34 {
  35   /* i186 or better required */
  36   Cpu186 = 0,
  37   /* i286 or better required */
  38   Cpu286,
  39   /* i386 or better required */
  40   Cpu386,
  41   /* i486 or better required */
  42   Cpu486,
  43   /* i585 or better required */
  44   Cpu586,
  45   /* i686 or better required */
  46   Cpu686,
  47   /* CLFLUSH Instuction support required */
  48   CpuClflush,
  49   /* SYSCALL Instuctions support required */
  50   CpuSYSCALL,
  51   /* Floating point support required */
  52   Cpu8087,
  53   /* i287 support required */
  54   Cpu287,
  55   /* i387 support required */
  56   Cpu387,
  57   /* i686 and floating point support required */
  58   Cpu687,
  59   /* SSE3 and floating point support required */
  60   CpuFISTTP,
  61   /* MMX support required */
  62   CpuMMX,
  63   /* SSE support required */
  64   CpuSSE,
  65   /* SSE2 support required */
  66   CpuSSE2,
  67   /* 3dnow! support required */
  68   Cpu3dnow,
  69   /* 3dnow! Extensions support required */
  70   Cpu3dnowA,
  71   /* SSE3 support required */
  72   CpuSSE3,
  73   /* VIA PadLock required */
  74   CpuPadLock,
  75   /* AMD Secure Virtual Machine Ext-s required */
  76   CpuSVME,
  77   /* VMX Instructions required */
  78   CpuVMX,
  79   /* SMX Instructions required */
  80   CpuSMX,
  81   /* SSSE3 support required */
  82   CpuSSSE3,
  83   /* SSE4a support required */
  84   CpuSSE4a,
  85   /* ABM New Instructions required */
  86   CpuABM,
  87   /* SSE4.1 support required */
  88   CpuSSE4_1,
  89   /* SSE4.2 support required */
  90   CpuSSE4_2,
  91   /* AVX support required */
  92   CpuAVX,
  93   /* Intel L1OM support required */
  94   CpuL1OM,
  95   /* Xsave/xrstor New Instuctions support required */
  96   CpuXsave,
  97   /* AES support required */
  98   CpuAES,
  99   /* PCLMUL support required */
 100   CpuPCLMUL,
 101   /* FMA support required */
 102   CpuFMA,
 103   /* FMA4 support required */
 104   CpuFMA4,
 105   /* MOVBE Instuction support required */
 106   CpuMovbe,
 107   /* EPT Instructions required */
 108   CpuEPT,
 109   /* RDTSCP Instuction support required */
 110   CpuRdtscp,
 111   /* 64bit support available, used by -march= in assembler.  */
 112   CpuLM,
 113   /* 64bit support required  */
 114   Cpu64,
 115   /* Not supported in the 64bit mode  */
 116   CpuNo64,
 117   /* The last bitfield in i386_cpu_flags.  */
 118   CpuMax = CpuNo64
 119 };
 120
 121 #define CpuNumOfUints \
 122   (CpuMax / sizeof (unsigned int) / CHAR_BIT + 1)
 123 #define CpuNumOfBits \
 124   (CpuNumOfUints * sizeof (unsigned int) * CHAR_BIT)
 125
 126 /* If you get a compiler error for zero width of the unused field,
 127    comment it out.  */
 128 #define CpuUnused       (CpuMax + 1)
 129
 130 /* We can check if an instruction is available with array instead
 131    of bitfield. */
 132 typedef union i386_cpu_flags
 133 {
 134   struct
 135     {
 136       unsigned int cpui186:1;
 137       unsigned int cpui286:1;
 138       unsigned int cpui386:1;
 139       unsigned int cpui486:1;
 140       unsigned int cpui586:1;
 141       unsigned int cpui686:1;
 142       unsigned int cpuclflush:1;
 143       unsigned int cpusyscall:1;
 144       unsigned int cpu8087:1;
 145       unsigned int cpu287:1;
 146       unsigned int cpu387:1;
 147       unsigned int cpu687:1;
 148       unsigned int cpufisttp:1;
 149       unsigned int cpummx:1;
 150       unsigned int cpusse:1;
 151       unsigned int cpusse2:1;
 152       unsigned int cpua3dnow:1;
 153       unsigned int cpua3dnowa:1;
 154       unsigned int cpusse3:1;
 155       unsigned int cpupadlock:1;
 156       unsigned int cpusvme:1;
 157       unsigned int cpuvmx:1;
 158       unsigned int cpusmx:1;
 159       unsigned int cpussse3:1;
 160       unsigned int cpusse4a:1;
 161       unsigned int cpuabm:1;
 162       unsigned int cpusse4_1:1;
 163       unsigned int cpusse4_2:1;
 164       unsigned int cpuavx:1;
 165       unsigned int cpul1om:1;
 166       unsigned int cpuxsave:1;
 167       unsigned int cpuaes:1;
 168       unsigned int cpupclmul:1;
 169       unsigned int cpufma:1;
 170       unsigned int cpufma4:1;
 171       unsigned int cpumovbe:1;
 172       unsigned int cpuept:1;
 173       unsigned int cpurdtscp:1;
 174       unsigned int cpulm:1;
 175       unsigned int cpu64:1;
 176       unsigned int cpuno64:1;
 177 #ifdef CpuUnused
 178       unsigned int unused:(CpuNumOfBits - CpuUnused);
 179 #endif
 180     } bitfield;
 181   unsigned int array[CpuNumOfUints];
 182 } i386_cpu_flags;
 183
 184 /* Position of opcode_modifier bits.  */
 185
 186 enum
 187 {
 188   /* has direction bit. */
 189   D = 0,
 190   /* set if operands can be words or dwords encoded the canonical way */
 191   W,
 192   /* Skip the current insn and use the next insn in i386-opc.tbl to swap
 193      operand in encoding.  */
 194   S,
 195   /* insn has a modrm byte. */
 196   Modrm,
 197   /* register is in low 3 bits of opcode */
 198   ShortForm,
 199   /* special case for jump insns.  */
 200   Jump,
 201   /* call and jump */
 202   JumpDword,
 203   /* loop and jecxz */
 204   JumpByte,
 205   /* special case for intersegment leaps/calls */
 206   JumpInterSegment,
 207   /* FP insn memory format bit, sized by 0x4 */
 208   FloatMF,
 209   /* src/dest swap for floats. */
 210   FloatR,
 211   /* has float insn direction bit. */
 212   FloatD,
 213   /* needs size prefix if in 32-bit mode */
 214   Size16,
 215   /* needs size prefix if in 16-bit mode */
 216   Size32,
 217   /* needs size prefix if in 64-bit mode */
 218   Size64,
 219   /* instruction ignores operand size prefix and in Intel mode ignores
 220      mnemonic size suffix check.  */
 221   IgnoreSize,
 222   /* default insn size depends on mode */
 223   DefaultSize,
 224   /* b suffix on instruction illegal */
 225   No_bSuf,
 226   /* w suffix on instruction illegal */
 227   No_wSuf,
 228   /* l suffix on instruction illegal */
 229   No_lSuf,
 230   /* s suffix on instruction illegal */
 231   No_sSuf,
 232   /* q suffix on instruction illegal */
 233   No_qSuf,
 234   /* long double suffix on instruction illegal */
 235   No_ldSuf,
 236   /* instruction needs FWAIT */
 237   FWait,
 238   /* quick test for string instructions */
 239   IsString,
 240   /* fake an extra reg operand for clr, imul and special register
 241      processing for some instructions.  */
 242   RegKludge,
 243   /* The first operand must be xmm0 */
 244   FirstXmm0,
 245   /* An implicit xmm0 as the first operand */
 246   Implicit1stXmm0,
 247   /* BYTE is OK in Intel syntax. */
 248   ByteOkIntel,
 249   /* Convert to DWORD */
 250   ToDword,
 251   /* Convert to QWORD */
 252   ToQword,
 253   /* Address prefix changes operand 0 */
 254   AddrPrefixOp0,
 255   /* opcode is a prefix */
 256   IsPrefix,
 257   /* instruction has extension in 8 bit imm */
 258   ImmExt,
 259   /* instruction don't need Rex64 prefix.  */
 260   NoRex64,
 261   /* instruction require Rex64 prefix.  */
 262   Rex64,
 263   /* deprecated fp insn, gets a warning */
 264   Ugh,
 265   /* insn has VEX prefix:
 266         1: 128bit VEX prefix.
 267         2: 256bit VEX prefix.
 268    */
 269   Vex,
 270   /* insn has VEX NDS. Register-only source is encoded in Vex prefix.
 271      We use VexNDS on insns with VEX DDS since the register-only source
 272      is the second source register.  */
 273   VexNDS,
 274   /* insn has VEX NDD. Register destination is encoded in Vex prefix. */
 275   VexNDD,
 276   /* insn has VEX W0. */
 277   VexW0,
 278   /* insn has VEX W1. */
 279   VexW1,
 280   /* insn has VEX 0x0F opcode prefix. */
 281   Vex0F,
 282   /* insn has VEX 0x0F38 opcode prefix. */
 283   Vex0F38,
 284   /* insn has VEX 0x0F3A opcode prefix. */
 285   Vex0F3A,
 286   /* insn has VEX prefix with 3 soures. */
 287   Vex3Sources,
 288   /* instruction has VEX 8 bit imm */
 289   VexImmExt,
 290   /* SSE to AVX support required */
 291   SSE2AVX,
 292   /* No AVX equivalent */
 293   NoAVX,
 294   /* Compatible with old (<= 2.8.1) versions of gcc  */
 295   OldGcc,
 296   /* AT&T mnemonic.  */
 297   ATTMnemonic,
 298   /* AT&T syntax.  */
 299   ATTSyntax,
 300   /* Intel syntax.  */
 301   IntelSyntax,
 302   /* The last bitfield in i386_opcode_modifier.  */
 303   Opcode_Modifier_Max
 304 };
 305
 306 typedef struct i386_opcode_modifier
 307 {
 308   unsigned int d:1;
 309   unsigned int w:1;
 310   unsigned int s:1;
 311   unsigned int modrm:1;
 312   unsigned int shortform:1;
 313   unsigned int jump:1;
 314   unsigned int jumpdword:1;
 315   unsigned int jumpbyte:1;
 316   unsigned int jumpintersegment:1;
 317   unsigned int floatmf:1;
 318   unsigned int floatr:1;
 319   unsigned int floatd:1;
 320   unsigned int size16:1;
 321   unsigned int size32:1;
 322   unsigned int size64:1;
 323   unsigned int ignoresize:1;
 324   unsigned int defaultsize:1;
 325   unsigned int no_bsuf:1;
 326   unsigned int no_wsuf:1;
 327   unsigned int no_lsuf:1;
 328   unsigned int no_ssuf:1;
 329   unsigned int no_qsuf:1;
 330   unsigned int no_ldsuf:1;
 331   unsigned int fwait:1;
 332   unsigned int isstring:1;
 333   unsigned int regkludge:1;
 334   unsigned int firstxmm0:1;
 335   unsigned int implicit1stxmm0:1;
 336   unsigned int byteokintel:1;
 337   unsigned int todword:1;
 338   unsigned int toqword:1;
 339   unsigned int addrprefixop0:1;
 340   unsigned int isprefix:1;
 341   unsigned int immext:1;
 342   unsigned int norex64:1;
 343   unsigned int rex64:1;
 344   unsigned int ugh:1;
 345   unsigned int vex:2;
 346   unsigned int vexnds:1;
 347   unsigned int vexndd:1;
 348   unsigned int vexw0:1;
 349   unsigned int vexw1:1;
 350   unsigned int vex0f:1;
 351   unsigned int vex0f38:1;
 352   unsigned int vex0f3a:1;
 353   unsigned int vex3sources:1;
 354   unsigned int veximmext:1;
 355   unsigned int sse2avx:1;
 356   unsigned int noavx:1;
 357   unsigned int oldgcc:1;
 358   unsigned int attmnemonic:1;
 359   unsigned int attsyntax:1;
 360   unsigned int intelsyntax:1;
 361 } i386_opcode_modifier;
 362
 363 /* Position of operand_type bits.  */
 364
 365 enum
 366 {
 367   /* 8bit register */
 368   Reg8 = 0,
 369   /* 16bit register */
 370   Reg16,
 371   /* 32bit register */
 372   Reg32,
 373   /* 64bit register */
 374   Reg64,
 375   /* Floating pointer stack register */
 376   FloatReg,
 377   /* MMX register */
 378   RegMMX,
 379   /* SSE register */
 380   RegXMM,
 381   /* AVX registers */
 382   RegYMM,
 383   /* Control register */
 384   Control,
 385   /* Debug register */
 386   Debug,
 387   /* Test register */
 388   Test,
 389   /* 2 bit segment register */
 390   SReg2,
 391   /* 3 bit segment register */
 392   SReg3,
 393   /* 1 bit immediate */
 394   Imm1,
 395   /* 8 bit immediate */
 396   Imm8,
 397   /* 8 bit immediate sign extended */
 398   Imm8S,
 399   /* 16 bit immediate */
 400   Imm16,
 401   /* 32 bit immediate */
 402   Imm32,
 403   /* 32 bit immediate sign extended */
 404   Imm32S,
 405   /* 64 bit immediate */
 406   Imm64,
 407   /* 8bit/16bit/32bit displacements are used in different ways,
 408      depending on the instruction.  For jumps, they specify the
 409      size of the PC relative displacement, for instructions with
 410      memory operand, they specify the size of the offset relative
 411      to the base register, and for instructions with memory offset
 412      such as `mov 1234,%al' they specify the size of the offset
 413      relative to the segment base.  */
 414   /* 8 bit displacement */
 415   Disp8,
 416   /* 16 bit displacement */
 417   Disp16,
 418   /* 32 bit displacement */
 419   Disp32,
 420   /* 32 bit signed displacement */
 421   Disp32S,
 422   /* 64 bit displacement */
 423   Disp64,
 424   /* Accumulator %al/%ax/%eax/%rax */
 425   Acc,
 426   /* Floating pointer top stack register %st(0) */
 427   FloatAcc,
 428   /* Register which can be used for base or index in memory operand.  */
 429   BaseIndex,
 430   /* Register to hold in/out port addr = dx */
 431   InOutPortReg,
 432   /* Register to hold shift count = cl */
 433   ShiftCount,
 434   /* Absolute address for jump.  */
 435   JumpAbsolute,
 436   /* String insn operand with fixed es segment */
 437   EsSeg,
 438   /* RegMem is for instructions with a modrm byte where the register
 439      destination operand should be encoded in the mod and regmem fields.
 440      Normally, it will be encoded in the reg field. We add a RegMem
 441      flag to the destination register operand to indicate that it should
 442      be encoded in the regmem field.  */
 443   RegMem,
 444   /* Memory.  */
 445   Mem,
 446   /* BYTE memory. */
 447   Byte,
 448   /* WORD memory. 2 byte */
 449   Word,
 450   /* DWORD memory. 4 byte */
 451   Dword,
 452   /* FWORD memory. 6 byte */
 453   Fword,
 454   /* QWORD memory. 8 byte */
 455   Qword,
 456   /* TBYTE memory. 10 byte */
 457   Tbyte,
 458   /* XMMWORD memory. */
 459   Xmmword,
 460   /* YMMWORD memory. */
 461   Ymmword,
 462   /* Unspecified memory size.  */
 463   Unspecified,
 464   /* Any memory size.  */
 465   Anysize,
 466
 467   /* The last bitfield in i386_operand_type.  */
 468   OTMax
 469 };
 470
 471 #define OTNumOfUints \
 472   (OTMax / sizeof (unsigned int) / CHAR_BIT + 1)
 473 #define OTNumOfBits \
 474   (OTNumOfUints * sizeof (unsigned int) * CHAR_BIT)
 475
 476 /* If you get a compiler error for zero width of the unused field,
 477    comment it out.  */
 478 #define OTUnused                (OTMax + 1)
 479
 480 typedef union i386_operand_type
 481 {
 482   struct
 483     {
 484       unsigned int reg8:1;
 485       unsigned int reg16:1;
 486       unsigned int reg32:1;
 487       unsigned int reg64:1;
 488       unsigned int floatreg:1;
 489       unsigned int regmmx:1;
 490       unsigned int regxmm:1;
 491       unsigned int regymm:1;
 492       unsigned int control:1;
 493       unsigned int debug:1;
 494       unsigned int test:1;
 495       unsigned int sreg2:1;
 496       unsigned int sreg3:1;
 497       unsigned int imm1:1;
 498       unsigned int imm8:1;
 499       unsigned int imm8s:1;
 500       unsigned int imm16:1;
 501       unsigned int imm32:1;
 502       unsigned int imm32s:1;
 503       unsigned int imm64:1;
 504       unsigned int disp8:1;
 505       unsigned int disp16:1;
 506       unsigned int disp32:1;
 507       unsigned int disp32s:1;
 508       unsigned int disp64:1;
 509       unsigned int acc:1;
 510       unsigned int floatacc:1;
 511       unsigned int baseindex:1;
 512       unsigned int inoutportreg:1;
 513       unsigned int shiftcount:1;
 514       unsigned int jumpabsolute:1;
 515       unsigned int esseg:1;
 516       unsigned int regmem:1;
 517       unsigned int mem:1;
 518       unsigned int byte:1;
 519       unsigned int word:1;
 520       unsigned int dword:1;
 521       unsigned int fword:1;
 522       unsigned int qword:1;
 523       unsigned int tbyte:1;
 524       unsigned int xmmword:1;
 525       unsigned int ymmword:1;
 526       unsigned int unspecified:1;
 527       unsigned int anysize:1;
 528 #ifdef OTUnused
 529       unsigned int unused:(OTNumOfBits - OTUnused);
 530 #endif
 531     } bitfield;
 532   unsigned int array[OTNumOfUints];
 533 } i386_operand_type;
 534
 535 typedef struct insn_template
 536 {
 537   /* instruction name sans width suffix ("mov" for movl insns) */
 538   char *name;
 539
 540   /* how many operands */
 541   unsigned int operands;
 542
 543   /* base_opcode is the fundamental opcode byte without optional
 544      prefix(es).  */
 545   unsigned int base_opcode;
 546 #define Opcode_D        0x2 /* Direction bit:
 547                                set if Reg --> Regmem;
 548                                unset if Regmem --> Reg. */
 549 #define Opcode_FloatR   0x8 /* Bit to swap src/dest for float insns. */
 550 #define Opcode_FloatD 0x400 /* Direction bit for float insns. */
 551
 552   /* extension_opcode is the 3 bit extension for group <n> insns.
 553      This field is also used to store the 8-bit opcode suffix for the
 554      AMD 3DNow! instructions.
 555      If this template has no extension opcode (the usual case) use None
 556      Instructions */
 557   unsigned int extension_opcode;
 558 #define None 0xffff             /* If no extension_opcode is possible.  */
 559
 560   /* Opcode length.  */
 561   unsigned char opcode_length;
 562
 563   /* cpu feature flags */
 564   i386_cpu_flags cpu_flags;
 565
 566   /* the bits in opcode_modifier are used to generate the final opcode from
 567      the base_opcode.  These bits also are used to detect alternate forms of
 568      the same instruction */
 569   i386_opcode_modifier opcode_modifier;
 570
 571   /* operand_types[i] describes the type of operand i.  This is made
 572      by OR'ing together all of the possible type masks.  (e.g.
 573      'operand_types[i] = Reg|Imm' specifies that operand i can be
 574      either a register or an immediate operand.  */
 575   i386_operand_type operand_types[MAX_OPERANDS];
 576 }
 577 insn_template;
 578
 579 extern const insn_template i386_optab[];
 580
 581 /* these are for register name --> number & type hash lookup */
 582 typedef struct
 583 {
 584   char *reg_name;
 585   i386_operand_type reg_type;
 586   unsigned char reg_flags;
 587 #define RegRex      0x1  /* Extended register.  */
 588 #define RegRex64    0x2  /* Extended 8 bit register.  */
 589   unsigned char reg_num;
 590 #define RegRip  ((unsigned char ) ~0)
 591 #define RegEip  (RegRip - 1)
 592 /* EIZ and RIZ are fake index registers.  */
 593 #define RegEiz  (RegEip - 1)
 594 #define RegRiz  (RegEiz - 1)
 595 /* FLAT is a fake segment register (Intel mode).  */
 596 #define RegFlat     ((unsigned char) ~0)
 597   signed char dw2_regnum[2];
 598 #define Dw2Inval (-1)
 599 }
 600 reg_entry;
 601
 602 /* Entries in i386_regtab.  */
 603 #define REGNAM_AL 1
 604 #define REGNAM_AX 25
 605 #define REGNAM_EAX 41
 606
 607 extern const reg_entry i386_regtab[];
 608 extern const unsigned int i386_regtab_size;
 609
 610 typedef struct
 611 {
 612   char *seg_name;
 613   unsigned int seg_prefix;
 614 }
 615 seg_entry;
 616
 617 extern const seg_entry cs;
 618 extern const seg_entry ds;
 619 extern const seg_entry ss;
 620 extern const seg_entry es;
 621 extern const seg_entry fs;
 622 extern const seg_entry gs;