opcodes/i386-dis.c

   1 /* Print i386 instructions for GDB, the GNU debugger.
   2    Copyright 1988, 1989, 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
   3    2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010
   4    Free Software Foundation, Inc.
   5
   6    This file is part of the GNU opcodes library.
   7
   8    This library is free software; you can redistribute it and/or modify
   9    it under the terms of the GNU General Public License as published by
  10    the Free Software Foundation; either version 3, or (at your option)
  11    any later version.
  12
  13    It is distributed in the hope that it will be useful, but WITHOUT
  14    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  15    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  16    License for more details.
  17
  18    You should have received a copy of the GNU General Public License
  19    along with this program; if not, write to the Free Software
  20    Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
  21    MA 02110-1301, USA.  */
  22
  23
  24 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
  25    July 1988
  26     modified by John Hassey (hassey@dg-rtp.dg.com)
  27     x86-64 support added by Jan Hubicka (jh@suse.cz)
  28     VIA PadLock support by Michal Ludvig (mludvig@suse.cz).  */
  29
  30 /* The main tables describing the instructions is essentially a copy
  31    of the "Opcode Map" chapter (Appendix A) of the Intel 80386
  32    Programmers Manual.  Usually, there is a capital letter, followed
  33    by a small letter.  The capital letter tell the addressing mode,
  34    and the small letter tells about the operand size.  Refer to
  35    the Intel manual for details.  */
  36
  37 #include "sysdep.h"
  38 #include "dis-asm.h"
  39 #include "opintl.h"
  40 #include "opcode/i386.h"
  41 #include "libiberty.h"
  42
  43 #include <setjmp.h>
  44
  45 static int print_insn (bfd_vma, disassemble_info *);
  46 static void dofloat (int);
  47 static void OP_ST (int, int);
  48 static void OP_STi (int, int);
  49 static int putop (const char *, int);
  50 static void oappend (const char *);
  51 static void append_seg (void);
  52 static void OP_indirE (int, int);
  53 static void print_operand_value (char *, int, bfd_vma);
  54 static void OP_E_register (int, int);
  55 static void OP_E_memory (int, int);
  56 static void print_displacement (char *, bfd_vma);
  57 static void OP_E (int, int);
  58 static void OP_G (int, int);
  59 static bfd_vma get64 (void);
  60 static bfd_signed_vma get32 (void);
  61 static bfd_signed_vma get32s (void);
  62 static int get16 (void);
  63 static void set_op (bfd_vma, int);
  64 static void OP_Skip_MODRM (int, int);
  65 static void OP_REG (int, int);
  66 static void OP_IMREG (int, int);
  67 static void OP_I (int, int);
  68 static void OP_I64 (int, int);
  69 static void OP_sI (int, int);
  70 static void OP_J (int, int);
  71 static void OP_SEG (int, int);
  72 static void OP_DIR (int, int);
  73 static void OP_OFF (int, int);
  74 static void OP_OFF64 (int, int);
  75 static void ptr_reg (int, int);
  76 static void OP_ESreg (int, int);
  77 static void OP_DSreg (int, int);
  78 static void OP_C (int, int);
  79 static void OP_D (int, int);
  80 static void OP_T (int, int);
  81 static void OP_R (int, int);
  82 static void OP_MMX (int, int);
  83 static void OP_XMM (int, int);
  84 static void OP_EM (int, int);
  85 static void OP_EX (int, int);
  86 static void OP_EMC (int,int);
  87 static void OP_MXC (int,int);
  88 static void OP_MS (int, int);
  89 static void OP_XS (int, int);
  90 static void OP_M (int, int);
  91 static void OP_VEX (int, int);
  92 static void OP_EX_Vex (int, int);
  93 static void OP_EX_VexW (int, int);
  94 static void OP_EX_VexImmW (int, int);
  95 static void OP_XMM_Vex (int, int);
  96 static void OP_XMM_VexW (int, int);
  97 static void OP_REG_VexI4 (int, int);
  98 static void PCLMUL_Fixup (int, int);
  99 static void VEXI4_Fixup (int, int);
 100 static void VZERO_Fixup (int, int);
 101 static void VCMP_Fixup (int, int);
 102 static void OP_0f07 (int, int);
 103 static void OP_Monitor (int, int);
 104 static void OP_Mwait (int, int);
 105 static void NOP_Fixup1 (int, int);
 106 static void NOP_Fixup2 (int, int);
 107 static void OP_3DNowSuffix (int, int);
 108 static void CMP_Fixup (int, int);
 109 static void BadOp (void);
 110 static void REP_Fixup (int, int);
 111 static void CMPXCHG8B_Fixup (int, int);
 112 static void XMM_Fixup (int, int);
 113 static void CRC32_Fixup (int, int);
 114 static void FXSAVE_Fixup (int, int);
 115 static void OP_LWPCB_E (int, int);
 116 static void OP_LWP_E (int, int);
 117 static void OP_LWP_I (int, int);
 118 static void OP_Vex_2src_1 (int, int);
 119 static void OP_Vex_2src_2 (int, int);
 120
 121 static void MOVBE_Fixup (int, int);
 122
 123 struct dis_private {
 124   /* Points to first byte not fetched.  */
 125   bfd_byte *max_fetched;
 126   bfd_byte the_buffer[MAX_MNEM_SIZE];
 127   bfd_vma insn_start;
 128   int orig_sizeflag;
 129   jmp_buf bailout;
 130 };
 131
 132 enum address_mode
 133 {
 134   mode_16bit,
 135   mode_32bit,
 136   mode_64bit
 137 };
 138
 139 enum address_mode address_mode;
 140
 141 /* Flags for the prefixes for the current instruction.  See below.  */
 142 static int prefixes;
 143
 144 /* REX prefix the current instruction.  See below.  */
 145 static int rex;
 146 /* Bits of REX we've already used.  */
 147 static int rex_used;
 148 /* REX bits in original REX prefix ignored.  */
 149 static int rex_ignored;
 150 /* Mark parts used in the REX prefix.  When we are testing for
 151    empty prefix (for 8bit register REX extension), just mask it
 152    out.  Otherwise test for REX bit is excuse for existence of REX
 153    only in case value is nonzero.  */
 154 #define USED_REX(value)                                 \
 155   {                                                     \
 156     if (value)                                          \
 157       {                                                 \
 158         if ((rex & value))                              \
 159           rex_used |= (value) | REX_OPCODE;             \
 160       }                                                 \
 161     else                                                \
 162       rex_used |= REX_OPCODE;                           \
 163   }
 164
 165 /* Flags for prefixes which we somehow handled when printing the
 166    current instruction.  */
 167 static int used_prefixes;
 168
 169 /* Flags stored in PREFIXES.  */
 170 #define PREFIX_REPZ 1
 171 #define PREFIX_REPNZ 2
 172 #define PREFIX_LOCK 4
 173 #define PREFIX_CS 8
 174 #define PREFIX_SS 0x10
 175 #define PREFIX_DS 0x20
 176 #define PREFIX_ES 0x40
 177 #define PREFIX_FS 0x80
 178 #define PREFIX_GS 0x100
 179 #define PREFIX_DATA 0x200
 180 #define PREFIX_ADDR 0x400
 181 #define PREFIX_FWAIT 0x800
 182
 183 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
 184    to ADDR (exclusive) are valid.  Returns 1 for success, longjmps
 185    on error.  */
 186 #define FETCH_DATA(info, addr) \
 187   ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
 188    ? 1 : fetch_data ((info), (addr)))
 189
 190 static int
 191 fetch_data (struct disassemble_info *info, bfd_byte *addr)
 192 {
 193   int status;
 194   struct dis_private *priv = (struct dis_private *) info->private_data;
 195   bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer);
 196
 197   if (addr <= priv->the_buffer + MAX_MNEM_SIZE)
 198     status = (*info->read_memory_func) (start,
 199                                         priv->max_fetched,
 200                                         addr - priv->max_fetched,
 201                                         info);
 202   else
 203     status = -1;
 204   if (status != 0)
 205     {
 206       /* If we did manage to read at least one byte, then
 207          print_insn_i386 will do something sensible.  Otherwise, print
 208          an error.  We do that here because this is where we know
 209          STATUS.  */
 210       if (priv->max_fetched == priv->the_buffer)
 211         (*info->memory_error_func) (status, start, info);
 212       longjmp (priv->bailout, 1);
 213     }
 214   else
 215     priv->max_fetched = addr;
 216   return 1;
 217 }
 218
 219 #define XX { NULL, 0 }
 220 #define Bad_Opcode NULL, { { NULL, 0 } }
 221
 222 #define Eb { OP_E, b_mode }
 223 #define EbS { OP_E, b_swap_mode }
 224 #define Ev { OP_E, v_mode }
 225 #define EvS { OP_E, v_swap_mode }
 226 #define Ed { OP_E, d_mode }
 227 #define Edq { OP_E, dq_mode }
 228 #define Edqw { OP_E, dqw_mode }
 229 #define Edqb { OP_E, dqb_mode }
 230 #define Edqd { OP_E, dqd_mode }
 231 #define Eq { OP_E, q_mode }
 232 #define indirEv { OP_indirE, stack_v_mode }
 233 #define indirEp { OP_indirE, f_mode }
 234 #define stackEv { OP_E, stack_v_mode }
 235 #define Em { OP_E, m_mode }
 236 #define Ew { OP_E, w_mode }
 237 #define M { OP_M, 0 }           /* lea, lgdt, etc. */
 238 #define Ma { OP_M, a_mode }
 239 #define Mb { OP_M, b_mode }
 240 #define Md { OP_M, d_mode }
 241 #define Mo { OP_M, o_mode }
 242 #define Mp { OP_M, f_mode }             /* 32 or 48 bit memory operand for LDS, LES etc */
 243 #define Mq { OP_M, q_mode }
 244 #define Mx { OP_M, x_mode }
 245 #define Mxmm { OP_M, xmm_mode }
 246 #define Gb { OP_G, b_mode }
 247 #define Gv { OP_G, v_mode }
 248 #define Gd { OP_G, d_mode }
 249 #define Gdq { OP_G, dq_mode }
 250 #define Gm { OP_G, m_mode }
 251 #define Gw { OP_G, w_mode }
 252 #define Rd { OP_R, d_mode }
 253 #define Rm { OP_R, m_mode }
 254 #define Ib { OP_I, b_mode }
 255 #define sIb { OP_sI, b_mode }   /* sign extened byte */
 256 #define Iv { OP_I, v_mode }
 257 #define Iq { OP_I, q_mode }
 258 #define Iv64 { OP_I64, v_mode }
 259 #define Iw { OP_I, w_mode }
 260 #define I1 { OP_I, const_1_mode }
 261 #define Jb { OP_J, b_mode }
 262 #define Jv { OP_J, v_mode }
 263 #define Cm { OP_C, m_mode }
 264 #define Dm { OP_D, m_mode }
 265 #define Td { OP_T, d_mode }
 266 #define Skip_MODRM { OP_Skip_MODRM, 0 }
 267
 268 #define RMeAX { OP_REG, eAX_reg }
 269 #define RMeBX { OP_REG, eBX_reg }
 270 #define RMeCX { OP_REG, eCX_reg }
 271 #define RMeDX { OP_REG, eDX_reg }
 272 #define RMeSP { OP_REG, eSP_reg }
 273 #define RMeBP { OP_REG, eBP_reg }
 274 #define RMeSI { OP_REG, eSI_reg }
 275 #define RMeDI { OP_REG, eDI_reg }
 276 #define RMrAX { OP_REG, rAX_reg }
 277 #define RMrBX { OP_REG, rBX_reg }
 278 #define RMrCX { OP_REG, rCX_reg }
 279 #define RMrDX { OP_REG, rDX_reg }
 280 #define RMrSP { OP_REG, rSP_reg }
 281 #define RMrBP { OP_REG, rBP_reg }
 282 #define RMrSI { OP_REG, rSI_reg }
 283 #define RMrDI { OP_REG, rDI_reg }
 284 #define RMAL { OP_REG, al_reg }
 285 #define RMAL { OP_REG, al_reg }
 286 #define RMCL { OP_REG, cl_reg }
 287 #define RMDL { OP_REG, dl_reg }
 288 #define RMBL { OP_REG, bl_reg }
 289 #define RMAH { OP_REG, ah_reg }
 290 #define RMCH { OP_REG, ch_reg }
 291 #define RMDH { OP_REG, dh_reg }
 292 #define RMBH { OP_REG, bh_reg }
 293 #define RMAX { OP_REG, ax_reg }
 294 #define RMDX { OP_REG, dx_reg }
 295
 296 #define eAX { OP_IMREG, eAX_reg }
 297 #define eBX { OP_IMREG, eBX_reg }
 298 #define eCX { OP_IMREG, eCX_reg }
 299 #define eDX { OP_IMREG, eDX_reg }
 300 #define eSP { OP_IMREG, eSP_reg }
 301 #define eBP { OP_IMREG, eBP_reg }
 302 #define eSI { OP_IMREG, eSI_reg }
 303 #define eDI { OP_IMREG, eDI_reg }
 304 #define AL { OP_IMREG, al_reg }
 305 #define CL { OP_IMREG, cl_reg }
 306 #define DL { OP_IMREG, dl_reg }
 307 #define BL { OP_IMREG, bl_reg }
 308 #define AH { OP_IMREG, ah_reg }
 309 #define CH { OP_IMREG, ch_reg }
 310 #define DH { OP_IMREG, dh_reg }
 311 #define BH { OP_IMREG, bh_reg }
 312 #define AX { OP_IMREG, ax_reg }
 313 #define DX { OP_IMREG, dx_reg }
 314 #define zAX { OP_IMREG, z_mode_ax_reg }
 315 #define indirDX { OP_IMREG, indir_dx_reg }
 316
 317 #define Sw { OP_SEG, w_mode }
 318 #define Sv { OP_SEG, v_mode }
 319 #define Ap { OP_DIR, 0 }
 320 #define Ob { OP_OFF64, b_mode }
 321 #define Ov { OP_OFF64, v_mode }
 322 #define Xb { OP_DSreg, eSI_reg }
 323 #define Xv { OP_DSreg, eSI_reg }
 324 #define Xz { OP_DSreg, eSI_reg }
 325 #define Yb { OP_ESreg, eDI_reg }
 326 #define Yv { OP_ESreg, eDI_reg }
 327 #define DSBX { OP_DSreg, eBX_reg }
 328
 329 #define es { OP_REG, es_reg }
 330 #define ss { OP_REG, ss_reg }
 331 #define cs { OP_REG, cs_reg }
 332 #define ds { OP_REG, ds_reg }
 333 #define fs { OP_REG, fs_reg }
 334 #define gs { OP_REG, gs_reg }
 335
 336 #define MX { OP_MMX, 0 }
 337 #define XM { OP_XMM, 0 }
 338 #define XMScalar { OP_XMM, scalar_mode }
 339 #define XMM { OP_XMM, xmm_mode }
 340 #define EM { OP_EM, v_mode }
 341 #define EMS { OP_EM, v_swap_mode }
 342 #define EMd { OP_EM, d_mode }
 343 #define EMx { OP_EM, x_mode }
 344 #define EXw { OP_EX, w_mode }
 345 #define EXd { OP_EX, d_mode }
 346 #define EXdScalar { OP_EX, d_scalar_mode }
 347 #define EXdS { OP_EX, d_swap_mode }
 348 #define EXq { OP_EX, q_mode }
 349 #define EXqScalar { OP_EX, q_scalar_mode }
 350 #define EXqScalarS { OP_EX, q_scalar_swap_mode }
 351 #define EXqS { OP_EX, q_swap_mode }
 352 #define EXx { OP_EX, x_mode }
 353 #define EXxS { OP_EX, x_swap_mode }
 354 #define EXxmm { OP_EX, xmm_mode }
 355 #define EXxmmq { OP_EX, xmmq_mode }
 356 #define EXymmq { OP_EX, ymmq_mode }
 357 #define EXVexWdq { OP_EX, vex_w_dq_mode }
 358 #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }
 359 #define MS { OP_MS, v_mode }
 360 #define XS { OP_XS, v_mode }
 361 #define EMCq { OP_EMC, q_mode }
 362 #define MXC { OP_MXC, 0 }
 363 #define OPSUF { OP_3DNowSuffix, 0 }
 364 #define CMP { CMP_Fixup, 0 }
 365 #define XMM0 { XMM_Fixup, 0 }
 366 #define FXSAVE { FXSAVE_Fixup, 0 }
 367 #define Vex_2src_1 { OP_Vex_2src_1, 0 }
 368 #define Vex_2src_2 { OP_Vex_2src_2, 0 }
 369
 370 #define Vex { OP_VEX, vex_mode }
 371 #define VexScalar { OP_VEX, vex_scalar_mode }
 372 #define Vex128 { OP_VEX, vex128_mode }
 373 #define Vex256 { OP_VEX, vex256_mode }
 374 #define VexI4 { VEXI4_Fixup, 0}
 375 #define EXdVex { OP_EX_Vex, d_mode }
 376 #define EXdVexS { OP_EX_Vex, d_swap_mode }
 377 #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode }
 378 #define EXqVex { OP_EX_Vex, q_mode }
 379 #define EXqVexS { OP_EX_Vex, q_swap_mode }
 380 #define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode }
 381 #define EXVexW { OP_EX_VexW, x_mode }
 382 #define EXdVexW { OP_EX_VexW, d_mode }
 383 #define EXqVexW { OP_EX_VexW, q_mode }
 384 #define EXVexImmW { OP_EX_VexImmW, x_mode }
 385 #define XMVex { OP_XMM_Vex, 0 }
 386 #define XMVexScalar { OP_XMM_Vex, scalar_mode }
 387 #define XMVexW { OP_XMM_VexW, 0 }
 388 #define XMVexI4 { OP_REG_VexI4, x_mode }
 389 #define PCLMUL { PCLMUL_Fixup, 0 }
 390 #define VZERO { VZERO_Fixup, 0 }
 391 #define VCMP { VCMP_Fixup, 0 }
 392
 393 /* Used handle "rep" prefix for string instructions.  */
 394 #define Xbr { REP_Fixup, eSI_reg }
 395 #define Xvr { REP_Fixup, eSI_reg }
 396 #define Ybr { REP_Fixup, eDI_reg }
 397 #define Yvr { REP_Fixup, eDI_reg }
 398 #define Yzr { REP_Fixup, eDI_reg }
 399 #define indirDXr { REP_Fixup, indir_dx_reg }
 400 #define ALr { REP_Fixup, al_reg }
 401 #define eAXr { REP_Fixup, eAX_reg }
 402
 403 #define cond_jump_flag { NULL, cond_jump_mode }
 404 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
 405
 406 /* bits in sizeflag */
 407 #define SUFFIX_ALWAYS 4
 408 #define AFLAG 2
 409 #define DFLAG 1
 410
 411 enum
 412 {
 413   /* byte operand */
 414   b_mode = 1,
 415   /* byte operand with operand swapped */
 416   b_swap_mode,
 417   /* operand size depends on prefixes */
 418   v_mode,
 419   /* operand size depends on prefixes with operand swapped */
 420   v_swap_mode,
 421   /* word operand */
 422   w_mode,
 423   /* double word operand  */
 424   d_mode,
 425   /* double word operand with operand swapped */
 426   d_swap_mode,
 427   /* quad word operand */
 428   q_mode,
 429   /* quad word operand with operand swapped */
 430   q_swap_mode,
 431   /* ten-byte operand */
 432   t_mode,
 433   /* 16-byte XMM or 32-byte YMM operand */
 434   x_mode,
 435   /* 16-byte XMM or 32-byte YMM operand with operand swapped */
 436   x_swap_mode,
 437   /* 16-byte XMM operand */
 438   xmm_mode,
 439   /* 16-byte XMM or quad word operand */
 440   xmmq_mode,
 441   /* 32-byte YMM or quad word operand */
 442   ymmq_mode,
 443   /* d_mode in 32bit, q_mode in 64bit mode.  */
 444   m_mode,
 445   /* pair of v_mode operands */
 446   a_mode,
 447   cond_jump_mode,
 448   loop_jcxz_mode,
 449   /* operand size depends on REX prefixes.  */
 450   dq_mode,
 451   /* registers like dq_mode, memory like w_mode.  */
 452   dqw_mode,
 453   /* 4- or 6-byte pointer operand */
 454   f_mode,
 455   const_1_mode,
 456   /* v_mode for stack-related opcodes.  */
 457   stack_v_mode,
 458   /* non-quad operand size depends on prefixes */
 459   z_mode,
 460   /* 16-byte operand */
 461   o_mode,
 462   /* registers like dq_mode, memory like b_mode.  */
 463   dqb_mode,
 464   /* registers like dq_mode, memory like d_mode.  */
 465   dqd_mode,
 466   /* normal vex mode */
 467   vex_mode,
 468   /* 128bit vex mode */
 469   vex128_mode,
 470   /* 256bit vex mode */
 471   vex256_mode,
 472   /* operand size depends on the VEX.W bit.  */
 473   vex_w_dq_mode,
 474
 475   /* scalar, ignore vector length.  */
 476   scalar_mode,
 477   /* like d_mode, ignore vector length.  */
 478   d_scalar_mode,
 479   /* like d_swap_mode, ignore vector length.  */
 480   d_scalar_swap_mode,
 481   /* like q_mode, ignore vector length.  */
 482   q_scalar_mode,
 483   /* like q_swap_mode, ignore vector length.  */
 484   q_scalar_swap_mode,
 485   /* like vex_mode, ignore vector length.  */
 486   vex_scalar_mode,
 487   /* like vex_w_dq_mode, ignore vector length.  */
 488   vex_scalar_w_dq_mode,
 489
 490   es_reg,
 491   cs_reg,
 492   ss_reg,
 493   ds_reg,
 494   fs_reg,
 495   gs_reg,
 496
 497   eAX_reg,
 498   eCX_reg,
 499   eDX_reg,
 500   eBX_reg,
 501   eSP_reg,
 502   eBP_reg,
 503   eSI_reg,
 504   eDI_reg,
 505
 506   al_reg,
 507   cl_reg,
 508   dl_reg,
 509   bl_reg,
 510   ah_reg,
 511   ch_reg,
 512   dh_reg,
 513   bh_reg,
 514
 515   ax_reg,
 516   cx_reg,
 517   dx_reg,
 518   bx_reg,
 519   sp_reg,
 520   bp_reg,
 521   si_reg,
 522   di_reg,
 523
 524   rAX_reg,
 525   rCX_reg,
 526   rDX_reg,
 527   rBX_reg,
 528   rSP_reg,
 529   rBP_reg,
 530   rSI_reg,
 531   rDI_reg,
 532
 533   z_mode_ax_reg,
 534   indir_dx_reg
 535 };
 536
 537 enum
 538 {
 539   FLOATCODE = 1,
 540   USE_REG_TABLE,
 541   USE_MOD_TABLE,
 542   USE_RM_TABLE,
 543   USE_PREFIX_TABLE,
 544   USE_X86_64_TABLE,
 545   USE_3BYTE_TABLE,
 546   USE_XOP_8F_TABLE,
 547   USE_VEX_C4_TABLE,
 548   USE_VEX_C5_TABLE,
 549   USE_VEX_LEN_TABLE,
 550   USE_VEX_W_TABLE
 551 };
 552
 553 #define FLOAT                   NULL, { { NULL, FLOATCODE } }
 554
 555 #define DIS386(T, I)            NULL, { { NULL, (T)}, { NULL,  (I) } }
 556 #define REG_TABLE(I)            DIS386 (USE_REG_TABLE, (I))
 557 #define MOD_TABLE(I)            DIS386 (USE_MOD_TABLE, (I))
 558 #define RM_TABLE(I)             DIS386 (USE_RM_TABLE, (I))
 559 #define PREFIX_TABLE(I)         DIS386 (USE_PREFIX_TABLE, (I))
 560 #define X86_64_TABLE(I)         DIS386 (USE_X86_64_TABLE, (I))
 561 #define THREE_BYTE_TABLE(I)     DIS386 (USE_3BYTE_TABLE, (I))
 562 #define XOP_8F_TABLE(I)         DIS386 (USE_XOP_8F_TABLE, (I))
 563 #define VEX_C4_TABLE(I)         DIS386 (USE_VEX_C4_TABLE, (I))
 564 #define VEX_C5_TABLE(I)         DIS386 (USE_VEX_C5_TABLE, (I))
 565 #define VEX_LEN_TABLE(I)        DIS386 (USE_VEX_LEN_TABLE, (I))
 566 #define VEX_W_TABLE(I)          DIS386 (USE_VEX_W_TABLE, (I))
 567
 568 enum
 569 {
 570   REG_80 = 0,
 571   REG_81,
 572   REG_82,
 573   REG_8F,
 574   REG_C0,
 575   REG_C1,
 576   REG_C6,
 577   REG_C7,
 578   REG_D0,
 579   REG_D1,
 580   REG_D2,
 581   REG_D3,
 582   REG_F6,
 583   REG_F7,
 584   REG_FE,
 585   REG_FF,
 586   REG_0F00,
 587   REG_0F01,
 588   REG_0F0D,
 589   REG_0F18,
 590   REG_0F71,
 591   REG_0F72,
 592   REG_0F73,
 593   REG_0FA6,
 594   REG_0FA7,
 595   REG_0FAE,
 596   REG_0FBA,
 597   REG_0FC7,
 598   REG_VEX_71,
 599   REG_VEX_72,
 600   REG_VEX_73,
 601   REG_VEX_AE,
 602   REG_XOP_LWPCB,
 603   REG_XOP_LWP
 604 };
 605
 606 enum
 607 {
 608   MOD_8D = 0,
 609   MOD_0F01_REG_0,
 610   MOD_0F01_REG_1,
 611   MOD_0F01_REG_2,
 612   MOD_0F01_REG_3,
 613   MOD_0F01_REG_7,
 614   MOD_0F12_PREFIX_0,
 615   MOD_0F13,
 616   MOD_0F16_PREFIX_0,
 617   MOD_0F17,
 618   MOD_0F18_REG_0,
 619   MOD_0F18_REG_1,
 620   MOD_0F18_REG_2,
 621   MOD_0F18_REG_3,
 622   MOD_0F20,
 623   MOD_0F21,
 624   MOD_0F22,
 625   MOD_0F23,
 626   MOD_0F24,
 627   MOD_0F26,
 628   MOD_0F2B_PREFIX_0,
 629   MOD_0F2B_PREFIX_1,
 630   MOD_0F2B_PREFIX_2,
 631   MOD_0F2B_PREFIX_3,
 632   MOD_0F51,
 633   MOD_0F71_REG_2,
 634   MOD_0F71_REG_4,
 635   MOD_0F71_REG_6,
 636   MOD_0F72_REG_2,
 637   MOD_0F72_REG_4,
 638   MOD_0F72_REG_6,
 639   MOD_0F73_REG_2,
 640   MOD_0F73_REG_3,
 641   MOD_0F73_REG_6,
 642   MOD_0F73_REG_7,
 643   MOD_0FAE_REG_0,
 644   MOD_0FAE_REG_1,
 645   MOD_0FAE_REG_2,
 646   MOD_0FAE_REG_3,
 647   MOD_0FAE_REG_4,
 648   MOD_0FAE_REG_5,
 649   MOD_0FAE_REG_6,
 650   MOD_0FAE_REG_7,
 651   MOD_0FB2,
 652   MOD_0FB4,
 653   MOD_0FB5,
 654   MOD_0FC7_REG_6,
 655   MOD_0FC7_REG_7,
 656   MOD_0FD7,
 657   MOD_0FE7_PREFIX_2,
 658   MOD_0FF0_PREFIX_3,
 659   MOD_0F382A_PREFIX_2,
 660   MOD_62_32BIT,
 661   MOD_C4_32BIT,
 662   MOD_C5_32BIT,
 663   MOD_VEX_12_PREFIX_0,
 664   MOD_VEX_13,
 665   MOD_VEX_16_PREFIX_0,
 666   MOD_VEX_17,
 667   MOD_VEX_2B,
 668   MOD_VEX_50,
 669   MOD_VEX_71_REG_2,
 670   MOD_VEX_71_REG_4,
 671   MOD_VEX_71_REG_6,
 672   MOD_VEX_72_REG_2,
 673   MOD_VEX_72_REG_4,
 674   MOD_VEX_72_REG_6,
 675   MOD_VEX_73_REG_2,
 676   MOD_VEX_73_REG_3,
 677   MOD_VEX_73_REG_6,
 678   MOD_VEX_73_REG_7,
 679   MOD_VEX_AE_REG_2,
 680   MOD_VEX_AE_REG_3,
 681   MOD_VEX_D7_PREFIX_2,
 682   MOD_VEX_E7_PREFIX_2,
 683   MOD_VEX_F0_PREFIX_3,
 684   MOD_VEX_3818_PREFIX_2,
 685   MOD_VEX_3819_PREFIX_2,
 686   MOD_VEX_381A_PREFIX_2,
 687   MOD_VEX_382A_PREFIX_2,
 688   MOD_VEX_382C_PREFIX_2,
 689   MOD_VEX_382D_PREFIX_2,
 690   MOD_VEX_382E_PREFIX_2,
 691   MOD_VEX_382F_PREFIX_2
 692 };
 693
 694 enum
 695 {
 696   RM_0F01_REG_0 = 0,
 697   RM_0F01_REG_1,
 698   RM_0F01_REG_2,
 699   RM_0F01_REG_3,
 700   RM_0F01_REG_7,
 701   RM_0FAE_REG_5,
 702   RM_0FAE_REG_6,
 703   RM_0FAE_REG_7
 704 };
 705
 706 enum
 707 {
 708   PREFIX_90 = 0,
 709   PREFIX_0F10,
 710   PREFIX_0F11,
 711   PREFIX_0F12,
 712   PREFIX_0F16,
 713   PREFIX_0F2A,
 714   PREFIX_0F2B,
 715   PREFIX_0F2C,
 716   PREFIX_0F2D,
 717   PREFIX_0F2E,
 718   PREFIX_0F2F,
 719   PREFIX_0F51,
 720   PREFIX_0F52,
 721   PREFIX_0F53,
 722   PREFIX_0F58,
 723   PREFIX_0F59,
 724   PREFIX_0F5A,
 725   PREFIX_0F5B,
 726   PREFIX_0F5C,
 727   PREFIX_0F5D,
 728   PREFIX_0F5E,
 729   PREFIX_0F5F,
 730   PREFIX_0F60,
 731   PREFIX_0F61,
 732   PREFIX_0F62,
 733   PREFIX_0F6C,
 734   PREFIX_0F6D,
 735   PREFIX_0F6F,
 736   PREFIX_0F70,
 737   PREFIX_0F73_REG_3,
 738   PREFIX_0F73_REG_7,
 739   PREFIX_0F78,
 740   PREFIX_0F79,
 741   PREFIX_0F7C,
 742   PREFIX_0F7D,
 743   PREFIX_0F7E,
 744   PREFIX_0F7F,
 745   PREFIX_0FB8,
 746   PREFIX_0FBD,
 747   PREFIX_0FC2,
 748   PREFIX_0FC3,
 749   PREFIX_0FC7_REG_6,
 750   PREFIX_0FD0,
 751   PREFIX_0FD6,
 752   PREFIX_0FE6,
 753   PREFIX_0FE7,
 754   PREFIX_0FF0,
 755   PREFIX_0FF7,
 756   PREFIX_0F3810,
 757   PREFIX_0F3814,
 758   PREFIX_0F3815,
 759   PREFIX_0F3817,
 760   PREFIX_0F3820,
 761   PREFIX_0F3821,
 762   PREFIX_0F3822,
 763   PREFIX_0F3823,
 764   PREFIX_0F3824,
 765   PREFIX_0F3825,
 766   PREFIX_0F3828,
 767   PREFIX_0F3829,
 768   PREFIX_0F382A,
 769   PREFIX_0F382B,
 770   PREFIX_0F3830,
 771   PREFIX_0F3831,
 772   PREFIX_0F3832,
 773   PREFIX_0F3833,
 774   PREFIX_0F3834,
 775   PREFIX_0F3835,
 776   PREFIX_0F3837,
 777   PREFIX_0F3838,
 778   PREFIX_0F3839,
 779   PREFIX_0F383A,
 780   PREFIX_0F383B,
 781   PREFIX_0F383C,
 782   PREFIX_0F383D,
 783   PREFIX_0F383E,
 784   PREFIX_0F383F,
 785   PREFIX_0F3840,
 786   PREFIX_0F3841,
 787   PREFIX_0F3880,
 788   PREFIX_0F3881,
 789   PREFIX_0F38DB,
 790   PREFIX_0F38DC,
 791   PREFIX_0F38DD,
 792   PREFIX_0F38DE,
 793   PREFIX_0F38DF,
 794   PREFIX_0F38F0,
 795   PREFIX_0F38F1,
 796   PREFIX_0F3A08,
 797   PREFIX_0F3A09,
 798   PREFIX_0F3A0A,
 799   PREFIX_0F3A0B,
 800   PREFIX_0F3A0C,
 801   PREFIX_0F3A0D,
 802   PREFIX_0F3A0E,
 803   PREFIX_0F3A14,
 804   PREFIX_0F3A15,
 805   PREFIX_0F3A16,
 806   PREFIX_0F3A17,
 807   PREFIX_0F3A20,
 808   PREFIX_0F3A21,
 809   PREFIX_0F3A22,
 810   PREFIX_0F3A40,
 811   PREFIX_0F3A41,
 812   PREFIX_0F3A42,
 813   PREFIX_0F3A44,
 814   PREFIX_0F3A60,
 815   PREFIX_0F3A61,
 816   PREFIX_0F3A62,
 817   PREFIX_0F3A63,
 818   PREFIX_0F3ADF,
 819   PREFIX_VEX_10,
 820   PREFIX_VEX_11,
 821   PREFIX_VEX_12,
 822   PREFIX_VEX_16,
 823   PREFIX_VEX_2A,
 824   PREFIX_VEX_2C,
 825   PREFIX_VEX_2D,
 826   PREFIX_VEX_2E,
 827   PREFIX_VEX_2F,
 828   PREFIX_VEX_51,
 829   PREFIX_VEX_52,
 830   PREFIX_VEX_53,
 831   PREFIX_VEX_58,
 832   PREFIX_VEX_59,
 833   PREFIX_VEX_5A,
 834   PREFIX_VEX_5B,
 835   PREFIX_VEX_5C,
 836   PREFIX_VEX_5D,
 837   PREFIX_VEX_5E,
 838   PREFIX_VEX_5F,
 839   PREFIX_VEX_60,
 840   PREFIX_VEX_61,
 841   PREFIX_VEX_62,
 842   PREFIX_VEX_63,
 843   PREFIX_VEX_64,
 844   PREFIX_VEX_65,
 845   PREFIX_VEX_66,
 846   PREFIX_VEX_67,
 847   PREFIX_VEX_68,
 848   PREFIX_VEX_69,
 849   PREFIX_VEX_6A,
 850   PREFIX_VEX_6B,
 851   PREFIX_VEX_6C,
 852   PREFIX_VEX_6D,
 853   PREFIX_VEX_6E,
 854   PREFIX_VEX_6F,
 855   PREFIX_VEX_70,
 856   PREFIX_VEX_71_REG_2,
 857   PREFIX_VEX_71_REG_4,
 858   PREFIX_VEX_71_REG_6,
 859   PREFIX_VEX_72_REG_2,
 860   PREFIX_VEX_72_REG_4,
 861   PREFIX_VEX_72_REG_6,
 862   PREFIX_VEX_73_REG_2,
 863   PREFIX_VEX_73_REG_3,
 864   PREFIX_VEX_73_REG_6,
 865   PREFIX_VEX_73_REG_7,
 866   PREFIX_VEX_74,
 867   PREFIX_VEX_75,
 868   PREFIX_VEX_76,
 869   PREFIX_VEX_77,
 870   PREFIX_VEX_7C,
 871   PREFIX_VEX_7D,
 872   PREFIX_VEX_7E,
 873   PREFIX_VEX_7F,
 874   PREFIX_VEX_C2,
 875   PREFIX_VEX_C4,
 876   PREFIX_VEX_C5,
 877   PREFIX_VEX_D0,
 878   PREFIX_VEX_D1,
 879   PREFIX_VEX_D2,
 880   PREFIX_VEX_D3,
 881   PREFIX_VEX_D4,
 882   PREFIX_VEX_D5,
 883   PREFIX_VEX_D6,
 884   PREFIX_VEX_D7,
 885   PREFIX_VEX_D8,
 886   PREFIX_VEX_D9,
 887   PREFIX_VEX_DA,
 888   PREFIX_VEX_DB,
 889   PREFIX_VEX_DC,
 890   PREFIX_VEX_DD,
 891   PREFIX_VEX_DE,
 892   PREFIX_VEX_DF,
 893   PREFIX_VEX_E0,
 894   PREFIX_VEX_E1,
 895   PREFIX_VEX_E2,
 896   PREFIX_VEX_E3,
 897   PREFIX_VEX_E4,
 898   PREFIX_VEX_E5,
 899   PREFIX_VEX_E6,
 900   PREFIX_VEX_E7,
 901   PREFIX_VEX_E8,
 902   PREFIX_VEX_E9,
 903   PREFIX_VEX_EA,
 904   PREFIX_VEX_EB,
 905   PREFIX_VEX_EC,
 906   PREFIX_VEX_ED,
 907   PREFIX_VEX_EE,
 908   PREFIX_VEX_EF,
 909   PREFIX_VEX_F0,
 910   PREFIX_VEX_F1,
 911   PREFIX_VEX_F2,
 912   PREFIX_VEX_F3,
 913   PREFIX_VEX_F4,
 914   PREFIX_VEX_F5,
 915   PREFIX_VEX_F6,
 916   PREFIX_VEX_F7,
 917   PREFIX_VEX_F8,
 918   PREFIX_VEX_F9,
 919   PREFIX_VEX_FA,
 920   PREFIX_VEX_FB,
 921   PREFIX_VEX_FC,
 922   PREFIX_VEX_FD,
 923   PREFIX_VEX_FE,
 924   PREFIX_VEX_3800,
 925   PREFIX_VEX_3801,
 926   PREFIX_VEX_3802,
 927   PREFIX_VEX_3803,
 928   PREFIX_VEX_3804,
 929   PREFIX_VEX_3805,
 930   PREFIX_VEX_3806,
 931   PREFIX_VEX_3807,
 932   PREFIX_VEX_3808,
 933   PREFIX_VEX_3809,
 934   PREFIX_VEX_380A,
 935   PREFIX_VEX_380B,
 936   PREFIX_VEX_380C,
 937   PREFIX_VEX_380D,
 938   PREFIX_VEX_380E,
 939   PREFIX_VEX_380F,
 940   PREFIX_VEX_3817,
 941   PREFIX_VEX_3818,
 942   PREFIX_VEX_3819,
 943   PREFIX_VEX_381A,
 944   PREFIX_VEX_381C,
 945   PREFIX_VEX_381D,
 946   PREFIX_VEX_381E,
 947   PREFIX_VEX_3820,
 948   PREFIX_VEX_3821,
 949   PREFIX_VEX_3822,
 950   PREFIX_VEX_3823,
 951   PREFIX_VEX_3824,
 952   PREFIX_VEX_3825,
 953   PREFIX_VEX_3828,
 954   PREFIX_VEX_3829,
 955   PREFIX_VEX_382A,
 956   PREFIX_VEX_382B,
 957   PREFIX_VEX_382C,
 958   PREFIX_VEX_382D,
 959   PREFIX_VEX_382E,
 960   PREFIX_VEX_382F,
 961   PREFIX_VEX_3830,
 962   PREFIX_VEX_3831,
 963   PREFIX_VEX_3832,
 964   PREFIX_VEX_3833,
 965   PREFIX_VEX_3834,
 966   PREFIX_VEX_3835,
 967   PREFIX_VEX_3837,
 968   PREFIX_VEX_3838,
 969   PREFIX_VEX_3839,
 970   PREFIX_VEX_383A,
 971   PREFIX_VEX_383B,
 972   PREFIX_VEX_383C,
 973   PREFIX_VEX_383D,
 974   PREFIX_VEX_383E,
 975   PREFIX_VEX_383F,
 976   PREFIX_VEX_3840,
 977   PREFIX_VEX_3841,
 978   PREFIX_VEX_3896,
 979   PREFIX_VEX_3897,
 980   PREFIX_VEX_3898,
 981   PREFIX_VEX_3899,
 982   PREFIX_VEX_389A,
 983   PREFIX_VEX_389B,
 984   PREFIX_VEX_389C,
 985   PREFIX_VEX_389D,
 986   PREFIX_VEX_389E,
 987   PREFIX_VEX_389F,
 988   PREFIX_VEX_38A6,
 989   PREFIX_VEX_38A7,
 990   PREFIX_VEX_38A8,
 991   PREFIX_VEX_38A9,
 992   PREFIX_VEX_38AA,
 993   PREFIX_VEX_38AB,
 994   PREFIX_VEX_38AC,
 995   PREFIX_VEX_38AD,
 996   PREFIX_VEX_38AE,
 997   PREFIX_VEX_38AF,
 998   PREFIX_VEX_38B6,
 999   PREFIX_VEX_38B7,
1000   PREFIX_VEX_38B8,
1001   PREFIX_VEX_38B9,
1002   PREFIX_VEX_38BA,
1003   PREFIX_VEX_38BB,
1004   PREFIX_VEX_38BC,
1005   PREFIX_VEX_38BD,
1006   PREFIX_VEX_38BE,
1007   PREFIX_VEX_38BF,
1008   PREFIX_VEX_38DB,
1009   PREFIX_VEX_38DC,
1010   PREFIX_VEX_38DD,
1011   PREFIX_VEX_38DE,
1012   PREFIX_VEX_38DF,
1013   PREFIX_VEX_3A04,
1014   PREFIX_VEX_3A05,
1015   PREFIX_VEX_3A06,
1016   PREFIX_VEX_3A08,
1017   PREFIX_VEX_3A09,
1018   PREFIX_VEX_3A0A,
1019   PREFIX_VEX_3A0B,
1020   PREFIX_VEX_3A0C,
1021   PREFIX_VEX_3A0D,
1022   PREFIX_VEX_3A0E,
1023   PREFIX_VEX_3A0F,
1024   PREFIX_VEX_3A14,
1025   PREFIX_VEX_3A15,
1026   PREFIX_VEX_3A16,
1027   PREFIX_VEX_3A17,
1028   PREFIX_VEX_3A18,
1029   PREFIX_VEX_3A19,
1030   PREFIX_VEX_3A20,
1031   PREFIX_VEX_3A21,
1032   PREFIX_VEX_3A22,
1033   PREFIX_VEX_3A40,
1034   PREFIX_VEX_3A41,
1035   PREFIX_VEX_3A42,
1036   PREFIX_VEX_3A44,
1037   PREFIX_VEX_3A48,
1038   PREFIX_VEX_3A49,
1039   PREFIX_VEX_3A4A,
1040   PREFIX_VEX_3A4B,
1041   PREFIX_VEX_3A4C,
1042   PREFIX_VEX_3A5C,
1043   PREFIX_VEX_3A5D,
1044   PREFIX_VEX_3A5E,
1045   PREFIX_VEX_3A5F,
1046   PREFIX_VEX_3A60,
1047   PREFIX_VEX_3A61,
1048   PREFIX_VEX_3A62,
1049   PREFIX_VEX_3A63,
1050   PREFIX_VEX_3A68,
1051   PREFIX_VEX_3A69,
1052   PREFIX_VEX_3A6A,
1053   PREFIX_VEX_3A6B,
1054   PREFIX_VEX_3A6C,
1055   PREFIX_VEX_3A6D,
1056   PREFIX_VEX_3A6E,
1057   PREFIX_VEX_3A6F,
1058   PREFIX_VEX_3A78,
1059   PREFIX_VEX_3A79,
1060   PREFIX_VEX_3A7A,
1061   PREFIX_VEX_3A7B,
1062   PREFIX_VEX_3A7C,
1063   PREFIX_VEX_3A7D,
1064   PREFIX_VEX_3A7E,
1065   PREFIX_VEX_3A7F,
1066   PREFIX_VEX_3ADF
1067 };
1068
1069 enum
1070 {
1071   X86_64_06 = 0,
1072   X86_64_07,
1073   X86_64_0D,
1074   X86_64_16,
1075   X86_64_17,
1076   X86_64_1E,
1077   X86_64_1F,
1078   X86_64_27,
1079   X86_64_2F,
1080   X86_64_37,
1081   X86_64_3F,
1082   X86_64_60,
1083   X86_64_61,
1084   X86_64_62,
1085   X86_64_63,
1086   X86_64_6D,
1087   X86_64_6F,
1088   X86_64_9A,
1089   X86_64_C4,
1090   X86_64_C5,
1091   X86_64_CE,
1092   X86_64_D4,
1093   X86_64_D5,
1094   X86_64_EA,
1095   X86_64_0F01_REG_0,
1096   X86_64_0F01_REG_1,
1097   X86_64_0F01_REG_2,
1098   X86_64_0F01_REG_3
1099 };
1100
1101 enum
1102 {
1103   THREE_BYTE_0F38 = 0,
1104   THREE_BYTE_0F3A,
1105   THREE_BYTE_0F7A
1106 };
1107
1108 enum
1109 {
1110   XOP_08 = 0,
1111   XOP_09,
1112   XOP_0A
1113 };
1114
1115 enum
1116 {
1117   VEX_0F = 0,
1118   VEX_0F38,
1119   VEX_0F3A
1120 };
1121
1122 enum
1123 {
1124   VEX_LEN_10_P_1 = 0,
1125   VEX_LEN_10_P_3,
1126   VEX_LEN_11_P_1,
1127   VEX_LEN_11_P_3,
1128   VEX_LEN_12_P_0_M_0,
1129   VEX_LEN_12_P_0_M_1,
1130   VEX_LEN_12_P_2,
1131   VEX_LEN_13_M_0,
1132   VEX_LEN_16_P_0_M_0,
1133   VEX_LEN_16_P_0_M_1,
1134   VEX_LEN_16_P_2,
1135   VEX_LEN_17_M_0,
1136   VEX_LEN_2A_P_1,
1137   VEX_LEN_2A_P_3,
1138   VEX_LEN_2C_P_1,
1139   VEX_LEN_2C_P_3,
1140   VEX_LEN_2D_P_1,
1141   VEX_LEN_2D_P_3,
1142   VEX_LEN_2E_P_0,
1143   VEX_LEN_2E_P_2,
1144   VEX_LEN_2F_P_0,
1145   VEX_LEN_2F_P_2,
1146   VEX_LEN_51_P_1,
1147   VEX_LEN_51_P_3,
1148   VEX_LEN_52_P_1,
1149   VEX_LEN_53_P_1,
1150   VEX_LEN_58_P_1,
1151   VEX_LEN_58_P_3,
1152   VEX_LEN_59_P_1,
1153   VEX_LEN_59_P_3,
1154   VEX_LEN_5A_P_1,
1155   VEX_LEN_5A_P_3,
1156   VEX_LEN_5C_P_1,
1157   VEX_LEN_5C_P_3,
1158   VEX_LEN_5D_P_1,
1159   VEX_LEN_5D_P_3,
1160   VEX_LEN_5E_P_1,
1161   VEX_LEN_5E_P_3,
1162   VEX_LEN_5F_P_1,
1163   VEX_LEN_5F_P_3,
1164   VEX_LEN_60_P_2,
1165   VEX_LEN_61_P_2,
1166   VEX_LEN_62_P_2,
1167   VEX_LEN_63_P_2,
1168   VEX_LEN_64_P_2,
1169   VEX_LEN_65_P_2,
1170   VEX_LEN_66_P_2,
1171   VEX_LEN_67_P_2,
1172   VEX_LEN_68_P_2,
1173   VEX_LEN_69_P_2,
1174   VEX_LEN_6A_P_2,
1175   VEX_LEN_6B_P_2,
1176   VEX_LEN_6C_P_2,
1177   VEX_LEN_6D_P_2,
1178   VEX_LEN_6E_P_2,
1179   VEX_LEN_70_P_1,
1180   VEX_LEN_70_P_2,
1181   VEX_LEN_70_P_3,
1182   VEX_LEN_71_R_2_P_2,
1183   VEX_LEN_71_R_4_P_2,
1184   VEX_LEN_71_R_6_P_2,
1185   VEX_LEN_72_R_2_P_2,
1186   VEX_LEN_72_R_4_P_2,
1187   VEX_LEN_72_R_6_P_2,
1188   VEX_LEN_73_R_2_P_2,
1189   VEX_LEN_73_R_3_P_2,
1190   VEX_LEN_73_R_6_P_2,
1191   VEX_LEN_73_R_7_P_2,
1192   VEX_LEN_74_P_2,
1193   VEX_LEN_75_P_2,
1194   VEX_LEN_76_P_2,
1195   VEX_LEN_7E_P_1,
1196   VEX_LEN_7E_P_2,
1197   VEX_LEN_AE_R_2_M_0,
1198   VEX_LEN_AE_R_3_M_0,
1199   VEX_LEN_C2_P_1,
1200   VEX_LEN_C2_P_3,
1201   VEX_LEN_C4_P_2,
1202   VEX_LEN_C5_P_2,
1203   VEX_LEN_D1_P_2,
1204   VEX_LEN_D2_P_2,
1205   VEX_LEN_D3_P_2,
1206   VEX_LEN_D4_P_2,
1207   VEX_LEN_D5_P_2,
1208   VEX_LEN_D6_P_2,
1209   VEX_LEN_D7_P_2_M_1,
1210   VEX_LEN_D8_P_2,
1211   VEX_LEN_D9_P_2,
1212   VEX_LEN_DA_P_2,
1213   VEX_LEN_DB_P_2,
1214   VEX_LEN_DC_P_2,
1215   VEX_LEN_DD_P_2,
1216   VEX_LEN_DE_P_2,
1217   VEX_LEN_DF_P_2,
1218   VEX_LEN_E0_P_2,
1219   VEX_LEN_E1_P_2,
1220   VEX_LEN_E2_P_2,
1221   VEX_LEN_E3_P_2,
1222   VEX_LEN_E4_P_2,
1223   VEX_LEN_E5_P_2,
1224   VEX_LEN_E8_P_2,
1225   VEX_LEN_E9_P_2,
1226   VEX_LEN_EA_P_2,
1227   VEX_LEN_EB_P_2,
1228   VEX_LEN_EC_P_2,
1229   VEX_LEN_ED_P_2,
1230   VEX_LEN_EE_P_2,
1231   VEX_LEN_EF_P_2,
1232   VEX_LEN_F1_P_2,
1233   VEX_LEN_F2_P_2,
1234   VEX_LEN_F3_P_2,
1235   VEX_LEN_F4_P_2,
1236   VEX_LEN_F5_P_2,
1237   VEX_LEN_F6_P_2,
1238   VEX_LEN_F7_P_2,
1239   VEX_LEN_F8_P_2,
1240   VEX_LEN_F9_P_2,
1241   VEX_LEN_FA_P_2,
1242   VEX_LEN_FB_P_2,
1243   VEX_LEN_FC_P_2,
1244   VEX_LEN_FD_P_2,
1245   VEX_LEN_FE_P_2,
1246   VEX_LEN_3800_P_2,
1247   VEX_LEN_3801_P_2,
1248   VEX_LEN_3802_P_2,
1249   VEX_LEN_3803_P_2,
1250   VEX_LEN_3804_P_2,
1251   VEX_LEN_3805_P_2,
1252   VEX_LEN_3806_P_2,
1253   VEX_LEN_3807_P_2,
1254   VEX_LEN_3808_P_2,
1255   VEX_LEN_3809_P_2,
1256   VEX_LEN_380A_P_2,
1257   VEX_LEN_380B_P_2,
1258   VEX_LEN_3819_P_2_M_0,
1259   VEX_LEN_381A_P_2_M_0,
1260   VEX_LEN_381C_P_2,
1261   VEX_LEN_381D_P_2,
1262   VEX_LEN_381E_P_2,
1263   VEX_LEN_3820_P_2,
1264   VEX_LEN_3821_P_2,
1265   VEX_LEN_3822_P_2,
1266   VEX_LEN_3823_P_2,
1267   VEX_LEN_3824_P_2,
1268   VEX_LEN_3825_P_2,
1269   VEX_LEN_3828_P_2,
1270   VEX_LEN_3829_P_2,
1271   VEX_LEN_382A_P_2_M_0,
1272   VEX_LEN_382B_P_2,
1273   VEX_LEN_3830_P_2,
1274   VEX_LEN_3831_P_2,
1275   VEX_LEN_3832_P_2,
1276   VEX_LEN_3833_P_2,
1277   VEX_LEN_3834_P_2,
1278   VEX_LEN_3835_P_2,
1279   VEX_LEN_3837_P_2,
1280   VEX_LEN_3838_P_2,
1281   VEX_LEN_3839_P_2,
1282   VEX_LEN_383A_P_2,
1283   VEX_LEN_383B_P_2,
1284   VEX_LEN_383C_P_2,
1285   VEX_LEN_383D_P_2,
1286   VEX_LEN_383E_P_2,
1287   VEX_LEN_383F_P_2,
1288   VEX_LEN_3840_P_2,
1289   VEX_LEN_3841_P_2,
1290   VEX_LEN_38DB_P_2,
1291   VEX_LEN_38DC_P_2,
1292   VEX_LEN_38DD_P_2,
1293   VEX_LEN_38DE_P_2,
1294   VEX_LEN_38DF_P_2,
1295   VEX_LEN_3A06_P_2,
1296   VEX_LEN_3A0A_P_2,
1297   VEX_LEN_3A0B_P_2,
1298   VEX_LEN_3A0E_P_2,
1299   VEX_LEN_3A0F_P_2,
1300   VEX_LEN_3A14_P_2,
1301   VEX_LEN_3A15_P_2,
1302   VEX_LEN_3A16_P_2,
1303   VEX_LEN_3A17_P_2,
1304   VEX_LEN_3A18_P_2,
1305   VEX_LEN_3A19_P_2,
1306   VEX_LEN_3A20_P_2,
1307   VEX_LEN_3A21_P_2,
1308   VEX_LEN_3A22_P_2,
1309   VEX_LEN_3A41_P_2,
1310   VEX_LEN_3A42_P_2,
1311   VEX_LEN_3A44_P_2,
1312   VEX_LEN_3A4C_P_2,
1313   VEX_LEN_3A60_P_2,
1314   VEX_LEN_3A61_P_2,
1315   VEX_LEN_3A62_P_2,
1316   VEX_LEN_3A63_P_2,
1317   VEX_LEN_3A6A_P_2,
1318   VEX_LEN_3A6B_P_2,
1319   VEX_LEN_3A6E_P_2,
1320   VEX_LEN_3A6F_P_2,
1321   VEX_LEN_3A7A_P_2,
1322   VEX_LEN_3A7B_P_2,
1323   VEX_LEN_3A7E_P_2,
1324   VEX_LEN_3A7F_P_2,
1325   VEX_LEN_3ADF_P_2,
1326   VEX_LEN_XOP_09_80,
1327   VEX_LEN_XOP_09_81
1328 };
1329
1330 enum
1331 {
1332   VEX_W_10_P_0 = 0,
1333   VEX_W_10_P_1,
1334   VEX_W_10_P_2,
1335   VEX_W_10_P_3,
1336   VEX_W_11_P_0,
1337   VEX_W_11_P_1,
1338   VEX_W_11_P_2,
1339   VEX_W_11_P_3,
1340   VEX_W_12_P_0_M_0,
1341   VEX_W_12_P_0_M_1,
1342   VEX_W_12_P_1,
1343   VEX_W_12_P_2,
1344   VEX_W_12_P_3,
1345   VEX_W_13_M_0,
1346   VEX_W_14,
1347   VEX_W_15,
1348   VEX_W_16_P_0_M_0,
1349   VEX_W_16_P_0_M_1,
1350   VEX_W_16_P_1,
1351   VEX_W_16_P_2,
1352   VEX_W_17_M_0,
1353   VEX_W_28,
1354   VEX_W_29,
1355   VEX_W_2B_M_0,
1356   VEX_W_2E_P_0,
1357   VEX_W_2E_P_2,
1358   VEX_W_2F_P_0,
1359   VEX_W_2F_P_2,
1360   VEX_W_50_M_0,
1361   VEX_W_51_P_0,
1362   VEX_W_51_P_1,
1363   VEX_W_51_P_2,
1364   VEX_W_51_P_3,
1365   VEX_W_52_P_0,
1366   VEX_W_52_P_1,
1367   VEX_W_53_P_0,
1368   VEX_W_53_P_1,
1369   VEX_W_58_P_0,
1370   VEX_W_58_P_1,
1371   VEX_W_58_P_2,
1372   VEX_W_58_P_3,
1373   VEX_W_59_P_0,
1374   VEX_W_59_P_1,
1375   VEX_W_59_P_2,
1376   VEX_W_59_P_3,
1377   VEX_W_5A_P_0,
1378   VEX_W_5A_P_1,
1379   VEX_W_5A_P_3,
1380   VEX_W_5B_P_0,
1381   VEX_W_5B_P_1,
1382   VEX_W_5B_P_2,
1383   VEX_W_5C_P_0,
1384   VEX_W_5C_P_1,
1385   VEX_W_5C_P_2,
1386   VEX_W_5C_P_3,
1387   VEX_W_5D_P_0,
1388   VEX_W_5D_P_1,
1389   VEX_W_5D_P_2,
1390   VEX_W_5D_P_3,
1391   VEX_W_5E_P_0,
1392   VEX_W_5E_P_1,
1393   VEX_W_5E_P_2,
1394   VEX_W_5E_P_3,
1395   VEX_W_5F_P_0,
1396   VEX_W_5F_P_1,
1397   VEX_W_5F_P_2,
1398   VEX_W_5F_P_3,
1399   VEX_W_60_P_2,
1400   VEX_W_61_P_2,
1401   VEX_W_62_P_2,
1402   VEX_W_63_P_2,
1403   VEX_W_64_P_2,
1404   VEX_W_65_P_2,
1405   VEX_W_66_P_2,
1406   VEX_W_67_P_2,
1407   VEX_W_68_P_2,
1408   VEX_W_69_P_2,
1409   VEX_W_6A_P_2,
1410   VEX_W_6B_P_2,
1411   VEX_W_6C_P_2,
1412   VEX_W_6D_P_2,
1413   VEX_W_6F_P_1,
1414   VEX_W_6F_P_2,
1415   VEX_W_70_P_1,
1416   VEX_W_70_P_2,
1417   VEX_W_70_P_3,
1418   VEX_W_71_R_2_P_2,
1419   VEX_W_71_R_4_P_2,
1420   VEX_W_71_R_6_P_2,
1421   VEX_W_72_R_2_P_2,
1422   VEX_W_72_R_4_P_2,
1423   VEX_W_72_R_6_P_2,
1424   VEX_W_73_R_2_P_2,
1425   VEX_W_73_R_3_P_2,
1426   VEX_W_73_R_6_P_2,
1427   VEX_W_73_R_7_P_2,
1428   VEX_W_74_P_2,
1429   VEX_W_75_P_2,
1430   VEX_W_76_P_2,
1431   VEX_W_77_P_0,
1432   VEX_W_7C_P_2,
1433   VEX_W_7C_P_3,
1434   VEX_W_7D_P_2,
1435   VEX_W_7D_P_3,
1436   VEX_W_7E_P_1,
1437   VEX_W_7F_P_1,
1438   VEX_W_7F_P_2,
1439   VEX_W_AE_R_2_M_0,
1440   VEX_W_AE_R_3_M_0,
1441   VEX_W_C2_P_0,
1442   VEX_W_C2_P_1,
1443   VEX_W_C2_P_2,
1444   VEX_W_C2_P_3,
1445   VEX_W_C4_P_2,
1446   VEX_W_C5_P_2,
1447   VEX_W_D0_P_2,
1448   VEX_W_D0_P_3,
1449   VEX_W_D1_P_2,
1450   VEX_W_D2_P_2,
1451   VEX_W_D3_P_2,
1452   VEX_W_D4_P_2,
1453   VEX_W_D5_P_2,
1454   VEX_W_D6_P_2,
1455   VEX_W_D7_P_2_M_1,
1456   VEX_W_D8_P_2,
1457   VEX_W_D9_P_2,
1458   VEX_W_DA_P_2,
1459   VEX_W_DB_P_2,
1460   VEX_W_DC_P_2,
1461   VEX_W_DD_P_2,
1462   VEX_W_DE_P_2,
1463   VEX_W_DF_P_2,
1464   VEX_W_E0_P_2,
1465   VEX_W_E1_P_2,
1466   VEX_W_E2_P_2,
1467   VEX_W_E3_P_2,
1468   VEX_W_E4_P_2,
1469   VEX_W_E5_P_2,
1470   VEX_W_E6_P_1,
1471   VEX_W_E6_P_2,
1472   VEX_W_E6_P_3,
1473   VEX_W_E7_P_2_M_0,
1474   VEX_W_E8_P_2,
1475   VEX_W_E9_P_2,
1476   VEX_W_EA_P_2,
1477   VEX_W_EB_P_2,
1478   VEX_W_EC_P_2,
1479   VEX_W_ED_P_2,
1480   VEX_W_EE_P_2,
1481   VEX_W_EF_P_2,
1482   VEX_W_F0_P_3_M_0,
1483   VEX_W_F1_P_2,
1484   VEX_W_F2_P_2,
1485   VEX_W_F3_P_2,
1486   VEX_W_F4_P_2,
1487   VEX_W_F5_P_2,
1488   VEX_W_F6_P_2,
1489   VEX_W_F7_P_2,
1490   VEX_W_F8_P_2,
1491   VEX_W_F9_P_2,
1492   VEX_W_FA_P_2,
1493   VEX_W_FB_P_2,
1494   VEX_W_FC_P_2,
1495   VEX_W_FD_P_2,
1496   VEX_W_FE_P_2,
1497   VEX_W_3800_P_2,
1498   VEX_W_3801_P_2,
1499   VEX_W_3802_P_2,
1500   VEX_W_3803_P_2,
1501   VEX_W_3804_P_2,
1502   VEX_W_3805_P_2,
1503   VEX_W_3806_P_2,
1504   VEX_W_3807_P_2,
1505   VEX_W_3808_P_2,
1506   VEX_W_3809_P_2,
1507   VEX_W_380A_P_2,
1508   VEX_W_380B_P_2,
1509   VEX_W_380C_P_2,
1510   VEX_W_380D_P_2,
1511   VEX_W_380E_P_2,
1512   VEX_W_380F_P_2,
1513   VEX_W_3817_P_2,
1514   VEX_W_3818_P_2_M_0,
1515   VEX_W_3819_P_2_M_0,
1516   VEX_W_381A_P_2_M_0,
1517   VEX_W_381C_P_2,
1518   VEX_W_381D_P_2,
1519   VEX_W_381E_P_2,
1520   VEX_W_3820_P_2,
1521   VEX_W_3821_P_2,
1522   VEX_W_3822_P_2,
1523   VEX_W_3823_P_2,
1524   VEX_W_3824_P_2,
1525   VEX_W_3825_P_2,
1526   VEX_W_3828_P_2,
1527   VEX_W_3829_P_2,
1528   VEX_W_382A_P_2_M_0,
1529   VEX_W_382B_P_2,
1530   VEX_W_382C_P_2_M_0,
1531   VEX_W_382D_P_2_M_0,
1532   VEX_W_382E_P_2_M_0,
1533   VEX_W_382F_P_2_M_0,
1534   VEX_W_3830_P_2,
1535   VEX_W_3831_P_2,
1536   VEX_W_3832_P_2,
1537   VEX_W_3833_P_2,
1538   VEX_W_3834_P_2,
1539   VEX_W_3835_P_2,
1540   VEX_W_3837_P_2,
1541   VEX_W_3838_P_2,
1542   VEX_W_3839_P_2,
1543   VEX_W_383A_P_2,
1544   VEX_W_383B_P_2,
1545   VEX_W_383C_P_2,
1546   VEX_W_383D_P_2,
1547   VEX_W_383E_P_2,
1548   VEX_W_383F_P_2,
1549   VEX_W_3840_P_2,
1550   VEX_W_3841_P_2,
1551   VEX_W_38DB_P_2,
1552   VEX_W_38DC_P_2,
1553   VEX_W_38DD_P_2,
1554   VEX_W_38DE_P_2,
1555   VEX_W_38DF_P_2,
1556   VEX_W_3A04_P_2,
1557   VEX_W_3A05_P_2,
1558   VEX_W_3A06_P_2,
1559   VEX_W_3A08_P_2,
1560   VEX_W_3A09_P_2,
1561   VEX_W_3A0A_P_2,
1562   VEX_W_3A0B_P_2,
1563   VEX_W_3A0C_P_2,
1564   VEX_W_3A0D_P_2,
1565   VEX_W_3A0E_P_2,
1566   VEX_W_3A0F_P_2,
1567   VEX_W_3A14_P_2,
1568   VEX_W_3A15_P_2,
1569   VEX_W_3A18_P_2,
1570   VEX_W_3A19_P_2,
1571   VEX_W_3A20_P_2,
1572   VEX_W_3A21_P_2,
1573   VEX_W_3A40_P_2,
1574   VEX_W_3A41_P_2,
1575   VEX_W_3A42_P_2,
1576   VEX_W_3A44_P_2,
1577   VEX_W_3A48_P_2,
1578   VEX_W_3A49_P_2,
1579   VEX_W_3A4A_P_2,
1580   VEX_W_3A4B_P_2,
1581   VEX_W_3A4C_P_2,
1582   VEX_W_3A60_P_2,
1583   VEX_W_3A61_P_2,
1584   VEX_W_3A62_P_2,
1585   VEX_W_3A63_P_2,
1586   VEX_W_3ADF_P_2
1587 };
1588
1589 typedef void (*op_rtn) (int bytemode, int sizeflag);
1590
1591 struct dis386 {
1592   const char *name;
1593   struct
1594     {
1595       op_rtn rtn;
1596       int bytemode;
1597     } op[MAX_OPERANDS];
1598 };
1599
1600 /* Upper case letters in the instruction names here are macros.
1601    'A' => print 'b' if no register operands or suffix_always is true
1602    'B' => print 'b' if suffix_always is true
1603    'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
1604           size prefix
1605    'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
1606           suffix_always is true
1607    'E' => print 'e' if 32-bit form of jcxz
1608    'F' => print 'w' or 'l' depending on address size prefix (loop insns)
1609    'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
1610    'H' => print ",pt" or ",pn" branch hint
1611    'I' => honor following macro letter even in Intel mode (implemented only
1612           for some of the macro letters)
1613    'J' => print 'l'
1614    'K' => print 'd' or 'q' if rex prefix is present.
1615    'L' => print 'l' if suffix_always is true
1616    'M' => print 'r' if intel_mnemonic is false.
1617    'N' => print 'n' if instruction has no wait "prefix"
1618    'O' => print 'd' or 'o' (or 'q' in Intel mode)
1619    'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
1620           or suffix_always is true.  print 'q' if rex prefix is present.
1621    'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
1622           is true
1623    'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
1624    'S' => print 'w', 'l' or 'q' if suffix_always is true
1625    'T' => print 'q' in 64bit mode and behave as 'P' otherwise
1626    'U' => print 'q' in 64bit mode and behave as 'Q' otherwise
1627    'V' => print 'q' in 64bit mode and behave as 'S' otherwise
1628    'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
1629    'X' => print 's', 'd' depending on data16 prefix (for XMM)
1630    'Y' => 'q' if instruction has an REX 64bit overwrite prefix and
1631           suffix_always is true.
1632    'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
1633    '!' => change condition from true to false or from false to true.
1634    '%' => add 1 upper case letter to the macro.
1635
1636    2 upper case letter macros:
1637    "XY" => print 'x' or 'y' if no register operands or suffix_always
1638            is true.
1639    "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
1640    "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand
1641            or suffix_always is true
1642    "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
1643    "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
1644    "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
1645
1646    Many of the above letters print nothing in Intel mode.  See "putop"
1647    for the details.
1648
1649    Braces '{' and '}', and vertical bars '|', indicate alternative
1650    mnemonic strings for AT&T and Intel.  */
1651
1652 static const struct dis386 dis386[] = {
1653   /* 00 */
1654   { "addB",             { Eb, Gb } },
1655   { "addS",             { Ev, Gv } },
1656   { "addB",             { Gb, EbS } },
1657   { "addS",             { Gv, EvS } },
1658   { "addB",             { AL, Ib } },
1659   { "addS",             { eAX, Iv } },
1660   { X86_64_TABLE (X86_64_06) },
1661   { X86_64_TABLE (X86_64_07) },
1662   /* 08 */
1663   { "orB",              { Eb, Gb } },
1664   { "orS",              { Ev, Gv } },
1665   { "orB",              { Gb, EbS } },
1666   { "orS",              { Gv, EvS } },
1667   { "orB",              { AL, Ib } },
1668   { "orS",              { eAX, Iv } },
1669   { X86_64_TABLE (X86_64_0D) },
1670   { Bad_Opcode },       /* 0x0f extended opcode escape */
1671   /* 10 */
1672   { "adcB",             { Eb, Gb } },
1673   { "adcS",             { Ev, Gv } },
1674   { "adcB",             { Gb, EbS } },
1675   { "adcS",             { Gv, EvS } },
1676   { "adcB",             { AL, Ib } },
1677   { "adcS",             { eAX, Iv } },
1678   { X86_64_TABLE (X86_64_16) },
1679   { X86_64_TABLE (X86_64_17) },
1680   /* 18 */
1681   { "sbbB",             { Eb, Gb } },
1682   { "sbbS",             { Ev, Gv } },
1683   { "sbbB",             { Gb, EbS } },
1684   { "sbbS",             { Gv, EvS } },
1685   { "sbbB",             { AL, Ib } },
1686   { "sbbS",             { eAX, Iv } },
1687   { X86_64_TABLE (X86_64_1E) },
1688   { X86_64_TABLE (X86_64_1F) },
1689   /* 20 */
1690   { "andB",             { Eb, Gb } },
1691   { "andS",             { Ev, Gv } },
1692   { "andB",             { Gb, EbS } },
1693   { "andS",             { Gv, EvS } },
1694   { "andB",             { AL, Ib } },
1695   { "andS",             { eAX, Iv } },
1696   { Bad_Opcode },       /* SEG ES prefix */
1697   { X86_64_TABLE (X86_64_27) },
1698   /* 28 */
1699   { "subB",             { Eb, Gb } },
1700   { "subS",             { Ev, Gv } },
1701   { "subB",             { Gb, EbS } },
1702   { "subS",             { Gv, EvS } },
1703   { "subB",             { AL, Ib } },
1704   { "subS",             { eAX, Iv } },
1705   { Bad_Opcode },       /* SEG CS prefix */
1706   { X86_64_TABLE (X86_64_2F) },
1707   /* 30 */
1708   { "xorB",             { Eb, Gb } },
1709   { "xorS",             { Ev, Gv } },
1710   { "xorB",             { Gb, EbS } },
1711   { "xorS",             { Gv, EvS } },
1712   { "xorB",             { AL, Ib } },
1713   { "xorS",             { eAX, Iv } },
1714   { Bad_Opcode },       /* SEG SS prefix */
1715   { X86_64_TABLE (X86_64_37) },
1716   /* 38 */
1717   { "cmpB",             { Eb, Gb } },
1718   { "cmpS",             { Ev, Gv } },
1719   { "cmpB",             { Gb, EbS } },
1720   { "cmpS",             { Gv, EvS } },
1721   { "cmpB",             { AL, Ib } },
1722   { "cmpS",             { eAX, Iv } },
1723   { Bad_Opcode },       /* SEG DS prefix */
1724   { X86_64_TABLE (X86_64_3F) },
1725   /* 40 */
1726   { "inc{S|}",          { RMeAX } },
1727   { "inc{S|}",          { RMeCX } },
1728   { "inc{S|}",          { RMeDX } },
1729   { "inc{S|}",          { RMeBX } },
1730   { "inc{S|}",          { RMeSP } },
1731   { "inc{S|}",          { RMeBP } },
1732   { "inc{S|}",          { RMeSI } },
1733   { "inc{S|}",          { RMeDI } },
1734   /* 48 */
1735   { "dec{S|}",          { RMeAX } },
1736   { "dec{S|}",          { RMeCX } },
1737   { "dec{S|}",          { RMeDX } },
1738   { "dec{S|}",          { RMeBX } },
1739   { "dec{S|}",          { RMeSP } },
1740   { "dec{S|}",          { RMeBP } },
1741   { "dec{S|}",          { RMeSI } },
1742   { "dec{S|}",          { RMeDI } },
1743   /* 50 */
1744   { "pushV",            { RMrAX } },
1745   { "pushV",            { RMrCX } },
1746   { "pushV",            { RMrDX } },
1747   { "pushV",            { RMrBX } },
1748   { "pushV",            { RMrSP } },
1749   { "pushV",            { RMrBP } },
1750   { "pushV",            { RMrSI } },
1751   { "pushV",            { RMrDI } },
1752   /* 58 */
1753   { "popV",             { RMrAX } },
1754   { "popV",             { RMrCX } },
1755   { "popV",             { RMrDX } },
1756   { "popV",             { RMrBX } },
1757   { "popV",             { RMrSP } },
1758   { "popV",             { RMrBP } },
1759   { "popV",             { RMrSI } },
1760   { "popV",             { RMrDI } },
1761   /* 60 */
1762   { X86_64_TABLE (X86_64_60) },
1763   { X86_64_TABLE (X86_64_61) },
1764   { X86_64_TABLE (X86_64_62) },
1765   { X86_64_TABLE (X86_64_63) },
1766   { Bad_Opcode },       /* seg fs */
1767   { Bad_Opcode },       /* seg gs */
1768   { Bad_Opcode },       /* op size prefix */
1769   { Bad_Opcode },       /* adr size prefix */
1770   /* 68 */
1771   { "pushT",            { Iq } },
1772   { "imulS",            { Gv, Ev, Iv } },
1773   { "pushT",            { sIb } },
1774   { "imulS",            { Gv, Ev, sIb } },
1775   { "ins{b|}",          { Ybr, indirDX } },
1776   { X86_64_TABLE (X86_64_6D) },
1777   { "outs{b|}",         { indirDXr, Xb } },
1778   { X86_64_TABLE (X86_64_6F) },
1779   /* 70 */
1780   { "joH",              { Jb, XX, cond_jump_flag } },
1781   { "jnoH",             { Jb, XX, cond_jump_flag } },
1782   { "jbH",              { Jb, XX, cond_jump_flag } },
1783   { "jaeH",             { Jb, XX, cond_jump_flag } },
1784   { "jeH",              { Jb, XX, cond_jump_flag } },
1785   { "jneH",             { Jb, XX, cond_jump_flag } },
1786   { "jbeH",             { Jb, XX, cond_jump_flag } },
1787   { "jaH",              { Jb, XX, cond_jump_flag } },
1788   /* 78 */
1789   { "jsH",              { Jb, XX, cond_jump_flag } },
1790   { "jnsH",             { Jb, XX, cond_jump_flag } },
1791   { "jpH",              { Jb, XX, cond_jump_flag } },
1792   { "jnpH",             { Jb, XX, cond_jump_flag } },
1793   { "jlH",              { Jb, XX, cond_jump_flag } },
1794   { "jgeH",             { Jb, XX, cond_jump_flag } },
1795   { "jleH",             { Jb, XX, cond_jump_flag } },
1796   { "jgH",              { Jb, XX, cond_jump_flag } },
1797   /* 80 */
1798   { REG_TABLE (REG_80) },
1799   { REG_TABLE (REG_81) },
1800   { Bad_Opcode },
1801   { REG_TABLE (REG_82) },
1802   { "testB",            { Eb, Gb } },
1803   { "testS",            { Ev, Gv } },
1804   { "xchgB",            { Eb, Gb } },
1805   { "xchgS",            { Ev, Gv } },
1806   /* 88 */
1807   { "movB",             { Eb, Gb } },
1808   { "movS",             { Ev, Gv } },
1809   { "movB",             { Gb, EbS } },
1810   { "movS",             { Gv, EvS } },
1811   { "movD",             { Sv, Sw } },
1812   { MOD_TABLE (MOD_8D) },
1813   { "movD",             { Sw, Sv } },
1814   { REG_TABLE (REG_8F) },
1815   /* 90 */
1816   { PREFIX_TABLE (PREFIX_90) },
1817   { "xchgS",            { RMeCX, eAX } },
1818   { "xchgS",            { RMeDX, eAX } },
1819   { "xchgS",            { RMeBX, eAX } },
1820   { "xchgS",            { RMeSP, eAX } },
1821   { "xchgS",            { RMeBP, eAX } },
1822   { "xchgS",            { RMeSI, eAX } },
1823   { "xchgS",            { RMeDI, eAX } },
1824   /* 98 */
1825   { "cW{t|}R",          { XX } },
1826   { "cR{t|}O",          { XX } },
1827   { X86_64_TABLE (X86_64_9A) },
1828   { Bad_Opcode },       /* fwait */
1829   { "pushfT",           { XX } },
1830   { "popfT",            { XX } },
1831   { "sahf",             { XX } },
1832   { "lahf",             { XX } },
1833   /* a0 */
1834   { "mov%LB",           { AL, Ob } },
1835   { "mov%LS",           { eAX, Ov } },
1836   { "mov%LB",           { Ob, AL } },
1837   { "mov%LS",           { Ov, eAX } },
1838   { "movs{b|}",         { Ybr, Xb } },
1839   { "movs{R|}",         { Yvr, Xv } },
1840   { "cmps{b|}",         { Xb, Yb } },
1841   { "cmps{R|}",         { Xv, Yv } },
1842   /* a8 */
1843   { "testB",            { AL, Ib } },
1844   { "testS",            { eAX, Iv } },
1845   { "stosB",            { Ybr, AL } },
1846   { "stosS",            { Yvr, eAX } },
1847   { "lodsB",            { ALr, Xb } },
1848   { "lodsS",            { eAXr, Xv } },
1849   { "scasB",            { AL, Yb } },
1850   { "scasS",            { eAX, Yv } },
1851   /* b0 */
1852   { "movB",             { RMAL, Ib } },
1853   { "movB",             { RMCL, Ib } },
1854   { "movB",             { RMDL, Ib } },
1855   { "movB",             { RMBL, Ib } },
1856   { "movB",             { RMAH, Ib } },
1857   { "movB",             { RMCH, Ib } },
1858   { "movB",             { RMDH, Ib } },
1859   { "movB",             { RMBH, Ib } },
1860   /* b8 */
1861   { "mov%LV",           { RMeAX, Iv64 } },
1862   { "mov%LV",           { RMeCX, Iv64 } },
1863   { "mov%LV",           { RMeDX, Iv64 } },
1864   { "mov%LV",           { RMeBX, Iv64 } },
1865   { "mov%LV",           { RMeSP, Iv64 } },
1866   { "mov%LV",           { RMeBP, Iv64 } },
1867   { "mov%LV",           { RMeSI, Iv64 } },
1868   { "mov%LV",           { RMeDI, Iv64 } },
1869   /* c0 */
1870   { REG_TABLE (REG_C0) },
1871   { REG_TABLE (REG_C1) },
1872   { "retT",             { Iw } },
1873   { "retT",             { XX } },
1874   { X86_64_TABLE (X86_64_C4) },
1875   { X86_64_TABLE (X86_64_C5) },
1876   { REG_TABLE (REG_C6) },
1877   { REG_TABLE (REG_C7) },
1878   /* c8 */
1879   { "enterT",           { Iw, Ib } },
1880   { "leaveT",           { XX } },
1881   { "Jret{|f}P",        { Iw } },
1882   { "Jret{|f}P",        { XX } },
1883   { "int3",             { XX } },
1884   { "int",              { Ib } },
1885   { X86_64_TABLE (X86_64_CE) },
1886   { "iretP",            { XX } },
1887   /* d0 */
1888   { REG_TABLE (REG_D0) },
1889   { REG_TABLE (REG_D1) },
1890   { REG_TABLE (REG_D2) },
1891   { REG_TABLE (REG_D3) },
1892   { X86_64_TABLE (X86_64_D4) },
1893   { X86_64_TABLE (X86_64_D5) },
1894   { Bad_Opcode },
1895   { "xlat",             { DSBX } },
1896   /* d8 */
1897   { FLOAT },
1898   { FLOAT },
1899   { FLOAT },
1900   { FLOAT },
1901   { FLOAT },
1902   { FLOAT },
1903   { FLOAT },
1904   { FLOAT },
1905   /* e0 */
1906   { "loopneFH",         { Jb, XX, loop_jcxz_flag } },
1907   { "loopeFH",          { Jb, XX, loop_jcxz_flag } },
1908   { "loopFH",           { Jb, XX, loop_jcxz_flag } },
1909   { "jEcxzH",           { Jb, XX, loop_jcxz_flag } },
1910   { "inB",              { AL, Ib } },
1911   { "inG",              { zAX, Ib } },
1912   { "outB",             { Ib, AL } },
1913   { "outG",             { Ib, zAX } },
1914   /* e8 */
1915   { "callT",            { Jv } },
1916   { "jmpT",             { Jv } },
1917   { X86_64_TABLE (X86_64_EA) },
1918   { "jmp",              { Jb } },
1919   { "inB",              { AL, indirDX } },
1920   { "inG",              { zAX, indirDX } },
1921   { "outB",             { indirDX, AL } },
1922   { "outG",             { indirDX, zAX } },
1923   /* f0 */
1924   { Bad_Opcode },       /* lock prefix */
1925   { "icebp",            { XX } },
1926   { Bad_Opcode },       /* repne */
1927   { Bad_Opcode },       /* repz */
1928   { "hlt",              { XX } },
1929   { "cmc",              { XX } },
1930   { REG_TABLE (REG_F6) },
1931   { REG_TABLE (REG_F7) },
1932   /* f8 */
1933   { "clc",              { XX } },
1934   { "stc",              { XX } },
1935   { "cli",              { XX } },
1936   { "sti",              { XX } },
1937   { "cld",              { XX } },
1938   { "std",              { XX } },
1939   { REG_TABLE (REG_FE) },
1940   { REG_TABLE (REG_FF) },
1941 };
1942
1943 static const struct dis386 dis386_twobyte[] = {
1944   /* 00 */
1945   { REG_TABLE (REG_0F00 ) },
1946   { REG_TABLE (REG_0F01 ) },
1947   { "larS",             { Gv, Ew } },
1948   { "lslS",             { Gv, Ew } },
1949   { Bad_Opcode },
1950   { "syscall",          { XX } },
1951   { "clts",             { XX } },
1952   { "sysretP",          { XX } },
1953   /* 08 */
1954   { "invd",             { XX } },
1955   { "wbinvd",           { XX } },
1956   { Bad_Opcode },
1957   { "ud2a",             { XX } },
1958   { Bad_Opcode },
1959   { REG_TABLE (REG_0F0D) },
1960   { "femms",            { XX } },
1961   { "",                 { MX, EM, OPSUF } }, /* See OP_3DNowSuffix.  */
1962   /* 10 */
1963   { PREFIX_TABLE (PREFIX_0F10) },
1964   { PREFIX_TABLE (PREFIX_0F11) },
1965   { PREFIX_TABLE (PREFIX_0F12) },
1966   { MOD_TABLE (MOD_0F13) },
1967   { "unpcklpX",         { XM, EXx } },
1968   { "unpckhpX",         { XM, EXx } },
1969   { PREFIX_TABLE (PREFIX_0F16) },
1970   { MOD_TABLE (MOD_0F17) },
1971   /* 18 */
1972   { REG_TABLE (REG_0F18) },
1973   { "nopQ",             { Ev } },
1974   { "nopQ",             { Ev } },
1975   { "nopQ",             { Ev } },
1976   { "nopQ",             { Ev } },
1977   { "nopQ",             { Ev } },
1978   { "nopQ",             { Ev } },
1979   { "nopQ",             { Ev } },
1980   /* 20 */
1981   { MOD_TABLE (MOD_0F20) },
1982   { MOD_TABLE (MOD_0F21) },
1983   { MOD_TABLE (MOD_0F22) },
1984   { MOD_TABLE (MOD_0F23) },
1985   { MOD_TABLE (MOD_0F24) },
1986   { Bad_Opcode },
1987   { MOD_TABLE (MOD_0F26) },
1988   { Bad_Opcode },
1989   /* 28 */
1990   { "movapX",           { XM, EXx } },
1991   { "movapX",           { EXxS, XM } },
1992   { PREFIX_TABLE (PREFIX_0F2A) },
1993   { PREFIX_TABLE (PREFIX_0F2B) },
1994   { PREFIX_TABLE (PREFIX_0F2C) },
1995   { PREFIX_TABLE (PREFIX_0F2D) },
1996   { PREFIX_TABLE (PREFIX_0F2E) },
1997   { PREFIX_TABLE (PREFIX_0F2F) },
1998   /* 30 */
1999   { "wrmsr",            { XX } },
2000   { "rdtsc",            { XX } },
2001   { "rdmsr",            { XX } },
2002   { "rdpmc",            { XX } },
2003   { "sysenter",         { XX } },
2004   { "sysexit",          { XX } },
2005   { Bad_Opcode },
2006   { "getsec",           { XX } },
2007   /* 38 */
2008   { THREE_BYTE_TABLE (THREE_BYTE_0F38) },
2009   { Bad_Opcode },
2010   { THREE_BYTE_TABLE (THREE_BYTE_0F3A) },
2011   { Bad_Opcode },
2012   { Bad_Opcode },
2013   { Bad_Opcode },
2014   { Bad_Opcode },
2015   { Bad_Opcode },
2016   /* 40 */
2017   { "cmovoS",           { Gv, Ev } },
2018   { "cmovnoS",          { Gv, Ev } },
2019   { "cmovbS",           { Gv, Ev } },
2020   { "cmovaeS",          { Gv, Ev } },
2021   { "cmoveS",           { Gv, Ev } },
2022   { "cmovneS",          { Gv, Ev } },
2023   { "cmovbeS",          { Gv, Ev } },
2024   { "cmovaS",           { Gv, Ev } },
2025   /* 48 */
2026   { "cmovsS",           { Gv, Ev } },
2027   { "cmovnsS",          { Gv, Ev } },
2028   { "cmovpS",           { Gv, Ev } },
2029   { "cmovnpS",          { Gv, Ev } },
2030   { "cmovlS",           { Gv, Ev } },
2031   { "cmovgeS",          { Gv, Ev } },
2032   { "cmovleS",          { Gv, Ev } },
2033   { "cmovgS",           { Gv, Ev } },
2034   /* 50 */
2035   { MOD_TABLE (MOD_0F51) },
2036   { PREFIX_TABLE (PREFIX_0F51) },
2037   { PREFIX_TABLE (PREFIX_0F52) },
2038   { PREFIX_TABLE (PREFIX_0F53) },
2039   { "andpX",            { XM, EXx } },
2040   { "andnpX",           { XM, EXx } },
2041   { "orpX",             { XM, EXx } },
2042   { "xorpX",            { XM, EXx } },
2043   /* 58 */
2044   { PREFIX_TABLE (PREFIX_0F58) },
2045   { PREFIX_TABLE (PREFIX_0F59) },
2046   { PREFIX_TABLE (PREFIX_0F5A) },
2047   { PREFIX_TABLE (PREFIX_0F5B) },
2048   { PREFIX_TABLE (PREFIX_0F5C) },
2049   { PREFIX_TABLE (PREFIX_0F5D) },
2050   { PREFIX_TABLE (PREFIX_0F5E) },
2051   { PREFIX_TABLE (PREFIX_0F5F) },
2052   /* 60 */
2053   { PREFIX_TABLE (PREFIX_0F60) },
2054   { PREFIX_TABLE (PREFIX_0F61) },
2055   { PREFIX_TABLE (PREFIX_0F62) },
2056   { "packsswb",         { MX, EM } },
2057   { "pcmpgtb",          { MX, EM } },
2058   { "pcmpgtw",          { MX, EM } },
2059   { "pcmpgtd",          { MX, EM } },
2060   { "packuswb",         { MX, EM } },
2061   /* 68 */
2062   { "punpckhbw",        { MX, EM } },
2063   { "punpckhwd",        { MX, EM } },
2064   { "punpckhdq",        { MX, EM } },
2065   { "packssdw",         { MX, EM } },
2066   { PREFIX_TABLE (PREFIX_0F6C) },
2067   { PREFIX_TABLE (PREFIX_0F6D) },
2068   { "movK",             { MX, Edq } },
2069   { PREFIX_TABLE (PREFIX_0F6F) },
2070   /* 70 */
2071   { PREFIX_TABLE (PREFIX_0F70) },
2072   { REG_TABLE (REG_0F71) },
2073   { REG_TABLE (REG_0F72) },
2074   { REG_TABLE (REG_0F73) },
2075   { "pcmpeqb",          { MX, EM } },
2076   { "pcmpeqw",          { MX, EM } },
2077   { "pcmpeqd",          { MX, EM } },
2078   { "emms",             { XX } },
2079   /* 78 */
2080   { PREFIX_TABLE (PREFIX_0F78) },
2081   { PREFIX_TABLE (PREFIX_0F79) },
2082   { THREE_BYTE_TABLE (THREE_BYTE_0F7A) },
2083   { Bad_Opcode },
2084   { PREFIX_TABLE (PREFIX_0F7C) },
2085   { PREFIX_TABLE (PREFIX_0F7D) },
2086   { PREFIX_TABLE (PREFIX_0F7E) },
2087   { PREFIX_TABLE (PREFIX_0F7F) },
2088   /* 80 */
2089   { "joH",              { Jv, XX, cond_jump_flag } },
2090   { "jnoH",             { Jv, XX, cond_jump_flag } },
2091   { "jbH",              { Jv, XX, cond_jump_flag } },
2092   { "jaeH",             { Jv, XX, cond_jump_flag } },
2093   { "jeH",              { Jv, XX, cond_jump_flag } },
2094   { "jneH",             { Jv, XX, cond_jump_flag } },
2095   { "jbeH",             { Jv, XX, cond_jump_flag } },
2096   { "jaH",              { Jv, XX, cond_jump_flag } },
2097   /* 88 */
2098   { "jsH",              { Jv, XX, cond_jump_flag } },
2099   { "jnsH",             { Jv, XX, cond_jump_flag } },
2100   { "jpH",              { Jv, XX, cond_jump_flag } },
2101   { "jnpH",             { Jv, XX, cond_jump_flag } },
2102   { "jlH",              { Jv, XX, cond_jump_flag } },
2103   { "jgeH",             { Jv, XX, cond_jump_flag } },
2104   { "jleH",             { Jv, XX, cond_jump_flag } },
2105   { "jgH",              { Jv, XX, cond_jump_flag } },
2106   /* 90 */
2107   { "seto",             { Eb } },
2108   { "setno",            { Eb } },
2109   { "setb",             { Eb } },
2110   { "setae",            { Eb } },
2111   { "sete",             { Eb } },
2112   { "setne",            { Eb } },
2113   { "setbe",            { Eb } },
2114   { "seta",             { Eb } },
2115   /* 98 */
2116   { "sets",             { Eb } },
2117   { "setns",            { Eb } },
2118   { "setp",             { Eb } },
2119   { "setnp",            { Eb } },
2120   { "setl",             { Eb } },
2121   { "setge",            { Eb } },
2122   { "setle",            { Eb } },
2123   { "setg",             { Eb } },
2124   /* a0 */
2125   { "pushT",            { fs } },
2126   { "popT",             { fs } },
2127   { "cpuid",            { XX } },
2128   { "btS",              { Ev, Gv } },
2129   { "shldS",            { Ev, Gv, Ib } },
2130   { "shldS",            { Ev, Gv, CL } },
2131   { REG_TABLE (REG_0FA6) },
2132   { REG_TABLE (REG_0FA7) },
2133   /* a8 */
2134   { "pushT",            { gs } },
2135   { "popT",             { gs } },
2136   { "rsm",              { XX } },
2137   { "btsS",             { Ev, Gv } },
2138   { "shrdS",            { Ev, Gv, Ib } },
2139   { "shrdS",            { Ev, Gv, CL } },
2140   { REG_TABLE (REG_0FAE) },
2141   { "imulS",            { Gv, Ev } },
2142   /* b0 */
2143   { "cmpxchgB",         { Eb, Gb } },
2144   { "cmpxchgS",         { Ev, Gv } },
2145   { MOD_TABLE (MOD_0FB2) },
2146   { "btrS",             { Ev, Gv } },
2147   { MOD_TABLE (MOD_0FB4) },
2148   { MOD_TABLE (MOD_0FB5) },
2149   { "movz{bR|x}",       { Gv, Eb } },
2150   { "movz{wR|x}",       { Gv, Ew } }, /* yes, there really is movzww ! */
2151   /* b8 */
2152   { PREFIX_TABLE (PREFIX_0FB8) },
2153   { "ud2b",             { XX } },
2154   { REG_TABLE (REG_0FBA) },
2155   { "btcS",             { Ev, Gv } },
2156   { "bsfS",             { Gv, Ev } },
2157   { PREFIX_TABLE (PREFIX_0FBD) },
2158   { "movs{bR|x}",       { Gv, Eb } },
2159   { "movs{wR|x}",       { Gv, Ew } }, /* yes, there really is movsww ! */
2160   /* c0 */
2161   { "xaddB",            { Eb, Gb } },
2162   { "xaddS",            { Ev, Gv } },
2163   { PREFIX_TABLE (PREFIX_0FC2) },
2164   { PREFIX_TABLE (PREFIX_0FC3) },
2165   { "pinsrw",           { MX, Edqw, Ib } },
2166   { "pextrw",           { Gdq, MS, Ib } },
2167   { "shufpX",           { XM, EXx, Ib } },
2168   { REG_TABLE (REG_0FC7) },
2169   /* c8 */
2170   { "bswap",            { RMeAX } },
2171   { "bswap",            { RMeCX } },
2172   { "bswap",            { RMeDX } },
2173   { "bswap",            { RMeBX } },
2174   { "bswap",            { RMeSP } },
2175   { "bswap",            { RMeBP } },
2176   { "bswap",            { RMeSI } },
2177   { "bswap",            { RMeDI } },
2178   /* d0 */
2179   { PREFIX_TABLE (PREFIX_0FD0) },
2180   { "psrlw",            { MX, EM } },
2181   { "psrld",            { MX, EM } },
2182   { "psrlq",            { MX, EM } },
2183   { "paddq",            { MX, EM } },
2184   { "pmullw",           { MX, EM } },
2185   { PREFIX_TABLE (PREFIX_0FD6) },
2186   { MOD_TABLE (MOD_0FD7) },
2187   /* d8 */
2188   { "psubusb",          { MX, EM } },
2189   { "psubusw",          { MX, EM } },
2190   { "pminub",           { MX, EM } },
2191   { "pand",             { MX, EM } },
2192   { "paddusb",          { MX, EM } },
2193   { "paddusw",          { MX, EM } },
2194   { "pmaxub",           { MX, EM } },
2195   { "pandn",            { MX, EM } },
2196   /* e0 */
2197   { "pavgb",            { MX, EM } },
2198   { "psraw",            { MX, EM } },
2199   { "psrad",            { MX, EM } },
2200   { "pavgw",            { MX, EM } },
2201   { "pmulhuw",          { MX, EM } },
2202   { "pmulhw",           { MX, EM } },
2203   { PREFIX_TABLE (PREFIX_0FE6) },
2204   { PREFIX_TABLE (PREFIX_0FE7) },
2205   /* e8 */
2206   { "psubsb",           { MX, EM } },
2207   { "psubsw",           { MX, EM } },
2208   { "pminsw",           { MX, EM } },
2209   { "por",              { MX, EM } },
2210   { "paddsb",           { MX, EM } },
2211   { "paddsw",           { MX, EM } },
2212   { "pmaxsw",           { MX, EM } },
2213   { "pxor",             { MX, EM } },
2214   /* f0 */
2215   { PREFIX_TABLE (PREFIX_0FF0) },
2216   { "psllw",            { MX, EM } },
2217   { "pslld",            { MX, EM } },
2218   { "psllq",            { MX, EM } },
2219   { "pmuludq",          { MX, EM } },
2220   { "pmaddwd",          { MX, EM } },
2221   { "psadbw",           { MX, EM } },
2222   { PREFIX_TABLE (PREFIX_0FF7) },
2223   /* f8 */
2224   { "psubb",            { MX, EM } },
2225   { "psubw",            { MX, EM } },
2226   { "psubd",            { MX, EM } },
2227   { "psubq",            { MX, EM } },
2228   { "paddb",            { MX, EM } },
2229   { "paddw",            { MX, EM } },
2230   { "paddd",            { MX, EM } },
2231   { Bad_Opcode },
2232 };
2233
2234 static const unsigned char onebyte_has_modrm[256] = {
2235   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2236   /*       -------------------------------        */
2237   /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
2238   /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
2239   /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
2240   /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
2241   /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
2242   /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
2243   /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
2244   /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
2245   /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
2246   /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
2247   /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
2248   /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
2249   /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
2250   /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
2251   /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
2252   /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1  /* f0 */
2253   /*       -------------------------------        */
2254   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2255 };
2256
2257 static const unsigned char twobyte_has_modrm[256] = {
2258   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2259   /*       -------------------------------        */
2260   /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
2261   /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
2262   /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
2263   /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
2264   /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
2265   /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
2266   /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
2267   /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
2268   /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
2269   /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
2270   /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
2271   /* b0 */ 1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1, /* bf */
2272   /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
2273   /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
2274   /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
2275   /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0  /* ff */
2276   /*       -------------------------------        */
2277   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2278 };
2279
2280 static char obuf[100];
2281 static char *obufp;
2282 static char *mnemonicendp;
2283 static char scratchbuf[100];
2284 static unsigned char *start_codep;
2285 static unsigned char *insn_codep;
2286 static unsigned char *codep;
2287 static int last_lock_prefix;
2288 static int last_repz_prefix;
2289 static int last_repnz_prefix;
2290 static int last_data_prefix;
2291 static int last_addr_prefix;
2292 static int last_rex_prefix;
2293 static int last_seg_prefix;
2294 #define MAX_CODE_LENGTH 15
2295 /* We can up to 14 prefixes since the maximum instruction length is
2296    15bytes.  */
2297 static int all_prefixes[MAX_CODE_LENGTH - 1];
2298 static disassemble_info *the_info;
2299 static struct
2300   {
2301     int mod;
2302     int reg;
2303     int rm;
2304   }
2305 modrm;
2306 static unsigned char need_modrm;
2307 static struct
2308   {
2309     int register_specifier;
2310     int length;
2311     int prefix;
2312     int w;
2313   }
2314 vex;
2315 static unsigned char need_vex;
2316 static unsigned char need_vex_reg;
2317 static unsigned char vex_w_done;
2318
2319 struct op
2320   {
2321     const char *name;
2322     unsigned int len;
2323   };
2324
2325 /* If we are accessing mod/rm/reg without need_modrm set, then the
2326    values are stale.  Hitting this abort likely indicates that you
2327    need to update onebyte_has_modrm or twobyte_has_modrm.  */
2328 #define MODRM_CHECK  if (!need_modrm) abort ()
2329
2330 static const char **names64;
2331 static const char **names32;
2332 static const char **names16;
2333 static const char **names8;
2334 static const char **names8rex;
2335 static const char **names_seg;
2336 static const char *index64;
2337 static const char *index32;
2338 static const char **index16;
2339
2340 static const char *intel_names64[] = {
2341   "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
2342   "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
2343 };
2344 static const char *intel_names32[] = {
2345   "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
2346   "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
2347 };
2348 static const char *intel_names16[] = {
2349   "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
2350   "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
2351 };
2352 static const char *intel_names8[] = {
2353   "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
2354 };
2355 static const char *intel_names8rex[] = {
2356   "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
2357   "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
2358 };
2359 static const char *intel_names_seg[] = {
2360   "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
2361 };
2362 static const char *intel_index64 = "riz";
2363 static const char *intel_index32 = "eiz";
2364 static const char *intel_index16[] = {
2365   "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
2366 };
2367
2368 static const char *att_names64[] = {
2369   "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
2370   "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
2371 };
2372 static const char *att_names32[] = {
2373   "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
2374   "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
2375 };
2376 static const char *att_names16[] = {
2377   "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
2378   "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
2379 };
2380 static const char *att_names8[] = {
2381   "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
2382 };
2383 static const char *att_names8rex[] = {
2384   "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
2385   "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
2386 };
2387 static const char *att_names_seg[] = {
2388   "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
2389 };
2390 static const char *att_index64 = "%riz";
2391 static const char *att_index32 = "%eiz";
2392 static const char *att_index16[] = {
2393   "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
2394 };
2395
2396 static const char **names_mm;
2397 static const char *intel_names_mm[] = {
2398   "mm0", "mm1", "mm2", "mm3",
2399   "mm4", "mm5", "mm6", "mm7"
2400 };
2401 static const char *att_names_mm[] = {
2402   "%mm0", "%mm1", "%mm2", "%mm3",
2403   "%mm4", "%mm5", "%mm6", "%mm7"
2404 };
2405
2406 static const char **names_xmm;
2407 static const char *intel_names_xmm[] = {
2408   "xmm0", "xmm1", "xmm2", "xmm3",
2409   "xmm4", "xmm5", "xmm6", "xmm7",
2410   "xmm8", "xmm9", "xmm10", "xmm11",
2411   "xmm12", "xmm13", "xmm14", "xmm15"
2412 };
2413 static const char *att_names_xmm[] = {
2414   "%xmm0", "%xmm1", "%xmm2", "%xmm3",
2415   "%xmm4", "%xmm5", "%xmm6", "%xmm7",
2416   "%xmm8", "%xmm9", "%xmm10", "%xmm11",
2417   "%xmm12", "%xmm13", "%xmm14", "%xmm15"
2418 };
2419
2420 static const char **names_ymm;
2421 static const char *intel_names_ymm[] = {
2422   "ymm0", "ymm1", "ymm2", "ymm3",
2423   "ymm4", "ymm5", "ymm6", "ymm7",
2424   "ymm8", "ymm9", "ymm10", "ymm11",
2425   "ymm12", "ymm13", "ymm14", "ymm15"
2426 };
2427 static const char *att_names_ymm[] = {
2428   "%ymm0", "%ymm1", "%ymm2", "%ymm3",
2429   "%ymm4", "%ymm5", "%ymm6", "%ymm7",
2430   "%ymm8", "%ymm9", "%ymm10", "%ymm11",
2431   "%ymm12", "%ymm13", "%ymm14", "%ymm15"
2432 };
2433
2434 static const struct dis386 reg_table[][8] = {
2435   /* REG_80 */
2436   {
2437     { "addA",   { Eb, Ib } },
2438     { "orA",    { Eb, Ib } },
2439     { "adcA",   { Eb, Ib } },
2440     { "sbbA",   { Eb, Ib } },
2441     { "andA",   { Eb, Ib } },
2442     { "subA",   { Eb, Ib } },
2443     { "xorA",   { Eb, Ib } },
2444     { "cmpA",   { Eb, Ib } },
2445   },
2446   /* REG_81 */
2447   {
2448     { "addQ",   { Ev, Iv } },
2449     { "orQ",    { Ev, Iv } },
2450     { "adcQ",   { Ev, Iv } },
2451     { "sbbQ",   { Ev, Iv } },
2452     { "andQ",   { Ev, Iv } },
2453     { "subQ",   { Ev, Iv } },
2454     { "xorQ",   { Ev, Iv } },
2455     { "cmpQ",   { Ev, Iv } },
2456   },
2457   /* REG_82 */
2458   {
2459     { "addQ",   { Ev, sIb } },
2460     { "orQ",    { Ev, sIb } },
2461     { "adcQ",   { Ev, sIb } },
2462     { "sbbQ",   { Ev, sIb } },
2463     { "andQ",   { Ev, sIb } },
2464     { "subQ",   { Ev, sIb } },
2465     { "xorQ",   { Ev, sIb } },
2466     { "cmpQ",   { Ev, sIb } },
2467   },
2468   /* REG_8F */
2469   {
2470     { "popU",   { stackEv } },
2471     { XOP_8F_TABLE (XOP_09) },
2472     { Bad_Opcode },
2473     { Bad_Opcode },
2474     { Bad_Opcode },
2475     { XOP_8F_TABLE (XOP_09) },
2476   },
2477   /* REG_C0 */
2478   {
2479     { "rolA",   { Eb, Ib } },
2480     { "rorA",   { Eb, Ib } },
2481     { "rclA",   { Eb, Ib } },
2482     { "rcrA",   { Eb, Ib } },
2483     { "shlA",   { Eb, Ib } },
2484     { "shrA",   { Eb, Ib } },
2485     { Bad_Opcode },
2486     { "sarA",   { Eb, Ib } },
2487   },
2488   /* REG_C1 */
2489   {
2490     { "rolQ",   { Ev, Ib } },
2491     { "rorQ",   { Ev, Ib } },
2492     { "rclQ",   { Ev, Ib } },
2493     { "rcrQ",   { Ev, Ib } },
2494     { "shlQ",   { Ev, Ib } },
2495     { "shrQ",   { Ev, Ib } },
2496     { Bad_Opcode },
2497     { "sarQ",   { Ev, Ib } },
2498   },
2499   /* REG_C6 */
2500   {
2501     { "movA",   { Eb, Ib } },
2502   },
2503   /* REG_C7 */
2504   {
2505     { "movQ",   { Ev, Iv } },
2506   },
2507   /* REG_D0 */
2508   {
2509     { "rolA",   { Eb, I1 } },
2510     { "rorA",   { Eb, I1 } },
2511     { "rclA",   { Eb, I1 } },
2512     { "rcrA",   { Eb, I1 } },
2513     { "shlA",   { Eb, I1 } },
2514     { "shrA",   { Eb, I1 } },
2515     { Bad_Opcode },
2516     { "sarA",   { Eb, I1 } },
2517   },
2518   /* REG_D1 */
2519   {
2520     { "rolQ",   { Ev, I1 } },
2521     { "rorQ",   { Ev, I1 } },
2522     { "rclQ",   { Ev, I1 } },
2523     { "rcrQ",   { Ev, I1 } },
2524     { "shlQ",   { Ev, I1 } },
2525     { "shrQ",   { Ev, I1 } },
2526     { Bad_Opcode },
2527     { "sarQ",   { Ev, I1 } },
2528   },
2529   /* REG_D2 */
2530   {
2531     { "rolA",   { Eb, CL } },
2532     { "rorA",   { Eb, CL } },
2533     { "rclA",   { Eb, CL } },
2534     { "rcrA",   { Eb, CL } },
2535     { "shlA",   { Eb, CL } },
2536     { "shrA",   { Eb, CL } },
2537     { Bad_Opcode },
2538     { "sarA",   { Eb, CL } },
2539   },
2540   /* REG_D3 */
2541   {
2542     { "rolQ",   { Ev, CL } },
2543     { "rorQ",   { Ev, CL } },
2544     { "rclQ",   { Ev, CL } },
2545     { "rcrQ",   { Ev, CL } },
2546     { "shlQ",   { Ev, CL } },
2547     { "shrQ",   { Ev, CL } },
2548     { Bad_Opcode },
2549     { "sarQ",   { Ev, CL } },
2550   },
2551   /* REG_F6 */
2552   {
2553     { "testA",  { Eb, Ib } },
2554     { Bad_Opcode },
2555     { "notA",   { Eb } },
2556     { "negA",   { Eb } },
2557     { "mulA",   { Eb } },       /* Don't print the implicit %al register,  */
2558     { "imulA",  { Eb } },       /* to distinguish these opcodes from other */
2559     { "divA",   { Eb } },       /* mul/imul opcodes.  Do the same for div  */
2560     { "idivA",  { Eb } },       /* and idiv for consistency.               */
2561   },
2562   /* REG_F7 */
2563   {
2564     { "testQ",  { Ev, Iv } },
2565     { Bad_Opcode },
2566     { "notQ",   { Ev } },
2567     { "negQ",   { Ev } },
2568     { "mulQ",   { Ev } },       /* Don't print the implicit register.  */
2569     { "imulQ",  { Ev } },
2570     { "divQ",   { Ev } },
2571     { "idivQ",  { Ev } },
2572   },
2573   /* REG_FE */
2574   {
2575     { "incA",   { Eb } },
2576     { "decA",   { Eb } },
2577   },
2578   /* REG_FF */
2579   {
2580     { "incQ",   { Ev } },
2581     { "decQ",   { Ev } },
2582     { "callT",  { indirEv } },
2583     { "JcallT", { indirEp } },
2584     { "jmpT",   { indirEv } },
2585     { "JjmpT",  { indirEp } },
2586     { "pushU",  { stackEv } },
2587     { Bad_Opcode },
2588   },
2589   /* REG_0F00 */
2590   {
2591     { "sldtD",  { Sv } },
2592     { "strD",   { Sv } },
2593     { "lldt",   { Ew } },
2594     { "ltr",    { Ew } },
2595     { "verr",   { Ew } },
2596     { "verw",   { Ew } },
2597     { Bad_Opcode },
2598     { Bad_Opcode },
2599   },
2600   /* REG_0F01 */
2601   {
2602     { MOD_TABLE (MOD_0F01_REG_0) },
2603     { MOD_TABLE (MOD_0F01_REG_1) },
2604     { MOD_TABLE (MOD_0F01_REG_2) },
2605     { MOD_TABLE (MOD_0F01_REG_3) },
2606     { "smswD",  { Sv } },
2607     { Bad_Opcode },
2608     { "lmsw",   { Ew } },
2609     { MOD_TABLE (MOD_0F01_REG_7) },
2610   },
2611   /* REG_0F0D */
2612   {
2613     { "prefetch",       { Eb } },
2614     { "prefetchw",      { Eb } },
2615   },
2616   /* REG_0F18 */
2617   {
2618     { MOD_TABLE (MOD_0F18_REG_0) },
2619     { MOD_TABLE (MOD_0F18_REG_1) },
2620     { MOD_TABLE (MOD_0F18_REG_2) },
2621     { MOD_TABLE (MOD_0F18_REG_3) },
2622   },
2623   /* REG_0F71 */
2624   {
2625     { Bad_Opcode },
2626     { Bad_Opcode },
2627     { MOD_TABLE (MOD_0F71_REG_2) },
2628     { Bad_Opcode },
2629     { MOD_TABLE (MOD_0F71_REG_4) },
2630     { Bad_Opcode },
2631     { MOD_TABLE (MOD_0F71_REG_6) },
2632   },
2633   /* REG_0F72 */
2634   {
2635     { Bad_Opcode },
2636     { Bad_Opcode },
2637     { MOD_TABLE (MOD_0F72_REG_2) },
2638     { Bad_Opcode },
2639     { MOD_TABLE (MOD_0F72_REG_4) },
2640     { Bad_Opcode },
2641     { MOD_TABLE (MOD_0F72_REG_6) },
2642   },
2643   /* REG_0F73 */
2644   {
2645     { Bad_Opcode },
2646     { Bad_Opcode },
2647     { MOD_TABLE (MOD_0F73_REG_2) },
2648     { MOD_TABLE (MOD_0F73_REG_3) },
2649     { Bad_Opcode },
2650     { Bad_Opcode },
2651     { MOD_TABLE (MOD_0F73_REG_6) },
2652     { MOD_TABLE (MOD_0F73_REG_7) },
2653   },
2654   /* REG_0FA6 */
2655   {
2656     { "montmul",        { { OP_0f07, 0 } } },
2657     { "xsha1",          { { OP_0f07, 0 } } },
2658     { "xsha256",        { { OP_0f07, 0 } } },
2659   },
2660   /* REG_0FA7 */
2661   {
2662     { "xstore-rng",     { { OP_0f07, 0 } } },
2663     { "xcrypt-ecb",     { { OP_0f07, 0 } } },
2664     { "xcrypt-cbc",     { { OP_0f07, 0 } } },
2665     { "xcrypt-ctr",     { { OP_0f07, 0 } } },
2666     { "xcrypt-cfb",     { { OP_0f07, 0 } } },
2667     { "xcrypt-ofb",     { { OP_0f07, 0 } } },
2668   },
2669   /* REG_0FAE */
2670   {
2671     { MOD_TABLE (MOD_0FAE_REG_0) },
2672     { MOD_TABLE (MOD_0FAE_REG_1) },
2673     { MOD_TABLE (MOD_0FAE_REG_2) },
2674     { MOD_TABLE (MOD_0FAE_REG_3) },
2675     { MOD_TABLE (MOD_0FAE_REG_4) },
2676     { MOD_TABLE (MOD_0FAE_REG_5) },
2677     { MOD_TABLE (MOD_0FAE_REG_6) },
2678     { MOD_TABLE (MOD_0FAE_REG_7) },
2679   },
2680   /* REG_0FBA */
2681   {
2682     { Bad_Opcode },
2683     { Bad_Opcode },
2684     { Bad_Opcode },
2685     { Bad_Opcode },
2686     { "btQ",    { Ev, Ib } },
2687     { "btsQ",   { Ev, Ib } },
2688     { "btrQ",   { Ev, Ib } },
2689     { "btcQ",   { Ev, Ib } },
2690   },
2691   /* REG_0FC7 */
2692   {
2693     { Bad_Opcode },
2694     { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } } },
2695     { Bad_Opcode },
2696     { Bad_Opcode },
2697     { Bad_Opcode },
2698     { Bad_Opcode },
2699     { MOD_TABLE (MOD_0FC7_REG_6) },
2700     { MOD_TABLE (MOD_0FC7_REG_7) },
2701   },
2702   /* REG_VEX_71 */
2703   {
2704     { Bad_Opcode },
2705     { Bad_Opcode },
2706     { MOD_TABLE (MOD_VEX_71_REG_2) },
2707     { Bad_Opcode },
2708     { MOD_TABLE (MOD_VEX_71_REG_4) },
2709     { Bad_Opcode },
2710     { MOD_TABLE (MOD_VEX_71_REG_6) },
2711   },
2712   /* REG_VEX_72 */
2713   {
2714     { Bad_Opcode },
2715     { Bad_Opcode },
2716     { MOD_TABLE (MOD_VEX_72_REG_2) },
2717     { Bad_Opcode },
2718     { MOD_TABLE (MOD_VEX_72_REG_4) },
2719     { Bad_Opcode },
2720     { MOD_TABLE (MOD_VEX_72_REG_6) },
2721   },
2722   /* REG_VEX_73 */
2723   {
2724     { Bad_Opcode },
2725     { Bad_Opcode },
2726     { MOD_TABLE (MOD_VEX_73_REG_2) },
2727     { MOD_TABLE (MOD_VEX_73_REG_3) },
2728     { Bad_Opcode },
2729     { Bad_Opcode },
2730     { MOD_TABLE (MOD_VEX_73_REG_6) },
2731     { MOD_TABLE (MOD_VEX_73_REG_7) },
2732   },
2733   /* REG_VEX_AE */
2734   {
2735     { Bad_Opcode },
2736     { Bad_Opcode },
2737     { MOD_TABLE (MOD_VEX_AE_REG_2) },
2738     { MOD_TABLE (MOD_VEX_AE_REG_3) },
2739   },
2740   /* REG_XOP_LWPCB */
2741   {
2742     { "llwpcb", { { OP_LWPCB_E, 0 } } },
2743     { "slwpcb", { { OP_LWPCB_E, 0 } } },
2744   },
2745   /* REG_XOP_LWP */
2746   {
2747     { "lwpins", { { OP_LWP_E, 0 }, Ed, { OP_LWP_I, 0 } } },
2748     { "lwpval", { { OP_LWP_E, 0 }, Ed, { OP_LWP_I, 0 } } },
2749   },
2750 };
2751
2752 static const struct dis386 prefix_table[][4] = {
2753   /* PREFIX_90 */
2754   {
2755     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } } },
2756     { "pause", { XX } },
2757     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } } },
2758   },
2759
2760   /* PREFIX_0F10 */
2761   {
2762     { "movups", { XM, EXx } },
2763     { "movss",  { XM, EXd } },
2764     { "movupd", { XM, EXx } },
2765     { "movsd",  { XM, EXq } },
2766   },
2767
2768   /* PREFIX_0F11 */
2769   {
2770     { "movups", { EXxS, XM } },
2771     { "movss",  { EXdS, XM } },
2772     { "movupd", { EXxS, XM } },
2773     { "movsd",  { EXqS, XM } },
2774   },
2775
2776   /* PREFIX_0F12 */
2777   {
2778     { MOD_TABLE (MOD_0F12_PREFIX_0) },
2779     { "movsldup", { XM, EXx } },
2780     { "movlpd", { XM, EXq } },
2781     { "movddup", { XM, EXq } },
2782   },
2783
2784   /* PREFIX_0F16 */
2785   {
2786     { MOD_TABLE (MOD_0F16_PREFIX_0) },
2787     { "movshdup", { XM, EXx } },
2788     { "movhpd", { XM, EXq } },
2789   },
2790
2791   /* PREFIX_0F2A */
2792   {
2793     { "cvtpi2ps", { XM, EMCq } },
2794     { "cvtsi2ss%LQ", { XM, Ev } },
2795     { "cvtpi2pd", { XM, EMCq } },
2796     { "cvtsi2sd%LQ", { XM, Ev } },
2797   },
2798
2799   /* PREFIX_0F2B */
2800   {
2801     { MOD_TABLE (MOD_0F2B_PREFIX_0) },
2802     { MOD_TABLE (MOD_0F2B_PREFIX_1) },
2803     { MOD_TABLE (MOD_0F2B_PREFIX_2) },
2804     { MOD_TABLE (MOD_0F2B_PREFIX_3) },
2805   },
2806
2807   /* PREFIX_0F2C */
2808   {
2809     { "cvttps2pi", { MXC, EXq } },
2810     { "cvttss2siY", { Gv, EXd } },
2811     { "cvttpd2pi", { MXC, EXx } },
2812     { "cvttsd2siY", { Gv, EXq } },
2813   },
2814
2815   /* PREFIX_0F2D */
2816   {
2817     { "cvtps2pi", { MXC, EXq } },
2818     { "cvtss2siY", { Gv, EXd } },
2819     { "cvtpd2pi", { MXC, EXx } },
2820     { "cvtsd2siY", { Gv, EXq } },
2821   },
2822
2823   /* PREFIX_0F2E */
2824   {
2825     { "ucomiss",{ XM, EXd } },
2826     { Bad_Opcode },
2827     { "ucomisd",{ XM, EXq } },
2828   },
2829
2830   /* PREFIX_0F2F */
2831   {
2832     { "comiss", { XM, EXd } },
2833     { Bad_Opcode },
2834     { "comisd", { XM, EXq } },
2835   },
2836
2837   /* PREFIX_0F51 */
2838   {
2839     { "sqrtps", { XM, EXx } },
2840     { "sqrtss", { XM, EXd } },
2841     { "sqrtpd", { XM, EXx } },
2842     { "sqrtsd", { XM, EXq } },
2843   },
2844
2845   /* PREFIX_0F52 */
2846   {
2847     { "rsqrtps",{ XM, EXx } },
2848     { "rsqrtss",{ XM, EXd } },
2849   },
2850
2851   /* PREFIX_0F53 */
2852   {
2853     { "rcpps",  { XM, EXx } },
2854     { "rcpss",  { XM, EXd } },
2855   },
2856
2857   /* PREFIX_0F58 */
2858   {
2859     { "addps", { XM, EXx } },
2860     { "addss", { XM, EXd } },
2861     { "addpd", { XM, EXx } },
2862     { "addsd", { XM, EXq } },
2863   },
2864
2865   /* PREFIX_0F59 */
2866   {
2867     { "mulps",  { XM, EXx } },
2868     { "mulss",  { XM, EXd } },
2869     { "mulpd",  { XM, EXx } },
2870     { "mulsd",  { XM, EXq } },
2871   },
2872
2873   /* PREFIX_0F5A */
2874   {
2875     { "cvtps2pd", { XM, EXq } },
2876     { "cvtss2sd", { XM, EXd } },
2877     { "cvtpd2ps", { XM, EXx } },
2878     { "cvtsd2ss", { XM, EXq } },
2879   },
2880
2881   /* PREFIX_0F5B */
2882   {
2883     { "cvtdq2ps", { XM, EXx } },
2884     { "cvttps2dq", { XM, EXx } },
2885     { "cvtps2dq", { XM, EXx } },
2886   },
2887
2888   /* PREFIX_0F5C */
2889   {
2890     { "subps",  { XM, EXx } },
2891     { "subss",  { XM, EXd } },
2892     { "subpd",  { XM, EXx } },
2893     { "subsd",  { XM, EXq } },
2894   },
2895
2896   /* PREFIX_0F5D */
2897   {
2898     { "minps",  { XM, EXx } },
2899     { "minss",  { XM, EXd } },
2900     { "minpd",  { XM, EXx } },
2901     { "minsd",  { XM, EXq } },
2902   },
2903
2904   /* PREFIX_0F5E */
2905   {
2906     { "divps",  { XM, EXx } },
2907     { "divss",  { XM, EXd } },
2908     { "divpd",  { XM, EXx } },
2909     { "divsd",  { XM, EXq } },
2910   },
2911
2912   /* PREFIX_0F5F */
2913   {
2914     { "maxps",  { XM, EXx } },
2915     { "maxss",  { XM, EXd } },
2916     { "maxpd",  { XM, EXx } },
2917     { "maxsd",  { XM, EXq } },
2918   },
2919
2920   /* PREFIX_0F60 */
2921   {
2922     { "punpcklbw",{ MX, EMd } },
2923     { Bad_Opcode },
2924     { "punpcklbw",{ MX, EMx } },
2925   },
2926
2927   /* PREFIX_0F61 */
2928   {
2929     { "punpcklwd",{ MX, EMd } },
2930     { Bad_Opcode },
2931     { "punpcklwd",{ MX, EMx } },
2932   },
2933
2934   /* PREFIX_0F62 */
2935   {
2936     { "punpckldq",{ MX, EMd } },
2937     { Bad_Opcode },
2938     { "punpckldq",{ MX, EMx } },
2939   },
2940
2941   /* PREFIX_0F6C */
2942   {
2943     { Bad_Opcode },
2944     { Bad_Opcode },
2945     { "punpcklqdq", { XM, EXx } },
2946   },
2947
2948   /* PREFIX_0F6D */
2949   {
2950     { Bad_Opcode },
2951     { Bad_Opcode },
2952     { "punpckhqdq", { XM, EXx } },
2953   },
2954
2955   /* PREFIX_0F6F */
2956   {
2957     { "movq",   { MX, EM } },
2958     { "movdqu", { XM, EXx } },
2959     { "movdqa", { XM, EXx } },
2960   },
2961
2962   /* PREFIX_0F70 */
2963   {
2964     { "pshufw", { MX, EM, Ib } },
2965     { "pshufhw",{ XM, EXx, Ib } },
2966     { "pshufd", { XM, EXx, Ib } },
2967     { "pshuflw",{ XM, EXx, Ib } },
2968   },
2969
2970   /* PREFIX_0F73_REG_3 */
2971   {
2972     { Bad_Opcode },
2973     { Bad_Opcode },
2974     { "psrldq", { XS, Ib } },
2975   },
2976
2977   /* PREFIX_0F73_REG_7 */
2978   {
2979     { Bad_Opcode },
2980     { Bad_Opcode },
2981     { "pslldq", { XS, Ib } },
2982   },
2983
2984   /* PREFIX_0F78 */
2985   {
2986     {"vmread",  { Em, Gm } },
2987     { Bad_Opcode },
2988     {"extrq",   { XS, Ib, Ib } },
2989     {"insertq", { XM, XS, Ib, Ib } },
2990   },
2991
2992   /* PREFIX_0F79 */
2993   {
2994     {"vmwrite", { Gm, Em } },
2995     { Bad_Opcode },
2996     {"extrq",   { XM, XS } },
2997     {"insertq", { XM, XS } },
2998   },
2999
3000   /* PREFIX_0F7C */
3001   {
3002     { Bad_Opcode },
3003     { Bad_Opcode },
3004     { "haddpd", { XM, EXx } },
3005     { "haddps", { XM, EXx } },
3006   },
3007
3008   /* PREFIX_0F7D */
3009   {
3010     { Bad_Opcode },
3011     { Bad_Opcode },
3012     { "hsubpd", { XM, EXx } },
3013     { "hsubps", { XM, EXx } },
3014   },
3015
3016   /* PREFIX_0F7E */
3017   {
3018     { "movK",   { Edq, MX } },
3019     { "movq",   { XM, EXq } },
3020     { "movK",   { Edq, XM } },
3021   },
3022
3023   /* PREFIX_0F7F */
3024   {
3025     { "movq",   { EMS, MX } },
3026     { "movdqu", { EXxS, XM } },
3027     { "movdqa", { EXxS, XM } },
3028   },
3029
3030   /* PREFIX_0FB8 */
3031   {
3032     { Bad_Opcode },
3033     { "popcntS", { Gv, Ev } },
3034   },
3035
3036   /* PREFIX_0FBD */
3037   {
3038     { "bsrS",   { Gv, Ev } },
3039     { "lzcntS", { Gv, Ev } },
3040     { "bsrS",   { Gv, Ev } },
3041   },
3042
3043   /* PREFIX_0FC2 */
3044   {
3045     { "cmpps",  { XM, EXx, CMP } },
3046     { "cmpss",  { XM, EXd, CMP } },
3047     { "cmppd",  { XM, EXx, CMP } },
3048     { "cmpsd",  { XM, EXq, CMP } },
3049   },
3050
3051   /* PREFIX_0FC3 */
3052   {
3053     { "movntiS", { Ma, Gv } },
3054   },
3055
3056   /* PREFIX_0FC7_REG_6 */
3057   {
3058     { "vmptrld",{ Mq } },
3059     { "vmxon",  { Mq } },
3060     { "vmclear",{ Mq } },
3061   },
3062
3063   /* PREFIX_0FD0 */
3064   {
3065     { Bad_Opcode },
3066     { Bad_Opcode },
3067     { "addsubpd", { XM, EXx } },
3068     { "addsubps", { XM, EXx } },
3069   },
3070
3071   /* PREFIX_0FD6 */
3072   {
3073     { Bad_Opcode },
3074     { "movq2dq",{ XM, MS } },
3075     { "movq",   { EXqS, XM } },
3076     { "movdq2q",{ MX, XS } },
3077   },
3078
3079   /* PREFIX_0FE6 */
3080   {
3081     { Bad_Opcode },
3082     { "cvtdq2pd", { XM, EXq } },
3083     { "cvttpd2dq", { XM, EXx } },
3084     { "cvtpd2dq", { XM, EXx } },
3085   },
3086
3087   /* PREFIX_0FE7 */
3088   {
3089     { "movntq", { Mq, MX } },
3090     { Bad_Opcode },
3091     { MOD_TABLE (MOD_0FE7_PREFIX_2) },
3092   },
3093
3094   /* PREFIX_0FF0 */
3095   {
3096     { Bad_Opcode },
3097     { Bad_Opcode },
3098     { Bad_Opcode },
3099     { MOD_TABLE (MOD_0FF0_PREFIX_3) },
3100   },
3101
3102   /* PREFIX_0FF7 */
3103   {
3104     { "maskmovq", { MX, MS } },
3105     { Bad_Opcode },
3106     { "maskmovdqu", { XM, XS } },
3107   },
3108
3109   /* PREFIX_0F3810 */
3110   {
3111     { Bad_Opcode },
3112     { Bad_Opcode },
3113     { "pblendvb", { XM, EXx, XMM0 } },
3114   },
3115
3116   /* PREFIX_0F3814 */
3117   {
3118     { Bad_Opcode },
3119     { Bad_Opcode },
3120     { "blendvps", { XM, EXx, XMM0 } },
3121   },
3122
3123   /* PREFIX_0F3815 */
3124   {
3125     { Bad_Opcode },
3126     { Bad_Opcode },
3127     { "blendvpd", { XM, EXx, XMM0 } },
3128   },
3129
3130   /* PREFIX_0F3817 */
3131   {
3132     { Bad_Opcode },
3133     { Bad_Opcode },
3134     { "ptest",  { XM, EXx } },
3135   },
3136
3137   /* PREFIX_0F3820 */
3138   {
3139     { Bad_Opcode },
3140     { Bad_Opcode },
3141     { "pmovsxbw", { XM, EXq } },
3142   },
3143
3144   /* PREFIX_0F3821 */
3145   {
3146     { Bad_Opcode },
3147     { Bad_Opcode },
3148     { "pmovsxbd", { XM, EXd } },
3149   },
3150
3151   /* PREFIX_0F3822 */
3152   {
3153     { Bad_Opcode },
3154     { Bad_Opcode },
3155     { "pmovsxbq", { XM, EXw } },
3156   },
3157
3158   /* PREFIX_0F3823 */
3159   {
3160     { Bad_Opcode },
3161     { Bad_Opcode },
3162     { "pmovsxwd", { XM, EXq } },
3163   },
3164
3165   /* PREFIX_0F3824 */
3166   {
3167     { Bad_Opcode },
3168     { Bad_Opcode },
3169     { "pmovsxwq", { XM, EXd } },
3170   },
3171
3172   /* PREFIX_0F3825 */
3173   {
3174     { Bad_Opcode },
3175     { Bad_Opcode },
3176     { "pmovsxdq", { XM, EXq } },
3177   },
3178
3179   /* PREFIX_0F3828 */
3180   {
3181     { Bad_Opcode },
3182     { Bad_Opcode },
3183     { "pmuldq", { XM, EXx } },
3184   },
3185
3186   /* PREFIX_0F3829 */
3187   {
3188     { Bad_Opcode },
3189     { Bad_Opcode },
3190     { "pcmpeqq", { XM, EXx } },
3191   },
3192
3193   /* PREFIX_0F382A */
3194   {
3195     { Bad_Opcode },
3196     { Bad_Opcode },
3197     { MOD_TABLE (MOD_0F382A_PREFIX_2) },
3198   },
3199
3200   /* PREFIX_0F382B */
3201   {
3202     { Bad_Opcode },
3203     { Bad_Opcode },
3204     { "packusdw", { XM, EXx } },
3205   },
3206
3207   /* PREFIX_0F3830 */
3208   {
3209     { Bad_Opcode },
3210     { Bad_Opcode },
3211     { "pmovzxbw", { XM, EXq } },
3212   },
3213
3214   /* PREFIX_0F3831 */
3215   {
3216     { Bad_Opcode },
3217     { Bad_Opcode },
3218     { "pmovzxbd", { XM, EXd } },
3219   },
3220
3221   /* PREFIX_0F3832 */
3222   {
3223     { Bad_Opcode },
3224     { Bad_Opcode },
3225     { "pmovzxbq", { XM, EXw } },
3226   },
3227
3228   /* PREFIX_0F3833 */
3229   {
3230     { Bad_Opcode },
3231     { Bad_Opcode },
3232     { "pmovzxwd", { XM, EXq } },
3233   },
3234
3235   /* PREFIX_0F3834 */
3236   {
3237     { Bad_Opcode },
3238     { Bad_Opcode },
3239     { "pmovzxwq", { XM, EXd } },
3240   },
3241
3242   /* PREFIX_0F3835 */
3243   {
3244     { Bad_Opcode },
3245     { Bad_Opcode },
3246     { "pmovzxdq", { XM, EXq } },
3247   },
3248
3249   /* PREFIX_0F3837 */
3250   {
3251     { Bad_Opcode },
3252     { Bad_Opcode },
3253     { "pcmpgtq", { XM, EXx } },
3254   },
3255
3256   /* PREFIX_0F3838 */
3257   {
3258     { Bad_Opcode },
3259     { Bad_Opcode },
3260     { "pminsb", { XM, EXx } },
3261   },
3262
3263   /* PREFIX_0F3839 */
3264   {
3265     { Bad_Opcode },
3266     { Bad_Opcode },
3267     { "pminsd", { XM, EXx } },
3268   },
3269
3270   /* PREFIX_0F383A */
3271   {
3272     { Bad_Opcode },
3273     { Bad_Opcode },
3274     { "pminuw", { XM, EXx } },
3275   },
3276
3277   /* PREFIX_0F383B */
3278   {
3279     { Bad_Opcode },
3280     { Bad_Opcode },
3281     { "pminud", { XM, EXx } },
3282   },
3283
3284   /* PREFIX_0F383C */
3285   {
3286     { Bad_Opcode },
3287     { Bad_Opcode },
3288     { "pmaxsb", { XM, EXx } },
3289   },
3290
3291   /* PREFIX_0F383D */
3292   {
3293     { Bad_Opcode },
3294     { Bad_Opcode },
3295     { "pmaxsd", { XM, EXx } },
3296   },
3297
3298   /* PREFIX_0F383E */
3299   {
3300     { Bad_Opcode },
3301     { Bad_Opcode },
3302     { "pmaxuw", { XM, EXx } },
3303   },
3304
3305   /* PREFIX_0F383F */
3306   {
3307     { Bad_Opcode },
3308     { Bad_Opcode },
3309     { "pmaxud", { XM, EXx } },
3310   },
3311
3312   /* PREFIX_0F3840 */
3313   {
3314     { Bad_Opcode },
3315     { Bad_Opcode },
3316     { "pmulld", { XM, EXx } },
3317   },
3318
3319   /* PREFIX_0F3841 */
3320   {
3321     { Bad_Opcode },
3322     { Bad_Opcode },
3323     { "phminposuw", { XM, EXx } },
3324   },
3325
3326   /* PREFIX_0F3880 */
3327   {
3328     { Bad_Opcode },
3329     { Bad_Opcode },
3330     { "invept", { Gm, Mo } },
3331   },
3332
3333   /* PREFIX_0F3881 */
3334   {
3335     { Bad_Opcode },
3336     { Bad_Opcode },
3337     { "invvpid", { Gm, Mo } },
3338   },
3339
3340   /* PREFIX_0F38DB */
3341   {
3342     { Bad_Opcode },
3343     { Bad_Opcode },
3344     { "aesimc", { XM, EXx } },
3345   },
3346
3347   /* PREFIX_0F38DC */
3348   {
3349     { Bad_Opcode },
3350     { Bad_Opcode },
3351     { "aesenc", { XM, EXx } },
3352   },
3353
3354   /* PREFIX_0F38DD */
3355   {
3356     { Bad_Opcode },
3357     { Bad_Opcode },
3358     { "aesenclast", { XM, EXx } },
3359   },
3360
3361   /* PREFIX_0F38DE */
3362   {
3363     { Bad_Opcode },
3364     { Bad_Opcode },
3365     { "aesdec", { XM, EXx } },
3366   },
3367
3368   /* PREFIX_0F38DF */
3369   {
3370     { Bad_Opcode },
3371     { Bad_Opcode },
3372     { "aesdeclast", { XM, EXx } },
3373   },
3374
3375   /* PREFIX_0F38F0 */
3376   {
3377     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } } },
3378     { Bad_Opcode },
3379     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } } },
3380     { "crc32",  { Gdq, { CRC32_Fixup, b_mode } } },
3381   },
3382
3383   /* PREFIX_0F38F1 */
3384   {
3385     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv } },
3386     { Bad_Opcode },
3387     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv } },
3388     { "crc32",  { Gdq, { CRC32_Fixup, v_mode } } },
3389   },
3390
3391   /* PREFIX_0F3A08 */
3392   {
3393     { Bad_Opcode },
3394     { Bad_Opcode },
3395     { "roundps", { XM, EXx, Ib } },
3396   },
3397
3398   /* PREFIX_0F3A09 */
3399   {
3400     { Bad_Opcode },
3401     { Bad_Opcode },
3402     { "roundpd", { XM, EXx, Ib } },
3403   },
3404
3405   /* PREFIX_0F3A0A */
3406   {
3407     { Bad_Opcode },
3408     { Bad_Opcode },
3409     { "roundss", { XM, EXd, Ib } },
3410   },
3411
3412   /* PREFIX_0F3A0B */
3413   {
3414     { Bad_Opcode },
3415     { Bad_Opcode },
3416     { "roundsd", { XM, EXq, Ib } },
3417   },
3418
3419   /* PREFIX_0F3A0C */
3420   {
3421     { Bad_Opcode },
3422     { Bad_Opcode },
3423     { "blendps", { XM, EXx, Ib } },
3424   },
3425
3426   /* PREFIX_0F3A0D */
3427   {
3428     { Bad_Opcode },
3429     { Bad_Opcode },
3430     { "blendpd", { XM, EXx, Ib } },
3431   },
3432
3433   /* PREFIX_0F3A0E */
3434   {
3435     { Bad_Opcode },
3436     { Bad_Opcode },
3437     { "pblendw", { XM, EXx, Ib } },
3438   },
3439
3440   /* PREFIX_0F3A14 */
3441   {
3442     { Bad_Opcode },
3443     { Bad_Opcode },
3444     { "pextrb", { Edqb, XM, Ib } },
3445   },
3446
3447   /* PREFIX_0F3A15 */
3448   {
3449     { Bad_Opcode },
3450     { Bad_Opcode },
3451     { "pextrw", { Edqw, XM, Ib } },
3452   },
3453
3454   /* PREFIX_0F3A16 */
3455   {
3456     { Bad_Opcode },
3457     { Bad_Opcode },
3458     { "pextrK", { Edq, XM, Ib } },
3459   },
3460
3461   /* PREFIX_0F3A17 */
3462   {
3463     { Bad_Opcode },
3464     { Bad_Opcode },
3465     { "extractps", { Edqd, XM, Ib } },
3466   },
3467
3468   /* PREFIX_0F3A20 */
3469   {
3470     { Bad_Opcode },
3471     { Bad_Opcode },
3472     { "pinsrb", { XM, Edqb, Ib } },
3473   },
3474
3475   /* PREFIX_0F3A21 */
3476   {
3477     { Bad_Opcode },
3478     { Bad_Opcode },
3479     { "insertps", { XM, EXd, Ib } },
3480   },
3481
3482   /* PREFIX_0F3A22 */
3483   {
3484     { Bad_Opcode },
3485     { Bad_Opcode },
3486     { "pinsrK", { XM, Edq, Ib } },
3487   },
3488
3489   /* PREFIX_0F3A40 */
3490   {
3491     { Bad_Opcode },
3492     { Bad_Opcode },
3493     { "dpps",   { XM, EXx, Ib } },
3494   },
3495
3496   /* PREFIX_0F3A41 */
3497   {
3498     { Bad_Opcode },
3499     { Bad_Opcode },
3500     { "dppd",   { XM, EXx, Ib } },
3501   },
3502
3503   /* PREFIX_0F3A42 */
3504   {
3505     { Bad_Opcode },
3506     { Bad_Opcode },
3507     { "mpsadbw", { XM, EXx, Ib } },
3508   },
3509
3510   /* PREFIX_0F3A44 */
3511   {
3512     { Bad_Opcode },
3513     { Bad_Opcode },
3514     { "pclmulqdq", { XM, EXx, PCLMUL } },
3515   },
3516
3517   /* PREFIX_0F3A60 */
3518   {
3519     { Bad_Opcode },
3520     { Bad_Opcode },
3521     { "pcmpestrm", { XM, EXx, Ib } },
3522   },
3523
3524   /* PREFIX_0F3A61 */
3525   {
3526     { Bad_Opcode },
3527     { Bad_Opcode },
3528     { "pcmpestri", { XM, EXx, Ib } },
3529   },
3530
3531   /* PREFIX_0F3A62 */
3532   {
3533     { Bad_Opcode },
3534     { Bad_Opcode },
3535     { "pcmpistrm", { XM, EXx, Ib } },
3536   },
3537
3538   /* PREFIX_0F3A63 */
3539   {
3540     { Bad_Opcode },
3541     { Bad_Opcode },
3542     { "pcmpistri", { XM, EXx, Ib } },
3543   },
3544
3545   /* PREFIX_0F3ADF */
3546   {
3547     { Bad_Opcode },
3548     { Bad_Opcode },
3549     { "aeskeygenassist", { XM, EXx, Ib } },
3550   },
3551
3552   /* PREFIX_VEX_10 */
3553   {
3554     { VEX_W_TABLE (VEX_W_10_P_0) },
3555     { VEX_LEN_TABLE (VEX_LEN_10_P_1) },
3556     { VEX_W_TABLE (VEX_W_10_P_2) },
3557     { VEX_LEN_TABLE (VEX_LEN_10_P_3) },
3558   },
3559
3560   /* PREFIX_VEX_11 */
3561   {
3562     { VEX_W_TABLE (VEX_W_11_P_0) },
3563     { VEX_LEN_TABLE (VEX_LEN_11_P_1) },
3564     { VEX_W_TABLE (VEX_W_11_P_2) },
3565     { VEX_LEN_TABLE (VEX_LEN_11_P_3) },
3566   },
3567
3568   /* PREFIX_VEX_12 */
3569   {
3570     { MOD_TABLE (MOD_VEX_12_PREFIX_0) },
3571     { VEX_W_TABLE (VEX_W_12_P_1) },
3572     { VEX_LEN_TABLE (VEX_LEN_12_P_2) },
3573     { VEX_W_TABLE (VEX_W_12_P_3) },
3574   },
3575
3576   /* PREFIX_VEX_16 */
3577   {
3578     { MOD_TABLE (MOD_VEX_16_PREFIX_0) },
3579     { VEX_W_TABLE (VEX_W_16_P_1) },
3580     { VEX_LEN_TABLE (VEX_LEN_16_P_2) },
3581   },
3582
3583   /* PREFIX_VEX_2A */
3584   {
3585     { Bad_Opcode },
3586     { VEX_LEN_TABLE (VEX_LEN_2A_P_1) },
3587     { Bad_Opcode },
3588     { VEX_LEN_TABLE (VEX_LEN_2A_P_3) },
3589   },
3590
3591   /* PREFIX_VEX_2C */
3592   {
3593     { Bad_Opcode },
3594     { VEX_LEN_TABLE (VEX_LEN_2C_P_1) },
3595     { Bad_Opcode },
3596     { VEX_LEN_TABLE (VEX_LEN_2C_P_3) },
3597   },
3598
3599   /* PREFIX_VEX_2D */
3600   {
3601     { Bad_Opcode },
3602     { VEX_LEN_TABLE (VEX_LEN_2D_P_1) },
3603     { Bad_Opcode },
3604     { VEX_LEN_TABLE (VEX_LEN_2D_P_3) },
3605   },
3606
3607   /* PREFIX_VEX_2E */
3608   {
3609     { VEX_LEN_TABLE (VEX_LEN_2E_P_0) },
3610     { Bad_Opcode },
3611     { VEX_LEN_TABLE (VEX_LEN_2E_P_2) },
3612   },
3613
3614   /* PREFIX_VEX_2F */
3615   {
3616     { VEX_LEN_TABLE (VEX_LEN_2F_P_0) },
3617     { Bad_Opcode },
3618     { VEX_LEN_TABLE (VEX_LEN_2F_P_2) },
3619   },
3620
3621   /* PREFIX_VEX_51 */
3622   {
3623     { VEX_W_TABLE (VEX_W_51_P_0) },
3624     { VEX_LEN_TABLE (VEX_LEN_51_P_1) },
3625     { VEX_W_TABLE (VEX_W_51_P_2) },
3626     { VEX_LEN_TABLE (VEX_LEN_51_P_3) },
3627   },
3628
3629   /* PREFIX_VEX_52 */
3630   {
3631     { VEX_W_TABLE (VEX_W_52_P_0) },
3632     { VEX_LEN_TABLE (VEX_LEN_52_P_1) },
3633   },
3634
3635   /* PREFIX_VEX_53 */
3636   {
3637     { VEX_W_TABLE (VEX_W_53_P_0) },
3638     { VEX_LEN_TABLE (VEX_LEN_53_P_1) },
3639   },
3640
3641   /* PREFIX_VEX_58 */
3642   {
3643     { VEX_W_TABLE (VEX_W_58_P_0) },
3644     { VEX_LEN_TABLE (VEX_LEN_58_P_1) },
3645     { VEX_W_TABLE (VEX_W_58_P_2) },
3646     { VEX_LEN_TABLE (VEX_LEN_58_P_3) },
3647   },
3648
3649   /* PREFIX_VEX_59 */
3650   {
3651     { VEX_W_TABLE (VEX_W_59_P_0) },
3652     { VEX_LEN_TABLE (VEX_LEN_59_P_1) },
3653     { VEX_W_TABLE (VEX_W_59_P_2) },
3654     { VEX_LEN_TABLE (VEX_LEN_59_P_3) },
3655   },
3656
3657   /* PREFIX_VEX_5A */
3658   {
3659     { VEX_W_TABLE (VEX_W_5A_P_0) },
3660     { VEX_LEN_TABLE (VEX_LEN_5A_P_1) },
3661     { "vcvtpd2ps%XY", { XMM, EXx } },
3662     { VEX_LEN_TABLE (VEX_LEN_5A_P_3) },
3663   },
3664
3665   /* PREFIX_VEX_5B */
3666   {
3667     { VEX_W_TABLE (VEX_W_5B_P_0) },
3668     { VEX_W_TABLE (VEX_W_5B_P_1) },
3669     { VEX_W_TABLE (VEX_W_5B_P_2) },
3670   },
3671
3672   /* PREFIX_VEX_5C */
3673   {
3674     { VEX_W_TABLE (VEX_W_5C_P_0) },
3675     { VEX_LEN_TABLE (VEX_LEN_5C_P_1) },
3676     { VEX_W_TABLE (VEX_W_5C_P_2) },
3677     { VEX_LEN_TABLE (VEX_LEN_5C_P_3) },
3678   },
3679
3680   /* PREFIX_VEX_5D */
3681   {
3682     { VEX_W_TABLE (VEX_W_5D_P_0) },
3683     { VEX_LEN_TABLE (VEX_LEN_5D_P_1) },
3684     { VEX_W_TABLE (VEX_W_5D_P_2) },
3685     { VEX_LEN_TABLE (VEX_LEN_5D_P_3) },
3686   },
3687
3688   /* PREFIX_VEX_5E */
3689   {
3690     { VEX_W_TABLE (VEX_W_5E_P_0) },
3691     { VEX_LEN_TABLE (VEX_LEN_5E_P_1) },
3692     { VEX_W_TABLE (VEX_W_5E_P_2) },
3693     { VEX_LEN_TABLE (VEX_LEN_5E_P_3) },
3694   },
3695
3696   /* PREFIX_VEX_5F */
3697   {
3698     { VEX_W_TABLE (VEX_W_5F_P_0) },
3699     { VEX_LEN_TABLE (VEX_LEN_5F_P_1) },
3700     { VEX_W_TABLE (VEX_W_5F_P_2) },
3701     { VEX_LEN_TABLE (VEX_LEN_5F_P_3) },
3702   },
3703
3704   /* PREFIX_VEX_60 */
3705   {
3706     { Bad_Opcode },
3707     { Bad_Opcode },
3708     { VEX_LEN_TABLE (VEX_LEN_60_P_2) },
3709   },
3710
3711   /* PREFIX_VEX_61 */
3712   {
3713     { Bad_Opcode },
3714     { Bad_Opcode },
3715     { VEX_LEN_TABLE (VEX_LEN_61_P_2) },
3716   },
3717
3718   /* PREFIX_VEX_62 */
3719   {
3720     { Bad_Opcode },
3721     { Bad_Opcode },
3722     { VEX_LEN_TABLE (VEX_LEN_62_P_2) },
3723   },
3724
3725   /* PREFIX_VEX_63 */
3726   {
3727     { Bad_Opcode },
3728     { Bad_Opcode },
3729     { VEX_LEN_TABLE (VEX_LEN_63_P_2) },
3730   },
3731
3732   /* PREFIX_VEX_64 */
3733   {
3734     { Bad_Opcode },
3735     { Bad_Opcode },
3736     { VEX_LEN_TABLE (VEX_LEN_64_P_2) },
3737   },
3738
3739   /* PREFIX_VEX_65 */
3740   {
3741     { Bad_Opcode },
3742     { Bad_Opcode },
3743     { VEX_LEN_TABLE (VEX_LEN_65_P_2) },
3744   },
3745
3746   /* PREFIX_VEX_66 */
3747   {
3748     { Bad_Opcode },
3749     { Bad_Opcode },
3750     { VEX_LEN_TABLE (VEX_LEN_66_P_2) },
3751   },
3752
3753   /* PREFIX_VEX_67 */
3754   {
3755     { Bad_Opcode },
3756     { Bad_Opcode },
3757     { VEX_LEN_TABLE (VEX_LEN_67_P_2) },
3758   },
3759
3760   /* PREFIX_VEX_68 */
3761   {
3762     { Bad_Opcode },
3763     { Bad_Opcode },
3764     { VEX_LEN_TABLE (VEX_LEN_68_P_2) },
3765   },
3766
3767   /* PREFIX_VEX_69 */
3768   {
3769     { Bad_Opcode },
3770     { Bad_Opcode },
3771     { VEX_LEN_TABLE (VEX_LEN_69_P_2) },
3772   },
3773
3774   /* PREFIX_VEX_6A */
3775   {
3776     { Bad_Opcode },
3777     { Bad_Opcode },
3778     { VEX_LEN_TABLE (VEX_LEN_6A_P_2) },
3779   },
3780
3781   /* PREFIX_VEX_6B */
3782   {
3783     { Bad_Opcode },
3784     { Bad_Opcode },
3785     { VEX_LEN_TABLE (VEX_LEN_6B_P_2) },
3786   },
3787
3788   /* PREFIX_VEX_6C */
3789   {
3790     { Bad_Opcode },
3791     { Bad_Opcode },
3792     { VEX_LEN_TABLE (VEX_LEN_6C_P_2) },
3793   },
3794
3795   /* PREFIX_VEX_6D */
3796   {
3797     { Bad_Opcode },
3798     { Bad_Opcode },
3799     { VEX_LEN_TABLE (VEX_LEN_6D_P_2) },
3800   },
3801
3802   /* PREFIX_VEX_6E */
3803   {
3804     { Bad_Opcode },
3805     { Bad_Opcode },
3806     { VEX_LEN_TABLE (VEX_LEN_6E_P_2) },
3807   },
3808
3809   /* PREFIX_VEX_6F */
3810   {
3811     { Bad_Opcode },
3812     { VEX_W_TABLE (VEX_W_6F_P_1) },
3813     { VEX_W_TABLE (VEX_W_6F_P_2) },
3814   },
3815
3816   /* PREFIX_VEX_70 */
3817   {
3818     { Bad_Opcode },
3819     { VEX_LEN_TABLE (VEX_LEN_70_P_1) },
3820     { VEX_LEN_TABLE (VEX_LEN_70_P_2) },
3821     { VEX_LEN_TABLE (VEX_LEN_70_P_3) },
3822   },
3823
3824   /* PREFIX_VEX_71_REG_2 */
3825   {
3826     { Bad_Opcode },
3827     { Bad_Opcode },
3828     { VEX_LEN_TABLE (VEX_LEN_71_R_2_P_2) },
3829   },
3830
3831   /* PREFIX_VEX_71_REG_4 */
3832   {
3833     { Bad_Opcode },
3834     { Bad_Opcode },
3835     { VEX_LEN_TABLE (VEX_LEN_71_R_4_P_2) },
3836   },
3837
3838   /* PREFIX_VEX_71_REG_6 */
3839   {
3840     { Bad_Opcode },
3841     { Bad_Opcode },
3842     { VEX_LEN_TABLE (VEX_LEN_71_R_6_P_2) },
3843   },
3844
3845   /* PREFIX_VEX_72_REG_2 */
3846   {
3847     { Bad_Opcode },
3848     { Bad_Opcode },
3849     { VEX_LEN_TABLE (VEX_LEN_72_R_2_P_2) },
3850   },
3851
3852   /* PREFIX_VEX_72_REG_4 */
3853   {
3854     { Bad_Opcode },
3855     { Bad_Opcode },
3856     { VEX_LEN_TABLE (VEX_LEN_72_R_4_P_2) },
3857   },
3858
3859   /* PREFIX_VEX_72_REG_6 */
3860   {
3861     { Bad_Opcode },
3862     { Bad_Opcode },
3863     { VEX_LEN_TABLE (VEX_LEN_72_R_6_P_2) },
3864   },
3865
3866   /* PREFIX_VEX_73_REG_2 */
3867   {
3868     { Bad_Opcode },
3869     { Bad_Opcode },
3870     { VEX_LEN_TABLE (VEX_LEN_73_R_2_P_2) },
3871   },
3872
3873   /* PREFIX_VEX_73_REG_3 */
3874   {
3875     { Bad_Opcode },
3876     { Bad_Opcode },
3877     { VEX_LEN_TABLE (VEX_LEN_73_R_3_P_2) },
3878   },
3879
3880   /* PREFIX_VEX_73_REG_6 */
3881   {
3882     { Bad_Opcode },
3883     { Bad_Opcode },
3884     { VEX_LEN_TABLE (VEX_LEN_73_R_6_P_2) },
3885   },
3886
3887   /* PREFIX_VEX_73_REG_7 */
3888   {
3889     { Bad_Opcode },
3890     { Bad_Opcode },
3891     { VEX_LEN_TABLE (VEX_LEN_73_R_7_P_2) },
3892   },
3893
3894   /* PREFIX_VEX_74 */
3895   {
3896     { Bad_Opcode },
3897     { Bad_Opcode },
3898     { VEX_LEN_TABLE (VEX_LEN_74_P_2) },
3899   },
3900
3901   /* PREFIX_VEX_75 */
3902   {
3903     { Bad_Opcode },
3904     { Bad_Opcode },
3905     { VEX_LEN_TABLE (VEX_LEN_75_P_2) },
3906   },
3907
3908   /* PREFIX_VEX_76 */
3909   {
3910     { Bad_Opcode },
3911     { Bad_Opcode },
3912     { VEX_LEN_TABLE (VEX_LEN_76_P_2) },
3913   },
3914
3915   /* PREFIX_VEX_77 */
3916   {
3917     { VEX_W_TABLE (VEX_W_77_P_0) },
3918   },
3919
3920   /* PREFIX_VEX_7C */
3921   {
3922     { Bad_Opcode },
3923     { Bad_Opcode },
3924     { VEX_W_TABLE (VEX_W_7C_P_2) },
3925     { VEX_W_TABLE (VEX_W_7C_P_3) },
3926   },
3927
3928   /* PREFIX_VEX_7D */
3929   {
3930     { Bad_Opcode },
3931     { Bad_Opcode },
3932     { VEX_W_TABLE (VEX_W_7D_P_2) },
3933     { VEX_W_TABLE (VEX_W_7D_P_3) },
3934   },
3935
3936   /* PREFIX_VEX_7E */
3937   {
3938     { Bad_Opcode },
3939     { VEX_LEN_TABLE (VEX_LEN_7E_P_1) },
3940     { VEX_LEN_TABLE (VEX_LEN_7E_P_2) },
3941   },
3942
3943   /* PREFIX_VEX_7F */
3944   {
3945     { Bad_Opcode },
3946     { VEX_W_TABLE (VEX_W_7F_P_1) },
3947     { VEX_W_TABLE (VEX_W_7F_P_2) },
3948   },
3949
3950   /* PREFIX_VEX_C2 */
3951   {
3952     { VEX_W_TABLE (VEX_W_C2_P_0) },
3953     { VEX_LEN_TABLE (VEX_LEN_C2_P_1) },
3954     { VEX_W_TABLE (VEX_W_C2_P_2) },
3955     { VEX_LEN_TABLE (VEX_LEN_C2_P_3) },
3956   },
3957
3958   /* PREFIX_VEX_C4 */
3959   {
3960     { Bad_Opcode },
3961     { Bad_Opcode },
3962     { VEX_LEN_TABLE (VEX_LEN_C4_P_2) },
3963   },
3964
3965   /* PREFIX_VEX_C5 */
3966   {
3967     { Bad_Opcode },
3968     { Bad_Opcode },
3969     { VEX_LEN_TABLE (VEX_LEN_C5_P_2) },
3970   },
3971
3972   /* PREFIX_VEX_D0 */
3973   {
3974     { Bad_Opcode },
3975     { Bad_Opcode },
3976     { VEX_W_TABLE (VEX_W_D0_P_2) },
3977     { VEX_W_TABLE (VEX_W_D0_P_3) },
3978   },
3979
3980   /* PREFIX_VEX_D1 */
3981   {
3982     { Bad_Opcode },
3983     { Bad_Opcode },
3984     { VEX_LEN_TABLE (VEX_LEN_D1_P_2) },
3985   },
3986
3987   /* PREFIX_VEX_D2 */
3988   {
3989     { Bad_Opcode },
3990     { Bad_Opcode },
3991     { VEX_LEN_TABLE (VEX_LEN_D2_P_2) },
3992   },
3993
3994   /* PREFIX_VEX_D3 */
3995   {
3996     { Bad_Opcode },
3997     { Bad_Opcode },
3998     { VEX_LEN_TABLE (VEX_LEN_D3_P_2) },
3999   },
4000
4001   /* PREFIX_VEX_D4 */
4002   {
4003     { Bad_Opcode },
4004     { Bad_Opcode },
4005     { VEX_LEN_TABLE (VEX_LEN_D4_P_2) },
4006   },
4007
4008   /* PREFIX_VEX_D5 */
4009   {
4010     { Bad_Opcode },
4011     { Bad_Opcode },
4012     { VEX_LEN_TABLE (VEX_LEN_D5_P_2) },
4013   },
4014
4015   /* PREFIX_VEX_D6 */
4016   {
4017     { Bad_Opcode },
4018     { Bad_Opcode },
4019     { VEX_LEN_TABLE (VEX_LEN_D6_P_2) },
4020   },
4021
4022   /* PREFIX_VEX_D7 */
4023   {
4024     { Bad_Opcode },
4025     { Bad_Opcode },
4026     { MOD_TABLE (MOD_VEX_D7_PREFIX_2) },
4027   },
4028
4029   /* PREFIX_VEX_D8 */
4030   {
4031     { Bad_Opcode },
4032     { Bad_Opcode },
4033     { VEX_LEN_TABLE (VEX_LEN_D8_P_2) },
4034   },
4035
4036   /* PREFIX_VEX_D9 */
4037   {
4038     { Bad_Opcode },
4039     { Bad_Opcode },
4040     { VEX_LEN_TABLE (VEX_LEN_D9_P_2) },
4041   },
4042
4043   /* PREFIX_VEX_DA */
4044   {
4045     { Bad_Opcode },
4046     { Bad_Opcode },
4047     { VEX_LEN_TABLE (VEX_LEN_DA_P_2) },
4048   },
4049
4050   /* PREFIX_VEX_DB */
4051   {
4052     { Bad_Opcode },
4053     { Bad_Opcode },
4054     { VEX_LEN_TABLE (VEX_LEN_DB_P_2) },
4055   },
4056
4057   /* PREFIX_VEX_DC */
4058   {
4059     { Bad_Opcode },
4060     { Bad_Opcode },
4061     { VEX_LEN_TABLE (VEX_LEN_DC_P_2) },
4062   },
4063
4064   /* PREFIX_VEX_DD */
4065   {
4066     { Bad_Opcode },
4067     { Bad_Opcode },
4068     { VEX_LEN_TABLE (VEX_LEN_DD_P_2) },
4069   },
4070
4071   /* PREFIX_VEX_DE */
4072   {
4073     { Bad_Opcode },
4074     { Bad_Opcode },
4075     { VEX_LEN_TABLE (VEX_LEN_DE_P_2) },
4076   },
4077
4078   /* PREFIX_VEX_DF */
4079   {
4080     { Bad_Opcode },
4081     { Bad_Opcode },
4082     { VEX_LEN_TABLE (VEX_LEN_DF_P_2) },
4083   },
4084
4085   /* PREFIX_VEX_E0 */
4086   {
4087     { Bad_Opcode },
4088     { Bad_Opcode },
4089     { VEX_LEN_TABLE (VEX_LEN_E0_P_2) },
4090   },
4091
4092   /* PREFIX_VEX_E1 */
4093   {
4094     { Bad_Opcode },
4095     { Bad_Opcode },
4096     { VEX_LEN_TABLE (VEX_LEN_E1_P_2) },
4097   },
4098
4099   /* PREFIX_VEX_E2 */
4100   {
4101     { Bad_Opcode },
4102     { Bad_Opcode },
4103     { VEX_LEN_TABLE (VEX_LEN_E2_P_2) },
4104   },
4105
4106   /* PREFIX_VEX_E3 */
4107   {
4108     { Bad_Opcode },
4109     { Bad_Opcode },
4110     { VEX_LEN_TABLE (VEX_LEN_E3_P_2) },
4111   },
4112
4113   /* PREFIX_VEX_E4 */
4114   {
4115     { Bad_Opcode },
4116     { Bad_Opcode },
4117     { VEX_LEN_TABLE (VEX_LEN_E4_P_2) },
4118   },
4119
4120   /* PREFIX_VEX_E5 */
4121   {
4122     { Bad_Opcode },
4123     { Bad_Opcode },
4124     { VEX_LEN_TABLE (VEX_LEN_E5_P_2) },
4125   },
4126
4127   /* PREFIX_VEX_E6 */
4128   {
4129     { Bad_Opcode },
4130     { VEX_W_TABLE (VEX_W_E6_P_1) },
4131     { VEX_W_TABLE (VEX_W_E6_P_2) },
4132     { VEX_W_TABLE (VEX_W_E6_P_3) },
4133   },
4134
4135   /* PREFIX_VEX_E7 */
4136   {
4137     { Bad_Opcode },
4138     { Bad_Opcode },
4139     { MOD_TABLE (MOD_VEX_E7_PREFIX_2) },
4140   },
4141
4142   /* PREFIX_VEX_E8 */
4143   {
4144     { Bad_Opcode },
4145     { Bad_Opcode },
4146     { VEX_LEN_TABLE (VEX_LEN_E8_P_2) },
4147   },
4148
4149   /* PREFIX_VEX_E9 */
4150   {
4151     { Bad_Opcode },
4152     { Bad_Opcode },
4153     { VEX_LEN_TABLE (VEX_LEN_E9_P_2) },
4154   },
4155
4156   /* PREFIX_VEX_EA */
4157   {
4158     { Bad_Opcode },
4159     { Bad_Opcode },
4160     { VEX_LEN_TABLE (VEX_LEN_EA_P_2) },
4161   },
4162
4163   /* PREFIX_VEX_EB */
4164   {
4165     { Bad_Opcode },
4166     { Bad_Opcode },
4167     { VEX_LEN_TABLE (VEX_LEN_EB_P_2) },
4168   },
4169
4170   /* PREFIX_VEX_EC */
4171   {
4172     { Bad_Opcode },
4173     { Bad_Opcode },
4174     { VEX_LEN_TABLE (VEX_LEN_EC_P_2) },
4175   },
4176
4177   /* PREFIX_VEX_ED */
4178   {
4179     { Bad_Opcode },
4180     { Bad_Opcode },
4181     { VEX_LEN_TABLE (VEX_LEN_ED_P_2) },
4182   },
4183
4184   /* PREFIX_VEX_EE */
4185   {
4186     { Bad_Opcode },
4187     { Bad_Opcode },
4188     { VEX_LEN_TABLE (VEX_LEN_EE_P_2) },
4189   },
4190
4191   /* PREFIX_VEX_EF */
4192   {
4193     { Bad_Opcode },
4194     { Bad_Opcode },
4195     { VEX_LEN_TABLE (VEX_LEN_EF_P_2) },
4196   },
4197
4198   /* PREFIX_VEX_F0 */
4199   {
4200     { Bad_Opcode },
4201     { Bad_Opcode },
4202     { Bad_Opcode },
4203     { MOD_TABLE (MOD_VEX_F0_PREFIX_3) },
4204   },
4205
4206   /* PREFIX_VEX_F1 */
4207   {
4208     { Bad_Opcode },
4209     { Bad_Opcode },
4210     { VEX_LEN_TABLE (VEX_LEN_F1_P_2) },
4211   },
4212
4213   /* PREFIX_VEX_F2 */
4214   {
4215     { Bad_Opcode },
4216     { Bad_Opcode },
4217     { VEX_LEN_TABLE (VEX_LEN_F2_P_2) },
4218   },
4219
4220   /* PREFIX_VEX_F3 */
4221   {
4222     { Bad_Opcode },
4223     { Bad_Opcode },
4224     { VEX_LEN_TABLE (VEX_LEN_F3_P_2) },
4225   },
4226
4227   /* PREFIX_VEX_F4 */
4228   {
4229     { Bad_Opcode },
4230     { Bad_Opcode },
4231     { VEX_LEN_TABLE (VEX_LEN_F4_P_2) },
4232   },
4233
4234   /* PREFIX_VEX_F5 */
4235   {
4236     { Bad_Opcode },
4237     { Bad_Opcode },
4238     { VEX_LEN_TABLE (VEX_LEN_F5_P_2) },
4239   },
4240
4241   /* PREFIX_VEX_F6 */
4242   {
4243     { Bad_Opcode },
4244     { Bad_Opcode },
4245     { VEX_LEN_TABLE (VEX_LEN_F6_P_2) },
4246   },
4247
4248   /* PREFIX_VEX_F7 */
4249   {
4250     { Bad_Opcode },
4251     { Bad_Opcode },
4252     { VEX_LEN_TABLE (VEX_LEN_F7_P_2) },
4253   },
4254
4255   /* PREFIX_VEX_F8 */
4256   {
4257     { Bad_Opcode },
4258     { Bad_Opcode },
4259     { VEX_LEN_TABLE (VEX_LEN_F8_P_2) },
4260   },
4261
4262   /* PREFIX_VEX_F9 */
4263   {
4264     { Bad_Opcode },
4265     { Bad_Opcode },
4266     { VEX_LEN_TABLE (VEX_LEN_F9_P_2) },
4267   },
4268
4269   /* PREFIX_VEX_FA */
4270   {
4271     { Bad_Opcode },
4272     { Bad_Opcode },
4273     { VEX_LEN_TABLE (VEX_LEN_FA_P_2) },
4274   },
4275
4276   /* PREFIX_VEX_FB */
4277   {
4278     { Bad_Opcode },
4279     { Bad_Opcode },
4280     { VEX_LEN_TABLE (VEX_LEN_FB_P_2) },
4281   },
4282
4283   /* PREFIX_VEX_FC */
4284   {
4285     { Bad_Opcode },
4286     { Bad_Opcode },
4287     { VEX_LEN_TABLE (VEX_LEN_FC_P_2) },
4288   },
4289
4290   /* PREFIX_VEX_FD */
4291   {
4292     { Bad_Opcode },
4293     { Bad_Opcode },
4294     { VEX_LEN_TABLE (VEX_LEN_FD_P_2) },
4295   },
4296
4297   /* PREFIX_VEX_FE */
4298   {
4299     { Bad_Opcode },
4300     { Bad_Opcode },
4301     { VEX_LEN_TABLE (VEX_LEN_FE_P_2) },
4302   },
4303
4304   /* PREFIX_VEX_3800 */
4305   {
4306     { Bad_Opcode },
4307     { Bad_Opcode },
4308     { VEX_LEN_TABLE (VEX_LEN_3800_P_2) },
4309   },
4310
4311   /* PREFIX_VEX_3801 */
4312   {
4313     { Bad_Opcode },
4314     { Bad_Opcode },
4315     { VEX_LEN_TABLE (VEX_LEN_3801_P_2) },
4316   },
4317
4318   /* PREFIX_VEX_3802 */
4319   {
4320     { Bad_Opcode },
4321     { Bad_Opcode },
4322     { VEX_LEN_TABLE (VEX_LEN_3802_P_2) },
4323   },
4324
4325   /* PREFIX_VEX_3803 */
4326   {
4327     { Bad_Opcode },
4328     { Bad_Opcode },
4329     { VEX_LEN_TABLE (VEX_LEN_3803_P_2) },
4330   },
4331
4332   /* PREFIX_VEX_3804 */
4333   {
4334     { Bad_Opcode },
4335     { Bad_Opcode },
4336     { VEX_LEN_TABLE (VEX_LEN_3804_P_2) },
4337   },
4338
4339   /* PREFIX_VEX_3805 */
4340   {
4341     { Bad_Opcode },
4342     { Bad_Opcode },
4343     { VEX_LEN_TABLE (VEX_LEN_3805_P_2) },
4344   },
4345
4346   /* PREFIX_VEX_3806 */
4347   {
4348     { Bad_Opcode },
4349     { Bad_Opcode },
4350     { VEX_LEN_TABLE (VEX_LEN_3806_P_2) },
4351   },
4352
4353   /* PREFIX_VEX_3807 */
4354   {
4355     { Bad_Opcode },
4356     { Bad_Opcode },
4357     { VEX_LEN_TABLE (VEX_LEN_3807_P_2) },
4358   },
4359
4360   /* PREFIX_VEX_3808 */
4361   {
4362     { Bad_Opcode },
4363     { Bad_Opcode },
4364     { VEX_LEN_TABLE (VEX_LEN_3808_P_2) },
4365   },
4366
4367   /* PREFIX_VEX_3809 */
4368   {
4369     { Bad_Opcode },
4370     { Bad_Opcode },
4371     { VEX_LEN_TABLE (VEX_LEN_3809_P_2) },
4372   },
4373
4374   /* PREFIX_VEX_380A */
4375   {
4376     { Bad_Opcode },
4377     { Bad_Opcode },
4378     { VEX_LEN_TABLE (VEX_LEN_380A_P_2) },
4379   },
4380
4381   /* PREFIX_VEX_380B */
4382   {
4383     { Bad_Opcode },
4384     { Bad_Opcode },
4385     { VEX_LEN_TABLE (VEX_LEN_380B_P_2) },
4386   },
4387
4388   /* PREFIX_VEX_380C */
4389   {
4390     { Bad_Opcode },
4391     { Bad_Opcode },
4392     { VEX_W_TABLE (VEX_W_380C_P_2) },
4393   },
4394
4395   /* PREFIX_VEX_380D */
4396   {
4397     { Bad_Opcode },
4398     { Bad_Opcode },
4399     { VEX_W_TABLE (VEX_W_380D_P_2) },
4400   },
4401
4402   /* PREFIX_VEX_380E */
4403   {
4404     { Bad_Opcode },
4405     { Bad_Opcode },
4406     { VEX_W_TABLE (VEX_W_380E_P_2) },
4407   },
4408
4409   /* PREFIX_VEX_380F */
4410   {
4411     { Bad_Opcode },
4412     { Bad_Opcode },
4413     { VEX_W_TABLE (VEX_W_380F_P_2) },
4414   },
4415
4416   /* PREFIX_VEX_3817 */
4417   {
4418     { Bad_Opcode },
4419     { Bad_Opcode },
4420     { VEX_W_TABLE (VEX_W_3817_P_2) },
4421   },
4422
4423   /* PREFIX_VEX_3818 */
4424   {
4425     { Bad_Opcode },
4426     { Bad_Opcode },
4427     { MOD_TABLE (MOD_VEX_3818_PREFIX_2) },
4428   },
4429
4430   /* PREFIX_VEX_3819 */
4431   {
4432     { Bad_Opcode },
4433     { Bad_Opcode },
4434     { MOD_TABLE (MOD_VEX_3819_PREFIX_2) },
4435   },
4436
4437   /* PREFIX_VEX_381A */
4438   {
4439     { Bad_Opcode },
4440     { Bad_Opcode },
4441     { MOD_TABLE (MOD_VEX_381A_PREFIX_2) },
4442   },
4443
4444   /* PREFIX_VEX_381C */
4445   {
4446     { Bad_Opcode },
4447     { Bad_Opcode },
4448     { VEX_LEN_TABLE (VEX_LEN_381C_P_2) },
4449   },
4450
4451   /* PREFIX_VEX_381D */
4452   {
4453     { Bad_Opcode },
4454     { Bad_Opcode },
4455     { VEX_LEN_TABLE (VEX_LEN_381D_P_2) },
4456   },
4457
4458   /* PREFIX_VEX_381E */
4459   {
4460     { Bad_Opcode },
4461     { Bad_Opcode },
4462     { VEX_LEN_TABLE (VEX_LEN_381E_P_2) },
4463   },
4464
4465   /* PREFIX_VEX_3820 */
4466   {
4467     { Bad_Opcode },
4468     { Bad_Opcode },
4469     { VEX_LEN_TABLE (VEX_LEN_3820_P_2) },
4470   },
4471
4472   /* PREFIX_VEX_3821 */
4473   {
4474     { Bad_Opcode },
4475     { Bad_Opcode },
4476     { VEX_LEN_TABLE (VEX_LEN_3821_P_2) },
4477   },
4478
4479   /* PREFIX_VEX_3822 */
4480   {
4481     { Bad_Opcode },
4482     { Bad_Opcode },
4483     { VEX_LEN_TABLE (VEX_LEN_3822_P_2) },
4484   },
4485
4486   /* PREFIX_VEX_3823 */
4487   {
4488     { Bad_Opcode },
4489     { Bad_Opcode },
4490     { VEX_LEN_TABLE (VEX_LEN_3823_P_2) },
4491   },
4492
4493   /* PREFIX_VEX_3824 */
4494   {
4495     { Bad_Opcode },
4496     { Bad_Opcode },
4497     { VEX_LEN_TABLE (VEX_LEN_3824_P_2) },
4498   },
4499
4500   /* PREFIX_VEX_3825 */
4501   {
4502     { Bad_Opcode },
4503     { Bad_Opcode },
4504     { VEX_LEN_TABLE (VEX_LEN_3825_P_2) },
4505   },
4506
4507   /* PREFIX_VEX_3828 */
4508   {
4509     { Bad_Opcode },
4510     { Bad_Opcode },
4511     { VEX_LEN_TABLE (VEX_LEN_3828_P_2) },
4512   },
4513
4514   /* PREFIX_VEX_3829 */
4515   {
4516     { Bad_Opcode },
4517     { Bad_Opcode },
4518     { VEX_LEN_TABLE (VEX_LEN_3829_P_2) },
4519   },
4520
4521   /* PREFIX_VEX_382A */
4522   {
4523     { Bad_Opcode },
4524     { Bad_Opcode },
4525     { MOD_TABLE (MOD_VEX_382A_PREFIX_2) },
4526   },
4527
4528   /* PREFIX_VEX_382B */
4529   {
4530     { Bad_Opcode },
4531     { Bad_Opcode },
4532     { VEX_LEN_TABLE (VEX_LEN_382B_P_2) },
4533   },
4534
4535   /* PREFIX_VEX_382C */
4536   {
4537     { Bad_Opcode },
4538     { Bad_Opcode },
4539      { MOD_TABLE (MOD_VEX_382C_PREFIX_2) },
4540   },
4541
4542   /* PREFIX_VEX_382D */
4543   {
4544     { Bad_Opcode },
4545     { Bad_Opcode },
4546      { MOD_TABLE (MOD_VEX_382D_PREFIX_2) },
4547   },
4548
4549   /* PREFIX_VEX_382E */
4550   {
4551     { Bad_Opcode },
4552     { Bad_Opcode },
4553      { MOD_TABLE (MOD_VEX_382E_PREFIX_2) },
4554   },
4555
4556   /* PREFIX_VEX_382F */
4557   {
4558     { Bad_Opcode },
4559     { Bad_Opcode },
4560      { MOD_TABLE (MOD_VEX_382F_PREFIX_2) },
4561   },
4562
4563   /* PREFIX_VEX_3830 */
4564   {
4565     { Bad_Opcode },
4566     { Bad_Opcode },
4567     { VEX_LEN_TABLE (VEX_LEN_3830_P_2) },
4568   },
4569
4570   /* PREFIX_VEX_3831 */
4571   {
4572     { Bad_Opcode },
4573     { Bad_Opcode },
4574     { VEX_LEN_TABLE (VEX_LEN_3831_P_2) },
4575   },
4576
4577   /* PREFIX_VEX_3832 */
4578   {
4579     { Bad_Opcode },
4580     { Bad_Opcode },
4581     { VEX_LEN_TABLE (VEX_LEN_3832_P_2) },
4582   },
4583
4584   /* PREFIX_VEX_3833 */
4585   {
4586     { Bad_Opcode },
4587     { Bad_Opcode },
4588     { VEX_LEN_TABLE (VEX_LEN_3833_P_2) },
4589   },
4590
4591   /* PREFIX_VEX_3834 */
4592   {
4593     { Bad_Opcode },
4594     { Bad_Opcode },
4595     { VEX_LEN_TABLE (VEX_LEN_3834_P_2) },
4596   },
4597
4598   /* PREFIX_VEX_3835 */
4599   {
4600     { Bad_Opcode },
4601     { Bad_Opcode },
4602     { VEX_LEN_TABLE (VEX_LEN_3835_P_2) },
4603   },
4604
4605   /* PREFIX_VEX_3837 */
4606   {
4607     { Bad_Opcode },
4608     { Bad_Opcode },
4609     { VEX_LEN_TABLE (VEX_LEN_3837_P_2) },
4610   },
4611
4612   /* PREFIX_VEX_3838 */
4613   {
4614     { Bad_Opcode },
4615     { Bad_Opcode },
4616     { VEX_LEN_TABLE (VEX_LEN_3838_P_2) },
4617   },
4618
4619   /* PREFIX_VEX_3839 */
4620   {
4621     { Bad_Opcode },
4622     { Bad_Opcode },
4623     { VEX_LEN_TABLE (VEX_LEN_3839_P_2) },
4624   },
4625
4626   /* PREFIX_VEX_383A */
4627   {
4628     { Bad_Opcode },
4629     { Bad_Opcode },
4630     { VEX_LEN_TABLE (VEX_LEN_383A_P_2) },
4631   },
4632
4633   /* PREFIX_VEX_383B */
4634   {
4635     { Bad_Opcode },
4636     { Bad_Opcode },
4637     { VEX_LEN_TABLE (VEX_LEN_383B_P_2) },
4638   },
4639
4640   /* PREFIX_VEX_383C */
4641   {
4642     { Bad_Opcode },
4643     { Bad_Opcode },
4644     { VEX_LEN_TABLE (VEX_LEN_383C_P_2) },
4645   },
4646
4647   /* PREFIX_VEX_383D */
4648   {
4649     { Bad_Opcode },
4650     { Bad_Opcode },
4651     { VEX_LEN_TABLE (VEX_LEN_383D_P_2) },
4652   },
4653
4654   /* PREFIX_VEX_383E */
4655   {
4656     { Bad_Opcode },
4657     { Bad_Opcode },
4658     { VEX_LEN_TABLE (VEX_LEN_383E_P_2) },
4659   },
4660
4661   /* PREFIX_VEX_383F */
4662   {
4663     { Bad_Opcode },
4664     { Bad_Opcode },
4665     { VEX_LEN_TABLE (VEX_LEN_383F_P_2) },
4666   },
4667
4668   /* PREFIX_VEX_3840 */
4669   {
4670     { Bad_Opcode },
4671     { Bad_Opcode },
4672     { VEX_LEN_TABLE (VEX_LEN_3840_P_2) },
4673   },
4674
4675   /* PREFIX_VEX_3841 */
4676   {
4677     { Bad_Opcode },
4678     { Bad_Opcode },
4679     { VEX_LEN_TABLE (VEX_LEN_3841_P_2) },
4680   },
4681
4682   /* PREFIX_VEX_3896 */
4683   {
4684     { Bad_Opcode },
4685     { Bad_Opcode },
4686     { "vfmaddsub132p%XW", { XM, Vex, EXx } },
4687   },
4688
4689   /* PREFIX_VEX_3897 */
4690   {
4691     { Bad_Opcode },
4692     { Bad_Opcode },
4693     { "vfmsubadd132p%XW", { XM, Vex, EXx } },
4694   },
4695
4696   /* PREFIX_VEX_3898 */
4697   {
4698     { Bad_Opcode },
4699     { Bad_Opcode },
4700     { "vfmadd132p%XW", { XM, Vex, EXx } },
4701   },
4702
4703   /* PREFIX_VEX_3899 */
4704   {
4705     { Bad_Opcode },
4706     { Bad_Opcode },
4707     { "vfmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
4708   },
4709
4710   /* PREFIX_VEX_389A */
4711   {
4712     { Bad_Opcode },
4713     { Bad_Opcode },
4714     { "vfmsub132p%XW", { XM, Vex, EXx } },
4715   },
4716
4717   /* PREFIX_VEX_389B */
4718   {
4719     { Bad_Opcode },
4720     { Bad_Opcode },
4721     { "vfmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
4722   },
4723
4724   /* PREFIX_VEX_389C */
4725   {
4726     { Bad_Opcode },
4727     { Bad_Opcode },
4728     { "vfnmadd132p%XW", { XM, Vex, EXx } },
4729   },
4730
4731   /* PREFIX_VEX_389D */
4732   {
4733     { Bad_Opcode },
4734     { Bad_Opcode },
4735     { "vfnmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
4736   },
4737
4738   /* PREFIX_VEX_389E */
4739   {
4740     { Bad_Opcode },
4741     { Bad_Opcode },
4742     { "vfnmsub132p%XW", { XM, Vex, EXx } },
4743   },
4744
4745   /* PREFIX_VEX_389F */
4746   {
4747     { Bad_Opcode },
4748     { Bad_Opcode },
4749     { "vfnmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
4750   },
4751
4752   /* PREFIX_VEX_38A6 */
4753   {
4754     { Bad_Opcode },
4755     { Bad_Opcode },
4756     { "vfmaddsub213p%XW", { XM, Vex, EXx } },
4757     { Bad_Opcode },
4758   },
4759
4760   /* PREFIX_VEX_38A7 */
4761   {
4762     { Bad_Opcode },
4763     { Bad_Opcode },
4764     { "vfmsubadd213p%XW", { XM, Vex, EXx } },
4765   },
4766
4767   /* PREFIX_VEX_38A8 */
4768   {
4769     { Bad_Opcode },
4770     { Bad_Opcode },
4771     { "vfmadd213p%XW", { XM, Vex, EXx } },
4772   },
4773
4774   /* PREFIX_VEX_38A9 */
4775   {
4776     { Bad_Opcode },
4777     { Bad_Opcode },
4778     { "vfmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
4779   },
4780
4781   /* PREFIX_VEX_38AA */
4782   {
4783     { Bad_Opcode },
4784     { Bad_Opcode },
4785     { "vfmsub213p%XW", { XM, Vex, EXx } },
4786   },
4787
4788   /* PREFIX_VEX_38AB */
4789   {
4790     { Bad_Opcode },
4791     { Bad_Opcode },
4792     { "vfmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
4793   },
4794
4795   /* PREFIX_VEX_38AC */
4796   {
4797     { Bad_Opcode },
4798     { Bad_Opcode },
4799     { "vfnmadd213p%XW", { XM, Vex, EXx } },
4800   },
4801
4802   /* PREFIX_VEX_38AD */
4803   {
4804     { Bad_Opcode },
4805     { Bad_Opcode },
4806     { "vfnmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
4807   },
4808
4809   /* PREFIX_VEX_38AE */
4810   {
4811     { Bad_Opcode },
4812     { Bad_Opcode },
4813     { "vfnmsub213p%XW", { XM, Vex, EXx } },
4814   },
4815
4816   /* PREFIX_VEX_38AF */
4817   {
4818     { Bad_Opcode },
4819     { Bad_Opcode },
4820     { "vfnmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
4821   },
4822
4823   /* PREFIX_VEX_38B6 */
4824   {
4825     { Bad_Opcode },
4826     { Bad_Opcode },
4827     { "vfmaddsub231p%XW", { XM, Vex, EXx } },
4828   },
4829
4830   /* PREFIX_VEX_38B7 */
4831   {
4832     { Bad_Opcode },
4833     { Bad_Opcode },
4834     { "vfmsubadd231p%XW", { XM, Vex, EXx } },
4835   },
4836
4837   /* PREFIX_VEX_38B8 */
4838   {
4839     { Bad_Opcode },
4840     { Bad_Opcode },
4841     { "vfmadd231p%XW", { XM, Vex, EXx } },
4842   },
4843
4844   /* PREFIX_VEX_38B9 */
4845   {
4846     { Bad_Opcode },
4847     { Bad_Opcode },
4848     { "vfmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
4849   },
4850
4851   /* PREFIX_VEX_38BA */
4852   {
4853     { Bad_Opcode },
4854     { Bad_Opcode },
4855     { "vfmsub231p%XW", { XM, Vex, EXx } },
4856   },
4857
4858   /* PREFIX_VEX_38BB */
4859   {
4860     { Bad_Opcode },
4861     { Bad_Opcode },
4862     { "vfmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
4863   },
4864
4865   /* PREFIX_VEX_38BC */
4866   {
4867     { Bad_Opcode },
4868     { Bad_Opcode },
4869     { "vfnmadd231p%XW", { XM, Vex, EXx } },
4870   },
4871
4872   /* PREFIX_VEX_38BD */
4873   {
4874     { Bad_Opcode },
4875     { Bad_Opcode },
4876     { "vfnmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
4877   },
4878
4879   /* PREFIX_VEX_38BE */
4880   {
4881     { Bad_Opcode },
4882     { Bad_Opcode },
4883     { "vfnmsub231p%XW", { XM, Vex, EXx } },
4884   },
4885
4886   /* PREFIX_VEX_38BF */
4887   {
4888     { Bad_Opcode },
4889     { Bad_Opcode },
4890     { "vfnmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
4891   },
4892
4893   /* PREFIX_VEX_38DB */
4894   {
4895     { Bad_Opcode },
4896     { Bad_Opcode },
4897     { VEX_LEN_TABLE (VEX_LEN_38DB_P_2) },
4898   },
4899
4900   /* PREFIX_VEX_38DC */
4901   {
4902     { Bad_Opcode },
4903     { Bad_Opcode },
4904     { VEX_LEN_TABLE (VEX_LEN_38DC_P_2) },
4905   },
4906
4907   /* PREFIX_VEX_38DD */
4908   {
4909     { Bad_Opcode },
4910     { Bad_Opcode },
4911     { VEX_LEN_TABLE (VEX_LEN_38DD_P_2) },
4912   },
4913
4914   /* PREFIX_VEX_38DE */
4915   {
4916     { Bad_Opcode },
4917     { Bad_Opcode },
4918     { VEX_LEN_TABLE (VEX_LEN_38DE_P_2) },
4919   },
4920
4921   /* PREFIX_VEX_38DF */
4922   {
4923     { Bad_Opcode },
4924     { Bad_Opcode },
4925     { VEX_LEN_TABLE (VEX_LEN_38DF_P_2) },
4926   },
4927
4928   /* PREFIX_VEX_3A04 */
4929   {
4930     { Bad_Opcode },
4931     { Bad_Opcode },
4932     { VEX_W_TABLE (VEX_W_3A04_P_2) },
4933   },
4934
4935   /* PREFIX_VEX_3A05 */
4936   {
4937     { Bad_Opcode },
4938     { Bad_Opcode },
4939     { VEX_W_TABLE (VEX_W_3A05_P_2) },
4940   },
4941
4942   /* PREFIX_VEX_3A06 */
4943   {
4944     { Bad_Opcode },
4945     { Bad_Opcode },
4946     { VEX_LEN_TABLE (VEX_LEN_3A06_P_2) },
4947   },
4948
4949   /* PREFIX_VEX_3A08 */
4950   {
4951     { Bad_Opcode },
4952     { Bad_Opcode },
4953     { VEX_W_TABLE (VEX_W_3A08_P_2) },
4954   },
4955
4956   /* PREFIX_VEX_3A09 */
4957   {
4958     { Bad_Opcode },
4959     { Bad_Opcode },
4960     { VEX_W_TABLE (VEX_W_3A09_P_2) },
4961   },
4962
4963   /* PREFIX_VEX_3A0A */
4964   {
4965     { Bad_Opcode },
4966     { Bad_Opcode },
4967     { VEX_LEN_TABLE (VEX_LEN_3A0A_P_2) },
4968   },
4969
4970   /* PREFIX_VEX_3A0B */
4971   {
4972     { Bad_Opcode },
4973     { Bad_Opcode },
4974     { VEX_LEN_TABLE (VEX_LEN_3A0B_P_2) },
4975   },
4976
4977   /* PREFIX_VEX_3A0C */
4978   {
4979     { Bad_Opcode },
4980     { Bad_Opcode },
4981     { VEX_W_TABLE (VEX_W_3A0C_P_2) },
4982   },
4983
4984   /* PREFIX_VEX_3A0D */
4985   {
4986     { Bad_Opcode },
4987     { Bad_Opcode },
4988     { VEX_W_TABLE (VEX_W_3A0D_P_2) },
4989   },
4990
4991   /* PREFIX_VEX_3A0E */
4992   {
4993     { Bad_Opcode },
4994     { Bad_Opcode },
4995     { VEX_LEN_TABLE (VEX_LEN_3A0E_P_2) },
4996   },
4997
4998   /* PREFIX_VEX_3A0F */
4999   {
5000     { Bad_Opcode },
5001     { Bad_Opcode },
5002     { VEX_LEN_TABLE (VEX_LEN_3A0F_P_2) },
5003   },
5004
5005   /* PREFIX_VEX_3A14 */
5006   {
5007     { Bad_Opcode },
5008     { Bad_Opcode },
5009     { VEX_LEN_TABLE (VEX_LEN_3A14_P_2) },
5010   },
5011
5012   /* PREFIX_VEX_3A15 */
5013   {
5014     { Bad_Opcode },
5015     { Bad_Opcode },
5016     { VEX_LEN_TABLE (VEX_LEN_3A15_P_2) },
5017   },
5018
5019   /* PREFIX_VEX_3A16 */
5020   {
5021     { Bad_Opcode },
5022     { Bad_Opcode },
5023     { VEX_LEN_TABLE (VEX_LEN_3A16_P_2) },
5024   },
5025
5026   /* PREFIX_VEX_3A17 */
5027   {
5028     { Bad_Opcode },
5029     { Bad_Opcode },
5030     { VEX_LEN_TABLE (VEX_LEN_3A17_P_2) },
5031   },
5032
5033   /* PREFIX_VEX_3A18 */
5034   {
5035     { Bad_Opcode },
5036     { Bad_Opcode },
5037     { VEX_LEN_TABLE (VEX_LEN_3A18_P_2) },
5038   },
5039
5040   /* PREFIX_VEX_3A19 */
5041   {
5042     { Bad_Opcode },
5043     { Bad_Opcode },
5044     { VEX_LEN_TABLE (VEX_LEN_3A19_P_2) },
5045   },
5046
5047   /* PREFIX_VEX_3A20 */
5048   {
5049     { Bad_Opcode },
5050     { Bad_Opcode },
5051     { VEX_LEN_TABLE (VEX_LEN_3A20_P_2) },
5052   },
5053
5054   /* PREFIX_VEX_3A21 */
5055   {
5056     { Bad_Opcode },
5057     { Bad_Opcode },
5058     { VEX_LEN_TABLE (VEX_LEN_3A21_P_2) },
5059   },
5060
5061   /* PREFIX_VEX_3A22 */
5062   {
5063     { Bad_Opcode },
5064     { Bad_Opcode },
5065     { VEX_LEN_TABLE (VEX_LEN_3A22_P_2) },
5066   },
5067
5068   /* PREFIX_VEX_3A40 */
5069   {
5070     { Bad_Opcode },
5071     { Bad_Opcode },
5072     { VEX_W_TABLE (VEX_W_3A40_P_2) },
5073   },
5074
5075   /* PREFIX_VEX_3A41 */
5076   {
5077     { Bad_Opcode },
5078     { Bad_Opcode },
5079     { VEX_LEN_TABLE (VEX_LEN_3A41_P_2) },
5080   },
5081
5082   /* PREFIX_VEX_3A42 */
5083   {
5084     { Bad_Opcode },
5085     { Bad_Opcode },
5086     { VEX_LEN_TABLE (VEX_LEN_3A42_P_2) },
5087   },
5088
5089   /* PREFIX_VEX_3A44 */
5090   {
5091     { Bad_Opcode },
5092     { Bad_Opcode },
5093     { VEX_LEN_TABLE (VEX_LEN_3A44_P_2) },
5094   },
5095
5096   /* PREFIX_VEX_3A48 */
5097   {
5098     { Bad_Opcode },
5099     { Bad_Opcode },
5100     { VEX_W_TABLE (VEX_W_3A48_P_2) },
5101   },
5102
5103   /* PREFIX_VEX_3A49 */
5104   {
5105     { Bad_Opcode },
5106     { Bad_Opcode },
5107     { VEX_W_TABLE (VEX_W_3A49_P_2) },
5108   },
5109
5110   /* PREFIX_VEX_3A4A */
5111   {
5112     { Bad_Opcode },
5113     { Bad_Opcode },
5114     { VEX_W_TABLE (VEX_W_3A4A_P_2) },
5115   },
5116
5117   /* PREFIX_VEX_3A4B */
5118   {
5119     { Bad_Opcode },
5120     { Bad_Opcode },
5121     { VEX_W_TABLE (VEX_W_3A4B_P_2) },
5122   },
5123
5124   /* PREFIX_VEX_3A4C */
5125   {
5126     { Bad_Opcode },
5127     { Bad_Opcode },
5128     { VEX_LEN_TABLE (VEX_LEN_3A4C_P_2) },
5129   },
5130
5131   /* PREFIX_VEX_3A5C */
5132   {
5133     { Bad_Opcode },
5134     { Bad_Opcode },
5135     { "vfmaddsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5136   },
5137
5138   /* PREFIX_VEX_3A5D */
5139   {
5140     { Bad_Opcode },
5141     { Bad_Opcode },
5142     { "vfmaddsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5143   },
5144
5145   /* PREFIX_VEX_3A5E */
5146   {
5147     { Bad_Opcode },
5148     { Bad_Opcode },
5149     { "vfmsubaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5150   },
5151
5152   /* PREFIX_VEX_3A5F */
5153   {
5154     { Bad_Opcode },
5155     { Bad_Opcode },
5156     { "vfmsubaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5157   },
5158
5159   /* PREFIX_VEX_3A60 */
5160   {
5161     { Bad_Opcode },
5162     { Bad_Opcode },
5163     { VEX_LEN_TABLE (VEX_LEN_3A60_P_2) },
5164     { Bad_Opcode },
5165   },
5166
5167   /* PREFIX_VEX_3A61 */
5168   {
5169     { Bad_Opcode },
5170     { Bad_Opcode },
5171     { VEX_LEN_TABLE (VEX_LEN_3A61_P_2) },
5172   },
5173
5174   /* PREFIX_VEX_3A62 */
5175   {
5176     { Bad_Opcode },
5177     { Bad_Opcode },
5178     { VEX_LEN_TABLE (VEX_LEN_3A62_P_2) },
5179   },
5180
5181   /* PREFIX_VEX_3A63 */
5182   {
5183     { Bad_Opcode },
5184     { Bad_Opcode },
5185     { VEX_LEN_TABLE (VEX_LEN_3A63_P_2) },
5186   },
5187
5188   /* PREFIX_VEX_3A68 */
5189   {
5190     { Bad_Opcode },
5191     { Bad_Opcode },
5192     { "vfmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5193   },
5194
5195   /* PREFIX_VEX_3A69 */
5196   {
5197     { Bad_Opcode },
5198     { Bad_Opcode },
5199     { "vfmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5200   },
5201
5202   /* PREFIX_VEX_3A6A */
5203   {
5204     { Bad_Opcode },
5205     { Bad_Opcode },
5206     { VEX_LEN_TABLE (VEX_LEN_3A6A_P_2) },
5207   },
5208
5209   /* PREFIX_VEX_3A6B */
5210   {
5211     { Bad_Opcode },
5212     { Bad_Opcode },
5213     { VEX_LEN_TABLE (VEX_LEN_3A6B_P_2) },
5214   },
5215
5216   /* PREFIX_VEX_3A6C */
5217   {
5218     { Bad_Opcode },
5219     { Bad_Opcode },
5220     { "vfmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5221   },
5222
5223   /* PREFIX_VEX_3A6D */
5224   {
5225     { Bad_Opcode },
5226     { Bad_Opcode },
5227     { "vfmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5228   },
5229
5230   /* PREFIX_VEX_3A6E */
5231   {
5232     { Bad_Opcode },
5233     { Bad_Opcode },
5234     { VEX_LEN_TABLE (VEX_LEN_3A6E_P_2) },
5235   },
5236
5237   /* PREFIX_VEX_3A6F */
5238   {
5239     { Bad_Opcode },
5240     { Bad_Opcode },
5241     { VEX_LEN_TABLE (VEX_LEN_3A6F_P_2) },
5242   },
5243
5244   /* PREFIX_VEX_3A78 */
5245   {
5246     { Bad_Opcode },
5247     { Bad_Opcode },
5248     { "vfnmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5249   },
5250
5251   /* PREFIX_VEX_3A79 */
5252   {
5253     { Bad_Opcode },
5254     { Bad_Opcode },
5255     { "vfnmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5256   },
5257
5258   /* PREFIX_VEX_3A7A */
5259   {
5260     { Bad_Opcode },
5261     { Bad_Opcode },
5262     { VEX_LEN_TABLE (VEX_LEN_3A7A_P_2) },
5263   },
5264
5265   /* PREFIX_VEX_3A7B */
5266   {
5267     { Bad_Opcode },
5268     { Bad_Opcode },
5269     { VEX_LEN_TABLE (VEX_LEN_3A7B_P_2) },
5270   },
5271
5272   /* PREFIX_VEX_3A7C */
5273   {
5274     { Bad_Opcode },
5275     { Bad_Opcode },
5276     { "vfnmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5277     { Bad_Opcode },
5278   },
5279
5280   /* PREFIX_VEX_3A7D */
5281   {
5282     { Bad_Opcode },
5283     { Bad_Opcode },
5284     { "vfnmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5285   },
5286
5287   /* PREFIX_VEX_3A7E */
5288   {
5289     { Bad_Opcode },
5290     { Bad_Opcode },
5291     { VEX_LEN_TABLE (VEX_LEN_3A7E_P_2) },
5292   },
5293
5294   /* PREFIX_VEX_3A7F */
5295   {
5296     { Bad_Opcode },
5297     { Bad_Opcode },
5298     { VEX_LEN_TABLE (VEX_LEN_3A7F_P_2) },
5299   },
5300
5301   /* PREFIX_VEX_3ADF */
5302   {
5303     { Bad_Opcode },
5304     { Bad_Opcode },
5305     { VEX_LEN_TABLE (VEX_LEN_3ADF_P_2) },
5306   },
5307 };
5308
5309 static const struct dis386 x86_64_table[][2] = {
5310   /* X86_64_06 */
5311   {
5312     { "push{T|}", { es } },
5313   },
5314
5315   /* X86_64_07 */
5316   {
5317     { "pop{T|}", { es } },
5318   },
5319
5320   /* X86_64_0D */
5321   {
5322     { "push{T|}", { cs } },
5323   },
5324
5325   /* X86_64_16 */
5326   {
5327     { "push{T|}", { ss } },
5328   },
5329
5330   /* X86_64_17 */
5331   {
5332     { "pop{T|}", { ss } },
5333   },
5334
5335   /* X86_64_1E */
5336   {
5337     { "push{T|}", { ds } },
5338   },
5339
5340   /* X86_64_1F */
5341   {
5342     { "pop{T|}", { ds } },
5343   },
5344
5345   /* X86_64_27 */
5346   {
5347     { "daa", { XX } },
5348   },
5349
5350   /* X86_64_2F */
5351   {
5352     { "das", { XX } },
5353   },
5354
5355   /* X86_64_37 */
5356   {
5357     { "aaa", { XX } },
5358   },
5359
5360   /* X86_64_3F */
5361   {
5362     { "aas", { XX } },
5363   },
5364
5365   /* X86_64_60 */
5366   {
5367     { "pusha{P|}", { XX } },
5368   },
5369
5370   /* X86_64_61 */
5371   {
5372     { "popa{P|}", { XX } },
5373   },
5374
5375   /* X86_64_62 */
5376   {
5377     { MOD_TABLE (MOD_62_32BIT) },
5378   },
5379
5380   /* X86_64_63 */
5381   {
5382     { "arpl", { Ew, Gw } },
5383     { "movs{lq|xd}", { Gv, Ed } },
5384   },
5385
5386   /* X86_64_6D */
5387   {
5388     { "ins{R|}", { Yzr, indirDX } },
5389     { "ins{G|}", { Yzr, indirDX } },
5390   },
5391
5392   /* X86_64_6F */
5393   {
5394     { "outs{R|}", { indirDXr, Xz } },
5395     { "outs{G|}", { indirDXr, Xz } },
5396   },
5397
5398   /* X86_64_9A */
5399   {
5400     { "Jcall{T|}", { Ap } },
5401   },
5402
5403   /* X86_64_C4 */
5404   {
5405     { MOD_TABLE (MOD_C4_32BIT) },
5406     { VEX_C4_TABLE (VEX_0F) },
5407   },
5408
5409   /* X86_64_C5 */
5410   {
5411     { MOD_TABLE (MOD_C5_32BIT) },
5412     { VEX_C5_TABLE (VEX_0F) },
5413   },
5414
5415   /* X86_64_CE */
5416   {
5417     { "into", { XX } },
5418   },
5419
5420   /* X86_64_D4 */
5421   {
5422     { "aam", { sIb } },
5423   },
5424
5425   /* X86_64_D5 */
5426   {
5427     { "aad", { sIb } },
5428   },
5429
5430   /* X86_64_EA */
5431   {
5432     { "Jjmp{T|}", { Ap } },
5433   },
5434
5435   /* X86_64_0F01_REG_0 */
5436   {
5437     { "sgdt{Q|IQ}", { M } },
5438     { "sgdt", { M } },
5439   },
5440
5441   /* X86_64_0F01_REG_1 */
5442   {
5443     { "sidt{Q|IQ}", { M } },
5444     { "sidt", { M } },
5445   },
5446
5447   /* X86_64_0F01_REG_2 */
5448   {
5449     { "lgdt{Q|Q}", { M } },
5450     { "lgdt", { M } },
5451   },
5452
5453   /* X86_64_0F01_REG_3 */
5454   {
5455     { "lidt{Q|Q}", { M } },
5456     { "lidt", { M } },
5457   },
5458 };
5459
5460 static const struct dis386 three_byte_table[][256] = {
5461
5462   /* THREE_BYTE_0F38 */
5463   {
5464     /* 00 */
5465     { "pshufb",         { MX, EM } },
5466     { "phaddw",         { MX, EM } },
5467     { "phaddd",         { MX, EM } },
5468     { "phaddsw",        { MX, EM } },
5469     { "pmaddubsw",      { MX, EM } },
5470     { "phsubw",         { MX, EM } },
5471     { "phsubd",         { MX, EM } },
5472     { "phsubsw",        { MX, EM } },
5473     /* 08 */
5474     { "psignb",         { MX, EM } },
5475     { "psignw",         { MX, EM } },
5476     { "psignd",         { MX, EM } },
5477     { "pmulhrsw",       { MX, EM } },
5478     { Bad_Opcode },
5479     { Bad_Opcode },
5480     { Bad_Opcode },
5481     { Bad_Opcode },
5482     /* 10 */
5483     { PREFIX_TABLE (PREFIX_0F3810) },
5484     { Bad_Opcode },
5485     { Bad_Opcode },
5486     { Bad_Opcode },
5487     { PREFIX_TABLE (PREFIX_0F3814) },
5488     { PREFIX_TABLE (PREFIX_0F3815) },
5489     { Bad_Opcode },
5490     { PREFIX_TABLE (PREFIX_0F3817) },
5491     /* 18 */
5492     { Bad_Opcode },
5493     { Bad_Opcode },
5494     { Bad_Opcode },
5495     { Bad_Opcode },
5496     { "pabsb",          { MX, EM } },
5497     { "pabsw",          { MX, EM } },
5498     { "pabsd",          { MX, EM } },
5499     { Bad_Opcode },
5500     /* 20 */
5501     { PREFIX_TABLE (PREFIX_0F3820) },
5502     { PREFIX_TABLE (PREFIX_0F3821) },
5503     { PREFIX_TABLE (PREFIX_0F3822) },
5504     { PREFIX_TABLE (PREFIX_0F3823) },
5505     { PREFIX_TABLE (PREFIX_0F3824) },
5506     { PREFIX_TABLE (PREFIX_0F3825) },
5507     { Bad_Opcode },
5508     { Bad_Opcode },
5509     /* 28 */
5510     { PREFIX_TABLE (PREFIX_0F3828) },
5511     { PREFIX_TABLE (PREFIX_0F3829) },
5512     { PREFIX_TABLE (PREFIX_0F382A) },
5513     { PREFIX_TABLE (PREFIX_0F382B) },
5514     { Bad_Opcode },
5515     { Bad_Opcode },
5516     { Bad_Opcode },
5517     { Bad_Opcode },
5518     /* 30 */
5519     { PREFIX_TABLE (PREFIX_0F3830) },
5520     { PREFIX_TABLE (PREFIX_0F3831) },
5521     { PREFIX_TABLE (PREFIX_0F3832) },
5522     { PREFIX_TABLE (PREFIX_0F3833) },
5523     { PREFIX_TABLE (PREFIX_0F3834) },
5524     { PREFIX_TABLE (PREFIX_0F3835) },
5525     { Bad_Opcode },
5526     { PREFIX_TABLE (PREFIX_0F3837) },
5527     /* 38 */
5528     { PREFIX_TABLE (PREFIX_0F3838) },
5529     { PREFIX_TABLE (PREFIX_0F3839) },
5530     { PREFIX_TABLE (PREFIX_0F383A) },
5531     { PREFIX_TABLE (PREFIX_0F383B) },
5532     { PREFIX_TABLE (PREFIX_0F383C) },
5533     { PREFIX_TABLE (PREFIX_0F383D) },
5534     { PREFIX_TABLE (PREFIX_0F383E) },
5535     { PREFIX_TABLE (PREFIX_0F383F) },
5536     /* 40 */
5537     { PREFIX_TABLE (PREFIX_0F3840) },
5538     { PREFIX_TABLE (PREFIX_0F3841) },
5539     { Bad_Opcode },
5540     { Bad_Opcode },
5541     { Bad_Opcode },
5542     { Bad_Opcode },
5543     { Bad_Opcode },
5544     { Bad_Opcode },
5545     /* 48 */
5546     { Bad_Opcode },
5547     { Bad_Opcode },
5548     { Bad_Opcode },
5549     { Bad_Opcode },
5550     { Bad_Opcode },
5551     { Bad_Opcode },
5552     { Bad_Opcode },
5553     { Bad_Opcode },
5554     /* 50 */
5555     { Bad_Opcode },
5556     { Bad_Opcode },
5557     { Bad_Opcode },
5558     { Bad_Opcode },
5559     { Bad_Opcode },
5560     { Bad_Opcode },
5561     { Bad_Opcode },
5562     { Bad_Opcode },
5563     /* 58 */
5564     { Bad_Opcode },
5565     { Bad_Opcode },
5566     { Bad_Opcode },
5567     { Bad_Opcode },
5568     { Bad_Opcode },
5569     { Bad_Opcode },
5570     { Bad_Opcode },
5571     { Bad_Opcode },
5572     /* 60 */
5573     { Bad_Opcode },
5574     { Bad_Opcode },
5575     { Bad_Opcode },
5576     { Bad_Opcode },
5577     { Bad_Opcode },
5578     { Bad_Opcode },
5579     { Bad_Opcode },
5580     { Bad_Opcode },
5581     /* 68 */
5582     { Bad_Opcode },
5583     { Bad_Opcode },
5584     { Bad_Opcode },
5585     { Bad_Opcode },
5586     { Bad_Opcode },
5587     { Bad_Opcode },
5588     { Bad_Opcode },
5589     { Bad_Opcode },
5590     /* 70 */
5591     { Bad_Opcode },
5592     { Bad_Opcode },
5593     { Bad_Opcode },
5594     { Bad_Opcode },
5595     { Bad_Opcode },
5596     { Bad_Opcode },
5597     { Bad_Opcode },
5598     { Bad_Opcode },
5599     /* 78 */
5600     { Bad_Opcode },
5601     { Bad_Opcode },
5602     { Bad_Opcode },
5603     { Bad_Opcode },
5604     { Bad_Opcode },
5605     { Bad_Opcode },
5606     { Bad_Opcode },
5607     { Bad_Opcode },
5608     /* 80 */
5609     { PREFIX_TABLE (PREFIX_0F3880) },
5610     { PREFIX_TABLE (PREFIX_0F3881) },
5611     { Bad_Opcode },
5612     { Bad_Opcode },
5613     { Bad_Opcode },
5614     { Bad_Opcode },
5615     { Bad_Opcode },
5616     { Bad_Opcode },
5617     /* 88 */
5618     { Bad_Opcode },
5619     { Bad_Opcode },
5620     { Bad_Opcode },
5621     { Bad_Opcode },
5622     { Bad_Opcode },
5623     { Bad_Opcode },
5624     { Bad_Opcode },
5625     { Bad_Opcode },
5626     /* 90 */
5627     { Bad_Opcode },
5628     { Bad_Opcode },
5629     { Bad_Opcode },
5630     { Bad_Opcode },
5631     { Bad_Opcode },
5632     { Bad_Opcode },
5633     { Bad_Opcode },
5634     { Bad_Opcode },
5635     /* 98 */
5636     { Bad_Opcode },
5637     { Bad_Opcode },
5638     { Bad_Opcode },
5639     { Bad_Opcode },
5640     { Bad_Opcode },
5641     { Bad_Opcode },
5642     { Bad_Opcode },
5643     { Bad_Opcode },
5644     /* a0 */
5645     { Bad_Opcode },
5646     { Bad_Opcode },
5647     { Bad_Opcode },
5648     { Bad_Opcode },
5649     { Bad_Opcode },
5650     { Bad_Opcode },
5651     { Bad_Opcode },
5652     { Bad_Opcode },
5653     /* a8 */
5654     { Bad_Opcode },
5655     { Bad_Opcode },
5656     { Bad_Opcode },
5657     { Bad_Opcode },
5658     { Bad_Opcode },
5659     { Bad_Opcode },
5660     { Bad_Opcode },
5661     { Bad_Opcode },
5662     /* b0 */
5663     { Bad_Opcode },
5664     { Bad_Opcode },
5665     { Bad_Opcode },
5666     { Bad_Opcode },
5667     { Bad_Opcode },
5668     { Bad_Opcode },
5669     { Bad_Opcode },
5670     { Bad_Opcode },
5671     /* b8 */
5672     { Bad_Opcode },
5673     { Bad_Opcode },
5674     { Bad_Opcode },
5675     { Bad_Opcode },
5676     { Bad_Opcode },
5677     { Bad_Opcode },
5678     { Bad_Opcode },
5679     { Bad_Opcode },
5680     /* c0 */
5681     { Bad_Opcode },
5682     { Bad_Opcode },
5683     { Bad_Opcode },
5684     { Bad_Opcode },
5685     { Bad_Opcode },
5686     { Bad_Opcode },
5687     { Bad_Opcode },
5688     { Bad_Opcode },
5689     /* c8 */
5690     { Bad_Opcode },
5691     { Bad_Opcode },
5692     { Bad_Opcode },
5693     { Bad_Opcode },
5694     { Bad_Opcode },
5695     { Bad_Opcode },
5696     { Bad_Opcode },
5697     { Bad_Opcode },
5698     /* d0 */
5699     { Bad_Opcode },
5700     { Bad_Opcode },
5701     { Bad_Opcode },
5702     { Bad_Opcode },
5703     { Bad_Opcode },
5704     { Bad_Opcode },
5705     { Bad_Opcode },
5706     { Bad_Opcode },
5707     /* d8 */
5708     { Bad_Opcode },
5709     { Bad_Opcode },
5710     { Bad_Opcode },
5711     { PREFIX_TABLE (PREFIX_0F38DB) },
5712     { PREFIX_TABLE (PREFIX_0F38DC) },
5713     { PREFIX_TABLE (PREFIX_0F38DD) },
5714     { PREFIX_TABLE (PREFIX_0F38DE) },
5715     { PREFIX_TABLE (PREFIX_0F38DF) },
5716     /* e0 */
5717     { Bad_Opcode },
5718     { Bad_Opcode },
5719     { Bad_Opcode },
5720     { Bad_Opcode },
5721     { Bad_Opcode },
5722     { Bad_Opcode },
5723     { Bad_Opcode },
5724     { Bad_Opcode },
5725     /* e8 */
5726     { Bad_Opcode },
5727     { Bad_Opcode },
5728     { Bad_Opcode },
5729     { Bad_Opcode },
5730     { Bad_Opcode },
5731     { Bad_Opcode },
5732     { Bad_Opcode },
5733     { Bad_Opcode },
5734     /* f0 */
5735     { PREFIX_TABLE (PREFIX_0F38F0) },
5736     { PREFIX_TABLE (PREFIX_0F38F1) },
5737     { Bad_Opcode },
5738     { Bad_Opcode },
5739     { Bad_Opcode },
5740     { Bad_Opcode },
5741     { Bad_Opcode },
5742     { Bad_Opcode },
5743     /* f8 */
5744     { Bad_Opcode },
5745     { Bad_Opcode },
5746     { Bad_Opcode },
5747     { Bad_Opcode },
5748     { Bad_Opcode },
5749     { Bad_Opcode },
5750     { Bad_Opcode },
5751     { Bad_Opcode },
5752   },
5753   /* THREE_BYTE_0F3A */
5754   {
5755     /* 00 */
5756     { Bad_Opcode },
5757     { Bad_Opcode },
5758     { Bad_Opcode },
5759     { Bad_Opcode },
5760     { Bad_Opcode },
5761     { Bad_Opcode },
5762     { Bad_Opcode },
5763     { Bad_Opcode },
5764     /* 08 */
5765     { PREFIX_TABLE (PREFIX_0F3A08) },
5766     { PREFIX_TABLE (PREFIX_0F3A09) },
5767     { PREFIX_TABLE (PREFIX_0F3A0A) },
5768     { PREFIX_TABLE (PREFIX_0F3A0B) },
5769     { PREFIX_TABLE (PREFIX_0F3A0C) },
5770     { PREFIX_TABLE (PREFIX_0F3A0D) },
5771     { PREFIX_TABLE (PREFIX_0F3A0E) },
5772     { "palignr",        { MX, EM, Ib } },
5773     /* 10 */
5774     { Bad_Opcode },
5775     { Bad_Opcode },
5776     { Bad_Opcode },
5777     { Bad_Opcode },
5778     { PREFIX_TABLE (PREFIX_0F3A14) },
5779     { PREFIX_TABLE (PREFIX_0F3A15) },
5780     { PREFIX_TABLE (PREFIX_0F3A16) },
5781     { PREFIX_TABLE (PREFIX_0F3A17) },
5782     /* 18 */
5783     { Bad_Opcode },
5784     { Bad_Opcode },
5785     { Bad_Opcode },
5786     { Bad_Opcode },
5787     { Bad_Opcode },
5788     { Bad_Opcode },
5789     { Bad_Opcode },
5790     { Bad_Opcode },
5791     /* 20 */
5792     { PREFIX_TABLE (PREFIX_0F3A20) },
5793     { PREFIX_TABLE (PREFIX_0F3A21) },
5794     { PREFIX_TABLE (PREFIX_0F3A22) },
5795     { Bad_Opcode },
5796     { Bad_Opcode },
5797     { Bad_Opcode },
5798     { Bad_Opcode },
5799     { Bad_Opcode },
5800     /* 28 */
5801     { Bad_Opcode },
5802     { Bad_Opcode },
5803     { Bad_Opcode },
5804     { Bad_Opcode },
5805     { Bad_Opcode },
5806     { Bad_Opcode },
5807     { Bad_Opcode },
5808     { Bad_Opcode },
5809     /* 30 */
5810     { Bad_Opcode },
5811     { Bad_Opcode },
5812     { Bad_Opcode },
5813     { Bad_Opcode },
5814     { Bad_Opcode },
5815     { Bad_Opcode },
5816     { Bad_Opcode },
5817     { Bad_Opcode },
5818     /* 38 */
5819     { Bad_Opcode },
5820     { Bad_Opcode },
5821     { Bad_Opcode },
5822     { Bad_Opcode },
5823     { Bad_Opcode },
5824     { Bad_Opcode },
5825     { Bad_Opcode },
5826     { Bad_Opcode },
5827     /* 40 */
5828     { PREFIX_TABLE (PREFIX_0F3A40) },
5829     { PREFIX_TABLE (PREFIX_0F3A41) },
5830     { PREFIX_TABLE (PREFIX_0F3A42) },
5831     { Bad_Opcode },
5832     { PREFIX_TABLE (PREFIX_0F3A44) },
5833     { Bad_Opcode },
5834     { Bad_Opcode },
5835     { Bad_Opcode },
5836     /* 48 */
5837     { Bad_Opcode },
5838     { Bad_Opcode },
5839     { Bad_Opcode },
5840     { Bad_Opcode },
5841     { Bad_Opcode },
5842     { Bad_Opcode },
5843     { Bad_Opcode },
5844     { Bad_Opcode },
5845     /* 50 */
5846     { Bad_Opcode },
5847     { Bad_Opcode },
5848     { Bad_Opcode },
5849     { Bad_Opcode },
5850     { Bad_Opcode },
5851     { Bad_Opcode },
5852     { Bad_Opcode },
5853     { Bad_Opcode },
5854     /* 58 */
5855     { Bad_Opcode },
5856     { Bad_Opcode },
5857     { Bad_Opcode },
5858     { Bad_Opcode },
5859     { Bad_Opcode },
5860     { Bad_Opcode },
5861     { Bad_Opcode },
5862     { Bad_Opcode },
5863     /* 60 */
5864     { PREFIX_TABLE (PREFIX_0F3A60) },
5865     { PREFIX_TABLE (PREFIX_0F3A61) },
5866     { PREFIX_TABLE (PREFIX_0F3A62) },
5867     { PREFIX_TABLE (PREFIX_0F3A63) },
5868     { Bad_Opcode },
5869     { Bad_Opcode },
5870     { Bad_Opcode },
5871     { Bad_Opcode },
5872     /* 68 */
5873     { Bad_Opcode },
5874     { Bad_Opcode },
5875     { Bad_Opcode },
5876     { Bad_Opcode },
5877     { Bad_Opcode },
5878     { Bad_Opcode },
5879     { Bad_Opcode },
5880     { Bad_Opcode },
5881     /* 70 */
5882     { Bad_Opcode },
5883     { Bad_Opcode },
5884     { Bad_Opcode },
5885     { Bad_Opcode },
5886     { Bad_Opcode },
5887     { Bad_Opcode },
5888     { Bad_Opcode },
5889     { Bad_Opcode },
5890     /* 78 */
5891     { Bad_Opcode },
5892     { Bad_Opcode },
5893     { Bad_Opcode },
5894     { Bad_Opcode },
5895     { Bad_Opcode },
5896     { Bad_Opcode },
5897     { Bad_Opcode },
5898     { Bad_Opcode },
5899     /* 80 */
5900     { Bad_Opcode },
5901     { Bad_Opcode },
5902     { Bad_Opcode },
5903     { Bad_Opcode },
5904     { Bad_Opcode },
5905     { Bad_Opcode },
5906     { Bad_Opcode },
5907     { Bad_Opcode },
5908     /* 88 */
5909     { Bad_Opcode },
5910     { Bad_Opcode },
5911     { Bad_Opcode },
5912     { Bad_Opcode },
5913     { Bad_Opcode },
5914     { Bad_Opcode },
5915     { Bad_Opcode },
5916     { Bad_Opcode },
5917     /* 90 */
5918     { Bad_Opcode },
5919     { Bad_Opcode },
5920     { Bad_Opcode },
5921     { Bad_Opcode },
5922     { Bad_Opcode },
5923     { Bad_Opcode },
5924     { Bad_Opcode },
5925     { Bad_Opcode },
5926     /* 98 */
5927     { Bad_Opcode },
5928     { Bad_Opcode },
5929     { Bad_Opcode },
5930     { Bad_Opcode },
5931     { Bad_Opcode },
5932     { Bad_Opcode },
5933     { Bad_Opcode },
5934     { Bad_Opcode },
5935     /* a0 */
5936     { Bad_Opcode },
5937     { Bad_Opcode },
5938     { Bad_Opcode },
5939     { Bad_Opcode },
5940     { Bad_Opcode },
5941     { Bad_Opcode },
5942     { Bad_Opcode },
5943     { Bad_Opcode },
5944     /* a8 */
5945     { Bad_Opcode },
5946     { Bad_Opcode },
5947     { Bad_Opcode },
5948     { Bad_Opcode },
5949     { Bad_Opcode },
5950     { Bad_Opcode },
5951     { Bad_Opcode },
5952     { Bad_Opcode },
5953     /* b0 */
5954     { Bad_Opcode },
5955     { Bad_Opcode },
5956     { Bad_Opcode },
5957     { Bad_Opcode },
5958     { Bad_Opcode },
5959     { Bad_Opcode },
5960     { Bad_Opcode },
5961     { Bad_Opcode },
5962     /* b8 */
5963     { Bad_Opcode },
5964     { Bad_Opcode },
5965     { Bad_Opcode },
5966     { Bad_Opcode },
5967     { Bad_Opcode },
5968     { Bad_Opcode },
5969     { Bad_Opcode },
5970     { Bad_Opcode },
5971     /* c0 */
5972     { Bad_Opcode },
5973     { Bad_Opcode },
5974     { Bad_Opcode },
5975     { Bad_Opcode },
5976     { Bad_Opcode },
5977     { Bad_Opcode },
5978     { Bad_Opcode },
5979     { Bad_Opcode },
5980     /* c8 */
5981     { Bad_Opcode },
5982     { Bad_Opcode },
5983     { Bad_Opcode },
5984     { Bad_Opcode },
5985     { Bad_Opcode },
5986     { Bad_Opcode },
5987     { Bad_Opcode },
5988     { Bad_Opcode },
5989     /* d0 */
5990     { Bad_Opcode },
5991     { Bad_Opcode },
5992     { Bad_Opcode },
5993     { Bad_Opcode },
5994     { Bad_Opcode },
5995     { Bad_Opcode },
5996     { Bad_Opcode },
5997     { Bad_Opcode },
5998     /* d8 */
5999     { Bad_Opcode },
6000     { Bad_Opcode },
6001     { Bad_Opcode },
6002     { Bad_Opcode },
6003     { Bad_Opcode },
6004     { Bad_Opcode },
6005     { Bad_Opcode },
6006     { PREFIX_TABLE (PREFIX_0F3ADF) },
6007     /* e0 */
6008     { Bad_Opcode },
6009     { Bad_Opcode },
6010     { Bad_Opcode },
6011     { Bad_Opcode },
6012     { Bad_Opcode },
6013     { Bad_Opcode },
6014     { Bad_Opcode },
6015     { Bad_Opcode },
6016     /* e8 */
6017     { Bad_Opcode },
6018     { Bad_Opcode },
6019     { Bad_Opcode },
6020     { Bad_Opcode },
6021     { Bad_Opcode },
6022     { Bad_Opcode },
6023     { Bad_Opcode },
6024     { Bad_Opcode },
6025     /* f0 */
6026     { Bad_Opcode },
6027     { Bad_Opcode },
6028     { Bad_Opcode },
6029     { Bad_Opcode },
6030     { Bad_Opcode },
6031     { Bad_Opcode },
6032     { Bad_Opcode },
6033     { Bad_Opcode },
6034     /* f8 */
6035     { Bad_Opcode },
6036     { Bad_Opcode },
6037     { Bad_Opcode },
6038     { Bad_Opcode },
6039     { Bad_Opcode },
6040     { Bad_Opcode },
6041     { Bad_Opcode },
6042     { Bad_Opcode },
6043   },
6044
6045   /* THREE_BYTE_0F7A */
6046   {
6047     /* 00 */
6048     { Bad_Opcode },
6049     { Bad_Opcode },
6050     { Bad_Opcode },
6051     { Bad_Opcode },
6052     { Bad_Opcode },
6053     { Bad_Opcode },
6054     { Bad_Opcode },
6055     { Bad_Opcode },
6056     /* 08 */
6057     { Bad_Opcode },
6058     { Bad_Opcode },
6059     { Bad_Opcode },
6060     { Bad_Opcode },
6061     { Bad_Opcode },
6062     { Bad_Opcode },
6063     { Bad_Opcode },
6064     { Bad_Opcode },
6065     /* 10 */
6066     { Bad_Opcode },
6067     { Bad_Opcode },
6068     { Bad_Opcode },
6069     { Bad_Opcode },
6070     { Bad_Opcode },
6071     { Bad_Opcode },
6072     { Bad_Opcode },
6073     { Bad_Opcode },
6074     /* 18 */
6075     { Bad_Opcode },
6076     { Bad_Opcode },
6077     { Bad_Opcode },
6078     { Bad_Opcode },
6079     { Bad_Opcode },
6080     { Bad_Opcode },
6081     { Bad_Opcode },
6082     { Bad_Opcode },
6083     /* 20 */
6084     { "ptest",          { XX } },
6085     { Bad_Opcode },
6086     { Bad_Opcode },
6087     { Bad_Opcode },
6088     { Bad_Opcode },
6089     { Bad_Opcode },
6090     { Bad_Opcode },
6091     { Bad_Opcode },
6092     /* 28 */
6093     { Bad_Opcode },
6094     { Bad_Opcode },
6095     { Bad_Opcode },
6096     { Bad_Opcode },
6097     { Bad_Opcode },
6098     { Bad_Opcode },
6099     { Bad_Opcode },
6100     { Bad_Opcode },
6101     /* 30 */
6102     { Bad_Opcode },
6103     { Bad_Opcode },
6104     { Bad_Opcode },
6105     { Bad_Opcode },
6106     { Bad_Opcode },
6107     { Bad_Opcode },
6108     { Bad_Opcode },
6109     { Bad_Opcode },
6110     /* 38 */
6111     { Bad_Opcode },
6112     { Bad_Opcode },
6113     { Bad_Opcode },
6114     { Bad_Opcode },
6115     { Bad_Opcode },
6116     { Bad_Opcode },
6117     { Bad_Opcode },
6118     { Bad_Opcode },
6119     /* 40 */
6120     { Bad_Opcode },
6121     { "phaddbw",        { XM, EXq } },
6122     { "phaddbd",        { XM, EXq } },
6123     { "phaddbq",        { XM, EXq } },
6124     { Bad_Opcode },
6125     { Bad_Opcode },
6126     { "phaddwd",        { XM, EXq } },
6127     { "phaddwq",        { XM, EXq } },
6128     /* 48 */
6129     { Bad_Opcode },
6130     { Bad_Opcode },
6131     { Bad_Opcode },
6132     { "phadddq",        { XM, EXq } },
6133     { Bad_Opcode },
6134     { Bad_Opcode },
6135     { Bad_Opcode },
6136     { Bad_Opcode },
6137     /* 50 */
6138     { Bad_Opcode },
6139     { "phaddubw",       { XM, EXq } },
6140     { "phaddubd",       { XM, EXq } },
6141     { "phaddubq",       { XM, EXq } },
6142     { Bad_Opcode },
6143     { Bad_Opcode },
6144     { "phadduwd",       { XM, EXq } },
6145     { "phadduwq",       { XM, EXq } },
6146     /* 58 */
6147     { Bad_Opcode },
6148     { Bad_Opcode },
6149     { Bad_Opcode },
6150     { "phaddudq",       { XM, EXq } },
6151     { Bad_Opcode },
6152     { Bad_Opcode },
6153     { Bad_Opcode },
6154     { Bad_Opcode },
6155     /* 60 */
6156     { Bad_Opcode },
6157     { "phsubbw",        { XM, EXq } },
6158     { "phsubbd",        { XM, EXq } },
6159     { "phsubbq",        { XM, EXq } },
6160     { Bad_Opcode },
6161     { Bad_Opcode },
6162     { Bad_Opcode },
6163     { Bad_Opcode },
6164     /* 68 */
6165     { Bad_Opcode },
6166     { Bad_Opcode },
6167     { Bad_Opcode },
6168     { Bad_Opcode },
6169     { Bad_Opcode },
6170     { Bad_Opcode },
6171     { Bad_Opcode },
6172     { Bad_Opcode },
6173     /* 70 */
6174     { Bad_Opcode },
6175     { Bad_Opcode },
6176     { Bad_Opcode },
6177     { Bad_Opcode },
6178     { Bad_Opcode },
6179     { Bad_Opcode },
6180     { Bad_Opcode },
6181     { Bad_Opcode },
6182     /* 78 */
6183     { Bad_Opcode },
6184     { Bad_Opcode },
6185     { Bad_Opcode },
6186     { Bad_Opcode },
6187     { Bad_Opcode },
6188     { Bad_Opcode },
6189     { Bad_Opcode },
6190     { Bad_Opcode },
6191     /* 80 */
6192     { Bad_Opcode },
6193     { Bad_Opcode },
6194     { Bad_Opcode },
6195     { Bad_Opcode },
6196     { Bad_Opcode },
6197     { Bad_Opcode },
6198     { Bad_Opcode },
6199     { Bad_Opcode },
6200     /* 88 */
6201     { Bad_Opcode },
6202     { Bad_Opcode },
6203     { Bad_Opcode },
6204     { Bad_Opcode },
6205     { Bad_Opcode },
6206     { Bad_Opcode },
6207     { Bad_Opcode },
6208     { Bad_Opcode },
6209     /* 90 */
6210     { Bad_Opcode },
6211     { Bad_Opcode },
6212     { Bad_Opcode },
6213     { Bad_Opcode },
6214     { Bad_Opcode },
6215     { Bad_Opcode },
6216     { Bad_Opcode },
6217     { Bad_Opcode },
6218     /* 98 */
6219     { Bad_Opcode },
6220     { Bad_Opcode },
6221     { Bad_Opcode },
6222     { Bad_Opcode },
6223     { Bad_Opcode },
6224     { Bad_Opcode },
6225     { Bad_Opcode },
6226     { Bad_Opcode },
6227     /* a0 */
6228     { Bad_Opcode },
6229     { Bad_Opcode },
6230     { Bad_Opcode },
6231     { Bad_Opcode },
6232     { Bad_Opcode },
6233     { Bad_Opcode },
6234     { Bad_Opcode },
6235     { Bad_Opcode },
6236     /* a8 */
6237     { Bad_Opcode },
6238     { Bad_Opcode },
6239     { Bad_Opcode },
6240     { Bad_Opcode },
6241     { Bad_Opcode },
6242     { Bad_Opcode },
6243     { Bad_Opcode },
6244     { Bad_Opcode },
6245     /* b0 */
6246     { Bad_Opcode },
6247     { Bad_Opcode },
6248     { Bad_Opcode },
6249     { Bad_Opcode },
6250     { Bad_Opcode },
6251     { Bad_Opcode },
6252     { Bad_Opcode },
6253     { Bad_Opcode },
6254     /* b8 */
6255     { Bad_Opcode },
6256     { Bad_Opcode },
6257     { Bad_Opcode },
6258     { Bad_Opcode },
6259     { Bad_Opcode },
6260     { Bad_Opcode },
6261     { Bad_Opcode },
6262     { Bad_Opcode },
6263     /* c0 */
6264     { Bad_Opcode },
6265     { Bad_Opcode },
6266     { Bad_Opcode },
6267     { Bad_Opcode },
6268     { Bad_Opcode },
6269     { Bad_Opcode },
6270     { Bad_Opcode },
6271     { Bad_Opcode },
6272     /* c8 */
6273     { Bad_Opcode },
6274     { Bad_Opcode },
6275     { Bad_Opcode },
6276     { Bad_Opcode },
6277     { Bad_Opcode },
6278     { Bad_Opcode },
6279     { Bad_Opcode },
6280     { Bad_Opcode },
6281     /* d0 */
6282     { Bad_Opcode },
6283     { Bad_Opcode },
6284     { Bad_Opcode },
6285     { Bad_Opcode },
6286     { Bad_Opcode },
6287     { Bad_Opcode },
6288     { Bad_Opcode },
6289     { Bad_Opcode },
6290     /* d8 */
6291     { Bad_Opcode },
6292     { Bad_Opcode },
6293     { Bad_Opcode },
6294     { Bad_Opcode },
6295     { Bad_Opcode },
6296     { Bad_Opcode },
6297     { Bad_Opcode },
6298     { Bad_Opcode },
6299     /* e0 */
6300     { Bad_Opcode },
6301     { Bad_Opcode },
6302     { Bad_Opcode },
6303     { Bad_Opcode },
6304     { Bad_Opcode },
6305     { Bad_Opcode },
6306     { Bad_Opcode },
6307     { Bad_Opcode },
6308     /* e8 */
6309     { Bad_Opcode },
6310     { Bad_Opcode },
6311     { Bad_Opcode },
6312     { Bad_Opcode },
6313     { Bad_Opcode },
6314     { Bad_Opcode },
6315     { Bad_Opcode },
6316     { Bad_Opcode },
6317     /* f0 */
6318     { Bad_Opcode },
6319     { Bad_Opcode },
6320     { Bad_Opcode },
6321     { Bad_Opcode },
6322     { Bad_Opcode },
6323     { Bad_Opcode },
6324     { Bad_Opcode },
6325     { Bad_Opcode },
6326     /* f8 */
6327     { Bad_Opcode },
6328     { Bad_Opcode },
6329     { Bad_Opcode },
6330     { Bad_Opcode },
6331     { Bad_Opcode },
6332     { Bad_Opcode },
6333     { Bad_Opcode },
6334     { Bad_Opcode },
6335   },
6336 };
6337
6338 static const struct dis386 xop_table[][256] = {
6339   /* XOP_08 */
6340   {
6341     /* 00 */
6342     { Bad_Opcode },
6343     { Bad_Opcode },
6344     { Bad_Opcode },
6345     { Bad_Opcode },
6346     { Bad_Opcode },
6347     { Bad_Opcode },
6348     { Bad_Opcode },
6349     { Bad_Opcode },
6350     /* 08 */
6351     { Bad_Opcode },
6352     { Bad_Opcode },
6353     { Bad_Opcode },
6354     { Bad_Opcode },
6355     { Bad_Opcode },
6356     { Bad_Opcode },
6357     { Bad_Opcode },
6358     { Bad_Opcode },
6359     /* 10 */
6360     { Bad_Opcode },
6361     { Bad_Opcode },
6362     { Bad_Opcode },
6363     { Bad_Opcode },
6364     { Bad_Opcode },
6365     { Bad_Opcode },
6366     { Bad_Opcode },
6367     { Bad_Opcode },
6368     /* 18 */
6369     { Bad_Opcode },
6370     { Bad_Opcode },
6371     { Bad_Opcode },
6372     { Bad_Opcode },
6373     { Bad_Opcode },
6374     { Bad_Opcode },
6375     { Bad_Opcode },
6376     { Bad_Opcode },
6377     /* 20 */
6378     { Bad_Opcode },
6379     { Bad_Opcode },
6380     { Bad_Opcode },
6381     { Bad_Opcode },
6382     { Bad_Opcode },
6383     { Bad_Opcode },
6384     { Bad_Opcode },
6385     { Bad_Opcode },
6386     /* 28 */
6387     { Bad_Opcode },
6388     { Bad_Opcode },
6389     { Bad_Opcode },
6390     { Bad_Opcode },
6391     { Bad_Opcode },
6392     { Bad_Opcode },
6393     { Bad_Opcode },
6394     { Bad_Opcode },
6395     /* 30 */
6396     { Bad_Opcode },
6397     { Bad_Opcode },
6398     { Bad_Opcode },
6399     { Bad_Opcode },
6400     { Bad_Opcode },
6401     { Bad_Opcode },
6402     { Bad_Opcode },
6403     { Bad_Opcode },
6404     /* 38 */
6405     { Bad_Opcode },
6406     { Bad_Opcode },
6407     { Bad_Opcode },
6408     { Bad_Opcode },
6409     { Bad_Opcode },
6410     { Bad_Opcode },
6411     { Bad_Opcode },
6412     { Bad_Opcode },
6413     /* 40 */
6414     { Bad_Opcode },
6415     { Bad_Opcode },
6416     { Bad_Opcode },
6417     { Bad_Opcode },
6418     { Bad_Opcode },
6419     { Bad_Opcode },
6420     { Bad_Opcode },
6421     { Bad_Opcode },
6422     /* 48 */
6423     { Bad_Opcode },
6424     { Bad_Opcode },
6425     { Bad_Opcode },
6426     { Bad_Opcode },
6427     { Bad_Opcode },
6428     { Bad_Opcode },
6429     { Bad_Opcode },
6430     { Bad_Opcode },
6431     /* 50 */
6432     { Bad_Opcode },
6433     { Bad_Opcode },
6434     { Bad_Opcode },
6435     { Bad_Opcode },
6436     { Bad_Opcode },
6437     { Bad_Opcode },
6438     { Bad_Opcode },
6439     { Bad_Opcode },
6440     /* 58 */
6441     { Bad_Opcode },
6442     { Bad_Opcode },
6443     { Bad_Opcode },
6444     { Bad_Opcode },
6445     { Bad_Opcode },
6446     { Bad_Opcode },
6447     { Bad_Opcode },
6448     { Bad_Opcode },
6449     /* 60 */
6450     { Bad_Opcode },
6451     { Bad_Opcode },
6452     { Bad_Opcode },
6453     { Bad_Opcode },
6454     { Bad_Opcode },
6455     { Bad_Opcode },
6456     { Bad_Opcode },
6457     { Bad_Opcode },
6458     /* 68 */
6459     { Bad_Opcode },
6460     { Bad_Opcode },
6461     { Bad_Opcode },
6462     { Bad_Opcode },
6463     { Bad_Opcode },
6464     { Bad_Opcode },
6465     { Bad_Opcode },
6466     { Bad_Opcode },
6467     /* 70 */
6468     { Bad_Opcode },
6469     { Bad_Opcode },
6470     { Bad_Opcode },
6471     { Bad_Opcode },
6472     { Bad_Opcode },
6473     { Bad_Opcode },
6474     { Bad_Opcode },
6475     { Bad_Opcode },
6476     /* 78 */
6477     { Bad_Opcode },
6478     { Bad_Opcode },
6479     { Bad_Opcode },
6480     { Bad_Opcode },
6481     { Bad_Opcode },
6482     { Bad_Opcode },
6483     { Bad_Opcode },
6484     { Bad_Opcode },
6485     /* 80 */
6486     { Bad_Opcode },
6487     { Bad_Opcode },
6488     { Bad_Opcode },
6489     { Bad_Opcode },
6490     { Bad_Opcode },
6491     { "vpmacssww",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6492     { "vpmacsswd",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6493     { "vpmacssdql",     { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6494     /* 88 */
6495     { Bad_Opcode },
6496     { Bad_Opcode },
6497     { Bad_Opcode },
6498     { Bad_Opcode },
6499     { Bad_Opcode },
6500     { Bad_Opcode },
6501     { "vpmacssdd",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6502     { "vpmacssdqh",     { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6503     /* 90 */
6504     { Bad_Opcode },
6505     { Bad_Opcode },
6506     { Bad_Opcode },
6507     { Bad_Opcode },
6508     { Bad_Opcode },
6509     { "vpmacsww",       { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6510     { "vpmacswd",       { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6511     { "vpmacsdql",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6512     /* 98 */
6513     { Bad_Opcode },
6514     { Bad_Opcode },
6515     { Bad_Opcode },
6516     { Bad_Opcode },
6517     { Bad_Opcode },
6518     { Bad_Opcode },
6519     { "vpmacsdd",       { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6520     { "vpmacsdqh",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6521     /* a0 */
6522     { Bad_Opcode },
6523     { Bad_Opcode },
6524     { "vpcmov",         { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6525     { "vpperm",         { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6526     { Bad_Opcode },
6527     { Bad_Opcode },
6528     { "vpmadcsswd",     { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6529     { Bad_Opcode },
6530     /* a8 */
6531     { Bad_Opcode },
6532     { Bad_Opcode },
6533     { Bad_Opcode },
6534     { Bad_Opcode },
6535     { Bad_Opcode },
6536     { Bad_Opcode },
6537     { Bad_Opcode },
6538     { Bad_Opcode },
6539     /* b0 */
6540     { Bad_Opcode },
6541     { Bad_Opcode },
6542     { Bad_Opcode },
6543     { Bad_Opcode },
6544     { Bad_Opcode },
6545     { Bad_Opcode },
6546     { "vpmadcswd",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6547     { Bad_Opcode },
6548     /* b8 */
6549     { Bad_Opcode },
6550     { Bad_Opcode },
6551     { Bad_Opcode },
6552     { Bad_Opcode },
6553     { Bad_Opcode },
6554     { Bad_Opcode },
6555     { Bad_Opcode },
6556     { Bad_Opcode },
6557     /* c0 */
6558     { "vprotb",         { XM, Vex_2src_1, Ib } },
6559     { "vprotw",         { XM, Vex_2src_1, Ib } },
6560     { "vprotd",         { XM, Vex_2src_1, Ib } },
6561     { "vprotq",         { XM, Vex_2src_1, Ib } },
6562     { Bad_Opcode },
6563     { Bad_Opcode },
6564     { Bad_Opcode },
6565     { Bad_Opcode },
6566     /* c8 */
6567     { Bad_Opcode },
6568     { Bad_Opcode },
6569     { Bad_Opcode },
6570     { Bad_Opcode },
6571     { "vpcomb",         { XM, Vex128, EXx, Ib } },
6572     { "vpcomw",         { XM, Vex128, EXx, Ib } },
6573     { "vpcomd",         { XM, Vex128, EXx, Ib } },
6574     { "vpcomq",         { XM, Vex128, EXx, Ib } },
6575     /* d0 */
6576     { Bad_Opcode },
6577     { Bad_Opcode },
6578     { Bad_Opcode },
6579     { Bad_Opcode },
6580     { Bad_Opcode },
6581     { Bad_Opcode },
6582     { Bad_Opcode },
6583     { Bad_Opcode },
6584     /* d8 */
6585     { Bad_Opcode },
6586     { Bad_Opcode },
6587     { Bad_Opcode },
6588     { Bad_Opcode },
6589     { Bad_Opcode },
6590     { Bad_Opcode },
6591     { Bad_Opcode },
6592     { Bad_Opcode },
6593     /* e0 */
6594     { Bad_Opcode },
6595     { Bad_Opcode },
6596     { Bad_Opcode },
6597     { Bad_Opcode },
6598     { Bad_Opcode },
6599     { Bad_Opcode },
6600     { Bad_Opcode },
6601     { Bad_Opcode },
6602     /* e8 */
6603     { Bad_Opcode },
6604     { Bad_Opcode },
6605     { Bad_Opcode },
6606     { Bad_Opcode },
6607     { "vpcomub",        { XM, Vex128, EXx, Ib } },
6608     { "vpcomuw",        { XM, Vex128, EXx, Ib } },
6609     { "vpcomud",        { XM, Vex128, EXx, Ib } },
6610     { "vpcomuq",        { XM, Vex128, EXx, Ib } },
6611     /* f0 */
6612     { Bad_Opcode },
6613     { Bad_Opcode },
6614     { Bad_Opcode },
6615     { Bad_Opcode },
6616     { Bad_Opcode },
6617     { Bad_Opcode },
6618     { Bad_Opcode },
6619     { Bad_Opcode },
6620     /* f8 */
6621     { Bad_Opcode },
6622     { Bad_Opcode },
6623     { Bad_Opcode },
6624     { Bad_Opcode },
6625     { Bad_Opcode },
6626     { Bad_Opcode },
6627     { Bad_Opcode },
6628     { Bad_Opcode },
6629   },
6630   /* XOP_09 */
6631   {
6632     /* 00 */
6633     { Bad_Opcode },
6634     { Bad_Opcode },
6635     { Bad_Opcode },
6636     { Bad_Opcode },
6637     { Bad_Opcode },
6638     { Bad_Opcode },
6639     { Bad_Opcode },
6640     { Bad_Opcode },
6641     /* 08 */
6642     { Bad_Opcode },
6643     { Bad_Opcode },
6644     { Bad_Opcode },
6645     { Bad_Opcode },
6646     { Bad_Opcode },
6647     { Bad_Opcode },
6648     { Bad_Opcode },
6649     { Bad_Opcode },
6650     /* 10 */
6651     { Bad_Opcode },
6652     { Bad_Opcode },
6653     { REG_TABLE (REG_XOP_LWPCB) },
6654     { Bad_Opcode },
6655     { Bad_Opcode },
6656     { Bad_Opcode },
6657     { Bad_Opcode },
6658     { Bad_Opcode },
6659     /* 18 */
6660     { Bad_Opcode },
6661     { Bad_Opcode },
6662     { Bad_Opcode },
6663     { Bad_Opcode },
6664     { Bad_Opcode },
6665     { Bad_Opcode },
6666     { Bad_Opcode },
6667     { Bad_Opcode },
6668     /* 20 */
6669     { Bad_Opcode },
6670     { Bad_Opcode },
6671     { Bad_Opcode },
6672     { Bad_Opcode },
6673     { Bad_Opcode },
6674     { Bad_Opcode },
6675     { Bad_Opcode },
6676     { Bad_Opcode },
6677     /* 28 */
6678     { Bad_Opcode },
6679     { Bad_Opcode },
6680     { Bad_Opcode },
6681     { Bad_Opcode },
6682     { Bad_Opcode },
6683     { Bad_Opcode },
6684     { Bad_Opcode },
6685     { Bad_Opcode },
6686     /* 30 */
6687     { Bad_Opcode },
6688     { Bad_Opcode },
6689     { Bad_Opcode },
6690     { Bad_Opcode },
6691     { Bad_Opcode },
6692     { Bad_Opcode },
6693     { Bad_Opcode },
6694     { Bad_Opcode },
6695     /* 38 */
6696     { Bad_Opcode },
6697     { Bad_Opcode },
6698     { Bad_Opcode },
6699     { Bad_Opcode },
6700     { Bad_Opcode },
6701     { Bad_Opcode },
6702     { Bad_Opcode },
6703     { Bad_Opcode },
6704     /* 40 */
6705     { Bad_Opcode },
6706     { Bad_Opcode },
6707     { Bad_Opcode },
6708     { Bad_Opcode },
6709     { Bad_Opcode },
6710     { Bad_Opcode },
6711     { Bad_Opcode },
6712     { Bad_Opcode },
6713     /* 48 */
6714     { Bad_Opcode },
6715     { Bad_Opcode },
6716     { Bad_Opcode },
6717     { Bad_Opcode },
6718     { Bad_Opcode },
6719     { Bad_Opcode },
6720     { Bad_Opcode },
6721     { Bad_Opcode },
6722     /* 50 */
6723     { Bad_Opcode },
6724     { Bad_Opcode },
6725     { Bad_Opcode },
6726     { Bad_Opcode },
6727     { Bad_Opcode },
6728     { Bad_Opcode },
6729     { Bad_Opcode },
6730     { Bad_Opcode },
6731     /* 58 */
6732     { Bad_Opcode },
6733     { Bad_Opcode },
6734     { Bad_Opcode },
6735     { Bad_Opcode },
6736     { Bad_Opcode },
6737     { Bad_Opcode },
6738     { Bad_Opcode },
6739     { Bad_Opcode },
6740     /* 60 */
6741     { Bad_Opcode },
6742     { Bad_Opcode },
6743     { Bad_Opcode },
6744     { Bad_Opcode },
6745     { Bad_Opcode },
6746     { Bad_Opcode },
6747     { Bad_Opcode },
6748     { Bad_Opcode },
6749     /* 68 */
6750     { Bad_Opcode },
6751     { Bad_Opcode },
6752     { Bad_Opcode },
6753     { Bad_Opcode },
6754     { Bad_Opcode },
6755     { Bad_Opcode },
6756     { Bad_Opcode },
6757     { Bad_Opcode },
6758     /* 70 */
6759     { Bad_Opcode },
6760     { Bad_Opcode },
6761     { Bad_Opcode },
6762     { Bad_Opcode },
6763     { Bad_Opcode },
6764     { Bad_Opcode },
6765     { Bad_Opcode },
6766     { Bad_Opcode },
6767     /* 78 */
6768     { Bad_Opcode },
6769     { Bad_Opcode },
6770     { Bad_Opcode },
6771     { Bad_Opcode },
6772     { Bad_Opcode },
6773     { Bad_Opcode },
6774     { Bad_Opcode },
6775     { Bad_Opcode },
6776     /* 80 */
6777     { VEX_LEN_TABLE (VEX_LEN_XOP_09_80) },
6778     { VEX_LEN_TABLE (VEX_LEN_XOP_09_81) },
6779     { "vfrczss",        { XM, EXd } },
6780     { "vfrczsd",        { XM, EXq } },
6781     { Bad_Opcode },
6782     { Bad_Opcode },
6783     { Bad_Opcode },
6784     { Bad_Opcode },
6785     /* 88 */
6786     { Bad_Opcode },
6787     { Bad_Opcode },
6788     { Bad_Opcode },
6789     { Bad_Opcode },
6790     { Bad_Opcode },
6791     { Bad_Opcode },
6792     { Bad_Opcode },
6793     { Bad_Opcode },
6794     /* 90 */
6795     { "vprotb",         { XM, Vex_2src_1, Vex_2src_2 } },
6796     { "vprotw",         { XM, Vex_2src_1, Vex_2src_2 } },
6797     { "vprotd",         { XM, Vex_2src_1, Vex_2src_2 } },
6798     { "vprotq",         { XM, Vex_2src_1, Vex_2src_2 } },
6799     { "vpshlb",         { XM, Vex_2src_1, Vex_2src_2 } },
6800     { "vpshlw",         { XM, Vex_2src_1, Vex_2src_2 } },
6801     { "vpshld",         { XM, Vex_2src_1, Vex_2src_2 } },
6802     { "vpshlq",         { XM, Vex_2src_1, Vex_2src_2 } },
6803     /* 98 */
6804     { "vpshab",         { XM, Vex_2src_1, Vex_2src_2 } },
6805     { "vpshaw",         { XM, Vex_2src_1, Vex_2src_2 } },
6806     { "vpshad",         { XM, Vex_2src_1, Vex_2src_2 } },
6807     { "vpshaq",         { XM, Vex_2src_1, Vex_2src_2 } },
6808     { Bad_Opcode },
6809     { Bad_Opcode },
6810     { Bad_Opcode },
6811     { Bad_Opcode },
6812     /* a0 */
6813     { Bad_Opcode },
6814     { Bad_Opcode },
6815     { Bad_Opcode },
6816     { Bad_Opcode },
6817     { Bad_Opcode },
6818     { Bad_Opcode },
6819     { Bad_Opcode },
6820     { Bad_Opcode },
6821     /* a8 */
6822     { Bad_Opcode },
6823     { Bad_Opcode },
6824     { Bad_Opcode },
6825     { Bad_Opcode },
6826     { Bad_Opcode },
6827     { Bad_Opcode },
6828     { Bad_Opcode },
6829     { Bad_Opcode },
6830     /* b0 */
6831     { Bad_Opcode },
6832     { Bad_Opcode },
6833     { Bad_Opcode },
6834     { Bad_Opcode },
6835     { Bad_Opcode },
6836     { Bad_Opcode },
6837     { Bad_Opcode },
6838     { Bad_Opcode },
6839     /* b8 */
6840     { Bad_Opcode },
6841     { Bad_Opcode },
6842     { Bad_Opcode },
6843     { Bad_Opcode },
6844     { Bad_Opcode },
6845     { Bad_Opcode },
6846     { Bad_Opcode },
6847     { Bad_Opcode },
6848     /* c0 */
6849     { Bad_Opcode },
6850     { "vphaddbw",       { XM, EXxmm } },
6851     { "vphaddbd",       { XM, EXxmm } },
6852     { "vphaddbq",       { XM, EXxmm } },
6853     { Bad_Opcode },
6854     { Bad_Opcode },
6855     { "vphaddwd",       { XM, EXxmm } },
6856     { "vphaddwq",       { XM, EXxmm } },
6857     /* c8 */
6858     { Bad_Opcode },
6859     { Bad_Opcode },
6860     { Bad_Opcode },
6861     { "vphadddq",       { XM, EXxmm } },
6862     { Bad_Opcode },
6863     { Bad_Opcode },
6864     { Bad_Opcode },
6865     { Bad_Opcode },
6866     /* d0 */
6867     { Bad_Opcode },
6868     { "vphaddubw",      { XM, EXxmm } },
6869     { "vphaddubd",      { XM, EXxmm } },
6870     { "vphaddubq",      { XM, EXxmm } },
6871     { Bad_Opcode },
6872     { Bad_Opcode },
6873     { "vphadduwd",      { XM, EXxmm } },
6874     { "vphadduwq",      { XM, EXxmm } },
6875     /* d8 */
6876     { Bad_Opcode },
6877     { Bad_Opcode },
6878     { Bad_Opcode },
6879     { "vphaddudq",      { XM, EXxmm } },
6880     { Bad_Opcode },
6881     { Bad_Opcode },
6882     { Bad_Opcode },
6883     { Bad_Opcode },
6884     /* e0 */
6885     { Bad_Opcode },
6886     { "vphsubbw",       { XM, EXxmm } },
6887     { "vphsubwd",       { XM, EXxmm } },
6888     { "vphsubdq",       { XM, EXxmm } },
6889     { Bad_Opcode },
6890     { Bad_Opcode },
6891     { Bad_Opcode },
6892     { Bad_Opcode },
6893     /* e8 */
6894     { Bad_Opcode },
6895     { Bad_Opcode },
6896     { Bad_Opcode },
6897     { Bad_Opcode },
6898     { Bad_Opcode },
6899     { Bad_Opcode },
6900     { Bad_Opcode },
6901     { Bad_Opcode },
6902     /* f0 */
6903     { Bad_Opcode },
6904     { Bad_Opcode },
6905     { Bad_Opcode },
6906     { Bad_Opcode },
6907     { Bad_Opcode },
6908     { Bad_Opcode },
6909     { Bad_Opcode },
6910     { Bad_Opcode },
6911     /* f8 */
6912     { Bad_Opcode },
6913     { Bad_Opcode },
6914     { Bad_Opcode },
6915     { Bad_Opcode },
6916     { Bad_Opcode },
6917     { Bad_Opcode },
6918     { Bad_Opcode },
6919     { Bad_Opcode },
6920   },
6921   /* XOP_0A */
6922   {
6923     /* 00 */
6924     { Bad_Opcode },
6925     { Bad_Opcode },
6926     { Bad_Opcode },
6927     { Bad_Opcode },
6928     { Bad_Opcode },
6929     { Bad_Opcode },
6930     { Bad_Opcode },
6931     { Bad_Opcode },
6932     /* 08 */
6933     { Bad_Opcode },
6934     { Bad_Opcode },
6935     { Bad_Opcode },
6936     { Bad_Opcode },
6937     { Bad_Opcode },
6938     { Bad_Opcode },
6939     { Bad_Opcode },
6940     { Bad_Opcode },
6941     /* 10 */
6942     { Bad_Opcode },
6943     { Bad_Opcode },
6944     { REG_TABLE (REG_XOP_LWP) },
6945     { Bad_Opcode },
6946     { Bad_Opcode },
6947     { Bad_Opcode },
6948     { Bad_Opcode },
6949     { Bad_Opcode },
6950     /* 18 */
6951     { Bad_Opcode },
6952     { Bad_Opcode },
6953     { Bad_Opcode },
6954     { Bad_Opcode },
6955     { Bad_Opcode },
6956     { Bad_Opcode },
6957     { Bad_Opcode },
6958     { Bad_Opcode },
6959     /* 20 */
6960     { Bad_Opcode },
6961     { Bad_Opcode },
6962     { Bad_Opcode },
6963     { Bad_Opcode },
6964     { Bad_Opcode },
6965     { Bad_Opcode },
6966     { Bad_Opcode },
6967     { Bad_Opcode },
6968     /* 28 */
6969     { Bad_Opcode },
6970     { Bad_Opcode },
6971     { Bad_Opcode },
6972     { Bad_Opcode },
6973     { Bad_Opcode },
6974     { Bad_Opcode },
6975     { Bad_Opcode },
6976     { Bad_Opcode },
6977     /* 30 */
6978     { Bad_Opcode },
6979     { Bad_Opcode },
6980     { Bad_Opcode },
6981     { Bad_Opcode },
6982     { Bad_Opcode },
6983     { Bad_Opcode },
6984     { Bad_Opcode },
6985     { Bad_Opcode },
6986     /* 38 */
6987     { Bad_Opcode },
6988     { Bad_Opcode },
6989     { Bad_Opcode },
6990     { Bad_Opcode },
6991     { Bad_Opcode },
6992     { Bad_Opcode },
6993     { Bad_Opcode },
6994     { Bad_Opcode },
6995     /* 40 */
6996     { Bad_Opcode },
6997     { Bad_Opcode },
6998     { Bad_Opcode },
6999     { Bad_Opcode },
7000     { Bad_Opcode },
7001     { Bad_Opcode },
7002     { Bad_Opcode },
7003     { Bad_Opcode },
7004     /* 48 */
7005     { Bad_Opcode },
7006     { Bad_Opcode },
7007     { Bad_Opcode },
7008     { Bad_Opcode },
7009     { Bad_Opcode },
7010     { Bad_Opcode },
7011     { Bad_Opcode },
7012     { Bad_Opcode },
7013     /* 50 */
7014     { Bad_Opcode },
7015     { Bad_Opcode },
7016     { Bad_Opcode },
7017     { Bad_Opcode },
7018     { Bad_Opcode },
7019     { Bad_Opcode },
7020     { Bad_Opcode },
7021     { Bad_Opcode },
7022     /* 58 */
7023     { Bad_Opcode },
7024     { Bad_Opcode },
7025     { Bad_Opcode },
7026     { Bad_Opcode },
7027     { Bad_Opcode },
7028     { Bad_Opcode },
7029     { Bad_Opcode },
7030     { Bad_Opcode },
7031     /* 60 */
7032     { Bad_Opcode },
7033     { Bad_Opcode },
7034     { Bad_Opcode },
7035     { Bad_Opcode },
7036     { Bad_Opcode },
7037     { Bad_Opcode },
7038     { Bad_Opcode },
7039     { Bad_Opcode },
7040     /* 68 */
7041     { Bad_Opcode },
7042     { Bad_Opcode },
7043     { Bad_Opcode },
7044     { Bad_Opcode },
7045     { Bad_Opcode },
7046     { Bad_Opcode },
7047     { Bad_Opcode },
7048     { Bad_Opcode },
7049     /* 70 */
7050     { Bad_Opcode },
7051     { Bad_Opcode },
7052     { Bad_Opcode },
7053     { Bad_Opcode },
7054     { Bad_Opcode },
7055     { Bad_Opcode },
7056     { Bad_Opcode },
7057     { Bad_Opcode },
7058     /* 78 */
7059     { Bad_Opcode },
7060     { Bad_Opcode },
7061     { Bad_Opcode },
7062     { Bad_Opcode },
7063     { Bad_Opcode },
7064     { Bad_Opcode },
7065     { Bad_Opcode },
7066     { Bad_Opcode },
7067     /* 80 */
7068     { Bad_Opcode },
7069     { Bad_Opcode },
7070     { Bad_Opcode },
7071     { Bad_Opcode },
7072     { Bad_Opcode },
7073     { Bad_Opcode },
7074     { Bad_Opcode },
7075     { Bad_Opcode },
7076     /* 88 */
7077     { Bad_Opcode },
7078     { Bad_Opcode },
7079     { Bad_Opcode },
7080     { Bad_Opcode },
7081     { Bad_Opcode },
7082     { Bad_Opcode },
7083     { Bad_Opcode },
7084     { Bad_Opcode },
7085     /* 90 */
7086     { Bad_Opcode },
7087     { Bad_Opcode },
7088     { Bad_Opcode },
7089     { Bad_Opcode },
7090     { Bad_Opcode },
7091     { Bad_Opcode },
7092     { Bad_Opcode },
7093     { Bad_Opcode },
7094     /* 98 */
7095     { Bad_Opcode },
7096     { Bad_Opcode },
7097     { Bad_Opcode },
7098     { Bad_Opcode },
7099     { Bad_Opcode },
7100     { Bad_Opcode },
7101     { Bad_Opcode },
7102     { Bad_Opcode },
7103     /* a0 */
7104     { Bad_Opcode },
7105     { Bad_Opcode },
7106     { Bad_Opcode },
7107     { Bad_Opcode },
7108     { Bad_Opcode },
7109     { Bad_Opcode },
7110     { Bad_Opcode },
7111     { Bad_Opcode },
7112     /* a8 */
7113     { Bad_Opcode },
7114     { Bad_Opcode },
7115     { Bad_Opcode },
7116     { Bad_Opcode },
7117     { Bad_Opcode },
7118     { Bad_Opcode },
7119     { Bad_Opcode },
7120     { Bad_Opcode },
7121     /* b0 */
7122     { Bad_Opcode },
7123     { Bad_Opcode },
7124     { Bad_Opcode },
7125     { Bad_Opcode },
7126     { Bad_Opcode },
7127     { Bad_Opcode },
7128     { Bad_Opcode },
7129     { Bad_Opcode },
7130     /* b8 */
7131     { Bad_Opcode },
7132     { Bad_Opcode },
7133     { Bad_Opcode },
7134     { Bad_Opcode },
7135     { Bad_Opcode },
7136     { Bad_Opcode },
7137     { Bad_Opcode },
7138     { Bad_Opcode },
7139     /* c0 */
7140     { Bad_Opcode },
7141     { Bad_Opcode },
7142     { Bad_Opcode },
7143     { Bad_Opcode },
7144     { Bad_Opcode },
7145     { Bad_Opcode },
7146     { Bad_Opcode },
7147     { Bad_Opcode },
7148     /* c8 */
7149     { Bad_Opcode },
7150     { Bad_Opcode },
7151     { Bad_Opcode },
7152     { Bad_Opcode },
7153     { Bad_Opcode },
7154     { Bad_Opcode },
7155     { Bad_Opcode },
7156     { Bad_Opcode },
7157     /* d0 */
7158     { Bad_Opcode },
7159     { Bad_Opcode },
7160     { Bad_Opcode },
7161     { Bad_Opcode },
7162     { Bad_Opcode },
7163     { Bad_Opcode },
7164     { Bad_Opcode },
7165     { Bad_Opcode },
7166     /* d8 */
7167     { Bad_Opcode },
7168     { Bad_Opcode },
7169     { Bad_Opcode },
7170     { Bad_Opcode },
7171     { Bad_Opcode },
7172     { Bad_Opcode },
7173     { Bad_Opcode },
7174     { Bad_Opcode },
7175     /* e0 */
7176     { Bad_Opcode },
7177     { Bad_Opcode },
7178     { Bad_Opcode },
7179     { Bad_Opcode },
7180     { Bad_Opcode },
7181     { Bad_Opcode },
7182     { Bad_Opcode },
7183     { Bad_Opcode },
7184     /* e8 */
7185     { Bad_Opcode },
7186     { Bad_Opcode },
7187     { Bad_Opcode },
7188     { Bad_Opcode },
7189     { Bad_Opcode },
7190     { Bad_Opcode },
7191     { Bad_Opcode },
7192     { Bad_Opcode },
7193     /* f0 */
7194     { Bad_Opcode },
7195     { Bad_Opcode },
7196     { Bad_Opcode },
7197     { Bad_Opcode },
7198     { Bad_Opcode },
7199     { Bad_Opcode },
7200     { Bad_Opcode },
7201     { Bad_Opcode },
7202     /* f8 */
7203     { Bad_Opcode },
7204     { Bad_Opcode },
7205     { Bad_Opcode },
7206     { Bad_Opcode },
7207     { Bad_Opcode },
7208     { Bad_Opcode },
7209     { Bad_Opcode },
7210     { Bad_Opcode },
7211   },
7212 };
7213
7214 static const struct dis386 vex_table[][256] = {
7215   /* VEX_0F */
7216   {
7217     /* 00 */
7218     { Bad_Opcode },
7219     { Bad_Opcode },
7220     { Bad_Opcode },
7221     { Bad_Opcode },
7222     { Bad_Opcode },
7223     { Bad_Opcode },
7224     { Bad_Opcode },
7225     { Bad_Opcode },
7226     /* 08 */
7227     { Bad_Opcode },
7228     { Bad_Opcode },
7229     { Bad_Opcode },
7230     { Bad_Opcode },
7231     { Bad_Opcode },
7232     { Bad_Opcode },
7233     { Bad_Opcode },
7234     { Bad_Opcode },
7235     /* 10 */
7236     { PREFIX_TABLE (PREFIX_VEX_10) },
7237     { PREFIX_TABLE (PREFIX_VEX_11) },
7238     { PREFIX_TABLE (PREFIX_VEX_12) },
7239     { MOD_TABLE (MOD_VEX_13) },
7240     { VEX_W_TABLE (VEX_W_14) },
7241     { VEX_W_TABLE (VEX_W_15) },
7242     { PREFIX_TABLE (PREFIX_VEX_16) },
7243     { MOD_TABLE (MOD_VEX_17) },
7244     /* 18 */
7245     { Bad_Opcode },
7246     { Bad_Opcode },
7247     { Bad_Opcode },
7248     { Bad_Opcode },
7249     { Bad_Opcode },
7250     { Bad_Opcode },
7251     { Bad_Opcode },
7252     { Bad_Opcode },
7253     /* 20 */
7254     { Bad_Opcode },
7255     { Bad_Opcode },
7256     { Bad_Opcode },
7257     { Bad_Opcode },
7258     { Bad_Opcode },
7259     { Bad_Opcode },
7260     { Bad_Opcode },
7261     { Bad_Opcode },
7262     /* 28 */
7263     { VEX_W_TABLE (VEX_W_28) },
7264     { VEX_W_TABLE (VEX_W_29) },
7265     { PREFIX_TABLE (PREFIX_VEX_2A) },
7266     { MOD_TABLE (MOD_VEX_2B) },
7267     { PREFIX_TABLE (PREFIX_VEX_2C) },
7268     { PREFIX_TABLE (PREFIX_VEX_2D) },
7269     { PREFIX_TABLE (PREFIX_VEX_2E) },
7270     { PREFIX_TABLE (PREFIX_VEX_2F) },
7271     /* 30 */
7272     { Bad_Opcode },
7273     { Bad_Opcode },
7274     { Bad_Opcode },
7275     { Bad_Opcode },
7276     { Bad_Opcode },
7277     { Bad_Opcode },
7278     { Bad_Opcode },
7279     { Bad_Opcode },
7280     /* 38 */
7281     { Bad_Opcode },
7282     { Bad_Opcode },
7283     { Bad_Opcode },
7284     { Bad_Opcode },
7285     { Bad_Opcode },
7286     { Bad_Opcode },
7287     { Bad_Opcode },
7288     { Bad_Opcode },
7289     /* 40 */
7290     { Bad_Opcode },
7291     { Bad_Opcode },
7292     { Bad_Opcode },
7293     { Bad_Opcode },
7294     { Bad_Opcode },
7295     { Bad_Opcode },
7296     { Bad_Opcode },
7297     { Bad_Opcode },
7298     /* 48 */
7299     { Bad_Opcode },
7300     { Bad_Opcode },
7301     { Bad_Opcode },
7302     { Bad_Opcode },
7303     { Bad_Opcode },
7304     { Bad_Opcode },
7305     { Bad_Opcode },
7306     { Bad_Opcode },
7307     /* 50 */
7308     { MOD_TABLE (MOD_VEX_50) },
7309     { PREFIX_TABLE (PREFIX_VEX_51) },
7310     { PREFIX_TABLE (PREFIX_VEX_52) },
7311     { PREFIX_TABLE (PREFIX_VEX_53) },
7312     { "vandpX",         { XM, Vex, EXx } },
7313     { "vandnpX",        { XM, Vex, EXx } },
7314     { "vorpX",          { XM, Vex, EXx } },
7315     { "vxorpX",         { XM, Vex, EXx } },
7316     /* 58 */
7317     { PREFIX_TABLE (PREFIX_VEX_58) },
7318     { PREFIX_TABLE (PREFIX_VEX_59) },
7319     { PREFIX_TABLE (PREFIX_VEX_5A) },
7320     { PREFIX_TABLE (PREFIX_VEX_5B) },
7321     { PREFIX_TABLE (PREFIX_VEX_5C) },
7322     { PREFIX_TABLE (PREFIX_VEX_5D) },
7323     { PREFIX_TABLE (PREFIX_VEX_5E) },
7324     { PREFIX_TABLE (PREFIX_VEX_5F) },
7325     /* 60 */
7326     { PREFIX_TABLE (PREFIX_VEX_60) },
7327     { PREFIX_TABLE (PREFIX_VEX_61) },
7328     { PREFIX_TABLE (PREFIX_VEX_62) },
7329     { PREFIX_TABLE (PREFIX_VEX_63) },
7330     { PREFIX_TABLE (PREFIX_VEX_64) },
7331     { PREFIX_TABLE (PREFIX_VEX_65) },
7332     { PREFIX_TABLE (PREFIX_VEX_66) },
7333     { PREFIX_TABLE (PREFIX_VEX_67) },
7334     /* 68 */
7335     { PREFIX_TABLE (PREFIX_VEX_68) },
7336     { PREFIX_TABLE (PREFIX_VEX_69) },
7337     { PREFIX_TABLE (PREFIX_VEX_6A) },
7338     { PREFIX_TABLE (PREFIX_VEX_6B) },
7339     { PREFIX_TABLE (PREFIX_VEX_6C) },
7340     { PREFIX_TABLE (PREFIX_VEX_6D) },
7341     { PREFIX_TABLE (PREFIX_VEX_6E) },
7342     { PREFIX_TABLE (PREFIX_VEX_6F) },
7343     /* 70 */
7344     { PREFIX_TABLE (PREFIX_VEX_70) },
7345     { REG_TABLE (REG_VEX_71) },
7346     { REG_TABLE (REG_VEX_72) },
7347     { REG_TABLE (REG_VEX_73) },
7348     { PREFIX_TABLE (PREFIX_VEX_74) },
7349     { PREFIX_TABLE (PREFIX_VEX_75) },
7350     { PREFIX_TABLE (PREFIX_VEX_76) },
7351     { PREFIX_TABLE (PREFIX_VEX_77) },
7352     /* 78 */
7353     { Bad_Opcode },
7354     { Bad_Opcode },
7355     { Bad_Opcode },
7356     { Bad_Opcode },
7357     { PREFIX_TABLE (PREFIX_VEX_7C) },
7358     { PREFIX_TABLE (PREFIX_VEX_7D) },
7359     { PREFIX_TABLE (PREFIX_VEX_7E) },
7360     { PREFIX_TABLE (PREFIX_VEX_7F) },
7361     /* 80 */
7362     { Bad_Opcode },
7363     { Bad_Opcode },
7364     { Bad_Opcode },
7365     { Bad_Opcode },
7366     { Bad_Opcode },
7367     { Bad_Opcode },
7368     { Bad_Opcode },
7369     { Bad_Opcode },
7370     /* 88 */
7371     { Bad_Opcode },
7372     { Bad_Opcode },
7373     { Bad_Opcode },
7374     { Bad_Opcode },
7375     { Bad_Opcode },
7376     { Bad_Opcode },
7377     { Bad_Opcode },
7378     { Bad_Opcode },
7379     /* 90 */
7380     { Bad_Opcode },
7381     { Bad_Opcode },
7382     { Bad_Opcode },
7383     { Bad_Opcode },
7384     { Bad_Opcode },
7385     { Bad_Opcode },
7386     { Bad_Opcode },
7387     { Bad_Opcode },
7388     /* 98 */
7389     { Bad_Opcode },
7390     { Bad_Opcode },
7391     { Bad_Opcode },
7392     { Bad_Opcode },
7393     { Bad_Opcode },
7394     { Bad_Opcode },
7395     { Bad_Opcode },
7396     { Bad_Opcode },
7397     /* a0 */
7398     { Bad_Opcode },
7399     { Bad_Opcode },
7400     { Bad_Opcode },
7401     { Bad_Opcode },
7402     { Bad_Opcode },
7403     { Bad_Opcode },
7404     { Bad_Opcode },
7405     { Bad_Opcode },
7406     /* a8 */
7407     { Bad_Opcode },
7408     { Bad_Opcode },
7409     { Bad_Opcode },
7410     { Bad_Opcode },
7411     { Bad_Opcode },
7412     { Bad_Opcode },
7413     { REG_TABLE (REG_VEX_AE) },
7414     { Bad_Opcode },
7415     /* b0 */
7416     { Bad_Opcode },
7417     { Bad_Opcode },
7418     { Bad_Opcode },
7419     { Bad_Opcode },
7420     { Bad_Opcode },
7421     { Bad_Opcode },
7422     { Bad_Opcode },
7423     { Bad_Opcode },
7424     /* b8 */
7425     { Bad_Opcode },
7426     { Bad_Opcode },
7427     { Bad_Opcode },
7428     { Bad_Opcode },
7429     { Bad_Opcode },
7430     { Bad_Opcode },
7431     { Bad_Opcode },
7432     { Bad_Opcode },
7433     /* c0 */
7434     { Bad_Opcode },
7435     { Bad_Opcode },
7436     { PREFIX_TABLE (PREFIX_VEX_C2) },
7437     { Bad_Opcode },
7438     { PREFIX_TABLE (PREFIX_VEX_C4) },
7439     { PREFIX_TABLE (PREFIX_VEX_C5) },
7440     { "vshufpX",        { XM, Vex, EXx, Ib } },
7441     { Bad_Opcode },
7442     /* c8 */
7443     { Bad_Opcode },
7444     { Bad_Opcode },
7445     { Bad_Opcode },
7446     { Bad_Opcode },
7447     { Bad_Opcode },
7448     { Bad_Opcode },
7449     { Bad_Opcode },
7450     { Bad_Opcode },
7451     /* d0 */
7452     { PREFIX_TABLE (PREFIX_VEX_D0) },
7453     { PREFIX_TABLE (PREFIX_VEX_D1) },
7454     { PREFIX_TABLE (PREFIX_VEX_D2) },
7455     { PREFIX_TABLE (PREFIX_VEX_D3) },
7456     { PREFIX_TABLE (PREFIX_VEX_D4) },
7457     { PREFIX_TABLE (PREFIX_VEX_D5) },
7458     { PREFIX_TABLE (PREFIX_VEX_D6) },
7459     { PREFIX_TABLE (PREFIX_VEX_D7) },
7460     /* d8 */
7461     { PREFIX_TABLE (PREFIX_VEX_D8) },
7462     { PREFIX_TABLE (PREFIX_VEX_D9) },
7463     { PREFIX_TABLE (PREFIX_VEX_DA) },
7464     { PREFIX_TABLE (PREFIX_VEX_DB) },
7465     { PREFIX_TABLE (PREFIX_VEX_DC) },
7466     { PREFIX_TABLE (PREFIX_VEX_DD) },
7467     { PREFIX_TABLE (PREFIX_VEX_DE) },
7468     { PREFIX_TABLE (PREFIX_VEX_DF) },
7469     /* e0 */
7470     { PREFIX_TABLE (PREFIX_VEX_E0) },
7471     { PREFIX_TABLE (PREFIX_VEX_E1) },
7472     { PREFIX_TABLE (PREFIX_VEX_E2) },
7473     { PREFIX_TABLE (PREFIX_VEX_E3) },
7474     { PREFIX_TABLE (PREFIX_VEX_E4) },
7475     { PREFIX_TABLE (PREFIX_VEX_E5) },
7476     { PREFIX_TABLE (PREFIX_VEX_E6) },
7477     { PREFIX_TABLE (PREFIX_VEX_E7) },
7478     /* e8 */
7479     { PREFIX_TABLE (PREFIX_VEX_E8) },
7480     { PREFIX_TABLE (PREFIX_VEX_E9) },
7481     { PREFIX_TABLE (PREFIX_VEX_EA) },
7482     { PREFIX_TABLE (PREFIX_VEX_EB) },
7483     { PREFIX_TABLE (PREFIX_VEX_EC) },
7484     { PREFIX_TABLE (PREFIX_VEX_ED) },
7485     { PREFIX_TABLE (PREFIX_VEX_EE) },
7486     { PREFIX_TABLE (PREFIX_VEX_EF) },
7487     /* f0 */
7488     { PREFIX_TABLE (PREFIX_VEX_F0) },
7489     { PREFIX_TABLE (PREFIX_VEX_F1) },
7490     { PREFIX_TABLE (PREFIX_VEX_F2) },
7491     { PREFIX_TABLE (PREFIX_VEX_F3) },
7492     { PREFIX_TABLE (PREFIX_VEX_F4) },
7493     { PREFIX_TABLE (PREFIX_VEX_F5) },
7494     { PREFIX_TABLE (PREFIX_VEX_F6) },
7495     { PREFIX_TABLE (PREFIX_VEX_F7) },
7496     /* f8 */
7497     { PREFIX_TABLE (PREFIX_VEX_F8) },
7498     { PREFIX_TABLE (PREFIX_VEX_F9) },
7499     { PREFIX_TABLE (PREFIX_VEX_FA) },
7500     { PREFIX_TABLE (PREFIX_VEX_FB) },
7501     { PREFIX_TABLE (PREFIX_VEX_FC) },
7502     { PREFIX_TABLE (PREFIX_VEX_FD) },
7503     { PREFIX_TABLE (PREFIX_VEX_FE) },
7504     { Bad_Opcode },
7505   },
7506   /* VEX_0F38 */
7507   {
7508     /* 00 */
7509     { PREFIX_TABLE (PREFIX_VEX_3800) },
7510     { PREFIX_TABLE (PREFIX_VEX_3801) },
7511     { PREFIX_TABLE (PREFIX_VEX_3802) },
7512     { PREFIX_TABLE (PREFIX_VEX_3803) },
7513     { PREFIX_TABLE (PREFIX_VEX_3804) },
7514     { PREFIX_TABLE (PREFIX_VEX_3805) },
7515     { PREFIX_TABLE (PREFIX_VEX_3806) },
7516     { PREFIX_TABLE (PREFIX_VEX_3807) },
7517     /* 08 */
7518     { PREFIX_TABLE (PREFIX_VEX_3808) },
7519     { PREFIX_TABLE (PREFIX_VEX_3809) },
7520     { PREFIX_TABLE (PREFIX_VEX_380A) },
7521     { PREFIX_TABLE (PREFIX_VEX_380B) },
7522     { PREFIX_TABLE (PREFIX_VEX_380C) },
7523     { PREFIX_TABLE (PREFIX_VEX_380D) },
7524     { PREFIX_TABLE (PREFIX_VEX_380E) },
7525     { PREFIX_TABLE (PREFIX_VEX_380F) },
7526     /* 10 */
7527     { Bad_Opcode },
7528     { Bad_Opcode },
7529     { Bad_Opcode },
7530     { Bad_Opcode },
7531     { Bad_Opcode },
7532     { Bad_Opcode },
7533     { Bad_Opcode },
7534     { PREFIX_TABLE (PREFIX_VEX_3817) },
7535     /* 18 */
7536     { PREFIX_TABLE (PREFIX_VEX_3818) },
7537     { PREFIX_TABLE (PREFIX_VEX_3819) },
7538     { PREFIX_TABLE (PREFIX_VEX_381A) },
7539     { Bad_Opcode },
7540     { PREFIX_TABLE (PREFIX_VEX_381C) },
7541     { PREFIX_TABLE (PREFIX_VEX_381D) },
7542     { PREFIX_TABLE (PREFIX_VEX_381E) },
7543     { Bad_Opcode },
7544     /* 20 */
7545     { PREFIX_TABLE (PREFIX_VEX_3820) },
7546     { PREFIX_TABLE (PREFIX_VEX_3821) },
7547     { PREFIX_TABLE (PREFIX_VEX_3822) },
7548     { PREFIX_TABLE (PREFIX_VEX_3823) },
7549     { PREFIX_TABLE (PREFIX_VEX_3824) },
7550     { PREFIX_TABLE (PREFIX_VEX_3825) },
7551     { Bad_Opcode },
7552     { Bad_Opcode },
7553     /* 28 */
7554     { PREFIX_TABLE (PREFIX_VEX_3828) },
7555     { PREFIX_TABLE (PREFIX_VEX_3829) },
7556     { PREFIX_TABLE (PREFIX_VEX_382A) },
7557     { PREFIX_TABLE (PREFIX_VEX_382B) },
7558     { PREFIX_TABLE (PREFIX_VEX_382C) },
7559     { PREFIX_TABLE (PREFIX_VEX_382D) },
7560     { PREFIX_TABLE (PREFIX_VEX_382E) },
7561     { PREFIX_TABLE (PREFIX_VEX_382F) },
7562     /* 30 */
7563     { PREFIX_TABLE (PREFIX_VEX_3830) },
7564     { PREFIX_TABLE (PREFIX_VEX_3831) },
7565     { PREFIX_TABLE (PREFIX_VEX_3832) },
7566     { PREFIX_TABLE (PREFIX_VEX_3833) },
7567     { PREFIX_TABLE (PREFIX_VEX_3834) },
7568     { PREFIX_TABLE (PREFIX_VEX_3835) },
7569     { Bad_Opcode },
7570     { PREFIX_TABLE (PREFIX_VEX_3837) },
7571     /* 38 */
7572     { PREFIX_TABLE (PREFIX_VEX_3838) },
7573     { PREFIX_TABLE (PREFIX_VEX_3839) },
7574     { PREFIX_TABLE (PREFIX_VEX_383A) },
7575     { PREFIX_TABLE (PREFIX_VEX_383B) },
7576     { PREFIX_TABLE (PREFIX_VEX_383C) },
7577     { PREFIX_TABLE (PREFIX_VEX_383D) },
7578     { PREFIX_TABLE (PREFIX_VEX_383E) },
7579     { PREFIX_TABLE (PREFIX_VEX_383F) },
7580     /* 40 */
7581     { PREFIX_TABLE (PREFIX_VEX_3840) },
7582     { PREFIX_TABLE (PREFIX_VEX_3841) },
7583     { Bad_Opcode },
7584     { Bad_Opcode },
7585     { Bad_Opcode },
7586     { Bad_Opcode },
7587     { Bad_Opcode },
7588     { Bad_Opcode },
7589     /* 48 */
7590     { Bad_Opcode },
7591     { Bad_Opcode },
7592     { Bad_Opcode },
7593     { Bad_Opcode },
7594     { Bad_Opcode },
7595     { Bad_Opcode },
7596     { Bad_Opcode },
7597     { Bad_Opcode },
7598     /* 50 */
7599     { Bad_Opcode },
7600     { Bad_Opcode },
7601     { Bad_Opcode },
7602     { Bad_Opcode },
7603     { Bad_Opcode },
7604     { Bad_Opcode },
7605     { Bad_Opcode },
7606     { Bad_Opcode },
7607     /* 58 */
7608     { Bad_Opcode },
7609     { Bad_Opcode },
7610     { Bad_Opcode },
7611     { Bad_Opcode },
7612     { Bad_Opcode },
7613     { Bad_Opcode },
7614     { Bad_Opcode },
7615     { Bad_Opcode },
7616     /* 60 */
7617     { Bad_Opcode },
7618     { Bad_Opcode },
7619     { Bad_Opcode },
7620     { Bad_Opcode },
7621     { Bad_Opcode },
7622     { Bad_Opcode },
7623     { Bad_Opcode },
7624     { Bad_Opcode },
7625     /* 68 */
7626     { Bad_Opcode },
7627     { Bad_Opcode },
7628     { Bad_Opcode },
7629     { Bad_Opcode },
7630     { Bad_Opcode },
7631     { Bad_Opcode },
7632     { Bad_Opcode },
7633     { Bad_Opcode },
7634     /* 70 */
7635     { Bad_Opcode },
7636     { Bad_Opcode },
7637     { Bad_Opcode },
7638     { Bad_Opcode },
7639     { Bad_Opcode },
7640     { Bad_Opcode },
7641     { Bad_Opcode },
7642     { Bad_Opcode },
7643     /* 78 */
7644     { Bad_Opcode },
7645     { Bad_Opcode },
7646     { Bad_Opcode },
7647     { Bad_Opcode },
7648     { Bad_Opcode },
7649     { Bad_Opcode },
7650     { Bad_Opcode },
7651     { Bad_Opcode },
7652     /* 80 */
7653     { Bad_Opcode },
7654     { Bad_Opcode },
7655     { Bad_Opcode },
7656     { Bad_Opcode },
7657     { Bad_Opcode },
7658     { Bad_Opcode },
7659     { Bad_Opcode },
7660     { Bad_Opcode },
7661     /* 88 */
7662     { Bad_Opcode },
7663     { Bad_Opcode },
7664     { Bad_Opcode },
7665     { Bad_Opcode },
7666     { Bad_Opcode },
7667     { Bad_Opcode },
7668     { Bad_Opcode },
7669     { Bad_Opcode },
7670     /* 90 */
7671     { Bad_Opcode },
7672     { Bad_Opcode },
7673     { Bad_Opcode },
7674     { Bad_Opcode },
7675     { Bad_Opcode },
7676     { Bad_Opcode },
7677     { PREFIX_TABLE (PREFIX_VEX_3896) },
7678     { PREFIX_TABLE (PREFIX_VEX_3897) },
7679     /* 98 */
7680     { PREFIX_TABLE (PREFIX_VEX_3898) },
7681     { PREFIX_TABLE (PREFIX_VEX_3899) },
7682     { PREFIX_TABLE (PREFIX_VEX_389A) },
7683     { PREFIX_TABLE (PREFIX_VEX_389B) },
7684     { PREFIX_TABLE (PREFIX_VEX_389C) },
7685     { PREFIX_TABLE (PREFIX_VEX_389D) },
7686     { PREFIX_TABLE (PREFIX_VEX_389E) },
7687     { PREFIX_TABLE (PREFIX_VEX_389F) },
7688     /* a0 */
7689     { Bad_Opcode },
7690     { Bad_Opcode },
7691     { Bad_Opcode },
7692     { Bad_Opcode },
7693     { Bad_Opcode },
7694     { Bad_Opcode },
7695     { PREFIX_TABLE (PREFIX_VEX_38A6) },
7696     { PREFIX_TABLE (PREFIX_VEX_38A7) },
7697     /* a8 */
7698     { PREFIX_TABLE (PREFIX_VEX_38A8) },
7699     { PREFIX_TABLE (PREFIX_VEX_38A9) },
7700     { PREFIX_TABLE (PREFIX_VEX_38AA) },
7701     { PREFIX_TABLE (PREFIX_VEX_38AB) },
7702     { PREFIX_TABLE (PREFIX_VEX_38AC) },
7703     { PREFIX_TABLE (PREFIX_VEX_38AD) },
7704     { PREFIX_TABLE (PREFIX_VEX_38AE) },
7705     { PREFIX_TABLE (PREFIX_VEX_38AF) },
7706     /* b0 */
7707     { Bad_Opcode },
7708     { Bad_Opcode },
7709     { Bad_Opcode },
7710     { Bad_Opcode },
7711     { Bad_Opcode },
7712     { Bad_Opcode },
7713     { PREFIX_TABLE (PREFIX_VEX_38B6) },
7714     { PREFIX_TABLE (PREFIX_VEX_38B7) },
7715     /* b8 */
7716     { PREFIX_TABLE (PREFIX_VEX_38B8) },
7717     { PREFIX_TABLE (PREFIX_VEX_38B9) },
7718     { PREFIX_TABLE (PREFIX_VEX_38BA) },
7719     { PREFIX_TABLE (PREFIX_VEX_38BB) },
7720     { PREFIX_TABLE (PREFIX_VEX_38BC) },
7721     { PREFIX_TABLE (PREFIX_VEX_38BD) },
7722     { PREFIX_TABLE (PREFIX_VEX_38BE) },
7723     { PREFIX_TABLE (PREFIX_VEX_38BF) },
7724     /* c0 */
7725     { Bad_Opcode },
7726     { Bad_Opcode },
7727     { Bad_Opcode },
7728     { Bad_Opcode },
7729     { Bad_Opcode },
7730     { Bad_Opcode },
7731     { Bad_Opcode },
7732     { Bad_Opcode },
7733     /* c8 */
7734     { Bad_Opcode },
7735     { Bad_Opcode },
7736     { Bad_Opcode },
7737     { Bad_Opcode },
7738     { Bad_Opcode },
7739     { Bad_Opcode },
7740     { Bad_Opcode },
7741     { Bad_Opcode },
7742     /* d0 */
7743     { Bad_Opcode },
7744     { Bad_Opcode },
7745     { Bad_Opcode },
7746     { Bad_Opcode },
7747     { Bad_Opcode },
7748     { Bad_Opcode },
7749     { Bad_Opcode },
7750     { Bad_Opcode },
7751     /* d8 */
7752     { Bad_Opcode },
7753     { Bad_Opcode },
7754     { Bad_Opcode },
7755     { PREFIX_TABLE (PREFIX_VEX_38DB) },
7756     { PREFIX_TABLE (PREFIX_VEX_38DC) },
7757     { PREFIX_TABLE (PREFIX_VEX_38DD) },
7758     { PREFIX_TABLE (PREFIX_VEX_38DE) },
7759     { PREFIX_TABLE (PREFIX_VEX_38DF) },
7760     /* e0 */
7761     { Bad_Opcode },
7762     { Bad_Opcode },
7763     { Bad_Opcode },
7764     { Bad_Opcode },
7765     { Bad_Opcode },
7766     { Bad_Opcode },
7767     { Bad_Opcode },
7768     { Bad_Opcode },
7769     /* e8 */
7770     { Bad_Opcode },
7771     { Bad_Opcode },
7772     { Bad_Opcode },
7773     { Bad_Opcode },
7774     { Bad_Opcode },
7775     { Bad_Opcode },
7776     { Bad_Opcode },
7777     { Bad_Opcode },
7778     /* f0 */
7779     { Bad_Opcode },
7780     { Bad_Opcode },
7781     { Bad_Opcode },
7782     { Bad_Opcode },
7783     { Bad_Opcode },
7784     { Bad_Opcode },
7785     { Bad_Opcode },
7786     { Bad_Opcode },
7787     /* f8 */
7788     { Bad_Opcode },
7789     { Bad_Opcode },
7790     { Bad_Opcode },
7791     { Bad_Opcode },
7792     { Bad_Opcode },
7793     { Bad_Opcode },
7794     { Bad_Opcode },
7795     { Bad_Opcode },
7796   },
7797   /* VEX_0F3A */
7798   {
7799     /* 00 */
7800     { Bad_Opcode },
7801     { Bad_Opcode },
7802     { Bad_Opcode },
7803     { Bad_Opcode },
7804     { PREFIX_TABLE (PREFIX_VEX_3A04) },
7805     { PREFIX_TABLE (PREFIX_VEX_3A05) },
7806     { PREFIX_TABLE (PREFIX_VEX_3A06) },
7807     { Bad_Opcode },
7808     /* 08 */
7809     { PREFIX_TABLE (PREFIX_VEX_3A08) },
7810     { PREFIX_TABLE (PREFIX_VEX_3A09) },
7811     { PREFIX_TABLE (PREFIX_VEX_3A0A) },
7812     { PREFIX_TABLE (PREFIX_VEX_3A0B) },
7813     { PREFIX_TABLE (PREFIX_VEX_3A0C) },
7814     { PREFIX_TABLE (PREFIX_VEX_3A0D) },
7815     { PREFIX_TABLE (PREFIX_VEX_3A0E) },
7816     { PREFIX_TABLE (PREFIX_VEX_3A0F) },
7817     /* 10 */
7818     { Bad_Opcode },
7819     { Bad_Opcode },
7820     { Bad_Opcode },
7821     { Bad_Opcode },
7822     { PREFIX_TABLE (PREFIX_VEX_3A14) },
7823     { PREFIX_TABLE (PREFIX_VEX_3A15) },
7824     { PREFIX_TABLE (PREFIX_VEX_3A16) },
7825     { PREFIX_TABLE (PREFIX_VEX_3A17) },
7826     /* 18 */
7827     { PREFIX_TABLE (PREFIX_VEX_3A18) },
7828     { PREFIX_TABLE (PREFIX_VEX_3A19) },
7829     { Bad_Opcode },
7830     { Bad_Opcode },
7831     { Bad_Opcode },
7832     { Bad_Opcode },
7833     { Bad_Opcode },
7834     { Bad_Opcode },
7835     /* 20 */
7836     { PREFIX_TABLE (PREFIX_VEX_3A20) },
7837     { PREFIX_TABLE (PREFIX_VEX_3A21) },
7838     { PREFIX_TABLE (PREFIX_VEX_3A22) },
7839     { Bad_Opcode },
7840     { Bad_Opcode },
7841     { Bad_Opcode },
7842     { Bad_Opcode },
7843     { Bad_Opcode },
7844     /* 28 */
7845     { Bad_Opcode },
7846     { Bad_Opcode },
7847     { Bad_Opcode },
7848     { Bad_Opcode },
7849     { Bad_Opcode },
7850     { Bad_Opcode },
7851     { Bad_Opcode },
7852     { Bad_Opcode },
7853     /* 30 */
7854     { Bad_Opcode },
7855     { Bad_Opcode },
7856     { Bad_Opcode },
7857     { Bad_Opcode },
7858     { Bad_Opcode },
7859     { Bad_Opcode },
7860     { Bad_Opcode },
7861     { Bad_Opcode },
7862     /* 38 */
7863     { Bad_Opcode },
7864     { Bad_Opcode },
7865     { Bad_Opcode },
7866     { Bad_Opcode },
7867     { Bad_Opcode },
7868     { Bad_Opcode },
7869     { Bad_Opcode },
7870     { Bad_Opcode },
7871     /* 40 */
7872     { PREFIX_TABLE (PREFIX_VEX_3A40) },
7873     { PREFIX_TABLE (PREFIX_VEX_3A41) },
7874     { PREFIX_TABLE (PREFIX_VEX_3A42) },
7875     { Bad_Opcode },
7876     { PREFIX_TABLE (PREFIX_VEX_3A44) },
7877     { Bad_Opcode },
7878     { Bad_Opcode },
7879     { Bad_Opcode },
7880     /* 48 */
7881     { PREFIX_TABLE (PREFIX_VEX_3A48) },
7882     { PREFIX_TABLE (PREFIX_VEX_3A49) },
7883     { PREFIX_TABLE (PREFIX_VEX_3A4A) },
7884     { PREFIX_TABLE (PREFIX_VEX_3A4B) },
7885     { PREFIX_TABLE (PREFIX_VEX_3A4C) },
7886     { Bad_Opcode },
7887     { Bad_Opcode },
7888     { Bad_Opcode },
7889     /* 50 */
7890     { Bad_Opcode },
7891     { Bad_Opcode },
7892     { Bad_Opcode },
7893     { Bad_Opcode },
7894     { Bad_Opcode },
7895     { Bad_Opcode },
7896     { Bad_Opcode },
7897     { Bad_Opcode },
7898     /* 58 */
7899     { Bad_Opcode },
7900     { Bad_Opcode },
7901     { Bad_Opcode },
7902     { Bad_Opcode },
7903     { PREFIX_TABLE (PREFIX_VEX_3A5C) },
7904     { PREFIX_TABLE (PREFIX_VEX_3A5D) },
7905     { PREFIX_TABLE (PREFIX_VEX_3A5E) },
7906     { PREFIX_TABLE (PREFIX_VEX_3A5F) },
7907     /* 60 */
7908     { PREFIX_TABLE (PREFIX_VEX_3A60) },
7909     { PREFIX_TABLE (PREFIX_VEX_3A61) },
7910     { PREFIX_TABLE (PREFIX_VEX_3A62) },
7911     { PREFIX_TABLE (PREFIX_VEX_3A63) },
7912     { Bad_Opcode },
7913     { Bad_Opcode },
7914     { Bad_Opcode },
7915     { Bad_Opcode },
7916     /* 68 */
7917     { PREFIX_TABLE (PREFIX_VEX_3A68) },
7918     { PREFIX_TABLE (PREFIX_VEX_3A69) },
7919     { PREFIX_TABLE (PREFIX_VEX_3A6A) },
7920     { PREFIX_TABLE (PREFIX_VEX_3A6B) },
7921     { PREFIX_TABLE (PREFIX_VEX_3A6C) },
7922     { PREFIX_TABLE (PREFIX_VEX_3A6D) },
7923     { PREFIX_TABLE (PREFIX_VEX_3A6E) },
7924     { PREFIX_TABLE (PREFIX_VEX_3A6F) },
7925     /* 70 */
7926     { Bad_Opcode },
7927     { Bad_Opcode },
7928     { Bad_Opcode },
7929     { Bad_Opcode },
7930     { Bad_Opcode },
7931     { Bad_Opcode },
7932     { Bad_Opcode },
7933     { Bad_Opcode },
7934     /* 78 */
7935     { PREFIX_TABLE (PREFIX_VEX_3A78) },
7936     { PREFIX_TABLE (PREFIX_VEX_3A79) },
7937     { PREFIX_TABLE (PREFIX_VEX_3A7A) },
7938     { PREFIX_TABLE (PREFIX_VEX_3A7B) },
7939     { PREFIX_TABLE (PREFIX_VEX_3A7C) },
7940     { PREFIX_TABLE (PREFIX_VEX_3A7D) },
7941     { PREFIX_TABLE (PREFIX_VEX_3A7E) },
7942     { PREFIX_TABLE (PREFIX_VEX_3A7F) },
7943     /* 80 */
7944     { Bad_Opcode },
7945     { Bad_Opcode },
7946     { Bad_Opcode },
7947     { Bad_Opcode },
7948     { Bad_Opcode },
7949     { Bad_Opcode },
7950     { Bad_Opcode },
7951     { Bad_Opcode },
7952     /* 88 */
7953     { Bad_Opcode },
7954     { Bad_Opcode },
7955     { Bad_Opcode },
7956     { Bad_Opcode },
7957     { Bad_Opcode },
7958     { Bad_Opcode },
7959     { Bad_Opcode },
7960     { Bad_Opcode },
7961     /* 90 */
7962     { Bad_Opcode },
7963     { Bad_Opcode },
7964     { Bad_Opcode },
7965     { Bad_Opcode },
7966     { Bad_Opcode },
7967     { Bad_Opcode },
7968     { Bad_Opcode },
7969     { Bad_Opcode },
7970     /* 98 */
7971     { Bad_Opcode },
7972     { Bad_Opcode },
7973     { Bad_Opcode },
7974     { Bad_Opcode },
7975     { Bad_Opcode },
7976     { Bad_Opcode },
7977     { Bad_Opcode },
7978     { Bad_Opcode },
7979     /* a0 */
7980     { Bad_Opcode },
7981     { Bad_Opcode },
7982     { Bad_Opcode },
7983     { Bad_Opcode },
7984     { Bad_Opcode },
7985     { Bad_Opcode },
7986     { Bad_Opcode },
7987     { Bad_Opcode },
7988     /* a8 */
7989     { Bad_Opcode },
7990     { Bad_Opcode },
7991     { Bad_Opcode },
7992     { Bad_Opcode },
7993     { Bad_Opcode },
7994     { Bad_Opcode },
7995     { Bad_Opcode },
7996     { Bad_Opcode },
7997     /* b0 */
7998     { Bad_Opcode },
7999     { Bad_Opcode },
8000     { Bad_Opcode },
8001     { Bad_Opcode },
8002     { Bad_Opcode },
8003     { Bad_Opcode },
8004     { Bad_Opcode },
8005     { Bad_Opcode },
8006     /* b8 */
8007     { Bad_Opcode },
8008     { Bad_Opcode },
8009     { Bad_Opcode },
8010     { Bad_Opcode },
8011     { Bad_Opcode },
8012     { Bad_Opcode },
8013     { Bad_Opcode },
8014     { Bad_Opcode },
8015     /* c0 */
8016     { Bad_Opcode },
8017     { Bad_Opcode },
8018     { Bad_Opcode },
8019     { Bad_Opcode },
8020     { Bad_Opcode },
8021     { Bad_Opcode },
8022     { Bad_Opcode },
8023     { Bad_Opcode },
8024     /* c8 */
8025     { Bad_Opcode },
8026     { Bad_Opcode },
8027     { Bad_Opcode },
8028     { Bad_Opcode },
8029     { Bad_Opcode },
8030     { Bad_Opcode },
8031     { Bad_Opcode },
8032     { Bad_Opcode },
8033     /* d0 */
8034     { Bad_Opcode },
8035     { Bad_Opcode },
8036     { Bad_Opcode },
8037     { Bad_Opcode },
8038     { Bad_Opcode },
8039     { Bad_Opcode },
8040     { Bad_Opcode },
8041     { Bad_Opcode },
8042     /* d8 */
8043     { Bad_Opcode },
8044     { Bad_Opcode },
8045     { Bad_Opcode },
8046     { Bad_Opcode },
8047     { Bad_Opcode },
8048     { Bad_Opcode },
8049     { Bad_Opcode },
8050     { PREFIX_TABLE (PREFIX_VEX_3ADF) },
8051     /* e0 */
8052     { Bad_Opcode },
8053     { Bad_Opcode },
8054     { Bad_Opcode },
8055     { Bad_Opcode },
8056     { Bad_Opcode },
8057     { Bad_Opcode },
8058     { Bad_Opcode },
8059     { Bad_Opcode },
8060     /* e8 */
8061     { Bad_Opcode },
8062     { Bad_Opcode },
8063     { Bad_Opcode },
8064     { Bad_Opcode },
8065     { Bad_Opcode },
8066     { Bad_Opcode },
8067     { Bad_Opcode },
8068     { Bad_Opcode },
8069     /* f0 */
8070     { Bad_Opcode },
8071     { Bad_Opcode },
8072     { Bad_Opcode },
8073     { Bad_Opcode },
8074     { Bad_Opcode },
8075     { Bad_Opcode },
8076     { Bad_Opcode },
8077     { Bad_Opcode },
8078     /* f8 */
8079     { Bad_Opcode },
8080     { Bad_Opcode },
8081     { Bad_Opcode },
8082     { Bad_Opcode },
8083     { Bad_Opcode },
8084     { Bad_Opcode },
8085     { Bad_Opcode },
8086     { Bad_Opcode },
8087   },
8088 };
8089
8090 static const struct dis386 vex_len_table[][2] = {
8091   /* VEX_LEN_10_P_1 */
8092   {
8093     { VEX_W_TABLE (VEX_W_10_P_1) },
8094     { VEX_W_TABLE (VEX_W_10_P_1) },
8095   },
8096
8097   /* VEX_LEN_10_P_3 */
8098   {
8099     { VEX_W_TABLE (VEX_W_10_P_3) },
8100     { VEX_W_TABLE (VEX_W_10_P_3) },
8101   },
8102
8103   /* VEX_LEN_11_P_1 */
8104   {
8105     { VEX_W_TABLE (VEX_W_11_P_1) },
8106     { VEX_W_TABLE (VEX_W_11_P_1) },
8107   },
8108
8109   /* VEX_LEN_11_P_3 */
8110   {
8111     { VEX_W_TABLE (VEX_W_11_P_3) },
8112     { VEX_W_TABLE (VEX_W_11_P_3) },
8113   },
8114
8115   /* VEX_LEN_12_P_0_M_0 */
8116   {
8117     { VEX_W_TABLE (VEX_W_12_P_0_M_0) },
8118   },
8119
8120   /* VEX_LEN_12_P_0_M_1 */
8121   {
8122     { VEX_W_TABLE (VEX_W_12_P_0_M_1) },
8123   },
8124
8125   /* VEX_LEN_12_P_2 */
8126   {
8127     { VEX_W_TABLE (VEX_W_12_P_2) },
8128   },
8129
8130   /* VEX_LEN_13_M_0 */
8131   {
8132     { VEX_W_TABLE (VEX_W_13_M_0) },
8133   },
8134
8135   /* VEX_LEN_16_P_0_M_0 */
8136   {
8137     { VEX_W_TABLE (VEX_W_16_P_0_M_0) },
8138   },
8139
8140   /* VEX_LEN_16_P_0_M_1 */
8141   {
8142     { VEX_W_TABLE (VEX_W_16_P_0_M_1) },
8143   },
8144
8145   /* VEX_LEN_16_P_2 */
8146   {
8147     { VEX_W_TABLE (VEX_W_16_P_2) },
8148   },
8149
8150   /* VEX_LEN_17_M_0 */
8151   {
8152     { VEX_W_TABLE (VEX_W_17_M_0) },
8153   },
8154
8155   /* VEX_LEN_2A_P_1 */
8156   {
8157     { "vcvtsi2ss%LQ",   { XMScalar, VexScalar, Ev } },
8158     { "vcvtsi2ss%LQ",   { XMScalar, VexScalar, Ev } },
8159   },
8160
8161   /* VEX_LEN_2A_P_3 */
8162   {
8163     { "vcvtsi2sd%LQ",   { XMScalar, VexScalar, Ev } },
8164     { "vcvtsi2sd%LQ",   { XMScalar, VexScalar, Ev } },
8165   },
8166
8167   /* VEX_LEN_2C_P_1 */
8168   {
8169     { "vcvttss2siY",    { Gv, EXdScalar } },
8170     { "vcvttss2siY",    { Gv, EXdScalar } },
8171   },
8172
8173   /* VEX_LEN_2C_P_3 */
8174   {
8175     { "vcvttsd2siY",    { Gv, EXqScalar } },
8176     { "vcvttsd2siY",    { Gv, EXqScalar } },
8177   },
8178
8179   /* VEX_LEN_2D_P_1 */
8180   {
8181     { "vcvtss2siY",     { Gv, EXdScalar } },
8182     { "vcvtss2siY",     { Gv, EXdScalar } },
8183   },
8184
8185   /* VEX_LEN_2D_P_3 */
8186   {
8187     { "vcvtsd2siY",     { Gv, EXqScalar } },
8188     { "vcvtsd2siY",     { Gv, EXqScalar } },
8189   },
8190
8191   /* VEX_LEN_2E_P_0 */
8192   {
8193     { VEX_W_TABLE (VEX_W_2E_P_0) },
8194     { VEX_W_TABLE (VEX_W_2E_P_0) },
8195   },
8196
8197   /* VEX_LEN_2E_P_2 */
8198   {
8199     { VEX_W_TABLE (VEX_W_2E_P_2) },
8200     { VEX_W_TABLE (VEX_W_2E_P_2) },
8201   },
8202
8203   /* VEX_LEN_2F_P_0 */
8204   {
8205     { VEX_W_TABLE (VEX_W_2F_P_0) },
8206     { VEX_W_TABLE (VEX_W_2F_P_0) },
8207   },
8208
8209   /* VEX_LEN_2F_P_2 */
8210   {
8211     { VEX_W_TABLE (VEX_W_2F_P_2) },
8212     { VEX_W_TABLE (VEX_W_2F_P_2) },
8213   },
8214
8215   /* VEX_LEN_51_P_1 */
8216   {
8217     { VEX_W_TABLE (VEX_W_51_P_1) },
8218     { VEX_W_TABLE (VEX_W_51_P_1) },
8219   },
8220
8221   /* VEX_LEN_51_P_3 */
8222   {
8223     { VEX_W_TABLE (VEX_W_51_P_3) },
8224     { VEX_W_TABLE (VEX_W_51_P_3) },
8225   },
8226
8227   /* VEX_LEN_52_P_1 */
8228   {
8229     { VEX_W_TABLE (VEX_W_52_P_1) },
8230     { VEX_W_TABLE (VEX_W_52_P_1) },
8231   },
8232
8233   /* VEX_LEN_53_P_1 */
8234   {
8235     { VEX_W_TABLE (VEX_W_53_P_1) },
8236     { VEX_W_TABLE (VEX_W_53_P_1) },
8237   },
8238
8239   /* VEX_LEN_58_P_1 */
8240   {
8241     { VEX_W_TABLE (VEX_W_58_P_1) },
8242     { VEX_W_TABLE (VEX_W_58_P_1) },
8243   },
8244
8245   /* VEX_LEN_58_P_3 */
8246   {
8247     { VEX_W_TABLE (VEX_W_58_P_3) },
8248     { VEX_W_TABLE (VEX_W_58_P_3) },
8249   },
8250
8251   /* VEX_LEN_59_P_1 */
8252   {
8253     { VEX_W_TABLE (VEX_W_59_P_1) },
8254     { VEX_W_TABLE (VEX_W_59_P_1) },
8255   },
8256
8257   /* VEX_LEN_59_P_3 */
8258   {
8259     { VEX_W_TABLE (VEX_W_59_P_3) },
8260     { VEX_W_TABLE (VEX_W_59_P_3) },
8261   },
8262
8263   /* VEX_LEN_5A_P_1 */
8264   {
8265     { VEX_W_TABLE (VEX_W_5A_P_1) },
8266     { VEX_W_TABLE (VEX_W_5A_P_1) },
8267   },
8268
8269   /* VEX_LEN_5A_P_3 */
8270   {
8271     { VEX_W_TABLE (VEX_W_5A_P_3) },
8272     { VEX_W_TABLE (VEX_W_5A_P_3) },
8273   },
8274
8275   /* VEX_LEN_5C_P_1 */
8276   {
8277     { VEX_W_TABLE (VEX_W_5C_P_1) },
8278     { VEX_W_TABLE (VEX_W_5C_P_1) },
8279   },
8280
8281   /* VEX_LEN_5C_P_3 */
8282   {
8283     { VEX_W_TABLE (VEX_W_5C_P_3) },
8284     { VEX_W_TABLE (VEX_W_5C_P_3) },
8285   },
8286
8287   /* VEX_LEN_5D_P_1 */
8288   {
8289     { VEX_W_TABLE (VEX_W_5D_P_1) },
8290     { VEX_W_TABLE (VEX_W_5D_P_1) },
8291   },
8292
8293   /* VEX_LEN_5D_P_3 */
8294   {
8295     { VEX_W_TABLE (VEX_W_5D_P_3) },
8296     { VEX_W_TABLE (VEX_W_5D_P_3) },
8297   },
8298
8299   /* VEX_LEN_5E_P_1 */
8300   {
8301     { VEX_W_TABLE (VEX_W_5E_P_1) },
8302     { VEX_W_TABLE (VEX_W_5E_P_1) },
8303   },
8304
8305   /* VEX_LEN_5E_P_3 */
8306   {
8307     { VEX_W_TABLE (VEX_W_5E_P_3) },
8308     { VEX_W_TABLE (VEX_W_5E_P_3) },
8309   },
8310
8311   /* VEX_LEN_5F_P_1 */
8312   {
8313     { VEX_W_TABLE (VEX_W_5F_P_1) },
8314     { VEX_W_TABLE (VEX_W_5F_P_1) },
8315   },
8316
8317   /* VEX_LEN_5F_P_3 */
8318   {
8319     { VEX_W_TABLE (VEX_W_5F_P_3) },
8320     { VEX_W_TABLE (VEX_W_5F_P_3) },
8321   },
8322
8323   /* VEX_LEN_60_P_2 */
8324   {
8325     { VEX_W_TABLE (VEX_W_60_P_2) },
8326   },
8327
8328   /* VEX_LEN_61_P_2 */
8329   {
8330     { VEX_W_TABLE (VEX_W_61_P_2) },
8331   },
8332
8333   /* VEX_LEN_62_P_2 */
8334   {
8335     { VEX_W_TABLE (VEX_W_62_P_2) },
8336   },
8337
8338   /* VEX_LEN_63_P_2 */
8339   {
8340     { VEX_W_TABLE (VEX_W_63_P_2) },
8341   },
8342
8343   /* VEX_LEN_64_P_2 */
8344   {
8345     { VEX_W_TABLE (VEX_W_64_P_2) },
8346   },
8347
8348   /* VEX_LEN_65_P_2 */
8349   {
8350     { VEX_W_TABLE (VEX_W_65_P_2) },
8351   },
8352
8353   /* VEX_LEN_66_P_2 */
8354   {
8355     { VEX_W_TABLE (VEX_W_66_P_2) },
8356   },
8357
8358   /* VEX_LEN_67_P_2 */
8359   {
8360     { VEX_W_TABLE (VEX_W_67_P_2) },
8361   },
8362
8363   /* VEX_LEN_68_P_2 */
8364   {
8365     { VEX_W_TABLE (VEX_W_68_P_2) },
8366   },
8367
8368   /* VEX_LEN_69_P_2 */
8369   {
8370     { VEX_W_TABLE (VEX_W_69_P_2) },
8371   },
8372
8373   /* VEX_LEN_6A_P_2 */
8374   {
8375     { VEX_W_TABLE (VEX_W_6A_P_2) },
8376   },
8377
8378   /* VEX_LEN_6B_P_2 */
8379   {
8380     { VEX_W_TABLE (VEX_W_6B_P_2) },
8381   },
8382
8383   /* VEX_LEN_6C_P_2 */
8384   {
8385     { VEX_W_TABLE (VEX_W_6C_P_2) },
8386   },
8387
8388   /* VEX_LEN_6D_P_2 */
8389   {
8390     { VEX_W_TABLE (VEX_W_6D_P_2) },
8391   },
8392
8393   /* VEX_LEN_6E_P_2 */
8394   {
8395     { "vmovK",          { XMScalar, Edq } },
8396     { "vmovK",          { XMScalar, Edq } },
8397   },
8398
8399   /* VEX_LEN_70_P_1 */
8400   {
8401     { VEX_W_TABLE (VEX_W_70_P_1) },
8402   },
8403
8404   /* VEX_LEN_70_P_2 */
8405   {
8406     { VEX_W_TABLE (VEX_W_70_P_2) },
8407   },
8408
8409   /* VEX_LEN_70_P_3 */
8410   {
8411     { VEX_W_TABLE (VEX_W_70_P_3) },
8412   },
8413
8414   /* VEX_LEN_71_R_2_P_2 */
8415   {
8416     { VEX_W_TABLE (VEX_W_71_R_2_P_2) },
8417   },
8418
8419   /* VEX_LEN_71_R_4_P_2 */
8420   {
8421     { VEX_W_TABLE (VEX_W_71_R_4_P_2) },
8422   },
8423
8424   /* VEX_LEN_71_R_6_P_2 */
8425   {
8426     { VEX_W_TABLE (VEX_W_71_R_6_P_2) },
8427   },
8428
8429   /* VEX_LEN_72_R_2_P_2 */
8430   {
8431     { VEX_W_TABLE (VEX_W_72_R_2_P_2) },
8432   },
8433
8434   /* VEX_LEN_72_R_4_P_2 */
8435   {
8436     { VEX_W_TABLE (VEX_W_72_R_4_P_2) },
8437   },
8438
8439   /* VEX_LEN_72_R_6_P_2 */
8440   {
8441     { VEX_W_TABLE (VEX_W_72_R_6_P_2) },
8442   },
8443
8444   /* VEX_LEN_73_R_2_P_2 */
8445   {
8446     { VEX_W_TABLE (VEX_W_73_R_2_P_2) },
8447   },
8448
8449   /* VEX_LEN_73_R_3_P_2 */
8450   {
8451     { VEX_W_TABLE (VEX_W_73_R_3_P_2) },
8452   },
8453
8454   /* VEX_LEN_73_R_6_P_2 */
8455   {
8456     { VEX_W_TABLE (VEX_W_73_R_6_P_2) },
8457   },
8458
8459   /* VEX_LEN_73_R_7_P_2 */
8460   {
8461     { VEX_W_TABLE (VEX_W_73_R_7_P_2) },
8462   },
8463
8464   /* VEX_LEN_74_P_2 */
8465   {
8466     { VEX_W_TABLE (VEX_W_74_P_2) },
8467   },
8468
8469   /* VEX_LEN_75_P_2 */
8470   {
8471     { VEX_W_TABLE (VEX_W_75_P_2) },
8472   },
8473
8474   /* VEX_LEN_76_P_2 */
8475   {
8476     { VEX_W_TABLE (VEX_W_76_P_2) },
8477   },
8478
8479   /* VEX_LEN_7E_P_1 */
8480   {
8481     { VEX_W_TABLE (VEX_W_7E_P_1) },
8482     { VEX_W_TABLE (VEX_W_7E_P_1) },
8483   },
8484
8485   /* VEX_LEN_7E_P_2 */
8486   {
8487     { "vmovK",          { Edq, XMScalar } },
8488     { "vmovK",          { Edq, XMScalar } },
8489   },
8490
8491   /* VEX_LEN_AE_R_2_M_0 */
8492   {
8493     { VEX_W_TABLE (VEX_W_AE_R_2_M_0) },
8494   },
8495
8496   /* VEX_LEN_AE_R_3_M_0 */
8497   {
8498     { VEX_W_TABLE (VEX_W_AE_R_3_M_0) },
8499   },
8500
8501   /* VEX_LEN_C2_P_1 */
8502   {
8503     { VEX_W_TABLE (VEX_W_C2_P_1) },
8504     { VEX_W_TABLE (VEX_W_C2_P_1) },
8505   },
8506
8507   /* VEX_LEN_C2_P_3 */
8508   {
8509     { VEX_W_TABLE (VEX_W_C2_P_3) },
8510     { VEX_W_TABLE (VEX_W_C2_P_3) },
8511   },
8512
8513   /* VEX_LEN_C4_P_2 */
8514   {
8515     { VEX_W_TABLE (VEX_W_C4_P_2) },
8516   },
8517
8518   /* VEX_LEN_C5_P_2 */
8519   {
8520     { VEX_W_TABLE (VEX_W_C5_P_2) },
8521   },
8522
8523   /* VEX_LEN_D1_P_2 */
8524   {
8525     { VEX_W_TABLE (VEX_W_D1_P_2) },
8526   },
8527
8528   /* VEX_LEN_D2_P_2 */
8529   {
8530     { VEX_W_TABLE (VEX_W_D2_P_2) },
8531   },
8532
8533   /* VEX_LEN_D3_P_2 */
8534   {
8535     { VEX_W_TABLE (VEX_W_D3_P_2) },
8536   },
8537
8538   /* VEX_LEN_D4_P_2 */
8539   {
8540     { VEX_W_TABLE (VEX_W_D4_P_2) },
8541   },
8542
8543   /* VEX_LEN_D5_P_2 */
8544   {
8545     { VEX_W_TABLE (VEX_W_D5_P_2) },
8546   },
8547
8548   /* VEX_LEN_D6_P_2 */
8549   {
8550     { VEX_W_TABLE (VEX_W_D6_P_2) },
8551     { VEX_W_TABLE (VEX_W_D6_P_2) },
8552   },
8553
8554   /* VEX_LEN_D7_P_2_M_1 */
8555   {
8556     { VEX_W_TABLE (VEX_W_D7_P_2_M_1) },
8557   },
8558
8559   /* VEX_LEN_D8_P_2 */
8560   {
8561     { VEX_W_TABLE (VEX_W_D8_P_2) },
8562   },
8563
8564   /* VEX_LEN_D9_P_2 */
8565   {
8566     { VEX_W_TABLE (VEX_W_D9_P_2) },
8567   },
8568
8569   /* VEX_LEN_DA_P_2 */
8570   {
8571     { VEX_W_TABLE (VEX_W_DA_P_2) },
8572   },
8573
8574   /* VEX_LEN_DB_P_2 */
8575   {
8576     { VEX_W_TABLE (VEX_W_DB_P_2) },
8577   },
8578
8579   /* VEX_LEN_DC_P_2 */
8580   {
8581     { VEX_W_TABLE (VEX_W_DC_P_2) },
8582   },
8583
8584   /* VEX_LEN_DD_P_2 */
8585   {
8586     { VEX_W_TABLE (VEX_W_DD_P_2) },
8587   },
8588
8589   /* VEX_LEN_DE_P_2 */
8590   {
8591     { VEX_W_TABLE (VEX_W_DE_P_2) },
8592   },
8593
8594   /* VEX_LEN_DF_P_2 */
8595   {
8596     { VEX_W_TABLE (VEX_W_DF_P_2) },
8597   },
8598
8599   /* VEX_LEN_E0_P_2 */
8600   {
8601     { VEX_W_TABLE (VEX_W_E0_P_2) },
8602   },
8603
8604   /* VEX_LEN_E1_P_2 */
8605   {
8606     { VEX_W_TABLE (VEX_W_E1_P_2) },
8607   },
8608
8609   /* VEX_LEN_E2_P_2 */
8610   {
8611     { VEX_W_TABLE (VEX_W_E2_P_2) },
8612   },
8613
8614   /* VEX_LEN_E3_P_2 */
8615   {
8616     { VEX_W_TABLE (VEX_W_E3_P_2) },
8617   },
8618
8619   /* VEX_LEN_E4_P_2 */
8620   {
8621     { VEX_W_TABLE (VEX_W_E4_P_2) },
8622   },
8623
8624   /* VEX_LEN_E5_P_2 */
8625   {
8626     { VEX_W_TABLE (VEX_W_E5_P_2) },
8627   },
8628
8629   /* VEX_LEN_E8_P_2 */
8630   {
8631     { VEX_W_TABLE (VEX_W_E8_P_2) },
8632   },
8633
8634   /* VEX_LEN_E9_P_2 */
8635   {
8636     { VEX_W_TABLE (VEX_W_E9_P_2) },
8637   },
8638
8639   /* VEX_LEN_EA_P_2 */
8640   {
8641     { VEX_W_TABLE (VEX_W_EA_P_2) },
8642   },
8643
8644   /* VEX_LEN_EB_P_2 */
8645   {
8646     { VEX_W_TABLE (VEX_W_EB_P_2) },
8647   },
8648
8649   /* VEX_LEN_EC_P_2 */
8650   {
8651     { VEX_W_TABLE (VEX_W_EC_P_2) },
8652   },
8653
8654   /* VEX_LEN_ED_P_2 */
8655   {
8656     { VEX_W_TABLE (VEX_W_ED_P_2) },
8657   },
8658
8659   /* VEX_LEN_EE_P_2 */
8660   {
8661     { VEX_W_TABLE (VEX_W_EE_P_2) },
8662   },
8663
8664   /* VEX_LEN_EF_P_2 */
8665   {
8666     { VEX_W_TABLE (VEX_W_EF_P_2) },
8667   },
8668
8669   /* VEX_LEN_F1_P_2 */
8670   {
8671     { VEX_W_TABLE (VEX_W_F1_P_2) },
8672   },
8673
8674   /* VEX_LEN_F2_P_2 */
8675   {
8676     { VEX_W_TABLE (VEX_W_F2_P_2) },
8677   },
8678
8679   /* VEX_LEN_F3_P_2 */
8680   {
8681     { VEX_W_TABLE (VEX_W_F3_P_2) },
8682   },
8683
8684   /* VEX_LEN_F4_P_2 */
8685   {
8686     { VEX_W_TABLE (VEX_W_F4_P_2) },
8687   },
8688
8689   /* VEX_LEN_F5_P_2 */
8690   {
8691     { VEX_W_TABLE (VEX_W_F5_P_2) },
8692   },
8693
8694   /* VEX_LEN_F6_P_2 */
8695   {
8696     { VEX_W_TABLE (VEX_W_F6_P_2) },
8697   },
8698
8699   /* VEX_LEN_F7_P_2 */
8700   {
8701     { VEX_W_TABLE (VEX_W_F7_P_2) },
8702   },
8703
8704   /* VEX_LEN_F8_P_2 */
8705   {
8706     { VEX_W_TABLE (VEX_W_F8_P_2) },
8707   },
8708
8709   /* VEX_LEN_F9_P_2 */
8710   {
8711     { VEX_W_TABLE (VEX_W_F9_P_2) },
8712   },
8713
8714   /* VEX_LEN_FA_P_2 */
8715   {
8716     { VEX_W_TABLE (VEX_W_FA_P_2) },
8717   },
8718
8719   /* VEX_LEN_FB_P_2 */
8720   {
8721     { VEX_W_TABLE (VEX_W_FB_P_2) },
8722   },
8723
8724   /* VEX_LEN_FC_P_2 */
8725   {
8726     { VEX_W_TABLE (VEX_W_FC_P_2) },
8727   },
8728
8729   /* VEX_LEN_FD_P_2 */
8730   {
8731     { VEX_W_TABLE (VEX_W_FD_P_2) },
8732   },
8733
8734   /* VEX_LEN_FE_P_2 */
8735   {
8736     { VEX_W_TABLE (VEX_W_FE_P_2) },
8737   },
8738
8739   /* VEX_LEN_3800_P_2 */
8740   {
8741     { VEX_W_TABLE (VEX_W_3800_P_2) },
8742   },
8743
8744   /* VEX_LEN_3801_P_2 */
8745   {
8746     { VEX_W_TABLE (VEX_W_3801_P_2) },
8747   },
8748
8749   /* VEX_LEN_3802_P_2 */
8750   {
8751     { VEX_W_TABLE (VEX_W_3802_P_2) },
8752   },
8753
8754   /* VEX_LEN_3803_P_2 */
8755   {
8756     { VEX_W_TABLE (VEX_W_3803_P_2) },
8757   },
8758
8759   /* VEX_LEN_3804_P_2 */
8760   {
8761     { VEX_W_TABLE (VEX_W_3804_P_2) },
8762   },
8763
8764   /* VEX_LEN_3805_P_2 */
8765   {
8766     { VEX_W_TABLE (VEX_W_3805_P_2) },
8767   },
8768
8769   /* VEX_LEN_3806_P_2 */
8770   {
8771     { VEX_W_TABLE (VEX_W_3806_P_2) },
8772   },
8773
8774   /* VEX_LEN_3807_P_2 */
8775   {
8776     { VEX_W_TABLE (VEX_W_3807_P_2) },
8777   },
8778
8779   /* VEX_LEN_3808_P_2 */
8780   {
8781     { VEX_W_TABLE (VEX_W_3808_P_2) },
8782   },
8783
8784   /* VEX_LEN_3809_P_2 */
8785   {
8786     { VEX_W_TABLE (VEX_W_3809_P_2) },
8787   },
8788
8789   /* VEX_LEN_380A_P_2 */
8790   {
8791     { VEX_W_TABLE (VEX_W_380A_P_2) },
8792   },
8793
8794   /* VEX_LEN_380B_P_2 */
8795   {
8796     { VEX_W_TABLE (VEX_W_380B_P_2) },
8797   },
8798
8799   /* VEX_LEN_3819_P_2_M_0 */
8800   {
8801     { Bad_Opcode },
8802     { VEX_W_TABLE (VEX_W_3819_P_2_M_0) },
8803   },
8804
8805   /* VEX_LEN_381A_P_2_M_0 */
8806   {
8807     { Bad_Opcode },
8808     { VEX_W_TABLE (VEX_W_381A_P_2_M_0) },
8809   },
8810
8811   /* VEX_LEN_381C_P_2 */
8812   {
8813     { VEX_W_TABLE (VEX_W_381C_P_2) },
8814   },
8815
8816   /* VEX_LEN_381D_P_2 */
8817   {
8818     { VEX_W_TABLE (VEX_W_381D_P_2) },
8819   },
8820
8821   /* VEX_LEN_381E_P_2 */
8822   {
8823     { VEX_W_TABLE (VEX_W_381E_P_2) },
8824   },
8825
8826   /* VEX_LEN_3820_P_2 */
8827   {
8828     { VEX_W_TABLE (VEX_W_3820_P_2) },
8829   },
8830
8831   /* VEX_LEN_3821_P_2 */
8832   {
8833     { VEX_W_TABLE (VEX_W_3821_P_2) },
8834   },
8835
8836   /* VEX_LEN_3822_P_2 */
8837   {
8838     { VEX_W_TABLE (VEX_W_3822_P_2) },
8839   },
8840
8841   /* VEX_LEN_3823_P_2 */
8842   {
8843     { VEX_W_TABLE (VEX_W_3823_P_2) },
8844   },
8845
8846   /* VEX_LEN_3824_P_2 */
8847   {
8848     { VEX_W_TABLE (VEX_W_3824_P_2) },
8849   },
8850
8851   /* VEX_LEN_3825_P_2 */
8852   {
8853     { VEX_W_TABLE (VEX_W_3825_P_2) },
8854   },
8855
8856   /* VEX_LEN_3828_P_2 */
8857   {
8858     { VEX_W_TABLE (VEX_W_3828_P_2) },
8859   },
8860
8861   /* VEX_LEN_3829_P_2 */
8862   {
8863     { VEX_W_TABLE (VEX_W_3829_P_2) },
8864   },
8865
8866   /* VEX_LEN_382A_P_2_M_0 */
8867   {
8868     { VEX_W_TABLE (VEX_W_382A_P_2_M_0) },
8869   },
8870
8871   /* VEX_LEN_382B_P_2 */
8872   {
8873     { VEX_W_TABLE (VEX_W_382B_P_2) },
8874   },
8875
8876   /* VEX_LEN_3830_P_2 */
8877   {
8878     { VEX_W_TABLE (VEX_W_3830_P_2) },
8879   },
8880
8881   /* VEX_LEN_3831_P_2 */
8882   {
8883     { VEX_W_TABLE (VEX_W_3831_P_2) },
8884   },
8885
8886   /* VEX_LEN_3832_P_2 */
8887   {
8888     { VEX_W_TABLE (VEX_W_3832_P_2) },
8889   },
8890
8891   /* VEX_LEN_3833_P_2 */
8892   {
8893     { VEX_W_TABLE (VEX_W_3833_P_2) },
8894   },
8895
8896   /* VEX_LEN_3834_P_2 */
8897   {
8898     { VEX_W_TABLE (VEX_W_3834_P_2) },
8899   },
8900
8901   /* VEX_LEN_3835_P_2 */
8902   {
8903     { VEX_W_TABLE (VEX_W_3835_P_2) },
8904   },
8905
8906   /* VEX_LEN_3837_P_2 */
8907   {
8908     { VEX_W_TABLE (VEX_W_3837_P_2) },
8909   },
8910
8911   /* VEX_LEN_3838_P_2 */
8912   {
8913     { VEX_W_TABLE (VEX_W_3838_P_2) },
8914   },
8915
8916   /* VEX_LEN_3839_P_2 */
8917   {
8918     { VEX_W_TABLE (VEX_W_3839_P_2) },
8919   },
8920
8921   /* VEX_LEN_383A_P_2 */
8922   {
8923     { VEX_W_TABLE (VEX_W_383A_P_2) },
8924   },
8925
8926   /* VEX_LEN_383B_P_2 */
8927   {
8928     { VEX_W_TABLE (VEX_W_383B_P_2) },
8929   },
8930
8931   /* VEX_LEN_383C_P_2 */
8932   {
8933     { VEX_W_TABLE (VEX_W_383C_P_2) },
8934   },
8935
8936   /* VEX_LEN_383D_P_2 */
8937   {
8938     { VEX_W_TABLE (VEX_W_383D_P_2) },
8939   },
8940
8941   /* VEX_LEN_383E_P_2 */
8942   {
8943     { VEX_W_TABLE (VEX_W_383E_P_2) },
8944   },
8945
8946   /* VEX_LEN_383F_P_2 */
8947   {
8948     { VEX_W_TABLE (VEX_W_383F_P_2) },
8949   },
8950
8951   /* VEX_LEN_3840_P_2 */
8952   {
8953     { VEX_W_TABLE (VEX_W_3840_P_2) },
8954   },
8955
8956   /* VEX_LEN_3841_P_2 */
8957   {
8958     { VEX_W_TABLE (VEX_W_3841_P_2) },
8959   },
8960
8961   /* VEX_LEN_38DB_P_2 */
8962   {
8963     { VEX_W_TABLE (VEX_W_38DB_P_2) },
8964   },
8965
8966   /* VEX_LEN_38DC_P_2 */
8967   {
8968     { VEX_W_TABLE (VEX_W_38DC_P_2) },
8969   },
8970
8971   /* VEX_LEN_38DD_P_2 */
8972   {
8973     { VEX_W_TABLE (VEX_W_38DD_P_2) },
8974   },
8975
8976   /* VEX_LEN_38DE_P_2 */
8977   {
8978     { VEX_W_TABLE (VEX_W_38DE_P_2) },
8979   },
8980
8981   /* VEX_LEN_38DF_P_2 */
8982   {
8983     { VEX_W_TABLE (VEX_W_38DF_P_2) },
8984   },
8985
8986   /* VEX_LEN_3A06_P_2 */
8987   {
8988     { Bad_Opcode },
8989     { VEX_W_TABLE (VEX_W_3A06_P_2) },
8990   },
8991
8992   /* VEX_LEN_3A0A_P_2 */
8993   {
8994     { VEX_W_TABLE (VEX_W_3A0A_P_2) },
8995     { VEX_W_TABLE (VEX_W_3A0A_P_2) },
8996   },
8997
8998   /* VEX_LEN_3A0B_P_2 */
8999   {
9000     { VEX_W_TABLE (VEX_W_3A0B_P_2) },
9001     { VEX_W_TABLE (VEX_W_3A0B_P_2) },
9002   },
9003
9004   /* VEX_LEN_3A0E_P_2 */
9005   {
9006     { VEX_W_TABLE (VEX_W_3A0E_P_2) },
9007   },
9008
9009   /* VEX_LEN_3A0F_P_2 */
9010   {
9011     { VEX_W_TABLE (VEX_W_3A0F_P_2) },
9012   },
9013
9014   /* VEX_LEN_3A14_P_2 */
9015   {
9016     { VEX_W_TABLE (VEX_W_3A14_P_2) },
9017   },
9018
9019   /* VEX_LEN_3A15_P_2 */
9020   {
9021     { VEX_W_TABLE (VEX_W_3A15_P_2) },
9022   },
9023
9024   /* VEX_LEN_3A16_P_2  */
9025   {
9026     { "vpextrK",        { Edq, XM, Ib } },
9027   },
9028
9029   /* VEX_LEN_3A17_P_2 */
9030   {
9031     { "vextractps",     { Edqd, XM, Ib } },
9032   },
9033
9034   /* VEX_LEN_3A18_P_2 */
9035   {
9036     { Bad_Opcode },
9037     { VEX_W_TABLE (VEX_W_3A18_P_2) },
9038   },
9039
9040   /* VEX_LEN_3A19_P_2 */
9041   {
9042     { Bad_Opcode },
9043     { VEX_W_TABLE (VEX_W_3A19_P_2) },
9044   },
9045
9046   /* VEX_LEN_3A20_P_2 */
9047   {
9048     { VEX_W_TABLE (VEX_W_3A20_P_2) },
9049   },
9050
9051   /* VEX_LEN_3A21_P_2 */
9052   {
9053     { VEX_W_TABLE (VEX_W_3A21_P_2) },
9054   },
9055
9056   /* VEX_LEN_3A22_P_2 */
9057   {
9058     { "vpinsrK",        { XM, Vex128, Edq, Ib } },
9059   },
9060
9061   /* VEX_LEN_3A41_P_2 */
9062   {
9063     { VEX_W_TABLE (VEX_W_3A41_P_2) },
9064   },
9065
9066   /* VEX_LEN_3A42_P_2 */
9067   {
9068     { VEX_W_TABLE (VEX_W_3A42_P_2) },
9069   },
9070
9071   /* VEX_LEN_3A44_P_2 */
9072   {
9073     { VEX_W_TABLE (VEX_W_3A44_P_2) },
9074   },
9075
9076   /* VEX_LEN_3A4C_P_2 */
9077   {
9078     { VEX_W_TABLE (VEX_W_3A4C_P_2) },
9079   },
9080
9081   /* VEX_LEN_3A60_P_2 */
9082   {
9083     { VEX_W_TABLE (VEX_W_3A60_P_2) },
9084   },
9085
9086   /* VEX_LEN_3A61_P_2 */
9087   {
9088     { VEX_W_TABLE (VEX_W_3A61_P_2) },
9089   },
9090
9091   /* VEX_LEN_3A62_P_2 */
9092   {
9093     { VEX_W_TABLE (VEX_W_3A62_P_2) },
9094   },
9095
9096   /* VEX_LEN_3A63_P_2 */
9097   {
9098     { VEX_W_TABLE (VEX_W_3A63_P_2) },
9099   },
9100
9101   /* VEX_LEN_3A6A_P_2 */
9102   {
9103     { "vfmaddss",       { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },
9104   },
9105
9106   /* VEX_LEN_3A6B_P_2 */
9107   {
9108     { "vfmaddsd",       { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },
9109   },
9110
9111   /* VEX_LEN_3A6E_P_2 */
9112   {
9113     { "vfmsubss",       { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },
9114   },
9115
9116   /* VEX_LEN_3A6F_P_2 */
9117   {
9118     { "vfmsubsd",       { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },
9119   },
9120
9121   /* VEX_LEN_3A7A_P_2 */
9122   {
9123     { "vfnmaddss",      { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },
9124   },
9125
9126   /* VEX_LEN_3A7B_P_2 */
9127   {
9128     { "vfnmaddsd",      { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },
9129   },
9130
9131   /* VEX_LEN_3A7E_P_2 */
9132   {
9133     { "vfnmsubss",      { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },
9134   },
9135
9136   /* VEX_LEN_3A7F_P_2 */
9137   {
9138     { "vfnmsubsd",      { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },
9139   },
9140
9141   /* VEX_LEN_3ADF_P_2 */
9142   {
9143     { VEX_W_TABLE (VEX_W_3ADF_P_2) },
9144   },
9145
9146   /* VEX_LEN_XOP_09_80 */
9147   {
9148     { "vfrczps",        { XM, EXxmm } },
9149     { "vfrczps",        { XM, EXymmq } },
9150   },
9151
9152   /* VEX_LEN_XOP_09_81 */
9153   {
9154     { "vfrczpd",        { XM, EXxmm } },
9155     { "vfrczpd",        { XM, EXymmq } },
9156   },
9157 };
9158
9159 static const struct dis386 vex_w_table[][2] = {
9160   {
9161     /* VEX_W_10_P_0 */
9162     { "vmovups",        { XM, EXx } },
9163   },
9164   {
9165     /* VEX_W_10_P_1 */
9166     { "vmovss",         { XMVexScalar, VexScalar, EXdScalar } },
9167   },
9168   {
9169     /* VEX_W_10_P_2 */
9170     { "vmovupd",        { XM, EXx } },
9171   },
9172   {
9173     /* VEX_W_10_P_3 */
9174     { "vmovsd",         { XMVexScalar, VexScalar, EXqScalar } },
9175   },
9176   {
9177     /* VEX_W_11_P_0 */
9178     { "vmovups",        { EXxS, XM } },
9179   },
9180   {
9181     /* VEX_W_11_P_1 */
9182     { "vmovss",         { EXdVexScalarS, VexScalar, XMScalar } },
9183   },
9184   {
9185     /* VEX_W_11_P_2 */
9186     { "vmovupd",        { EXxS, XM } },
9187   },
9188   {
9189     /* VEX_W_11_P_3 */
9190     { "vmovsd",         { EXqVexScalarS, VexScalar, XMScalar } },
9191   },
9192   {
9193     /* VEX_W_12_P_0_M_0 */
9194     { "vmovlps",        { XM, Vex128, EXq } },
9195   },
9196   {
9197     /* VEX_W_12_P_0_M_1 */
9198     { "vmovhlps",       { XM, Vex128, EXq } },
9199   },
9200   {
9201     /* VEX_W_12_P_1 */
9202     { "vmovsldup",      { XM, EXx } },
9203   },
9204   {
9205     /* VEX_W_12_P_2 */
9206     { "vmovlpd",        { XM, Vex128, EXq } },
9207   },
9208   {
9209     /* VEX_W_12_P_3 */
9210     { "vmovddup",       { XM, EXymmq } },
9211   },
9212   {
9213     /* VEX_W_13_M_0 */
9214     { "vmovlpX",        { EXq, XM } },
9215   },
9216   {
9217     /* VEX_W_14 */
9218     { "vunpcklpX",      { XM, Vex, EXx } },
9219   },
9220   {
9221     /* VEX_W_15 */
9222     { "vunpckhpX",      { XM, Vex, EXx } },
9223   },
9224   {
9225     /* VEX_W_16_P_0_M_0 */
9226     { "vmovhps",        { XM, Vex128, EXq } },
9227   },
9228   {
9229     /* VEX_W_16_P_0_M_1 */
9230     { "vmovlhps",       { XM, Vex128, EXq } },
9231   },
9232   {
9233     /* VEX_W_16_P_1 */
9234     { "vmovshdup",      { XM, EXx } },
9235   },
9236   {
9237     /* VEX_W_16_P_2 */
9238     { "vmovhpd",        { XM, Vex128, EXq } },
9239   },
9240   {
9241     /* VEX_W_17_M_0 */
9242     { "vmovhpX",        { EXq, XM } },
9243   },
9244   {
9245     /* VEX_W_28 */
9246     { "vmovapX",        { XM, EXx } },
9247   },
9248   {
9249     /* VEX_W_29 */
9250     { "vmovapX",        { EXxS, XM } },
9251   },
9252   {
9253     /* VEX_W_2B_M_0 */
9254     { "vmovntpX",       { Mx, XM } },
9255   },
9256   {
9257     /* VEX_W_2E_P_0 */
9258     { "vucomiss",       { XMScalar, EXdScalar } },
9259   },
9260   {
9261     /* VEX_W_2E_P_2 */
9262     { "vucomisd",       { XMScalar, EXqScalar } },
9263   },
9264   {
9265     /* VEX_W_2F_P_0 */
9266     { "vcomiss",        { XMScalar, EXdScalar } },
9267   },
9268   {
9269     /* VEX_W_2F_P_2 */
9270     { "vcomisd",        { XMScalar, EXqScalar } },
9271   },
9272   {
9273     /* VEX_W_50_M_0 */
9274     { "vmovmskpX",      { Gdq, XS } },
9275   },
9276   {
9277     /* VEX_W_51_P_0 */
9278     { "vsqrtps",        { XM, EXx } },
9279   },
9280   {
9281     /* VEX_W_51_P_1 */
9282     { "vsqrtss",        { XMScalar, VexScalar, EXdScalar } },
9283   },
9284   {
9285     /* VEX_W_51_P_2  */
9286     { "vsqrtpd",        { XM, EXx } },
9287   },
9288   {
9289     /* VEX_W_51_P_3 */
9290     { "vsqrtsd",        { XMScalar, VexScalar, EXqScalar } },
9291   },
9292   {
9293     /* VEX_W_52_P_0 */
9294     { "vrsqrtps",       { XM, EXx } },
9295   },
9296   {
9297     /* VEX_W_52_P_1 */
9298     { "vrsqrtss",       { XMScalar, VexScalar, EXdScalar } },
9299   },
9300   {
9301     /* VEX_W_53_P_0  */
9302     { "vrcpps",         { XM, EXx } },
9303   },
9304   {
9305     /* VEX_W_53_P_1  */
9306     { "vrcpss",         { XMScalar, VexScalar, EXdScalar } },
9307   },
9308   {
9309     /* VEX_W_58_P_0  */
9310     { "vaddps",         { XM, Vex, EXx } },
9311   },
9312   {
9313     /* VEX_W_58_P_1  */
9314     { "vaddss",         { XMScalar, VexScalar, EXdScalar } },
9315   },
9316   {
9317     /* VEX_W_58_P_2  */
9318     { "vaddpd",         { XM, Vex, EXx } },
9319   },
9320   {
9321     /* VEX_W_58_P_3  */
9322     { "vaddsd",         { XMScalar, VexScalar, EXqScalar } },
9323   },
9324   {
9325     /* VEX_W_59_P_0  */
9326     { "vmulps",         { XM, Vex, EXx } },
9327   },
9328   {
9329     /* VEX_W_59_P_1  */
9330     { "vmulss",         { XMScalar, VexScalar, EXdScalar } },
9331   },
9332   {
9333     /* VEX_W_59_P_2  */
9334     { "vmulpd",         { XM, Vex, EXx } },
9335   },
9336   {
9337     /* VEX_W_59_P_3  */
9338     { "vmulsd",         { XMScalar, VexScalar, EXqScalar } },
9339   },
9340   {
9341     /* VEX_W_5A_P_0  */
9342     { "vcvtps2pd",      { XM, EXxmmq } },
9343   },
9344   {
9345     /* VEX_W_5A_P_1  */
9346     { "vcvtss2sd",      { XMScalar, VexScalar, EXdScalar } },
9347   },
9348   {
9349     /* VEX_W_5A_P_3  */
9350     { "vcvtsd2ss",      { XMScalar, VexScalar, EXqScalar } },
9351   },
9352   {
9353     /* VEX_W_5B_P_0  */
9354     { "vcvtdq2ps",      { XM, EXx } },
9355   },
9356   {
9357     /* VEX_W_5B_P_1  */
9358     { "vcvttps2dq",     { XM, EXx } },
9359   },
9360   {
9361     /* VEX_W_5B_P_2  */
9362     { "vcvtps2dq",      { XM, EXx } },
9363   },
9364   {
9365     /* VEX_W_5C_P_0  */
9366     { "vsubps",         { XM, Vex, EXx } },
9367   },
9368   {
9369     /* VEX_W_5C_P_1  */
9370     { "vsubss",         { XMScalar, VexScalar, EXdScalar } },
9371   },
9372   {
9373     /* VEX_W_5C_P_2  */
9374     { "vsubpd",         { XM, Vex, EXx } },
9375   },
9376   {
9377     /* VEX_W_5C_P_3  */
9378     { "vsubsd",         { XMScalar, VexScalar, EXqScalar } },
9379   },
9380   {
9381     /* VEX_W_5D_P_0  */
9382     { "vminps",         { XM, Vex, EXx } },
9383   },
9384   {
9385     /* VEX_W_5D_P_1  */
9386     { "vminss",         { XMScalar, VexScalar, EXdScalar } },
9387   },
9388   {
9389     /* VEX_W_5D_P_2  */
9390     { "vminpd",         { XM, Vex, EXx } },
9391   },
9392   {
9393     /* VEX_W_5D_P_3  */
9394     { "vminsd",         { XMScalar, VexScalar, EXqScalar } },
9395   },
9396   {
9397     /* VEX_W_5E_P_0  */
9398     { "vdivps",         { XM, Vex, EXx } },
9399   },
9400   {
9401     /* VEX_W_5E_P_1  */
9402     { "vdivss",         { XMScalar, VexScalar, EXdScalar } },
9403   },
9404   {
9405     /* VEX_W_5E_P_2  */
9406     { "vdivpd",         { XM, Vex, EXx } },
9407   },
9408   {
9409     /* VEX_W_5E_P_3  */
9410     { "vdivsd",         { XMScalar, VexScalar, EXqScalar } },
9411   },
9412   {
9413     /* VEX_W_5F_P_0  */
9414     { "vmaxps",         { XM, Vex, EXx } },
9415   },
9416   {
9417     /* VEX_W_5F_P_1  */
9418     { "vmaxss",         { XMScalar, VexScalar, EXdScalar } },
9419   },
9420   {
9421     /* VEX_W_5F_P_2  */
9422     { "vmaxpd",         { XM, Vex, EXx } },
9423   },
9424   {
9425     /* VEX_W_5F_P_3  */
9426     { "vmaxsd",         { XMScalar, VexScalar, EXqScalar } },
9427   },
9428   {
9429     /* VEX_W_60_P_2  */
9430     { "vpunpcklbw",     { XM, Vex128, EXx } },
9431   },
9432   {
9433     /* VEX_W_61_P_2  */
9434     { "vpunpcklwd",     { XM, Vex128, EXx } },
9435   },
9436   {
9437     /* VEX_W_62_P_2  */
9438     { "vpunpckldq",     { XM, Vex128, EXx } },
9439   },
9440   {
9441     /* VEX_W_63_P_2  */
9442     { "vpacksswb",      { XM, Vex128, EXx } },
9443   },
9444   {
9445     /* VEX_W_64_P_2  */
9446     { "vpcmpgtb",       { XM, Vex128, EXx } },
9447   },
9448   {
9449     /* VEX_W_65_P_2  */
9450     { "vpcmpgtw",       { XM, Vex128, EXx } },
9451   },
9452   {
9453     /* VEX_W_66_P_2  */
9454     { "vpcmpgtd",       { XM, Vex128, EXx } },
9455   },
9456   {
9457     /* VEX_W_67_P_2  */
9458     { "vpackuswb",      { XM, Vex128, EXx } },
9459   },
9460   {
9461     /* VEX_W_68_P_2  */
9462     { "vpunpckhbw",     { XM, Vex128, EXx } },
9463   },
9464   {
9465     /* VEX_W_69_P_2  */
9466     { "vpunpckhwd",     { XM, Vex128, EXx } },
9467   },
9468   {
9469     /* VEX_W_6A_P_2  */
9470     { "vpunpckhdq",     { XM, Vex128, EXx } },
9471   },
9472   {
9473     /* VEX_W_6B_P_2  */
9474     { "vpackssdw",      { XM, Vex128, EXx } },
9475   },
9476   {
9477     /* VEX_W_6C_P_2  */
9478     { "vpunpcklqdq",    { XM, Vex128, EXx } },
9479   },
9480   {
9481     /* VEX_W_6D_P_2  */
9482     { "vpunpckhqdq",    { XM, Vex128, EXx } },
9483   },
9484   {
9485     /* VEX_W_6F_P_1  */
9486     { "vmovdqu",        { XM, EXx } },
9487   },
9488   {
9489     /* VEX_W_6F_P_2  */
9490     { "vmovdqa",        { XM, EXx } },
9491   },
9492   {
9493     /* VEX_W_70_P_1 */
9494     { "vpshufhw",       { XM, EXx, Ib } },
9495   },
9496   {
9497     /* VEX_W_70_P_2 */
9498     { "vpshufd",        { XM, EXx, Ib } },
9499   },
9500   {
9501     /* VEX_W_70_P_3 */
9502     { "vpshuflw",       { XM, EXx, Ib } },
9503   },
9504   {
9505     /* VEX_W_71_R_2_P_2  */
9506     { "vpsrlw",         { Vex128, XS, Ib } },
9507   },
9508   {
9509     /* VEX_W_71_R_4_P_2  */
9510     { "vpsraw",         { Vex128, XS, Ib } },
9511   },
9512   {
9513     /* VEX_W_71_R_6_P_2  */
9514     { "vpsllw",         { Vex128, XS, Ib } },
9515   },
9516   {
9517     /* VEX_W_72_R_2_P_2  */
9518     { "vpsrld",         { Vex128, XS, Ib } },
9519   },
9520   {
9521     /* VEX_W_72_R_4_P_2  */
9522     { "vpsrad",         { Vex128, XS, Ib } },
9523   },
9524   {
9525     /* VEX_W_72_R_6_P_2  */
9526     { "vpslld",         { Vex128, XS, Ib } },
9527   },
9528   {
9529     /* VEX_W_73_R_2_P_2  */
9530     { "vpsrlq",         { Vex128, XS, Ib } },
9531   },
9532   {
9533     /* VEX_W_73_R_3_P_2  */
9534     { "vpsrldq",        { Vex128, XS, Ib } },
9535   },
9536   {
9537     /* VEX_W_73_R_6_P_2  */
9538     { "vpsllq",         { Vex128, XS, Ib } },
9539   },
9540   {
9541     /* VEX_W_73_R_7_P_2  */
9542     { "vpslldq",        { Vex128, XS, Ib } },
9543   },
9544   {
9545     /* VEX_W_74_P_2 */
9546     { "vpcmpeqb",       { XM, Vex128, EXx } },
9547   },
9548   {
9549     /* VEX_W_75_P_2 */
9550     { "vpcmpeqw",       { XM, Vex128, EXx } },
9551   },
9552   {
9553     /* VEX_W_76_P_2 */
9554     { "vpcmpeqd",       { XM, Vex128, EXx } },
9555   },
9556   {
9557     /* VEX_W_77_P_0 */
9558     { "",               { VZERO } },
9559   },
9560   {
9561     /* VEX_W_7C_P_2 */
9562     { "vhaddpd",        { XM, Vex, EXx } },
9563   },
9564   {
9565     /* VEX_W_7C_P_3 */
9566     { "vhaddps",        { XM, Vex, EXx } },
9567   },
9568   {
9569     /* VEX_W_7D_P_2 */
9570     { "vhsubpd",        { XM, Vex, EXx } },
9571   },
9572   {
9573     /* VEX_W_7D_P_3 */
9574     { "vhsubps",        { XM, Vex, EXx } },
9575   },
9576   {
9577     /* VEX_W_7E_P_1 */
9578     { "vmovq",          { XMScalar, EXqScalar } },
9579   },
9580   {
9581     /* VEX_W_7F_P_1 */
9582     { "vmovdqu",        { EXxS, XM } },
9583   },
9584   {
9585     /* VEX_W_7F_P_2 */
9586     { "vmovdqa",        { EXxS, XM } },
9587   },
9588   {
9589     /* VEX_W_AE_R_2_M_0 */
9590     { "vldmxcsr",       { Md } },
9591   },
9592   {
9593     /* VEX_W_AE_R_3_M_0 */
9594     { "vstmxcsr",       { Md } },
9595   },
9596   {
9597     /* VEX_W_C2_P_0 */
9598     { "vcmpps",         { XM, Vex, EXx, VCMP } },
9599   },
9600   {
9601     /* VEX_W_C2_P_1 */
9602     { "vcmpss",         { XMScalar, VexScalar, EXdScalar, VCMP } },
9603   },
9604   {
9605     /* VEX_W_C2_P_2 */
9606     { "vcmppd",         { XM, Vex, EXx, VCMP } },
9607   },
9608   {
9609     /* VEX_W_C2_P_3 */
9610     { "vcmpsd",         { XMScalar, VexScalar, EXqScalar, VCMP } },
9611   },
9612   {
9613     /* VEX_W_C4_P_2 */
9614     { "vpinsrw",        { XM, Vex128, Edqw, Ib } },
9615   },
9616   {
9617     /* VEX_W_C5_P_2 */
9618     { "vpextrw",        { Gdq, XS, Ib } },
9619   },
9620   {
9621     /* VEX_W_D0_P_2 */
9622     { "vaddsubpd",      { XM, Vex, EXx } },
9623   },
9624   {
9625     /* VEX_W_D0_P_3 */
9626     { "vaddsubps",      { XM, Vex, EXx } },
9627   },
9628   {
9629     /* VEX_W_D1_P_2 */
9630     { "vpsrlw",         { XM, Vex128, EXx } },
9631   },
9632   {
9633     /* VEX_W_D2_P_2 */
9634     { "vpsrld",         { XM, Vex128, EXx } },
9635   },
9636   {
9637     /* VEX_W_D3_P_2 */
9638     { "vpsrlq",         { XM, Vex128, EXx } },
9639   },
9640   {
9641     /* VEX_W_D4_P_2 */
9642     { "vpaddq",         { XM, Vex128, EXx } },
9643   },
9644   {
9645     /* VEX_W_D5_P_2 */
9646     { "vpmullw",        { XM, Vex128, EXx } },
9647   },
9648   {
9649     /* VEX_W_D6_P_2 */
9650     { "vmovq",          { EXqScalarS, XMScalar } },
9651   },
9652   {
9653     /* VEX_W_D7_P_2_M_1 */
9654     { "vpmovmskb",      { Gdq, XS } },
9655   },
9656   {
9657     /* VEX_W_D8_P_2 */
9658     { "vpsubusb",       { XM, Vex128, EXx } },
9659   },
9660   {
9661     /* VEX_W_D9_P_2 */
9662     { "vpsubusw",       { XM, Vex128, EXx } },
9663   },
9664   {
9665     /* VEX_W_DA_P_2 */
9666     { "vpminub",        { XM, Vex128, EXx } },
9667   },
9668   {
9669     /* VEX_W_DB_P_2 */
9670     { "vpand",          { XM, Vex128, EXx } },
9671   },
9672   {
9673     /* VEX_W_DC_P_2 */
9674     { "vpaddusb",       { XM, Vex128, EXx } },
9675   },
9676   {
9677     /* VEX_W_DD_P_2 */
9678     { "vpaddusw",       { XM, Vex128, EXx } },
9679   },
9680   {
9681     /* VEX_W_DE_P_2 */
9682     { "vpmaxub",        { XM, Vex128, EXx } },
9683   },
9684   {
9685     /* VEX_W_DF_P_2 */
9686     { "vpandn",         { XM, Vex128, EXx } },
9687   },
9688   {
9689     /* VEX_W_E0_P_2  */
9690     { "vpavgb",         { XM, Vex128, EXx } },
9691   },
9692   {
9693     /* VEX_W_E1_P_2  */
9694     { "vpsraw",         { XM, Vex128, EXx } },
9695   },
9696   {
9697     /* VEX_W_E2_P_2  */
9698     { "vpsrad",         { XM, Vex128, EXx } },
9699   },
9700   {
9701     /* VEX_W_E3_P_2  */
9702     { "vpavgw",         { XM, Vex128, EXx } },
9703   },
9704   {
9705     /* VEX_W_E4_P_2  */
9706     { "vpmulhuw",       { XM, Vex128, EXx } },
9707   },
9708   {
9709     /* VEX_W_E5_P_2  */
9710     { "vpmulhw",        { XM, Vex128, EXx } },
9711   },
9712   {
9713     /* VEX_W_E6_P_1  */
9714     { "vcvtdq2pd",      { XM, EXxmmq } },
9715   },
9716   {
9717     /* VEX_W_E6_P_2  */
9718     { "vcvttpd2dq%XY",  { XMM, EXx } },
9719   },
9720   {
9721     /* VEX_W_E6_P_3  */
9722     { "vcvtpd2dq%XY",   { XMM, EXx } },
9723   },
9724   {
9725     /* VEX_W_E7_P_2_M_0 */
9726     { "vmovntdq",       { Mx, XM } },
9727   },
9728   {
9729     /* VEX_W_E8_P_2  */
9730     { "vpsubsb",        { XM, Vex128, EXx } },
9731   },
9732   {
9733     /* VEX_W_E9_P_2  */
9734     { "vpsubsw",        { XM, Vex128, EXx } },
9735   },
9736   {
9737     /* VEX_W_EA_P_2  */
9738     { "vpminsw",        { XM, Vex128, EXx } },
9739   },
9740   {
9741     /* VEX_W_EB_P_2  */
9742     { "vpor",           { XM, Vex128, EXx } },
9743   },
9744   {
9745     /* VEX_W_EC_P_2  */
9746     { "vpaddsb",        { XM, Vex128, EXx } },
9747   },
9748   {
9749     /* VEX_W_ED_P_2  */
9750     { "vpaddsw",        { XM, Vex128, EXx } },
9751   },
9752   {
9753     /* VEX_W_EE_P_2  */
9754     { "vpmaxsw",        { XM, Vex128, EXx } },
9755   },
9756   {
9757     /* VEX_W_EF_P_2  */
9758     { "vpxor",          { XM, Vex128, EXx } },
9759   },
9760   {
9761     /* VEX_W_F0_P_3_M_0 */
9762     { "vlddqu",         { XM, M } },
9763   },
9764   {
9765     /* VEX_W_F1_P_2 */
9766     { "vpsllw",         { XM, Vex128, EXx } },
9767   },
9768   {
9769     /* VEX_W_F2_P_2 */
9770     { "vpslld",         { XM, Vex128, EXx } },
9771   },
9772   {
9773     /* VEX_W_F3_P_2 */
9774     { "vpsllq",         { XM, Vex128, EXx } },
9775   },
9776   {
9777     /* VEX_W_F4_P_2 */
9778     { "vpmuludq",       { XM, Vex128, EXx } },
9779   },
9780   {
9781     /* VEX_W_F5_P_2 */
9782     { "vpmaddwd",       { XM, Vex128, EXx } },
9783   },
9784   {
9785     /* VEX_W_F6_P_2 */
9786     { "vpsadbw",        { XM, Vex128, EXx } },
9787   },
9788   {
9789     /* VEX_W_F7_P_2 */
9790     { "vmaskmovdqu",    { XM, XS } },
9791   },
9792   {
9793     /* VEX_W_F8_P_2 */
9794     { "vpsubb",         { XM, Vex128, EXx } },
9795   },
9796   {
9797     /* VEX_W_F9_P_2 */
9798     { "vpsubw",         { XM, Vex128, EXx } },
9799   },
9800   {
9801     /* VEX_W_FA_P_2 */
9802     { "vpsubd",         { XM, Vex128, EXx } },
9803   },
9804   {
9805     /* VEX_W_FB_P_2 */
9806     { "vpsubq",         { XM, Vex128, EXx } },
9807   },
9808   {
9809     /* VEX_W_FC_P_2 */
9810     { "vpaddb",         { XM, Vex128, EXx } },
9811   },
9812   {
9813     /* VEX_W_FD_P_2 */
9814     { "vpaddw",         { XM, Vex128, EXx } },
9815   },
9816   {
9817     /* VEX_W_FE_P_2 */
9818     { "vpaddd",         { XM, Vex128, EXx } },
9819   },
9820   {
9821     /* VEX_W_3800_P_2  */
9822     { "vpshufb",        { XM, Vex128, EXx } },
9823   },
9824   {
9825     /* VEX_W_3801_P_2  */
9826     { "vphaddw",        { XM, Vex128, EXx } },
9827   },
9828   {
9829     /* VEX_W_3802_P_2  */
9830     { "vphaddd",        { XM, Vex128, EXx } },
9831   },
9832   {
9833     /* VEX_W_3803_P_2  */
9834     { "vphaddsw",       { XM, Vex128, EXx } },
9835   },
9836   {
9837     /* VEX_W_3804_P_2  */
9838     { "vpmaddubsw",     { XM, Vex128, EXx } },
9839   },
9840   {
9841     /* VEX_W_3805_P_2  */
9842     { "vphsubw",        { XM, Vex128, EXx } },
9843   },
9844   {
9845     /* VEX_W_3806_P_2  */
9846     { "vphsubd",        { XM, Vex128, EXx } },
9847   },
9848   {
9849     /* VEX_W_3807_P_2  */
9850     { "vphsubsw",       { XM, Vex128, EXx } },
9851   },
9852   {
9853     /* VEX_W_3808_P_2  */
9854     { "vpsignb",        { XM, Vex128, EXx } },
9855   },
9856   {
9857     /* VEX_W_3809_P_2  */
9858     { "vpsignw",        { XM, Vex128, EXx } },
9859   },
9860   {
9861     /* VEX_W_380A_P_2  */
9862     { "vpsignd",        { XM, Vex128, EXx } },
9863   },
9864   {
9865     /* VEX_W_380B_P_2  */
9866     { "vpmulhrsw",      { XM, Vex128, EXx } },
9867   },
9868   {
9869     /* VEX_W_380C_P_2  */
9870     { "vpermilps",      { XM, Vex, EXx } },
9871   },
9872   {
9873     /* VEX_W_380D_P_2  */
9874     { "vpermilpd",      { XM, Vex, EXx } },
9875   },
9876   {
9877     /* VEX_W_380E_P_2  */
9878     { "vtestps",        { XM, EXx } },
9879   },
9880   {
9881     /* VEX_W_380F_P_2  */
9882     { "vtestpd",        { XM, EXx } },
9883   },
9884   {
9885     /* VEX_W_3817_P_2 */
9886     { "vptest",         { XM, EXx } },
9887   },
9888   {
9889     /* VEX_W_3818_P_2_M_0 */
9890     { "vbroadcastss",   { XM, Md } },
9891   },
9892   {
9893     /* VEX_W_3819_P_2_M_0 */
9894     { "vbroadcastsd",   { XM, Mq } },
9895   },
9896   {
9897     /* VEX_W_381A_P_2_M_0 */
9898     { "vbroadcastf128", { XM, Mxmm } },
9899   },
9900   {
9901     /* VEX_W_381C_P_2 */
9902     { "vpabsb",         { XM, EXx } },
9903   },
9904   {
9905     /* VEX_W_381D_P_2 */
9906     { "vpabsw",         { XM, EXx } },
9907   },
9908   {
9909     /* VEX_W_381E_P_2 */
9910     { "vpabsd",         { XM, EXx } },
9911   },
9912   {
9913     /* VEX_W_3820_P_2 */
9914     { "vpmovsxbw",      { XM, EXq } },
9915   },
9916   {
9917     /* VEX_W_3821_P_2 */
9918     { "vpmovsxbd",      { XM, EXd } },
9919   },
9920   {
9921     /* VEX_W_3822_P_2 */
9922     { "vpmovsxbq",      { XM, EXw } },
9923   },
9924   {
9925     /* VEX_W_3823_P_2 */
9926     { "vpmovsxwd",      { XM, EXq } },
9927   },
9928   {
9929     /* VEX_W_3824_P_2 */
9930     { "vpmovsxwq",      { XM, EXd } },
9931   },
9932   {
9933     /* VEX_W_3825_P_2 */
9934     { "vpmovsxdq",      { XM, EXq } },
9935   },
9936   {
9937     /* VEX_W_3828_P_2 */
9938     { "vpmuldq",        { XM, Vex128, EXx } },
9939   },
9940   {
9941     /* VEX_W_3829_P_2 */
9942     { "vpcmpeqq",       { XM, Vex128, EXx } },
9943   },
9944   {
9945     /* VEX_W_382A_P_2_M_0 */
9946     { "vmovntdqa",      { XM, Mx } },
9947   },
9948   {
9949     /* VEX_W_382B_P_2 */
9950     { "vpackusdw",      { XM, Vex128, EXx } },
9951   },
9952   {
9953     /* VEX_W_382C_P_2_M_0 */
9954     { "vmaskmovps",     { XM, Vex, Mx } },
9955   },
9956   {
9957     /* VEX_W_382D_P_2_M_0 */
9958     { "vmaskmovpd",     { XM, Vex, Mx } },
9959   },
9960   {
9961     /* VEX_W_382E_P_2_M_0 */
9962     { "vmaskmovps",     { Mx, Vex, XM } },
9963   },
9964   {
9965     /* VEX_W_382F_P_2_M_0 */
9966     { "vmaskmovpd",     { Mx, Vex, XM } },
9967   },
9968   {
9969     /* VEX_W_3830_P_2 */
9970     { "vpmovzxbw",      { XM, EXq } },
9971   },
9972   {
9973     /* VEX_W_3831_P_2 */
9974     { "vpmovzxbd",      { XM, EXd } },
9975   },
9976   {
9977     /* VEX_W_3832_P_2 */
9978     { "vpmovzxbq",      { XM, EXw } },
9979   },
9980   {
9981     /* VEX_W_3833_P_2 */
9982     { "vpmovzxwd",      { XM, EXq } },
9983   },
9984   {
9985     /* VEX_W_3834_P_2 */
9986     { "vpmovzxwq",      { XM, EXd } },
9987   },
9988   {
9989     /* VEX_W_3835_P_2 */
9990     { "vpmovzxdq",      { XM, EXq } },
9991   },
9992   {
9993     /* VEX_W_3837_P_2 */
9994     { "vpcmpgtq",       { XM, Vex128, EXx } },
9995   },
9996   {
9997     /* VEX_W_3838_P_2 */
9998     { "vpminsb",        { XM, Vex128, EXx } },
9999   },
10000   {
10001     /* VEX_W_3839_P_2 */
10002     { "vpminsd",        { XM, Vex128, EXx } },
10003   },
10004   {
10005     /* VEX_W_383A_P_2 */
10006     { "vpminuw",        { XM, Vex128, EXx } },
10007   },
10008   {
10009     /* VEX_W_383B_P_2 */
10010     { "vpminud",        { XM, Vex128, EXx } },
10011   },
10012   {
10013     /* VEX_W_383C_P_2 */
10014     { "vpmaxsb",        { XM, Vex128, EXx } },
10015   },
10016   {
10017     /* VEX_W_383D_P_2 */
10018     { "vpmaxsd",        { XM, Vex128, EXx } },
10019   },
10020   {
10021     /* VEX_W_383E_P_2 */
10022     { "vpmaxuw",        { XM, Vex128, EXx } },
10023   },
10024   {
10025     /* VEX_W_383F_P_2 */
10026     { "vpmaxud",        { XM, Vex128, EXx } },
10027   },
10028   {
10029     /* VEX_W_3840_P_2 */
10030     { "vpmulld",        { XM, Vex128, EXx } },
10031   },
10032   {
10033     /* VEX_W_3841_P_2 */
10034     { "vphminposuw",    { XM, EXx } },
10035   },
10036   {
10037     /* VEX_W_38DB_P_2 */
10038     { "vaesimc",        { XM, EXx } },
10039   },
10040   {
10041     /* VEX_W_38DC_P_2 */
10042     { "vaesenc",        { XM, Vex128, EXx } },
10043   },
10044   {
10045     /* VEX_W_38DD_P_2 */
10046     { "vaesenclast",    { XM, Vex128, EXx } },
10047   },
10048   {
10049     /* VEX_W_38DE_P_2 */
10050     { "vaesdec",        { XM, Vex128, EXx } },
10051   },
10052   {
10053     /* VEX_W_38DF_P_2 */
10054     { "vaesdeclast",    { XM, Vex128, EXx } },
10055   },
10056   {
10057     /* VEX_W_3A04_P_2 */
10058     { "vpermilps",      { XM, EXx, Ib } },
10059   },
10060   {
10061     /* VEX_W_3A05_P_2 */
10062     { "vpermilpd",      { XM, EXx, Ib } },
10063   },
10064   {
10065     /* VEX_W_3A06_P_2 */
10066     { "vperm2f128",     { XM, Vex256, EXx, Ib } },
10067   },
10068   {
10069     /* VEX_W_3A08_P_2 */
10070     { "vroundps",       { XM, EXx, Ib } },
10071   },
10072   {
10073     /* VEX_W_3A09_P_2 */
10074     { "vroundpd",       { XM, EXx, Ib } },
10075   },
10076   {
10077     /* VEX_W_3A0A_P_2 */
10078     { "vroundss",       { XMScalar, VexScalar, EXdScalar, Ib } },
10079   },
10080   {
10081     /* VEX_W_3A0B_P_2 */
10082     { "vroundsd",       { XMScalar, VexScalar, EXqScalar, Ib } },
10083   },
10084   {
10085     /* VEX_W_3A0C_P_2 */
10086     { "vblendps",       { XM, Vex, EXx, Ib } },
10087   },
10088   {
10089     /* VEX_W_3A0D_P_2 */
10090     { "vblendpd",       { XM, Vex, EXx, Ib } },
10091   },
10092   {
10093     /* VEX_W_3A0E_P_2 */
10094     { "vpblendw",       { XM, Vex128, EXx, Ib } },
10095   },
10096   {
10097     /* VEX_W_3A0F_P_2 */
10098     { "vpalignr",       { XM, Vex128, EXx, Ib } },
10099   },
10100   {
10101     /* VEX_W_3A14_P_2 */
10102     { "vpextrb",        { Edqb, XM, Ib } },
10103   },
10104   {
10105     /* VEX_W_3A15_P_2 */
10106     { "vpextrw",        { Edqw, XM, Ib } },
10107   },
10108   {
10109     /* VEX_W_3A18_P_2 */
10110     { "vinsertf128",    { XM, Vex256, EXxmm, Ib } },
10111   },
10112   {
10113     /* VEX_W_3A19_P_2 */
10114     { "vextractf128",   { EXxmm, XM, Ib } },
10115   },
10116   {
10117     /* VEX_W_3A20_P_2 */
10118     { "vpinsrb",        { XM, Vex128, Edqb, Ib } },
10119   },
10120   {
10121     /* VEX_W_3A21_P_2 */
10122     { "vinsertps",      { XM, Vex128, EXd, Ib } },
10123   },
10124   {
10125     /* VEX_W_3A40_P_2 */
10126     { "vdpps",          { XM, Vex, EXx, Ib } },
10127   },
10128   {
10129     /* VEX_W_3A41_P_2 */
10130     { "vdppd",          { XM, Vex128, EXx, Ib } },
10131   },
10132   {
10133     /* VEX_W_3A42_P_2 */
10134     { "vmpsadbw",       { XM, Vex128, EXx, Ib } },
10135   },
10136   {
10137     /* VEX_W_3A44_P_2 */
10138     { "vpclmulqdq",     { XM, Vex128, EXx, PCLMUL } },
10139   },
10140   {
10141     /* VEX_W_3A48_P_2 */
10142     { "vpermil2ps",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW } },
10143     { "vpermil2ps",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW } },
10144   },
10145   {
10146     /* VEX_W_3A49_P_2 */
10147     { "vpermil2pd",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW } },
10148     { "vpermil2pd",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW } },
10149   },
10150   {
10151     /* VEX_W_3A4A_P_2 */
10152     { "vblendvps",      { XM, Vex, EXx, XMVexI4 } },
10153   },
10154   {
10155     /* VEX_W_3A4B_P_2 */
10156     { "vblendvpd",      { XM, Vex, EXx, XMVexI4 } },
10157   },
10158   {
10159     /* VEX_W_3A4C_P_2 */
10160     { "vpblendvb",      { XM, Vex128, EXx, XMVexI4 } },
10161   },
10162   {
10163     /* VEX_W_3A60_P_2 */
10164     { "vpcmpestrm",     { XM, EXx, Ib } },
10165   },
10166   {
10167     /* VEX_W_3A61_P_2 */
10168     { "vpcmpestri",     { XM, EXx, Ib } },
10169   },
10170   {
10171     /* VEX_W_3A62_P_2 */
10172     { "vpcmpistrm",     { XM, EXx, Ib } },
10173   },
10174   {
10175     /* VEX_W_3A63_P_2 */
10176     { "vpcmpistri",     { XM, EXx, Ib } },
10177   },
10178   {
10179     /* VEX_W_3ADF_P_2 */
10180     { "vaeskeygenassist", { XM, EXx, Ib } },
10181   },
10182 };
10183
10184 static const struct dis386 mod_table[][2] = {
10185   {
10186     /* MOD_8D */
10187     { "leaS",           { Gv, M } },
10188   },
10189   {
10190     /* MOD_0F01_REG_0 */
10191     { X86_64_TABLE (X86_64_0F01_REG_0) },
10192     { RM_TABLE (RM_0F01_REG_0) },
10193   },
10194   {
10195     /* MOD_0F01_REG_1 */
10196     { X86_64_TABLE (X86_64_0F01_REG_1) },
10197     { RM_TABLE (RM_0F01_REG_1) },
10198   },
10199   {
10200     /* MOD_0F01_REG_2 */
10201     { X86_64_TABLE (X86_64_0F01_REG_2) },
10202     { RM_TABLE (RM_0F01_REG_2) },
10203   },
10204   {
10205     /* MOD_0F01_REG_3 */
10206     { X86_64_TABLE (X86_64_0F01_REG_3) },
10207     { RM_TABLE (RM_0F01_REG_3) },
10208   },
10209   {
10210     /* MOD_0F01_REG_7 */
10211     { "invlpg",         { Mb } },
10212     { RM_TABLE (RM_0F01_REG_7) },
10213   },
10214   {
10215     /* MOD_0F12_PREFIX_0 */
10216     { "movlps",         { XM, EXq } },
10217     { "movhlps",        { XM, EXq } },
10218   },
10219   {
10220     /* MOD_0F13 */
10221     { "movlpX",         { EXq, XM } },
10222   },
10223   {
10224     /* MOD_0F16_PREFIX_0 */
10225     { "movhps",         { XM, EXq } },
10226     { "movlhps",        { XM, EXq } },
10227   },
10228   {
10229     /* MOD_0F17 */
10230     { "movhpX",         { EXq, XM } },
10231   },
10232   {
10233     /* MOD_0F18_REG_0 */
10234     { "prefetchnta",    { Mb } },
10235   },
10236   {
10237     /* MOD_0F18_REG_1 */
10238     { "prefetcht0",     { Mb } },
10239   },
10240   {
10241     /* MOD_0F18_REG_2 */
10242     { "prefetcht1",     { Mb } },
10243   },
10244   {
10245     /* MOD_0F18_REG_3 */
10246     { "prefetcht2",     { Mb } },
10247   },
10248   {
10249     /* MOD_0F20 */
10250     { Bad_Opcode },
10251     { "movZ",           { Rm, Cm } },
10252   },
10253   {
10254     /* MOD_0F21 */
10255     { Bad_Opcode },
10256     { "movZ",           { Rm, Dm } },
10257   },
10258   {
10259     /* MOD_0F22 */
10260     { Bad_Opcode },
10261     { "movZ",           { Cm, Rm } },
10262   },
10263   {
10264     /* MOD_0F23 */
10265     { Bad_Opcode },
10266     { "movZ",           { Dm, Rm } },
10267   },
10268   {
10269     /* MOD_0F24 */
10270     { Bad_Opcode },
10271     { "movL",           { Rd, Td } },
10272   },
10273   {
10274     /* MOD_0F26 */
10275     { Bad_Opcode },
10276     { "movL",           { Td, Rd } },
10277   },
10278   {
10279     /* MOD_0F2B_PREFIX_0 */
10280     {"movntps",         { Mx, XM } },
10281   },
10282   {
10283     /* MOD_0F2B_PREFIX_1 */
10284     {"movntss",         { Md, XM } },
10285   },
10286   {
10287     /* MOD_0F2B_PREFIX_2 */
10288     {"movntpd",         { Mx, XM } },
10289   },
10290   {
10291     /* MOD_0F2B_PREFIX_3 */
10292     {"movntsd",         { Mq, XM } },
10293   },
10294   {
10295     /* MOD_0F51 */
10296     { Bad_Opcode },
10297     { "movmskpX",       { Gdq, XS } },
10298   },
10299   {
10300     /* MOD_0F71_REG_2 */
10301     { Bad_Opcode },
10302     { "psrlw",          { MS, Ib } },
10303   },
10304   {
10305     /* MOD_0F71_REG_4 */
10306     { Bad_Opcode },
10307     { "psraw",          { MS, Ib } },
10308   },
10309   {
10310     /* MOD_0F71_REG_6 */
10311     { Bad_Opcode },
10312     { "psllw",          { MS, Ib } },
10313   },
10314   {
10315     /* MOD_0F72_REG_2 */
10316     { Bad_Opcode },
10317     { "psrld",          { MS, Ib } },
10318   },
10319   {
10320     /* MOD_0F72_REG_4 */
10321     { Bad_Opcode },
10322     { "psrad",          { MS, Ib } },
10323   },
10324   {
10325     /* MOD_0F72_REG_6 */
10326     { Bad_Opcode },
10327     { "pslld",          { MS, Ib } },
10328   },
10329   {
10330     /* MOD_0F73_REG_2 */
10331     { Bad_Opcode },
10332     { "psrlq",          { MS, Ib } },
10333   },
10334   {
10335     /* MOD_0F73_REG_3 */
10336     { Bad_Opcode },
10337     { PREFIX_TABLE (PREFIX_0F73_REG_3) },
10338   },
10339   {
10340     /* MOD_0F73_REG_6 */
10341     { Bad_Opcode },
10342     { "psllq",          { MS, Ib } },
10343   },
10344   {
10345     /* MOD_0F73_REG_7 */
10346     { Bad_Opcode },
10347     { PREFIX_TABLE (PREFIX_0F73_REG_7) },
10348   },
10349   {
10350     /* MOD_0FAE_REG_0 */
10351     { "fxsave",         { FXSAVE } },
10352   },
10353   {
10354     /* MOD_0FAE_REG_1 */
10355     { "fxrstor",        { FXSAVE } },
10356   },
10357   {
10358     /* MOD_0FAE_REG_2 */
10359     { "ldmxcsr",        { Md } },
10360   },
10361   {
10362     /* MOD_0FAE_REG_3 */
10363     { "stmxcsr",        { Md } },
10364   },
10365   {
10366     /* MOD_0FAE_REG_4 */
10367     { "xsave",          { FXSAVE } },
10368   },
10369   {
10370     /* MOD_0FAE_REG_5 */
10371     { "xrstor",         { FXSAVE } },
10372     { RM_TABLE (RM_0FAE_REG_5) },
10373   },
10374   {
10375     /* MOD_0FAE_REG_6 */
10376     { Bad_Opcode },
10377     { RM_TABLE (RM_0FAE_REG_6) },
10378   },
10379   {
10380     /* MOD_0FAE_REG_7 */
10381     { "clflush",        { Mb } },
10382     { RM_TABLE (RM_0FAE_REG_7) },
10383   },
10384   {
10385     /* MOD_0FB2 */
10386     { "lssS",           { Gv, Mp } },
10387   },
10388   {
10389     /* MOD_0FB4 */
10390     { "lfsS",           { Gv, Mp } },
10391   },
10392   {
10393     /* MOD_0FB5 */
10394     { "lgsS",           { Gv, Mp } },
10395   },
10396   {
10397     /* MOD_0FC7_REG_6 */
10398     { PREFIX_TABLE (PREFIX_0FC7_REG_6) },
10399   },
10400   {
10401     /* MOD_0FC7_REG_7 */
10402     { "vmptrst",        { Mq } },
10403   },
10404   {
10405     /* MOD_0FD7 */
10406     { Bad_Opcode },
10407     { "pmovmskb",       { Gdq, MS } },
10408   },
10409   {
10410     /* MOD_0FE7_PREFIX_2 */
10411     { "movntdq",        { Mx, XM } },
10412   },
10413   {
10414     /* MOD_0FF0_PREFIX_3 */
10415     { "lddqu",          { XM, M } },
10416   },
10417   {
10418     /* MOD_0F382A_PREFIX_2 */
10419     { "movntdqa",       { XM, Mx } },
10420   },
10421   {
10422     /* MOD_62_32BIT */
10423     { "bound{S|}",      { Gv, Ma } },
10424   },
10425   {
10426     /* MOD_C4_32BIT */
10427     { "lesS",           { Gv, Mp } },
10428     { VEX_C4_TABLE (VEX_0F) },
10429   },
10430   {
10431     /* MOD_C5_32BIT */
10432     { "ldsS",           { Gv, Mp } },
10433     { VEX_C5_TABLE (VEX_0F) },
10434   },
10435   {
10436     /* MOD_VEX_12_PREFIX_0 */
10437     { VEX_LEN_TABLE (VEX_LEN_12_P_0_M_0) },
10438     { VEX_LEN_TABLE (VEX_LEN_12_P_0_M_1) },
10439   },
10440   {
10441     /* MOD_VEX_13 */
10442     { VEX_LEN_TABLE (VEX_LEN_13_M_0) },
10443   },
10444   {
10445     /* MOD_VEX_16_PREFIX_0 */
10446     { VEX_LEN_TABLE (VEX_LEN_16_P_0_M_0) },
10447     { VEX_LEN_TABLE (VEX_LEN_16_P_0_M_1) },
10448   },
10449   {
10450     /* MOD_VEX_17 */
10451     { VEX_LEN_TABLE (VEX_LEN_17_M_0) },
10452   },
10453   {
10454     /* MOD_VEX_2B */
10455     { VEX_W_TABLE (VEX_W_2B_M_0) },
10456   },
10457   {
10458     /* MOD_VEX_50 */
10459     { Bad_Opcode },
10460     { VEX_W_TABLE (VEX_W_50_M_0) },
10461   },
10462   {
10463     /* MOD_VEX_71_REG_2 */
10464     { Bad_Opcode },
10465     { PREFIX_TABLE (PREFIX_VEX_71_REG_2) },
10466   },
10467   {
10468     /* MOD_VEX_71_REG_4 */
10469     { Bad_Opcode },
10470     { PREFIX_TABLE (PREFIX_VEX_71_REG_4) },
10471   },
10472   {
10473     /* MOD_VEX_71_REG_6 */
10474     { Bad_Opcode },
10475     { PREFIX_TABLE (PREFIX_VEX_71_REG_6) },
10476   },
10477   {
10478     /* MOD_VEX_72_REG_2 */
10479     { Bad_Opcode },
10480     { PREFIX_TABLE (PREFIX_VEX_72_REG_2) },
10481   },
10482   {
10483     /* MOD_VEX_72_REG_4 */
10484     { Bad_Opcode },
10485     { PREFIX_TABLE (PREFIX_VEX_72_REG_4) },
10486   },
10487   {
10488     /* MOD_VEX_72_REG_6 */
10489     { Bad_Opcode },
10490     { PREFIX_TABLE (PREFIX_VEX_72_REG_6) },
10491   },
10492   {
10493     /* MOD_VEX_73_REG_2 */
10494     { Bad_Opcode },
10495     { PREFIX_TABLE (PREFIX_VEX_73_REG_2) },
10496   },
10497   {
10498     /* MOD_VEX_73_REG_3 */
10499     { Bad_Opcode },
10500     { PREFIX_TABLE (PREFIX_VEX_73_REG_3) },
10501   },
10502   {
10503     /* MOD_VEX_73_REG_6 */
10504     { Bad_Opcode },
10505     { PREFIX_TABLE (PREFIX_VEX_73_REG_6) },
10506   },
10507   {
10508     /* MOD_VEX_73_REG_7 */
10509     { Bad_Opcode },
10510     { PREFIX_TABLE (PREFIX_VEX_73_REG_7) },
10511   },
10512   {
10513     /* MOD_VEX_AE_REG_2 */
10514     { VEX_LEN_TABLE (VEX_LEN_AE_R_2_M_0) },
10515   },
10516   {
10517     /* MOD_VEX_AE_REG_3 */
10518     { VEX_LEN_TABLE (VEX_LEN_AE_R_3_M_0) },
10519   },
10520   {
10521     /* MOD_VEX_D7_PREFIX_2 */
10522     { Bad_Opcode },
10523     { VEX_LEN_TABLE (VEX_LEN_D7_P_2_M_1) },
10524   },
10525   {
10526     /* MOD_VEX_E7_PREFIX_2 */
10527     { VEX_W_TABLE (VEX_W_E7_P_2_M_0) },
10528   },
10529   {
10530     /* MOD_VEX_F0_PREFIX_3 */
10531     { VEX_W_TABLE (VEX_W_F0_P_3_M_0) },
10532   },
10533   {
10534     /* MOD_VEX_3818_PREFIX_2 */
10535     { VEX_W_TABLE (VEX_W_3818_P_2_M_0) },
10536   },
10537   {
10538     /* MOD_VEX_3819_PREFIX_2 */
10539     { VEX_LEN_TABLE (VEX_LEN_3819_P_2_M_0) },
10540   },
10541   {
10542     /* MOD_VEX_381A_PREFIX_2 */
10543     { VEX_LEN_TABLE (VEX_LEN_381A_P_2_M_0) },
10544   },
10545   {
10546     /* MOD_VEX_382A_PREFIX_2 */
10547     { VEX_LEN_TABLE (VEX_LEN_382A_P_2_M_0) },
10548   },
10549   {
10550     /* MOD_VEX_382C_PREFIX_2 */
10551     { VEX_W_TABLE (VEX_W_382C_P_2_M_0) },
10552   },
10553   {
10554     /* MOD_VEX_382D_PREFIX_2 */
10555     { VEX_W_TABLE (VEX_W_382D_P_2_M_0) },
10556   },
10557   {
10558     /* MOD_VEX_382E_PREFIX_2 */
10559     { VEX_W_TABLE (VEX_W_382E_P_2_M_0) },
10560   },
10561   {
10562     /* MOD_VEX_382F_PREFIX_2 */
10563     { VEX_W_TABLE (VEX_W_382F_P_2_M_0) },
10564   },
10565 };
10566
10567 static const struct dis386 rm_table[][8] = {
10568   {
10569     /* RM_0F01_REG_0 */
10570     { Bad_Opcode },
10571     { "vmcall",         { Skip_MODRM } },
10572     { "vmlaunch",       { Skip_MODRM } },
10573     { "vmresume",       { Skip_MODRM } },
10574     { "vmxoff",         { Skip_MODRM } },
10575   },
10576   {
10577     /* RM_0F01_REG_1 */
10578     { "monitor",        { { OP_Monitor, 0 } } },
10579     { "mwait",          { { OP_Mwait, 0 } } },
10580   },
10581   {
10582     /* RM_0F01_REG_2 */
10583     { "xgetbv",         { Skip_MODRM } },
10584     { "xsetbv",         { Skip_MODRM } },
10585   },
10586   {
10587     /* RM_0F01_REG_3 */
10588     { "vmrun",          { Skip_MODRM } },
10589     { "vmmcall",        { Skip_MODRM } },
10590     { "vmload",         { Skip_MODRM } },
10591     { "vmsave",         { Skip_MODRM } },
10592     { "stgi",           { Skip_MODRM } },
10593     { "clgi",           { Skip_MODRM } },
10594     { "skinit",         { Skip_MODRM } },
10595     { "invlpga",        { Skip_MODRM } },
10596   },
10597   {
10598     /* RM_0F01_REG_7 */
10599     { "swapgs",         { Skip_MODRM } },
10600     { "rdtscp",         { Skip_MODRM } },
10601   },
10602   {
10603     /* RM_0FAE_REG_5 */
10604     { "lfence",         { Skip_MODRM } },
10605   },
10606   {
10607     /* RM_0FAE_REG_6 */
10608     { "mfence",         { Skip_MODRM } },
10609   },
10610   {
10611     /* RM_0FAE_REG_7 */
10612     { "sfence",         { Skip_MODRM } },
10613   },
10614 };
10615
10616 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
10617
10618 /* We use the high bit to indicate different name for the same
10619    prefix.  */
10620 #define ADDR16_PREFIX   (0x67 | 0x100)
10621 #define ADDR32_PREFIX   (0x67 | 0x200)
10622 #define DATA16_PREFIX   (0x66 | 0x100)
10623 #define DATA32_PREFIX   (0x66 | 0x200)
10624 #define REP_PREFIX      (0xf3 | 0x100)
10625
10626 static int
10627 ckprefix (void)
10628 {
10629   int newrex, i, length;
10630   rex = 0;
10631   rex_ignored = 0;
10632   prefixes = 0;
10633   used_prefixes = 0;
10634   rex_used = 0;
10635   last_lock_prefix = -1;
10636   last_repz_prefix = -1;
10637   last_repnz_prefix = -1;
10638   last_data_prefix = -1;
10639   last_addr_prefix = -1;
10640   last_rex_prefix = -1;
10641   last_seg_prefix = -1;
10642   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
10643     all_prefixes[i] = 0;
10644   i = 0;
10645   length = 0;
10646   /* The maximum instruction length is 15bytes.  */
10647   while (length < MAX_CODE_LENGTH - 1)
10648     {
10649       FETCH_DATA (the_info, codep + 1);
10650       newrex = 0;
10651       switch (*codep)
10652         {
10653         /* REX prefixes family.  */
10654         case 0x40:
10655         case 0x41:
10656         case 0x42:
10657         case 0x43:
10658         case 0x44:
10659         case 0x45:
10660         case 0x46:
10661         case 0x47:
10662         case 0x48:
10663         case 0x49:
10664         case 0x4a:
10665         case 0x4b:
10666         case 0x4c:
10667         case 0x4d:
10668         case 0x4e:
10669         case 0x4f:
10670           if (address_mode == mode_64bit)
10671             newrex = *codep;
10672           else
10673             return 1;
10674           last_rex_prefix = i;
10675           break;
10676         case 0xf3:
10677           prefixes |= PREFIX_REPZ;
10678           last_repz_prefix = i;
10679           break;
10680         case 0xf2:
10681           prefixes |= PREFIX_REPNZ;
10682           last_repnz_prefix = i;
10683           break;
10684         case 0xf0:
10685           prefixes |= PREFIX_LOCK;
10686           last_lock_prefix = i;
10687           break;
10688         case 0x2e:
10689           prefixes |= PREFIX_CS;
10690           last_seg_prefix = i;
10691           break;
10692         case 0x36:
10693           prefixes |= PREFIX_SS;
10694           last_seg_prefix = i;
10695           break;
10696         case 0x3e:
10697           prefixes |= PREFIX_DS;
10698           last_seg_prefix = i;
10699           break;
10700         case 0x26:
10701           prefixes |= PREFIX_ES;
10702           last_seg_prefix = i;
10703           break;
10704         case 0x64:
10705           prefixes |= PREFIX_FS;
10706           last_seg_prefix = i;
10707           break;
10708         case 0x65:
10709           prefixes |= PREFIX_GS;
10710           last_seg_prefix = i;
10711           break;
10712         case 0x66:
10713           prefixes |= PREFIX_DATA;
10714           last_data_prefix = i;
10715           break;
10716         case 0x67:
10717           prefixes |= PREFIX_ADDR;
10718           last_addr_prefix = i;
10719           break;
10720         case FWAIT_OPCODE:
10721           /* fwait is really an instruction.  If there are prefixes
10722              before the fwait, they belong to the fwait, *not* to the
10723              following instruction.  */
10724           if (prefixes || rex)
10725             {
10726               prefixes |= PREFIX_FWAIT;
10727               codep++;
10728               return 1;
10729             }
10730           prefixes = PREFIX_FWAIT;
10731           break;
10732         default:
10733           return 1;
10734         }
10735       /* Rex is ignored when followed by another prefix.  */
10736       if (rex)
10737         {
10738           rex_used = rex;
10739           return 1;
10740         }
10741       if (*codep != FWAIT_OPCODE)
10742         all_prefixes[i++] = *codep;
10743       rex = newrex;
10744       codep++;
10745       length++;
10746     }
10747   return 0;
10748 }
10749
10750 static int
10751 seg_prefix (int pref)
10752 {
10753   switch (pref)
10754     {
10755     case 0x2e:
10756       return PREFIX_CS;
10757     case 0x36:
10758       return PREFIX_SS;
10759     case 0x3e:
10760       return PREFIX_DS;
10761     case 0x26:
10762       return PREFIX_ES;
10763     case 0x64:
10764       return PREFIX_FS;
10765     case 0x65:
10766       return PREFIX_GS;
10767     default:
10768       return 0;
10769     }
10770 }
10771
10772 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
10773    prefix byte.  */
10774
10775 static const char *
10776 prefix_name (int pref, int sizeflag)
10777 {
10778   static const char *rexes [16] =
10779     {
10780       "rex",            /* 0x40 */
10781       "rex.B",          /* 0x41 */
10782       "rex.X",          /* 0x42 */
10783       "rex.XB",         /* 0x43 */
10784       "rex.R",          /* 0x44 */
10785       "rex.RB",         /* 0x45 */
10786       "rex.RX",         /* 0x46 */
10787       "rex.RXB",        /* 0x47 */
10788       "rex.W",          /* 0x48 */
10789       "rex.WB",         /* 0x49 */
10790       "rex.WX",         /* 0x4a */
10791       "rex.WXB",        /* 0x4b */
10792       "rex.WR",         /* 0x4c */
10793       "rex.WRB",        /* 0x4d */
10794       "rex.WRX",        /* 0x4e */
10795       "rex.WRXB",       /* 0x4f */
10796     };
10797
10798   switch (pref)
10799     {
10800     /* REX prefixes family.  */
10801     case 0x40:
10802     case 0x41:
10803     case 0x42:
10804     case 0x43:
10805     case 0x44:
10806     case 0x45:
10807     case 0x46:
10808     case 0x47:
10809     case 0x48:
10810     case 0x49:
10811     case 0x4a:
10812     case 0x4b:
10813     case 0x4c:
10814     case 0x4d:
10815     case 0x4e:
10816     case 0x4f:
10817       return rexes [pref - 0x40];
10818     case 0xf3:
10819       return "repz";
10820     case 0xf2:
10821       return "repnz";
10822     case 0xf0:
10823       return "lock";
10824     case 0x2e:
10825       return "cs";
10826     case 0x36:
10827       return "ss";
10828     case 0x3e:
10829       return "ds";
10830     case 0x26:
10831       return "es";
10832     case 0x64:
10833       return "fs";
10834     case 0x65:
10835       return "gs";
10836     case 0x66:
10837       return (sizeflag & DFLAG) ? "data16" : "data32";
10838     case 0x67:
10839       if (address_mode == mode_64bit)
10840         return (sizeflag & AFLAG) ? "addr32" : "addr64";
10841       else
10842         return (sizeflag & AFLAG) ? "addr16" : "addr32";
10843     case FWAIT_OPCODE:
10844       return "fwait";
10845     case ADDR16_PREFIX:
10846       return "addr16";
10847     case ADDR32_PREFIX:
10848       return "addr32";
10849     case DATA16_PREFIX:
10850       return "data16";
10851     case DATA32_PREFIX:
10852       return "data32";
10853     case REP_PREFIX:
10854       return "rep";
10855     default:
10856       return NULL;
10857     }
10858 }
10859
10860 static char op_out[MAX_OPERANDS][100];
10861 static int op_ad, op_index[MAX_OPERANDS];
10862 static int two_source_ops;
10863 static bfd_vma op_address[MAX_OPERANDS];
10864 static bfd_vma op_riprel[MAX_OPERANDS];
10865 static bfd_vma start_pc;
10866
10867 /*
10868  *   On the 386's of 1988, the maximum length of an instruction is 15 bytes.
10869  *   (see topic "Redundant prefixes" in the "Differences from 8086"
10870  *   section of the "Virtual 8086 Mode" chapter.)
10871  * 'pc' should be the address of this instruction, it will
10872  *   be used to print the target address if this is a relative jump or call
10873  * The function returns the length of this instruction in bytes.
10874  */
10875
10876 static char intel_syntax;
10877 static char intel_mnemonic = !SYSV386_COMPAT;
10878 static char open_char;
10879 static char close_char;
10880 static char separator_char;
10881 static char scale_char;
10882
10883 /* Here for backwards compatibility.  When gdb stops using
10884    print_insn_i386_att and print_insn_i386_intel these functions can
10885    disappear, and print_insn_i386 be merged into print_insn.  */
10886 int
10887 print_insn_i386_att (bfd_vma pc, disassemble_info *info)
10888 {
10889   intel_syntax = 0;
10890
10891   return print_insn (pc, info);
10892 }
10893
10894 int
10895 print_insn_i386_intel (bfd_vma pc, disassemble_info *info)
10896 {
10897   intel_syntax = 1;
10898
10899   return print_insn (pc, info);
10900 }
10901
10902 int
10903 print_insn_i386 (bfd_vma pc, disassemble_info *info)
10904 {
10905   intel_syntax = -1;
10906
10907   return print_insn (pc, info);
10908 }
10909
10910 void
10911 print_i386_disassembler_options (FILE *stream)
10912 {
10913   fprintf (stream, _("\n\
10914 The following i386/x86-64 specific disassembler options are supported for use\n\
10915 with the -M switch (multiple options should be separated by commas):\n"));
10916
10917   fprintf (stream, _("  x86-64      Disassemble in 64bit mode\n"));
10918   fprintf (stream, _("  i386        Disassemble in 32bit mode\n"));
10919   fprintf (stream, _("  i8086       Disassemble in 16bit mode\n"));
10920   fprintf (stream, _("  att         Display instruction in AT&T syntax\n"));
10921   fprintf (stream, _("  intel       Display instruction in Intel syntax\n"));
10922   fprintf (stream, _("  att-mnemonic\n"
10923                      "              Display instruction in AT&T mnemonic\n"));
10924   fprintf (stream, _("  intel-mnemonic\n"
10925                      "              Display instruction in Intel mnemonic\n"));
10926   fprintf (stream, _("  addr64      Assume 64bit address size\n"));
10927   fprintf (stream, _("  addr32      Assume 32bit address size\n"));
10928   fprintf (stream, _("  addr16      Assume 16bit address size\n"));
10929   fprintf (stream, _("  data32      Assume 32bit data size\n"));
10930   fprintf (stream, _("  data16      Assume 16bit data size\n"));
10931   fprintf (stream, _("  suffix      Always display instruction suffix in AT&T syntax\n"));
10932 }
10933
10934 /* Bad opcode.  */
10935 static const struct dis386 bad_opcode = { "(bad)", { XX } };
10936
10937 /* Get a pointer to struct dis386 with a valid name.  */
10938
10939 static const struct dis386 *
10940 get_valid_dis386 (const struct dis386 *dp, disassemble_info *info)
10941 {
10942   int vindex, vex_table_index;
10943
10944   if (dp->name != NULL)
10945     return dp;
10946
10947   switch (dp->op[0].bytemode)
10948     {
10949     case USE_REG_TABLE:
10950       dp = &reg_table[dp->op[1].bytemode][modrm.reg];
10951       break;
10952
10953     case USE_MOD_TABLE:
10954       vindex = modrm.mod == 0x3 ? 1 : 0;
10955       dp = &mod_table[dp->op[1].bytemode][vindex];
10956       break;
10957
10958     case USE_RM_TABLE:
10959       dp = &rm_table[dp->op[1].bytemode][modrm.rm];
10960       break;
10961
10962     case USE_PREFIX_TABLE:
10963       if (need_vex)
10964         {
10965           /* The prefix in VEX is implicit.  */
10966           switch (vex.prefix)
10967             {
10968             case 0:
10969               vindex = 0;
10970               break;
10971             case REPE_PREFIX_OPCODE:
10972               vindex = 1;
10973               break;
10974             case DATA_PREFIX_OPCODE:
10975               vindex = 2;
10976               break;
10977             case REPNE_PREFIX_OPCODE:
10978               vindex = 3;
10979               break;
10980             default:
10981               abort ();
10982               break;
10983             }
10984         }
10985       else
10986         {
10987           vindex = 0;
10988           used_prefixes |= (prefixes & PREFIX_REPZ);
10989           if (prefixes & PREFIX_REPZ)
10990             {
10991               vindex = 1;
10992               all_prefixes[last_repz_prefix] = 0;
10993             }
10994           else
10995             {
10996               /* We should check PREFIX_REPNZ and PREFIX_REPZ before
10997                  PREFIX_DATA.  */
10998               used_prefixes |= (prefixes & PREFIX_REPNZ);
10999               if (prefixes & PREFIX_REPNZ)
11000                 {
11001                   vindex = 3;
11002                   all_prefixes[last_repnz_prefix] = 0;
11003                 }
11004               else
11005                 {
11006                   used_prefixes |= (prefixes & PREFIX_DATA);
11007                   if (prefixes & PREFIX_DATA)
11008                     {
11009                       vindex = 2;
11010                       all_prefixes[last_data_prefix] = 0;
11011                     }
11012                 }
11013             }
11014         }
11015       dp = &prefix_table[dp->op[1].bytemode][vindex];
11016       break;
11017
11018     case USE_X86_64_TABLE:
11019       vindex = address_mode == mode_64bit ? 1 : 0;
11020       dp = &x86_64_table[dp->op[1].bytemode][vindex];
11021       break;
11022
11023     case USE_3BYTE_TABLE:
11024       FETCH_DATA (info, codep + 2);
11025       vindex = *codep++;
11026       dp = &three_byte_table[dp->op[1].bytemode][vindex];
11027       modrm.mod = (*codep >> 6) & 3;
11028       modrm.reg = (*codep >> 3) & 7;
11029       modrm.rm = *codep & 7;
11030       break;
11031
11032     case USE_VEX_LEN_TABLE:
11033       if (!need_vex)
11034         abort ();
11035
11036       switch (vex.length)
11037         {
11038         case 128:
11039           vindex = 0;
11040           break;
11041         case 256:
11042           vindex = 1;
11043           break;
11044         default:
11045           abort ();
11046           break;
11047         }
11048
11049       dp = &vex_len_table[dp->op[1].bytemode][vindex];
11050       break;
11051
11052     case USE_XOP_8F_TABLE:
11053       FETCH_DATA (info, codep + 3);
11054       /* All bits in the REX prefix are ignored.  */
11055       rex_ignored = rex;
11056       rex = ~(*codep >> 5) & 0x7;
11057
11058       /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm".  */
11059       switch ((*codep & 0x1f))
11060         {
11061         default:
11062           BadOp ();
11063         case 0x8:
11064           vex_table_index = XOP_08;
11065           break;
11066         case 0x9:
11067           vex_table_index = XOP_09;
11068           break;
11069         case 0xa:
11070           vex_table_index = XOP_0A;
11071           break;
11072         }
11073       codep++;
11074       vex.w = *codep & 0x80;
11075       if (vex.w && address_mode == mode_64bit)
11076         rex |= REX_W;
11077
11078       vex.register_specifier = (~(*codep >> 3)) & 0xf;
11079       if (address_mode != mode_64bit
11080           && vex.register_specifier > 0x7)
11081         BadOp ();
11082
11083       vex.length = (*codep & 0x4) ? 256 : 128;
11084       switch ((*codep & 0x3))
11085         {
11086         case 0:
11087           vex.prefix = 0;
11088           break;
11089         case 1:
11090           vex.prefix = DATA_PREFIX_OPCODE;
11091           break;
11092         case 2:
11093           vex.prefix = REPE_PREFIX_OPCODE;
11094           break;
11095         case 3:
11096           vex.prefix = REPNE_PREFIX_OPCODE;
11097           break;
11098         }
11099       need_vex = 1;
11100       need_vex_reg = 1;
11101       codep++;
11102       vindex = *codep++;
11103       dp = &xop_table[vex_table_index][vindex];
11104
11105       FETCH_DATA (info, codep + 1);
11106       modrm.mod = (*codep >> 6) & 3;
11107       modrm.reg = (*codep >> 3) & 7;
11108       modrm.rm = *codep & 7;
11109       break;
11110
11111     case USE_VEX_C4_TABLE:
11112       FETCH_DATA (info, codep + 3);
11113       /* All bits in the REX prefix are ignored.  */
11114       rex_ignored = rex;
11115       rex = ~(*codep >> 5) & 0x7;
11116       switch ((*codep & 0x1f))
11117         {
11118         default:
11119           BadOp ();
11120         case 0x1:
11121           vex_table_index = VEX_0F;
11122           break;
11123         case 0x2:
11124           vex_table_index = VEX_0F38;
11125           break;
11126         case 0x3:
11127           vex_table_index = VEX_0F3A;
11128           break;
11129         }
11130       codep++;
11131       vex.w = *codep & 0x80;
11132       if (vex.w && address_mode == mode_64bit)
11133         rex |= REX_W;
11134
11135       vex.register_specifier = (~(*codep >> 3)) & 0xf;
11136       if (address_mode != mode_64bit
11137           && vex.register_specifier > 0x7)
11138         BadOp ();
11139
11140       vex.length = (*codep & 0x4) ? 256 : 128;
11141       switch ((*codep & 0x3))
11142         {
11143         case 0:
11144           vex.prefix = 0;
11145           break;
11146         case 1:
11147           vex.prefix = DATA_PREFIX_OPCODE;
11148           break;
11149         case 2:
11150           vex.prefix = REPE_PREFIX_OPCODE;
11151           break;
11152         case 3:
11153           vex.prefix = REPNE_PREFIX_OPCODE;
11154           break;
11155         }
11156       need_vex = 1;
11157       need_vex_reg = 1;
11158       codep++;
11159       vindex = *codep++;
11160       dp = &vex_table[vex_table_index][vindex];
11161       /* There is no MODRM byte for VEX [82|77].  */
11162       if (vindex != 0x77 && vindex != 0x82)
11163         {
11164           FETCH_DATA (info, codep + 1);
11165           modrm.mod = (*codep >> 6) & 3;
11166           modrm.reg = (*codep >> 3) & 7;
11167           modrm.rm = *codep & 7;
11168         }
11169       break;
11170
11171     case USE_VEX_C5_TABLE:
11172       FETCH_DATA (info, codep + 2);
11173       /* All bits in the REX prefix are ignored.  */
11174       rex_ignored = rex;
11175       rex = (*codep & 0x80) ? 0 : REX_R;
11176
11177       vex.register_specifier = (~(*codep >> 3)) & 0xf;
11178       if (address_mode != mode_64bit
11179           && vex.register_specifier > 0x7)
11180         BadOp ();
11181
11182       vex.w = 0;
11183
11184       vex.length = (*codep & 0x4) ? 256 : 128;
11185       switch ((*codep & 0x3))
11186         {
11187         case 0:
11188           vex.prefix = 0;
11189           break;
11190         case 1:
11191           vex.prefix = DATA_PREFIX_OPCODE;
11192           break;
11193         case 2:
11194           vex.prefix = REPE_PREFIX_OPCODE;
11195           break;
11196         case 3:
11197           vex.prefix = REPNE_PREFIX_OPCODE;
11198           break;
11199         }
11200       need_vex = 1;
11201       need_vex_reg = 1;
11202       codep++;
11203       vindex = *codep++;
11204       dp = &vex_table[dp->op[1].bytemode][vindex];
11205       /* There is no MODRM byte for VEX [82|77].  */
11206       if (vindex != 0x77 && vindex != 0x82)
11207         {
11208           FETCH_DATA (info, codep + 1);
11209           modrm.mod = (*codep >> 6) & 3;
11210           modrm.reg = (*codep >> 3) & 7;
11211           modrm.rm = *codep & 7;
11212         }
11213       break;
11214
11215     case USE_VEX_W_TABLE:
11216       if (!need_vex)
11217         abort ();
11218
11219       dp = &vex_w_table[dp->op[1].bytemode][vex.w ? 1 : 0];
11220       break;
11221
11222     case 0:
11223       dp = &bad_opcode;
11224       break;
11225
11226     default:
11227       abort ();
11228     }
11229
11230   if (dp->name != NULL)
11231     return dp;
11232   else
11233     return get_valid_dis386 (dp, info);
11234 }
11235
11236 static int
11237 print_insn (bfd_vma pc, disassemble_info *info)
11238 {
11239   const struct dis386 *dp;
11240   int i;
11241   char *op_txt[MAX_OPERANDS];
11242   int needcomma;
11243   int sizeflag;
11244   const char *p;
11245   struct dis_private priv;
11246   unsigned char op;
11247   int prefix_length;
11248   int default_prefixes;
11249
11250   if (info->mach == bfd_mach_x86_64_intel_syntax
11251       || info->mach == bfd_mach_x86_64
11252       || info->mach == bfd_mach_l1om
11253       || info->mach == bfd_mach_l1om_intel_syntax)
11254     address_mode = mode_64bit;
11255   else
11256     address_mode = mode_32bit;
11257
11258   if (intel_syntax == (char) -1)
11259     intel_syntax = (info->mach == bfd_mach_i386_i386_intel_syntax
11260                     || info->mach == bfd_mach_x86_64_intel_syntax
11261                     || info->mach == bfd_mach_l1om_intel_syntax);
11262
11263   if (info->mach == bfd_mach_i386_i386
11264       || info->mach == bfd_mach_x86_64
11265       || info->mach == bfd_mach_l1om
11266       || info->mach == bfd_mach_i386_i386_intel_syntax
11267       || info->mach == bfd_mach_x86_64_intel_syntax
11268       || info->mach == bfd_mach_l1om_intel_syntax)
11269     priv.orig_sizeflag = AFLAG | DFLAG;
11270   else if (info->mach == bfd_mach_i386_i8086)
11271     priv.orig_sizeflag = 0;
11272   else
11273     abort ();
11274
11275   for (p = info->disassembler_options; p != NULL; )
11276     {
11277       if (CONST_STRNEQ (p, "x86-64"))
11278         {
11279           address_mode = mode_64bit;
11280           priv.orig_sizeflag = AFLAG | DFLAG;
11281         }
11282       else if (CONST_STRNEQ (p, "i386"))
11283         {
11284           address_mode = mode_32bit;
11285           priv.orig_sizeflag = AFLAG | DFLAG;
11286         }
11287       else if (CONST_STRNEQ (p, "i8086"))
11288         {
11289           address_mode = mode_16bit;
11290           priv.orig_sizeflag = 0;
11291         }
11292       else if (CONST_STRNEQ (p, "intel"))
11293         {
11294           intel_syntax = 1;
11295           if (CONST_STRNEQ (p + 5, "-mnemonic"))
11296             intel_mnemonic = 1;
11297         }
11298       else if (CONST_STRNEQ (p, "att"))
11299         {
11300           intel_syntax = 0;
11301           if (CONST_STRNEQ (p + 3, "-mnemonic"))
11302             intel_mnemonic = 0;
11303         }
11304       else if (CONST_STRNEQ (p, "addr"))
11305         {
11306           if (address_mode == mode_64bit)
11307             {
11308               if (p[4] == '3' && p[5] == '2')
11309                 priv.orig_sizeflag &= ~AFLAG;
11310               else if (p[4] == '6' && p[5] == '4')
11311                 priv.orig_sizeflag |= AFLAG;
11312             }
11313           else
11314             {
11315               if (p[4] == '1' && p[5] == '6')
11316                 priv.orig_sizeflag &= ~AFLAG;
11317               else if (p[4] == '3' && p[5] == '2')
11318                 priv.orig_sizeflag |= AFLAG;
11319             }
11320         }
11321       else if (CONST_STRNEQ (p, "data"))
11322         {
11323           if (p[4] == '1' && p[5] == '6')
11324             priv.orig_sizeflag &= ~DFLAG;
11325           else if (p[4] == '3' && p[5] == '2')
11326             priv.orig_sizeflag |= DFLAG;
11327         }
11328       else if (CONST_STRNEQ (p, "suffix"))
11329         priv.orig_sizeflag |= SUFFIX_ALWAYS;
11330
11331       p = strchr (p, ',');
11332       if (p != NULL)
11333         p++;
11334     }
11335
11336   if (intel_syntax)
11337     {
11338       names64 = intel_names64;
11339       names32 = intel_names32;
11340       names16 = intel_names16;
11341       names8 = intel_names8;
11342       names8rex = intel_names8rex;
11343       names_seg = intel_names_seg;
11344       names_mm = intel_names_mm;
11345       names_xmm = intel_names_xmm;
11346       names_ymm = intel_names_ymm;
11347       index64 = intel_index64;
11348       index32 = intel_index32;
11349       index16 = intel_index16;
11350       open_char = '[';
11351       close_char = ']';
11352       separator_char = '+';
11353       scale_char = '*';
11354     }
11355   else
11356     {
11357       names64 = att_names64;
11358       names32 = att_names32;
11359       names16 = att_names16;
11360       names8 = att_names8;
11361       names8rex = att_names8rex;
11362       names_seg = att_names_seg;
11363       names_mm = att_names_mm;
11364       names_xmm = att_names_xmm;
11365       names_ymm = att_names_ymm;
11366       index64 = att_index64;
11367       index32 = att_index32;
11368       index16 = att_index16;
11369       open_char = '(';
11370       close_char =  ')';
11371       separator_char = ',';
11372       scale_char = ',';
11373     }
11374
11375   /* The output looks better if we put 7 bytes on a line, since that
11376      puts most long word instructions on a single line.  Use 8 bytes
11377      for Intel L1OM.  */
11378   if (info->mach == bfd_mach_l1om
11379       || info->mach == bfd_mach_l1om_intel_syntax)
11380     info->bytes_per_line = 8;
11381   else
11382     info->bytes_per_line = 7;
11383
11384   info->private_data = &priv;
11385   priv.max_fetched = priv.the_buffer;
11386   priv.insn_start = pc;
11387
11388   obuf[0] = 0;
11389   for (i = 0; i < MAX_OPERANDS; ++i)
11390     {
11391       op_out[i][0] = 0;
11392       op_index[i] = -1;
11393     }
11394
11395   the_info = info;
11396   start_pc = pc;
11397   start_codep = priv.the_buffer;
11398   codep = priv.the_buffer;
11399
11400   if (setjmp (priv.bailout) != 0)
11401     {
11402       const char *name;
11403
11404       /* Getting here means we tried for data but didn't get it.  That
11405          means we have an incomplete instruction of some sort.  Just
11406          print the first byte as a prefix or a .byte pseudo-op.  */
11407       if (codep > priv.the_buffer)
11408         {
11409           name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
11410           if (name != NULL)
11411             (*info->fprintf_func) (info->stream, "%s", name);
11412           else
11413             {
11414               /* Just print the first byte as a .byte instruction.  */
11415               (*info->fprintf_func) (info->stream, ".byte 0x%x",
11416                                      (unsigned int) priv.the_buffer[0]);
11417             }
11418
11419           return 1;
11420         }
11421
11422       return -1;
11423     }
11424
11425   obufp = obuf;
11426   sizeflag = priv.orig_sizeflag;
11427
11428   if (!ckprefix () || rex_used)
11429     {
11430       /* Too many prefixes or unused REX prefixes.  */
11431       for (i = 0;
11432            all_prefixes[i] && i < (int) ARRAY_SIZE (all_prefixes);
11433            i++)
11434         (*info->fprintf_func) (info->stream, "%s",
11435                                prefix_name (all_prefixes[i], sizeflag));
11436       return 1;
11437     }
11438
11439   insn_codep = codep;
11440
11441   FETCH_DATA (info, codep + 1);
11442   two_source_ops = (*codep == 0x62) || (*codep == 0xc8);
11443
11444   if (((prefixes & PREFIX_FWAIT)
11445        && ((*codep < 0xd8) || (*codep > 0xdf))))
11446     {
11447       (*info->fprintf_func) (info->stream, "fwait");
11448       return 1;
11449     }
11450
11451   op = 0;
11452
11453   if (*codep == 0x0f)
11454     {
11455       unsigned char threebyte;
11456       FETCH_DATA (info, codep + 2);
11457       threebyte = *++codep;
11458       dp = &dis386_twobyte[threebyte];
11459       need_modrm = twobyte_has_modrm[*codep];
11460       codep++;
11461     }
11462   else
11463     {
11464       dp = &dis386[*codep];
11465       need_modrm = onebyte_has_modrm[*codep];
11466       codep++;
11467     }
11468
11469   if ((prefixes & PREFIX_REPZ))
11470     used_prefixes |= PREFIX_REPZ;
11471   if ((prefixes & PREFIX_REPNZ))
11472     used_prefixes |= PREFIX_REPNZ;
11473   if ((prefixes & PREFIX_LOCK))
11474     used_prefixes |= PREFIX_LOCK;
11475
11476   default_prefixes = 0;
11477   if (prefixes & PREFIX_ADDR)
11478     {
11479       sizeflag ^= AFLAG;
11480       if (dp->op[2].bytemode != loop_jcxz_mode || intel_syntax)
11481         {
11482           if ((sizeflag & AFLAG) || address_mode == mode_64bit)
11483             all_prefixes[last_addr_prefix] = ADDR32_PREFIX;
11484           else
11485             all_prefixes[last_addr_prefix] = ADDR16_PREFIX;
11486           default_prefixes |= PREFIX_ADDR;
11487         }
11488     }
11489
11490   if ((prefixes & PREFIX_DATA))
11491     {
11492       sizeflag ^= DFLAG;
11493       if (dp->op[2].bytemode == cond_jump_mode
11494           && dp->op[0].bytemode == v_mode
11495           && !intel_syntax)
11496         {
11497           if (sizeflag & DFLAG)
11498             all_prefixes[last_data_prefix] = DATA32_PREFIX;
11499           else
11500             all_prefixes[last_data_prefix] = DATA16_PREFIX;
11501           default_prefixes |= PREFIX_DATA;
11502         }
11503       else if (rex & REX_W)
11504         {
11505           /* REX_W will override PREFIX_DATA.  */
11506           default_prefixes |= PREFIX_DATA;
11507         }
11508     }
11509
11510   if (need_modrm)
11511     {
11512       FETCH_DATA (info, codep + 1);
11513       modrm.mod = (*codep >> 6) & 3;
11514       modrm.reg = (*codep >> 3) & 7;
11515       modrm.rm = *codep & 7;
11516     }
11517
11518    need_vex = 0;
11519    need_vex_reg = 0;
11520    vex_w_done = 0;
11521
11522   if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
11523     {
11524       dofloat (sizeflag);
11525     }
11526   else
11527     {
11528       dp = get_valid_dis386 (dp, info);
11529       if (dp != NULL && putop (dp->name, sizeflag) == 0)
11530         {
11531           for (i = 0; i < MAX_OPERANDS; ++i)
11532             {
11533               obufp = op_out[i];
11534               op_ad = MAX_OPERANDS - 1 - i;
11535               if (dp->op[i].rtn)
11536                 (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag);
11537             }
11538         }
11539     }
11540
11541   /* See if any prefixes were not used.  If so, print the first one
11542      separately.  If we don't do this, we'll wind up printing an
11543      instruction stream which does not precisely correspond to the
11544      bytes we are disassembling.  */
11545   if ((prefixes & ~(used_prefixes | default_prefixes)) != 0)
11546     {
11547       for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
11548         if (all_prefixes[i])
11549           {
11550             const char *name;
11551             name = prefix_name (all_prefixes[i], priv.orig_sizeflag);
11552             if (name == NULL)
11553               name = INTERNAL_DISASSEMBLER_ERROR;
11554             (*info->fprintf_func) (info->stream, "%s", name);
11555             return 1;
11556           }
11557     }
11558
11559   /* Check if the REX prefix is used.  */
11560   if (rex_ignored == 0 && (rex ^ rex_used) == 0)
11561     all_prefixes[last_rex_prefix] = 0;
11562
11563   /* Check if the SEG prefix is used.  */
11564   if ((prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES
11565                    | PREFIX_FS | PREFIX_GS)) != 0
11566       && (used_prefixes
11567           & seg_prefix (all_prefixes[last_seg_prefix])) != 0)
11568     all_prefixes[last_seg_prefix] = 0;
11569
11570   /* Check if the ADDR prefix is used.  */
11571   if ((prefixes & PREFIX_ADDR) != 0
11572       && (used_prefixes & PREFIX_ADDR) != 0)
11573     all_prefixes[last_addr_prefix] = 0;
11574
11575   /* Check if the DATA prefix is used.  */
11576   if ((prefixes & PREFIX_DATA) != 0
11577       && (used_prefixes & PREFIX_DATA) != 0)
11578     all_prefixes[last_data_prefix] = 0;
11579
11580   prefix_length = 0;
11581   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
11582     if (all_prefixes[i])
11583       {
11584         const char *name;
11585         name = prefix_name (all_prefixes[i], sizeflag);
11586         if (name == NULL)
11587           abort ();
11588         prefix_length += strlen (name) + 1;
11589         (*info->fprintf_func) (info->stream, "%s ", name);
11590       }
11591
11592   /* Check maximum code length.  */
11593   if ((codep - start_codep) > MAX_CODE_LENGTH)
11594     {
11595       (*info->fprintf_func) (info->stream, "(bad)");
11596       return MAX_CODE_LENGTH;
11597     }
11598
11599   obufp = mnemonicendp;
11600   for (i = strlen (obuf) + prefix_length; i < 6; i++)
11601     oappend (" ");
11602   oappend (" ");
11603   (*info->fprintf_func) (info->stream, "%s", obuf);
11604
11605   /* The enter and bound instructions are printed with operands in the same
11606      order as the intel book; everything else is printed in reverse order.  */
11607   if (intel_syntax || two_source_ops)
11608     {
11609       bfd_vma riprel;
11610
11611       for (i = 0; i < MAX_OPERANDS; ++i)
11612         op_txt[i] = op_out[i];
11613
11614       for (i = 0; i < (MAX_OPERANDS >> 1); ++i)
11615         {
11616           op_ad = op_index[i];
11617           op_index[i] = op_index[MAX_OPERANDS - 1 - i];
11618           op_index[MAX_OPERANDS - 1 - i] = op_ad;
11619           riprel = op_riprel[i];
11620           op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i];
11621           op_riprel[MAX_OPERANDS - 1 - i] = riprel;
11622         }
11623     }
11624   else
11625     {
11626       for (i = 0; i < MAX_OPERANDS; ++i)
11627         op_txt[MAX_OPERANDS - 1 - i] = op_out[i];
11628     }
11629
11630   needcomma = 0;
11631   for (i = 0; i < MAX_OPERANDS; ++i)
11632     if (*op_txt[i])
11633       {
11634         if (needcomma)
11635           (*info->fprintf_func) (info->stream, ",");
11636         if (op_index[i] != -1 && !op_riprel[i])
11637           (*info->print_address_func) ((bfd_vma) op_address[op_index[i]], info);
11638         else
11639           (*info->fprintf_func) (info->stream, "%s", op_txt[i]);
11640         needcomma = 1;
11641       }
11642
11643   for (i = 0; i < MAX_OPERANDS; i++)
11644     if (op_index[i] != -1 && op_riprel[i])
11645       {
11646         (*info->fprintf_func) (info->stream, "        # ");
11647         (*info->print_address_func) ((bfd_vma) (start_pc + codep - start_codep
11648                                                 + op_address[op_index[i]]), info);
11649         break;
11650       }
11651   return codep - priv.the_buffer;
11652 }
11653
11654 static const char *float_mem[] = {
11655   /* d8 */
11656   "fadd{s|}",
11657   "fmul{s|}",
11658   "fcom{s|}",
11659   "fcomp{s|}",
11660   "fsub{s|}",
11661   "fsubr{s|}",
11662   "fdiv{s|}",
11663   "fdivr{s|}",
11664   /* d9 */
11665   "fld{s|}",
11666   "(bad)",
11667   "fst{s|}",
11668   "fstp{s|}",
11669   "fldenvIC",
11670   "fldcw",
11671   "fNstenvIC",
11672   "fNstcw",
11673   /* da */
11674   "fiadd{l|}",
11675   "fimul{l|}",
11676   "ficom{l|}",
11677   "ficomp{l|}",
11678   "fisub{l|}",
11679   "fisubr{l|}",
11680   "fidiv{l|}",
11681   "fidivr{l|}",
11682   /* db */
11683   "fild{l|}",
11684   "fisttp{l|}",
11685   "fist{l|}",
11686   "fistp{l|}",
11687   "(bad)",
11688   "fld{t||t|}",
11689   "(bad)",
11690   "fstp{t||t|}",
11691   /* dc */
11692   "fadd{l|}",
11693   "fmul{l|}",
11694   "fcom{l|}",
11695   "fcomp{l|}",
11696   "fsub{l|}",
11697   "fsubr{l|}",
11698   "fdiv{l|}",
11699   "fdivr{l|}",
11700   /* dd */
11701   "fld{l|}",
11702   "fisttp{ll|}",
11703   "fst{l||}",
11704   "fstp{l|}",
11705   "frstorIC",
11706   "(bad)",
11707   "fNsaveIC",
11708   "fNstsw",
11709   /* de */
11710   "fiadd",
11711   "fimul",
11712   "ficom",
11713   "ficomp",
11714   "fisub",
11715   "fisubr",
11716   "fidiv",
11717   "fidivr",
11718   /* df */
11719   "fild",
11720   "fisttp",
11721   "fist",
11722   "fistp",
11723   "fbld",
11724   "fild{ll|}",
11725   "fbstp",
11726   "fistp{ll|}",
11727 };
11728
11729 static const unsigned char float_mem_mode[] = {
11730   /* d8 */
11731   d_mode,
11732   d_mode,
11733   d_mode,
11734   d_mode,
11735   d_mode,
11736   d_mode,
11737   d_mode,
11738   d_mode,
11739   /* d9 */
11740   d_mode,
11741   0,
11742   d_mode,
11743   d_mode,
11744   0,
11745   w_mode,
11746   0,
11747   w_mode,
11748   /* da */
11749   d_mode,
11750   d_mode,
11751   d_mode,
11752   d_mode,
11753   d_mode,
11754   d_mode,
11755   d_mode,
11756   d_mode,
11757   /* db */
11758   d_mode,
11759   d_mode,
11760   d_mode,
11761   d_mode,
11762   0,
11763   t_mode,
11764   0,
11765   t_mode,
11766   /* dc */
11767   q_mode,
11768   q_mode,
11769   q_mode,
11770   q_mode,
11771   q_mode,
11772   q_mode,
11773   q_mode,
11774   q_mode,
11775   /* dd */
11776   q_mode,
11777   q_mode,
11778   q_mode,
11779   q_mode,
11780   0,
11781   0,
11782   0,
11783   w_mode,
11784   /* de */
11785   w_mode,
11786   w_mode,
11787   w_mode,
11788   w_mode,
11789   w_mode,
11790   w_mode,
11791   w_mode,
11792   w_mode,
11793   /* df */
11794   w_mode,
11795   w_mode,
11796   w_mode,
11797   w_mode,
11798   t_mode,
11799   q_mode,
11800   t_mode,
11801   q_mode
11802 };
11803
11804 #define ST { OP_ST, 0 }
11805 #define STi { OP_STi, 0 }
11806
11807 #define FGRPd9_2 NULL, { { NULL, 0 } }
11808 #define FGRPd9_4 NULL, { { NULL, 1 } }
11809 #define FGRPd9_5 NULL, { { NULL, 2 } }
11810 #define FGRPd9_6 NULL, { { NULL, 3 } }
11811 #define FGRPd9_7 NULL, { { NULL, 4 } }
11812 #define FGRPda_5 NULL, { { NULL, 5 } }
11813 #define FGRPdb_4 NULL, { { NULL, 6 } }
11814 #define FGRPde_3 NULL, { { NULL, 7 } }
11815 #define FGRPdf_4 NULL, { { NULL, 8 } }
11816
11817 static const struct dis386 float_reg[][8] = {
11818   /* d8 */
11819   {
11820     { "fadd",   { ST, STi } },
11821     { "fmul",   { ST, STi } },
11822     { "fcom",   { STi } },
11823     { "fcomp",  { STi } },
11824     { "fsub",   { ST, STi } },
11825     { "fsubr",  { ST, STi } },
11826     { "fdiv",   { ST, STi } },
11827     { "fdivr",  { ST, STi } },
11828   },
11829   /* d9 */
11830   {
11831     { "fld",    { STi } },
11832     { "fxch",   { STi } },
11833     { FGRPd9_2 },
11834     { Bad_Opcode },
11835     { FGRPd9_4 },
11836     { FGRPd9_5 },
11837     { FGRPd9_6 },
11838     { FGRPd9_7 },
11839   },
11840   /* da */
11841   {
11842     { "fcmovb", { ST, STi } },
11843     { "fcmove", { ST, STi } },
11844     { "fcmovbe",{ ST, STi } },
11845     { "fcmovu", { ST, STi } },
11846     { Bad_Opcode },
11847     { FGRPda_5 },
11848     { Bad_Opcode },
11849     { Bad_Opcode },
11850   },
11851   /* db */
11852   {
11853     { "fcmovnb",{ ST, STi } },
11854     { "fcmovne",{ ST, STi } },
11855     { "fcmovnbe",{ ST, STi } },
11856     { "fcmovnu",{ ST, STi } },
11857     { FGRPdb_4 },
11858     { "fucomi", { ST, STi } },
11859     { "fcomi",  { ST, STi } },
11860     { Bad_Opcode },
11861   },
11862   /* dc */
11863   {
11864     { "fadd",   { STi, ST } },
11865     { "fmul",   { STi, ST } },
11866     { Bad_Opcode },
11867     { Bad_Opcode },
11868     { "fsub!M", { STi, ST } },
11869     { "fsubM",  { STi, ST } },
11870     { "fdiv!M", { STi, ST } },
11871     { "fdivM",  { STi, ST } },
11872   },
11873   /* dd */
11874   {
11875     { "ffree",  { STi } },
11876     { Bad_Opcode },
11877     { "fst",    { STi } },
11878     { "fstp",   { STi } },
11879     { "fucom",  { STi } },
11880     { "fucomp", { STi } },
11881     { Bad_Opcode },
11882     { Bad_Opcode },
11883   },
11884   /* de */
11885   {
11886     { "faddp",  { STi, ST } },
11887     { "fmulp",  { STi, ST } },
11888     { Bad_Opcode },
11889     { FGRPde_3 },
11890     { "fsub!Mp", { STi, ST } },
11891     { "fsubMp", { STi, ST } },
11892     { "fdiv!Mp", { STi, ST } },
11893     { "fdivMp", { STi, ST } },
11894   },
11895   /* df */
11896   {
11897     { "ffreep", { STi } },
11898     { Bad_Opcode },
11899     { Bad_Opcode },
11900     { Bad_Opcode },
11901     { FGRPdf_4 },
11902     { "fucomip", { ST, STi } },
11903     { "fcomip", { ST, STi } },
11904     { Bad_Opcode },
11905   },
11906 };
11907
11908 static char *fgrps[][8] = {
11909   /* d9_2  0 */
11910   {
11911     "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
11912   },
11913
11914   /* d9_4  1 */
11915   {
11916     "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
11917   },
11918
11919   /* d9_5  2 */
11920   {
11921     "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
11922   },
11923
11924   /* d9_6  3 */
11925   {
11926     "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
11927   },
11928
11929   /* d9_7  4 */
11930   {
11931     "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
11932   },
11933
11934   /* da_5  5 */
11935   {
11936     "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
11937   },
11938
11939   /* db_4  6 */
11940   {
11941     "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
11942     "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
11943   },
11944
11945   /* de_3  7 */
11946   {
11947     "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
11948   },
11949
11950   /* df_4  8 */
11951   {
11952     "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
11953   },
11954 };
11955
11956 static void
11957 swap_operand (void)
11958 {
11959   mnemonicendp[0] = '.';
11960   mnemonicendp[1] = 's';
11961   mnemonicendp += 2;
11962 }
11963
11964 static void
11965 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED,
11966                int sizeflag ATTRIBUTE_UNUSED)
11967 {
11968   /* Skip mod/rm byte.  */
11969   MODRM_CHECK;
11970   codep++;
11971 }
11972
11973 static void
11974 dofloat (int sizeflag)
11975 {
11976   const struct dis386 *dp;
11977   unsigned char floatop;
11978
11979   floatop = codep[-1];
11980
11981   if (modrm.mod != 3)
11982     {
11983       int fp_indx = (floatop - 0xd8) * 8 + modrm.reg;
11984
11985       putop (float_mem[fp_indx], sizeflag);
11986       obufp = op_out[0];
11987       op_ad = 2;
11988       OP_E (float_mem_mode[fp_indx], sizeflag);
11989       return;
11990     }
11991   /* Skip mod/rm byte.  */
11992   MODRM_CHECK;
11993   codep++;
11994
11995   dp = &float_reg[floatop - 0xd8][modrm.reg];
11996   if (dp->name == NULL)
11997     {
11998       putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag);
11999
12000       /* Instruction fnstsw is only one with strange arg.  */
12001       if (floatop == 0xdf && codep[-1] == 0xe0)
12002         strcpy (op_out[0], names16[0]);
12003     }
12004   else
12005     {
12006       putop (dp->name, sizeflag);
12007
12008       obufp = op_out[0];
12009       op_ad = 2;
12010       if (dp->op[0].rtn)
12011         (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag);
12012
12013       obufp = op_out[1];
12014       op_ad = 1;
12015       if (dp->op[1].rtn)
12016         (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag);
12017     }
12018 }
12019
12020 static void
12021 OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12022 {
12023   oappend ("%st" + intel_syntax);
12024 }
12025
12026 static void
12027 OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12028 {
12029   sprintf (scratchbuf, "%%st(%d)", modrm.rm);
12030   oappend (scratchbuf + intel_syntax);
12031 }
12032
12033 /* Capital letters in template are macros.  */
12034 static int
12035 putop (const char *in_template, int sizeflag)
12036 {
12037   const char *p;
12038   int alt = 0;
12039   int cond = 1;
12040   unsigned int l = 0, len = 1;
12041   char last[4];
12042
12043 #define SAVE_LAST(c)                    \
12044   if (l < len && l < sizeof (last))     \
12045     last[l++] = c;                      \
12046   else                                  \
12047     abort ();
12048
12049   for (p = in_template; *p; p++)
12050     {
12051       switch (*p)
12052         {
12053         default:
12054           *obufp++ = *p;
12055           break;
12056         case '%':
12057           len++;
12058           break;
12059         case '!':
12060           cond = 0;
12061           break;
12062         case '{':
12063           alt = 0;
12064           if (intel_syntax)
12065             {
12066               while (*++p != '|')
12067                 if (*p == '}' || *p == '\0')
12068                   abort ();
12069             }
12070           /* Fall through.  */
12071         case 'I':
12072           alt = 1;
12073           continue;
12074         case '|':
12075           while (*++p != '}')
12076             {
12077               if (*p == '\0')
12078                 abort ();
12079             }
12080           break;
12081         case '}':
12082           break;
12083         case 'A':
12084           if (intel_syntax)
12085             break;
12086           if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
12087             *obufp++ = 'b';
12088           break;
12089         case 'B':
12090           if (l == 0 && len == 1)
12091             {
12092 case_B:
12093               if (intel_syntax)
12094                 break;
12095               if (sizeflag & SUFFIX_ALWAYS)
12096                 *obufp++ = 'b';
12097             }
12098           else
12099             {
12100               if (l != 1
12101                   || len != 2
12102                   || last[0] != 'L')
12103                 {
12104                   SAVE_LAST (*p);
12105                   break;
12106                 }
12107
12108               if (address_mode == mode_64bit
12109                   && !(prefixes & PREFIX_ADDR))
12110                 {
12111                   *obufp++ = 'a';
12112                   *obufp++ = 'b';
12113                   *obufp++ = 's';
12114                 }
12115
12116               goto case_B;
12117             }
12118           break;
12119         case 'C':
12120           if (intel_syntax && !alt)
12121             break;
12122           if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
12123             {
12124               if (sizeflag & DFLAG)
12125                 *obufp++ = intel_syntax ? 'd' : 'l';
12126               else
12127                 *obufp++ = intel_syntax ? 'w' : 's';
12128               used_prefixes |= (prefixes & PREFIX_DATA);
12129             }
12130           break;
12131         case 'D':
12132           if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
12133             break;
12134           USED_REX (REX_W);
12135           if (modrm.mod == 3)
12136             {
12137               if (rex & REX_W)
12138                 *obufp++ = 'q';
12139               else
12140                 {
12141                   if (sizeflag & DFLAG)
12142                     *obufp++ = intel_syntax ? 'd' : 'l';
12143                   else
12144                     *obufp++ = 'w';
12145                   used_prefixes |= (prefixes & PREFIX_DATA);
12146                 }
12147             }
12148           else
12149             *obufp++ = 'w';
12150           break;
12151         case 'E':               /* For jcxz/jecxz */
12152           if (address_mode == mode_64bit)
12153             {
12154               if (sizeflag & AFLAG)
12155                 *obufp++ = 'r';
12156               else
12157                 *obufp++ = 'e';
12158             }
12159           else
12160             if (sizeflag & AFLAG)
12161               *obufp++ = 'e';
12162           used_prefixes |= (prefixes & PREFIX_ADDR);
12163           break;
12164         case 'F':
12165           if (intel_syntax)
12166             break;
12167           if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
12168             {
12169               if (sizeflag & AFLAG)
12170                 *obufp++ = address_mode == mode_64bit ? 'q' : 'l';
12171               else
12172                 *obufp++ = address_mode == mode_64bit ? 'l' : 'w';
12173               used_prefixes |= (prefixes & PREFIX_ADDR);
12174             }
12175           break;
12176         case 'G':
12177           if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS)))
12178             break;
12179           if ((rex & REX_W) || (sizeflag & DFLAG))
12180             *obufp++ = 'l';
12181           else
12182             *obufp++ = 'w';
12183           if (!(rex & REX_W))
12184             used_prefixes |= (prefixes & PREFIX_DATA);
12185           break;
12186         case 'H':
12187           if (intel_syntax)
12188             break;
12189           if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS
12190               || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS)
12191             {
12192               used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS);
12193               *obufp++ = ',';
12194               *obufp++ = 'p';
12195               if (prefixes & PREFIX_DS)
12196                 *obufp++ = 't';
12197               else
12198                 *obufp++ = 'n';
12199             }
12200           break;
12201         case 'J':
12202           if (intel_syntax)
12203             break;
12204           *obufp++ = 'l';
12205           break;
12206         case 'K':
12207           USED_REX (REX_W);
12208           if (rex & REX_W)
12209             *obufp++ = 'q';
12210           else
12211             *obufp++ = 'd';
12212           break;
12213         case 'Z':
12214           if (intel_syntax)
12215             break;
12216           if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS))
12217             {
12218               *obufp++ = 'q';
12219               break;
12220             }
12221           /* Fall through.  */
12222           goto case_L;
12223         case 'L':
12224           if (l != 0 || len != 1)
12225             {
12226               SAVE_LAST (*p);
12227               break;
12228             }
12229 case_L:
12230           if (intel_syntax)
12231             break;
12232           if (sizeflag & SUFFIX_ALWAYS)
12233             *obufp++ = 'l';
12234           break;
12235         case 'M':
12236           if (intel_mnemonic != cond)
12237             *obufp++ = 'r';
12238           break;
12239         case 'N':
12240           if ((prefixes & PREFIX_FWAIT) == 0)
12241             *obufp++ = 'n';
12242           else
12243             used_prefixes |= PREFIX_FWAIT;
12244           break;
12245         case 'O':
12246           USED_REX (REX_W);
12247           if (rex & REX_W)
12248             *obufp++ = 'o';
12249           else if (intel_syntax && (sizeflag & DFLAG))
12250             *obufp++ = 'q';
12251           else
12252             *obufp++ = 'd';
12253           if (!(rex & REX_W))
12254             used_prefixes |= (prefixes & PREFIX_DATA);
12255           break;
12256         case 'T':
12257           if (intel_syntax)
12258             break;
12259           if (address_mode == mode_64bit && (sizeflag & DFLAG))
12260             {
12261               *obufp++ = 'q';
12262               break;
12263             }
12264           /* Fall through.  */
12265         case 'P':
12266           if (intel_syntax)
12267             break;
12268           if ((prefixes & PREFIX_DATA)
12269               || (rex & REX_W)
12270               || (sizeflag & SUFFIX_ALWAYS))
12271             {
12272               USED_REX (REX_W);
12273               if (rex & REX_W)
12274                 *obufp++ = 'q';
12275               else
12276                 {
12277                    if (sizeflag & DFLAG)
12278                       *obufp++ = 'l';
12279                    else
12280                      *obufp++ = 'w';
12281                    used_prefixes |= (prefixes & PREFIX_DATA);
12282                 }
12283             }
12284           break;
12285         case 'U':
12286           if (intel_syntax)
12287             break;
12288           if (address_mode == mode_64bit && (sizeflag & DFLAG))
12289             {
12290               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
12291                 *obufp++ = 'q';
12292               break;
12293             }
12294           /* Fall through.  */
12295           goto case_Q;
12296         case 'Q':
12297           if (l == 0 && len == 1)
12298             {
12299 case_Q:
12300               if (intel_syntax && !alt)
12301                 break;
12302               USED_REX (REX_W);
12303               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
12304                 {
12305                   if (rex & REX_W)
12306                     *obufp++ = 'q';
12307                   else
12308                     {
12309                       if (sizeflag & DFLAG)
12310                         *obufp++ = intel_syntax ? 'd' : 'l';
12311                       else
12312                         *obufp++ = 'w';
12313                       used_prefixes |= (prefixes & PREFIX_DATA);
12314                     }
12315                 }
12316             }
12317           else
12318             {
12319               if (l != 1 || len != 2 || last[0] != 'L')
12320                 {
12321                   SAVE_LAST (*p);
12322                   break;
12323                 }
12324               if (intel_syntax
12325                   || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
12326                 break;
12327               if ((rex & REX_W))
12328                 {
12329                   USED_REX (REX_W);
12330                   *obufp++ = 'q';
12331                 }
12332               else
12333                 *obufp++ = 'l';
12334             }
12335           break;
12336         case 'R':
12337           USED_REX (REX_W);
12338           if (rex & REX_W)
12339             *obufp++ = 'q';
12340           else if (sizeflag & DFLAG)
12341             {
12342               if (intel_syntax)
12343                   *obufp++ = 'd';
12344               else
12345                   *obufp++ = 'l';
12346             }
12347           else
12348             *obufp++ = 'w';
12349           if (intel_syntax && !p[1]
12350               && ((rex & REX_W) || (sizeflag & DFLAG)))
12351             *obufp++ = 'e';
12352           if (!(rex & REX_W))
12353             used_prefixes |= (prefixes & PREFIX_DATA);
12354           break;
12355         case 'V':
12356           if (l == 0 && len == 1)
12357             {
12358               if (intel_syntax)
12359                 break;
12360               if (address_mode == mode_64bit && (sizeflag & DFLAG))
12361                 {
12362                   if (sizeflag & SUFFIX_ALWAYS)
12363                     *obufp++ = 'q';
12364                   break;
12365                 }
12366             }
12367           else
12368             {
12369               if (l != 1
12370                   || len != 2
12371                   || last[0] != 'L')
12372                 {
12373                   SAVE_LAST (*p);
12374                   break;
12375                 }
12376
12377               if (rex & REX_W)
12378                 {
12379                   *obufp++ = 'a';
12380                   *obufp++ = 'b';
12381                   *obufp++ = 's';
12382                 }
12383             }
12384           /* Fall through.  */
12385           goto case_S;
12386         case 'S':
12387           if (l == 0 && len == 1)
12388             {
12389 case_S:
12390               if (intel_syntax)
12391                 break;
12392               if (sizeflag & SUFFIX_ALWAYS)
12393                 {
12394                   if (rex & REX_W)
12395                     *obufp++ = 'q';
12396                   else
12397                     {
12398                       if (sizeflag & DFLAG)
12399                         *obufp++ = 'l';
12400                       else
12401                         *obufp++ = 'w';
12402                       used_prefixes |= (prefixes & PREFIX_DATA);
12403                     }
12404                 }
12405             }
12406           else
12407             {
12408               if (l != 1
12409                   || len != 2
12410                   || last[0] != 'L')
12411                 {
12412                   SAVE_LAST (*p);
12413                   break;
12414                 }
12415
12416               if (address_mode == mode_64bit
12417                   && !(prefixes & PREFIX_ADDR))
12418                 {
12419                   *obufp++ = 'a';
12420                   *obufp++ = 'b';
12421                   *obufp++ = 's';
12422                 }
12423
12424               goto case_S;
12425             }
12426           break;
12427         case 'X':
12428           if (l != 0 || len != 1)
12429             {
12430               SAVE_LAST (*p);
12431               break;
12432             }
12433           if (need_vex && vex.prefix)
12434             {
12435               if (vex.prefix == DATA_PREFIX_OPCODE)
12436                 *obufp++ = 'd';
12437               else
12438                 *obufp++ = 's';
12439             }
12440           else
12441             {
12442               if (prefixes & PREFIX_DATA)
12443                 *obufp++ = 'd';
12444               else
12445                 *obufp++ = 's';
12446               used_prefixes |= (prefixes & PREFIX_DATA);
12447             }
12448           break;
12449         case 'Y':
12450           if (l == 0 && len == 1)
12451             {
12452               if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
12453                 break;
12454               if (rex & REX_W)
12455                 {
12456                   USED_REX (REX_W);
12457                   *obufp++ = 'q';
12458                 }
12459               break;
12460             }
12461           else
12462             {
12463               if (l != 1 || len != 2 || last[0] != 'X')
12464                 {
12465                   SAVE_LAST (*p);
12466                   break;
12467                 }
12468               if (!need_vex)
12469                 abort ();
12470               if (intel_syntax
12471                   || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
12472                 break;
12473               switch (vex.length)
12474                 {
12475                 case 128:
12476                   *obufp++ = 'x';
12477                   break;
12478                 case 256:
12479                   *obufp++ = 'y';
12480                   break;
12481                 default:
12482                   abort ();
12483                 }
12484             }
12485           break;
12486         case 'W':
12487           if (l == 0 && len == 1)
12488             {
12489               /* operand size flag for cwtl, cbtw */
12490               USED_REX (REX_W);
12491               if (rex & REX_W)
12492                 {
12493                   if (intel_syntax)
12494                     *obufp++ = 'd';
12495                   else
12496                     *obufp++ = 'l';
12497                 }
12498               else if (sizeflag & DFLAG)
12499                 *obufp++ = 'w';
12500               else
12501                 *obufp++ = 'b';
12502               if (!(rex & REX_W))
12503                 used_prefixes |= (prefixes & PREFIX_DATA);
12504             }
12505           else
12506             {
12507               if (l != 1 || len != 2 || last[0] != 'X')
12508                 {
12509                   SAVE_LAST (*p);
12510                   break;
12511                 }
12512               if (!need_vex)
12513                 abort ();
12514               *obufp++ = vex.w ? 'd': 's';
12515             }
12516           break;
12517         }
12518       alt = 0;
12519     }
12520   *obufp = 0;
12521   mnemonicendp = obufp;
12522   return 0;
12523 }
12524
12525 static void
12526 oappend (const char *s)
12527 {
12528   obufp = stpcpy (obufp, s);
12529 }
12530
12531 static void
12532 append_seg (void)
12533 {
12534   if (prefixes & PREFIX_CS)
12535     {
12536       used_prefixes |= PREFIX_CS;
12537       oappend ("%cs:" + intel_syntax);
12538     }
12539   if (prefixes & PREFIX_DS)
12540     {
12541       used_prefixes |= PREFIX_DS;
12542       oappend ("%ds:" + intel_syntax);
12543     }
12544   if (prefixes & PREFIX_SS)
12545     {
12546       used_prefixes |= PREFIX_SS;
12547       oappend ("%ss:" + intel_syntax);
12548     }
12549   if (prefixes & PREFIX_ES)
12550     {
12551       used_prefixes |= PREFIX_ES;
12552       oappend ("%es:" + intel_syntax);
12553     }
12554   if (prefixes & PREFIX_FS)
12555     {
12556       used_prefixes |= PREFIX_FS;
12557       oappend ("%fs:" + intel_syntax);
12558     }
12559   if (prefixes & PREFIX_GS)
12560     {
12561       used_prefixes |= PREFIX_GS;
12562       oappend ("%gs:" + intel_syntax);
12563     }
12564 }
12565
12566 static void
12567 OP_indirE (int bytemode, int sizeflag)
12568 {
12569   if (!intel_syntax)
12570     oappend ("*");
12571   OP_E (bytemode, sizeflag);
12572 }
12573
12574 static void
12575 print_operand_value (char *buf, int hex, bfd_vma disp)
12576 {
12577   if (address_mode == mode_64bit)
12578     {
12579       if (hex)
12580         {
12581           char tmp[30];
12582           int i;
12583           buf[0] = '0';
12584           buf[1] = 'x';
12585           sprintf_vma (tmp, disp);
12586           for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++);
12587           strcpy (buf + 2, tmp + i);
12588         }
12589       else
12590         {
12591           bfd_signed_vma v = disp;
12592           char tmp[30];
12593           int i;
12594           if (v < 0)
12595             {
12596               *(buf++) = '-';
12597               v = -disp;
12598               /* Check for possible overflow on 0x8000000000000000.  */
12599               if (v < 0)
12600                 {
12601                   strcpy (buf, "9223372036854775808");
12602                   return;
12603                 }
12604             }
12605           if (!v)
12606             {
12607               strcpy (buf, "0");
12608               return;
12609             }
12610
12611           i = 0;
12612           tmp[29] = 0;
12613           while (v)
12614             {
12615               tmp[28 - i] = (v % 10) + '0';
12616               v /= 10;
12617               i++;
12618             }
12619           strcpy (buf, tmp + 29 - i);
12620         }
12621     }
12622   else
12623     {
12624       if (hex)
12625         sprintf (buf, "0x%x", (unsigned int) disp);
12626       else
12627         sprintf (buf, "%d", (int) disp);
12628     }
12629 }
12630
12631 /* Put DISP in BUF as signed hex number.  */
12632
12633 static void
12634 print_displacement (char *buf, bfd_vma disp)
12635 {
12636   bfd_signed_vma val = disp;
12637   char tmp[30];
12638   int i, j = 0;
12639
12640   if (val < 0)
12641     {
12642       buf[j++] = '-';
12643       val = -disp;
12644
12645       /* Check for possible overflow.  */
12646       if (val < 0)
12647         {
12648           switch (address_mode)
12649             {
12650             case mode_64bit:
12651               strcpy (buf + j, "0x8000000000000000");
12652               break;
12653             case mode_32bit:
12654               strcpy (buf + j, "0x80000000");
12655               break;
12656             case mode_16bit:
12657               strcpy (buf + j, "0x8000");
12658               break;
12659             }
12660           return;
12661         }
12662     }
12663
12664   buf[j++] = '0';
12665   buf[j++] = 'x';
12666
12667   sprintf_vma (tmp, (bfd_vma) val);
12668   for (i = 0; tmp[i] == '0'; i++)
12669     continue;
12670   if (tmp[i] == '\0')
12671     i--;
12672   strcpy (buf + j, tmp + i);
12673 }
12674
12675 static void
12676 intel_operand_size (int bytemode, int sizeflag)
12677 {
12678   switch (bytemode)
12679     {
12680     case b_mode:
12681     case b_swap_mode:
12682     case dqb_mode:
12683       oappend ("BYTE PTR ");
12684       break;
12685     case w_mode:
12686     case dqw_mode:
12687       oappend ("WORD PTR ");
12688       break;
12689     case stack_v_mode:
12690       if (address_mode == mode_64bit && (sizeflag & DFLAG))
12691         {
12692           oappend ("QWORD PTR ");
12693           break;
12694         }
12695       /* FALLTHRU */
12696     case v_mode:
12697     case v_swap_mode:
12698     case dq_mode:
12699       USED_REX (REX_W);
12700       if (rex & REX_W)
12701         oappend ("QWORD PTR ");
12702       else
12703         {
12704           if ((sizeflag & DFLAG) || bytemode == dq_mode)
12705             oappend ("DWORD PTR ");
12706           else
12707             oappend ("WORD PTR ");
12708           used_prefixes |= (prefixes & PREFIX_DATA);
12709         }
12710       break;
12711     case z_mode:
12712       if ((rex & REX_W) || (sizeflag & DFLAG))
12713         *obufp++ = 'D';
12714       oappend ("WORD PTR ");
12715       if (!(rex & REX_W))
12716         used_prefixes |= (prefixes & PREFIX_DATA);
12717       break;
12718     case a_mode:
12719       if (sizeflag & DFLAG)
12720         oappend ("QWORD PTR ");
12721       else
12722         oappend ("DWORD PTR ");
12723       used_prefixes |= (prefixes & PREFIX_DATA);
12724       break;
12725     case d_mode:
12726     case d_scalar_mode:
12727     case d_scalar_swap_mode:
12728     case d_swap_mode:
12729     case dqd_mode:
12730       oappend ("DWORD PTR ");
12731       break;
12732     case q_mode:
12733     case q_scalar_mode:
12734     case q_scalar_swap_mode:
12735     case q_swap_mode:
12736       oappend ("QWORD PTR ");
12737       break;
12738     case m_mode:
12739       if (address_mode == mode_64bit)
12740         oappend ("QWORD PTR ");
12741       else
12742         oappend ("DWORD PTR ");
12743       break;
12744     case f_mode:
12745       if (sizeflag & DFLAG)
12746         oappend ("FWORD PTR ");
12747       else
12748         oappend ("DWORD PTR ");
12749       used_prefixes |= (prefixes & PREFIX_DATA);
12750       break;
12751     case t_mode:
12752       oappend ("TBYTE PTR ");
12753       break;
12754     case x_mode:
12755     case x_swap_mode:
12756       if (need_vex)
12757         {
12758           switch (vex.length)
12759             {
12760             case 128:
12761               oappend ("XMMWORD PTR ");
12762               break;
12763             case 256:
12764               oappend ("YMMWORD PTR ");
12765               break;
12766             default:
12767               abort ();
12768             }
12769         }
12770       else
12771         oappend ("XMMWORD PTR ");
12772       break;
12773     case xmm_mode:
12774       oappend ("XMMWORD PTR ");
12775       break;
12776     case xmmq_mode:
12777       if (!need_vex)
12778         abort ();
12779
12780       switch (vex.length)
12781         {
12782         case 128:
12783           oappend ("QWORD PTR ");
12784           break;
12785         case 256:
12786           oappend ("XMMWORD PTR ");
12787           break;
12788         default:
12789           abort ();
12790         }
12791       break;
12792     case ymmq_mode:
12793       if (!need_vex)
12794         abort ();
12795
12796       switch (vex.length)
12797         {
12798         case 128:
12799           oappend ("QWORD PTR ");
12800           break;
12801         case 256:
12802           oappend ("YMMWORD PTR ");
12803           break;
12804         default:
12805           abort ();
12806         }
12807       break;
12808     case o_mode:
12809       oappend ("OWORD PTR ");
12810       break;
12811     case vex_w_dq_mode:
12812     case vex_scalar_w_dq_mode:
12813       if (!need_vex)
12814         abort ();
12815
12816       if (vex.w)
12817         oappend ("QWORD PTR ");
12818       else
12819         oappend ("DWORD PTR ");
12820       break;
12821     default:
12822       break;
12823     }
12824 }
12825
12826 static void
12827 OP_E_register (int bytemode, int sizeflag)
12828 {
12829   int reg = modrm.rm;
12830   const char **names;
12831
12832   USED_REX (REX_B);
12833   if ((rex & REX_B))
12834     reg += 8;
12835
12836   if ((sizeflag & SUFFIX_ALWAYS)
12837       && (bytemode == b_swap_mode || bytemode == v_swap_mode))
12838     swap_operand ();
12839
12840   switch (bytemode)
12841     {
12842     case b_mode:
12843     case b_swap_mode:
12844       USED_REX (0);
12845       if (rex)
12846         names = names8rex;
12847       else
12848         names = names8;
12849       break;
12850     case w_mode:
12851       names = names16;
12852       break;
12853     case d_mode:
12854       names = names32;
12855       break;
12856     case q_mode:
12857       names = names64;
12858       break;
12859     case m_mode:
12860       names = address_mode == mode_64bit ? names64 : names32;
12861       break;
12862     case stack_v_mode:
12863       if (address_mode == mode_64bit && (sizeflag & DFLAG))
12864         {
12865           names = names64;
12866           break;
12867         }
12868       bytemode = v_mode;
12869       /* FALLTHRU */
12870     case v_mode:
12871     case v_swap_mode:
12872     case dq_mode:
12873     case dqb_mode:
12874     case dqd_mode:
12875     case dqw_mode:
12876       USED_REX (REX_W);
12877       if (rex & REX_W)
12878         names = names64;
12879       else
12880         {
12881           if ((sizeflag & DFLAG)
12882               || (bytemode != v_mode
12883                   && bytemode != v_swap_mode))
12884             names = names32;
12885           else
12886             names = names16;
12887           used_prefixes |= (prefixes & PREFIX_DATA);
12888         }
12889       break;
12890     case 0:
12891       return;
12892     default:
12893       oappend (INTERNAL_DISASSEMBLER_ERROR);
12894       return;
12895     }
12896   oappend (names[reg]);
12897 }
12898
12899 static void
12900 OP_E_memory (int bytemode, int sizeflag)
12901 {
12902   bfd_vma disp = 0;
12903   int add = (rex & REX_B) ? 8 : 0;
12904   int riprel = 0;
12905
12906   USED_REX (REX_B);
12907   if (intel_syntax)
12908     intel_operand_size (bytemode, sizeflag);
12909   append_seg ();
12910
12911   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
12912     {
12913       /* 32/64 bit address mode */
12914       int havedisp;
12915       int havesib;
12916       int havebase;
12917       int haveindex;
12918       int needindex;
12919       int base, rbase;
12920       int vindex = 0;
12921       int scale = 0;
12922
12923       havesib = 0;
12924       havebase = 1;
12925       haveindex = 0;
12926       base = modrm.rm;
12927
12928       if (base == 4)
12929         {
12930           havesib = 1;
12931           FETCH_DATA (the_info, codep + 1);
12932           vindex = (*codep >> 3) & 7;
12933           scale = (*codep >> 6) & 3;
12934           base = *codep & 7;
12935           USED_REX (REX_X);
12936           if (rex & REX_X)
12937             vindex += 8;
12938           haveindex = vindex != 4;
12939           codep++;
12940         }
12941       rbase = base + add;
12942
12943       switch (modrm.mod)
12944         {
12945         case 0:
12946           if (base == 5)
12947             {
12948               havebase = 0;
12949               if (address_mode == mode_64bit && !havesib)
12950                 riprel = 1;
12951               disp = get32s ();
12952             }
12953           break;
12954         case 1:
12955           FETCH_DATA (the_info, codep + 1);
12956           disp = *codep++;
12957           if ((disp & 0x80) != 0)
12958             disp -= 0x100;
12959           break;
12960         case 2:
12961           disp = get32s ();
12962           break;
12963         }
12964
12965       /* In 32bit mode, we need index register to tell [offset] from
12966          [eiz*1 + offset].  */
12967       needindex = (havesib
12968                    && !havebase
12969                    && !haveindex
12970                    && address_mode == mode_32bit);
12971       havedisp = (havebase
12972                   || needindex
12973                   || (havesib && (haveindex || scale != 0)));
12974
12975       if (!intel_syntax)
12976         if (modrm.mod != 0 || base == 5)
12977           {
12978             if (havedisp || riprel)
12979               print_displacement (scratchbuf, disp);
12980             else
12981               print_operand_value (scratchbuf, 1, disp);
12982             oappend (scratchbuf);
12983             if (riprel)
12984               {
12985                 set_op (disp, 1);
12986                 oappend (sizeflag & AFLAG ? "(%rip)" : "(%eip)");
12987               }
12988           }
12989
12990       if (havebase || haveindex || riprel)
12991         used_prefixes |= PREFIX_ADDR;
12992
12993       if (havedisp || (intel_syntax && riprel))
12994         {
12995           *obufp++ = open_char;
12996           if (intel_syntax && riprel)
12997             {
12998               set_op (disp, 1);
12999               oappend (sizeflag & AFLAG ? "rip" : "eip");
13000             }
13001           *obufp = '\0';
13002           if (havebase)
13003             oappend (address_mode == mode_64bit && (sizeflag & AFLAG)
13004                      ? names64[rbase] : names32[rbase]);
13005           if (havesib)
13006             {
13007               /* ESP/RSP won't allow index.  If base isn't ESP/RSP,
13008                  print index to tell base + index from base.  */
13009               if (scale != 0
13010                   || needindex
13011                   || haveindex
13012                   || (havebase && base != ESP_REG_NUM))
13013                 {
13014                   if (!intel_syntax || havebase)
13015                     {
13016                       *obufp++ = separator_char;
13017                       *obufp = '\0';
13018                     }
13019                   if (haveindex)
13020                     oappend (address_mode == mode_64bit
13021                              && (sizeflag & AFLAG)
13022                              ? names64[vindex] : names32[vindex]);
13023                   else
13024                     oappend (address_mode == mode_64bit
13025                              && (sizeflag & AFLAG)
13026                              ? index64 : index32);
13027
13028                   *obufp++ = scale_char;
13029                   *obufp = '\0';
13030                   sprintf (scratchbuf, "%d", 1 << scale);
13031                   oappend (scratchbuf);
13032                 }
13033             }
13034           if (intel_syntax
13035               && (disp || modrm.mod != 0 || base == 5))
13036             {
13037               if (!havedisp || (bfd_signed_vma) disp >= 0)
13038                 {
13039                   *obufp++ = '+';
13040                   *obufp = '\0';
13041                 }
13042               else if (modrm.mod != 1 && disp != -disp)
13043                 {
13044                   *obufp++ = '-';
13045                   *obufp = '\0';
13046                   disp = - (bfd_signed_vma) disp;
13047                 }
13048
13049               if (havedisp)
13050                 print_displacement (scratchbuf, disp);
13051               else
13052                 print_operand_value (scratchbuf, 1, disp);
13053               oappend (scratchbuf);
13054             }
13055
13056           *obufp++ = close_char;
13057           *obufp = '\0';
13058         }
13059       else if (intel_syntax)
13060         {
13061           if (modrm.mod != 0 || base == 5)
13062             {
13063               if (prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
13064                               | PREFIX_ES | PREFIX_FS | PREFIX_GS))
13065                 ;
13066               else
13067                 {
13068                   oappend (names_seg[ds_reg - es_reg]);
13069                   oappend (":");
13070                 }
13071               print_operand_value (scratchbuf, 1, disp);
13072               oappend (scratchbuf);
13073             }
13074         }
13075     }
13076   else
13077     {
13078       /* 16 bit address mode */
13079       used_prefixes |= prefixes & PREFIX_ADDR;
13080       switch (modrm.mod)
13081         {
13082         case 0:
13083           if (modrm.rm == 6)
13084             {
13085               disp = get16 ();
13086               if ((disp & 0x8000) != 0)
13087                 disp -= 0x10000;
13088             }
13089           break;
13090         case 1:
13091           FETCH_DATA (the_info, codep + 1);
13092           disp = *codep++;
13093           if ((disp & 0x80) != 0)
13094             disp -= 0x100;
13095           break;
13096         case 2:
13097           disp = get16 ();
13098           if ((disp & 0x8000) != 0)
13099             disp -= 0x10000;
13100           break;
13101         }
13102
13103       if (!intel_syntax)
13104         if (modrm.mod != 0 || modrm.rm == 6)
13105           {
13106             print_displacement (scratchbuf, disp);
13107             oappend (scratchbuf);
13108           }
13109
13110       if (modrm.mod != 0 || modrm.rm != 6)
13111         {
13112           *obufp++ = open_char;
13113           *obufp = '\0';
13114           oappend (index16[modrm.rm]);
13115           if (intel_syntax
13116               && (disp || modrm.mod != 0 || modrm.rm == 6))
13117             {
13118               if ((bfd_signed_vma) disp >= 0)
13119                 {
13120                   *obufp++ = '+';
13121                   *obufp = '\0';
13122                 }
13123               else if (modrm.mod != 1)
13124                 {
13125                   *obufp++ = '-';
13126                   *obufp = '\0';
13127                   disp = - (bfd_signed_vma) disp;
13128                 }
13129
13130               print_displacement (scratchbuf, disp);
13131               oappend (scratchbuf);
13132             }
13133
13134           *obufp++ = close_char;
13135           *obufp = '\0';
13136         }
13137       else if (intel_syntax)
13138         {
13139           if (prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
13140                           | PREFIX_ES | PREFIX_FS | PREFIX_GS))
13141             ;
13142           else
13143             {
13144               oappend (names_seg[ds_reg - es_reg]);
13145               oappend (":");
13146             }
13147           print_operand_value (scratchbuf, 1, disp & 0xffff);
13148           oappend (scratchbuf);
13149         }
13150     }
13151 }
13152
13153 static void
13154 OP_E (int bytemode, int sizeflag)
13155 {
13156   /* Skip mod/rm byte.  */
13157   MODRM_CHECK;
13158   codep++;
13159
13160   if (modrm.mod == 3)
13161     OP_E_register (bytemode, sizeflag);
13162   else
13163     OP_E_memory (bytemode, sizeflag);
13164 }
13165
13166 static void
13167 OP_G (int bytemode, int sizeflag)
13168 {
13169   int add = 0;
13170   USED_REX (REX_R);
13171   if (rex & REX_R)
13172     add += 8;
13173   switch (bytemode)
13174     {
13175     case b_mode:
13176       USED_REX (0);
13177       if (rex)
13178         oappend (names8rex[modrm.reg + add]);
13179       else
13180         oappend (names8[modrm.reg + add]);
13181       break;
13182     case w_mode:
13183       oappend (names16[modrm.reg + add]);
13184       break;
13185     case d_mode:
13186       oappend (names32[modrm.reg + add]);
13187       break;
13188     case q_mode:
13189       oappend (names64[modrm.reg + add]);
13190       break;
13191     case v_mode:
13192     case dq_mode:
13193     case dqb_mode:
13194     case dqd_mode:
13195     case dqw_mode:
13196       USED_REX (REX_W);
13197       if (rex & REX_W)
13198         oappend (names64[modrm.reg + add]);
13199       else
13200         {
13201           if ((sizeflag & DFLAG) || bytemode != v_mode)
13202             oappend (names32[modrm.reg + add]);
13203           else
13204             oappend (names16[modrm.reg + add]);
13205           used_prefixes |= (prefixes & PREFIX_DATA);
13206         }
13207       break;
13208     case m_mode:
13209       if (address_mode == mode_64bit)
13210         oappend (names64[modrm.reg + add]);
13211       else
13212         oappend (names32[modrm.reg + add]);
13213       break;
13214     default:
13215       oappend (INTERNAL_DISASSEMBLER_ERROR);
13216       break;
13217     }
13218 }
13219
13220 static bfd_vma
13221 get64 (void)
13222 {
13223   bfd_vma x;
13224 #ifdef BFD64
13225   unsigned int a;
13226   unsigned int b;
13227
13228   FETCH_DATA (the_info, codep + 8);
13229   a = *codep++ & 0xff;
13230   a |= (*codep++ & 0xff) << 8;
13231   a |= (*codep++ & 0xff) << 16;
13232   a |= (*codep++ & 0xff) << 24;
13233   b = *codep++ & 0xff;
13234   b |= (*codep++ & 0xff) << 8;
13235   b |= (*codep++ & 0xff) << 16;
13236   b |= (*codep++ & 0xff) << 24;
13237   x = a + ((bfd_vma) b << 32);
13238 #else
13239   abort ();
13240   x = 0;
13241 #endif
13242   return x;
13243 }
13244
13245 static bfd_signed_vma
13246 get32 (void)
13247 {
13248   bfd_signed_vma x = 0;
13249
13250   FETCH_DATA (the_info, codep + 4);
13251   x = *codep++ & (bfd_signed_vma) 0xff;
13252   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
13253   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
13254   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
13255   return x;
13256 }
13257
13258 static bfd_signed_vma
13259 get32s (void)
13260 {
13261   bfd_signed_vma x = 0;
13262
13263   FETCH_DATA (the_info, codep + 4);
13264   x = *codep++ & (bfd_signed_vma) 0xff;
13265   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
13266   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
13267   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
13268
13269   x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31);
13270
13271   return x;
13272 }
13273
13274 static int
13275 get16 (void)
13276 {
13277   int x = 0;
13278
13279   FETCH_DATA (the_info, codep + 2);
13280   x = *codep++ & 0xff;
13281   x |= (*codep++ & 0xff) << 8;
13282   return x;
13283 }
13284
13285 static void
13286 set_op (bfd_vma op, int riprel)
13287 {
13288   op_index[op_ad] = op_ad;
13289   if (address_mode == mode_64bit)
13290     {
13291       op_address[op_ad] = op;
13292       op_riprel[op_ad] = riprel;
13293     }
13294   else
13295     {
13296       /* Mask to get a 32-bit address.  */
13297       op_address[op_ad] = op & 0xffffffff;
13298       op_riprel[op_ad] = riprel & 0xffffffff;
13299     }
13300 }
13301
13302 static void
13303 OP_REG (int code, int sizeflag)
13304 {
13305   const char *s;
13306   int add;
13307   USED_REX (REX_B);
13308   if (rex & REX_B)
13309     add = 8;
13310   else
13311     add = 0;
13312
13313   switch (code)
13314     {
13315     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
13316     case sp_reg: case bp_reg: case si_reg: case di_reg:
13317       s = names16[code - ax_reg + add];
13318       break;
13319     case es_reg: case ss_reg: case cs_reg:
13320     case ds_reg: case fs_reg: case gs_reg:
13321       s = names_seg[code - es_reg + add];
13322       break;
13323     case al_reg: case ah_reg: case cl_reg: case ch_reg:
13324     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
13325       USED_REX (0);
13326       if (rex)
13327         s = names8rex[code - al_reg + add];
13328       else
13329         s = names8[code - al_reg];
13330       break;
13331     case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
13332     case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
13333       if (address_mode == mode_64bit && (sizeflag & DFLAG))
13334         {
13335           s = names64[code - rAX_reg + add];
13336           break;
13337         }
13338       code += eAX_reg - rAX_reg;
13339       /* Fall through.  */
13340     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
13341     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
13342       USED_REX (REX_W);
13343       if (rex & REX_W)
13344         s = names64[code - eAX_reg + add];
13345       else
13346         {
13347           if (sizeflag & DFLAG)
13348             s = names32[code - eAX_reg + add];
13349           else
13350             s = names16[code - eAX_reg + add];
13351           used_prefixes |= (prefixes & PREFIX_DATA);
13352         }
13353       break;
13354     default:
13355       s = INTERNAL_DISASSEMBLER_ERROR;
13356       break;
13357     }
13358   oappend (s);
13359 }
13360
13361 static void
13362 OP_IMREG (int code, int sizeflag)
13363 {
13364   const char *s;
13365
13366   switch (code)
13367     {
13368     case indir_dx_reg:
13369       if (intel_syntax)
13370         s = "dx";
13371       else
13372         s = "(%dx)";
13373       break;
13374     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
13375     case sp_reg: case bp_reg: case si_reg: case di_reg:
13376       s = names16[code - ax_reg];
13377       break;
13378     case es_reg: case ss_reg: case cs_reg:
13379     case ds_reg: case fs_reg: case gs_reg:
13380       s = names_seg[code - es_reg];
13381       break;
13382     case al_reg: case ah_reg: case cl_reg: case ch_reg:
13383     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
13384       USED_REX (0);
13385       if (rex)
13386         s = names8rex[code - al_reg];
13387       else
13388         s = names8[code - al_reg];
13389       break;
13390     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
13391     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
13392       USED_REX (REX_W);
13393       if (rex & REX_W)
13394         s = names64[code - eAX_reg];
13395       else
13396         {
13397           if (sizeflag & DFLAG)
13398             s = names32[code - eAX_reg];
13399           else
13400             s = names16[code - eAX_reg];
13401           used_prefixes |= (prefixes & PREFIX_DATA);
13402         }
13403       break;
13404     case z_mode_ax_reg:
13405       if ((rex & REX_W) || (sizeflag & DFLAG))
13406         s = *names32;
13407       else
13408         s = *names16;
13409       if (!(rex & REX_W))
13410         used_prefixes |= (prefixes & PREFIX_DATA);
13411       break;
13412     default:
13413       s = INTERNAL_DISASSEMBLER_ERROR;
13414       break;
13415     }
13416   oappend (s);
13417 }
13418
13419 static void
13420 OP_I (int bytemode, int sizeflag)
13421 {
13422   bfd_signed_vma op;
13423   bfd_signed_vma mask = -1;
13424
13425   switch (bytemode)
13426     {
13427     case b_mode:
13428       FETCH_DATA (the_info, codep + 1);
13429       op = *codep++;
13430       mask = 0xff;
13431       break;
13432     case q_mode:
13433       if (address_mode == mode_64bit)
13434         {
13435           op = get32s ();
13436           break;
13437         }
13438       /* Fall through.  */
13439     case v_mode:
13440       USED_REX (REX_W);
13441       if (rex & REX_W)
13442         op = get32s ();
13443       else
13444         {
13445           if (sizeflag & DFLAG)
13446             {
13447               op = get32 ();
13448               mask = 0xffffffff;
13449             }
13450           else
13451             {
13452               op = get16 ();
13453               mask = 0xfffff;
13454             }
13455           used_prefixes |= (prefixes & PREFIX_DATA);
13456         }
13457       break;
13458     case w_mode:
13459       mask = 0xfffff;
13460       op = get16 ();
13461       break;
13462     case const_1_mode:
13463       if (intel_syntax)
13464         oappend ("1");
13465       return;
13466     default:
13467       oappend (INTERNAL_DISASSEMBLER_ERROR);
13468       return;
13469     }
13470
13471   op &= mask;
13472   scratchbuf[0] = '$';
13473   print_operand_value (scratchbuf + 1, 1, op);
13474   oappend (scratchbuf + intel_syntax);
13475   scratchbuf[0] = '\0';
13476 }
13477
13478 static void
13479 OP_I64 (int bytemode, int sizeflag)
13480 {
13481   bfd_signed_vma op;
13482   bfd_signed_vma mask = -1;
13483
13484   if (address_mode != mode_64bit)
13485     {
13486       OP_I (bytemode, sizeflag);
13487       return;
13488     }
13489
13490   switch (bytemode)
13491     {
13492     case b_mode:
13493       FETCH_DATA (the_info, codep + 1);
13494       op = *codep++;
13495       mask = 0xff;
13496       break;
13497     case v_mode:
13498       USED_REX (REX_W);
13499       if (rex & REX_W)
13500         op = get64 ();
13501       else
13502         {
13503           if (sizeflag & DFLAG)
13504             {
13505               op = get32 ();
13506               mask = 0xffffffff;
13507             }
13508           else
13509             {
13510               op = get16 ();
13511               mask = 0xfffff;
13512             }
13513           used_prefixes |= (prefixes & PREFIX_DATA);
13514         }
13515       break;
13516     case w_mode:
13517       mask = 0xfffff;
13518       op = get16 ();
13519       break;
13520     default:
13521       oappend (INTERNAL_DISASSEMBLER_ERROR);
13522       return;
13523     }
13524
13525   op &= mask;
13526   scratchbuf[0] = '$';
13527   print_operand_value (scratchbuf + 1, 1, op);
13528   oappend (scratchbuf + intel_syntax);
13529   scratchbuf[0] = '\0';
13530 }
13531
13532 static void
13533 OP_sI (int bytemode, int sizeflag)
13534 {
13535   bfd_signed_vma op;
13536   bfd_signed_vma mask = -1;
13537
13538   switch (bytemode)
13539     {
13540     case b_mode:
13541       FETCH_DATA (the_info, codep + 1);
13542       op = *codep++;
13543       if ((op & 0x80) != 0)
13544         op -= 0x100;
13545       mask = 0xffffffff;
13546       break;
13547     case v_mode:
13548       USED_REX (REX_W);
13549       if (rex & REX_W)
13550         op = get32s ();
13551       else
13552         {
13553           if (sizeflag & DFLAG)
13554             {
13555               op = get32s ();
13556               mask = 0xffffffff;
13557             }
13558           else
13559             {
13560               mask = 0xffffffff;
13561               op = get16 ();
13562               if ((op & 0x8000) != 0)
13563                 op -= 0x10000;
13564             }
13565           used_prefixes |= (prefixes & PREFIX_DATA);
13566         }
13567       break;
13568     case w_mode:
13569       op = get16 ();
13570       mask = 0xffffffff;
13571       if ((op & 0x8000) != 0)
13572         op -= 0x10000;
13573       break;
13574     default:
13575       oappend (INTERNAL_DISASSEMBLER_ERROR);
13576       return;
13577     }
13578
13579   scratchbuf[0] = '$';
13580   print_operand_value (scratchbuf + 1, 1, op);
13581   oappend (scratchbuf + intel_syntax);
13582 }
13583
13584 static void
13585 OP_J (int bytemode, int sizeflag)
13586 {
13587   bfd_vma disp;
13588   bfd_vma mask = -1;
13589   bfd_vma segment = 0;
13590
13591   switch (bytemode)
13592     {
13593     case b_mode:
13594       FETCH_DATA (the_info, codep + 1);
13595       disp = *codep++;
13596       if ((disp & 0x80) != 0)
13597         disp -= 0x100;
13598       break;
13599     case v_mode:
13600       USED_REX (REX_W);
13601       if ((sizeflag & DFLAG) || (rex & REX_W))
13602         disp = get32s ();
13603       else
13604         {
13605           disp = get16 ();
13606           if ((disp & 0x8000) != 0)
13607             disp -= 0x10000;
13608           /* In 16bit mode, address is wrapped around at 64k within
13609              the same segment.  Otherwise, a data16 prefix on a jump
13610              instruction means that the pc is masked to 16 bits after
13611              the displacement is added!  */
13612           mask = 0xffff;
13613           if ((prefixes & PREFIX_DATA) == 0)
13614             segment = ((start_pc + codep - start_codep)
13615                        & ~((bfd_vma) 0xffff));
13616         }
13617       if (!(rex & REX_W))
13618         used_prefixes |= (prefixes & PREFIX_DATA);
13619       break;
13620     default:
13621       oappend (INTERNAL_DISASSEMBLER_ERROR);
13622       return;
13623     }
13624   disp = ((start_pc + codep - start_codep + disp) & mask) | segment;
13625   set_op (disp, 0);
13626   print_operand_value (scratchbuf, 1, disp);
13627   oappend (scratchbuf);
13628 }
13629
13630 static void
13631 OP_SEG (int bytemode, int sizeflag)
13632 {
13633   if (bytemode == w_mode)
13634     oappend (names_seg[modrm.reg]);
13635   else
13636     OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag);
13637 }
13638
13639 static void
13640 OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag)
13641 {
13642   int seg, offset;
13643
13644   if (sizeflag & DFLAG)
13645     {
13646       offset = get32 ();
13647       seg = get16 ();
13648     }
13649   else
13650     {
13651       offset = get16 ();
13652       seg = get16 ();
13653     }
13654   used_prefixes |= (prefixes & PREFIX_DATA);
13655   if (intel_syntax)
13656     sprintf (scratchbuf, "0x%x:0x%x", seg, offset);
13657   else
13658     sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset);
13659   oappend (scratchbuf);
13660 }
13661
13662 static void
13663 OP_OFF (int bytemode, int sizeflag)
13664 {
13665   bfd_vma off;
13666
13667   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
13668     intel_operand_size (bytemode, sizeflag);
13669   append_seg ();
13670
13671   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
13672     off = get32 ();
13673   else
13674     off = get16 ();
13675
13676   if (intel_syntax)
13677     {
13678       if (!(prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
13679                         | PREFIX_ES | PREFIX_FS | PREFIX_GS)))
13680         {
13681           oappend (names_seg[ds_reg - es_reg]);
13682           oappend (":");
13683         }
13684     }
13685   print_operand_value (scratchbuf, 1, off);
13686   oappend (scratchbuf);
13687 }
13688
13689 static void
13690 OP_OFF64 (int bytemode, int sizeflag)
13691 {
13692   bfd_vma off;
13693
13694   if (address_mode != mode_64bit
13695       || (prefixes & PREFIX_ADDR))
13696     {
13697       OP_OFF (bytemode, sizeflag);
13698       return;
13699     }
13700
13701   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
13702     intel_operand_size (bytemode, sizeflag);
13703   append_seg ();
13704
13705   off = get64 ();
13706
13707   if (intel_syntax)
13708     {
13709       if (!(prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
13710                         | PREFIX_ES | PREFIX_FS | PREFIX_GS)))
13711         {
13712           oappend (names_seg[ds_reg - es_reg]);
13713           oappend (":");
13714         }
13715     }
13716   print_operand_value (scratchbuf, 1, off);
13717   oappend (scratchbuf);
13718 }
13719
13720 static void
13721 ptr_reg (int code, int sizeflag)
13722 {
13723   const char *s;
13724
13725   *obufp++ = open_char;
13726   used_prefixes |= (prefixes & PREFIX_ADDR);
13727   if (address_mode == mode_64bit)
13728     {
13729       if (!(sizeflag & AFLAG))
13730         s = names32[code - eAX_reg];
13731       else
13732         s = names64[code - eAX_reg];
13733     }
13734   else if (sizeflag & AFLAG)
13735     s = names32[code - eAX_reg];
13736   else
13737     s = names16[code - eAX_reg];
13738   oappend (s);
13739   *obufp++ = close_char;
13740   *obufp = 0;
13741 }
13742
13743 static void
13744 OP_ESreg (int code, int sizeflag)
13745 {
13746   if (intel_syntax)
13747     {
13748       switch (codep[-1])
13749         {
13750         case 0x6d:      /* insw/insl */
13751           intel_operand_size (z_mode, sizeflag);
13752           break;
13753         case 0xa5:      /* movsw/movsl/movsq */
13754         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
13755         case 0xab:      /* stosw/stosl */
13756         case 0xaf:      /* scasw/scasl */
13757           intel_operand_size (v_mode, sizeflag);
13758           break;
13759         default:
13760           intel_operand_size (b_mode, sizeflag);
13761         }
13762     }
13763   oappend ("%es:" + intel_syntax);
13764   ptr_reg (code, sizeflag);
13765 }
13766
13767 static void
13768 OP_DSreg (int code, int sizeflag)
13769 {
13770   if (intel_syntax)
13771     {
13772       switch (codep[-1])
13773         {
13774         case 0x6f:      /* outsw/outsl */
13775           intel_operand_size (z_mode, sizeflag);
13776           break;
13777         case 0xa5:      /* movsw/movsl/movsq */
13778         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
13779         case 0xad:      /* lodsw/lodsl/lodsq */
13780           intel_operand_size (v_mode, sizeflag);
13781           break;
13782         default:
13783           intel_operand_size (b_mode, sizeflag);
13784         }
13785     }
13786   if ((prefixes
13787        & (PREFIX_CS
13788           | PREFIX_DS
13789           | PREFIX_SS
13790           | PREFIX_ES
13791           | PREFIX_FS
13792           | PREFIX_GS)) == 0)
13793     prefixes |= PREFIX_DS;
13794   append_seg ();
13795   ptr_reg (code, sizeflag);
13796 }
13797
13798 static void
13799 OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13800 {
13801   int add;
13802   if (rex & REX_R)
13803     {
13804       USED_REX (REX_R);
13805       add = 8;
13806     }
13807   else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK))
13808     {
13809       all_prefixes[last_lock_prefix] = 0;
13810       used_prefixes |= PREFIX_LOCK;
13811       add = 8;
13812     }
13813   else
13814     add = 0;
13815   sprintf (scratchbuf, "%%cr%d", modrm.reg + add);
13816   oappend (scratchbuf + intel_syntax);
13817 }
13818
13819 static void
13820 OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13821 {
13822   int add;
13823   USED_REX (REX_R);
13824   if (rex & REX_R)
13825     add = 8;
13826   else
13827     add = 0;
13828   if (intel_syntax)
13829     sprintf (scratchbuf, "db%d", modrm.reg + add);
13830   else
13831     sprintf (scratchbuf, "%%db%d", modrm.reg + add);
13832   oappend (scratchbuf);
13833 }
13834
13835 static void
13836 OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13837 {
13838   sprintf (scratchbuf, "%%tr%d", modrm.reg);
13839   oappend (scratchbuf + intel_syntax);
13840 }
13841
13842 static void
13843 OP_R (int bytemode, int sizeflag)
13844 {
13845   if (modrm.mod == 3)
13846     OP_E (bytemode, sizeflag);
13847   else
13848     BadOp ();
13849 }
13850
13851 static void
13852 OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13853 {
13854   int reg = modrm.reg;
13855   const char **names;
13856
13857   used_prefixes |= (prefixes & PREFIX_DATA);
13858   if (prefixes & PREFIX_DATA)
13859     {
13860       names = names_xmm;
13861       USED_REX (REX_R);
13862       if (rex & REX_R)
13863         reg += 8;
13864     }
13865   else
13866     names = names_mm;
13867   oappend (names[reg]);
13868 }
13869
13870 static void
13871 OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
13872 {
13873   int reg = modrm.reg;
13874   const char **names;
13875
13876   USED_REX (REX_R);
13877   if (rex & REX_R)
13878     reg += 8;
13879   if (need_vex
13880       && bytemode != xmm_mode
13881       && bytemode != scalar_mode)
13882     {
13883       switch (vex.length)
13884         {
13885         case 128:
13886           names = names_xmm;
13887           break;
13888         case 256:
13889           names = names_ymm;
13890           break;
13891         default:
13892           abort ();
13893         }
13894     }
13895   else
13896     names = names_xmm;
13897   oappend (names[reg]);
13898 }
13899
13900 static void
13901 OP_EM (int bytemode, int sizeflag)
13902 {
13903   int reg;
13904   const char **names;
13905
13906   if (modrm.mod != 3)
13907     {
13908       if (intel_syntax
13909           && (bytemode == v_mode || bytemode == v_swap_mode))
13910         {
13911           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
13912           used_prefixes |= (prefixes & PREFIX_DATA);
13913         }
13914       OP_E (bytemode, sizeflag);
13915       return;
13916     }
13917
13918   if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode)
13919     swap_operand ();
13920
13921   /* Skip mod/rm byte.  */
13922   MODRM_CHECK;
13923   codep++;
13924   used_prefixes |= (prefixes & PREFIX_DATA);
13925   reg = modrm.rm;
13926   if (prefixes & PREFIX_DATA)
13927     {
13928       names = names_xmm;
13929       USED_REX (REX_B);
13930       if (rex & REX_B)
13931         reg += 8;
13932     }
13933   else
13934     names = names_mm;
13935   oappend (names[reg]);
13936 }
13937
13938 /* cvt* are the only instructions in sse2 which have
13939    both SSE and MMX operands and also have 0x66 prefix
13940    in their opcode. 0x66 was originally used to differentiate
13941    between SSE and MMX instruction(operands). So we have to handle the
13942    cvt* separately using OP_EMC and OP_MXC */
13943 static void
13944 OP_EMC (int bytemode, int sizeflag)
13945 {
13946   if (modrm.mod != 3)
13947     {
13948       if (intel_syntax && bytemode == v_mode)
13949         {
13950           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
13951           used_prefixes |= (prefixes & PREFIX_DATA);
13952         }
13953       OP_E (bytemode, sizeflag);
13954       return;
13955     }
13956
13957   /* Skip mod/rm byte.  */
13958   MODRM_CHECK;
13959   codep++;
13960   used_prefixes |= (prefixes & PREFIX_DATA);
13961   oappend (names_mm[modrm.rm]);
13962 }
13963
13964 static void
13965 OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13966 {
13967   used_prefixes |= (prefixes & PREFIX_DATA);
13968   oappend (names_mm[modrm.reg]);
13969 }
13970
13971 static void
13972 OP_EX (int bytemode, int sizeflag)
13973 {
13974   int reg;
13975   const char **names;
13976
13977   /* Skip mod/rm byte.  */
13978   MODRM_CHECK;
13979   codep++;
13980
13981   if (modrm.mod != 3)
13982     {
13983       OP_E_memory (bytemode, sizeflag);
13984       return;
13985     }
13986
13987   reg = modrm.rm;
13988   USED_REX (REX_B);
13989   if (rex & REX_B)
13990     reg += 8;
13991
13992   if ((sizeflag & SUFFIX_ALWAYS)
13993       && (bytemode == x_swap_mode
13994           || bytemode == d_swap_mode
13995           || bytemode == d_scalar_swap_mode
13996           || bytemode == q_swap_mode
13997           || bytemode == q_scalar_swap_mode))
13998     swap_operand ();
13999
14000   if (need_vex
14001       && bytemode != xmm_mode
14002       && bytemode != xmmq_mode
14003       && bytemode != d_scalar_mode
14004       && bytemode != d_scalar_swap_mode
14005       && bytemode != q_scalar_mode
14006       && bytemode != q_scalar_swap_mode
14007       && bytemode != vex_scalar_w_dq_mode)
14008     {
14009       switch (vex.length)
14010         {
14011         case 128:
14012           names = names_xmm;
14013           break;
14014         case 256:
14015           names = names_ymm;
14016           break;
14017         default:
14018           abort ();
14019         }
14020     }
14021   else
14022     names = names_xmm;
14023   oappend (names[reg]);
14024 }
14025
14026 static void
14027 OP_MS (int bytemode, int sizeflag)
14028 {
14029   if (modrm.mod == 3)
14030     OP_EM (bytemode, sizeflag);
14031   else
14032     BadOp ();
14033 }
14034
14035 static void
14036 OP_XS (int bytemode, int sizeflag)
14037 {
14038   if (modrm.mod == 3)
14039     OP_EX (bytemode, sizeflag);
14040   else
14041     BadOp ();
14042 }
14043
14044 static void
14045 OP_M (int bytemode, int sizeflag)
14046 {
14047   if (modrm.mod == 3)
14048     /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
14049     BadOp ();
14050   else
14051     OP_E (bytemode, sizeflag);
14052 }
14053
14054 static void
14055 OP_0f07 (int bytemode, int sizeflag)
14056 {
14057   if (modrm.mod != 3 || modrm.rm != 0)
14058     BadOp ();
14059   else
14060     OP_E (bytemode, sizeflag);
14061 }
14062
14063 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
14064    32bit mode and "xchg %rax,%rax" in 64bit mode.  */
14065
14066 static void
14067 NOP_Fixup1 (int bytemode, int sizeflag)
14068 {
14069   if ((prefixes & PREFIX_DATA) != 0
14070       || (rex != 0
14071           && rex != 0x48
14072           && address_mode == mode_64bit))
14073     OP_REG (bytemode, sizeflag);
14074   else
14075     strcpy (obuf, "nop");
14076 }
14077
14078 static void
14079 NOP_Fixup2 (int bytemode, int sizeflag)
14080 {
14081   if ((prefixes & PREFIX_DATA) != 0
14082       || (rex != 0
14083           && rex != 0x48
14084           && address_mode == mode_64bit))
14085     OP_IMREG (bytemode, sizeflag);
14086 }
14087
14088 static const char *const Suffix3DNow[] = {
14089 /* 00 */        NULL,           NULL,           NULL,           NULL,
14090 /* 04 */        NULL,           NULL,           NULL,           NULL,
14091 /* 08 */        NULL,           NULL,           NULL,           NULL,
14092 /* 0C */        "pi2fw",        "pi2fd",        NULL,           NULL,
14093 /* 10 */        NULL,           NULL,           NULL,           NULL,
14094 /* 14 */        NULL,           NULL,           NULL,           NULL,
14095 /* 18 */        NULL,           NULL,           NULL,           NULL,
14096 /* 1C */        "pf2iw",        "pf2id",        NULL,           NULL,
14097 /* 20 */        NULL,           NULL,           NULL,           NULL,
14098 /* 24 */        NULL,           NULL,           NULL,           NULL,
14099 /* 28 */        NULL,           NULL,           NULL,           NULL,
14100 /* 2C */        NULL,           NULL,           NULL,           NULL,
14101 /* 30 */        NULL,           NULL,           NULL,           NULL,
14102 /* 34 */        NULL,           NULL,           NULL,           NULL,
14103 /* 38 */        NULL,           NULL,           NULL,           NULL,
14104 /* 3C */        NULL,           NULL,           NULL,           NULL,
14105 /* 40 */        NULL,           NULL,           NULL,           NULL,
14106 /* 44 */        NULL,           NULL,           NULL,           NULL,
14107 /* 48 */        NULL,           NULL,           NULL,           NULL,
14108 /* 4C */        NULL,           NULL,           NULL,           NULL,
14109 /* 50 */        NULL,           NULL,           NULL,           NULL,
14110 /* 54 */        NULL,           NULL,           NULL,           NULL,
14111 /* 58 */        NULL,           NULL,           NULL,           NULL,
14112 /* 5C */        NULL,           NULL,           NULL,           NULL,
14113 /* 60 */        NULL,           NULL,           NULL,           NULL,
14114 /* 64 */        NULL,           NULL,           NULL,           NULL,
14115 /* 68 */        NULL,           NULL,           NULL,           NULL,
14116 /* 6C */        NULL,           NULL,           NULL,           NULL,
14117 /* 70 */        NULL,           NULL,           NULL,           NULL,
14118 /* 74 */        NULL,           NULL,           NULL,           NULL,
14119 /* 78 */        NULL,           NULL,           NULL,           NULL,
14120 /* 7C */        NULL,           NULL,           NULL,           NULL,
14121 /* 80 */        NULL,           NULL,           NULL,           NULL,
14122 /* 84 */        NULL,           NULL,           NULL,           NULL,
14123 /* 88 */        NULL,           NULL,           "pfnacc",       NULL,
14124 /* 8C */        NULL,           NULL,           "pfpnacc",      NULL,
14125 /* 90 */        "pfcmpge",      NULL,           NULL,           NULL,
14126 /* 94 */        "pfmin",        NULL,           "pfrcp",        "pfrsqrt",
14127 /* 98 */        NULL,           NULL,           "pfsub",        NULL,
14128 /* 9C */        NULL,           NULL,           "pfadd",        NULL,
14129 /* A0 */        "pfcmpgt",      NULL,           NULL,           NULL,
14130 /* A4 */        "pfmax",        NULL,           "pfrcpit1",     "pfrsqit1",
14131 /* A8 */        NULL,           NULL,           "pfsubr",       NULL,
14132 /* AC */        NULL,           NULL,           "pfacc",        NULL,
14133 /* B0 */        "pfcmpeq",      NULL,           NULL,           NULL,
14134 /* B4 */        "pfmul",        NULL,           "pfrcpit2",     "pmulhrw",
14135 /* B8 */        NULL,           NULL,           NULL,           "pswapd",
14136 /* BC */        NULL,           NULL,           NULL,           "pavgusb",
14137 /* C0 */        NULL,           NULL,           NULL,           NULL,
14138 /* C4 */        NULL,           NULL,           NULL,           NULL,
14139 /* C8 */        NULL,           NULL,           NULL,           NULL,
14140 /* CC */        NULL,           NULL,           NULL,           NULL,
14141 /* D0 */        NULL,           NULL,           NULL,           NULL,
14142 /* D4 */        NULL,           NULL,           NULL,           NULL,
14143 /* D8 */        NULL,           NULL,           NULL,           NULL,
14144 /* DC */        NULL,           NULL,           NULL,           NULL,
14145 /* E0 */        NULL,           NULL,           NULL,           NULL,
14146 /* E4 */        NULL,           NULL,           NULL,           NULL,
14147 /* E8 */        NULL,           NULL,           NULL,           NULL,
14148 /* EC */        NULL,           NULL,           NULL,           NULL,
14149 /* F0 */        NULL,           NULL,           NULL,           NULL,
14150 /* F4 */        NULL,           NULL,           NULL,           NULL,
14151 /* F8 */        NULL,           NULL,           NULL,           NULL,
14152 /* FC */        NULL,           NULL,           NULL,           NULL,
14153 };
14154
14155 static void
14156 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
14157 {
14158   const char *mnemonic;
14159
14160   FETCH_DATA (the_info, codep + 1);
14161   /* AMD 3DNow! instructions are specified by an opcode suffix in the
14162      place where an 8-bit immediate would normally go.  ie. the last
14163      byte of the instruction.  */
14164   obufp = mnemonicendp;
14165   mnemonic = Suffix3DNow[*codep++ & 0xff];
14166   if (mnemonic)
14167     oappend (mnemonic);
14168   else
14169     {
14170       /* Since a variable sized modrm/sib chunk is between the start
14171          of the opcode (0x0f0f) and the opcode suffix, we need to do
14172          all the modrm processing first, and don't know until now that
14173          we have a bad opcode.  This necessitates some cleaning up.  */
14174       op_out[0][0] = '\0';
14175       op_out[1][0] = '\0';
14176       BadOp ();
14177     }
14178   mnemonicendp = obufp;
14179 }
14180
14181 static struct op simd_cmp_op[] =
14182 {
14183   { STRING_COMMA_LEN ("eq") },
14184   { STRING_COMMA_LEN ("lt") },
14185   { STRING_COMMA_LEN ("le") },
14186   { STRING_COMMA_LEN ("unord") },
14187   { STRING_COMMA_LEN ("neq") },
14188   { STRING_COMMA_LEN ("nlt") },
14189   { STRING_COMMA_LEN ("nle") },
14190   { STRING_COMMA_LEN ("ord") }
14191 };
14192
14193 static void
14194 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
14195 {
14196   unsigned int cmp_type;
14197
14198   FETCH_DATA (the_info, codep + 1);
14199   cmp_type = *codep++ & 0xff;
14200   if (cmp_type < ARRAY_SIZE (simd_cmp_op))
14201     {
14202       char suffix [3];
14203       char *p = mnemonicendp - 2;
14204       suffix[0] = p[0];
14205       suffix[1] = p[1];
14206       suffix[2] = '\0';
14207       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
14208       mnemonicendp += simd_cmp_op[cmp_type].len;
14209     }
14210   else
14211     {
14212       /* We have a reserved extension byte.  Output it directly.  */
14213       scratchbuf[0] = '$';
14214       print_operand_value (scratchbuf + 1, 1, cmp_type);
14215       oappend (scratchbuf + intel_syntax);
14216       scratchbuf[0] = '\0';
14217     }
14218 }
14219
14220 static void
14221 OP_Mwait (int bytemode ATTRIBUTE_UNUSED,
14222           int sizeflag ATTRIBUTE_UNUSED)
14223 {
14224   /* mwait %eax,%ecx  */
14225   if (!intel_syntax)
14226     {
14227       const char **names = (address_mode == mode_64bit
14228                             ? names64 : names32);
14229       strcpy (op_out[0], names[0]);
14230       strcpy (op_out[1], names[1]);
14231       two_source_ops = 1;
14232     }
14233   /* Skip mod/rm byte.  */
14234   MODRM_CHECK;
14235   codep++;
14236 }
14237
14238 static void
14239 OP_Monitor (int bytemode ATTRIBUTE_UNUSED,
14240             int sizeflag ATTRIBUTE_UNUSED)
14241 {
14242   /* monitor %eax,%ecx,%edx"  */
14243   if (!intel_syntax)
14244     {
14245       const char **op1_names;
14246       const char **names = (address_mode == mode_64bit
14247                             ? names64 : names32);
14248
14249       if (!(prefixes & PREFIX_ADDR))
14250         op1_names = (address_mode == mode_16bit
14251                      ? names16 : names);
14252       else
14253         {
14254           /* Remove "addr16/addr32".  */
14255           all_prefixes[last_addr_prefix] = 0;
14256           op1_names = (address_mode != mode_32bit
14257                        ? names32 : names16);
14258           used_prefixes |= PREFIX_ADDR;
14259         }
14260       strcpy (op_out[0], op1_names[0]);
14261       strcpy (op_out[1], names[1]);
14262       strcpy (op_out[2], names[2]);
14263       two_source_ops = 1;
14264     }
14265   /* Skip mod/rm byte.  */
14266   MODRM_CHECK;
14267   codep++;
14268 }
14269
14270 static void
14271 BadOp (void)
14272 {
14273   /* Throw away prefixes and 1st. opcode byte.  */
14274   codep = insn_codep + 1;
14275   oappend ("(bad)");
14276 }
14277
14278 static void
14279 REP_Fixup (int bytemode, int sizeflag)
14280 {
14281   /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
14282      lods and stos.  */
14283   if (prefixes & PREFIX_REPZ)
14284     all_prefixes[last_repz_prefix] = REP_PREFIX;
14285
14286   switch (bytemode)
14287     {
14288     case al_reg:
14289     case eAX_reg:
14290     case indir_dx_reg:
14291       OP_IMREG (bytemode, sizeflag);
14292       break;
14293     case eDI_reg:
14294       OP_ESreg (bytemode, sizeflag);
14295       break;
14296     case eSI_reg:
14297       OP_DSreg (bytemode, sizeflag);
14298       break;
14299     default:
14300       abort ();
14301       break;
14302     }
14303 }
14304
14305 static void
14306 CMPXCHG8B_Fixup (int bytemode, int sizeflag)
14307 {
14308   USED_REX (REX_W);
14309   if (rex & REX_W)
14310     {
14311       /* Change cmpxchg8b to cmpxchg16b.  */
14312       char *p = mnemonicendp - 2;
14313       mnemonicendp = stpcpy (p, "16b");
14314       bytemode = o_mode;
14315     }
14316   OP_M (bytemode, sizeflag);
14317 }
14318
14319 static void
14320 XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED)
14321 {
14322   const char **names;
14323
14324   if (need_vex)
14325     {
14326       switch (vex.length)
14327         {
14328         case 128:
14329           names = names_xmm;
14330           break;
14331         case 256:
14332           names = names_ymm;
14333           break;
14334         default:
14335           abort ();
14336         }
14337     }
14338   else
14339     names = names_xmm;
14340   oappend (names[reg]);
14341 }
14342
14343 static void
14344 CRC32_Fixup (int bytemode, int sizeflag)
14345 {
14346   /* Add proper suffix to "crc32".  */
14347   char *p = mnemonicendp;
14348
14349   switch (bytemode)
14350     {
14351     case b_mode:
14352       if (intel_syntax)
14353         goto skip;
14354
14355       *p++ = 'b';
14356       break;
14357     case v_mode:
14358       if (intel_syntax)
14359         goto skip;
14360
14361       USED_REX (REX_W);
14362       if (rex & REX_W)
14363         *p++ = 'q';
14364       else
14365         {
14366           if (sizeflag & DFLAG)
14367             *p++ = 'l';
14368           else
14369             *p++ = 'w';
14370           used_prefixes |= (prefixes & PREFIX_DATA);
14371         }
14372       break;
14373     default:
14374       oappend (INTERNAL_DISASSEMBLER_ERROR);
14375       break;
14376     }
14377   mnemonicendp = p;
14378   *p = '\0';
14379
14380 skip:
14381   if (modrm.mod == 3)
14382     {
14383       int add;
14384
14385       /* Skip mod/rm byte.  */
14386       MODRM_CHECK;
14387       codep++;
14388
14389       USED_REX (REX_B);
14390       add = (rex & REX_B) ? 8 : 0;
14391       if (bytemode == b_mode)
14392         {
14393           USED_REX (0);
14394           if (rex)
14395             oappend (names8rex[modrm.rm + add]);
14396           else
14397             oappend (names8[modrm.rm + add]);
14398         }
14399       else
14400         {
14401           USED_REX (REX_W);
14402           if (rex & REX_W)
14403             oappend (names64[modrm.rm + add]);
14404           else if ((prefixes & PREFIX_DATA))
14405             oappend (names16[modrm.rm + add]);
14406           else
14407             oappend (names32[modrm.rm + add]);
14408         }
14409     }
14410   else
14411     OP_E (bytemode, sizeflag);
14412 }
14413
14414 static void
14415 FXSAVE_Fixup (int bytemode, int sizeflag)
14416 {
14417   /* Add proper suffix to "fxsave" and "fxrstor".  */
14418   USED_REX (REX_W);
14419   if (rex & REX_W)
14420     {
14421       char *p = mnemonicendp;
14422       *p++ = '6';
14423       *p++ = '4';
14424       *p = '\0';
14425       mnemonicendp = p;
14426     }
14427   OP_M (bytemode, sizeflag);
14428 }
14429
14430 /* Display the destination register operand for instructions with
14431    VEX. */
14432
14433 static void
14434 OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
14435 {
14436   int reg;
14437   const char **names;
14438
14439   if (!need_vex)
14440     abort ();
14441
14442   if (!need_vex_reg)
14443     return;
14444
14445   reg = vex.register_specifier;
14446   if (bytemode == vex_scalar_mode)
14447     {
14448       oappend (names_xmm[reg]);
14449       return;
14450     }
14451
14452   switch (vex.length)
14453     {
14454     case 128:
14455       switch (bytemode)
14456         {
14457         case vex_mode:
14458         case vex128_mode:
14459           break;
14460         default:
14461           abort ();
14462           return;
14463         }
14464
14465       names = names_xmm;
14466       break;
14467     case 256:
14468       switch (bytemode)
14469         {
14470         case vex_mode:
14471         case vex256_mode:
14472           break;
14473         default:
14474           abort ();
14475           return;
14476         }
14477
14478       names = names_ymm;
14479       break;
14480     default:
14481       abort ();
14482       break;
14483     }
14484   oappend (names[reg]);
14485 }
14486
14487 /* Get the VEX immediate byte without moving codep.  */
14488
14489 static unsigned char
14490 get_vex_imm8 (int sizeflag, int opnum)
14491 {
14492   int bytes_before_imm = 0;
14493
14494   if (modrm.mod != 3)
14495     {
14496       /* There are SIB/displacement bytes.  */
14497       if ((sizeflag & AFLAG) || address_mode == mode_64bit)
14498         {
14499           /* 32/64 bit address mode */
14500           int base = modrm.rm;
14501
14502           /* Check SIB byte.  */
14503           if (base == 4)
14504             {
14505               FETCH_DATA (the_info, codep + 1);
14506               base = *codep & 7;
14507               /* When decoding the third source, don't increase
14508                  bytes_before_imm as this has already been incremented
14509                  by one in OP_E_memory while decoding the second
14510                  source operand.  */
14511               if (opnum == 0)
14512                 bytes_before_imm++;
14513             }
14514
14515           /* Don't increase bytes_before_imm when decoding the third source,
14516              it has already been incremented by OP_E_memory while decoding
14517              the second source operand.  */
14518           if (opnum == 0)
14519             {
14520               switch (modrm.mod)
14521                 {
14522                   case 0:
14523                     /* When modrm.rm == 5 or modrm.rm == 4 and base in
14524                        SIB == 5, there is a 4 byte displacement.  */
14525                     if (base != 5)
14526                       /* No displacement. */
14527                       break;
14528                   case 2:
14529                     /* 4 byte displacement.  */
14530                     bytes_before_imm += 4;
14531                     break;
14532                   case 1:
14533                     /* 1 byte displacement.  */
14534                     bytes_before_imm++;
14535                     break;
14536                 }
14537             }
14538         }
14539       else
14540         {
14541           /* 16 bit address mode */
14542           /* Don't increase bytes_before_imm when decoding the third source,
14543              it has already been incremented by OP_E_memory while decoding
14544              the second source operand.  */
14545           if (opnum == 0)
14546             {
14547               switch (modrm.mod)
14548                 {
14549                 case 0:
14550                   /* When modrm.rm == 6, there is a 2 byte displacement.  */
14551                   if (modrm.rm != 6)
14552                     /* No displacement. */
14553                     break;
14554                 case 2:
14555                   /* 2 byte displacement.  */
14556                   bytes_before_imm += 2;
14557                   break;
14558                 case 1:
14559                   /* 1 byte displacement: when decoding the third source,
14560                      don't increase bytes_before_imm as this has already
14561                      been incremented by one in OP_E_memory while decoding
14562                      the second source operand.  */
14563                   if (opnum == 0)
14564                     bytes_before_imm++;
14565
14566                   break;
14567                 }
14568             }
14569         }
14570     }
14571
14572   FETCH_DATA (the_info, codep + bytes_before_imm + 1);
14573   return codep [bytes_before_imm];
14574 }
14575
14576 static void
14577 OP_EX_VexReg (int bytemode, int sizeflag, int reg)
14578 {
14579   const char **names;
14580
14581   if (reg == -1 && modrm.mod != 3)
14582     {
14583       OP_E_memory (bytemode, sizeflag);
14584       return;
14585     }
14586   else
14587     {
14588       if (reg == -1)
14589         {
14590           reg = modrm.rm;
14591           USED_REX (REX_B);
14592           if (rex & REX_B)
14593             reg += 8;
14594         }
14595       else if (reg > 7 && address_mode != mode_64bit)
14596         BadOp ();
14597     }
14598
14599   switch (vex.length)
14600     {
14601     case 128:
14602       names = names_xmm;
14603       break;
14604     case 256:
14605       names = names_ymm;
14606       break;
14607     default:
14608       abort ();
14609     }
14610   oappend (names[reg]);
14611 }
14612
14613 static void
14614 OP_EX_VexImmW (int bytemode, int sizeflag)
14615 {
14616   int reg = -1;
14617   static unsigned char vex_imm8;
14618
14619   if (vex_w_done == 0)
14620     {
14621       vex_w_done = 1;
14622
14623       /* Skip mod/rm byte.  */
14624       MODRM_CHECK;
14625       codep++;
14626
14627       vex_imm8 = get_vex_imm8 (sizeflag, 0);
14628
14629       if (vex.w)
14630           reg = vex_imm8 >> 4;
14631
14632       OP_EX_VexReg (bytemode, sizeflag, reg);
14633     }
14634   else if (vex_w_done == 1)
14635     {
14636       vex_w_done = 2;
14637
14638       if (!vex.w)
14639           reg = vex_imm8 >> 4;
14640
14641       OP_EX_VexReg (bytemode, sizeflag, reg);
14642     }
14643   else
14644     {
14645       /* Output the imm8 directly.  */
14646       scratchbuf[0] = '$';
14647       print_operand_value (scratchbuf + 1, 1, vex_imm8 & 0xf);
14648       oappend (scratchbuf + intel_syntax);
14649       scratchbuf[0] = '\0';
14650       codep++;
14651     }
14652 }
14653
14654 static void
14655 OP_Vex_2src (int bytemode, int sizeflag)
14656 {
14657   if (modrm.mod == 3)
14658     {
14659       int reg = modrm.rm;
14660       USED_REX (REX_B);
14661       if (rex & REX_B)
14662         reg += 8;
14663       oappend (names_xmm[reg]);
14664     }
14665   else
14666     {
14667       if (intel_syntax
14668           && (bytemode == v_mode || bytemode == v_swap_mode))
14669         {
14670           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
14671           used_prefixes |= (prefixes & PREFIX_DATA);
14672         }
14673       OP_E (bytemode, sizeflag);
14674     }
14675 }
14676
14677 static void
14678 OP_Vex_2src_1 (int bytemode, int sizeflag)
14679 {
14680   if (modrm.mod == 3)
14681     {
14682       /* Skip mod/rm byte.   */
14683       MODRM_CHECK;
14684       codep++;
14685     }
14686
14687   if (vex.w)
14688     oappend (names_xmm[vex.register_specifier]);
14689   else
14690     OP_Vex_2src (bytemode, sizeflag);
14691 }
14692
14693 static void
14694 OP_Vex_2src_2 (int bytemode, int sizeflag)
14695 {
14696   if (vex.w)
14697     OP_Vex_2src (bytemode, sizeflag);
14698   else
14699     oappend (names_xmm[vex.register_specifier]);
14700 }
14701
14702 static void
14703 OP_EX_VexW (int bytemode, int sizeflag)
14704 {
14705   int reg = -1;
14706
14707   if (!vex_w_done)
14708     {
14709       vex_w_done = 1;
14710
14711       /* Skip mod/rm byte.  */
14712       MODRM_CHECK;
14713       codep++;
14714
14715       if (vex.w)
14716         reg = get_vex_imm8 (sizeflag, 0) >> 4;
14717     }
14718   else
14719     {
14720       if (!vex.w)
14721         reg = get_vex_imm8 (sizeflag, 1) >> 4;
14722     }
14723
14724   OP_EX_VexReg (bytemode, sizeflag, reg);
14725 }
14726
14727 static void
14728 VEXI4_Fixup (int bytemode ATTRIBUTE_UNUSED,
14729              int sizeflag ATTRIBUTE_UNUSED)
14730 {
14731   /* Skip the immediate byte and check for invalid bits.  */
14732   FETCH_DATA (the_info, codep + 1);
14733   if (*codep++ & 0xf)
14734     BadOp ();
14735 }
14736
14737 static void
14738 OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
14739 {
14740   int reg;
14741   const char **names;
14742
14743   FETCH_DATA (the_info, codep + 1);
14744   reg = *codep++;
14745
14746   if (bytemode != x_mode)
14747     abort ();
14748
14749   if (reg & 0xf)
14750       BadOp ();
14751
14752   reg >>= 4;
14753   if (reg > 7 && address_mode != mode_64bit)
14754     BadOp ();
14755
14756   switch (vex.length)
14757     {
14758     case 128:
14759       names = names_xmm;
14760       break;
14761     case 256:
14762       names = names_ymm;
14763       break;
14764     default:
14765       abort ();
14766     }
14767   oappend (names[reg]);
14768 }
14769
14770 static void
14771 OP_XMM_VexW (int bytemode, int sizeflag)
14772 {
14773   /* Turn off the REX.W bit since it is used for swapping operands
14774      now.  */
14775   rex &= ~REX_W;
14776   OP_XMM (bytemode, sizeflag);
14777 }
14778
14779 static void
14780 OP_EX_Vex (int bytemode, int sizeflag)
14781 {
14782   if (modrm.mod != 3)
14783     {
14784       if (vex.register_specifier != 0)
14785         BadOp ();
14786       need_vex_reg = 0;
14787     }
14788   OP_EX (bytemode, sizeflag);
14789 }
14790
14791 static void
14792 OP_XMM_Vex (int bytemode, int sizeflag)
14793 {
14794   if (modrm.mod != 3)
14795     {
14796       if (vex.register_specifier != 0)
14797         BadOp ();
14798       need_vex_reg = 0;
14799     }
14800   OP_XMM (bytemode, sizeflag);
14801 }
14802
14803 static void
14804 VZERO_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
14805 {
14806   switch (vex.length)
14807     {
14808     case 128:
14809       mnemonicendp = stpcpy (obuf, "vzeroupper");
14810       break;
14811     case 256:
14812       mnemonicendp = stpcpy (obuf, "vzeroall");
14813       break;
14814     default:
14815       abort ();
14816     }
14817 }
14818
14819 static struct op vex_cmp_op[] =
14820 {
14821   { STRING_COMMA_LEN ("eq") },
14822   { STRING_COMMA_LEN ("lt") },
14823   { STRING_COMMA_LEN ("le") },
14824   { STRING_COMMA_LEN ("unord") },
14825   { STRING_COMMA_LEN ("neq") },
14826   { STRING_COMMA_LEN ("nlt") },
14827   { STRING_COMMA_LEN ("nle") },
14828   { STRING_COMMA_LEN ("ord") },
14829   { STRING_COMMA_LEN ("eq_uq") },
14830   { STRING_COMMA_LEN ("nge") },
14831   { STRING_COMMA_LEN ("ngt") },
14832   { STRING_COMMA_LEN ("false") },
14833   { STRING_COMMA_LEN ("neq_oq") },
14834   { STRING_COMMA_LEN ("ge") },
14835   { STRING_COMMA_LEN ("gt") },
14836   { STRING_COMMA_LEN ("true") },
14837   { STRING_COMMA_LEN ("eq_os") },
14838   { STRING_COMMA_LEN ("lt_oq") },
14839   { STRING_COMMA_LEN ("le_oq") },
14840   { STRING_COMMA_LEN ("unord_s") },
14841   { STRING_COMMA_LEN ("neq_us") },
14842   { STRING_COMMA_LEN ("nlt_uq") },
14843   { STRING_COMMA_LEN ("nle_uq") },
14844   { STRING_COMMA_LEN ("ord_s") },
14845   { STRING_COMMA_LEN ("eq_us") },
14846   { STRING_COMMA_LEN ("nge_uq") },
14847   { STRING_COMMA_LEN ("ngt_uq") },
14848   { STRING_COMMA_LEN ("false_os") },
14849   { STRING_COMMA_LEN ("neq_os") },
14850   { STRING_COMMA_LEN ("ge_oq") },
14851   { STRING_COMMA_LEN ("gt_oq") },
14852   { STRING_COMMA_LEN ("true_us") },
14853 };
14854
14855 static void
14856 VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
14857 {
14858   unsigned int cmp_type;
14859
14860   FETCH_DATA (the_info, codep + 1);
14861   cmp_type = *codep++ & 0xff;
14862   if (cmp_type < ARRAY_SIZE (vex_cmp_op))
14863     {
14864       char suffix [3];
14865       char *p = mnemonicendp - 2;
14866       suffix[0] = p[0];
14867       suffix[1] = p[1];
14868       suffix[2] = '\0';
14869       sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix);
14870       mnemonicendp += vex_cmp_op[cmp_type].len;
14871     }
14872   else
14873     {
14874       /* We have a reserved extension byte.  Output it directly.  */
14875       scratchbuf[0] = '$';
14876       print_operand_value (scratchbuf + 1, 1, cmp_type);
14877       oappend (scratchbuf + intel_syntax);
14878       scratchbuf[0] = '\0';
14879     }
14880 }
14881
14882 static const struct op pclmul_op[] =
14883 {
14884   { STRING_COMMA_LEN ("lql") },
14885   { STRING_COMMA_LEN ("hql") },
14886   { STRING_COMMA_LEN ("lqh") },
14887   { STRING_COMMA_LEN ("hqh") }
14888 };
14889
14890 static void
14891 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED,
14892               int sizeflag ATTRIBUTE_UNUSED)
14893 {
14894   unsigned int pclmul_type;
14895
14896   FETCH_DATA (the_info, codep + 1);
14897   pclmul_type = *codep++ & 0xff;
14898   switch (pclmul_type)
14899     {
14900     case 0x10:
14901       pclmul_type = 2;
14902       break;
14903     case 0x11:
14904       pclmul_type = 3;
14905       break;
14906     default:
14907       break;
14908     }
14909   if (pclmul_type < ARRAY_SIZE (pclmul_op))
14910     {
14911       char suffix [4];
14912       char *p = mnemonicendp - 3;
14913       suffix[0] = p[0];
14914       suffix[1] = p[1];
14915       suffix[2] = p[2];
14916       suffix[3] = '\0';
14917       sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix);
14918       mnemonicendp += pclmul_op[pclmul_type].len;
14919     }
14920   else
14921     {
14922       /* We have a reserved extension byte.  Output it directly.  */
14923       scratchbuf[0] = '$';
14924       print_operand_value (scratchbuf + 1, 1, pclmul_type);
14925       oappend (scratchbuf + intel_syntax);
14926       scratchbuf[0] = '\0';
14927     }
14928 }
14929
14930 static void
14931 MOVBE_Fixup (int bytemode, int sizeflag)
14932 {
14933   /* Add proper suffix to "movbe".  */
14934   char *p = mnemonicendp;
14935
14936   switch (bytemode)
14937     {
14938     case v_mode:
14939       if (intel_syntax)
14940         goto skip;
14941
14942       USED_REX (REX_W);
14943       if (sizeflag & SUFFIX_ALWAYS)
14944         {
14945           if (rex & REX_W)
14946             *p++ = 'q';
14947           else
14948             {
14949               if (sizeflag & DFLAG)
14950                 *p++ = 'l';
14951               else
14952                 *p++ = 'w';
14953               used_prefixes |= (prefixes & PREFIX_DATA);
14954             }
14955         }
14956       break;
14957     default:
14958       oappend (INTERNAL_DISASSEMBLER_ERROR);
14959       break;
14960     }
14961   mnemonicendp = p;
14962   *p = '\0';
14963
14964 skip:
14965   OP_M (bytemode, sizeflag);
14966 }
14967
14968 static void
14969 OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
14970 {
14971   int reg;
14972   const char **names;
14973
14974   /* Skip mod/rm byte.  */
14975   MODRM_CHECK;
14976   codep++;
14977
14978   if (vex.w)
14979     names = names64;
14980   else if (vex.length == 256)
14981     names = names32;
14982   else
14983     names = names16;
14984
14985   reg = modrm.rm;
14986   USED_REX (REX_B);
14987   if (rex & REX_B)
14988     reg += 8;
14989
14990   oappend (names[reg]);
14991 }
14992
14993 static void
14994 OP_LWP_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
14995 {
14996   const char **names;
14997
14998   if (vex.w)
14999     names = names64;
15000   else if (vex.length == 256)
15001     names = names32;
15002   else
15003     names = names16;
15004
15005   oappend (names[vex.register_specifier]);
15006 }
15007
15008 static void
15009 OP_LWP_I (int bytemode ATTRIBUTE_UNUSED, int sizeflag)
15010 {
15011   if (vex.w || vex.length == 256)
15012     OP_I (q_mode, sizeflag);
15013   else
15014     OP_I (w_mode, sizeflag);
15015 }
15016