opcodes/i386-opc.h

   1 /* Declarations for Intel 80386 opcode table
   2    Copyright 2007, 2008, 2009
   3    Free Software Foundation, Inc.
   4
   5    This file is part of the GNU opcodes library.
   6
   7    This library is free software; you can redistribute it and/or modify
   8    it under the terms of the GNU General Public License as published by
   9    the Free Software Foundation; either version 3, or (at your option)
  10    any later version.
  11
  12    It is distributed in the hope that it will be useful, but WITHOUT
  13    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  14    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  15    License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with GAS; see the file COPYING.  If not, write to the Free
  19    Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
  20    02110-1301, USA.  */
  21
  22 #include "opcode/i386.h"
  23 #ifdef HAVE_LIMITS_H
  24 #include <limits.h>
  25 #endif
  26
  27 #ifndef CHAR_BIT
  28 #define CHAR_BIT 8
  29 #endif
  30
  31 /* Position of cpu flags bitfiled.  */
  32
  33 enum
  34 {
  35   /* i186 or better required */
  36   Cpu186 = 0,
  37   /* i286 or better required */
  38   Cpu286,
  39   /* i386 or better required */
  40   Cpu386,
  41   /* i486 or better required */
  42   Cpu486,
  43   /* i585 or better required */
  44   Cpu586,
  45   /* i686 or better required */
  46   Cpu686,
  47   /* CLFLUSH Instuction support required */
  48   CpuClflush,
  49   /* SYSCALL Instuctions support required */
  50   CpuSYSCALL,
  51   /* Floating point support required */
  52   Cpu8087,
  53   /* i287 support required */
  54   Cpu287,
  55   /* i387 support required */
  56   Cpu387,
  57   /* i686 and floating point support required */
  58   Cpu687,
  59   /* SSE3 and floating point support required */
  60   CpuFISTTP,
  61   /* MMX support required */
  62   CpuMMX,
  63   /* SSE support required */
  64   CpuSSE,
  65   /* SSE2 support required */
  66   CpuSSE2,
  67   /* 3dnow! support required */
  68   Cpu3dnow,
  69   /* 3dnow! Extensions support required */
  70   Cpu3dnowA,
  71   /* SSE3 support required */
  72   CpuSSE3,
  73   /* VIA PadLock required */
  74   CpuPadLock,
  75   /* AMD Secure Virtual Machine Ext-s required */
  76   CpuSVME,
  77   /* VMX Instructions required */
  78   CpuVMX,
  79   /* SMX Instructions required */
  80   CpuSMX,
  81   /* SSSE3 support required */
  82   CpuSSSE3,
  83   /* SSE4a support required */
  84   CpuSSE4a,
  85   /* ABM New Instructions required */
  86   CpuABM,
  87   /* SSE4.1 support required */
  88   CpuSSE4_1,
  89   /* SSE4.2 support required */
  90   CpuSSE4_2,
  91   /* AVX support required */
  92   CpuAVX,
  93   /* Intel L1OM support required */
  94   CpuL1OM,
  95   /* Xsave/xrstor New Instuctions support required */
  96   CpuXsave,
  97   /* AES support required */
  98   CpuAES,
  99   /* PCLMUL support required */
 100   CpuPCLMUL,
 101   /* FMA support required */
 102   CpuFMA,
 103   /* FMA4 support required */
 104   CpuFMA4,
 105   /* XOP support required */
 106   CpuXOP,
 107   /* LWP support required */
 108   CpuLWP,
 109   /* MOVBE Instuction support required */
 110   CpuMovbe,
 111   /* EPT Instructions required */
 112   CpuEPT,
 113   /* RDTSCP Instuction support required */
 114   CpuRdtscp,
 115   /* 64bit support available, used by -march= in assembler.  */
 116   CpuLM,
 117   /* 64bit support required  */
 118   Cpu64,
 119   /* Not supported in the 64bit mode  */
 120   CpuNo64,
 121   /* The last bitfield in i386_cpu_flags.  */
 122   CpuMax = CpuNo64
 123 };
 124
 125 #define CpuNumOfUints \
 126   (CpuMax / sizeof (unsigned int) / CHAR_BIT + 1)
 127 #define CpuNumOfBits \
 128   (CpuNumOfUints * sizeof (unsigned int) * CHAR_BIT)
 129
 130 /* If you get a compiler error for zero width of the unused field,
 131    comment it out.  */
 132 #define CpuUnused       (CpuMax + 1)
 133
 134 /* We can check if an instruction is available with array instead
 135    of bitfield. */
 136 typedef union i386_cpu_flags
 137 {
 138   struct
 139     {
 140       unsigned int cpui186:1;
 141       unsigned int cpui286:1;
 142       unsigned int cpui386:1;
 143       unsigned int cpui486:1;
 144       unsigned int cpui586:1;
 145       unsigned int cpui686:1;
 146       unsigned int cpuclflush:1;
 147       unsigned int cpusyscall:1;
 148       unsigned int cpu8087:1;
 149       unsigned int cpu287:1;
 150       unsigned int cpu387:1;
 151       unsigned int cpu687:1;
 152       unsigned int cpufisttp:1;
 153       unsigned int cpummx:1;
 154       unsigned int cpusse:1;
 155       unsigned int cpusse2:1;
 156       unsigned int cpua3dnow:1;
 157       unsigned int cpua3dnowa:1;
 158       unsigned int cpusse3:1;
 159       unsigned int cpupadlock:1;
 160       unsigned int cpusvme:1;
 161       unsigned int cpuvmx:1;
 162       unsigned int cpusmx:1;
 163       unsigned int cpussse3:1;
 164       unsigned int cpusse4a:1;
 165       unsigned int cpuabm:1;
 166       unsigned int cpusse4_1:1;
 167       unsigned int cpusse4_2:1;
 168       unsigned int cpuavx:1;
 169       unsigned int cpul1om:1;
 170       unsigned int cpuxsave:1;
 171       unsigned int cpuaes:1;
 172       unsigned int cpupclmul:1;
 173       unsigned int cpufma:1;
 174       unsigned int cpufma4:1;
 175       unsigned int cpuxop:1;
 176       unsigned int cpulwp:1;
 177       unsigned int cpumovbe:1;
 178       unsigned int cpuept:1;
 179       unsigned int cpurdtscp:1;
 180       unsigned int cpulm:1;
 181       unsigned int cpu64:1;
 182       unsigned int cpuno64:1;
 183 #ifdef CpuUnused
 184       unsigned int unused:(CpuNumOfBits - CpuUnused);
 185 #endif
 186     } bitfield;
 187   unsigned int array[CpuNumOfUints];
 188 } i386_cpu_flags;
 189
 190 /* Position of opcode_modifier bits.  */
 191
 192 enum
 193 {
 194   /* has direction bit. */
 195   D = 0,
 196   /* set if operands can be words or dwords encoded the canonical way */
 197   W,
 198   /* Skip the current insn and use the next insn in i386-opc.tbl to swap
 199      operand in encoding.  */
 200   S,
 201   /* insn has a modrm byte. */
 202   Modrm,
 203   /* register is in low 3 bits of opcode */
 204   ShortForm,
 205   /* special case for jump insns.  */
 206   Jump,
 207   /* call and jump */
 208   JumpDword,
 209   /* loop and jecxz */
 210   JumpByte,
 211   /* special case for intersegment leaps/calls */
 212   JumpInterSegment,
 213   /* FP insn memory format bit, sized by 0x4 */
 214   FloatMF,
 215   /* src/dest swap for floats. */
 216   FloatR,
 217   /* has float insn direction bit. */
 218   FloatD,
 219   /* needs size prefix if in 32-bit mode */
 220   Size16,
 221   /* needs size prefix if in 16-bit mode */
 222   Size32,
 223   /* needs size prefix if in 64-bit mode */
 224   Size64,
 225   /* instruction ignores operand size prefix and in Intel mode ignores
 226      mnemonic size suffix check.  */
 227   IgnoreSize,
 228   /* default insn size depends on mode */
 229   DefaultSize,
 230   /* b suffix on instruction illegal */
 231   No_bSuf,
 232   /* w suffix on instruction illegal */
 233   No_wSuf,
 234   /* l suffix on instruction illegal */
 235   No_lSuf,
 236   /* s suffix on instruction illegal */
 237   No_sSuf,
 238   /* q suffix on instruction illegal */
 239   No_qSuf,
 240   /* long double suffix on instruction illegal */
 241   No_ldSuf,
 242   /* instruction needs FWAIT */
 243   FWait,
 244   /* quick test for string instructions */
 245   IsString,
 246   /* quick test for lockable instructions */
 247   IsLockable,
 248   /* fake an extra reg operand for clr, imul and special register
 249      processing for some instructions.  */
 250   RegKludge,
 251   /* The first operand must be xmm0 */
 252   FirstXmm0,
 253   /* An implicit xmm0 as the first operand */
 254   Implicit1stXmm0,
 255   /* BYTE is OK in Intel syntax. */
 256   ByteOkIntel,
 257   /* Convert to DWORD */
 258   ToDword,
 259   /* Convert to QWORD */
 260   ToQword,
 261   /* Address prefix changes operand 0 */
 262   AddrPrefixOp0,
 263   /* opcode is a prefix */
 264   IsPrefix,
 265   /* instruction has extension in 8 bit imm */
 266   ImmExt,
 267   /* instruction don't need Rex64 prefix.  */
 268   NoRex64,
 269   /* instruction require Rex64 prefix.  */
 270   Rex64,
 271   /* deprecated fp insn, gets a warning */
 272   Ugh,
 273   /* insn has VEX prefix:
 274         1: 128bit VEX prefix.
 275         2: 256bit VEX prefix.
 276    */
 277   Vex,
 278   /* insn has VEX NDS. Register-only source is encoded in Vex prefix.
 279      We use VexNDS on insns with VEX DDS since the register-only source
 280      is the second source register.  */
 281   VexNDS,
 282   /* insn has VEX NDD. Register destination is encoded in Vex prefix. */
 283   VexNDD,
 284   /* insn has VEX NDD. Register destination is encoded in Vex prefix
 285      and one of the operands can access a memory location.  */
 286   VexLWP,
 287   /* insn has VEX W0. */
 288   VexW0,
 289   /* insn has VEX W1. */
 290   VexW1,
 291   /* insn has VEX 0x0F opcode prefix. */
 292   Vex0F,
 293   /* insn has VEX 0x0F38 opcode prefix. */
 294   Vex0F38,
 295   /* insn has VEX 0x0F3A opcode prefix. */
 296   Vex0F3A,
 297   /* insn has XOP 0x08 opcode prefix. */
 298   XOP08,
 299   /* insn has XOP 0x09 opcode prefix. */
 300   XOP09,
 301   /* insn has XOP 0x0A opcode prefix. */
 302   XOP0A,
 303   /* insn has VEX prefix with 2 sources. */
 304   Vex2Sources,
 305   /* insn has VEX prefix with 3 sources. */
 306   Vex3Sources,
 307   /* instruction has VEX 8 bit imm */
 308   VexImmExt,
 309   /* SSE to AVX support required */
 310   SSE2AVX,
 311   /* No AVX equivalent */
 312   NoAVX,
 313   /* Compatible with old (<= 2.8.1) versions of gcc  */
 314   OldGcc,
 315   /* AT&T mnemonic.  */
 316   ATTMnemonic,
 317   /* AT&T syntax.  */
 318   ATTSyntax,
 319   /* Intel syntax.  */
 320   IntelSyntax,
 321   /* The last bitfield in i386_opcode_modifier.  */
 322   Opcode_Modifier_Max
 323 };
 324
 325 typedef struct i386_opcode_modifier
 326 {
 327   unsigned int d:1;
 328   unsigned int w:1;
 329   unsigned int s:1;
 330   unsigned int modrm:1;
 331   unsigned int shortform:1;
 332   unsigned int jump:1;
 333   unsigned int jumpdword:1;
 334   unsigned int jumpbyte:1;
 335   unsigned int jumpintersegment:1;
 336   unsigned int floatmf:1;
 337   unsigned int floatr:1;
 338   unsigned int floatd:1;
 339   unsigned int size16:1;
 340   unsigned int size32:1;
 341   unsigned int size64:1;
 342   unsigned int ignoresize:1;
 343   unsigned int defaultsize:1;
 344   unsigned int no_bsuf:1;
 345   unsigned int no_wsuf:1;
 346   unsigned int no_lsuf:1;
 347   unsigned int no_ssuf:1;
 348   unsigned int no_qsuf:1;
 349   unsigned int no_ldsuf:1;
 350   unsigned int fwait:1;
 351   unsigned int isstring:1;
 352   unsigned int islockable:1;
 353   unsigned int regkludge:1;
 354   unsigned int firstxmm0:1;
 355   unsigned int implicit1stxmm0:1;
 356   unsigned int byteokintel:1;
 357   unsigned int todword:1;
 358   unsigned int toqword:1;
 359   unsigned int addrprefixop0:1;
 360   unsigned int isprefix:1;
 361   unsigned int immext:1;
 362   unsigned int norex64:1;
 363   unsigned int rex64:1;
 364   unsigned int ugh:1;
 365   unsigned int vex:2;
 366   unsigned int vexnds:1;
 367   unsigned int vexndd:1;
 368   unsigned int vexlwp:1;
 369   unsigned int vexw0:1;
 370   unsigned int vexw1:1;
 371   unsigned int vex0f:1;
 372   unsigned int vex0f38:1;
 373   unsigned int vex0f3a:1;
 374   unsigned int xop08:1;
 375   unsigned int xop09:1;
 376   unsigned int xop0a:1;
 377   unsigned int vex2sources:1;
 378   unsigned int vex3sources:1;
 379   unsigned int veximmext:1;
 380   unsigned int sse2avx:1;
 381   unsigned int noavx:1;
 382   unsigned int oldgcc:1;
 383   unsigned int attmnemonic:1;
 384   unsigned int attsyntax:1;
 385   unsigned int intelsyntax:1;
 386 } i386_opcode_modifier;
 387
 388 /* Position of operand_type bits.  */
 389
 390 enum
 391 {
 392   /* 8bit register */
 393   Reg8 = 0,
 394   /* 16bit register */
 395   Reg16,
 396   /* 32bit register */
 397   Reg32,
 398   /* 64bit register */
 399   Reg64,
 400   /* Floating pointer stack register */
 401   FloatReg,
 402   /* MMX register */
 403   RegMMX,
 404   /* SSE register */
 405   RegXMM,
 406   /* AVX registers */
 407   RegYMM,
 408   /* Control register */
 409   Control,
 410   /* Debug register */
 411   Debug,
 412   /* Test register */
 413   Test,
 414   /* 2 bit segment register */
 415   SReg2,
 416   /* 3 bit segment register */
 417   SReg3,
 418   /* 1 bit immediate */
 419   Imm1,
 420   /* 8 bit immediate */
 421   Imm8,
 422   /* 8 bit immediate sign extended */
 423   Imm8S,
 424   /* 16 bit immediate */
 425   Imm16,
 426   /* 32 bit immediate */
 427   Imm32,
 428   /* 32 bit immediate sign extended */
 429   Imm32S,
 430   /* 64 bit immediate */
 431   Imm64,
 432   /* 8bit/16bit/32bit displacements are used in different ways,
 433      depending on the instruction.  For jumps, they specify the
 434      size of the PC relative displacement, for instructions with
 435      memory operand, they specify the size of the offset relative
 436      to the base register, and for instructions with memory offset
 437      such as `mov 1234,%al' they specify the size of the offset
 438      relative to the segment base.  */
 439   /* 8 bit displacement */
 440   Disp8,
 441   /* 16 bit displacement */
 442   Disp16,
 443   /* 32 bit displacement */
 444   Disp32,
 445   /* 32 bit signed displacement */
 446   Disp32S,
 447   /* 64 bit displacement */
 448   Disp64,
 449   /* Accumulator %al/%ax/%eax/%rax */
 450   Acc,
 451   /* Floating pointer top stack register %st(0) */
 452   FloatAcc,
 453   /* Register which can be used for base or index in memory operand.  */
 454   BaseIndex,
 455   /* Register to hold in/out port addr = dx */
 456   InOutPortReg,
 457   /* Register to hold shift count = cl */
 458   ShiftCount,
 459   /* Absolute address for jump.  */
 460   JumpAbsolute,
 461   /* String insn operand with fixed es segment */
 462   EsSeg,
 463   /* RegMem is for instructions with a modrm byte where the register
 464      destination operand should be encoded in the mod and regmem fields.
 465      Normally, it will be encoded in the reg field. We add a RegMem
 466      flag to the destination register operand to indicate that it should
 467      be encoded in the regmem field.  */
 468   RegMem,
 469   /* Memory.  */
 470   Mem,
 471   /* BYTE memory. */
 472   Byte,
 473   /* WORD memory. 2 byte */
 474   Word,
 475   /* DWORD memory. 4 byte */
 476   Dword,
 477   /* FWORD memory. 6 byte */
 478   Fword,
 479   /* QWORD memory. 8 byte */
 480   Qword,
 481   /* TBYTE memory. 10 byte */
 482   Tbyte,
 483   /* XMMWORD memory. */
 484   Xmmword,
 485   /* YMMWORD memory. */
 486   Ymmword,
 487   /* Unspecified memory size.  */
 488   Unspecified,
 489   /* Any memory size.  */
 490   Anysize,
 491
 492   /* The last bitfield in i386_operand_type.  */
 493   OTMax
 494 };
 495
 496 #define OTNumOfUints \
 497   (OTMax / sizeof (unsigned int) / CHAR_BIT + 1)
 498 #define OTNumOfBits \
 499   (OTNumOfUints * sizeof (unsigned int) * CHAR_BIT)
 500
 501 /* If you get a compiler error for zero width of the unused field,
 502    comment it out.  */
 503 #define OTUnused                (OTMax + 1)
 504
 505 typedef union i386_operand_type
 506 {
 507   struct
 508     {
 509       unsigned int reg8:1;
 510       unsigned int reg16:1;
 511       unsigned int reg32:1;
 512       unsigned int reg64:1;
 513       unsigned int floatreg:1;
 514       unsigned int regmmx:1;
 515       unsigned int regxmm:1;
 516       unsigned int regymm:1;
 517       unsigned int control:1;
 518       unsigned int debug:1;
 519       unsigned int test:1;
 520       unsigned int sreg2:1;
 521       unsigned int sreg3:1;
 522       unsigned int imm1:1;
 523       unsigned int imm8:1;
 524       unsigned int imm8s:1;
 525       unsigned int imm16:1;
 526       unsigned int imm32:1;
 527       unsigned int imm32s:1;
 528       unsigned int imm64:1;
 529       unsigned int disp8:1;
 530       unsigned int disp16:1;
 531       unsigned int disp32:1;
 532       unsigned int disp32s:1;
 533       unsigned int disp64:1;
 534       unsigned int acc:1;
 535       unsigned int floatacc:1;
 536       unsigned int baseindex:1;
 537       unsigned int inoutportreg:1;
 538       unsigned int shiftcount:1;
 539       unsigned int jumpabsolute:1;
 540       unsigned int esseg:1;
 541       unsigned int regmem:1;
 542       unsigned int mem:1;
 543       unsigned int byte:1;
 544       unsigned int word:1;
 545       unsigned int dword:1;
 546       unsigned int fword:1;
 547       unsigned int qword:1;
 548       unsigned int tbyte:1;
 549       unsigned int xmmword:1;
 550       unsigned int ymmword:1;
 551       unsigned int unspecified:1;
 552       unsigned int anysize:1;
 553 #ifdef OTUnused
 554       unsigned int unused:(OTNumOfBits - OTUnused);
 555 #endif
 556     } bitfield;
 557   unsigned int array[OTNumOfUints];
 558 } i386_operand_type;
 559
 560 typedef struct insn_template
 561 {
 562   /* instruction name sans width suffix ("mov" for movl insns) */
 563   char *name;
 564
 565   /* how many operands */
 566   unsigned int operands;
 567
 568   /* base_opcode is the fundamental opcode byte without optional
 569      prefix(es).  */
 570   unsigned int base_opcode;
 571 #define Opcode_D        0x2 /* Direction bit:
 572                                set if Reg --> Regmem;
 573                                unset if Regmem --> Reg. */
 574 #define Opcode_FloatR   0x8 /* Bit to swap src/dest for float insns. */
 575 #define Opcode_FloatD 0x400 /* Direction bit for float insns. */
 576
 577   /* extension_opcode is the 3 bit extension for group <n> insns.
 578      This field is also used to store the 8-bit opcode suffix for the
 579      AMD 3DNow! instructions.
 580      If this template has no extension opcode (the usual case) use None
 581      Instructions */
 582   unsigned int extension_opcode;
 583 #define None 0xffff             /* If no extension_opcode is possible.  */
 584
 585   /* Opcode length.  */
 586   unsigned char opcode_length;
 587
 588   /* cpu feature flags */
 589   i386_cpu_flags cpu_flags;
 590
 591   /* the bits in opcode_modifier are used to generate the final opcode from
 592      the base_opcode.  These bits also are used to detect alternate forms of
 593      the same instruction */
 594   i386_opcode_modifier opcode_modifier;
 595
 596   /* operand_types[i] describes the type of operand i.  This is made
 597      by OR'ing together all of the possible type masks.  (e.g.
 598      'operand_types[i] = Reg|Imm' specifies that operand i can be
 599      either a register or an immediate operand.  */
 600   i386_operand_type operand_types[MAX_OPERANDS];
 601 }
 602 insn_template;
 603
 604 extern const insn_template i386_optab[];
 605
 606 /* these are for register name --> number & type hash lookup */
 607 typedef struct
 608 {
 609   char *reg_name;
 610   i386_operand_type reg_type;
 611   unsigned char reg_flags;
 612 #define RegRex      0x1  /* Extended register.  */
 613 #define RegRex64    0x2  /* Extended 8 bit register.  */
 614   unsigned char reg_num;
 615 #define RegRip  ((unsigned char ) ~0)
 616 #define RegEip  (RegRip - 1)
 617 /* EIZ and RIZ are fake index registers.  */
 618 #define RegEiz  (RegEip - 1)
 619 #define RegRiz  (RegEiz - 1)
 620 /* FLAT is a fake segment register (Intel mode).  */
 621 #define RegFlat     ((unsigned char) ~0)
 622   signed char dw2_regnum[2];
 623 #define Dw2Inval (-1)
 624 }
 625 reg_entry;
 626
 627 /* Entries in i386_regtab.  */
 628 #define REGNAM_AL 1
 629 #define REGNAM_AX 25
 630 #define REGNAM_EAX 41
 631
 632 extern const reg_entry i386_regtab[];
 633 extern const unsigned int i386_regtab_size;
 634
 635 typedef struct
 636 {
 637   char *seg_name;
 638   unsigned int seg_prefix;
 639 }
 640 seg_entry;
 641
 642 extern const seg_entry cs;
 643 extern const seg_entry ds;
 644 extern const seg_entry ss;
 645 extern const seg_entry es;
 646 extern const seg_entry fs;
 647 extern const seg_entry gs;