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Merge remote branch 'origin/master'
[binutils/dougsmingw.git] / opcodes / mips-dis.c
blob203f29fb775199dad386190cbad762cc35fba841
1 /* Print mips instructions for GDB, the GNU debugger, or for objdump.
2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2005, 2006, 2007, 2008, 2009
4 Free Software Foundation, Inc.
5 Contributed by Nobuyuki Hikichi(hikichi@sra.co.jp).
6
7 This file is part of the GNU opcodes library.
8
9 This library is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3, or (at your option)
12 any later version.
13
14 It is distributed in the hope that it will be useful, but WITHOUT
15 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
16 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
17 License for more details.
18
19 You should have received a copy of the GNU General Public License
20 along with this program; if not, write to the Free Software
21 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
22 MA 02110-1301, USA. */
23
24 #include "sysdep.h"
25 #include "dis-asm.h"
26 #include "libiberty.h"
27 #include "opcode/mips.h"
28 #include "opintl.h"
29
30 /* FIXME: These are needed to figure out if the code is mips16 or
31 not. The low bit of the address is often a good indicator. No
32 symbol table is available when this code runs out in an embedded
33 system as when it is used for disassembler support in a monitor. */
34
35 #if !defined(EMBEDDED_ENV)
36 #define SYMTAB_AVAILABLE 1
37 #include "elf-bfd.h"
38 #include "elf/mips.h"
39 #endif
40
41 /* Mips instructions are at maximum this many bytes long. */
42 #define INSNLEN 4
43
44 \f
45 /* FIXME: These should be shared with gdb somehow. */
46
47 struct mips_cp0sel_name
48 {
49 unsigned int cp0reg;
50 unsigned int sel;
51 const char * const name;
52 };
53
54 /* The mips16 registers. */
55 static const unsigned int mips16_to_32_reg_map[] =
56 {
57 16, 17, 2, 3, 4, 5, 6, 7
58 };
59
60 #define mips16_reg_names(rn) mips_gpr_names[mips16_to_32_reg_map[rn]]
61
62
63 static const char * const mips_gpr_names_numeric[32] =
64 {
65 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7",
66 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
67 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
68 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31"
69 };
70
71 static const char * const mips_gpr_names_oldabi[32] =
72 {
73 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
74 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
75 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
76 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
77 };
78
79 static const char * const mips_gpr_names_newabi[32] =
80 {
81 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
82 "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3",
83 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
84 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
85 };
86
87 static const char * const mips_fpr_names_numeric[32] =
88 {
89 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7",
90 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
91 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
92 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31"
93 };
94
95 static const char * const mips_fpr_names_32[32] =
96 {
97 "fv0", "fv0f", "fv1", "fv1f", "ft0", "ft0f", "ft1", "ft1f",
98 "ft2", "ft2f", "ft3", "ft3f", "fa0", "fa0f", "fa1", "fa1f",
99 "ft4", "ft4f", "ft5", "ft5f", "fs0", "fs0f", "fs1", "fs1f",
100 "fs2", "fs2f", "fs3", "fs3f", "fs4", "fs4f", "fs5", "fs5f"
101 };
102
103 static const char * const mips_fpr_names_n32[32] =
104 {
105 "fv0", "ft14", "fv1", "ft15", "ft0", "ft1", "ft2", "ft3",
106 "ft4", "ft5", "ft6", "ft7", "fa0", "fa1", "fa2", "fa3",
107 "fa4", "fa5", "fa6", "fa7", "fs0", "ft8", "fs1", "ft9",
108 "fs2", "ft10", "fs3", "ft11", "fs4", "ft12", "fs5", "ft13"
109 };
110
111 static const char * const mips_fpr_names_64[32] =
112 {
113 "fv0", "ft12", "fv1", "ft13", "ft0", "ft1", "ft2", "ft3",
114 "ft4", "ft5", "ft6", "ft7", "fa0", "fa1", "fa2", "fa3",
115 "fa4", "fa5", "fa6", "fa7", "ft8", "ft9", "ft10", "ft11",
116 "fs0", "fs1", "fs2", "fs3", "fs4", "fs5", "fs6", "fs7"
117 };
118
119 static const char * const mips_cp0_names_numeric[32] =
120 {
121 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7",
122 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
123 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
124 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31"
125 };
126
127 static const char * const mips_cp0_names_r3000[32] =
128 {
129 "c0_index", "c0_random", "c0_entrylo", "$3",
130 "c0_context", "$5", "$6", "$7",
131 "c0_badvaddr", "$9", "c0_entryhi", "$11",
132 "c0_sr", "c0_cause", "c0_epc", "c0_prid",
133 "$16", "$17", "$18", "$19",
134 "$20", "$21", "$22", "$23",
135 "$24", "$25", "$26", "$27",
136 "$28", "$29", "$30", "$31",
137 };
138
139 static const char * const mips_cp0_names_r4000[32] =
140 {
141 "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1",
142 "c0_context", "c0_pagemask", "c0_wired", "$7",
143 "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare",
144 "c0_sr", "c0_cause", "c0_epc", "c0_prid",
145 "c0_config", "c0_lladdr", "c0_watchlo", "c0_watchhi",
146 "c0_xcontext", "$21", "$22", "$23",
147 "$24", "$25", "c0_ecc", "c0_cacheerr",
148 "c0_taglo", "c0_taghi", "c0_errorepc", "$31",
149 };
150
151 static const char * const mips_cp0_names_mips3264[32] =
152 {
153 "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1",
154 "c0_context", "c0_pagemask", "c0_wired", "$7",
155 "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare",
156 "c0_status", "c0_cause", "c0_epc", "c0_prid",
157 "c0_config", "c0_lladdr", "c0_watchlo", "c0_watchhi",
158 "c0_xcontext", "$21", "$22", "c0_debug",
159 "c0_depc", "c0_perfcnt", "c0_errctl", "c0_cacheerr",
160 "c0_taglo", "c0_taghi", "c0_errorepc", "c0_desave",
161 };
162
163 static const struct mips_cp0sel_name mips_cp0sel_names_mips3264[] =
164 {
165 { 16, 1, "c0_config1" },
166 { 16, 2, "c0_config2" },
167 { 16, 3, "c0_config3" },
168 { 18, 1, "c0_watchlo,1" },
169 { 18, 2, "c0_watchlo,2" },
170 { 18, 3, "c0_watchlo,3" },
171 { 18, 4, "c0_watchlo,4" },
172 { 18, 5, "c0_watchlo,5" },
173 { 18, 6, "c0_watchlo,6" },
174 { 18, 7, "c0_watchlo,7" },
175 { 19, 1, "c0_watchhi,1" },
176 { 19, 2, "c0_watchhi,2" },
177 { 19, 3, "c0_watchhi,3" },
178 { 19, 4, "c0_watchhi,4" },
179 { 19, 5, "c0_watchhi,5" },
180 { 19, 6, "c0_watchhi,6" },
181 { 19, 7, "c0_watchhi,7" },
182 { 25, 1, "c0_perfcnt,1" },
183 { 25, 2, "c0_perfcnt,2" },
184 { 25, 3, "c0_perfcnt,3" },
185 { 25, 4, "c0_perfcnt,4" },
186 { 25, 5, "c0_perfcnt,5" },
187 { 25, 6, "c0_perfcnt,6" },
188 { 25, 7, "c0_perfcnt,7" },
189 { 27, 1, "c0_cacheerr,1" },
190 { 27, 2, "c0_cacheerr,2" },
191 { 27, 3, "c0_cacheerr,3" },
192 { 28, 1, "c0_datalo" },
193 { 29, 1, "c0_datahi" }
194 };
195
196 static const char * const mips_cp0_names_mips3264r2[32] =
197 {
198 "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1",
199 "c0_context", "c0_pagemask", "c0_wired", "c0_hwrena",
200 "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare",
201 "c0_status", "c0_cause", "c0_epc", "c0_prid",
202 "c0_config", "c0_lladdr", "c0_watchlo", "c0_watchhi",
203 "c0_xcontext", "$21", "$22", "c0_debug",
204 "c0_depc", "c0_perfcnt", "c0_errctl", "c0_cacheerr",
205 "c0_taglo", "c0_taghi", "c0_errorepc", "c0_desave",
206 };
207
208 static const struct mips_cp0sel_name mips_cp0sel_names_mips3264r2[] =
209 {
210 { 4, 1, "c0_contextconfig" },
211 { 0, 1, "c0_mvpcontrol" },
212 { 0, 2, "c0_mvpconf0" },
213 { 0, 3, "c0_mvpconf1" },
214 { 1, 1, "c0_vpecontrol" },
215 { 1, 2, "c0_vpeconf0" },
216 { 1, 3, "c0_vpeconf1" },
217 { 1, 4, "c0_yqmask" },
218 { 1, 5, "c0_vpeschedule" },
219 { 1, 6, "c0_vpeschefback" },
220 { 2, 1, "c0_tcstatus" },
221 { 2, 2, "c0_tcbind" },
222 { 2, 3, "c0_tcrestart" },
223 { 2, 4, "c0_tchalt" },
224 { 2, 5, "c0_tccontext" },
225 { 2, 6, "c0_tcschedule" },
226 { 2, 7, "c0_tcschefback" },
227 { 5, 1, "c0_pagegrain" },
228 { 6, 1, "c0_srsconf0" },
229 { 6, 2, "c0_srsconf1" },
230 { 6, 3, "c0_srsconf2" },
231 { 6, 4, "c0_srsconf3" },
232 { 6, 5, "c0_srsconf4" },
233 { 12, 1, "c0_intctl" },
234 { 12, 2, "c0_srsctl" },
235 { 12, 3, "c0_srsmap" },
236 { 15, 1, "c0_ebase" },
237 { 16, 1, "c0_config1" },
238 { 16, 2, "c0_config2" },
239 { 16, 3, "c0_config3" },
240 { 18, 1, "c0_watchlo,1" },
241 { 18, 2, "c0_watchlo,2" },
242 { 18, 3, "c0_watchlo,3" },
243 { 18, 4, "c0_watchlo,4" },
244 { 18, 5, "c0_watchlo,5" },
245 { 18, 6, "c0_watchlo,6" },
246 { 18, 7, "c0_watchlo,7" },
247 { 19, 1, "c0_watchhi,1" },
248 { 19, 2, "c0_watchhi,2" },
249 { 19, 3, "c0_watchhi,3" },
250 { 19, 4, "c0_watchhi,4" },
251 { 19, 5, "c0_watchhi,5" },
252 { 19, 6, "c0_watchhi,6" },
253 { 19, 7, "c0_watchhi,7" },
254 { 23, 1, "c0_tracecontrol" },
255 { 23, 2, "c0_tracecontrol2" },
256 { 23, 3, "c0_usertracedata" },
257 { 23, 4, "c0_tracebpc" },
258 { 25, 1, "c0_perfcnt,1" },
259 { 25, 2, "c0_perfcnt,2" },
260 { 25, 3, "c0_perfcnt,3" },
261 { 25, 4, "c0_perfcnt,4" },
262 { 25, 5, "c0_perfcnt,5" },
263 { 25, 6, "c0_perfcnt,6" },
264 { 25, 7, "c0_perfcnt,7" },
265 { 27, 1, "c0_cacheerr,1" },
266 { 27, 2, "c0_cacheerr,2" },
267 { 27, 3, "c0_cacheerr,3" },
268 { 28, 1, "c0_datalo" },
269 { 28, 2, "c0_taglo1" },
270 { 28, 3, "c0_datalo1" },
271 { 28, 4, "c0_taglo2" },
272 { 28, 5, "c0_datalo2" },
273 { 28, 6, "c0_taglo3" },
274 { 28, 7, "c0_datalo3" },
275 { 29, 1, "c0_datahi" },
276 { 29, 2, "c0_taghi1" },
277 { 29, 3, "c0_datahi1" },
278 { 29, 4, "c0_taghi2" },
279 { 29, 5, "c0_datahi2" },
280 { 29, 6, "c0_taghi3" },
281 { 29, 7, "c0_datahi3" },
282 };
283
284 /* SB-1: MIPS64 (mips_cp0_names_mips3264) with minor mods. */
285 static const char * const mips_cp0_names_sb1[32] =
286 {
287 "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1",
288 "c0_context", "c0_pagemask", "c0_wired", "$7",
289 "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare",
290 "c0_status", "c0_cause", "c0_epc", "c0_prid",
291 "c0_config", "c0_lladdr", "c0_watchlo", "c0_watchhi",
292 "c0_xcontext", "$21", "$22", "c0_debug",
293 "c0_depc", "c0_perfcnt", "c0_errctl", "c0_cacheerr_i",
294 "c0_taglo_i", "c0_taghi_i", "c0_errorepc", "c0_desave",
295 };
296
297 static const struct mips_cp0sel_name mips_cp0sel_names_sb1[] =
298 {
299 { 16, 1, "c0_config1" },
300 { 18, 1, "c0_watchlo,1" },
301 { 19, 1, "c0_watchhi,1" },
302 { 22, 0, "c0_perftrace" },
303 { 23, 3, "c0_edebug" },
304 { 25, 1, "c0_perfcnt,1" },
305 { 25, 2, "c0_perfcnt,2" },
306 { 25, 3, "c0_perfcnt,3" },
307 { 25, 4, "c0_perfcnt,4" },
308 { 25, 5, "c0_perfcnt,5" },
309 { 25, 6, "c0_perfcnt,6" },
310 { 25, 7, "c0_perfcnt,7" },
311 { 26, 1, "c0_buserr_pa" },
312 { 27, 1, "c0_cacheerr_d" },
313 { 27, 3, "c0_cacheerr_d_pa" },
314 { 28, 1, "c0_datalo_i" },
315 { 28, 2, "c0_taglo_d" },
316 { 28, 3, "c0_datalo_d" },
317 { 29, 1, "c0_datahi_i" },
318 { 29, 2, "c0_taghi_d" },
319 { 29, 3, "c0_datahi_d" },
320 };
321
322 /* Xlr cop0 register names. */
323 static const char * const mips_cp0_names_xlr[32] = {
324 "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1",
325 "c0_context", "c0_pagemask", "c0_wired", "$7",
326 "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare",
327 "c0_status", "c0_cause", "c0_epc", "c0_prid",
328 "c0_config", "c0_lladdr", "c0_watchlo", "c0_watchhi",
329 "c0_xcontext", "$21", "$22", "c0_debug",
330 "c0_depc", "c0_perfcnt", "c0_errctl", "c0_cacheerr_i",
331 "c0_taglo_i", "c0_taghi_i", "c0_errorepc", "c0_desave",
332 };
333
334 /* XLR's CP0 Select Registers. */
335
336 static const struct mips_cp0sel_name mips_cp0sel_names_xlr[] = {
337 { 9, 6, "c0_extintreq" },
338 { 9, 7, "c0_extintmask" },
339 { 15, 1, "c0_ebase" },
340 { 16, 1, "c0_config1" },
341 { 16, 2, "c0_config2" },
342 { 16, 3, "c0_config3" },
343 { 16, 7, "c0_procid2" },
344 { 18, 1, "c0_watchlo,1" },
345 { 18, 2, "c0_watchlo,2" },
346 { 18, 3, "c0_watchlo,3" },
347 { 18, 4, "c0_watchlo,4" },
348 { 18, 5, "c0_watchlo,5" },
349 { 18, 6, "c0_watchlo,6" },
350 { 18, 7, "c0_watchlo,7" },
351 { 19, 1, "c0_watchhi,1" },
352 { 19, 2, "c0_watchhi,2" },
353 { 19, 3, "c0_watchhi,3" },
354 { 19, 4, "c0_watchhi,4" },
355 { 19, 5, "c0_watchhi,5" },
356 { 19, 6, "c0_watchhi,6" },
357 { 19, 7, "c0_watchhi,7" },
358 { 25, 1, "c0_perfcnt,1" },
359 { 25, 2, "c0_perfcnt,2" },
360 { 25, 3, "c0_perfcnt,3" },
361 { 25, 4, "c0_perfcnt,4" },
362 { 25, 5, "c0_perfcnt,5" },
363 { 25, 6, "c0_perfcnt,6" },
364 { 25, 7, "c0_perfcnt,7" },
365 { 27, 1, "c0_cacheerr,1" },
366 { 27, 2, "c0_cacheerr,2" },
367 { 27, 3, "c0_cacheerr,3" },
368 { 28, 1, "c0_datalo" },
369 { 29, 1, "c0_datahi" }
370 };
371
372 static const char * const mips_hwr_names_numeric[32] =
373 {
374 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7",
375 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
376 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
377 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31"
378 };
379
380 static const char * const mips_hwr_names_mips3264r2[32] =
381 {
382 "hwr_cpunum", "hwr_synci_step", "hwr_cc", "hwr_ccres",
383 "$4", "$5", "$6", "$7",
384 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
385 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
386 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31"
387 };
388
389 struct mips_abi_choice
390 {
391 const char * name;
392 const char * const *gpr_names;
393 const char * const *fpr_names;
394 };
395
396 struct mips_abi_choice mips_abi_choices[] =
397 {
398 { "numeric", mips_gpr_names_numeric, mips_fpr_names_numeric },
399 { "32", mips_gpr_names_oldabi, mips_fpr_names_32 },
400 { "n32", mips_gpr_names_newabi, mips_fpr_names_n32 },
401 { "64", mips_gpr_names_newabi, mips_fpr_names_64 },
402 };
403
404 struct mips_arch_choice
405 {
406 const char *name;
407 int bfd_mach_valid;
408 unsigned long bfd_mach;
409 int processor;
410 int isa;
411 const char * const *cp0_names;
412 const struct mips_cp0sel_name *cp0sel_names;
413 unsigned int cp0sel_names_len;
414 const char * const *hwr_names;
415 };
416
417 const struct mips_arch_choice mips_arch_choices[] =
418 {
419 { "numeric", 0, 0, 0, 0,
420 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
421
422 { "r3000", 1, bfd_mach_mips3000, CPU_R3000, ISA_MIPS1,
423 mips_cp0_names_r3000, NULL, 0, mips_hwr_names_numeric },
424 { "r3900", 1, bfd_mach_mips3900, CPU_R3900, ISA_MIPS1,
425 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
426 { "r4000", 1, bfd_mach_mips4000, CPU_R4000, ISA_MIPS3,
427 mips_cp0_names_r4000, NULL, 0, mips_hwr_names_numeric },
428 { "r4010", 1, bfd_mach_mips4010, CPU_R4010, ISA_MIPS2,
429 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
430 { "vr4100", 1, bfd_mach_mips4100, CPU_VR4100, ISA_MIPS3,
431 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
432 { "vr4111", 1, bfd_mach_mips4111, CPU_R4111, ISA_MIPS3,
433 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
434 { "vr4120", 1, bfd_mach_mips4120, CPU_VR4120, ISA_MIPS3,
435 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
436 { "r4300", 1, bfd_mach_mips4300, CPU_R4300, ISA_MIPS3,
437 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
438 { "r4400", 1, bfd_mach_mips4400, CPU_R4400, ISA_MIPS3,
439 mips_cp0_names_r4000, NULL, 0, mips_hwr_names_numeric },
440 { "r4600", 1, bfd_mach_mips4600, CPU_R4600, ISA_MIPS3,
441 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
442 { "r4650", 1, bfd_mach_mips4650, CPU_R4650, ISA_MIPS3,
443 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
444 { "r5000", 1, bfd_mach_mips5000, CPU_R5000, ISA_MIPS4,
445 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
446 { "vr5400", 1, bfd_mach_mips5400, CPU_VR5400, ISA_MIPS4,
447 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
448 { "vr5500", 1, bfd_mach_mips5500, CPU_VR5500, ISA_MIPS4,
449 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
450 { "r6000", 1, bfd_mach_mips6000, CPU_R6000, ISA_MIPS2,
451 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
452 { "rm7000", 1, bfd_mach_mips7000, CPU_RM7000, ISA_MIPS4,
453 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
454 { "rm9000", 1, bfd_mach_mips7000, CPU_RM7000, ISA_MIPS4,
455 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
456 { "r8000", 1, bfd_mach_mips8000, CPU_R8000, ISA_MIPS4,
457 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
458 { "r10000", 1, bfd_mach_mips10000, CPU_R10000, ISA_MIPS4,
459 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
460 { "r12000", 1, bfd_mach_mips12000, CPU_R12000, ISA_MIPS4,
461 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
462 { "r14000", 1, bfd_mach_mips14000, CPU_R14000, ISA_MIPS4,
463 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
464 { "r16000", 1, bfd_mach_mips16000, CPU_R16000, ISA_MIPS4,
465 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
466 { "mips5", 1, bfd_mach_mips5, CPU_MIPS5, ISA_MIPS5,
467 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
468
469 /* For stock MIPS32, disassemble all applicable MIPS-specified ASEs.
470 Note that MIPS-3D and MDMX are not applicable to MIPS32. (See
471 _MIPS32 Architecture For Programmers Volume I: Introduction to the
472 MIPS32 Architecture_ (MIPS Document Number MD00082, Revision 0.95),
473 page 1. */
474 { "mips32", 1, bfd_mach_mipsisa32, CPU_MIPS32,
475 ISA_MIPS32 | INSN_MIPS16 | INSN_SMARTMIPS,
476 mips_cp0_names_mips3264,
477 mips_cp0sel_names_mips3264, ARRAY_SIZE (mips_cp0sel_names_mips3264),
478 mips_hwr_names_numeric },
479
480 { "mips32r2", 1, bfd_mach_mipsisa32r2, CPU_MIPS32R2,
481 (ISA_MIPS32R2 | INSN_MIPS16 | INSN_SMARTMIPS | INSN_DSP | INSN_DSPR2
482 | INSN_MIPS3D | INSN_MT),
483 mips_cp0_names_mips3264r2,
484 mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2),
485 mips_hwr_names_mips3264r2 },
486
487 /* For stock MIPS64, disassemble all applicable MIPS-specified ASEs. */
488 { "mips64", 1, bfd_mach_mipsisa64, CPU_MIPS64,
489 ISA_MIPS64 | INSN_MIPS16 | INSN_MIPS3D | INSN_MDMX,
490 mips_cp0_names_mips3264,
491 mips_cp0sel_names_mips3264, ARRAY_SIZE (mips_cp0sel_names_mips3264),
492 mips_hwr_names_numeric },
493
494 { "mips64r2", 1, bfd_mach_mipsisa64r2, CPU_MIPS64R2,
495 (ISA_MIPS64R2 | INSN_MIPS16 | INSN_MIPS3D | INSN_DSP | INSN_DSPR2
496 | INSN_DSP64 | INSN_MT | INSN_MDMX),
497 mips_cp0_names_mips3264r2,
498 mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2),
499 mips_hwr_names_mips3264r2 },
500
501 { "sb1", 1, bfd_mach_mips_sb1, CPU_SB1,
502 ISA_MIPS64 | INSN_MIPS3D | INSN_SB1,
503 mips_cp0_names_sb1,
504 mips_cp0sel_names_sb1, ARRAY_SIZE (mips_cp0sel_names_sb1),
505 mips_hwr_names_numeric },
506
507 { "loongson2e", 1, bfd_mach_mips_loongson_2e, CPU_LOONGSON_2E,
508 ISA_MIPS3 | INSN_LOONGSON_2E, mips_cp0_names_numeric,
509 NULL, 0, mips_hwr_names_numeric },
510
511 { "loongson2f", 1, bfd_mach_mips_loongson_2f, CPU_LOONGSON_2F,
512 ISA_MIPS3 | INSN_LOONGSON_2F, mips_cp0_names_numeric,
513 NULL, 0, mips_hwr_names_numeric },
514
515 { "octeon", 1, bfd_mach_mips_octeon, CPU_OCTEON,
516 ISA_MIPS64R2 | INSN_OCTEON, mips_cp0_names_numeric, NULL, 0,
517 mips_hwr_names_numeric },
518
519 { "xlr", 1, bfd_mach_mips_xlr, CPU_XLR,
520 ISA_MIPS64 | INSN_XLR,
521 mips_cp0_names_xlr,
522 mips_cp0sel_names_xlr, ARRAY_SIZE (mips_cp0sel_names_xlr),
523 mips_hwr_names_numeric },
524
525 /* This entry, mips16, is here only for ISA/processor selection; do
526 not print its name. */
527 { "", 1, bfd_mach_mips16, CPU_MIPS16, ISA_MIPS3 | INSN_MIPS16,
528 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
529 };
530
531 /* ISA and processor type to disassemble for, and register names to use.
532 set_default_mips_dis_options and parse_mips_dis_options fill in these
533 values. */
534 static int mips_processor;
535 static int mips_isa;
536 static const char * const *mips_gpr_names;
537 static const char * const *mips_fpr_names;
538 static const char * const *mips_cp0_names;
539 static const struct mips_cp0sel_name *mips_cp0sel_names;
540 static int mips_cp0sel_names_len;
541 static const char * const *mips_hwr_names;
542
543 /* Other options */
544 static int no_aliases; /* If set disassemble as most general inst. */
545 \f
546 static const struct mips_abi_choice *
547 choose_abi_by_name (const char *name, unsigned int namelen)
548 {
549 const struct mips_abi_choice *c;
550 unsigned int i;
551
552 for (i = 0, c = NULL; i < ARRAY_SIZE (mips_abi_choices) && c == NULL; i++)
553 if (strncmp (mips_abi_choices[i].name, name, namelen) == 0
554 && strlen (mips_abi_choices[i].name) == namelen)
555 c = &mips_abi_choices[i];
556
557 return c;
558 }
559
560 static const struct mips_arch_choice *
561 choose_arch_by_name (const char *name, unsigned int namelen)
562 {
563 const struct mips_arch_choice *c = NULL;
564 unsigned int i;
565
566 for (i = 0, c = NULL; i < ARRAY_SIZE (mips_arch_choices) && c == NULL; i++)
567 if (strncmp (mips_arch_choices[i].name, name, namelen) == 0
568 && strlen (mips_arch_choices[i].name) == namelen)
569 c = &mips_arch_choices[i];
570
571 return c;
572 }
573
574 static const struct mips_arch_choice *
575 choose_arch_by_number (unsigned long mach)
576 {
577 static unsigned long hint_bfd_mach;
578 static const struct mips_arch_choice *hint_arch_choice;
579 const struct mips_arch_choice *c;
580 unsigned int i;
581
582 /* We optimize this because even if the user specifies no
583 flags, this will be done for every instruction! */
584 if (hint_bfd_mach == mach
585 && hint_arch_choice != NULL
586 && hint_arch_choice->bfd_mach == hint_bfd_mach)
587 return hint_arch_choice;
588
589 for (i = 0, c = NULL; i < ARRAY_SIZE (mips_arch_choices) && c == NULL; i++)
590 {
591 if (mips_arch_choices[i].bfd_mach_valid
592 && mips_arch_choices[i].bfd_mach == mach)
593 {
594 c = &mips_arch_choices[i];
595 hint_bfd_mach = mach;
596 hint_arch_choice = c;
597 }
598 }
599 return c;
600 }
601
602 /* Check if the object uses NewABI conventions. */
603
604 static int
605 is_newabi (Elf_Internal_Ehdr *header)
606 {
607 /* There are no old-style ABIs which use 64-bit ELF. */
608 if (header->e_ident[EI_CLASS] == ELFCLASS64)
609 return 1;
610
611 /* If a 32-bit ELF file, n32 is a new-style ABI. */
612 if ((header->e_flags & EF_MIPS_ABI2) != 0)
613 return 1;
614
615 return 0;
616 }
617
618 static void
619 set_default_mips_dis_options (struct disassemble_info *info)
620 {
621 const struct mips_arch_choice *chosen_arch;
622
623 /* Defaults: mipsIII/r3000 (?!), (o)32-style ("oldabi") GPR names,
624 and numeric FPR, CP0 register, and HWR names. */
625 mips_isa = ISA_MIPS3;
626 mips_processor = CPU_R3000;
627 mips_gpr_names = mips_gpr_names_oldabi;
628 mips_fpr_names = mips_fpr_names_numeric;
629 mips_cp0_names = mips_cp0_names_numeric;
630 mips_cp0sel_names = NULL;
631 mips_cp0sel_names_len = 0;
632 mips_hwr_names = mips_hwr_names_numeric;
633 no_aliases = 0;
634
635 /* If an ELF "newabi" binary, use the n32/(n)64 GPR names. */
636 if (info->flavour == bfd_target_elf_flavour && info->section != NULL)
637 {
638 Elf_Internal_Ehdr *header;
639
640 header = elf_elfheader (info->section->owner);
641 if (is_newabi (header))
642 mips_gpr_names = mips_gpr_names_newabi;
643 }
644
645 /* Set ISA, architecture, and cp0 register names as best we can. */
646 #if ! SYMTAB_AVAILABLE
647 /* This is running out on a target machine, not in a host tool.
648 FIXME: Where does mips_target_info come from? */
649 target_processor = mips_target_info.processor;
650 mips_isa = mips_target_info.isa;
651 #else
652 chosen_arch = choose_arch_by_number (info->mach);
653 if (chosen_arch != NULL)
654 {
655 mips_processor = chosen_arch->processor;
656 mips_isa = chosen_arch->isa;
657 mips_cp0_names = chosen_arch->cp0_names;
658 mips_cp0sel_names = chosen_arch->cp0sel_names;
659 mips_cp0sel_names_len = chosen_arch->cp0sel_names_len;
660 mips_hwr_names = chosen_arch->hwr_names;
661 }
662 #endif
663 }
664
665 static void
666 parse_mips_dis_option (const char *option, unsigned int len)
667 {
668 unsigned int i, optionlen, vallen;
669 const char *val;
670 const struct mips_abi_choice *chosen_abi;
671 const struct mips_arch_choice *chosen_arch;
672
673 /* Try to match options that are simple flags */
674 if (CONST_STRNEQ (option, "no-aliases"))
675 {
676 no_aliases = 1;
677 return;
678 }
679
680 /* Look for the = that delimits the end of the option name. */
681 for (i = 0; i < len; i++)
682 if (option[i] == '=')
683 break;
684
685 if (i == 0) /* Invalid option: no name before '='. */
686 return;
687 if (i == len) /* Invalid option: no '='. */
688 return;
689 if (i == (len - 1)) /* Invalid option: no value after '='. */
690 return;
691
692 optionlen = i;
693 val = option + (optionlen + 1);
694 vallen = len - (optionlen + 1);
695
696 if (strncmp ("gpr-names", option, optionlen) == 0
697 && strlen ("gpr-names") == optionlen)
698 {
699 chosen_abi = choose_abi_by_name (val, vallen);
700 if (chosen_abi != NULL)
701 mips_gpr_names = chosen_abi->gpr_names;
702 return;
703 }
704
705 if (strncmp ("fpr-names", option, optionlen) == 0
706 && strlen ("fpr-names") == optionlen)
707 {
708 chosen_abi = choose_abi_by_name (val, vallen);
709 if (chosen_abi != NULL)
710 mips_fpr_names = chosen_abi->fpr_names;
711 return;
712 }
713
714 if (strncmp ("cp0-names", option, optionlen) == 0
715 && strlen ("cp0-names") == optionlen)
716 {
717 chosen_arch = choose_arch_by_name (val, vallen);
718 if (chosen_arch != NULL)
719 {
720 mips_cp0_names = chosen_arch->cp0_names;
721 mips_cp0sel_names = chosen_arch->cp0sel_names;
722 mips_cp0sel_names_len = chosen_arch->cp0sel_names_len;
723 }
724 return;
725 }
726
727 if (strncmp ("hwr-names", option, optionlen) == 0
728 && strlen ("hwr-names") == optionlen)
729 {
730 chosen_arch = choose_arch_by_name (val, vallen);
731 if (chosen_arch != NULL)
732 mips_hwr_names = chosen_arch->hwr_names;
733 return;
734 }
735
736 if (strncmp ("reg-names", option, optionlen) == 0
737 && strlen ("reg-names") == optionlen)
738 {
739 /* We check both ABI and ARCH here unconditionally, so
740 that "numeric" will do the desirable thing: select
741 numeric register names for all registers. Other than
742 that, a given name probably won't match both. */
743 chosen_abi = choose_abi_by_name (val, vallen);
744 if (chosen_abi != NULL)
745 {
746 mips_gpr_names = chosen_abi->gpr_names;
747 mips_fpr_names = chosen_abi->fpr_names;
748 }
749 chosen_arch = choose_arch_by_name (val, vallen);
750 if (chosen_arch != NULL)
751 {
752 mips_cp0_names = chosen_arch->cp0_names;
753 mips_cp0sel_names = chosen_arch->cp0sel_names;
754 mips_cp0sel_names_len = chosen_arch->cp0sel_names_len;
755 mips_hwr_names = chosen_arch->hwr_names;
756 }
757 return;
758 }
759
760 /* Invalid option. */
761 }
762
763 static void
764 parse_mips_dis_options (const char *options)
765 {
766 const char *option_end;
767
768 if (options == NULL)
769 return;
770
771 while (*options != '\0')
772 {
773 /* Skip empty options. */
774 if (*options == ',')
775 {
776 options++;
777 continue;
778 }
779
780 /* We know that *options is neither NUL or a comma. */
781 option_end = options + 1;
782 while (*option_end != ',' && *option_end != '\0')
783 option_end++;
784
785 parse_mips_dis_option (options, option_end - options);
786
787 /* Go on to the next one. If option_end points to a comma, it
788 will be skipped above. */
789 options = option_end;
790 }
791 }
792
793 static const struct mips_cp0sel_name *
794 lookup_mips_cp0sel_name (const struct mips_cp0sel_name *names,
795 unsigned int len,
796 unsigned int cp0reg,
797 unsigned int sel)
798 {
799 unsigned int i;
800
801 for (i = 0; i < len; i++)
802 if (names[i].cp0reg == cp0reg && names[i].sel == sel)
803 return &names[i];
804 return NULL;
805 }
806 \f
807 /* Print insn arguments for 32/64-bit code. */
808
809 static void
810 print_insn_args (const char *d,
811 register unsigned long int l,
812 bfd_vma pc,
813 struct disassemble_info *info,
814 const struct mips_opcode *opp)
815 {
816 int op, delta;
817 unsigned int lsb, msb, msbd;
818
819 lsb = 0;
820
821 for (; *d != '\0'; d++)
822 {
823 switch (*d)
824 {
825 case ',':
826 case '(':
827 case ')':
828 case '[':
829 case ']':
830 (*info->fprintf_func) (info->stream, "%c", *d);
831 break;
832
833 case '+':
834 /* Extension character; switch for second char. */
835 d++;
836 switch (*d)
837 {
838 case '\0':
839 /* xgettext:c-format */
840 (*info->fprintf_func) (info->stream,
841 _("# internal error, incomplete extension sequence (+)"));
842 return;
843
844 case 'A':
845 lsb = (l >> OP_SH_SHAMT) & OP_MASK_SHAMT;
846 (*info->fprintf_func) (info->stream, "0x%x", lsb);
847 break;
848
849 case 'B':
850 msb = (l >> OP_SH_INSMSB) & OP_MASK_INSMSB;
851 (*info->fprintf_func) (info->stream, "0x%x", msb - lsb + 1);
852 break;
853
854 case '1':
855 (*info->fprintf_func) (info->stream, "0x%lx",
856 (l >> OP_SH_UDI1) & OP_MASK_UDI1);
857 break;
858
859 case '2':
860 (*info->fprintf_func) (info->stream, "0x%lx",
861 (l >> OP_SH_UDI2) & OP_MASK_UDI2);
862 break;
863
864 case '3':
865 (*info->fprintf_func) (info->stream, "0x%lx",
866 (l >> OP_SH_UDI3) & OP_MASK_UDI3);
867 break;
868
869 case '4':
870 (*info->fprintf_func) (info->stream, "0x%lx",
871 (l >> OP_SH_UDI4) & OP_MASK_UDI4);
872 break;
873
874 case 'C':
875 case 'H':
876 msbd = (l >> OP_SH_EXTMSBD) & OP_MASK_EXTMSBD;
877 (*info->fprintf_func) (info->stream, "0x%x", msbd + 1);
878 break;
879
880 case 'D':
881 {
882 const struct mips_cp0sel_name *n;
883 unsigned int cp0reg, sel;
884
885 cp0reg = (l >> OP_SH_RD) & OP_MASK_RD;
886 sel = (l >> OP_SH_SEL) & OP_MASK_SEL;
887
888 /* CP0 register including 'sel' code for mtcN (et al.), to be
889 printed textually if known. If not known, print both
890 CP0 register name and sel numerically since CP0 register
891 with sel 0 may have a name unrelated to register being
892 printed. */
893 n = lookup_mips_cp0sel_name(mips_cp0sel_names,
894 mips_cp0sel_names_len, cp0reg, sel);
895 if (n != NULL)
896 (*info->fprintf_func) (info->stream, "%s", n->name);
897 else
898 (*info->fprintf_func) (info->stream, "$%d,%d", cp0reg, sel);
899 break;
900 }
901
902 case 'E':
903 lsb = ((l >> OP_SH_SHAMT) & OP_MASK_SHAMT) + 32;
904 (*info->fprintf_func) (info->stream, "0x%x", lsb);
905 break;
906
907 case 'F':
908 msb = ((l >> OP_SH_INSMSB) & OP_MASK_INSMSB) + 32;
909 (*info->fprintf_func) (info->stream, "0x%x", msb - lsb + 1);
910 break;
911
912 case 'G':
913 msbd = ((l >> OP_SH_EXTMSBD) & OP_MASK_EXTMSBD) + 32;
914 (*info->fprintf_func) (info->stream, "0x%x", msbd + 1);
915 break;
916
917 case 't': /* Coprocessor 0 reg name */
918 (*info->fprintf_func) (info->stream, "%s",
919 mips_cp0_names[(l >> OP_SH_RT) &
920 OP_MASK_RT]);
921 break;
922
923 case 'T': /* Coprocessor 0 reg name */
924 {
925 const struct mips_cp0sel_name *n;
926 unsigned int cp0reg, sel;
927
928 cp0reg = (l >> OP_SH_RT) & OP_MASK_RT;
929 sel = (l >> OP_SH_SEL) & OP_MASK_SEL;
930
931 /* CP0 register including 'sel' code for mftc0, to be
932 printed textually if known. If not known, print both
933 CP0 register name and sel numerically since CP0 register
934 with sel 0 may have a name unrelated to register being
935 printed. */
936 n = lookup_mips_cp0sel_name(mips_cp0sel_names,
937 mips_cp0sel_names_len, cp0reg, sel);
938 if (n != NULL)
939 (*info->fprintf_func) (info->stream, "%s", n->name);
940 else
941 (*info->fprintf_func) (info->stream, "$%d,%d", cp0reg, sel);
942 break;
943 }
944
945 case 'x': /* bbit bit index */
946 (*info->fprintf_func) (info->stream, "0x%lx",
947 (l >> OP_SH_BBITIND) & OP_MASK_BBITIND);
948 break;
949
950 case 'p': /* cins, cins32, exts and exts32 position */
951 (*info->fprintf_func) (info->stream, "0x%lx",
952 (l >> OP_SH_CINSPOS) & OP_MASK_CINSPOS);
953 break;
954
955 case 's': /* cins and exts length-minus-one */
956 (*info->fprintf_func) (info->stream, "0x%lx",
957 (l >> OP_SH_CINSLM1) & OP_MASK_CINSLM1);
958 break;
959
960 case 'S': /* cins32 and exts32 length-minus-one field */
961 (*info->fprintf_func) (info->stream, "0x%lx",
962 (l >> OP_SH_CINSLM1) & OP_MASK_CINSLM1);
963 break;
964
965 case 'Q': /* seqi/snei immediate field */
966 op = (l >> OP_SH_SEQI) & OP_MASK_SEQI;
967 /* Sign-extend it. */
968 op = (op ^ 512) - 512;
969 (*info->fprintf_func) (info->stream, "%d", op);
970 break;
971
972 default:
973 /* xgettext:c-format */
974 (*info->fprintf_func) (info->stream,
975 _("# internal error, undefined extension sequence (+%c)"),
976 *d);
977 return;
978 }
979 break;
980
981 case '2':
982 (*info->fprintf_func) (info->stream, "0x%lx",
983 (l >> OP_SH_BP) & OP_MASK_BP);
984 break;
985
986 case '3':
987 (*info->fprintf_func) (info->stream, "0x%lx",
988 (l >> OP_SH_SA3) & OP_MASK_SA3);
989 break;
990
991 case '4':
992 (*info->fprintf_func) (info->stream, "0x%lx",
993 (l >> OP_SH_SA4) & OP_MASK_SA4);
994 break;
995
996 case '5':
997 (*info->fprintf_func) (info->stream, "0x%lx",
998 (l >> OP_SH_IMM8) & OP_MASK_IMM8);
999 break;
1000
1001 case '6':
1002 (*info->fprintf_func) (info->stream, "0x%lx",
1003 (l >> OP_SH_RS) & OP_MASK_RS);
1004 break;
1005
1006 case '7':
1007 (*info->fprintf_func) (info->stream, "$ac%ld",
1008 (l >> OP_SH_DSPACC) & OP_MASK_DSPACC);
1009 break;
1010
1011 case '8':
1012 (*info->fprintf_func) (info->stream, "0x%lx",
1013 (l >> OP_SH_WRDSP) & OP_MASK_WRDSP);
1014 break;
1015
1016 case '9':
1017 (*info->fprintf_func) (info->stream, "$ac%ld",
1018 (l >> OP_SH_DSPACC_S) & OP_MASK_DSPACC_S);
1019 break;
1020
1021 case '0': /* dsp 6-bit signed immediate in bit 20 */
1022 delta = ((l >> OP_SH_DSPSFT) & OP_MASK_DSPSFT);
1023 if (delta & 0x20) /* test sign bit */
1024 delta |= ~OP_MASK_DSPSFT;
1025 (*info->fprintf_func) (info->stream, "%d", delta);
1026 break;
1027
1028 case ':': /* dsp 7-bit signed immediate in bit 19 */
1029 delta = ((l >> OP_SH_DSPSFT_7) & OP_MASK_DSPSFT_7);
1030 if (delta & 0x40) /* test sign bit */
1031 delta |= ~OP_MASK_DSPSFT_7;
1032 (*info->fprintf_func) (info->stream, "%d", delta);
1033 break;
1034
1035 case '\'':
1036 (*info->fprintf_func) (info->stream, "0x%lx",
1037 (l >> OP_SH_RDDSP) & OP_MASK_RDDSP);
1038 break;
1039
1040 case '@': /* dsp 10-bit signed immediate in bit 16 */
1041 delta = ((l >> OP_SH_IMM10) & OP_MASK_IMM10);
1042 if (delta & 0x200) /* test sign bit */
1043 delta |= ~OP_MASK_IMM10;
1044 (*info->fprintf_func) (info->stream, "%d", delta);
1045 break;
1046
1047 case '!':
1048 (*info->fprintf_func) (info->stream, "%ld",
1049 (l >> OP_SH_MT_U) & OP_MASK_MT_U);
1050 break;
1051
1052 case '$':
1053 (*info->fprintf_func) (info->stream, "%ld",
1054 (l >> OP_SH_MT_H) & OP_MASK_MT_H);
1055 break;
1056
1057 case '*':
1058 (*info->fprintf_func) (info->stream, "$ac%ld",
1059 (l >> OP_SH_MTACC_T) & OP_MASK_MTACC_T);
1060 break;
1061
1062 case '&':
1063 (*info->fprintf_func) (info->stream, "$ac%ld",
1064 (l >> OP_SH_MTACC_D) & OP_MASK_MTACC_D);
1065 break;
1066
1067 case 'g':
1068 /* Coprocessor register for CTTC1, MTTC2, MTHC2, CTTC2. */
1069 (*info->fprintf_func) (info->stream, "$%ld",
1070 (l >> OP_SH_RD) & OP_MASK_RD);
1071 break;
1072
1073 case 's':
1074 case 'b':
1075 case 'r':
1076 case 'v':
1077 (*info->fprintf_func) (info->stream, "%s",
1078 mips_gpr_names[(l >> OP_SH_RS) & OP_MASK_RS]);
1079 break;
1080
1081 case 't':
1082 case 'w':
1083 (*info->fprintf_func) (info->stream, "%s",
1084 mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]);
1085 break;
1086
1087 case 'i':
1088 case 'u':
1089 (*info->fprintf_func) (info->stream, "0x%lx",
1090 (l >> OP_SH_IMMEDIATE) & OP_MASK_IMMEDIATE);
1091 break;
1092
1093 case 'j': /* Same as i, but sign-extended. */
1094 case 'o':
1095 delta = (l >> OP_SH_DELTA) & OP_MASK_DELTA;
1096 if (delta & 0x8000)
1097 delta |= ~0xffff;
1098 (*info->fprintf_func) (info->stream, "%d",
1099 delta);
1100 break;
1101
1102 case 'h':
1103 (*info->fprintf_func) (info->stream, "0x%x",
1104 (unsigned int) ((l >> OP_SH_PREFX)
1105 & OP_MASK_PREFX));
1106 break;
1107
1108 case 'k':
1109 (*info->fprintf_func) (info->stream, "0x%x",
1110 (unsigned int) ((l >> OP_SH_CACHE)
1111 & OP_MASK_CACHE));
1112 break;
1113
1114 case 'a':
1115 info->target = (((pc + 4) & ~(bfd_vma) 0x0fffffff)
1116 | (((l >> OP_SH_TARGET) & OP_MASK_TARGET) << 2));
1117 /* For gdb disassembler, force odd address on jalx. */
1118 if (info->flavour == bfd_target_unknown_flavour
1119 && strcmp (opp->name, "jalx") == 0)
1120 info->target |= 1;
1121 (*info->print_address_func) (info->target, info);
1122 break;
1123
1124 case 'p':
1125 /* Sign extend the displacement. */
1126 delta = (l >> OP_SH_DELTA) & OP_MASK_DELTA;
1127 if (delta & 0x8000)
1128 delta |= ~0xffff;
1129 info->target = (delta << 2) + pc + INSNLEN;
1130 (*info->print_address_func) (info->target, info);
1131 break;
1132
1133 case 'd':
1134 (*info->fprintf_func) (info->stream, "%s",
1135 mips_gpr_names[(l >> OP_SH_RD) & OP_MASK_RD]);
1136 break;
1137
1138 case 'U':
1139 {
1140 /* First check for both rd and rt being equal. */
1141 unsigned int reg = (l >> OP_SH_RD) & OP_MASK_RD;
1142 if (reg == ((l >> OP_SH_RT) & OP_MASK_RT))
1143 (*info->fprintf_func) (info->stream, "%s",
1144 mips_gpr_names[reg]);
1145 else
1146 {
1147 /* If one is zero use the other. */
1148 if (reg == 0)
1149 (*info->fprintf_func) (info->stream, "%s",
1150 mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]);
1151 else if (((l >> OP_SH_RT) & OP_MASK_RT) == 0)
1152 (*info->fprintf_func) (info->stream, "%s",
1153 mips_gpr_names[reg]);
1154 else /* Bogus, result depends on processor. */
1155 (*info->fprintf_func) (info->stream, "%s or %s",
1156 mips_gpr_names[reg],
1157 mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]);
1158 }
1159 }
1160 break;
1161
1162 case 'z':
1163 (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[0]);
1164 break;
1165
1166 case '<':
1167 case '1':
1168 (*info->fprintf_func) (info->stream, "0x%lx",
1169 (l >> OP_SH_SHAMT) & OP_MASK_SHAMT);
1170 break;
1171
1172 case 'c':
1173 (*info->fprintf_func) (info->stream, "0x%lx",
1174 (l >> OP_SH_CODE) & OP_MASK_CODE);
1175 break;
1176
1177 case 'q':
1178 (*info->fprintf_func) (info->stream, "0x%lx",
1179 (l >> OP_SH_CODE2) & OP_MASK_CODE2);
1180 break;
1181
1182 case 'C':
1183 (*info->fprintf_func) (info->stream, "0x%lx",
1184 (l >> OP_SH_COPZ) & OP_MASK_COPZ);
1185 break;
1186
1187 case 'B':
1188 (*info->fprintf_func) (info->stream, "0x%lx",
1189
1190 (l >> OP_SH_CODE20) & OP_MASK_CODE20);
1191 break;
1192
1193 case 'J':
1194 (*info->fprintf_func) (info->stream, "0x%lx",
1195 (l >> OP_SH_CODE19) & OP_MASK_CODE19);
1196 break;
1197
1198 case 'S':
1199 case 'V':
1200 (*info->fprintf_func) (info->stream, "%s",
1201 mips_fpr_names[(l >> OP_SH_FS) & OP_MASK_FS]);
1202 break;
1203
1204 case 'T':
1205 case 'W':
1206 (*info->fprintf_func) (info->stream, "%s",
1207 mips_fpr_names[(l >> OP_SH_FT) & OP_MASK_FT]);
1208 break;
1209
1210 case 'D':
1211 (*info->fprintf_func) (info->stream, "%s",
1212 mips_fpr_names[(l >> OP_SH_FD) & OP_MASK_FD]);
1213 break;
1214
1215 case 'R':
1216 (*info->fprintf_func) (info->stream, "%s",
1217 mips_fpr_names[(l >> OP_SH_FR) & OP_MASK_FR]);
1218 break;
1219
1220 case 'E':
1221 /* Coprocessor register for lwcN instructions, et al.
1222
1223 Note that there is no load/store cp0 instructions, and
1224 that FPU (cp1) instructions disassemble this field using
1225 'T' format. Therefore, until we gain understanding of
1226 cp2 register names, we can simply print the register
1227 numbers. */
1228 (*info->fprintf_func) (info->stream, "$%ld",
1229 (l >> OP_SH_RT) & OP_MASK_RT);
1230 break;
1231
1232 case 'G':
1233 /* Coprocessor register for mtcN instructions, et al. Note
1234 that FPU (cp1) instructions disassemble this field using
1235 'S' format. Therefore, we only need to worry about cp0,
1236 cp2, and cp3. */
1237 op = (l >> OP_SH_OP) & OP_MASK_OP;
1238 if (op == OP_OP_COP0)
1239 (*info->fprintf_func) (info->stream, "%s",
1240 mips_cp0_names[(l >> OP_SH_RD) & OP_MASK_RD]);
1241 else
1242 (*info->fprintf_func) (info->stream, "$%ld",
1243 (l >> OP_SH_RD) & OP_MASK_RD);
1244 break;
1245
1246 case 'K':
1247 (*info->fprintf_func) (info->stream, "%s",
1248 mips_hwr_names[(l >> OP_SH_RD) & OP_MASK_RD]);
1249 break;
1250
1251 case 'N':
1252 (*info->fprintf_func) (info->stream,
1253 ((opp->pinfo & (FP_D | FP_S)) != 0
1254 ? "$fcc%ld" : "$cc%ld"),
1255 (l >> OP_SH_BCC) & OP_MASK_BCC);
1256 break;
1257
1258 case 'M':
1259 (*info->fprintf_func) (info->stream, "$fcc%ld",
1260 (l >> OP_SH_CCC) & OP_MASK_CCC);
1261 break;
1262
1263 case 'P':
1264 (*info->fprintf_func) (info->stream, "%ld",
1265 (l >> OP_SH_PERFREG) & OP_MASK_PERFREG);
1266 break;
1267
1268 case 'e':
1269 (*info->fprintf_func) (info->stream, "%ld",
1270 (l >> OP_SH_VECBYTE) & OP_MASK_VECBYTE);
1271 break;
1272
1273 case '%':
1274 (*info->fprintf_func) (info->stream, "%ld",
1275 (l >> OP_SH_VECALIGN) & OP_MASK_VECALIGN);
1276 break;
1277
1278 case 'H':
1279 (*info->fprintf_func) (info->stream, "%ld",
1280 (l >> OP_SH_SEL) & OP_MASK_SEL);
1281 break;
1282
1283 case 'O':
1284 (*info->fprintf_func) (info->stream, "%ld",
1285 (l >> OP_SH_ALN) & OP_MASK_ALN);
1286 break;
1287
1288 case 'Q':
1289 {
1290 unsigned int vsel = (l >> OP_SH_VSEL) & OP_MASK_VSEL;
1291
1292 if ((vsel & 0x10) == 0)
1293 {
1294 int fmt;
1295
1296 vsel &= 0x0f;
1297 for (fmt = 0; fmt < 3; fmt++, vsel >>= 1)
1298 if ((vsel & 1) == 0)
1299 break;
1300 (*info->fprintf_func) (info->stream, "$v%ld[%d]",
1301 (l >> OP_SH_FT) & OP_MASK_FT,
1302 vsel >> 1);
1303 }
1304 else if ((vsel & 0x08) == 0)
1305 {
1306 (*info->fprintf_func) (info->stream, "$v%ld",
1307 (l >> OP_SH_FT) & OP_MASK_FT);
1308 }
1309 else
1310 {
1311 (*info->fprintf_func) (info->stream, "0x%lx",
1312 (l >> OP_SH_FT) & OP_MASK_FT);
1313 }
1314 }
1315 break;
1316
1317 case 'X':
1318 (*info->fprintf_func) (info->stream, "$v%ld",
1319 (l >> OP_SH_FD) & OP_MASK_FD);
1320 break;
1321
1322 case 'Y':
1323 (*info->fprintf_func) (info->stream, "$v%ld",
1324 (l >> OP_SH_FS) & OP_MASK_FS);
1325 break;
1326
1327 case 'Z':
1328 (*info->fprintf_func) (info->stream, "$v%ld",
1329 (l >> OP_SH_FT) & OP_MASK_FT);
1330 break;
1331
1332 default:
1333 /* xgettext:c-format */
1334 (*info->fprintf_func) (info->stream,
1335 _("# internal error, undefined modifier (%c)"),
1336 *d);
1337 return;
1338 }
1339 }
1340 }
1341 \f
1342 /* Print the mips instruction at address MEMADDR in debugged memory,
1343 on using INFO. Returns length of the instruction, in bytes, which is
1344 always INSNLEN. BIGENDIAN must be 1 if this is big-endian code, 0 if
1345 this is little-endian code. */
1346
1347 static int
1348 print_insn_mips (bfd_vma memaddr,
1349 unsigned long int word,
1350 struct disassemble_info *info)
1351 {
1352 const struct mips_opcode *op;
1353 static bfd_boolean init = 0;
1354 static const struct mips_opcode *mips_hash[OP_MASK_OP + 1];
1355
1356 /* Build a hash table to shorten the search time. */
1357 if (! init)
1358 {
1359 unsigned int i;
1360
1361 for (i = 0; i <= OP_MASK_OP; i++)
1362 {
1363 for (op = mips_opcodes; op < &mips_opcodes[NUMOPCODES]; op++)
1364 {
1365 if (op->pinfo == INSN_MACRO
1366 || (no_aliases && (op->pinfo2 & INSN2_ALIAS)))
1367 continue;
1368 if (i == ((op->match >> OP_SH_OP) & OP_MASK_OP))
1369 {
1370 mips_hash[i] = op;
1371 break;
1372 }
1373 }
1374 }
1375
1376 init = 1;
1377 }
1378
1379 info->bytes_per_chunk = INSNLEN;
1380 info->display_endian = info->endian;
1381 info->insn_info_valid = 1;
1382 info->branch_delay_insns = 0;
1383 info->data_size = 0;
1384 info->insn_type = dis_nonbranch;
1385 info->target = 0;
1386 info->target2 = 0;
1387
1388 op = mips_hash[(word >> OP_SH_OP) & OP_MASK_OP];
1389 if (op != NULL)
1390 {
1391 for (; op < &mips_opcodes[NUMOPCODES]; op++)
1392 {
1393 if (op->pinfo != INSN_MACRO
1394 && !(no_aliases && (op->pinfo2 & INSN2_ALIAS))
1395 && (word & op->mask) == op->match)
1396 {
1397 const char *d;
1398
1399 /* We always allow to disassemble the jalx instruction. */
1400 if (! OPCODE_IS_MEMBER (op, mips_isa, mips_processor)
1401 && strcmp (op->name, "jalx"))
1402 continue;
1403
1404 /* Figure out instruction type and branch delay information. */
1405 if ((op->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0)
1406 {
1407 if ((info->insn_type & INSN_WRITE_GPR_31) != 0)
1408 info->insn_type = dis_jsr;
1409 else
1410 info->insn_type = dis_branch;
1411 info->branch_delay_insns = 1;
1412 }
1413 else if ((op->pinfo & (INSN_COND_BRANCH_DELAY
1414 | INSN_COND_BRANCH_LIKELY)) != 0)
1415 {
1416 if ((info->insn_type & INSN_WRITE_GPR_31) != 0)
1417 info->insn_type = dis_condjsr;
1418 else
1419 info->insn_type = dis_condbranch;
1420 info->branch_delay_insns = 1;
1421 }
1422 else if ((op->pinfo & (INSN_STORE_MEMORY
1423 | INSN_LOAD_MEMORY_DELAY)) != 0)
1424 info->insn_type = dis_dref;
1425
1426 (*info->fprintf_func) (info->stream, "%s", op->name);
1427
1428 d = op->args;
1429 if (d != NULL && *d != '\0')
1430 {
1431 (*info->fprintf_func) (info->stream, "\t");
1432 print_insn_args (d, word, memaddr, info, op);
1433 }
1434
1435 return INSNLEN;
1436 }
1437 }
1438 }
1439
1440 /* Handle undefined instructions. */
1441 info->insn_type = dis_noninsn;
1442 (*info->fprintf_func) (info->stream, "0x%lx", word);
1443 return INSNLEN;
1444 }
1445 \f
1446 /* Disassemble an operand for a mips16 instruction. */
1447
1448 static void
1449 print_mips16_insn_arg (char type,
1450 const struct mips_opcode *op,
1451 int l,
1452 bfd_boolean use_extend,
1453 int extend,
1454 bfd_vma memaddr,
1455 struct disassemble_info *info)
1456 {
1457 switch (type)
1458 {
1459 case ',':
1460 case '(':
1461 case ')':
1462 (*info->fprintf_func) (info->stream, "%c", type);
1463 break;
1464
1465 case 'y':
1466 case 'w':
1467 (*info->fprintf_func) (info->stream, "%s",
1468 mips16_reg_names(((l >> MIPS16OP_SH_RY)
1469 & MIPS16OP_MASK_RY)));
1470 break;
1471
1472 case 'x':
1473 case 'v':
1474 (*info->fprintf_func) (info->stream, "%s",
1475 mips16_reg_names(((l >> MIPS16OP_SH_RX)
1476 & MIPS16OP_MASK_RX)));
1477 break;
1478
1479 case 'z':
1480 (*info->fprintf_func) (info->stream, "%s",
1481 mips16_reg_names(((l >> MIPS16OP_SH_RZ)
1482 & MIPS16OP_MASK_RZ)));
1483 break;
1484
1485 case 'Z':
1486 (*info->fprintf_func) (info->stream, "%s",
1487 mips16_reg_names(((l >> MIPS16OP_SH_MOVE32Z)
1488 & MIPS16OP_MASK_MOVE32Z)));
1489 break;
1490
1491 case '0':
1492 (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[0]);
1493 break;
1494
1495 case 'S':
1496 (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[29]);
1497 break;
1498
1499 case 'P':
1500 (*info->fprintf_func) (info->stream, "$pc");
1501 break;
1502
1503 case 'R':
1504 (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[31]);
1505 break;
1506
1507 case 'X':
1508 (*info->fprintf_func) (info->stream, "%s",
1509 mips_gpr_names[((l >> MIPS16OP_SH_REGR32)
1510 & MIPS16OP_MASK_REGR32)]);
1511 break;
1512
1513 case 'Y':
1514 (*info->fprintf_func) (info->stream, "%s",
1515 mips_gpr_names[MIPS16OP_EXTRACT_REG32R (l)]);
1516 break;
1517
1518 case '<':
1519 case '>':
1520 case '[':
1521 case ']':
1522 case '4':
1523 case '5':
1524 case 'H':
1525 case 'W':
1526 case 'D':
1527 case 'j':
1528 case '6':
1529 case '8':
1530 case 'V':
1531 case 'C':
1532 case 'U':
1533 case 'k':
1534 case 'K':
1535 case 'p':
1536 case 'q':
1537 case 'A':
1538 case 'B':
1539 case 'E':
1540 {
1541 int immed, nbits, shift, signedp, extbits, pcrel, extu, branch;
1542
1543 shift = 0;
1544 signedp = 0;
1545 extbits = 16;
1546 pcrel = 0;
1547 extu = 0;
1548 branch = 0;
1549 switch (type)
1550 {
1551 case '<':
1552 nbits = 3;
1553 immed = (l >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ;
1554 extbits = 5;
1555 extu = 1;
1556 break;
1557 case '>':
1558 nbits = 3;
1559 immed = (l >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX;
1560 extbits = 5;
1561 extu = 1;
1562 break;
1563 case '[':
1564 nbits = 3;
1565 immed = (l >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ;
1566 extbits = 6;
1567 extu = 1;
1568 break;
1569 case ']':
1570 nbits = 3;
1571 immed = (l >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX;
1572 extbits = 6;
1573 extu = 1;
1574 break;
1575 case '4':
1576 nbits = 4;
1577 immed = (l >> MIPS16OP_SH_IMM4) & MIPS16OP_MASK_IMM4;
1578 signedp = 1;
1579 extbits = 15;
1580 break;
1581 case '5':
1582 nbits = 5;
1583 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
1584 info->insn_type = dis_dref;
1585 info->data_size = 1;
1586 break;
1587 case 'H':
1588 nbits = 5;
1589 shift = 1;
1590 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
1591 info->insn_type = dis_dref;
1592 info->data_size = 2;
1593 break;
1594 case 'W':
1595 nbits = 5;
1596 shift = 2;
1597 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
1598 if ((op->pinfo & MIPS16_INSN_READ_PC) == 0
1599 && (op->pinfo & MIPS16_INSN_READ_SP) == 0)
1600 {
1601 info->insn_type = dis_dref;
1602 info->data_size = 4;
1603 }
1604 break;
1605 case 'D':
1606 nbits = 5;
1607 shift = 3;
1608 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
1609 info->insn_type = dis_dref;
1610 info->data_size = 8;
1611 break;
1612 case 'j':
1613 nbits = 5;
1614 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
1615 signedp = 1;
1616 break;
1617 case '6':
1618 nbits = 6;
1619 immed = (l >> MIPS16OP_SH_IMM6) & MIPS16OP_MASK_IMM6;
1620 break;
1621 case '8':
1622 nbits = 8;
1623 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
1624 break;
1625 case 'V':
1626 nbits = 8;
1627 shift = 2;
1628 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
1629 /* FIXME: This might be lw, or it might be addiu to $sp or
1630 $pc. We assume it's load. */
1631 info->insn_type = dis_dref;
1632 info->data_size = 4;
1633 break;
1634 case 'C':
1635 nbits = 8;
1636 shift = 3;
1637 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
1638 info->insn_type = dis_dref;
1639 info->data_size = 8;
1640 break;
1641 case 'U':
1642 nbits = 8;
1643 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
1644 extu = 1;
1645 break;
1646 case 'k':
1647 nbits = 8;
1648 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
1649 signedp = 1;
1650 break;
1651 case 'K':
1652 nbits = 8;
1653 shift = 3;
1654 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
1655 signedp = 1;
1656 break;
1657 case 'p':
1658 nbits = 8;
1659 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
1660 signedp = 1;
1661 pcrel = 1;
1662 branch = 1;
1663 info->insn_type = dis_condbranch;
1664 break;
1665 case 'q':
1666 nbits = 11;
1667 immed = (l >> MIPS16OP_SH_IMM11) & MIPS16OP_MASK_IMM11;
1668 signedp = 1;
1669 pcrel = 1;
1670 branch = 1;
1671 info->insn_type = dis_branch;
1672 break;
1673 case 'A':
1674 nbits = 8;
1675 shift = 2;
1676 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
1677 pcrel = 1;
1678 /* FIXME: This can be lw or la. We assume it is lw. */
1679 info->insn_type = dis_dref;
1680 info->data_size = 4;
1681 break;
1682 case 'B':
1683 nbits = 5;
1684 shift = 3;
1685 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
1686 pcrel = 1;
1687 info->insn_type = dis_dref;
1688 info->data_size = 8;
1689 break;
1690 case 'E':
1691 nbits = 5;
1692 shift = 2;
1693 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
1694 pcrel = 1;
1695 break;
1696 default:
1697 abort ();
1698 }
1699
1700 if (! use_extend)
1701 {
1702 if (signedp && immed >= (1 << (nbits - 1)))
1703 immed -= 1 << nbits;
1704 immed <<= shift;
1705 if ((type == '<' || type == '>' || type == '[' || type == ']')
1706 && immed == 0)
1707 immed = 8;
1708 }
1709 else
1710 {
1711 if (extbits == 16)
1712 immed |= ((extend & 0x1f) << 11) | (extend & 0x7e0);
1713 else if (extbits == 15)
1714 immed |= ((extend & 0xf) << 11) | (extend & 0x7f0);
1715 else
1716 immed = ((extend >> 6) & 0x1f) | (extend & 0x20);
1717 immed &= (1 << extbits) - 1;
1718 if (! extu && immed >= (1 << (extbits - 1)))
1719 immed -= 1 << extbits;
1720 }
1721
1722 if (! pcrel)
1723 (*info->fprintf_func) (info->stream, "%d", immed);
1724 else
1725 {
1726 bfd_vma baseaddr;
1727
1728 if (branch)
1729 {
1730 immed *= 2;
1731 baseaddr = memaddr + 2;
1732 }
1733 else if (use_extend)
1734 baseaddr = memaddr - 2;
1735 else
1736 {
1737 int status;
1738 bfd_byte buffer[2];
1739
1740 baseaddr = memaddr;
1741
1742 /* If this instruction is in the delay slot of a jr
1743 instruction, the base address is the address of the
1744 jr instruction. If it is in the delay slot of jalr
1745 instruction, the base address is the address of the
1746 jalr instruction. This test is unreliable: we have
1747 no way of knowing whether the previous word is
1748 instruction or data. */
1749 status = (*info->read_memory_func) (memaddr - 4, buffer, 2,
1750 info);
1751 if (status == 0
1752 && (((info->endian == BFD_ENDIAN_BIG
1753 ? bfd_getb16 (buffer)
1754 : bfd_getl16 (buffer))
1755 & 0xf800) == 0x1800))
1756 baseaddr = memaddr - 4;
1757 else
1758 {
1759 status = (*info->read_memory_func) (memaddr - 2, buffer,
1760 2, info);
1761 if (status == 0
1762 && (((info->endian == BFD_ENDIAN_BIG
1763 ? bfd_getb16 (buffer)
1764 : bfd_getl16 (buffer))
1765 & 0xf81f) == 0xe800))
1766 baseaddr = memaddr - 2;
1767 }
1768 }
1769 info->target = (baseaddr & ~((1 << shift) - 1)) + immed;
1770 if (pcrel && branch
1771 && info->flavour == bfd_target_unknown_flavour)
1772 /* For gdb disassembler, maintain odd address. */
1773 info->target |= 1;
1774 (*info->print_address_func) (info->target, info);
1775 }
1776 }
1777 break;
1778
1779 case 'a':
1780 {
1781 int jalx = l & 0x400;
1782
1783 if (! use_extend)
1784 extend = 0;
1785 l = ((l & 0x1f) << 23) | ((l & 0x3e0) << 13) | (extend << 2);
1786 if (!jalx && info->flavour == bfd_target_unknown_flavour)
1787 /* For gdb disassembler, maintain odd address. */
1788 l |= 1;
1789 }
1790 info->target = ((memaddr + 4) & ~(bfd_vma) 0x0fffffff) | l;
1791 (*info->print_address_func) (info->target, info);
1792 info->insn_type = dis_jsr;
1793 info->branch_delay_insns = 1;
1794 break;
1795
1796 case 'l':
1797 case 'L':
1798 {
1799 int need_comma, amask, smask;
1800
1801 need_comma = 0;
1802
1803 l = (l >> MIPS16OP_SH_IMM6) & MIPS16OP_MASK_IMM6;
1804
1805 amask = (l >> 3) & 7;
1806
1807 if (amask > 0 && amask < 5)
1808 {
1809 (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[4]);
1810 if (amask > 1)
1811 (*info->fprintf_func) (info->stream, "-%s",
1812 mips_gpr_names[amask + 3]);
1813 need_comma = 1;
1814 }
1815
1816 smask = (l >> 1) & 3;
1817 if (smask == 3)
1818 {
1819 (*info->fprintf_func) (info->stream, "%s??",
1820 need_comma ? "," : "");
1821 need_comma = 1;
1822 }
1823 else if (smask > 0)
1824 {
1825 (*info->fprintf_func) (info->stream, "%s%s",
1826 need_comma ? "," : "",
1827 mips_gpr_names[16]);
1828 if (smask > 1)
1829 (*info->fprintf_func) (info->stream, "-%s",
1830 mips_gpr_names[smask + 15]);
1831 need_comma = 1;
1832 }
1833
1834 if (l & 1)
1835 {
1836 (*info->fprintf_func) (info->stream, "%s%s",
1837 need_comma ? "," : "",
1838 mips_gpr_names[31]);
1839 need_comma = 1;
1840 }
1841
1842 if (amask == 5 || amask == 6)
1843 {
1844 (*info->fprintf_func) (info->stream, "%s$f0",
1845 need_comma ? "," : "");
1846 if (amask == 6)
1847 (*info->fprintf_func) (info->stream, "-$f1");
1848 }
1849 }
1850 break;
1851
1852 case 'm':
1853 case 'M':
1854 /* MIPS16e save/restore. */
1855 {
1856 int need_comma = 0;
1857 int amask, args, statics;
1858 int nsreg, smask;
1859 int framesz;
1860 int i, j;
1861
1862 l = l & 0x7f;
1863 if (use_extend)
1864 l |= extend << 16;
1865
1866 amask = (l >> 16) & 0xf;
1867 if (amask == MIPS16_ALL_ARGS)
1868 {
1869 args = 4;
1870 statics = 0;
1871 }
1872 else if (amask == MIPS16_ALL_STATICS)
1873 {
1874 args = 0;
1875 statics = 4;
1876 }
1877 else
1878 {
1879 args = amask >> 2;
1880 statics = amask & 3;
1881 }
1882
1883 if (args > 0) {
1884 (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[4]);
1885 if (args > 1)
1886 (*info->fprintf_func) (info->stream, "-%s",
1887 mips_gpr_names[4 + args - 1]);
1888 need_comma = 1;
1889 }
1890
1891 framesz = (((l >> 16) & 0xf0) | (l & 0x0f)) * 8;
1892 if (framesz == 0 && !use_extend)
1893 framesz = 128;
1894
1895 (*info->fprintf_func) (info->stream, "%s%d",
1896 need_comma ? "," : "",
1897 framesz);
1898
1899 if (l & 0x40) /* $ra */
1900 (*info->fprintf_func) (info->stream, ",%s", mips_gpr_names[31]);
1901
1902 nsreg = (l >> 24) & 0x7;
1903 smask = 0;
1904 if (l & 0x20) /* $s0 */
1905 smask |= 1 << 0;
1906 if (l & 0x10) /* $s1 */
1907 smask |= 1 << 1;
1908 if (nsreg > 0) /* $s2-$s8 */
1909 smask |= ((1 << nsreg) - 1) << 2;
1910
1911 /* Find first set static reg bit. */
1912 for (i = 0; i < 9; i++)
1913 {
1914 if (smask & (1 << i))
1915 {
1916 (*info->fprintf_func) (info->stream, ",%s",
1917 mips_gpr_names[i == 8 ? 30 : (16 + i)]);
1918 /* Skip over string of set bits. */
1919 for (j = i; smask & (2 << j); j++)
1920 continue;
1921 if (j > i)
1922 (*info->fprintf_func) (info->stream, "-%s",
1923 mips_gpr_names[j == 8 ? 30 : (16 + j)]);
1924 i = j + 1;
1925 }
1926 }
1927
1928 /* Statics $ax - $a3. */
1929 if (statics == 1)
1930 (*info->fprintf_func) (info->stream, ",%s", mips_gpr_names[7]);
1931 else if (statics > 0)
1932 (*info->fprintf_func) (info->stream, ",%s-%s",
1933 mips_gpr_names[7 - statics + 1],
1934 mips_gpr_names[7]);
1935 }
1936 break;
1937
1938 default:
1939 /* xgettext:c-format */
1940 (*info->fprintf_func)
1941 (info->stream,
1942 _("# internal disassembler error, unrecognised modifier (%c)"),
1943 type);
1944 abort ();
1945 }
1946 }
1947
1948 /* Disassemble mips16 instructions. */
1949
1950 static int
1951 print_insn_mips16 (bfd_vma memaddr, struct disassemble_info *info)
1952 {
1953 int status;
1954 bfd_byte buffer[2];
1955 int length;
1956 int insn;
1957 bfd_boolean use_extend;
1958 int extend = 0;
1959 const struct mips_opcode *op, *opend;
1960
1961 info->bytes_per_chunk = 2;
1962 info->display_endian = info->endian;
1963 info->insn_info_valid = 1;
1964 info->branch_delay_insns = 0;
1965 info->data_size = 0;
1966 info->insn_type = dis_nonbranch;
1967 info->target = 0;
1968 info->target2 = 0;
1969
1970 status = (*info->read_memory_func) (memaddr, buffer, 2, info);
1971 if (status != 0)
1972 {
1973 (*info->memory_error_func) (status, memaddr, info);
1974 return -1;
1975 }
1976
1977 length = 2;
1978
1979 if (info->endian == BFD_ENDIAN_BIG)
1980 insn = bfd_getb16 (buffer);
1981 else
1982 insn = bfd_getl16 (buffer);
1983
1984 /* Handle the extend opcode specially. */
1985 use_extend = FALSE;
1986 if ((insn & 0xf800) == 0xf000)
1987 {
1988 use_extend = TRUE;
1989 extend = insn & 0x7ff;
1990
1991 memaddr += 2;
1992
1993 status = (*info->read_memory_func) (memaddr, buffer, 2, info);
1994 if (status != 0)
1995 {
1996 (*info->fprintf_func) (info->stream, "extend 0x%x",
1997 (unsigned int) extend);
1998 (*info->memory_error_func) (status, memaddr, info);
1999 return -1;
2000 }
2001
2002 if (info->endian == BFD_ENDIAN_BIG)
2003 insn = bfd_getb16 (buffer);
2004 else
2005 insn = bfd_getl16 (buffer);
2006
2007 /* Check for an extend opcode followed by an extend opcode. */
2008 if ((insn & 0xf800) == 0xf000)
2009 {
2010 (*info->fprintf_func) (info->stream, "extend 0x%x",
2011 (unsigned int) extend);
2012 info->insn_type = dis_noninsn;
2013 return length;
2014 }
2015
2016 length += 2;
2017 }
2018
2019 /* FIXME: Should probably use a hash table on the major opcode here. */
2020
2021 opend = mips16_opcodes + bfd_mips16_num_opcodes;
2022 for (op = mips16_opcodes; op < opend; op++)
2023 {
2024 if (op->pinfo != INSN_MACRO
2025 && !(no_aliases && (op->pinfo2 & INSN2_ALIAS))
2026 && (insn & op->mask) == op->match)
2027 {
2028 const char *s;
2029
2030 if (strchr (op->args, 'a') != NULL)
2031 {
2032 if (use_extend)
2033 {
2034 (*info->fprintf_func) (info->stream, "extend 0x%x",
2035 (unsigned int) extend);
2036 info->insn_type = dis_noninsn;
2037 return length - 2;
2038 }
2039
2040 use_extend = FALSE;
2041
2042 memaddr += 2;
2043
2044 status = (*info->read_memory_func) (memaddr, buffer, 2,
2045 info);
2046 if (status == 0)
2047 {
2048 use_extend = TRUE;
2049 if (info->endian == BFD_ENDIAN_BIG)
2050 extend = bfd_getb16 (buffer);
2051 else
2052 extend = bfd_getl16 (buffer);
2053 length += 2;
2054 }
2055 }
2056
2057 (*info->fprintf_func) (info->stream, "%s", op->name);
2058 if (op->args[0] != '\0')
2059 (*info->fprintf_func) (info->stream, "\t");
2060
2061 for (s = op->args; *s != '\0'; s++)
2062 {
2063 if (*s == ','
2064 && s[1] == 'w'
2065 && (((insn >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX)
2066 == ((insn >> MIPS16OP_SH_RY) & MIPS16OP_MASK_RY)))
2067 {
2068 /* Skip the register and the comma. */
2069 ++s;
2070 continue;
2071 }
2072 if (*s == ','
2073 && s[1] == 'v'
2074 && (((insn >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ)
2075 == ((insn >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX)))
2076 {
2077 /* Skip the register and the comma. */
2078 ++s;
2079 continue;
2080 }
2081 print_mips16_insn_arg (*s, op, insn, use_extend, extend, memaddr,
2082 info);
2083 }
2084
2085 if ((op->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0)
2086 {
2087 info->branch_delay_insns = 1;
2088 if (info->insn_type != dis_jsr)
2089 info->insn_type = dis_branch;
2090 }
2091
2092 return length;
2093 }
2094 }
2095
2096 if (use_extend)
2097 (*info->fprintf_func) (info->stream, "0x%x", extend | 0xf000);
2098 (*info->fprintf_func) (info->stream, "0x%x", insn);
2099 info->insn_type = dis_noninsn;
2100
2101 return length;
2102 }
2103
2104 /* In an environment where we do not know the symbol type of the
2105 instruction we are forced to assume that the low order bit of the
2106 instructions' address may mark it as a mips16 instruction. If we
2107 are single stepping, or the pc is within the disassembled function,
2108 this works. Otherwise, we need a clue. Sometimes. */
2109
2110 static int
2111 _print_insn_mips (bfd_vma memaddr,
2112 struct disassemble_info *info,
2113 enum bfd_endian endianness)
2114 {
2115 bfd_byte buffer[INSNLEN];
2116 int status;
2117
2118 set_default_mips_dis_options (info);
2119 parse_mips_dis_options (info->disassembler_options);
2120
2121 #if 1
2122 /* FIXME: If odd address, this is CLEARLY a mips 16 instruction. */
2123 /* Only a few tools will work this way. */
2124 if (memaddr & 0x01)
2125 return print_insn_mips16 (memaddr, info);
2126 #endif
2127
2128 #if SYMTAB_AVAILABLE
2129 if (info->mach == bfd_mach_mips16
2130 || (info->symbols != NULL
2131 && bfd_asymbol_flavour (*info->symbols) == bfd_target_elf_flavour
2132 && ELF_ST_IS_MIPS16 ((*(elf_symbol_type **) info->symbols)
2133 ->internal_elf_sym.st_other)))
2134 return print_insn_mips16 (memaddr, info);
2135 #endif
2136
2137 status = (*info->read_memory_func) (memaddr, buffer, INSNLEN, info);
2138 if (status == 0)
2139 {
2140 unsigned long insn;
2141
2142 if (endianness == BFD_ENDIAN_BIG)
2143 insn = (unsigned long) bfd_getb32 (buffer);
2144 else
2145 insn = (unsigned long) bfd_getl32 (buffer);
2146
2147 return print_insn_mips (memaddr, insn, info);
2148 }
2149 else
2150 {
2151 (*info->memory_error_func) (status, memaddr, info);
2152 return -1;
2153 }
2154 }
2155
2156 int
2157 print_insn_big_mips (bfd_vma memaddr, struct disassemble_info *info)
2158 {
2159 return _print_insn_mips (memaddr, info, BFD_ENDIAN_BIG);
2160 }
2161
2162 int
2163 print_insn_little_mips (bfd_vma memaddr, struct disassemble_info *info)
2164 {
2165 return _print_insn_mips (memaddr, info, BFD_ENDIAN_LITTLE);
2166 }
2167 \f
2168 void
2169 print_mips_disassembler_options (FILE *stream)
2170 {
2171 unsigned int i;
2172
2173 fprintf (stream, _("\n\
2174 The following MIPS specific disassembler options are supported for use\n\
2175 with the -M switch (multiple options should be separated by commas):\n"));
2176
2177 fprintf (stream, _("\n\
2178 gpr-names=ABI Print GPR names according to specified ABI.\n\
2179 Default: based on binary being disassembled.\n"));
2180
2181 fprintf (stream, _("\n\
2182 fpr-names=ABI Print FPR names according to specified ABI.\n\
2183 Default: numeric.\n"));
2184
2185 fprintf (stream, _("\n\
2186 cp0-names=ARCH Print CP0 register names according to\n\
2187 specified architecture.\n\
2188 Default: based on binary being disassembled.\n"));
2189
2190 fprintf (stream, _("\n\
2191 hwr-names=ARCH Print HWR names according to specified \n\
2192 architecture.\n\
2193 Default: based on binary being disassembled.\n"));
2194
2195 fprintf (stream, _("\n\
2196 reg-names=ABI Print GPR and FPR names according to\n\
2197 specified ABI.\n"));
2198
2199 fprintf (stream, _("\n\
2200 reg-names=ARCH Print CP0 register and HWR names according to\n\
2201 specified architecture.\n"));
2202
2203 fprintf (stream, _("\n\
2204 For the options above, the following values are supported for \"ABI\":\n\
2205 "));
2206 for (i = 0; i < ARRAY_SIZE (mips_abi_choices); i++)
2207 fprintf (stream, " %s", mips_abi_choices[i].name);
2208 fprintf (stream, _("\n"));
2209
2210 fprintf (stream, _("\n\
2211 For the options above, The following values are supported for \"ARCH\":\n\
2212 "));
2213 for (i = 0; i < ARRAY_SIZE (mips_arch_choices); i++)
2214 if (*mips_arch_choices[i].name != '\0')
2215 fprintf (stream, " %s", mips_arch_choices[i].name);
2216 fprintf (stream, _("\n"));
2217
2218 fprintf (stream, _("\n"));
2219 }
Patches to binutils for mingw-w64