opcodes/fr30-desc.h

   1 /* CPU data header for fr30.
   2
   3 THIS FILE IS MACHINE GENERATED WITH CGEN.
   4
   5 Copyright 1996-2010 Free Software Foundation, Inc.
   6
   7 This file is part of the GNU Binutils and/or GDB, the GNU debugger.
   8
   9    This file is free software; you can redistribute it and/or modify
  10    it under the terms of the GNU General Public License as published by
  11    the Free Software Foundation; either version 3, or (at your option)
  12    any later version.
  13
  14    It is distributed in the hope that it will be useful, but WITHOUT
  15    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  16    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  17    License for more details.
  18
  19    You should have received a copy of the GNU General Public License along
  20    with this program; if not, write to the Free Software Foundation, Inc.,
  21    51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
  22
  23 */
  24
  25 #ifndef FR30_CPU_H
  26 #define FR30_CPU_H
  27
  28 #define CGEN_ARCH fr30
  29
  30 /* Given symbol S, return fr30_cgen_<S>.  */
  31 #define CGEN_SYM(s) fr30##_cgen_##s
  32
  33
  34 /* Selected cpu families.  */
  35 #define HAVE_CPU_FR30BF
  36
  37 #define CGEN_INSN_LSB0_P 0
  38
  39 /* Minimum size of any insn (in bytes).  */
  40 #define CGEN_MIN_INSN_SIZE 2
  41
  42 /* Maximum size of any insn (in bytes).  */
  43 #define CGEN_MAX_INSN_SIZE 6
  44
  45 #define CGEN_INT_INSN_P 0
  46
  47 /* Maximum number of syntax elements in an instruction.  */
  48 #define CGEN_ACTUAL_MAX_SYNTAX_ELEMENTS 15
  49
  50 /* CGEN_MNEMONIC_OPERANDS is defined if mnemonics have operands.
  51    e.g. In "b,a foo" the ",a" is an operand.  If mnemonics have operands
  52    we can't hash on everything up to the space.  */
  53 #define CGEN_MNEMONIC_OPERANDS
  54
  55 /* Maximum number of fields in an instruction.  */
  56 #define CGEN_ACTUAL_MAX_IFMT_OPERANDS 7
  57
  58 /* Enums.  */
  59
  60 /* Enum declaration for insn op1 enums.  */
  61 typedef enum insn_op1 {
  62   OP1_0, OP1_1, OP1_2, OP1_3
  63  , OP1_4, OP1_5, OP1_6, OP1_7
  64  , OP1_8, OP1_9, OP1_A, OP1_B
  65  , OP1_C, OP1_D, OP1_E, OP1_F
  66 } INSN_OP1;
  67
  68 /* Enum declaration for insn op2 enums.  */
  69 typedef enum insn_op2 {
  70   OP2_0, OP2_1, OP2_2, OP2_3
  71  , OP2_4, OP2_5, OP2_6, OP2_7
  72  , OP2_8, OP2_9, OP2_A, OP2_B
  73  , OP2_C, OP2_D, OP2_E, OP2_F
  74 } INSN_OP2;
  75
  76 /* Enum declaration for insn op3 enums.  */
  77 typedef enum insn_op3 {
  78   OP3_0, OP3_1, OP3_2, OP3_3
  79  , OP3_4, OP3_5, OP3_6, OP3_7
  80  , OP3_8, OP3_9, OP3_A, OP3_B
  81  , OP3_C, OP3_D, OP3_E, OP3_F
  82 } INSN_OP3;
  83
  84 /* Enum declaration for insn op4 enums.  */
  85 typedef enum insn_op4 {
  86   OP4_0
  87 } INSN_OP4;
  88
  89 /* Enum declaration for insn op5 enums.  */
  90 typedef enum insn_op5 {
  91   OP5_0, OP5_1
  92 } INSN_OP5;
  93
  94 /* Enum declaration for insn cc enums.  */
  95 typedef enum insn_cc {
  96   CC_RA, CC_NO, CC_EQ, CC_NE
  97  , CC_C, CC_NC, CC_N, CC_P
  98  , CC_V, CC_NV, CC_LT, CC_GE
  99  , CC_LE, CC_GT, CC_LS, CC_HI
 100 } INSN_CC;
 101
 102 /* Enum declaration for .  */
 103 typedef enum gr_names {
 104   H_GR_R0 = 0, H_GR_R1 = 1, H_GR_R2 = 2, H_GR_R3 = 3
 105  , H_GR_R4 = 4, H_GR_R5 = 5, H_GR_R6 = 6, H_GR_R7 = 7
 106  , H_GR_R8 = 8, H_GR_R9 = 9, H_GR_R10 = 10, H_GR_R11 = 11
 107  , H_GR_R12 = 12, H_GR_R13 = 13, H_GR_R14 = 14, H_GR_R15 = 15
 108  , H_GR_AC = 13, H_GR_FP = 14, H_GR_SP = 15
 109 } GR_NAMES;
 110
 111 /* Enum declaration for .  */
 112 typedef enum cr_names {
 113   H_CR_CR0, H_CR_CR1, H_CR_CR2, H_CR_CR3
 114  , H_CR_CR4, H_CR_CR5, H_CR_CR6, H_CR_CR7
 115  , H_CR_CR8, H_CR_CR9, H_CR_CR10, H_CR_CR11
 116  , H_CR_CR12, H_CR_CR13, H_CR_CR14, H_CR_CR15
 117 } CR_NAMES;
 118
 119 /* Enum declaration for .  */
 120 typedef enum dr_names {
 121   H_DR_TBR, H_DR_RP, H_DR_SSP, H_DR_USP
 122  , H_DR_MDH, H_DR_MDL
 123 } DR_NAMES;
 124
 125 /* Attributes.  */
 126
 127 /* Enum declaration for machine type selection.  */
 128 typedef enum mach_attr {
 129   MACH_BASE, MACH_FR30, MACH_MAX
 130 } MACH_ATTR;
 131
 132 /* Enum declaration for instruction set selection.  */
 133 typedef enum isa_attr {
 134   ISA_FR30, ISA_MAX
 135 } ISA_ATTR;
 136
 137 /* Number of architecture variants.  */
 138 #define MAX_ISAS  1
 139 #define MAX_MACHS ((int) MACH_MAX)
 140
 141 /* Ifield support.  */
 142
 143 /* Ifield attribute indices.  */
 144
 145 /* Enum declaration for cgen_ifld attrs.  */
 146 typedef enum cgen_ifld_attr {
 147   CGEN_IFLD_VIRTUAL, CGEN_IFLD_PCREL_ADDR, CGEN_IFLD_ABS_ADDR, CGEN_IFLD_RESERVED
 148  , CGEN_IFLD_SIGN_OPT, CGEN_IFLD_SIGNED, CGEN_IFLD_END_BOOLS, CGEN_IFLD_START_NBOOLS = 31
 149  , CGEN_IFLD_MACH, CGEN_IFLD_END_NBOOLS
 150 } CGEN_IFLD_ATTR;
 151
 152 /* Number of non-boolean elements in cgen_ifld_attr.  */
 153 #define CGEN_IFLD_NBOOL_ATTRS (CGEN_IFLD_END_NBOOLS - CGEN_IFLD_START_NBOOLS - 1)
 154
 155 /* cgen_ifld attribute accessor macros.  */
 156 #define CGEN_ATTR_CGEN_IFLD_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_IFLD_MACH-CGEN_IFLD_START_NBOOLS-1].nonbitset)
 157 #define CGEN_ATTR_CGEN_IFLD_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_VIRTUAL)) != 0)
 158 #define CGEN_ATTR_CGEN_IFLD_PCREL_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_PCREL_ADDR)) != 0)
 159 #define CGEN_ATTR_CGEN_IFLD_ABS_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_ABS_ADDR)) != 0)
 160 #define CGEN_ATTR_CGEN_IFLD_RESERVED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_RESERVED)) != 0)
 161 #define CGEN_ATTR_CGEN_IFLD_SIGN_OPT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_SIGN_OPT)) != 0)
 162 #define CGEN_ATTR_CGEN_IFLD_SIGNED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_SIGNED)) != 0)
 163
 164 /* Enum declaration for fr30 ifield types.  */
 165 typedef enum ifield_type {
 166   FR30_F_NIL, FR30_F_ANYOF, FR30_F_OP1, FR30_F_OP2
 167  , FR30_F_OP3, FR30_F_OP4, FR30_F_OP5, FR30_F_CC
 168  , FR30_F_CCC, FR30_F_RJ, FR30_F_RI, FR30_F_RS1
 169  , FR30_F_RS2, FR30_F_RJC, FR30_F_RIC, FR30_F_CRJ
 170  , FR30_F_CRI, FR30_F_U4, FR30_F_U4C, FR30_F_I4
 171  , FR30_F_M4, FR30_F_U8, FR30_F_I8, FR30_F_I20_4
 172  , FR30_F_I20_16, FR30_F_I20, FR30_F_I32, FR30_F_UDISP6
 173  , FR30_F_DISP8, FR30_F_DISP9, FR30_F_DISP10, FR30_F_S10
 174  , FR30_F_U10, FR30_F_REL9, FR30_F_DIR8, FR30_F_DIR9
 175  , FR30_F_DIR10, FR30_F_REL12, FR30_F_REGLIST_HI_ST, FR30_F_REGLIST_LOW_ST
 176  , FR30_F_REGLIST_HI_LD, FR30_F_REGLIST_LOW_LD, FR30_F_MAX
 177 } IFIELD_TYPE;
 178
 179 #define MAX_IFLD ((int) FR30_F_MAX)
 180
 181 /* Hardware attribute indices.  */
 182
 183 /* Enum declaration for cgen_hw attrs.  */
 184 typedef enum cgen_hw_attr {
 185   CGEN_HW_VIRTUAL, CGEN_HW_CACHE_ADDR, CGEN_HW_PC, CGEN_HW_PROFILE
 186  , CGEN_HW_END_BOOLS, CGEN_HW_START_NBOOLS = 31, CGEN_HW_MACH, CGEN_HW_END_NBOOLS
 187 } CGEN_HW_ATTR;
 188
 189 /* Number of non-boolean elements in cgen_hw_attr.  */
 190 #define CGEN_HW_NBOOL_ATTRS (CGEN_HW_END_NBOOLS - CGEN_HW_START_NBOOLS - 1)
 191
 192 /* cgen_hw attribute accessor macros.  */
 193 #define CGEN_ATTR_CGEN_HW_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_HW_MACH-CGEN_HW_START_NBOOLS-1].nonbitset)
 194 #define CGEN_ATTR_CGEN_HW_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_VIRTUAL)) != 0)
 195 #define CGEN_ATTR_CGEN_HW_CACHE_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_CACHE_ADDR)) != 0)
 196 #define CGEN_ATTR_CGEN_HW_PC_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_PC)) != 0)
 197 #define CGEN_ATTR_CGEN_HW_PROFILE_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_PROFILE)) != 0)
 198
 199 /* Enum declaration for fr30 hardware types.  */
 200 typedef enum cgen_hw_type {
 201   HW_H_MEMORY, HW_H_SINT, HW_H_UINT, HW_H_ADDR
 202  , HW_H_IADDR, HW_H_PC, HW_H_GR, HW_H_CR
 203  , HW_H_DR, HW_H_PS, HW_H_R13, HW_H_R14
 204  , HW_H_R15, HW_H_NBIT, HW_H_ZBIT, HW_H_VBIT
 205  , HW_H_CBIT, HW_H_IBIT, HW_H_SBIT, HW_H_TBIT
 206  , HW_H_D0BIT, HW_H_D1BIT, HW_H_CCR, HW_H_SCR
 207  , HW_H_ILM, HW_MAX
 208 } CGEN_HW_TYPE;
 209
 210 #define MAX_HW ((int) HW_MAX)
 211
 212 /* Operand attribute indices.  */
 213
 214 /* Enum declaration for cgen_operand attrs.  */
 215 typedef enum cgen_operand_attr {
 216   CGEN_OPERAND_VIRTUAL, CGEN_OPERAND_PCREL_ADDR, CGEN_OPERAND_ABS_ADDR, CGEN_OPERAND_SIGN_OPT
 217  , CGEN_OPERAND_SIGNED, CGEN_OPERAND_NEGATIVE, CGEN_OPERAND_RELAX, CGEN_OPERAND_SEM_ONLY
 218  , CGEN_OPERAND_HASH_PREFIX, CGEN_OPERAND_END_BOOLS, CGEN_OPERAND_START_NBOOLS = 31, CGEN_OPERAND_MACH
 219  , CGEN_OPERAND_END_NBOOLS
 220 } CGEN_OPERAND_ATTR;
 221
 222 /* Number of non-boolean elements in cgen_operand_attr.  */
 223 #define CGEN_OPERAND_NBOOL_ATTRS (CGEN_OPERAND_END_NBOOLS - CGEN_OPERAND_START_NBOOLS - 1)
 224
 225 /* cgen_operand attribute accessor macros.  */
 226 #define CGEN_ATTR_CGEN_OPERAND_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_OPERAND_MACH-CGEN_OPERAND_START_NBOOLS-1].nonbitset)
 227 #define CGEN_ATTR_CGEN_OPERAND_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_VIRTUAL)) != 0)
 228 #define CGEN_ATTR_CGEN_OPERAND_PCREL_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_PCREL_ADDR)) != 0)
 229 #define CGEN_ATTR_CGEN_OPERAND_ABS_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_ABS_ADDR)) != 0)
 230 #define CGEN_ATTR_CGEN_OPERAND_SIGN_OPT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_SIGN_OPT)) != 0)
 231 #define CGEN_ATTR_CGEN_OPERAND_SIGNED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_SIGNED)) != 0)
 232 #define CGEN_ATTR_CGEN_OPERAND_NEGATIVE_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_NEGATIVE)) != 0)
 233 #define CGEN_ATTR_CGEN_OPERAND_RELAX_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_RELAX)) != 0)
 234 #define CGEN_ATTR_CGEN_OPERAND_SEM_ONLY_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_SEM_ONLY)) != 0)
 235 #define CGEN_ATTR_CGEN_OPERAND_HASH_PREFIX_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_HASH_PREFIX)) != 0)
 236
 237 /* Enum declaration for fr30 operand types.  */
 238 typedef enum cgen_operand_type {
 239   FR30_OPERAND_PC, FR30_OPERAND_RI, FR30_OPERAND_RJ, FR30_OPERAND_RIC
 240  , FR30_OPERAND_RJC, FR30_OPERAND_CRI, FR30_OPERAND_CRJ, FR30_OPERAND_RS1
 241  , FR30_OPERAND_RS2, FR30_OPERAND_R13, FR30_OPERAND_R14, FR30_OPERAND_R15
 242  , FR30_OPERAND_PS, FR30_OPERAND_U4, FR30_OPERAND_U4C, FR30_OPERAND_U8
 243  , FR30_OPERAND_I8, FR30_OPERAND_UDISP6, FR30_OPERAND_DISP8, FR30_OPERAND_DISP9
 244  , FR30_OPERAND_DISP10, FR30_OPERAND_S10, FR30_OPERAND_U10, FR30_OPERAND_I32
 245  , FR30_OPERAND_M4, FR30_OPERAND_I20, FR30_OPERAND_DIR8, FR30_OPERAND_DIR9
 246  , FR30_OPERAND_DIR10, FR30_OPERAND_LABEL9, FR30_OPERAND_LABEL12, FR30_OPERAND_REGLIST_LOW_LD
 247  , FR30_OPERAND_REGLIST_HI_LD, FR30_OPERAND_REGLIST_LOW_ST, FR30_OPERAND_REGLIST_HI_ST, FR30_OPERAND_CC
 248  , FR30_OPERAND_CCC, FR30_OPERAND_NBIT, FR30_OPERAND_VBIT, FR30_OPERAND_ZBIT
 249  , FR30_OPERAND_CBIT, FR30_OPERAND_IBIT, FR30_OPERAND_SBIT, FR30_OPERAND_TBIT
 250  , FR30_OPERAND_D0BIT, FR30_OPERAND_D1BIT, FR30_OPERAND_CCR, FR30_OPERAND_SCR
 251  , FR30_OPERAND_ILM, FR30_OPERAND_MAX
 252 } CGEN_OPERAND_TYPE;
 253
 254 /* Number of operands types.  */
 255 #define MAX_OPERANDS 49
 256
 257 /* Maximum number of operands referenced by any insn.  */
 258 #define MAX_OPERAND_INSTANCES 8
 259
 260 /* Insn attribute indices.  */
 261
 262 /* Enum declaration for cgen_insn attrs.  */
 263 typedef enum cgen_insn_attr {
 264   CGEN_INSN_ALIAS, CGEN_INSN_VIRTUAL, CGEN_INSN_UNCOND_CTI, CGEN_INSN_COND_CTI
 265  , CGEN_INSN_SKIP_CTI, CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE, CGEN_INSN_RELAXED
 266  , CGEN_INSN_NO_DIS, CGEN_INSN_PBB, CGEN_INSN_NOT_IN_DELAY_SLOT, CGEN_INSN_END_BOOLS
 267  , CGEN_INSN_START_NBOOLS = 31, CGEN_INSN_MACH, CGEN_INSN_END_NBOOLS
 268 } CGEN_INSN_ATTR;
 269
 270 /* Number of non-boolean elements in cgen_insn_attr.  */
 271 #define CGEN_INSN_NBOOL_ATTRS (CGEN_INSN_END_NBOOLS - CGEN_INSN_START_NBOOLS - 1)
 272
 273 /* cgen_insn attribute accessor macros.  */
 274 #define CGEN_ATTR_CGEN_INSN_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_MACH-CGEN_INSN_START_NBOOLS-1].nonbitset)
 275 #define CGEN_ATTR_CGEN_INSN_ALIAS_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_ALIAS)) != 0)
 276 #define CGEN_ATTR_CGEN_INSN_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_VIRTUAL)) != 0)
 277 #define CGEN_ATTR_CGEN_INSN_UNCOND_CTI_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_UNCOND_CTI)) != 0)
 278 #define CGEN_ATTR_CGEN_INSN_COND_CTI_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_COND_CTI)) != 0)
 279 #define CGEN_ATTR_CGEN_INSN_SKIP_CTI_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_SKIP_CTI)) != 0)
 280 #define CGEN_ATTR_CGEN_INSN_DELAY_SLOT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_DELAY_SLOT)) != 0)
 281 #define CGEN_ATTR_CGEN_INSN_RELAXABLE_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_RELAXABLE)) != 0)
 282 #define CGEN_ATTR_CGEN_INSN_RELAXED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_RELAXED)) != 0)
 283 #define CGEN_ATTR_CGEN_INSN_NO_DIS_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_NO_DIS)) != 0)
 284 #define CGEN_ATTR_CGEN_INSN_PBB_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_PBB)) != 0)
 285 #define CGEN_ATTR_CGEN_INSN_NOT_IN_DELAY_SLOT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_NOT_IN_DELAY_SLOT)) != 0)
 286
 287 /* cgen.h uses things we just defined.  */
 288 #include "opcode/cgen.h"
 289
 290 extern const struct cgen_ifld fr30_cgen_ifld_table[];
 291
 292 /* Attributes.  */
 293 extern const CGEN_ATTR_TABLE fr30_cgen_hardware_attr_table[];
 294 extern const CGEN_ATTR_TABLE fr30_cgen_ifield_attr_table[];
 295 extern const CGEN_ATTR_TABLE fr30_cgen_operand_attr_table[];
 296 extern const CGEN_ATTR_TABLE fr30_cgen_insn_attr_table[];
 297
 298 /* Hardware decls.  */
 299
 300 extern CGEN_KEYWORD fr30_cgen_opval_gr_names;
 301 extern CGEN_KEYWORD fr30_cgen_opval_cr_names;
 302 extern CGEN_KEYWORD fr30_cgen_opval_dr_names;
 303 extern CGEN_KEYWORD fr30_cgen_opval_h_ps;
 304 extern CGEN_KEYWORD fr30_cgen_opval_h_r13;
 305 extern CGEN_KEYWORD fr30_cgen_opval_h_r14;
 306 extern CGEN_KEYWORD fr30_cgen_opval_h_r15;
 307
 308 extern const CGEN_HW_ENTRY fr30_cgen_hw_table[];
 309
 310
 311
 312 #endif /* FR30_CPU_H */