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Check in ARCompact simulator. A valid configuration is arc-elf.
[binutils/xnox.git] / opcodes / arc-ibld.c
blob958dde723e2857dee70b8bd99813ac2a439d49ec
1 /* Instruction building/extraction support for arc. -*- C -*-
2
3 THIS FILE IS MACHINE GENERATED WITH CGEN: Cpu tools GENerator.
4 - the resultant file is machine generated, cgen-ibld.in isn't
5
6 Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2005, 2006, 2007
7 Free Software Foundation, Inc.
8
9 This file is part of libopcodes.
10
11 This library is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 3, or (at your option)
14 any later version.
15
16 It is distributed in the hope that it will be useful, but WITHOUT
17 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
18 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
19 License for more details.
20
21 You should have received a copy of the GNU General Public License
22 along with this program; if not, write to the Free Software Foundation, Inc.,
23 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
24
25 /* ??? Eventually more and more of this stuff can go to cpu-independent files.
26 Keep that in mind. */
27
28 #include "sysdep.h"
29 #include <stdio.h>
30 #include "ansidecl.h"
31 #include "dis-asm.h"
32 #include "bfd.h"
33 #include "symcat.h"
34 #include "arc-desc.h"
35 #include "arc-opc.h"
36 #include "opintl.h"
37 #include "safe-ctype.h"
38
39 #undef min
40 #define min(a,b) ((a) < (b) ? (a) : (b))
41 #undef max
42 #define max(a,b) ((a) > (b) ? (a) : (b))
43
44 /* Used by the ifield rtx function. */
45 #define FLD(f) (fields->f)
46
47 static const char * insert_normal
48 (CGEN_CPU_DESC, long, unsigned int, unsigned int, unsigned int,
49 unsigned int, unsigned int, unsigned int, CGEN_INSN_BYTES_PTR);
50 static const char * insert_insn_normal
51 (CGEN_CPU_DESC, const CGEN_INSN *,
52 CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma);
53 static int extract_normal
54 (CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, CGEN_INSN_INT,
55 unsigned int, unsigned int, unsigned int, unsigned int,
56 unsigned int, unsigned int, bfd_vma, long *);
57 static int extract_insn_normal
58 (CGEN_CPU_DESC, const CGEN_INSN *, CGEN_EXTRACT_INFO *,
59 CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma);
60 #if CGEN_INT_INSN_P
61 static void put_insn_int_value
62 (CGEN_CPU_DESC, CGEN_INSN_BYTES_PTR, int, int, CGEN_INSN_INT);
63 #endif
64 #if ! CGEN_INT_INSN_P
65 static CGEN_INLINE void insert_1
66 (CGEN_CPU_DESC, unsigned long, int, int, int, unsigned char *);
67 static CGEN_INLINE int fill_cache
68 (CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, int, int, bfd_vma);
69 static CGEN_INLINE long extract_1
70 (CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, int, int, int, unsigned char *, bfd_vma);
71 #endif
72 \f
73 /* Operand insertion. */
74
75 #if ! CGEN_INT_INSN_P
76
77 /* Subroutine of insert_normal. */
78
79 static CGEN_INLINE void
80 insert_1 (CGEN_CPU_DESC cd,
81 unsigned long value,
82 int start,
83 int length,
84 int word_length,
85 unsigned char *bufp)
86 {
87 unsigned long x,mask;
88 int shift;
89
90 x = cgen_get_insn_value (cd, bufp, word_length);
91
92 /* Written this way to avoid undefined behaviour. */
93 mask = (((1L << (length - 1)) - 1) << 1) | 1;
94 if (CGEN_INSN_LSB0_P)
95 shift = (start + 1) - length;
96 else
97 shift = (word_length - (start + length));
98 x = (x & ~(mask << shift)) | ((value & mask) << shift);
99
100 cgen_put_insn_value (cd, bufp, word_length, (bfd_vma) x);
101 }
102
103 #endif /* ! CGEN_INT_INSN_P */
104
105 /* Default insertion routine.
106
107 ATTRS is a mask of the boolean attributes.
108 WORD_OFFSET is the offset in bits from the start of the insn of the value.
109 WORD_LENGTH is the length of the word in bits in which the value resides.
110 START is the starting bit number in the word, architecture origin.
111 LENGTH is the length of VALUE in bits.
112 TOTAL_LENGTH is the total length of the insn in bits.
113
114 The result is an error message or NULL if success. */
115
116 /* ??? This duplicates functionality with bfd's howto table and
117 bfd_install_relocation. */
118 /* ??? This doesn't handle bfd_vma's. Create another function when
119 necessary. */
120
121 static const char *
122 insert_normal (CGEN_CPU_DESC cd,
123 long value,
124 unsigned int attrs,
125 unsigned int word_offset,
126 unsigned int start,
127 unsigned int length,
128 unsigned int word_length,
129 unsigned int total_length,
130 CGEN_INSN_BYTES_PTR buffer)
131 {
132 static char errbuf[100];
133 /* Written this way to avoid undefined behaviour. */
134 unsigned long mask = (((1L << (length - 1)) - 1) << 1) | 1;
135
136 /* If LENGTH is zero, this operand doesn't contribute to the value. */
137 if (length == 0)
138 return NULL;
139
140 if (word_length > 32)
141 abort ();
142
143 /* For architectures with insns smaller than the base-insn-bitsize,
144 word_length may be too big. */
145 if (cd->min_insn_bitsize < cd->base_insn_bitsize)
146 {
147 if (word_offset == 0
148 && word_length > total_length)
149 word_length = total_length;
150 }
151
152 /* Ensure VALUE will fit. */
153 if (CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGN_OPT))
154 {
155 long minval = - (1L << (length - 1));
156 unsigned long maxval = mask;
157
158 if ((value > 0 && (unsigned long) value > maxval)
159 || value < minval)
160 {
161 /* xgettext:c-format */
162 sprintf (errbuf,
163 _("operand out of range (%ld not between %ld and %lu)"),
164 value, minval, maxval);
165 return errbuf;
166 }
167 }
168 else if (! CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGNED))
169 {
170 unsigned long maxval = mask;
171 unsigned long val = (unsigned long) value;
172
173 /* For hosts with a word size > 32 check to see if value has been sign
174 extended beyond 32 bits. If so then ignore these higher sign bits
175 as the user is attempting to store a 32-bit signed value into an
176 unsigned 32-bit field which is allowed. */
177 if (sizeof (unsigned long) > 4 && ((value >> 32) == -1))
178 val &= 0xFFFFFFFF;
179
180 if (val > maxval)
181 {
182 /* xgettext:c-format */
183 sprintf (errbuf,
184 _("operand out of range (0x%lx not between 0 and 0x%lx)"),
185 val, maxval);
186 return errbuf;
187 }
188 }
189 else
190 {
191 if (! cgen_signed_overflow_ok_p (cd))
192 {
193 long minval = - (1L << (length - 1));
194 long maxval = (1L << (length - 1)) - 1;
195
196 if (value < minval || value > maxval)
197 {
198 sprintf
199 /* xgettext:c-format */
200 (errbuf, _("operand out of range (%ld not between %ld and %ld)"),
201 value, minval, maxval);
202 return errbuf;
203 }
204 }
205 }
206
207 #if CGEN_INT_INSN_P
208
209 {
210 int shift;
211
212 if (CGEN_INSN_LSB0_P)
213 shift = (word_offset + start + 1) - length;
214 else
215 shift = total_length - (word_offset + start + length);
216 *buffer = (*buffer & ~(mask << shift)) | ((value & mask) << shift);
217 }
218
219 #else /* ! CGEN_INT_INSN_P */
220
221 {
222 unsigned char *bufp = (unsigned char *) buffer + word_offset / 8;
223
224 insert_1 (cd, value, start, length, word_length, bufp);
225 }
226
227 #endif /* ! CGEN_INT_INSN_P */
228
229 return NULL;
230 }
231
232 /* Default insn builder (insert handler).
233 The instruction is recorded in CGEN_INT_INSN_P byte order (meaning
234 that if CGEN_INSN_BYTES_PTR is an int * and thus, the value is
235 recorded in host byte order, otherwise BUFFER is an array of bytes
236 and the value is recorded in target byte order).
237 The result is an error message or NULL if success. */
238
239 static const char *
240 insert_insn_normal (CGEN_CPU_DESC cd,
241 const CGEN_INSN * insn,
242 CGEN_FIELDS * fields,
243 CGEN_INSN_BYTES_PTR buffer,
244 bfd_vma pc)
245 {
246 const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn);
247 unsigned long value;
248 const CGEN_SYNTAX_CHAR_TYPE * syn;
249
250 CGEN_INIT_INSERT (cd);
251 value = CGEN_INSN_BASE_VALUE (insn);
252
253 /* If we're recording insns as numbers (rather than a string of bytes),
254 target byte order handling is deferred until later. */
255
256 #if CGEN_INT_INSN_P
257
258 put_insn_int_value (cd, buffer, cd->base_insn_bitsize,
259 CGEN_FIELDS_BITSIZE (fields), value);
260
261 #else
262
263 cgen_put_insn_value (cd, buffer, min ((unsigned) cd->base_insn_bitsize,
264 (unsigned) CGEN_FIELDS_BITSIZE (fields)),
265 value);
266
267 #endif /* ! CGEN_INT_INSN_P */
268
269 /* ??? It would be better to scan the format's fields.
270 Still need to be able to insert a value based on the operand though;
271 e.g. storing a branch displacement that got resolved later.
272 Needs more thought first. */
273
274 for (syn = CGEN_SYNTAX_STRING (syntax); * syn; ++ syn)
275 {
276 const char *errmsg;
277
278 if (CGEN_SYNTAX_CHAR_P (* syn))
279 continue;
280
281 errmsg = (* cd->insert_operand) (cd, CGEN_SYNTAX_FIELD (*syn),
282 fields, buffer, pc);
283 if (errmsg)
284 return errmsg;
285 }
286
287 return NULL;
288 }
289
290 #if CGEN_INT_INSN_P
291 /* Cover function to store an insn value into an integral insn. Must go here
292 because it needs <prefix>-desc.h for CGEN_INT_INSN_P. */
293
294 static void
295 put_insn_int_value (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
296 CGEN_INSN_BYTES_PTR buf,
297 int length,
298 int insn_length,
299 CGEN_INSN_INT value)
300 {
301 /* For architectures with insns smaller than the base-insn-bitsize,
302 length may be too big. */
303 if (length > insn_length)
304 *buf = value;
305 else
306 {
307 int shift = insn_length - length;
308 /* Written this way to avoid undefined behaviour. */
309 CGEN_INSN_INT mask = (((1L << (length - 1)) - 1) << 1) | 1;
310
311 *buf = (*buf & ~(mask << shift)) | ((value & mask) << shift);
312 }
313 }
314 #endif
315 \f
316 /* Operand extraction. */
317
318 #if ! CGEN_INT_INSN_P
319
320 /* Subroutine of extract_normal.
321 Ensure sufficient bytes are cached in EX_INFO.
322 OFFSET is the offset in bytes from the start of the insn of the value.
323 BYTES is the length of the needed value.
324 Returns 1 for success, 0 for failure. */
325
326 static CGEN_INLINE int
327 fill_cache (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
328 CGEN_EXTRACT_INFO *ex_info,
329 int offset,
330 int bytes,
331 bfd_vma pc)
332 {
333 /* It's doubtful that the middle part has already been fetched so
334 we don't optimize that case. kiss. */
335 unsigned int mask;
336 disassemble_info *info = (disassemble_info *) ex_info->dis_info;
337
338 /* First do a quick check. */
339 mask = (1 << bytes) - 1;
340 if (((ex_info->valid >> offset) & mask) == mask)
341 return 1;
342
343 /* Search for the first byte we need to read. */
344 for (mask = 1 << offset; bytes > 0; --bytes, ++offset, mask <<= 1)
345 if (! (mask & ex_info->valid))
346 break;
347
348 if (bytes)
349 {
350 int status;
351
352 pc += offset;
353 status = (*info->read_memory_func)
354 (pc, ex_info->insn_bytes + offset, bytes, info);
355
356 if (status != 0)
357 {
358 (*info->memory_error_func) (status, pc, info);
359 return 0;
360 }
361
362 ex_info->valid |= ((1 << bytes) - 1) << offset;
363 }
364
365 return 1;
366 }
367
368 /* Subroutine of extract_normal. */
369
370 static CGEN_INLINE long
371 extract_1 (CGEN_CPU_DESC cd,
372 CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED,
373 int start,
374 int length,
375 int word_length,
376 unsigned char *bufp,
377 bfd_vma pc ATTRIBUTE_UNUSED)
378 {
379 unsigned long x;
380 int shift;
381
382 x = cgen_get_insn_value (cd, bufp, word_length);
383
384 if (CGEN_INSN_LSB0_P)
385 shift = (start + 1) - length;
386 else
387 shift = (word_length - (start + length));
388 return x >> shift;
389 }
390
391 #endif /* ! CGEN_INT_INSN_P */
392
393 /* Default extraction routine.
394
395 INSN_VALUE is the first base_insn_bitsize bits of the insn in host order,
396 or sometimes less for cases like the m32r where the base insn size is 32
397 but some insns are 16 bits.
398 ATTRS is a mask of the boolean attributes. We only need `SIGNED',
399 but for generality we take a bitmask of all of them.
400 WORD_OFFSET is the offset in bits from the start of the insn of the value.
401 WORD_LENGTH is the length of the word in bits in which the value resides.
402 START is the starting bit number in the word, architecture origin.
403 LENGTH is the length of VALUE in bits.
404 TOTAL_LENGTH is the total length of the insn in bits.
405
406 Returns 1 for success, 0 for failure. */
407
408 /* ??? The return code isn't properly used. wip. */
409
410 /* ??? This doesn't handle bfd_vma's. Create another function when
411 necessary. */
412
413 static int
414 extract_normal (CGEN_CPU_DESC cd,
415 #if ! CGEN_INT_INSN_P
416 CGEN_EXTRACT_INFO *ex_info,
417 #else
418 CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED,
419 #endif
420 CGEN_INSN_INT insn_value,
421 unsigned int attrs,
422 unsigned int word_offset,
423 unsigned int start,
424 unsigned int length,
425 unsigned int word_length,
426 unsigned int total_length,
427 #if ! CGEN_INT_INSN_P
428 bfd_vma pc,
429 #else
430 bfd_vma pc ATTRIBUTE_UNUSED,
431 #endif
432 long *valuep)
433 {
434 long value, mask;
435
436 /* If LENGTH is zero, this operand doesn't contribute to the value
437 so give it a standard value of zero. */
438 if (length == 0)
439 {
440 *valuep = 0;
441 return 1;
442 }
443
444 if (word_length > 32)
445 abort ();
446
447 /* For architectures with insns smaller than the insn-base-bitsize,
448 word_length may be too big. */
449 if (cd->min_insn_bitsize < cd->base_insn_bitsize)
450 {
451 if (word_offset + word_length > total_length)
452 word_length = total_length - word_offset;
453 }
454
455 /* Does the value reside in INSN_VALUE, and at the right alignment? */
456
457 if (CGEN_INT_INSN_P || (word_offset == 0 && word_length == total_length))
458 {
459 if (CGEN_INSN_LSB0_P)
460 value = insn_value >> ((word_offset + start + 1) - length);
461 else
462 value = insn_value >> (total_length - ( word_offset + start + length));
463 }
464
465 #if ! CGEN_INT_INSN_P
466
467 else
468 {
469 unsigned char *bufp = ex_info->insn_bytes + word_offset / 8;
470
471 if (word_length > 32)
472 abort ();
473
474 if (fill_cache (cd, ex_info, word_offset / 8, word_length / 8, pc) == 0)
475 return 0;
476
477 value = extract_1 (cd, ex_info, start, length, word_length, bufp, pc);
478 }
479
480 #endif /* ! CGEN_INT_INSN_P */
481
482 /* Written this way to avoid undefined behaviour. */
483 mask = (((1L << (length - 1)) - 1) << 1) | 1;
484
485 value &= mask;
486 /* sign extend? */
487 if (CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGNED)
488 && (value & (1L << (length - 1))))
489 value |= ~mask;
490
491 *valuep = value;
492
493 return 1;
494 }
495
496 /* Default insn extractor.
497
498 INSN_VALUE is the first base_insn_bitsize bits, translated to host order.
499 The extracted fields are stored in FIELDS.
500 EX_INFO is used to handle reading variable length insns.
501 Return the length of the insn in bits, or 0 if no match,
502 or -1 if an error occurs fetching data (memory_error_func will have
503 been called). */
504
505 static int
506 extract_insn_normal (CGEN_CPU_DESC cd,
507 const CGEN_INSN *insn,
508 CGEN_EXTRACT_INFO *ex_info,
509 CGEN_INSN_INT insn_value,
510 CGEN_FIELDS *fields,
511 bfd_vma pc)
512 {
513 const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn);
514 const CGEN_SYNTAX_CHAR_TYPE *syn;
515
516 CGEN_FIELDS_BITSIZE (fields) = CGEN_INSN_BITSIZE (insn);
517
518 CGEN_INIT_EXTRACT (cd);
519
520 for (syn = CGEN_SYNTAX_STRING (syntax); *syn; ++syn)
521 {
522 int length;
523
524 if (CGEN_SYNTAX_CHAR_P (*syn))
525 continue;
526
527 length = (* cd->extract_operand) (cd, CGEN_SYNTAX_FIELD (*syn),
528 ex_info, insn_value, fields, pc);
529 if (length <= 0)
530 return length;
531 }
532
533 /* We recognized and successfully extracted this insn. */
534 return CGEN_INSN_BITSIZE (insn);
535 }
536 \f
537 /* Machine generated code added here. */
538
539 const char * arc_cgen_insert_operand
540 (CGEN_CPU_DESC, int, CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma);
541
542 /* Main entry point for operand insertion.
543
544 This function is basically just a big switch statement. Earlier versions
545 used tables to look up the function to use, but
546 - if the table contains both assembler and disassembler functions then
547 the disassembler contains much of the assembler and vice-versa,
548 - there's a lot of inlining possibilities as things grow,
549 - using a switch statement avoids the function call overhead.
550
551 This function could be moved into `parse_insn_normal', but keeping it
552 separate makes clear the interface between `parse_insn_normal' and each of
553 the handlers. It's also needed by GAS to insert operands that couldn't be
554 resolved during parsing. */
555
556 const char *
557 arc_cgen_insert_operand (CGEN_CPU_DESC cd,
558 int opindex,
559 CGEN_FIELDS * fields,
560 CGEN_INSN_BYTES_PTR buffer,
561 bfd_vma pc ATTRIBUTE_UNUSED)
562 {
563 const char * errmsg = NULL;
564 unsigned int total_length = CGEN_FIELDS_BITSIZE (fields);
565
566 switch (opindex)
567 {
568 case ARC_OPERAND_EXDI :
569 errmsg = insert_normal (cd, fields->f_F, 0, 0, 16, 1, 32, total_length, buffer);
570 break;
571 case ARC_OPERAND_F :
572 errmsg = insert_normal (cd, fields->f_F, 0, 0, 16, 1, 32, total_length, buffer);
573 break;
574 case ARC_OPERAND_F0 :
575 errmsg = insert_normal (cd, fields->f_F, 0, 0, 16, 1, 32, total_length, buffer);
576 break;
577 case ARC_OPERAND_F1 :
578 errmsg = insert_normal (cd, fields->f_F, 0, 0, 16, 1, 32, total_length, buffer);
579 break;
580 case ARC_OPERAND_F1F :
581 errmsg = insert_normal (cd, fields->f_F, 0, 0, 16, 1, 32, total_length, buffer);
582 break;
583 case ARC_OPERAND_GP :
584 break;
585 case ARC_OPERAND_LDODI :
586 errmsg = insert_normal (cd, fields->f_LDODi, 0, 0, 20, 1, 32, total_length, buffer);
587 break;
588 case ARC_OPERAND_LDRDI :
589 errmsg = insert_normal (cd, fields->f_LDRDi, 0, 0, 16, 1, 32, total_length, buffer);
590 break;
591 case ARC_OPERAND_NE :
592 break;
593 case ARC_OPERAND_PCL :
594 break;
595 case ARC_OPERAND_QCONDB :
596 errmsg = insert_normal (cd, fields->f_cond_Q, 0, 0, 27, 5, 32, total_length, buffer);
597 break;
598 case ARC_OPERAND_QCONDI :
599 errmsg = insert_normal (cd, fields->f_cond_Q, 0, 0, 27, 5, 32, total_length, buffer);
600 break;
601 case ARC_OPERAND_QCONDJ :
602 errmsg = insert_normal (cd, fields->f_cond_Q, 0, 0, 27, 5, 32, total_length, buffer);
603 break;
604 case ARC_OPERAND_R0 :
605 break;
606 case ARC_OPERAND_R31 :
607 break;
608 case ARC_OPERAND_RA :
609 errmsg = insert_normal (cd, fields->f_op_A, 0, 0, 26, 6, 32, total_length, buffer);
610 break;
611 case ARC_OPERAND_RA_0 :
612 errmsg = insert_normal (cd, fields->f_op_A, 0, 0, 26, 6, 32, total_length, buffer);
613 break;
614 case ARC_OPERAND_RB :
615 {
616 {
617 FLD (f_op__b) = ((FLD (f_op_B)) & (7));
618 FLD (f_B_5_3) = ((unsigned int) (FLD (f_op_B)) >> (3));
619 }
620 errmsg = insert_normal (cd, fields->f_op__b, 0, 0, 5, 3, 32, total_length, buffer);
621 if (errmsg)
622 break;
623 errmsg = insert_normal (cd, fields->f_B_5_3, 0, 0, 17, 3, 32, total_length, buffer);
624 if (errmsg)
625 break;
626 }
627 break;
628 case ARC_OPERAND_RB_0 :
629 {
630 {
631 FLD (f_op__b) = ((FLD (f_op_B)) & (7));
632 FLD (f_B_5_3) = ((unsigned int) (FLD (f_op_B)) >> (3));
633 }
634 errmsg = insert_normal (cd, fields->f_op__b, 0, 0, 5, 3, 32, total_length, buffer);
635 if (errmsg)
636 break;
637 errmsg = insert_normal (cd, fields->f_B_5_3, 0, 0, 17, 3, 32, total_length, buffer);
638 if (errmsg)
639 break;
640 }
641 break;
642 case ARC_OPERAND_RC :
643 errmsg = insert_normal (cd, fields->f_op_C, 0, 0, 20, 6, 32, total_length, buffer);
644 break;
645 case ARC_OPERAND_RC_ILINK :
646 errmsg = insert_normal (cd, fields->f_op_Cj, 0, 0, 20, 6, 32, total_length, buffer);
647 break;
648 case ARC_OPERAND_RC_NOILINK :
649 errmsg = insert_normal (cd, fields->f_op_Cj, 0, 0, 20, 6, 32, total_length, buffer);
650 break;
651 case ARC_OPERAND_R_A :
652 errmsg = insert_normal (cd, fields->f_op__a, 0, 0, 13, 3, 32, total_length, buffer);
653 break;
654 case ARC_OPERAND_R_B :
655 errmsg = insert_normal (cd, fields->f_op__b, 0, 0, 5, 3, 32, total_length, buffer);
656 break;
657 case ARC_OPERAND_R_C :
658 errmsg = insert_normal (cd, fields->f_op__c, 0, 0, 8, 3, 32, total_length, buffer);
659 break;
660 case ARC_OPERAND_RCC :
661 errmsg = insert_normal (cd, fields->f_brcond, 0, 0, 28, 4, 32, total_length, buffer);
662 break;
663 case ARC_OPERAND_RCCS :
664 errmsg = insert_normal (cd, fields->f_brscond, 0, 0, 8, 1, 32, total_length, buffer);
665 break;
666 case ARC_OPERAND_RH :
667 {
668 {
669 FLD (f_h_2_0) = ((FLD (f_op_h)) & (7));
670 FLD (f_h_5_3) = ((unsigned int) (FLD (f_op_h)) >> (3));
671 }
672 errmsg = insert_normal (cd, fields->f_h_2_0, 0, 0, 8, 3, 32, total_length, buffer);
673 if (errmsg)
674 break;
675 errmsg = insert_normal (cd, fields->f_h_5_3, 0, 0, 13, 3, 32, total_length, buffer);
676 if (errmsg)
677 break;
678 }
679 break;
680 case ARC_OPERAND_SP :
681 break;
682 case ARC_OPERAND_STODI :
683 errmsg = insert_normal (cd, fields->f_STODi, 0, 0, 26, 1, 32, total_length, buffer);
684 break;
685 case ARC_OPERAND_U6 :
686 errmsg = insert_normal (cd, fields->f_u6, 0, 0, 20, 6, 32, total_length, buffer);
687 break;
688 case ARC_OPERAND_U6X2 :
689 {
690 long value = fields->f_u6x2;
691 value = ((unsigned int) (value) >> (1));
692 errmsg = insert_normal (cd, value, 0, 0, 20, 6, 32, total_length, buffer);
693 }
694 break;
695 case ARC_OPERAND__AW :
696 break;
697 case ARC_OPERAND__L :
698 break;
699 case ARC_OPERAND__S :
700 break;
701 case ARC_OPERAND_CBIT :
702 break;
703 case ARC_OPERAND_DELAY_N :
704 errmsg = insert_normal (cd, fields->f_delay_N, 0, 0, 26, 1, 32, total_length, buffer);
705 break;
706 case ARC_OPERAND_DUMMY_OP :
707 errmsg = insert_normal (cd, fields->f_dummy, 0, 0, 16, 16, 32, total_length, buffer);
708 break;
709 case ARC_OPERAND_I2COND :
710 errmsg = insert_normal (cd, fields->f_cond_i2, 0, 0, 5, 2, 32, total_length, buffer);
711 break;
712 case ARC_OPERAND_I3COND :
713 errmsg = insert_normal (cd, fields->f_cond_i3, 0, 0, 7, 3, 32, total_length, buffer);
714 break;
715 case ARC_OPERAND_LABEL10 :
716 {
717 long value = fields->f_rel10;
718 value = ((int) (((value) - (((pc) & (-4))))) >> (1));
719 errmsg = insert_normal (cd, value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 7, 9, 32, total_length, buffer);
720 }
721 break;
722 case ARC_OPERAND_LABEL13A :
723 {
724 long value = fields->f_rel13bl;
725 value = ((int) (((value) - (((pc) & (-4))))) >> (2));
726 errmsg = insert_normal (cd, value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 5, 11, 32, total_length, buffer);
727 }
728 break;
729 case ARC_OPERAND_LABEL21 :
730 {
731 {
732 FLD (f_d21l) = ((((unsigned int) (((FLD (f_rel21)) - (((pc) & (-4))))) >> (1))) & (1023));
733 FLD (f_d21h) = ((unsigned int) (((FLD (f_rel21)) - (((pc) & (-4))))) >> (11));
734 }
735 errmsg = insert_normal (cd, fields->f_d21l, 0, 0, 5, 10, 32, total_length, buffer);
736 if (errmsg)
737 break;
738 errmsg = insert_normal (cd, fields->f_d21h, 0|(1<<CGEN_IFLD_SIGNED), 0, 16, 10, 32, total_length, buffer);
739 if (errmsg)
740 break;
741 }
742 break;
743 case ARC_OPERAND_LABEL21A :
744 {
745 {
746 FLD (f_d21bl) = ((((unsigned int) (((FLD (f_rel21bl)) - (((pc) & (-4))))) >> (2))) & (511));
747 FLD (f_d21h) = ((unsigned int) (((FLD (f_rel21bl)) - (((pc) & (-4))))) >> (11));
748 }
749 errmsg = insert_normal (cd, fields->f_d21bl, 0, 0, 5, 9, 32, total_length, buffer);
750 if (errmsg)
751 break;
752 errmsg = insert_normal (cd, fields->f_d21h, 0|(1<<CGEN_IFLD_SIGNED), 0, 16, 10, 32, total_length, buffer);
753 if (errmsg)
754 break;
755 }
756 break;
757 case ARC_OPERAND_LABEL25 :
758 {
759 {
760 FLD (f_d21l) = ((((unsigned int) (((FLD (f_rel25)) - (((pc) & (-4))))) >> (1))) & (1023));
761 FLD (f_d25m) = ((unsigned int) (((FLD (f_rel25)) - (((pc) & (-4))))) >> (11));
762 FLD (f_d25h) = ((unsigned int) (((FLD (f_rel25)) - (((pc) & (-4))))) >> (21));
763 }
764 errmsg = insert_normal (cd, fields->f_d21l, 0, 0, 5, 10, 32, total_length, buffer);
765 if (errmsg)
766 break;
767 errmsg = insert_normal (cd, fields->f_d25m, 0, 0, 16, 10, 32, total_length, buffer);
768 if (errmsg)
769 break;
770 errmsg = insert_normal (cd, fields->f_d25h, 0|(1<<CGEN_IFLD_SIGNED), 0, 28, 4, 32, total_length, buffer);
771 if (errmsg)
772 break;
773 }
774 break;
775 case ARC_OPERAND_LABEL25A :
776 {
777 {
778 FLD (f_d21bl) = ((((unsigned int) (((FLD (f_rel25bl)) - (((pc) & (-4))))) >> (2))) & (511));
779 FLD (f_d25m) = ((unsigned int) (((FLD (f_rel25bl)) - (((pc) & (-4))))) >> (11));
780 FLD (f_d25h) = ((unsigned int) (((FLD (f_rel25bl)) - (((pc) & (-4))))) >> (21));
781 }
782 errmsg = insert_normal (cd, fields->f_d21bl, 0, 0, 5, 9, 32, total_length, buffer);
783 if (errmsg)
784 break;
785 errmsg = insert_normal (cd, fields->f_d25m, 0, 0, 16, 10, 32, total_length, buffer);
786 if (errmsg)
787 break;
788 errmsg = insert_normal (cd, fields->f_d25h, 0|(1<<CGEN_IFLD_SIGNED), 0, 28, 4, 32, total_length, buffer);
789 if (errmsg)
790 break;
791 }
792 break;
793 case ARC_OPERAND_LABEL7 :
794 {
795 long value = fields->f_rel7;
796 value = ((int) (((value) - (((pc) & (-4))))) >> (1));
797 errmsg = insert_normal (cd, value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 10, 6, 32, total_length, buffer);
798 }
799 break;
800 case ARC_OPERAND_LABEL8 :
801 {
802 long value = fields->f_rel8;
803 value = ((int) (((value) - (((pc) & (-4))))) >> (1));
804 errmsg = insert_normal (cd, value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 9, 7, 32, total_length, buffer);
805 }
806 break;
807 case ARC_OPERAND_LABEL9 :
808 {
809 {
810 FLD (f_d9l) = ((((unsigned int) (((FLD (f_rel9)) - (((pc) & (-4))))) >> (1))) & (127));
811 FLD (f_d9h) = ((unsigned int) (((FLD (f_rel9)) - (((pc) & (-4))))) >> (8));
812 }
813 errmsg = insert_normal (cd, fields->f_d9l, 0, 0, 8, 7, 32, total_length, buffer);
814 if (errmsg)
815 break;
816 errmsg = insert_normal (cd, fields->f_d9h, 0|(1<<CGEN_IFLD_SIGNED), 0, 16, 1, 32, total_length, buffer);
817 if (errmsg)
818 break;
819 }
820 break;
821 case ARC_OPERAND_LBIT :
822 break;
823 case ARC_OPERAND_NBIT :
824 break;
825 case ARC_OPERAND_S12 :
826 {
827 {
828 FLD (f_u6) = ((FLD (f_s12)) & (63));
829 FLD (f_s12h) = ((unsigned int) (FLD (f_s12)) >> (6));
830 }
831 errmsg = insert_normal (cd, fields->f_u6, 0, 0, 20, 6, 32, total_length, buffer);
832 if (errmsg)
833 break;
834 errmsg = insert_normal (cd, fields->f_s12h, 0|(1<<CGEN_IFLD_SIGNED), 0, 26, 6, 32, total_length, buffer);
835 if (errmsg)
836 break;
837 }
838 break;
839 case ARC_OPERAND_S12X2 :
840 {
841 {
842 FLD (f_u6) = ((((unsigned int) (FLD (f_s12x2)) >> (1))) & (63));
843 FLD (f_s12h) = ((unsigned int) (FLD (f_s12x2)) >> (7));
844 }
845 errmsg = insert_normal (cd, fields->f_u6, 0, 0, 20, 6, 32, total_length, buffer);
846 if (errmsg)
847 break;
848 errmsg = insert_normal (cd, fields->f_s12h, 0|(1<<CGEN_IFLD_SIGNED), 0, 26, 6, 32, total_length, buffer);
849 if (errmsg)
850 break;
851 }
852 break;
853 case ARC_OPERAND_S1BIT :
854 break;
855 case ARC_OPERAND_S2BIT :
856 break;
857 case ARC_OPERAND_S9 :
858 {
859 {
860 FLD (f_u8) = ((FLD (f_s9)) & (255));
861 FLD (f_d9h) = ((unsigned int) (FLD (f_s9)) >> (8));
862 }
863 errmsg = insert_normal (cd, fields->f_u8, 0, 0, 8, 8, 32, total_length, buffer);
864 if (errmsg)
865 break;
866 errmsg = insert_normal (cd, fields->f_d9h, 0|(1<<CGEN_IFLD_SIGNED), 0, 16, 1, 32, total_length, buffer);
867 if (errmsg)
868 break;
869 }
870 break;
871 case ARC_OPERAND_S9X4 :
872 {
873 long value = fields->f_s9x4;
874 value = ((unsigned int) (value) >> (2));
875 errmsg = insert_normal (cd, value, 0|(1<<CGEN_IFLD_SIGNED), 0, 7, 9, 32, total_length, buffer);
876 }
877 break;
878 case ARC_OPERAND_SC_S9_ :
879 {
880 long value = fields->f_s9x4;
881 value = ((unsigned int) (value) >> (2));
882 errmsg = insert_normal (cd, value, 0|(1<<CGEN_IFLD_SIGNED), 0, 7, 9, 32, total_length, buffer);
883 }
884 break;
885 case ARC_OPERAND_SC_S9B :
886 errmsg = insert_normal (cd, fields->f_s9x1, 0|(1<<CGEN_IFLD_SIGNED), 0, 7, 9, 32, total_length, buffer);
887 break;
888 case ARC_OPERAND_SC_S9W :
889 {
890 long value = fields->f_s9x2;
891 value = ((unsigned int) (value) >> (1));
892 errmsg = insert_normal (cd, value, 0|(1<<CGEN_IFLD_SIGNED), 0, 7, 9, 32, total_length, buffer);
893 }
894 break;
895 case ARC_OPERAND_SC_U5_ :
896 {
897 long value = fields->f_u5x4;
898 value = ((unsigned int) (value) >> (2));
899 errmsg = insert_normal (cd, value, 0, 0, 11, 5, 32, total_length, buffer);
900 }
901 break;
902 case ARC_OPERAND_SC_U5B :
903 errmsg = insert_normal (cd, fields->f_u5, 0, 0, 11, 5, 32, total_length, buffer);
904 break;
905 case ARC_OPERAND_SC_U5W :
906 {
907 long value = fields->f_u5x2;
908 value = ((unsigned int) (value) >> (1));
909 errmsg = insert_normal (cd, value, 0, 0, 11, 5, 32, total_length, buffer);
910 }
911 break;
912 case ARC_OPERAND_TRAPNUM :
913 errmsg = insert_normal (cd, fields->f_trapnum, 0, 0, 5, 6, 32, total_length, buffer);
914 break;
915 case ARC_OPERAND_U3 :
916 errmsg = insert_normal (cd, fields->f_u3, 0, 0, 13, 3, 32, total_length, buffer);
917 break;
918 case ARC_OPERAND_U5 :
919 errmsg = insert_normal (cd, fields->f_u5, 0, 0, 11, 5, 32, total_length, buffer);
920 break;
921 case ARC_OPERAND_U5X4 :
922 {
923 long value = fields->f_u5x4;
924 value = ((unsigned int) (value) >> (2));
925 errmsg = insert_normal (cd, value, 0, 0, 11, 5, 32, total_length, buffer);
926 }
927 break;
928 case ARC_OPERAND_U7 :
929 errmsg = insert_normal (cd, fields->f_u7, 0, 0, 9, 7, 32, total_length, buffer);
930 break;
931 case ARC_OPERAND_U8 :
932 errmsg = insert_normal (cd, fields->f_u8, 0, 0, 8, 8, 32, total_length, buffer);
933 break;
934 case ARC_OPERAND_U8X4 :
935 {
936 long value = fields->f_u8x4;
937 value = ((unsigned int) (value) >> (2));
938 errmsg = insert_normal (cd, value, 0, 0, 8, 8, 32, total_length, buffer);
939 }
940 break;
941 case ARC_OPERAND_UNCONDB :
942 break;
943 case ARC_OPERAND_UNCONDI :
944 break;
945 case ARC_OPERAND_UNCONDJ :
946 break;
947 case ARC_OPERAND_VBIT :
948 break;
949 case ARC_OPERAND_ZBIT :
950 break;
951
952 default :
953 /* xgettext:c-format */
954 fprintf (stderr, _("Unrecognized field %d while building insn.\n"),
955 opindex);
956 abort ();
957 }
958
959 return errmsg;
960 }
961
962 int arc_cgen_extract_operand
963 (CGEN_CPU_DESC, int, CGEN_EXTRACT_INFO *, CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma);
964
965 /* Main entry point for operand extraction.
966 The result is <= 0 for error, >0 for success.
967 ??? Actual values aren't well defined right now.
968
969 This function is basically just a big switch statement. Earlier versions
970 used tables to look up the function to use, but
971 - if the table contains both assembler and disassembler functions then
972 the disassembler contains much of the assembler and vice-versa,
973 - there's a lot of inlining possibilities as things grow,
974 - using a switch statement avoids the function call overhead.
975
976 This function could be moved into `print_insn_normal', but keeping it
977 separate makes clear the interface between `print_insn_normal' and each of
978 the handlers. */
979
980 int
981 arc_cgen_extract_operand (CGEN_CPU_DESC cd,
982 int opindex,
983 CGEN_EXTRACT_INFO *ex_info,
984 CGEN_INSN_INT insn_value,
985 CGEN_FIELDS * fields,
986 bfd_vma pc)
987 {
988 /* Assume success (for those operands that are nops). */
989 int length = 1;
990 unsigned int total_length = CGEN_FIELDS_BITSIZE (fields);
991
992 switch (opindex)
993 {
994 case ARC_OPERAND_EXDI :
995 length = extract_normal (cd, ex_info, insn_value, 0, 0, 16, 1, 32, total_length, pc, & fields->f_F);
996 break;
997 case ARC_OPERAND_F :
998 length = extract_normal (cd, ex_info, insn_value, 0, 0, 16, 1, 32, total_length, pc, & fields->f_F);
999 break;
1000 case ARC_OPERAND_F0 :
1001 length = extract_normal (cd, ex_info, insn_value, 0, 0, 16, 1, 32, total_length, pc, & fields->f_F);
1002 break;
1003 case ARC_OPERAND_F1 :
1004 length = extract_normal (cd, ex_info, insn_value, 0, 0, 16, 1, 32, total_length, pc, & fields->f_F);
1005 break;
1006 case ARC_OPERAND_F1F :
1007 length = extract_normal (cd, ex_info, insn_value, 0, 0, 16, 1, 32, total_length, pc, & fields->f_F);
1008 break;
1009 case ARC_OPERAND_GP :
1010 break;
1011 case ARC_OPERAND_LDODI :
1012 length = extract_normal (cd, ex_info, insn_value, 0, 0, 20, 1, 32, total_length, pc, & fields->f_LDODi);
1013 break;
1014 case ARC_OPERAND_LDRDI :
1015 length = extract_normal (cd, ex_info, insn_value, 0, 0, 16, 1, 32, total_length, pc, & fields->f_LDRDi);
1016 break;
1017 case ARC_OPERAND_NE :
1018 break;
1019 case ARC_OPERAND_PCL :
1020 break;
1021 case ARC_OPERAND_QCONDB :
1022 length = extract_normal (cd, ex_info, insn_value, 0, 0, 27, 5, 32, total_length, pc, & fields->f_cond_Q);
1023 break;
1024 case ARC_OPERAND_QCONDI :
1025 length = extract_normal (cd, ex_info, insn_value, 0, 0, 27, 5, 32, total_length, pc, & fields->f_cond_Q);
1026 break;
1027 case ARC_OPERAND_QCONDJ :
1028 length = extract_normal (cd, ex_info, insn_value, 0, 0, 27, 5, 32, total_length, pc, & fields->f_cond_Q);
1029 break;
1030 case ARC_OPERAND_R0 :
1031 break;
1032 case ARC_OPERAND_R31 :
1033 break;
1034 case ARC_OPERAND_RA :
1035 length = extract_normal (cd, ex_info, insn_value, 0, 0, 26, 6, 32, total_length, pc, & fields->f_op_A);
1036 break;
1037 case ARC_OPERAND_RA_0 :
1038 length = extract_normal (cd, ex_info, insn_value, 0, 0, 26, 6, 32, total_length, pc, & fields->f_op_A);
1039 break;
1040 case ARC_OPERAND_RB :
1041 {
1042 length = extract_normal (cd, ex_info, insn_value, 0, 0, 5, 3, 32, total_length, pc, & fields->f_op__b);
1043 if (length <= 0) break;
1044 length = extract_normal (cd, ex_info, insn_value, 0, 0, 17, 3, 32, total_length, pc, & fields->f_B_5_3);
1045 if (length <= 0) break;
1046 {
1047 FLD (f_op_B) = ((FLD (f_op__b)) | (((FLD (f_B_5_3)) << (3))));
1048 }
1049 }
1050 break;
1051 case ARC_OPERAND_RB_0 :
1052 {
1053 length = extract_normal (cd, ex_info, insn_value, 0, 0, 5, 3, 32, total_length, pc, & fields->f_op__b);
1054 if (length <= 0) break;
1055 length = extract_normal (cd, ex_info, insn_value, 0, 0, 17, 3, 32, total_length, pc, & fields->f_B_5_3);
1056 if (length <= 0) break;
1057 {
1058 FLD (f_op_B) = ((FLD (f_op__b)) | (((FLD (f_B_5_3)) << (3))));
1059 }
1060 }
1061 break;
1062 case ARC_OPERAND_RC :
1063 length = extract_normal (cd, ex_info, insn_value, 0, 0, 20, 6, 32, total_length, pc, & fields->f_op_C);
1064 break;
1065 case ARC_OPERAND_RC_ILINK :
1066 length = extract_normal (cd, ex_info, insn_value, 0, 0, 20, 6, 32, total_length, pc, & fields->f_op_Cj);
1067 break;
1068 case ARC_OPERAND_RC_NOILINK :
1069 length = extract_normal (cd, ex_info, insn_value, 0, 0, 20, 6, 32, total_length, pc, & fields->f_op_Cj);
1070 break;
1071 case ARC_OPERAND_R_A :
1072 length = extract_normal (cd, ex_info, insn_value, 0, 0, 13, 3, 32, total_length, pc, & fields->f_op__a);
1073 break;
1074 case ARC_OPERAND_R_B :
1075 length = extract_normal (cd, ex_info, insn_value, 0, 0, 5, 3, 32, total_length, pc, & fields->f_op__b);
1076 break;
1077 case ARC_OPERAND_R_C :
1078 length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 3, 32, total_length, pc, & fields->f_op__c);
1079 break;
1080 case ARC_OPERAND_RCC :
1081 length = extract_normal (cd, ex_info, insn_value, 0, 0, 28, 4, 32, total_length, pc, & fields->f_brcond);
1082 break;
1083 case ARC_OPERAND_RCCS :
1084 length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 1, 32, total_length, pc, & fields->f_brscond);
1085 break;
1086 case ARC_OPERAND_RH :
1087 {
1088 length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 3, 32, total_length, pc, & fields->f_h_2_0);
1089 if (length <= 0) break;
1090 length = extract_normal (cd, ex_info, insn_value, 0, 0, 13, 3, 32, total_length, pc, & fields->f_h_5_3);
1091 if (length <= 0) break;
1092 {
1093 FLD (f_op_h) = ((FLD (f_h_2_0)) | (((FLD (f_h_5_3)) << (3))));
1094 }
1095 }
1096 break;
1097 case ARC_OPERAND_SP :
1098 break;
1099 case ARC_OPERAND_STODI :
1100 length = extract_normal (cd, ex_info, insn_value, 0, 0, 26, 1, 32, total_length, pc, & fields->f_STODi);
1101 break;
1102 case ARC_OPERAND_U6 :
1103 length = extract_normal (cd, ex_info, insn_value, 0, 0, 20, 6, 32, total_length, pc, & fields->f_u6);
1104 break;
1105 case ARC_OPERAND_U6X2 :
1106 {
1107 long value;
1108 length = extract_normal (cd, ex_info, insn_value, 0, 0, 20, 6, 32, total_length, pc, & value);
1109 value = ((value) << (1));
1110 fields->f_u6x2 = value;
1111 }
1112 break;
1113 case ARC_OPERAND__AW :
1114 break;
1115 case ARC_OPERAND__L :
1116 break;
1117 case ARC_OPERAND__S :
1118 break;
1119 case ARC_OPERAND_CBIT :
1120 break;
1121 case ARC_OPERAND_DELAY_N :
1122 length = extract_normal (cd, ex_info, insn_value, 0, 0, 26, 1, 32, total_length, pc, & fields->f_delay_N);
1123 break;
1124 case ARC_OPERAND_DUMMY_OP :
1125 length = extract_normal (cd, ex_info, insn_value, 0, 0, 16, 16, 32, total_length, pc, & fields->f_dummy);
1126 break;
1127 case ARC_OPERAND_I2COND :
1128 length = extract_normal (cd, ex_info, insn_value, 0, 0, 5, 2, 32, total_length, pc, & fields->f_cond_i2);
1129 break;
1130 case ARC_OPERAND_I3COND :
1131 length = extract_normal (cd, ex_info, insn_value, 0, 0, 7, 3, 32, total_length, pc, & fields->f_cond_i3);
1132 break;
1133 case ARC_OPERAND_LABEL10 :
1134 {
1135 long value;
1136 length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 7, 9, 32, total_length, pc, & value);
1137 value = ((((value) << (1))) + (((pc) & (-4))));
1138 fields->f_rel10 = value;
1139 }
1140 break;
1141 case ARC_OPERAND_LABEL13A :
1142 {
1143 long value;
1144 length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 5, 11, 32, total_length, pc, & value);
1145 value = ((((value) << (2))) + (((pc) & (-4))));
1146 fields->f_rel13bl = value;
1147 }
1148 break;
1149 case ARC_OPERAND_LABEL21 :
1150 {
1151 length = extract_normal (cd, ex_info, insn_value, 0, 0, 5, 10, 32, total_length, pc, & fields->f_d21l);
1152 if (length <= 0) break;
1153 length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 0, 16, 10, 32, total_length, pc, & fields->f_d21h);
1154 if (length <= 0) break;
1155 {
1156 FLD (f_rel21) = ((((((FLD (f_d21l)) << (1))) | (((FLD (f_d21h)) << (11))))) + (((pc) & (-4))));
1157 }
1158 }
1159 break;
1160 case ARC_OPERAND_LABEL21A :
1161 {
1162 length = extract_normal (cd, ex_info, insn_value, 0, 0, 5, 9, 32, total_length, pc, & fields->f_d21bl);
1163 if (length <= 0) break;
1164 length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 0, 16, 10, 32, total_length, pc, & fields->f_d21h);
1165 if (length <= 0) break;
1166 {
1167 FLD (f_rel21bl) = ((((((FLD (f_d21bl)) << (2))) | (((FLD (f_d21h)) << (11))))) + (((pc) & (-4))));
1168 }
1169 }
1170 break;
1171 case ARC_OPERAND_LABEL25 :
1172 {
1173 length = extract_normal (cd, ex_info, insn_value, 0, 0, 5, 10, 32, total_length, pc, & fields->f_d21l);
1174 if (length <= 0) break;
1175 length = extract_normal (cd, ex_info, insn_value, 0, 0, 16, 10, 32, total_length, pc, & fields->f_d25m);
1176 if (length <= 0) break;
1177 length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 0, 28, 4, 32, total_length, pc, & fields->f_d25h);
1178 if (length <= 0) break;
1179 {
1180 FLD (f_rel25) = ((((((((FLD (f_d21l)) << (1))) | (((FLD (f_d25m)) << (11))))) | (((FLD (f_d25h)) << (21))))) + (((pc) & (-4))));
1181 }
1182 }
1183 break;
1184 case ARC_OPERAND_LABEL25A :
1185 {
1186 length = extract_normal (cd, ex_info, insn_value, 0, 0, 5, 9, 32, total_length, pc, & fields->f_d21bl);
1187 if (length <= 0) break;
1188 length = extract_normal (cd, ex_info, insn_value, 0, 0, 16, 10, 32, total_length, pc, & fields->f_d25m);
1189 if (length <= 0) break;
1190 length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 0, 28, 4, 32, total_length, pc, & fields->f_d25h);
1191 if (length <= 0) break;
1192 {
1193 FLD (f_rel25bl) = ((((((((FLD (f_d21bl)) << (2))) | (((FLD (f_d25m)) << (11))))) | (((FLD (f_d25h)) << (21))))) + (((pc) & (-4))));
1194 }
1195 }
1196 break;
1197 case ARC_OPERAND_LABEL7 :
1198 {
1199 long value;
1200 length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 10, 6, 32, total_length, pc, & value);
1201 value = ((((value) << (1))) + (((pc) & (-4))));
1202 fields->f_rel7 = value;
1203 }
1204 break;
1205 case ARC_OPERAND_LABEL8 :
1206 {
1207 long value;
1208 length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 9, 7, 32, total_length, pc, & value);
1209 value = ((((value) << (1))) + (((pc) & (-4))));
1210 fields->f_rel8 = value;
1211 }
1212 break;
1213 case ARC_OPERAND_LABEL9 :
1214 {
1215 length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 7, 32, total_length, pc, & fields->f_d9l);
1216 if (length <= 0) break;
1217 length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 0, 16, 1, 32, total_length, pc, & fields->f_d9h);
1218 if (length <= 0) break;
1219 {
1220 FLD (f_rel9) = ((((((FLD (f_d9l)) << (1))) | (((FLD (f_d9h)) << (8))))) + (((pc) & (-4))));
1221 }
1222 }
1223 break;
1224 case ARC_OPERAND_LBIT :
1225 break;
1226 case ARC_OPERAND_NBIT :
1227 break;
1228 case ARC_OPERAND_S12 :
1229 {
1230 length = extract_normal (cd, ex_info, insn_value, 0, 0, 20, 6, 32, total_length, pc, & fields->f_u6);
1231 if (length <= 0) break;
1232 length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 0, 26, 6, 32, total_length, pc, & fields->f_s12h);
1233 if (length <= 0) break;
1234 {
1235 FLD (f_s12) = ((FLD (f_u6)) | (((FLD (f_s12h)) << (6))));
1236 }
1237 }
1238 break;
1239 case ARC_OPERAND_S12X2 :
1240 {
1241 length = extract_normal (cd, ex_info, insn_value, 0, 0, 20, 6, 32, total_length, pc, & fields->f_u6);
1242 if (length <= 0) break;
1243 length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 0, 26, 6, 32, total_length, pc, & fields->f_s12h);
1244 if (length <= 0) break;
1245 {
1246 FLD (f_s12x2) = ((((FLD (f_u6)) << (1))) | (((FLD (f_s12h)) << (7))));
1247 }
1248 }
1249 break;
1250 case ARC_OPERAND_S1BIT :
1251 break;
1252 case ARC_OPERAND_S2BIT :
1253 break;
1254 case ARC_OPERAND_S9 :
1255 {
1256 length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 8, 32, total_length, pc, & fields->f_u8);
1257 if (length <= 0) break;
1258 length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 0, 16, 1, 32, total_length, pc, & fields->f_d9h);
1259 if (length <= 0) break;
1260 {
1261 FLD (f_s9) = ((FLD (f_u8)) | (((FLD (f_d9h)) << (8))));
1262 }
1263 }
1264 break;
1265 case ARC_OPERAND_S9X4 :
1266 {
1267 long value;
1268 length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 0, 7, 9, 32, total_length, pc, & value);
1269 value = ((value) << (2));
1270 fields->f_s9x4 = value;
1271 }
1272 break;
1273 case ARC_OPERAND_SC_S9_ :
1274 {
1275 long value;
1276 length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 0, 7, 9, 32, total_length, pc, & value);
1277 value = ((value) << (2));
1278 fields->f_s9x4 = value;
1279 }
1280 break;
1281 case ARC_OPERAND_SC_S9B :
1282 length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 0, 7, 9, 32, total_length, pc, & fields->f_s9x1);
1283 break;
1284 case ARC_OPERAND_SC_S9W :
1285 {
1286 long value;
1287 length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 0, 7, 9, 32, total_length, pc, & value);
1288 value = ((value) << (1));
1289 fields->f_s9x2 = value;
1290 }
1291 break;
1292 case ARC_OPERAND_SC_U5_ :
1293 {
1294 long value;
1295 length = extract_normal (cd, ex_info, insn_value, 0, 0, 11, 5, 32, total_length, pc, & value);
1296 value = ((value) << (2));
1297 fields->f_u5x4 = value;
1298 }
1299 break;
1300 case ARC_OPERAND_SC_U5B :
1301 length = extract_normal (cd, ex_info, insn_value, 0, 0, 11, 5, 32, total_length, pc, & fields->f_u5);
1302 break;
1303 case ARC_OPERAND_SC_U5W :
1304 {
1305 long value;
1306 length = extract_normal (cd, ex_info, insn_value, 0, 0, 11, 5, 32, total_length, pc, & value);
1307 value = ((value) << (1));
1308 fields->f_u5x2 = value;
1309 }
1310 break;
1311 case ARC_OPERAND_TRAPNUM :
1312 length = extract_normal (cd, ex_info, insn_value, 0, 0, 5, 6, 32, total_length, pc, & fields->f_trapnum);
1313 break;
1314 case ARC_OPERAND_U3 :
1315 length = extract_normal (cd, ex_info, insn_value, 0, 0, 13, 3, 32, total_length, pc, & fields->f_u3);
1316 break;
1317 case ARC_OPERAND_U5 :
1318 length = extract_normal (cd, ex_info, insn_value, 0, 0, 11, 5, 32, total_length, pc, & fields->f_u5);
1319 break;
1320 case ARC_OPERAND_U5X4 :
1321 {
1322 long value;
1323 length = extract_normal (cd, ex_info, insn_value, 0, 0, 11, 5, 32, total_length, pc, & value);
1324 value = ((value) << (2));
1325 fields->f_u5x4 = value;
1326 }
1327 break;
1328 case ARC_OPERAND_U7 :
1329 length = extract_normal (cd, ex_info, insn_value, 0, 0, 9, 7, 32, total_length, pc, & fields->f_u7);
1330 break;
1331 case ARC_OPERAND_U8 :
1332 length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 8, 32, total_length, pc, & fields->f_u8);
1333 break;
1334 case ARC_OPERAND_U8X4 :
1335 {
1336 long value;
1337 length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 8, 32, total_length, pc, & value);
1338 value = ((value) << (2));
1339 fields->f_u8x4 = value;
1340 }
1341 break;
1342 case ARC_OPERAND_UNCONDB :
1343 break;
1344 case ARC_OPERAND_UNCONDI :
1345 break;
1346 case ARC_OPERAND_UNCONDJ :
1347 break;
1348 case ARC_OPERAND_VBIT :
1349 break;
1350 case ARC_OPERAND_ZBIT :
1351 break;
1352
1353 default :
1354 /* xgettext:c-format */
1355 fprintf (stderr, _("Unrecognized field %d while decoding insn.\n"),
1356 opindex);
1357 abort ();
1358 }
1359
1360 return length;
1361 }
1362
1363 cgen_insert_fn * const arc_cgen_insert_handlers[] =
1364 {
1365 insert_insn_normal,
1366 };
1367
1368 cgen_extract_fn * const arc_cgen_extract_handlers[] =
1369 {
1370 extract_insn_normal,
1371 };
1372
1373 int arc_cgen_get_int_operand (CGEN_CPU_DESC, int, const CGEN_FIELDS *);
1374 bfd_vma arc_cgen_get_vma_operand (CGEN_CPU_DESC, int, const CGEN_FIELDS *);
1375
1376 /* Getting values from cgen_fields is handled by a collection of functions.
1377 They are distinguished by the type of the VALUE argument they return.
1378 TODO: floating point, inlining support, remove cases where result type
1379 not appropriate. */
1380
1381 int
1382 arc_cgen_get_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
1383 int opindex,
1384 const CGEN_FIELDS * fields)
1385 {
1386 int value;
1387
1388 switch (opindex)
1389 {
1390 case ARC_OPERAND_EXDI :
1391 value = fields->f_F;
1392 break;
1393 case ARC_OPERAND_F :
1394 value = fields->f_F;
1395 break;
1396 case ARC_OPERAND_F0 :
1397 value = fields->f_F;
1398 break;
1399 case ARC_OPERAND_F1 :
1400 value = fields->f_F;
1401 break;
1402 case ARC_OPERAND_F1F :
1403 value = fields->f_F;
1404 break;
1405 case ARC_OPERAND_GP :
1406 value = 0;
1407 break;
1408 case ARC_OPERAND_LDODI :
1409 value = fields->f_LDODi;
1410 break;
1411 case ARC_OPERAND_LDRDI :
1412 value = fields->f_LDRDi;
1413 break;
1414 case ARC_OPERAND_NE :
1415 value = 0;
1416 break;
1417 case ARC_OPERAND_PCL :
1418 value = 0;
1419 break;
1420 case ARC_OPERAND_QCONDB :
1421 value = fields->f_cond_Q;
1422 break;
1423 case ARC_OPERAND_QCONDI :
1424 value = fields->f_cond_Q;
1425 break;
1426 case ARC_OPERAND_QCONDJ :
1427 value = fields->f_cond_Q;
1428 break;
1429 case ARC_OPERAND_R0 :
1430 value = 0;
1431 break;
1432 case ARC_OPERAND_R31 :
1433 value = 0;
1434 break;
1435 case ARC_OPERAND_RA :
1436 value = fields->f_op_A;
1437 break;
1438 case ARC_OPERAND_RA_0 :
1439 value = fields->f_op_A;
1440 break;
1441 case ARC_OPERAND_RB :
1442 value = fields->f_op_B;
1443 break;
1444 case ARC_OPERAND_RB_0 :
1445 value = fields->f_op_B;
1446 break;
1447 case ARC_OPERAND_RC :
1448 value = fields->f_op_C;
1449 break;
1450 case ARC_OPERAND_RC_ILINK :
1451 value = fields->f_op_Cj;
1452 break;
1453 case ARC_OPERAND_RC_NOILINK :
1454 value = fields->f_op_Cj;
1455 break;
1456 case ARC_OPERAND_R_A :
1457 value = fields->f_op__a;
1458 break;
1459 case ARC_OPERAND_R_B :
1460 value = fields->f_op__b;
1461 break;
1462 case ARC_OPERAND_R_C :
1463 value = fields->f_op__c;
1464 break;
1465 case ARC_OPERAND_RCC :
1466 value = fields->f_brcond;
1467 break;
1468 case ARC_OPERAND_RCCS :
1469 value = fields->f_brscond;
1470 break;
1471 case ARC_OPERAND_RH :
1472 value = fields->f_op_h;
1473 break;
1474 case ARC_OPERAND_SP :
1475 value = 0;
1476 break;
1477 case ARC_OPERAND_STODI :
1478 value = fields->f_STODi;
1479 break;
1480 case ARC_OPERAND_U6 :
1481 value = fields->f_u6;
1482 break;
1483 case ARC_OPERAND_U6X2 :
1484 value = fields->f_u6x2;
1485 break;
1486 case ARC_OPERAND__AW :
1487 value = 0;
1488 break;
1489 case ARC_OPERAND__L :
1490 value = 0;
1491 break;
1492 case ARC_OPERAND__S :
1493 value = 0;
1494 break;
1495 case ARC_OPERAND_CBIT :
1496 value = 0;
1497 break;
1498 case ARC_OPERAND_DELAY_N :
1499 value = fields->f_delay_N;
1500 break;
1501 case ARC_OPERAND_DUMMY_OP :
1502 value = fields->f_dummy;
1503 break;
1504 case ARC_OPERAND_I2COND :
1505 value = fields->f_cond_i2;
1506 break;
1507 case ARC_OPERAND_I3COND :
1508 value = fields->f_cond_i3;
1509 break;
1510 case ARC_OPERAND_LABEL10 :
1511 value = fields->f_rel10;
1512 break;
1513 case ARC_OPERAND_LABEL13A :
1514 value = fields->f_rel13bl;
1515 break;
1516 case ARC_OPERAND_LABEL21 :
1517 value = fields->f_rel21;
1518 break;
1519 case ARC_OPERAND_LABEL21A :
1520 value = fields->f_rel21bl;
1521 break;
1522 case ARC_OPERAND_LABEL25 :
1523 value = fields->f_rel25;
1524 break;
1525 case ARC_OPERAND_LABEL25A :
1526 value = fields->f_rel25bl;
1527 break;
1528 case ARC_OPERAND_LABEL7 :
1529 value = fields->f_rel7;
1530 break;
1531 case ARC_OPERAND_LABEL8 :
1532 value = fields->f_rel8;
1533 break;
1534 case ARC_OPERAND_LABEL9 :
1535 value = fields->f_rel9;
1536 break;
1537 case ARC_OPERAND_LBIT :
1538 value = 0;
1539 break;
1540 case ARC_OPERAND_NBIT :
1541 value = 0;
1542 break;
1543 case ARC_OPERAND_S12 :
1544 value = fields->f_s12;
1545 break;
1546 case ARC_OPERAND_S12X2 :
1547 value = fields->f_s12x2;
1548 break;
1549 case ARC_OPERAND_S1BIT :
1550 value = 0;
1551 break;
1552 case ARC_OPERAND_S2BIT :
1553 value = 0;
1554 break;
1555 case ARC_OPERAND_S9 :
1556 value = fields->f_s9;
1557 break;
1558 case ARC_OPERAND_S9X4 :
1559 value = fields->f_s9x4;
1560 break;
1561 case ARC_OPERAND_SC_S9_ :
1562 value = fields->f_s9x4;
1563 break;
1564 case ARC_OPERAND_SC_S9B :
1565 value = fields->f_s9x1;
1566 break;
1567 case ARC_OPERAND_SC_S9W :
1568 value = fields->f_s9x2;
1569 break;
1570 case ARC_OPERAND_SC_U5_ :
1571 value = fields->f_u5x4;
1572 break;
1573 case ARC_OPERAND_SC_U5B :
1574 value = fields->f_u5;
1575 break;
1576 case ARC_OPERAND_SC_U5W :
1577 value = fields->f_u5x2;
1578 break;
1579 case ARC_OPERAND_TRAPNUM :
1580 value = fields->f_trapnum;
1581 break;
1582 case ARC_OPERAND_U3 :
1583 value = fields->f_u3;
1584 break;
1585 case ARC_OPERAND_U5 :
1586 value = fields->f_u5;
1587 break;
1588 case ARC_OPERAND_U5X4 :
1589 value = fields->f_u5x4;
1590 break;
1591 case ARC_OPERAND_U7 :
1592 value = fields->f_u7;
1593 break;
1594 case ARC_OPERAND_U8 :
1595 value = fields->f_u8;
1596 break;
1597 case ARC_OPERAND_U8X4 :
1598 value = fields->f_u8x4;
1599 break;
1600 case ARC_OPERAND_UNCONDB :
1601 value = 0;
1602 break;
1603 case ARC_OPERAND_UNCONDI :
1604 value = 0;
1605 break;
1606 case ARC_OPERAND_UNCONDJ :
1607 value = 0;
1608 break;
1609 case ARC_OPERAND_VBIT :
1610 value = 0;
1611 break;
1612 case ARC_OPERAND_ZBIT :
1613 value = 0;
1614 break;
1615
1616 default :
1617 /* xgettext:c-format */
1618 fprintf (stderr, _("Unrecognized field %d while getting int operand.\n"),
1619 opindex);
1620 abort ();
1621 }
1622
1623 return value;
1624 }
1625
1626 bfd_vma
1627 arc_cgen_get_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
1628 int opindex,
1629 const CGEN_FIELDS * fields)
1630 {
1631 bfd_vma value;
1632
1633 switch (opindex)
1634 {
1635 case ARC_OPERAND_EXDI :
1636 value = fields->f_F;
1637 break;
1638 case ARC_OPERAND_F :
1639 value = fields->f_F;
1640 break;
1641 case ARC_OPERAND_F0 :
1642 value = fields->f_F;
1643 break;
1644 case ARC_OPERAND_F1 :
1645 value = fields->f_F;
1646 break;
1647 case ARC_OPERAND_F1F :
1648 value = fields->f_F;
1649 break;
1650 case ARC_OPERAND_GP :
1651 value = 0;
1652 break;
1653 case ARC_OPERAND_LDODI :
1654 value = fields->f_LDODi;
1655 break;
1656 case ARC_OPERAND_LDRDI :
1657 value = fields->f_LDRDi;
1658 break;
1659 case ARC_OPERAND_NE :
1660 value = 0;
1661 break;
1662 case ARC_OPERAND_PCL :
1663 value = 0;
1664 break;
1665 case ARC_OPERAND_QCONDB :
1666 value = fields->f_cond_Q;
1667 break;
1668 case ARC_OPERAND_QCONDI :
1669 value = fields->f_cond_Q;
1670 break;
1671 case ARC_OPERAND_QCONDJ :
1672 value = fields->f_cond_Q;
1673 break;
1674 case ARC_OPERAND_R0 :
1675 value = 0;
1676 break;
1677 case ARC_OPERAND_R31 :
1678 value = 0;
1679 break;
1680 case ARC_OPERAND_RA :
1681 value = fields->f_op_A;
1682 break;
1683 case ARC_OPERAND_RA_0 :
1684 value = fields->f_op_A;
1685 break;
1686 case ARC_OPERAND_RB :
1687 value = fields->f_op_B;
1688 break;
1689 case ARC_OPERAND_RB_0 :
1690 value = fields->f_op_B;
1691 break;
1692 case ARC_OPERAND_RC :
1693 value = fields->f_op_C;
1694 break;
1695 case ARC_OPERAND_RC_ILINK :
1696 value = fields->f_op_Cj;
1697 break;
1698 case ARC_OPERAND_RC_NOILINK :
1699 value = fields->f_op_Cj;
1700 break;
1701 case ARC_OPERAND_R_A :
1702 value = fields->f_op__a;
1703 break;
1704 case ARC_OPERAND_R_B :
1705 value = fields->f_op__b;
1706 break;
1707 case ARC_OPERAND_R_C :
1708 value = fields->f_op__c;
1709 break;
1710 case ARC_OPERAND_RCC :
1711 value = fields->f_brcond;
1712 break;
1713 case ARC_OPERAND_RCCS :
1714 value = fields->f_brscond;
1715 break;
1716 case ARC_OPERAND_RH :
1717 value = fields->f_op_h;
1718 break;
1719 case ARC_OPERAND_SP :
1720 value = 0;
1721 break;
1722 case ARC_OPERAND_STODI :
1723 value = fields->f_STODi;
1724 break;
1725 case ARC_OPERAND_U6 :
1726 value = fields->f_u6;
1727 break;
1728 case ARC_OPERAND_U6X2 :
1729 value = fields->f_u6x2;
1730 break;
1731 case ARC_OPERAND__AW :
1732 value = 0;
1733 break;
1734 case ARC_OPERAND__L :
1735 value = 0;
1736 break;
1737 case ARC_OPERAND__S :
1738 value = 0;
1739 break;
1740 case ARC_OPERAND_CBIT :
1741 value = 0;
1742 break;
1743 case ARC_OPERAND_DELAY_N :
1744 value = fields->f_delay_N;
1745 break;
1746 case ARC_OPERAND_DUMMY_OP :
1747 value = fields->f_dummy;
1748 break;
1749 case ARC_OPERAND_I2COND :
1750 value = fields->f_cond_i2;
1751 break;
1752 case ARC_OPERAND_I3COND :
1753 value = fields->f_cond_i3;
1754 break;
1755 case ARC_OPERAND_LABEL10 :
1756 value = fields->f_rel10;
1757 break;
1758 case ARC_OPERAND_LABEL13A :
1759 value = fields->f_rel13bl;
1760 break;
1761 case ARC_OPERAND_LABEL21 :
1762 value = fields->f_rel21;
1763 break;
1764 case ARC_OPERAND_LABEL21A :
1765 value = fields->f_rel21bl;
1766 break;
1767 case ARC_OPERAND_LABEL25 :
1768 value = fields->f_rel25;
1769 break;
1770 case ARC_OPERAND_LABEL25A :
1771 value = fields->f_rel25bl;
1772 break;
1773 case ARC_OPERAND_LABEL7 :
1774 value = fields->f_rel7;
1775 break;
1776 case ARC_OPERAND_LABEL8 :
1777 value = fields->f_rel8;
1778 break;
1779 case ARC_OPERAND_LABEL9 :
1780 value = fields->f_rel9;
1781 break;
1782 case ARC_OPERAND_LBIT :
1783 value = 0;
1784 break;
1785 case ARC_OPERAND_NBIT :
1786 value = 0;
1787 break;
1788 case ARC_OPERAND_S12 :
1789 value = fields->f_s12;
1790 break;
1791 case ARC_OPERAND_S12X2 :
1792 value = fields->f_s12x2;
1793 break;
1794 case ARC_OPERAND_S1BIT :
1795 value = 0;
1796 break;
1797 case ARC_OPERAND_S2BIT :
1798 value = 0;
1799 break;
1800 case ARC_OPERAND_S9 :
1801 value = fields->f_s9;
1802 break;
1803 case ARC_OPERAND_S9X4 :
1804 value = fields->f_s9x4;
1805 break;
1806 case ARC_OPERAND_SC_S9_ :
1807 value = fields->f_s9x4;
1808 break;
1809 case ARC_OPERAND_SC_S9B :
1810 value = fields->f_s9x1;
1811 break;
1812 case ARC_OPERAND_SC_S9W :
1813 value = fields->f_s9x2;
1814 break;
1815 case ARC_OPERAND_SC_U5_ :
1816 value = fields->f_u5x4;
1817 break;
1818 case ARC_OPERAND_SC_U5B :
1819 value = fields->f_u5;
1820 break;
1821 case ARC_OPERAND_SC_U5W :
1822 value = fields->f_u5x2;
1823 break;
1824 case ARC_OPERAND_TRAPNUM :
1825 value = fields->f_trapnum;
1826 break;
1827 case ARC_OPERAND_U3 :
1828 value = fields->f_u3;
1829 break;
1830 case ARC_OPERAND_U5 :
1831 value = fields->f_u5;
1832 break;
1833 case ARC_OPERAND_U5X4 :
1834 value = fields->f_u5x4;
1835 break;
1836 case ARC_OPERAND_U7 :
1837 value = fields->f_u7;
1838 break;
1839 case ARC_OPERAND_U8 :
1840 value = fields->f_u8;
1841 break;
1842 case ARC_OPERAND_U8X4 :
1843 value = fields->f_u8x4;
1844 break;
1845 case ARC_OPERAND_UNCONDB :
1846 value = 0;
1847 break;
1848 case ARC_OPERAND_UNCONDI :
1849 value = 0;
1850 break;
1851 case ARC_OPERAND_UNCONDJ :
1852 value = 0;
1853 break;
1854 case ARC_OPERAND_VBIT :
1855 value = 0;
1856 break;
1857 case ARC_OPERAND_ZBIT :
1858 value = 0;
1859 break;
1860
1861 default :
1862 /* xgettext:c-format */
1863 fprintf (stderr, _("Unrecognized field %d while getting vma operand.\n"),
1864 opindex);
1865 abort ();
1866 }
1867
1868 return value;
1869 }
1870
1871 void arc_cgen_set_int_operand (CGEN_CPU_DESC, int, CGEN_FIELDS *, int);
1872 void arc_cgen_set_vma_operand (CGEN_CPU_DESC, int, CGEN_FIELDS *, bfd_vma);
1873
1874 /* Stuffing values in cgen_fields is handled by a collection of functions.
1875 They are distinguished by the type of the VALUE argument they accept.
1876 TODO: floating point, inlining support, remove cases where argument type
1877 not appropriate. */
1878
1879 void
1880 arc_cgen_set_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
1881 int opindex,
1882 CGEN_FIELDS * fields,
1883 int value)
1884 {
1885 switch (opindex)
1886 {
1887 case ARC_OPERAND_EXDI :
1888 fields->f_F = value;
1889 break;
1890 case ARC_OPERAND_F :
1891 fields->f_F = value;
1892 break;
1893 case ARC_OPERAND_F0 :
1894 fields->f_F = value;
1895 break;
1896 case ARC_OPERAND_F1 :
1897 fields->f_F = value;
1898 break;
1899 case ARC_OPERAND_F1F :
1900 fields->f_F = value;
1901 break;
1902 case ARC_OPERAND_GP :
1903 break;
1904 case ARC_OPERAND_LDODI :
1905 fields->f_LDODi = value;
1906 break;
1907 case ARC_OPERAND_LDRDI :
1908 fields->f_LDRDi = value;
1909 break;
1910 case ARC_OPERAND_NE :
1911 break;
1912 case ARC_OPERAND_PCL :
1913 break;
1914 case ARC_OPERAND_QCONDB :
1915 fields->f_cond_Q = value;
1916 break;
1917 case ARC_OPERAND_QCONDI :
1918 fields->f_cond_Q = value;
1919 break;
1920 case ARC_OPERAND_QCONDJ :
1921 fields->f_cond_Q = value;
1922 break;
1923 case ARC_OPERAND_R0 :
1924 break;
1925 case ARC_OPERAND_R31 :
1926 break;
1927 case ARC_OPERAND_RA :
1928 fields->f_op_A = value;
1929 break;
1930 case ARC_OPERAND_RA_0 :
1931 fields->f_op_A = value;
1932 break;
1933 case ARC_OPERAND_RB :
1934 fields->f_op_B = value;
1935 break;
1936 case ARC_OPERAND_RB_0 :
1937 fields->f_op_B = value;
1938 break;
1939 case ARC_OPERAND_RC :
1940 fields->f_op_C = value;
1941 break;
1942 case ARC_OPERAND_RC_ILINK :
1943 fields->f_op_Cj = value;
1944 break;
1945 case ARC_OPERAND_RC_NOILINK :
1946 fields->f_op_Cj = value;
1947 break;
1948 case ARC_OPERAND_R_A :
1949 fields->f_op__a = value;
1950 break;
1951 case ARC_OPERAND_R_B :
1952 fields->f_op__b = value;
1953 break;
1954 case ARC_OPERAND_R_C :
1955 fields->f_op__c = value;
1956 break;
1957 case ARC_OPERAND_RCC :
1958 fields->f_brcond = value;
1959 break;
1960 case ARC_OPERAND_RCCS :
1961 fields->f_brscond = value;
1962 break;
1963 case ARC_OPERAND_RH :
1964 fields->f_op_h = value;
1965 break;
1966 case ARC_OPERAND_SP :
1967 break;
1968 case ARC_OPERAND_STODI :
1969 fields->f_STODi = value;
1970 break;
1971 case ARC_OPERAND_U6 :
1972 fields->f_u6 = value;
1973 break;
1974 case ARC_OPERAND_U6X2 :
1975 fields->f_u6x2 = value;
1976 break;
1977 case ARC_OPERAND__AW :
1978 break;
1979 case ARC_OPERAND__L :
1980 break;
1981 case ARC_OPERAND__S :
1982 break;
1983 case ARC_OPERAND_CBIT :
1984 break;
1985 case ARC_OPERAND_DELAY_N :
1986 fields->f_delay_N = value;
1987 break;
1988 case ARC_OPERAND_DUMMY_OP :
1989 fields->f_dummy = value;
1990 break;
1991 case ARC_OPERAND_I2COND :
1992 fields->f_cond_i2 = value;
1993 break;
1994 case ARC_OPERAND_I3COND :
1995 fields->f_cond_i3 = value;
1996 break;
1997 case ARC_OPERAND_LABEL10 :
1998 fields->f_rel10 = value;
1999 break;
2000 case ARC_OPERAND_LABEL13A :
2001 fields->f_rel13bl = value;
2002 break;
2003 case ARC_OPERAND_LABEL21 :
2004 fields->f_rel21 = value;
2005 break;
2006 case ARC_OPERAND_LABEL21A :
2007 fields->f_rel21bl = value;
2008 break;
2009 case ARC_OPERAND_LABEL25 :
2010 fields->f_rel25 = value;
2011 break;
2012 case ARC_OPERAND_LABEL25A :
2013 fields->f_rel25bl = value;
2014 break;
2015 case ARC_OPERAND_LABEL7 :
2016 fields->f_rel7 = value;
2017 break;
2018 case ARC_OPERAND_LABEL8 :
2019 fields->f_rel8 = value;
2020 break;
2021 case ARC_OPERAND_LABEL9 :
2022 fields->f_rel9 = value;
2023 break;
2024 case ARC_OPERAND_LBIT :
2025 break;
2026 case ARC_OPERAND_NBIT :
2027 break;
2028 case ARC_OPERAND_S12 :
2029 fields->f_s12 = value;
2030 break;
2031 case ARC_OPERAND_S12X2 :
2032 fields->f_s12x2 = value;
2033 break;
2034 case ARC_OPERAND_S1BIT :
2035 break;
2036 case ARC_OPERAND_S2BIT :
2037 break;
2038 case ARC_OPERAND_S9 :
2039 fields->f_s9 = value;
2040 break;
2041 case ARC_OPERAND_S9X4 :
2042 fields->f_s9x4 = value;
2043 break;
2044 case ARC_OPERAND_SC_S9_ :
2045 fields->f_s9x4 = value;
2046 break;
2047 case ARC_OPERAND_SC_S9B :
2048 fields->f_s9x1 = value;
2049 break;
2050 case ARC_OPERAND_SC_S9W :
2051 fields->f_s9x2 = value;
2052 break;
2053 case ARC_OPERAND_SC_U5_ :
2054 fields->f_u5x4 = value;
2055 break;
2056 case ARC_OPERAND_SC_U5B :
2057 fields->f_u5 = value;
2058 break;
2059 case ARC_OPERAND_SC_U5W :
2060 fields->f_u5x2 = value;
2061 break;
2062 case ARC_OPERAND_TRAPNUM :
2063 fields->f_trapnum = value;
2064 break;
2065 case ARC_OPERAND_U3 :
2066 fields->f_u3 = value;
2067 break;
2068 case ARC_OPERAND_U5 :
2069 fields->f_u5 = value;
2070 break;
2071 case ARC_OPERAND_U5X4 :
2072 fields->f_u5x4 = value;
2073 break;
2074 case ARC_OPERAND_U7 :
2075 fields->f_u7 = value;
2076 break;
2077 case ARC_OPERAND_U8 :
2078 fields->f_u8 = value;
2079 break;
2080 case ARC_OPERAND_U8X4 :
2081 fields->f_u8x4 = value;
2082 break;
2083 case ARC_OPERAND_UNCONDB :
2084 break;
2085 case ARC_OPERAND_UNCONDI :
2086 break;
2087 case ARC_OPERAND_UNCONDJ :
2088 break;
2089 case ARC_OPERAND_VBIT :
2090 break;
2091 case ARC_OPERAND_ZBIT :
2092 break;
2093
2094 default :
2095 /* xgettext:c-format */
2096 fprintf (stderr, _("Unrecognized field %d while setting int operand.\n"),
2097 opindex);
2098 abort ();
2099 }
2100 }
2101
2102 void
2103 arc_cgen_set_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
2104 int opindex,
2105 CGEN_FIELDS * fields,
2106 bfd_vma value)
2107 {
2108 switch (opindex)
2109 {
2110 case ARC_OPERAND_EXDI :
2111 fields->f_F = value;
2112 break;
2113 case ARC_OPERAND_F :
2114 fields->f_F = value;
2115 break;
2116 case ARC_OPERAND_F0 :
2117 fields->f_F = value;
2118 break;
2119 case ARC_OPERAND_F1 :
2120 fields->f_F = value;
2121 break;
2122 case ARC_OPERAND_F1F :
2123 fields->f_F = value;
2124 break;
2125 case ARC_OPERAND_GP :
2126 break;
2127 case ARC_OPERAND_LDODI :
2128 fields->f_LDODi = value;
2129 break;
2130 case ARC_OPERAND_LDRDI :
2131 fields->f_LDRDi = value;
2132 break;
2133 case ARC_OPERAND_NE :
2134 break;
2135 case ARC_OPERAND_PCL :
2136 break;
2137 case ARC_OPERAND_QCONDB :
2138 fields->f_cond_Q = value;
2139 break;
2140 case ARC_OPERAND_QCONDI :
2141 fields->f_cond_Q = value;
2142 break;
2143 case ARC_OPERAND_QCONDJ :
2144 fields->f_cond_Q = value;
2145 break;
2146 case ARC_OPERAND_R0 :
2147 break;
2148 case ARC_OPERAND_R31 :
2149 break;
2150 case ARC_OPERAND_RA :
2151 fields->f_op_A = value;
2152 break;
2153 case ARC_OPERAND_RA_0 :
2154 fields->f_op_A = value;
2155 break;
2156 case ARC_OPERAND_RB :
2157 fields->f_op_B = value;
2158 break;
2159 case ARC_OPERAND_RB_0 :
2160 fields->f_op_B = value;
2161 break;
2162 case ARC_OPERAND_RC :
2163 fields->f_op_C = value;
2164 break;
2165 case ARC_OPERAND_RC_ILINK :
2166 fields->f_op_Cj = value;
2167 break;
2168 case ARC_OPERAND_RC_NOILINK :
2169 fields->f_op_Cj = value;
2170 break;
2171 case ARC_OPERAND_R_A :
2172 fields->f_op__a = value;
2173 break;
2174 case ARC_OPERAND_R_B :
2175 fields->f_op__b = value;
2176 break;
2177 case ARC_OPERAND_R_C :
2178 fields->f_op__c = value;
2179 break;
2180 case ARC_OPERAND_RCC :
2181 fields->f_brcond = value;
2182 break;
2183 case ARC_OPERAND_RCCS :
2184 fields->f_brscond = value;
2185 break;
2186 case ARC_OPERAND_RH :
2187 fields->f_op_h = value;
2188 break;
2189 case ARC_OPERAND_SP :
2190 break;
2191 case ARC_OPERAND_STODI :
2192 fields->f_STODi = value;
2193 break;
2194 case ARC_OPERAND_U6 :
2195 fields->f_u6 = value;
2196 break;
2197 case ARC_OPERAND_U6X2 :
2198 fields->f_u6x2 = value;
2199 break;
2200 case ARC_OPERAND__AW :
2201 break;
2202 case ARC_OPERAND__L :
2203 break;
2204 case ARC_OPERAND__S :
2205 break;
2206 case ARC_OPERAND_CBIT :
2207 break;
2208 case ARC_OPERAND_DELAY_N :
2209 fields->f_delay_N = value;
2210 break;
2211 case ARC_OPERAND_DUMMY_OP :
2212 fields->f_dummy = value;
2213 break;
2214 case ARC_OPERAND_I2COND :
2215 fields->f_cond_i2 = value;
2216 break;
2217 case ARC_OPERAND_I3COND :
2218 fields->f_cond_i3 = value;
2219 break;
2220 case ARC_OPERAND_LABEL10 :
2221 fields->f_rel10 = value;
2222 break;
2223 case ARC_OPERAND_LABEL13A :
2224 fields->f_rel13bl = value;
2225 break;
2226 case ARC_OPERAND_LABEL21 :
2227 fields->f_rel21 = value;
2228 break;
2229 case ARC_OPERAND_LABEL21A :
2230 fields->f_rel21bl = value;
2231 break;
2232 case ARC_OPERAND_LABEL25 :
2233 fields->f_rel25 = value;
2234 break;
2235 case ARC_OPERAND_LABEL25A :
2236 fields->f_rel25bl = value;
2237 break;
2238 case ARC_OPERAND_LABEL7 :
2239 fields->f_rel7 = value;
2240 break;
2241 case ARC_OPERAND_LABEL8 :
2242 fields->f_rel8 = value;
2243 break;
2244 case ARC_OPERAND_LABEL9 :
2245 fields->f_rel9 = value;
2246 break;
2247 case ARC_OPERAND_LBIT :
2248 break;
2249 case ARC_OPERAND_NBIT :
2250 break;
2251 case ARC_OPERAND_S12 :
2252 fields->f_s12 = value;
2253 break;
2254 case ARC_OPERAND_S12X2 :
2255 fields->f_s12x2 = value;
2256 break;
2257 case ARC_OPERAND_S1BIT :
2258 break;
2259 case ARC_OPERAND_S2BIT :
2260 break;
2261 case ARC_OPERAND_S9 :
2262 fields->f_s9 = value;
2263 break;
2264 case ARC_OPERAND_S9X4 :
2265 fields->f_s9x4 = value;
2266 break;
2267 case ARC_OPERAND_SC_S9_ :
2268 fields->f_s9x4 = value;
2269 break;
2270 case ARC_OPERAND_SC_S9B :
2271 fields->f_s9x1 = value;
2272 break;
2273 case ARC_OPERAND_SC_S9W :
2274 fields->f_s9x2 = value;
2275 break;
2276 case ARC_OPERAND_SC_U5_ :
2277 fields->f_u5x4 = value;
2278 break;
2279 case ARC_OPERAND_SC_U5B :
2280 fields->f_u5 = value;
2281 break;
2282 case ARC_OPERAND_SC_U5W :
2283 fields->f_u5x2 = value;
2284 break;
2285 case ARC_OPERAND_TRAPNUM :
2286 fields->f_trapnum = value;
2287 break;
2288 case ARC_OPERAND_U3 :
2289 fields->f_u3 = value;
2290 break;
2291 case ARC_OPERAND_U5 :
2292 fields->f_u5 = value;
2293 break;
2294 case ARC_OPERAND_U5X4 :
2295 fields->f_u5x4 = value;
2296 break;
2297 case ARC_OPERAND_U7 :
2298 fields->f_u7 = value;
2299 break;
2300 case ARC_OPERAND_U8 :
2301 fields->f_u8 = value;
2302 break;
2303 case ARC_OPERAND_U8X4 :
2304 fields->f_u8x4 = value;
2305 break;
2306 case ARC_OPERAND_UNCONDB :
2307 break;
2308 case ARC_OPERAND_UNCONDI :
2309 break;
2310 case ARC_OPERAND_UNCONDJ :
2311 break;
2312 case ARC_OPERAND_VBIT :
2313 break;
2314 case ARC_OPERAND_ZBIT :
2315 break;
2316
2317 default :
2318 /* xgettext:c-format */
2319 fprintf (stderr, _("Unrecognized field %d while setting vma operand.\n"),
2320 opindex);
2321 abort ();
2322 }
2323 }
2324
2325 /* Function to call before using the instruction builder tables. */
2326
2327 void
2328 arc_cgen_init_ibld_table (CGEN_CPU_DESC cd)
2329 {
2330 cd->insert_handlers = & arc_cgen_insert_handlers[0];
2331 cd->extract_handlers = & arc_cgen_extract_handlers[0];
2332
2333 cd->insert_operand = arc_cgen_insert_operand;
2334 cd->extract_operand = arc_cgen_extract_operand;
2335
2336 cd->get_int_operand = arc_cgen_get_int_operand;
2337 cd->set_int_operand = arc_cgen_set_int_operand;
2338 cd->get_vma_operand = arc_cgen_get_vma_operand;
2339 cd->set_vma_operand = arc_cgen_set_vma_operand;
2340 }