cpu/stack16.cc

   1 /////////////////////////////////////////////////////////////////////////
   2 // $Id: stack16.cc,v 1.43 2008/08/27 21:57:40 sshwarts Exp $
   3 /////////////////////////////////////////////////////////////////////////
   4 //
   5 //  Copyright (C) 2001  MandrakeSoft S.A.
   6 //
   7 //    MandrakeSoft S.A.
   8 //    43, rue d'Aboukir
   9 //    75002 Paris - France
  10 //    http://www.linux-mandrake.com/
  11 //    http://www.mandrakesoft.com/
  12 //
  13 //  This library is free software; you can redistribute it and/or
  14 //  modify it under the terms of the GNU Lesser General Public
  15 //  License as published by the Free Software Foundation; either
  16 //  version 2 of the License, or (at your option) any later version.
  17 //
  18 //  This library is distributed in the hope that it will be useful,
  19 //  but WITHOUT ANY WARRANTY; without even the implied warranty of
  20 //  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  21 //  Lesser General Public License for more details.
  22 //
  23 //  You should have received a copy of the GNU Lesser General Public
  24 //  License along with this library; if not, write to the Free Software
  25 //  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  26 /////////////////////////////////////////////////////////////////////////
  27
  28 #define NEED_CPU_REG_SHORTCUTS 1
  29 #include "bochs.h"
  30 #include "cpu.h"
  31 #define LOG_THIS BX_CPU_THIS_PTR
  32
  33 // Make code more tidy with a few macros.
  34 #if BX_SUPPORT_X86_64==0
  35 #define RSP ESP
  36 #endif
  37
  38 void BX_CPP_AttrRegparmN(1) BX_CPU_C::PUSH_RX(bxInstruction_c *i)
  39 {
  40   push_16(BX_READ_16BIT_REG(i->opcodeReg()));
  41 }
  42
  43 void BX_CPP_AttrRegparmN(1) BX_CPU_C::PUSH16_CS(bxInstruction_c *i)
  44 {
  45   push_16(BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value);
  46 }
  47
  48 void BX_CPP_AttrRegparmN(1) BX_CPU_C::PUSH16_DS(bxInstruction_c *i)
  49 {
  50   push_16(BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS].selector.value);
  51 }
  52
  53 void BX_CPP_AttrRegparmN(1) BX_CPU_C::PUSH16_ES(bxInstruction_c *i)
  54 {
  55   push_16(BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES].selector.value);
  56 }
  57
  58 void BX_CPP_AttrRegparmN(1) BX_CPU_C::PUSH16_FS(bxInstruction_c *i)
  59 {
  60   push_16(BX_CPU_THIS_PTR sregs[BX_SEG_REG_FS].selector.value);
  61 }
  62
  63 void BX_CPP_AttrRegparmN(1) BX_CPU_C::PUSH16_GS(bxInstruction_c *i)
  64 {
  65   push_16(BX_CPU_THIS_PTR sregs[BX_SEG_REG_GS].selector.value);
  66 }
  67
  68 void BX_CPP_AttrRegparmN(1) BX_CPU_C::PUSH16_SS(bxInstruction_c *i)
  69 {
  70   push_16(BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].selector.value);
  71 }
  72
  73 void BX_CPP_AttrRegparmN(1) BX_CPU_C::POP16_DS(bxInstruction_c *i)
  74 {
  75   BX_CPU_THIS_PTR speculative_rsp = 1;
  76   BX_CPU_THIS_PTR prev_rsp = RSP;
  77
  78   Bit16u ds = pop_16();
  79   load_seg_reg(&BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS], ds);
  80
  81   BX_CPU_THIS_PTR speculative_rsp = 0;
  82 }
  83
  84 void BX_CPP_AttrRegparmN(1) BX_CPU_C::POP16_ES(bxInstruction_c *i)
  85 {
  86   BX_CPU_THIS_PTR speculative_rsp = 1;
  87   BX_CPU_THIS_PTR prev_rsp = RSP;
  88
  89   Bit16u es = pop_16();
  90   load_seg_reg(&BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES], es);
  91
  92   BX_CPU_THIS_PTR speculative_rsp = 0;
  93 }
  94
  95 void BX_CPP_AttrRegparmN(1) BX_CPU_C::POP16_FS(bxInstruction_c *i)
  96 {
  97   BX_CPU_THIS_PTR speculative_rsp = 1;
  98   BX_CPU_THIS_PTR prev_rsp = RSP;
  99
 100   Bit16u fs = pop_16();
 101   load_seg_reg(&BX_CPU_THIS_PTR sregs[BX_SEG_REG_FS], fs);
 102
 103   BX_CPU_THIS_PTR speculative_rsp = 0;
 104 }
 105
 106 void BX_CPP_AttrRegparmN(1) BX_CPU_C::POP16_GS(bxInstruction_c *i)
 107 {
 108   BX_CPU_THIS_PTR speculative_rsp = 1;
 109   BX_CPU_THIS_PTR prev_rsp = RSP;
 110
 111   Bit16u gs = pop_16();
 112   load_seg_reg(&BX_CPU_THIS_PTR sregs[BX_SEG_REG_GS], gs);
 113
 114   BX_CPU_THIS_PTR speculative_rsp = 0;
 115 }
 116
 117 void BX_CPP_AttrRegparmN(1) BX_CPU_C::POP16_SS(bxInstruction_c *i)
 118 {
 119   BX_CPU_THIS_PTR speculative_rsp = 1;
 120   BX_CPU_THIS_PTR prev_rsp = RSP;
 121
 122   Bit16u ss = pop_16();
 123   load_seg_reg(&BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS], ss);
 124
 125   BX_CPU_THIS_PTR speculative_rsp = 0;
 126
 127   // POP SS inhibits interrupts, debug exceptions and single-step
 128   // trap exceptions until the execution boundary following the
 129   // next instruction is reached.
 130   // Same code as MOV_SwEw()
 131   BX_CPU_THIS_PTR inhibit_mask |=
 132     BX_INHIBIT_INTERRUPTS | BX_INHIBIT_DEBUG;
 133   BX_CPU_THIS_PTR async_event = 1;
 134 }
 135
 136 void BX_CPP_AttrRegparmN(1) BX_CPU_C::POP_RX(bxInstruction_c *i)
 137 {
 138   BX_WRITE_16BIT_REG(i->opcodeReg(), pop_16());
 139 }
 140
 141 void BX_CPP_AttrRegparmN(1) BX_CPU_C::POP_EwM(bxInstruction_c *i)
 142 {
 143   BX_CPU_THIS_PTR speculative_rsp = 1;
 144   BX_CPU_THIS_PTR prev_rsp = RSP;
 145
 146   Bit16u val16 = pop_16();
 147
 148   // Note: there is one little weirdism here.  It is possible to use
 149   // SP in the modrm addressing. If used, the value of SP after the
 150   // pop is used to calculate the address.
 151   bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
 152
 153   write_virtual_word(i->seg(), eaddr, val16);
 154
 155   BX_CPU_THIS_PTR speculative_rsp = 0;
 156 }
 157
 158 void BX_CPP_AttrRegparmN(1) BX_CPU_C::PUSH_Iw(bxInstruction_c *i)
 159 {
 160   push_16(i->Iw());
 161 }
 162
 163 void BX_CPP_AttrRegparmN(1) BX_CPU_C::PUSH_EwM(bxInstruction_c *i)
 164 {
 165   bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
 166
 167   Bit16u op1_16 = read_virtual_word(i->seg(), eaddr);
 168
 169   push_16(op1_16);
 170 }
 171
 172 void BX_CPP_AttrRegparmN(1) BX_CPU_C::PUSHAD16(bxInstruction_c *i)
 173 {
 174   Bit32u temp_ESP = ESP;
 175   Bit16u temp_SP  = SP;
 176
 177   if (BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.d_b)
 178   {
 179     write_virtual_word_32(BX_SEG_REG_SS, (Bit32u)(temp_ESP -  2), AX);
 180     write_virtual_word_32(BX_SEG_REG_SS, (Bit32u)(temp_ESP -  4), CX);
 181     write_virtual_word_32(BX_SEG_REG_SS, (Bit32u)(temp_ESP -  6), DX);
 182     write_virtual_word_32(BX_SEG_REG_SS, (Bit32u)(temp_ESP -  8), BX);
 183     write_virtual_word_32(BX_SEG_REG_SS, (Bit32u)(temp_ESP - 10), temp_SP);
 184     write_virtual_word_32(BX_SEG_REG_SS, (Bit32u)(temp_ESP - 12), BP);
 185     write_virtual_word_32(BX_SEG_REG_SS, (Bit32u)(temp_ESP - 14), SI);
 186     write_virtual_word_32(BX_SEG_REG_SS, (Bit32u)(temp_ESP - 16), DI);
 187     ESP -= 16;
 188   }
 189   else
 190   {
 191     write_virtual_word_32(BX_SEG_REG_SS, (Bit16u)(temp_SP -  2), AX);
 192     write_virtual_word_32(BX_SEG_REG_SS, (Bit16u)(temp_SP -  4), CX);
 193     write_virtual_word_32(BX_SEG_REG_SS, (Bit16u)(temp_SP -  6), DX);
 194     write_virtual_word_32(BX_SEG_REG_SS, (Bit16u)(temp_SP -  8), BX);
 195     write_virtual_word_32(BX_SEG_REG_SS, (Bit16u)(temp_SP - 10), temp_SP);
 196     write_virtual_word_32(BX_SEG_REG_SS, (Bit16u)(temp_SP - 12), BP);
 197     write_virtual_word_32(BX_SEG_REG_SS, (Bit16u)(temp_SP - 14), SI);
 198     write_virtual_word_32(BX_SEG_REG_SS, (Bit16u)(temp_SP - 16), DI);
 199     SP -= 16;
 200   }
 201 }
 202
 203 void BX_CPP_AttrRegparmN(1) BX_CPU_C::POPAD16(bxInstruction_c *i)
 204 {
 205   Bit16u di, si, bp, bx, dx, cx, ax, dummy;
 206
 207   if (BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.d_b)
 208   {
 209     Bit32u temp_ESP = ESP;
 210     di = read_virtual_word_32(BX_SEG_REG_SS, (Bit32u)(temp_ESP +  0));
 211     si = read_virtual_word_32(BX_SEG_REG_SS, (Bit32u)(temp_ESP +  2));
 212     bp = read_virtual_word_32(BX_SEG_REG_SS, (Bit32u)(temp_ESP +  4));
 213     dummy = read_virtual_word_32(BX_SEG_REG_SS, (Bit32u)(temp_ESP +  6));
 214     bx = read_virtual_word_32(BX_SEG_REG_SS, (Bit32u)(temp_ESP +  8));
 215     dx = read_virtual_word_32(BX_SEG_REG_SS, (Bit32u)(temp_ESP + 10));
 216     cx = read_virtual_word_32(BX_SEG_REG_SS, (Bit32u)(temp_ESP + 12));
 217     ax = read_virtual_word_32(BX_SEG_REG_SS, (Bit32u)(temp_ESP + 14));
 218     ESP += 16;
 219   }
 220   else
 221   {
 222     Bit16u temp_SP = SP;
 223     di = read_virtual_word_32(BX_SEG_REG_SS, (Bit16u)(temp_SP +  0));
 224     si = read_virtual_word_32(BX_SEG_REG_SS, (Bit16u)(temp_SP +  2));
 225     bp = read_virtual_word_32(BX_SEG_REG_SS, (Bit16u)(temp_SP +  4));
 226     dummy = read_virtual_word_32(BX_SEG_REG_SS, (Bit16u)(temp_SP +  6));
 227     bx = read_virtual_word_32(BX_SEG_REG_SS, (Bit16u)(temp_SP +  8));
 228     dx = read_virtual_word_32(BX_SEG_REG_SS, (Bit16u)(temp_SP + 10));
 229     cx = read_virtual_word_32(BX_SEG_REG_SS, (Bit16u)(temp_SP + 12));
 230     ax = read_virtual_word_32(BX_SEG_REG_SS, (Bit16u)(temp_SP + 14));
 231     SP += 16;
 232   }
 233
 234   DI = di;
 235   SI = si;
 236   BP = bp;
 237   BX = bx;
 238   DX = dx;
 239   CX = cx;
 240   AX = ax;
 241 }
 242
 243 void BX_CPP_AttrRegparmN(1) BX_CPU_C::ENTER16_IwIb(bxInstruction_c *i)
 244 {
 245   Bit16u imm16 = i->Iw();
 246   Bit8u level = i->Ib2();
 247   level &= 0x1F;
 248
 249   BX_CPU_THIS_PTR speculative_rsp = 1;
 250   BX_CPU_THIS_PTR prev_rsp = RSP;
 251
 252   push_16(BP);
 253   Bit16u frame_ptr16 = SP;
 254
 255   if (BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.d_b) {
 256     Bit32u ebp = EBP; // Use temp copy for case of exception.
 257
 258     if (level > 0) {
 259       /* do level-1 times */
 260       while (--level) {
 261         ebp -= 2;
 262         Bit16u temp16 = read_virtual_word_32(BX_SEG_REG_SS, ebp);
 263         push_16(temp16);
 264       }
 265
 266       /* push(frame pointer) */
 267       push_16(frame_ptr16);
 268     }
 269
 270     ESP -= imm16;
 271
 272     // ENTER finishes with memory write check on the final stack pointer
 273     // the memory is touched but no write actually occurs
 274     // emulate it by doing RMW read access from SS:ESP
 275     read_RMW_virtual_word(BX_SEG_REG_SS, ESP);
 276
 277     BP = frame_ptr16;
 278   }
 279   else {
 280     Bit16u bp = BP;
 281
 282     if (level > 0) {
 283       /* do level-1 times */
 284       while (--level) {
 285         bp -= 2;
 286         Bit16u temp16 = read_virtual_word_32(BX_SEG_REG_SS, bp);
 287         push_16(temp16);
 288       }
 289
 290       /* push(frame pointer) */
 291       push_16(frame_ptr16);
 292     }
 293
 294     SP -= imm16;
 295
 296     // ENTER finishes with memory write check on the final stack pointer
 297     // the memory is touched but no write actually occurs
 298     // emulate it by doing RMW read access from SS:SP
 299     read_RMW_virtual_word_32(BX_SEG_REG_SS, SP);
 300   }
 301
 302   BP = frame_ptr16;
 303
 304   BX_CPU_THIS_PTR speculative_rsp = 0;
 305 }
 306
 307 void BX_CPP_AttrRegparmN(1) BX_CPU_C::LEAVE16(bxInstruction_c *i)
 308 {
 309   BX_ASSERT(BX_CPU_THIS_PTR cpu_mode != BX_MODE_LONG_64);
 310
 311   Bit16u value16;
 312
 313   if (BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.d_b) {
 314     value16 = read_virtual_word_32(BX_SEG_REG_SS, EBP);
 315     ESP = EBP + 2;
 316   }
 317   else {
 318     value16 = read_virtual_word_32(BX_SEG_REG_SS, BP);
 319     SP = BP + 2;
 320   }
 321
 322   BP = value16;
 323 }