cpu/apic.h

   1 /////////////////////////////////////////////////////////////////////////
   2 // $Id: apic.h,v 1.38 2008/06/17 21:21:17 sshwarts Exp $
   3 /////////////////////////////////////////////////////////////////////////
   4 //
   5 //  Copyright (c) 2002 Zwane Mwaikambo, Stanislav Shwartsman
   6 //
   7 //  This library is free software; you can redistribute it and/or
   8 //  modify it under the terms of the GNU Lesser General Public
   9 //  License as published by the Free Software Foundation; either
  10 //  version 2 of the License, or (at your option) any later version.
  11 //
  12 //  This library is distributed in the hope that it will be useful,
  13 //  but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 //  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15 //  Lesser General Public License for more details.
  16 //
  17 //  You should have received a copy of the GNU Lesser General Public
  18 //  License along with this library; if not, write to the Free Software
  19 //  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  20 //
  21 /////////////////////////////////////////////////////////////////////////
  22
  23 #ifndef BX_CPU_APIC_H
  24 #  define BX_CPU_APIC_H 1
  25
  26 #if BX_CPU_LEVEL == 6 && BX_SUPPORT_SSE >= 2
  27   #define BX_IMPLEMENT_XAPIC 1
  28 #endif
  29
  30 #if BX_SUPPORT_APIC
  31
  32 #define APIC_LEVEL_TRIGGERED    1
  33 #define APIC_EDGE_TRIGGERED     0
  34
  35 class BOCHSAPI bx_generic_apic_c : public logfunctions {
  36 protected:
  37   bx_phy_address base_addr;
  38   Bit8u id;
  39 #define APIC_UNKNOWN_ID 0xff
  40 public:
  41   bx_generic_apic_c(bx_phy_address base);
  42   virtual ~bx_generic_apic_c() { }
  43   // init is called during RESET and when an INIT message is delivered
  44   virtual void init() { }
  45   virtual void reset(unsigned type) {}
  46   bx_phy_address get_base(void) const { return base_addr; }
  47   void set_base(bx_phy_address newbase);
  48   void set_id(Bit8u newid);
  49   Bit8u get_id() const { return id; }
  50   bx_bool is_selected(bx_phy_address addr, unsigned len);
  51   void read(bx_phy_address addr, void *data, unsigned len);
  52   virtual void read_aligned(bx_phy_address address, Bit32u *data) = 0;
  53   void write(bx_phy_address address, void *value, unsigned len);
  54   virtual void write_aligned(bx_phy_address address, Bit32u *data) = 0;
  55 };
  56
  57 #ifdef BX_INCLUDE_LOCAL_APIC
  58
  59 #define BX_CPU_APIC(i) (&(BX_CPU(i)->local_apic))
  60
  61 #ifdef BX_IMPLEMENT_XAPIC
  62 #  define BX_LAPIC_VERSION_ID 0x00050014  // P4 has 6 LVT entries
  63 #else
  64 #  define BX_LAPIC_VERSION_ID 0x00040010  // P6 has 4 LVT entries
  65 #endif
  66
  67 #define BX_LAPIC_BASE_ADDR  0xfee00000  // default Local APIC address
  68 #define BX_NUM_LOCAL_APICS  BX_SMP_PROCESSORS
  69 #define BX_LAPIC_MAX_INTS   256
  70
  71 class BOCHSAPI bx_local_apic_c : public bx_generic_apic_c
  72 {
  73   Bit32u  spurious_vector;
  74   bx_bool software_enabled;
  75   bx_bool focus_disable;
  76
  77   Bit32u task_priority;         // Task priority (TPR)
  78   Bit32u log_dest;              // Logical destination (LDR)
  79   Bit32u dest_format;           // Destination format (DFR)
  80
  81   // ISR=in-service register.  When an IRR bit is cleared, the corresponding
  82   // bit in ISR is set.
  83   Bit8u isr[BX_LAPIC_MAX_INTS];
  84   // TMR=trigger mode register.  Cleared for edge-triggered interrupts
  85   // and set for level-triggered interrupts. If set, local APIC must send
  86   // EOI message to all other APICs.
  87   Bit8u tmr[BX_LAPIC_MAX_INTS];
  88   // IRR=interrupt request register. When an interrupt is triggered by
  89   // the I/O APIC or another processor, it sets a bit in irr. The bit is
  90   // cleared when the interrupt is acknowledged by the processor.
  91   Bit8u irr[BX_LAPIC_MAX_INTS];
  92
  93 #define APIC_ERR_ILLEGAL_ADDR    0x80
  94 #define APIC_ERR_RX_ILLEGAL_VEC  0x40
  95 #define APIC_ERR_TX_ILLEGAL_VEC  0x20
  96 #define APIC_ERR_RX_ACCEPT_ERR   0x08
  97 #define APIC_ERR_TX_ACCEPT_ERR   0x04
  98 #define APIC_ERR_RX_CHECKSUM     0x02
  99 #define APIC_ERR_TX_CHECKSUM     0x01
 100
 101   // Error status Register (ESR)
 102   Bit32u error_status, shadow_error_status;
 103
 104   Bit32u icr_hi;                // Interrupt command register (ICR)
 105   Bit32u icr_lo;
 106
 107 #define APIC_LVT_ENTRIES 6
 108   Bit32u lvt[APIC_LVT_ENTRIES];
 109 #define APIC_LVT_TIMER   0
 110 #define APIC_LVT_THERMAL 1
 111 #define APIC_LVT_PERFORM 2
 112 #define APIC_LVT_LINT0   3
 113 #define APIC_LVT_LINT1   4
 114 #define APIC_LVT_ERROR   5
 115
 116   Bit32u timer_initial;         // Initial timer count
 117   Bit32u timer_current;         // current timer count
 118
 119   Bit32u timer_divconf;         // Timer divide configuration register
 120   Bit32u timer_divide_factor;
 121
 122   // Internal timer state, not accessible from bus
 123   bx_bool timer_active;
 124   int timer_handle;
 125   Bit64u ticksInitial;
 126
 127 /* APIC delivery modes */
 128 #define APIC_DM_FIXED   0
 129 #define APIC_DM_LOWPRI  1
 130 #define APIC_DM_SMI     2
 131 /* RESERVED             3 */
 132 #define APIC_DM_NMI     4
 133 #define APIC_DM_INIT    5
 134 #define APIC_DM_SIPI    6
 135 #define APIC_DM_EXTINT  7
 136
 137   BX_CPU_C *cpu;
 138
 139   // corresponding BX_CPU_ID for the local APIC
 140   unsigned cpu_id;
 141
 142 public:
 143   bx_bool INTR;
 144   bx_local_apic_c(BX_CPU_C *cpu);
 145   virtual ~bx_local_apic_c() { }
 146   virtual void reset(unsigned type);
 147   virtual void init(void);
 148   void set_id(Bit8u newid);   // redefine to set cpu->name
 149   virtual void write_aligned(bx_phy_address addr, Bit32u *data);
 150   virtual void read_aligned(bx_phy_address address, Bit32u *data);
 151   void startup_msg(Bit32u vector);
 152   // on local APIC, trigger means raise the CPU's INTR line. For now
 153   // I also have to raise pc_system.INTR but that should be replaced
 154   // with the cpu-specific INTR signals.
 155   void trigger_irq(unsigned num, unsigned trigger_mode, bx_bool bypass_irr_isr = 0);
 156   void untrigger_irq(unsigned num, unsigned trigger_mode);
 157   Bit8u acknowledge_int(void);  // only the local CPU should call this
 158   int highest_priority_int(Bit8u *array);
 159   void receive_EOI(Bit32u value);
 160   void send_ipi(void);
 161   void write_spurious_interrupt_register(Bit32u value);
 162   void service_local_apic(void);
 163   void print_status(void);
 164   bx_bool match_logical_addr (Bit8u address);
 165   bx_bool deliver(Bit8u vector, Bit8u delivery_mode, Bit8u trig_mode);
 166   Bit8u get_tpr(void);
 167   void  set_tpr(Bit8u tpr);
 168   Bit8u get_ppr(void);
 169   Bit8u get_apr(void);
 170   bx_bool is_focus(Bit8u vector);
 171   static void periodic_smf(void *);
 172   void periodic(void);
 173   void set_divide_configuration(Bit32u value);
 174   void set_initial_timer_count(Bit32u value);
 175   void register_state(bx_param_c *parent);
 176 };
 177
 178 #endif /* BX_INCLUDE_LOCAL_APIC */
 179
 180 // For P6 and Pentium family processors the local APIC ID feild is 4 bits.
 181 #ifdef BX_IMPLEMENT_XAPIC
 182   #define APIC_MAX_ID  0xff
 183   #define APIC_ID_MASK 0xff
 184 #else
 185   #define APIC_MAX_ID  0x0f
 186   #define APIC_ID_MASK 0x0f
 187 #endif
 188
 189 int apic_bus_deliver_lowest_priority(Bit8u vector, Bit8u dest, bx_bool trig_mode, bx_bool broadcast);
 190 int apic_bus_deliver_interrupt(Bit8u vector, Bit8u dest, Bit8u delivery_mode, Bit8u dest_mode, bx_bool level, bx_bool trig_mode);
 191 int apic_bus_broadcast_interrupt(Bit8u vector, Bit8u delivery_mode, bx_bool trig_mode, int exclude_cpu);
 192
 193 #endif // if BX_SUPPORT_APIC
 194
 195 #endif