cpu/arith32.cc

   1 /////////////////////////////////////////////////////////////////////////
   2 // $Id: arith32.cc,v 1.82 2008/08/09 21:05:05 sshwarts Exp $
   3 /////////////////////////////////////////////////////////////////////////
   4 //
   5 //  Copyright (C) 2001  MandrakeSoft S.A.
   6 //
   7 //    MandrakeSoft S.A.
   8 //    43, rue d'Aboukir
   9 //    75002 Paris - France
  10 //    http://www.linux-mandrake.com/
  11 //    http://www.mandrakesoft.com/
  12 //
  13 //  This library is free software; you can redistribute it and/or
  14 //  modify it under the terms of the GNU Lesser General Public
  15 //  License as published by the Free Software Foundation; either
  16 //  version 2 of the License, or (at your option) any later version.
  17 //
  18 //  This library is distributed in the hope that it will be useful,
  19 //  but WITHOUT ANY WARRANTY; without even the implied warranty of
  20 //  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  21 //  Lesser General Public License for more details.
  22 //
  23 //  You should have received a copy of the GNU Lesser General Public
  24 //  License along with this library; if not, write to the Free Software
  25 //  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  26 /////////////////////////////////////////////////////////////////////////
  27
  28 #define NEED_CPU_REG_SHORTCUTS 1
  29 #include "bochs.h"
  30 #include "cpu.h"
  31 #define LOG_THIS BX_CPU_THIS_PTR
  32
  33 #if BX_SUPPORT_X86_64==0
  34 // Make life easier for merging cpu64 and cpu code.
  35 #define RAX EAX
  36 #define RDX EDX
  37 #endif
  38
  39 void BX_CPP_AttrRegparmN(1) BX_CPU_C::INC_ERX(bxInstruction_c *i)
  40 {
  41   Bit32u erx = ++BX_READ_32BIT_REG(i->opcodeReg());
  42   SET_FLAGS_OSZAPC_INC_32(erx);
  43   BX_CLEAR_64BIT_HIGH(i->opcodeReg());
  44 }
  45
  46 void BX_CPP_AttrRegparmN(1) BX_CPU_C::DEC_ERX(bxInstruction_c *i)
  47 {
  48   Bit32u erx = --BX_READ_32BIT_REG(i->opcodeReg());
  49   SET_FLAGS_OSZAPC_DEC_32(erx);
  50   BX_CLEAR_64BIT_HIGH(i->opcodeReg());
  51 }
  52
  53 void BX_CPP_AttrRegparmN(1) BX_CPU_C::ADD_EdGdM(bxInstruction_c *i)
  54 {
  55   Bit32u op1_32, op2_32, sum_32;
  56
  57   bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
  58
  59   op1_32 = read_RMW_virtual_dword(i->seg(), eaddr);
  60   op2_32 = BX_READ_32BIT_REG(i->nnn());
  61   sum_32 = op1_32 + op2_32;
  62   write_RMW_virtual_dword(sum_32);
  63
  64   SET_FLAGS_OSZAPC_ADD_32(op1_32, op2_32, sum_32);
  65 }
  66
  67 void BX_CPP_AttrRegparmN(1) BX_CPU_C::ADD_GdEdR(bxInstruction_c *i)
  68 {
  69   Bit32u op1_32, op2_32, sum_32;
  70
  71   op1_32 = BX_READ_32BIT_REG(i->nnn());
  72   op2_32 = BX_READ_32BIT_REG(i->rm());
  73   sum_32 = op1_32 + op2_32;
  74
  75   BX_WRITE_32BIT_REGZ(i->nnn(), sum_32);
  76
  77   SET_FLAGS_OSZAPC_ADD_32(op1_32, op2_32, sum_32);
  78 }
  79
  80 void BX_CPP_AttrRegparmN(1) BX_CPU_C::ADD_EAXId(bxInstruction_c *i)
  81 {
  82   Bit32u op1_32, op2_32 = i->Id(), sum_32;
  83
  84   op1_32 = EAX;
  85   sum_32 = op1_32 + op2_32;
  86   RAX = sum_32;
  87
  88   SET_FLAGS_OSZAPC_ADD_32(op1_32, op2_32, sum_32);
  89 }
  90
  91 void BX_CPP_AttrRegparmN(1) BX_CPU_C::ADC_EdGdM(bxInstruction_c *i)
  92 {
  93   bx_bool temp_CF = getB_CF();
  94
  95   Bit32u op1_32, op2_32, sum_32;
  96
  97   bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
  98
  99   op1_32 = read_RMW_virtual_dword(i->seg(), eaddr);
 100   op2_32 = BX_READ_32BIT_REG(i->nnn());
 101   sum_32 = op1_32 + op2_32 + temp_CF;
 102   write_RMW_virtual_dword(sum_32);
 103
 104   SET_FLAGS_OSZAPC_32(op1_32, op2_32, sum_32, BX_LF_INSTR_ADD_ADC32(temp_CF));
 105 }
 106
 107 void BX_CPP_AttrRegparmN(1) BX_CPU_C::ADC_GdEdR(bxInstruction_c *i)
 108 {
 109   bx_bool temp_CF = getB_CF();
 110
 111   Bit32u op1_32, op2_32, sum_32;
 112
 113   op1_32 = BX_READ_32BIT_REG(i->nnn());
 114   op2_32 = BX_READ_32BIT_REG(i->rm());
 115   sum_32 = op1_32 + op2_32 + temp_CF;
 116   BX_WRITE_32BIT_REGZ(i->nnn(), sum_32);
 117
 118   SET_FLAGS_OSZAPC_32(op1_32, op2_32, sum_32, BX_LF_INSTR_ADD_ADC32(temp_CF));
 119 }
 120
 121 void BX_CPP_AttrRegparmN(1) BX_CPU_C::ADC_EAXId(bxInstruction_c *i)
 122 {
 123   bx_bool temp_CF = getB_CF();
 124
 125   Bit32u op1_32, op2_32 = i->Id(), sum_32;
 126
 127   op1_32 = EAX;
 128   sum_32 = op1_32 + op2_32 + temp_CF;
 129   RAX = sum_32;
 130
 131   SET_FLAGS_OSZAPC_32(op1_32, op2_32, sum_32, BX_LF_INSTR_ADD_ADC32(temp_CF));
 132 }
 133
 134 void BX_CPP_AttrRegparmN(1) BX_CPU_C::SBB_EdGdM(bxInstruction_c *i)
 135 {
 136   bx_bool temp_CF = getB_CF();
 137
 138   Bit32u op1_32, op2_32, diff_32;
 139
 140   bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
 141
 142   op1_32 = read_RMW_virtual_dword(i->seg(), eaddr);
 143   op2_32 = BX_READ_32BIT_REG(i->nnn());
 144   diff_32 = op1_32 - (op2_32 + temp_CF);
 145   write_RMW_virtual_dword(diff_32);
 146
 147   SET_FLAGS_OSZAPC_32(op1_32, op2_32, diff_32, BX_LF_INSTR_SUB_SBB32(temp_CF));
 148 }
 149
 150 void BX_CPP_AttrRegparmN(1) BX_CPU_C::SBB_GdEdR(bxInstruction_c *i)
 151 {
 152   bx_bool temp_CF = getB_CF();
 153
 154   Bit32u op1_32, op2_32, diff_32;
 155
 156   op1_32 = BX_READ_32BIT_REG(i->nnn());
 157   op2_32 = BX_READ_32BIT_REG(i->rm());
 158   diff_32 = op1_32 - (op2_32 + temp_CF);
 159   BX_WRITE_32BIT_REGZ(i->nnn(), diff_32);
 160
 161   SET_FLAGS_OSZAPC_32(op1_32, op2_32, diff_32, BX_LF_INSTR_SUB_SBB32(temp_CF));
 162 }
 163
 164 void BX_CPP_AttrRegparmN(1) BX_CPU_C::SBB_EAXId(bxInstruction_c *i)
 165 {
 166   bx_bool temp_CF = getB_CF();
 167
 168   Bit32u op1_32, op2_32, diff_32;
 169
 170   op1_32 = EAX;
 171   op2_32 = i->Id();
 172   diff_32 = op1_32 - (op2_32 + temp_CF);
 173   RAX = diff_32;
 174
 175   SET_FLAGS_OSZAPC_32(op1_32, op2_32, diff_32, BX_LF_INSTR_SUB_SBB32(temp_CF));
 176 }
 177
 178 void BX_CPP_AttrRegparmN(1) BX_CPU_C::SBB_EdIdM(bxInstruction_c *i)
 179 {
 180   bx_bool temp_CF = getB_CF();
 181
 182   Bit32u op1_32, op2_32 = i->Id(), diff_32;
 183
 184   bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
 185
 186   op1_32 = read_RMW_virtual_dword(i->seg(), eaddr);
 187   diff_32 = op1_32 - (op2_32 + temp_CF);
 188   write_RMW_virtual_dword(diff_32);
 189
 190   SET_FLAGS_OSZAPC_32(op1_32, op2_32, diff_32, BX_LF_INSTR_SUB_SBB32(temp_CF));
 191 }
 192
 193 void BX_CPP_AttrRegparmN(1) BX_CPU_C::SBB_EdIdR(bxInstruction_c *i)
 194 {
 195   bx_bool temp_CF = getB_CF();
 196
 197   Bit32u op1_32, op2_32 = i->Id(), diff_32;
 198
 199   op1_32 = BX_READ_32BIT_REG(i->rm());
 200   diff_32 = op1_32 - (op2_32 + temp_CF);
 201   BX_WRITE_32BIT_REGZ(i->rm(), diff_32);
 202
 203   SET_FLAGS_OSZAPC_32(op1_32, op2_32, diff_32, BX_LF_INSTR_SUB_SBB32(temp_CF));
 204 }
 205
 206 void BX_CPP_AttrRegparmN(1) BX_CPU_C::SUB_EdGdM(bxInstruction_c *i)
 207 {
 208   Bit32u op1_32, op2_32, diff_32;
 209
 210   bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
 211
 212   op1_32 = read_RMW_virtual_dword(i->seg(), eaddr);
 213   op2_32 = BX_READ_32BIT_REG(i->nnn());
 214   diff_32 = op1_32 - op2_32;
 215   write_RMW_virtual_dword(diff_32);
 216
 217   SET_FLAGS_OSZAPC_SUB_32(op1_32, op2_32, diff_32);
 218 }
 219
 220 void BX_CPP_AttrRegparmN(1) BX_CPU_C::SUB_GdEdR(bxInstruction_c *i)
 221 {
 222   Bit32u op1_32, op2_32, diff_32;
 223
 224   op1_32 = BX_READ_32BIT_REG(i->nnn());
 225   op2_32 = BX_READ_32BIT_REG(i->rm());
 226   diff_32 = op1_32 - op2_32;
 227   BX_WRITE_32BIT_REGZ(i->nnn(), diff_32);
 228
 229   SET_FLAGS_OSZAPC_SUB_32(op1_32, op2_32, diff_32);
 230 }
 231
 232 void BX_CPP_AttrRegparmN(1) BX_CPU_C::SUB_EAXId(bxInstruction_c *i)
 233 {
 234   Bit32u op1_32, op2_32, diff_32;
 235
 236   op1_32 = EAX;
 237   op2_32 = i->Id();
 238   diff_32 = op1_32 - op2_32;
 239   RAX = diff_32;
 240
 241   SET_FLAGS_OSZAPC_SUB_32(op1_32, op2_32, diff_32);
 242 }
 243
 244 void BX_CPP_AttrRegparmN(1) BX_CPU_C::CMP_EdGdM(bxInstruction_c *i)
 245 {
 246   Bit32u op1_32, op2_32, diff_32;
 247
 248   bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
 249
 250   op1_32 = read_virtual_dword(i->seg(), eaddr);
 251   op2_32 = BX_READ_32BIT_REG(i->nnn());
 252   diff_32 = op1_32 - op2_32;
 253
 254   SET_FLAGS_OSZAPC_SUB_32(op1_32, op2_32, diff_32);
 255 }
 256
 257 void BX_CPP_AttrRegparmN(1) BX_CPU_C::CMP_GdEdR(bxInstruction_c *i)
 258 {
 259   Bit32u op1_32, op2_32, diff_32;
 260
 261   op1_32 = BX_READ_32BIT_REG(i->nnn());
 262   op2_32 = BX_READ_32BIT_REG(i->rm());
 263   diff_32 = op1_32 - op2_32;
 264
 265   SET_FLAGS_OSZAPC_SUB_32(op1_32, op2_32, diff_32);
 266 }
 267
 268 void BX_CPP_AttrRegparmN(1) BX_CPU_C::CMP_EAXId(bxInstruction_c *i)
 269 {
 270   Bit32u op1_32, op2_32, diff_32;
 271
 272   op1_32 = EAX;
 273   op2_32 = i->Id();
 274   diff_32 = op1_32 - op2_32;
 275
 276   SET_FLAGS_OSZAPC_SUB_32(op1_32, op2_32, diff_32);
 277 }
 278
 279 void BX_CPP_AttrRegparmN(1) BX_CPU_C::CWDE(bxInstruction_c *i)
 280 {
 281   /* CWDE: no flags are effected */
 282   Bit32u tmp = (Bit16s) AX;
 283   RAX = tmp;
 284 }
 285
 286 void BX_CPP_AttrRegparmN(1) BX_CPU_C::CDQ(bxInstruction_c *i)
 287 {
 288   /* CDQ: no flags are affected */
 289   if (EAX & 0x80000000) {
 290     RDX = 0xFFFFFFFF;
 291   }
 292   else {
 293     RDX = 0x00000000;
 294   }
 295 }
 296
 297 // Some info on the opcodes at {0F,A6} and {0F,A7}
 298 // On 386 steps A0-B0:
 299 //   {OF,A6} = XBTS
 300 //   {OF,A7} = IBTS
 301 // On 486 steps A0-B0:
 302 //   {OF,A6} = CMPXCHG 8
 303 //   {OF,A7} = CMPXCHG 16|32
 304 //
 305 // On 486 >= B steps, and further processors, the
 306 // CMPXCHG instructions were moved to opcodes:
 307 //   {OF,B0} = CMPXCHG 8
 308 //   {OF,B1} = CMPXCHG 16|32
 309
 310 void BX_CPP_AttrRegparmN(1) BX_CPU_C::CMPXCHG_XBTS(bxInstruction_c *i)
 311 {
 312   BX_INFO(("CMPXCHG_XBTS: Generate #UD exception"));
 313   exception(BX_UD_EXCEPTION, 0, 0);
 314 }
 315
 316 void BX_CPP_AttrRegparmN(1) BX_CPU_C::CMPXCHG_IBTS(bxInstruction_c *i)
 317 {
 318   BX_INFO(("CMPXCHG_IBTS: Generate #UD exception"));
 319   exception(BX_UD_EXCEPTION, 0, 0);
 320 }
 321
 322 void BX_CPP_AttrRegparmN(1) BX_CPU_C::XADD_EdGdM(bxInstruction_c *i)
 323 {
 324 #if BX_CPU_LEVEL >= 4
 325   Bit32u op1_32, op2_32, sum_32;
 326
 327   /* XADD dst(r/m), src(r)
 328    * temp <-- src + dst         | sum = op2 + op1
 329    * src  <-- dst               | op2 = op1
 330    * dst  <-- tmp               | op1 = sum
 331    */
 332
 333   bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
 334
 335   op1_32 = read_RMW_virtual_dword(i->seg(), eaddr);
 336   op2_32 = BX_READ_32BIT_REG(i->nnn());
 337   sum_32 = op1_32 + op2_32;
 338   write_RMW_virtual_dword(sum_32);
 339
 340   /* and write destination into source */
 341   BX_WRITE_32BIT_REGZ(i->nnn(), op1_32);
 342
 343   SET_FLAGS_OSZAPC_ADD_32(op1_32, op2_32, sum_32);
 344 #else
 345   BX_INFO (("XADD_EdGd not supported for cpulevel <= 3"));
 346   exception(BX_UD_EXCEPTION, 0, 0);
 347 #endif
 348 }
 349
 350 void BX_CPP_AttrRegparmN(1) BX_CPU_C::XADD_EdGdR(bxInstruction_c *i)
 351 {
 352 #if BX_CPU_LEVEL >= 4
 353   Bit32u op1_32, op2_32, sum_32;
 354
 355   /* XADD dst(r/m), src(r)
 356    * temp <-- src + dst         | sum = op2 + op1
 357    * src  <-- dst               | op2 = op1
 358    * dst  <-- tmp               | op1 = sum
 359    */
 360
 361   op1_32 = BX_READ_32BIT_REG(i->rm());
 362   op2_32 = BX_READ_32BIT_REG(i->nnn());
 363   sum_32 = op1_32 + op2_32;
 364
 365   // and write destination into source
 366   // Note: if both op1 & op2 are registers, the last one written
 367   //       should be the sum, as op1 & op2 may be the same register.
 368   //       For example:  XADD AL, AL
 369   BX_WRITE_32BIT_REGZ(i->nnn(), op1_32);
 370   BX_WRITE_32BIT_REGZ(i->rm(), sum_32);
 371
 372   SET_FLAGS_OSZAPC_ADD_32(op1_32, op2_32, sum_32);
 373 #else
 374   BX_INFO (("XADD_EdGd not supported for cpulevel <= 3"));
 375   exception(BX_UD_EXCEPTION, 0, 0);
 376 #endif
 377 }
 378
 379 void BX_CPP_AttrRegparmN(1) BX_CPU_C::ADD_EdIdM(bxInstruction_c *i)
 380 {
 381   Bit32u op1_32, op2_32, sum_32;
 382
 383   bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
 384
 385   op1_32 = read_RMW_virtual_dword(i->seg(), eaddr);
 386   op2_32 = i->Id();
 387   sum_32 = op1_32 + op2_32;
 388   write_RMW_virtual_dword(sum_32);
 389
 390   SET_FLAGS_OSZAPC_ADD_32(op1_32, op2_32, sum_32);
 391 }
 392
 393 void BX_CPP_AttrRegparmN(1) BX_CPU_C::ADD_EdIdR(bxInstruction_c *i)
 394 {
 395   Bit32u op1_32, op2_32, sum_32;
 396
 397   op1_32 = BX_READ_32BIT_REG(i->rm());
 398   op2_32 = i->Id();
 399   sum_32 = op1_32 + op2_32;
 400
 401   BX_WRITE_32BIT_REGZ(i->rm(), sum_32);
 402
 403   SET_FLAGS_OSZAPC_ADD_32(op1_32, op2_32, sum_32);
 404 }
 405
 406 void BX_CPP_AttrRegparmN(1) BX_CPU_C::ADC_EdIdM(bxInstruction_c *i)
 407 {
 408   bx_bool temp_CF = getB_CF();
 409
 410   Bit32u op1_32, op2_32 = i->Id(), sum_32;
 411
 412   bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
 413
 414   op1_32 = read_RMW_virtual_dword(i->seg(), eaddr);
 415   sum_32 = op1_32 + op2_32 + temp_CF;
 416   write_RMW_virtual_dword(sum_32);
 417
 418   SET_FLAGS_OSZAPC_32(op1_32, op2_32, sum_32, BX_LF_INSTR_ADD_ADC32(temp_CF));
 419 }
 420
 421 void BX_CPP_AttrRegparmN(1) BX_CPU_C::ADC_EdIdR(bxInstruction_c *i)
 422 {
 423   bx_bool temp_CF = getB_CF();
 424
 425   Bit32u op1_32, op2_32 = i->Id(), sum_32;
 426
 427   op1_32 = BX_READ_32BIT_REG(i->rm());
 428   sum_32 = op1_32 + op2_32 + temp_CF;
 429   BX_WRITE_32BIT_REGZ(i->rm(), sum_32);
 430
 431   SET_FLAGS_OSZAPC_32(op1_32, op2_32, sum_32, BX_LF_INSTR_ADD_ADC32(temp_CF));
 432 }
 433
 434 void BX_CPP_AttrRegparmN(1) BX_CPU_C::SUB_EdIdM(bxInstruction_c *i)
 435 {
 436   Bit32u op1_32, op2_32 = i->Id(), diff_32;
 437
 438   bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
 439
 440   op1_32 = read_RMW_virtual_dword(i->seg(), eaddr);
 441   diff_32 = op1_32 - op2_32;
 442   write_RMW_virtual_dword(diff_32);
 443
 444   SET_FLAGS_OSZAPC_SUB_32(op1_32, op2_32, diff_32);
 445 }
 446
 447 void BX_CPP_AttrRegparmN(1) BX_CPU_C::SUB_EdIdR(bxInstruction_c *i)
 448 {
 449   Bit32u op1_32, op2_32 = i->Id(), diff_32;
 450
 451   op1_32 = BX_READ_32BIT_REG(i->rm());
 452   diff_32 = op1_32 - op2_32;
 453   BX_WRITE_32BIT_REGZ(i->rm(), diff_32);
 454
 455   SET_FLAGS_OSZAPC_SUB_32(op1_32, op2_32, diff_32);
 456 }
 457
 458 void BX_CPP_AttrRegparmN(1) BX_CPU_C::CMP_EdIdM(bxInstruction_c *i)
 459 {
 460   Bit32u op1_32, op2_32, diff_32;
 461
 462   bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
 463
 464   op1_32 = read_virtual_dword(i->seg(), eaddr);
 465   op2_32 = i->Id();
 466   diff_32 = op1_32 - op2_32;
 467
 468   SET_FLAGS_OSZAPC_SUB_32(op1_32, op2_32, diff_32);
 469 }
 470
 471 void BX_CPP_AttrRegparmN(1) BX_CPU_C::CMP_EdIdR(bxInstruction_c *i)
 472 {
 473   Bit32u op1_32, op2_32, diff_32;
 474
 475   op1_32 = BX_READ_32BIT_REG(i->rm());
 476   op2_32 = i->Id();
 477   diff_32 = op1_32 - op2_32;
 478
 479   SET_FLAGS_OSZAPC_SUB_32(op1_32, op2_32, diff_32);
 480 }
 481
 482 void BX_CPP_AttrRegparmN(1) BX_CPU_C::NEG_EdM(bxInstruction_c *i)
 483 {
 484   Bit32u op1_32;
 485
 486   bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
 487
 488   op1_32 = read_RMW_virtual_dword(i->seg(), eaddr);
 489   op1_32 = - (Bit32s)(op1_32);
 490   write_RMW_virtual_dword(op1_32);
 491
 492   SET_FLAGS_OSZAPC_RESULT_32(op1_32, BX_LF_INSTR_NEG32);
 493 }
 494
 495 void BX_CPP_AttrRegparmN(1) BX_CPU_C::NEG_EdR(bxInstruction_c *i)
 496 {
 497   Bit32u op1_32 = BX_READ_32BIT_REG(i->rm());
 498   op1_32 = - (Bit32s)(op1_32);
 499   BX_WRITE_32BIT_REGZ(i->rm(), op1_32);
 500
 501   SET_FLAGS_OSZAPC_RESULT_32(op1_32, BX_LF_INSTR_NEG32);
 502 }
 503
 504 void BX_CPP_AttrRegparmN(1) BX_CPU_C::INC_EdM(bxInstruction_c *i)
 505 {
 506   Bit32u op1_32;
 507
 508   bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
 509
 510   op1_32 = read_RMW_virtual_dword(i->seg(), eaddr);
 511   op1_32++;
 512   write_RMW_virtual_dword(op1_32);
 513
 514   SET_FLAGS_OSZAPC_INC_32(op1_32);
 515 }
 516
 517 void BX_CPP_AttrRegparmN(1) BX_CPU_C::DEC_EdM(bxInstruction_c *i)
 518 {
 519   Bit32u op1_32;
 520
 521   bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
 522
 523   op1_32 = read_RMW_virtual_dword(i->seg(), eaddr);
 524   op1_32--;
 525   write_RMW_virtual_dword(op1_32);
 526
 527   SET_FLAGS_OSZAPC_DEC_32(op1_32);
 528 }
 529
 530 void BX_CPP_AttrRegparmN(1) BX_CPU_C::CMPXCHG_EdGdM(bxInstruction_c *i)
 531 {
 532 #if BX_CPU_LEVEL >= 4
 533   Bit32u op1_32, op2_32, diff_32;
 534
 535   bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
 536
 537   op1_32 = read_RMW_virtual_dword(i->seg(), eaddr);
 538   diff_32 = EAX - op1_32;
 539   SET_FLAGS_OSZAPC_SUB_32(EAX, op1_32, diff_32);
 540
 541   if (diff_32 == 0) {  // if accumulator == dest
 542     // dest <-- src
 543     op2_32 = BX_READ_32BIT_REG(i->nnn());
 544     write_RMW_virtual_dword(op2_32);
 545   }
 546   else {
 547     // accumulator <-- dest
 548     RAX = op1_32;
 549   }
 550 #else
 551   BX_INFO(("CMPXCHG_EdGd: not supported for cpulevel <= 3"));
 552   exception(BX_UD_EXCEPTION, 0, 0);
 553 #endif
 554 }
 555
 556 void BX_CPP_AttrRegparmN(1) BX_CPU_C::CMPXCHG_EdGdR(bxInstruction_c *i)
 557 {
 558 #if BX_CPU_LEVEL >= 4
 559   Bit32u op1_32, op2_32, diff_32;
 560
 561   op1_32 = BX_READ_32BIT_REG(i->rm());
 562   diff_32 = EAX - op1_32;
 563   SET_FLAGS_OSZAPC_SUB_32(EAX, op1_32, diff_32);
 564
 565   if (diff_32 == 0) {  // if accumulator == dest
 566     // dest <-- src
 567     op2_32 = BX_READ_32BIT_REG(i->nnn());
 568     BX_WRITE_32BIT_REGZ(i->rm(), op2_32);
 569   }
 570   else {
 571     // accumulator <-- dest
 572     RAX = op1_32;
 573   }
 574 #else
 575   BX_INFO(("CMPXCHG_EdGd: not supported for cpulevel <= 3"));
 576   exception(BX_UD_EXCEPTION, 0, 0);
 577 #endif
 578 }
 579
 580 void BX_CPP_AttrRegparmN(1) BX_CPU_C::CMPXCHG8B(bxInstruction_c *i)
 581 {
 582 #if BX_CPU_LEVEL >= 5
 583   Bit64u op1_64, op2_64;
 584
 585   bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
 586
 587   // check write permission for following write
 588   op1_64 = read_RMW_virtual_qword(i->seg(), eaddr);
 589   op2_64 = ((Bit64u) EDX << 32) | EAX;
 590
 591   if (op1_64 == op2_64) {  // if accumulator == dest
 592     // dest <-- src (ECX:EBX)
 593     op2_64 = ((Bit64u) ECX << 32) | EBX;
 594     write_RMW_virtual_qword(op2_64);
 595     assert_ZF();
 596   }
 597   else {
 598     // accumulator <-- dest
 599     RAX = GET32L(op1_64);
 600     RDX = GET32H(op1_64);
 601     clear_ZF();
 602   }
 603
 604 #else
 605   BX_INFO(("CMPXCHG8B: not supported for cpulevel <= 4"));
 606   exception(BX_UD_EXCEPTION, 0, 0);
 607 #endif
 608 }