cpu/ctrl_xfer32.cc

   1 /////////////////////////////////////////////////////////////////////////
   2 // $Id: ctrl_xfer32.cc,v 1.80 2008/10/06 20:41:28 sshwarts Exp $
   3 /////////////////////////////////////////////////////////////////////////
   4 //
   5 //  Copyright (C) 2001  MandrakeSoft S.A.
   6 //
   7 //    MandrakeSoft S.A.
   8 //    43, rue d'Aboukir
   9 //    75002 Paris - France
  10 //    http://www.linux-mandrake.com/
  11 //    http://www.mandrakesoft.com/
  12 //
  13 //  This library is free software; you can redistribute it and/or
  14 //  modify it under the terms of the GNU Lesser General Public
  15 //  License as published by the Free Software Foundation; either
  16 //  version 2 of the License, or (at your option) any later version.
  17 //
  18 //  This library is distributed in the hope that it will be useful,
  19 //  but WITHOUT ANY WARRANTY; without even the implied warranty of
  20 //  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  21 //  Lesser General Public License for more details.
  22 //
  23 //  You should have received a copy of the GNU Lesser General Public
  24 //  License along with this library; if not, write to the Free Software
  25 //  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  26 /////////////////////////////////////////////////////////////////////////
  27
  28 #define NEED_CPU_REG_SHORTCUTS 1
  29 #include "bochs.h"
  30 #include "cpu.h"
  31 #define LOG_THIS BX_CPU_THIS_PTR
  32
  33 // Make code more tidy with a few macros.
  34 #if BX_SUPPORT_X86_64==0
  35 #define RSP ESP
  36 #define RIP EIP
  37 #endif
  38
  39 #if BX_CPU_LEVEL >= 3
  40
  41 BX_CPP_INLINE void BX_CPP_AttrRegparmN(1) BX_CPU_C::branch_near32(Bit32u new_EIP)
  42 {
  43   BX_ASSERT(BX_CPU_THIS_PTR cpu_mode != BX_MODE_LONG_64);
  44
  45   // check always, not only in protected mode
  46   if (new_EIP > BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.limit_scaled)
  47   {
  48     BX_ERROR(("branch_near32: offset outside of CS limits"));
  49     exception(BX_GP_EXCEPTION, 0, 0);
  50   }
  51
  52   EIP = new_EIP;
  53
  54 #if BX_SUPPORT_TRACE_CACHE && !defined(BX_TRACE_CACHE_NO_SPECULATIVE_TRACING)
  55   // assert magic async_event to stop trace execution
  56   BX_CPU_THIS_PTR async_event |= BX_ASYNC_EVENT_STOP_TRACE;
  57 #endif
  58 }
  59
  60 void BX_CPP_AttrRegparmN(1) BX_CPU_C::RETnear32_Iw(bxInstruction_c *i)
  61 {
  62   BX_ASSERT(BX_CPU_THIS_PTR cpu_mode != BX_MODE_LONG_64);
  63
  64 #if BX_DEBUGGER
  65   BX_CPU_THIS_PTR show_flag |= Flag_ret;
  66 #endif
  67
  68   BX_CPU_THIS_PTR speculative_rsp = 1;
  69   BX_CPU_THIS_PTR prev_rsp = ESP;
  70
  71   Bit16u imm16 = i->Iw();
  72   Bit32u return_EIP = pop_32();
  73   if (return_EIP > BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.limit_scaled)
  74   {
  75     BX_ERROR(("RETnear32_Iw: offset outside of CS limits"));
  76     exception(BX_GP_EXCEPTION, 0, 0);
  77   }
  78   EIP = return_EIP;
  79
  80   if (BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.d_b)
  81     ESP += imm16;
  82   else
  83      SP += imm16;
  84
  85   BX_CPU_THIS_PTR speculative_rsp = 0;
  86
  87   BX_INSTR_UCNEAR_BRANCH(BX_CPU_ID, BX_INSTR_IS_RET, EIP);
  88 }
  89
  90 void BX_CPP_AttrRegparmN(1) BX_CPU_C::RETnear32(bxInstruction_c *i)
  91 {
  92   BX_ASSERT(BX_CPU_THIS_PTR cpu_mode != BX_MODE_LONG_64);
  93
  94 #if BX_DEBUGGER
  95   BX_CPU_THIS_PTR show_flag |= Flag_ret;
  96 #endif
  97
  98   BX_CPU_THIS_PTR speculative_rsp = 1;
  99   BX_CPU_THIS_PTR prev_rsp = ESP;
 100
 101   Bit32u return_EIP = pop_32();
 102   if (return_EIP > BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.limit_scaled)
 103   {
 104     BX_ERROR(("RETnear32: offset outside of CS limits"));
 105     exception(BX_GP_EXCEPTION, 0, 0);
 106   }
 107   EIP = return_EIP;
 108
 109   BX_CPU_THIS_PTR speculative_rsp = 0;
 110
 111   BX_INSTR_UCNEAR_BRANCH(BX_CPU_ID, BX_INSTR_IS_RET, EIP);
 112 }
 113
 114 void BX_CPP_AttrRegparmN(1) BX_CPU_C::RETfar32_Iw(bxInstruction_c *i)
 115 {
 116   invalidate_prefetch_q();
 117
 118 #if BX_DEBUGGER
 119   BX_CPU_THIS_PTR show_flag |= Flag_ret;
 120 #endif
 121
 122   Bit16u imm16 = i->Iw();
 123   Bit16u cs_raw;
 124   Bit32u eip;
 125
 126   BX_CPU_THIS_PTR speculative_rsp = 1;
 127   BX_CPU_THIS_PTR prev_rsp = RSP;
 128
 129   if (protected_mode()) {
 130     BX_CPU_THIS_PTR return_protected(i, imm16);
 131     goto done;
 132   }
 133
 134   eip    =          pop_32();
 135   cs_raw = (Bit16u) pop_32(); /* 32bit pop, MSW discarded */
 136
 137   // CS.LIMIT can't change when in real/v8086 mode
 138   if (eip > BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.limit_scaled) {
 139     BX_ERROR(("RETfar32_Iw: instruction pointer not within code segment limits"));
 140     exception(BX_GP_EXCEPTION, 0, 0);
 141   }
 142
 143   load_seg_reg(&BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS], cs_raw);
 144   EIP = eip;
 145
 146   if (BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.d_b)
 147     ESP += imm16;
 148   else
 149      SP += imm16;
 150
 151 done:
 152   BX_CPU_THIS_PTR speculative_rsp = 0;
 153
 154   BX_INSTR_FAR_BRANCH(BX_CPU_ID, BX_INSTR_IS_RET,
 155                       BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value, EIP);
 156 }
 157
 158 void BX_CPP_AttrRegparmN(1) BX_CPU_C::RETfar32(bxInstruction_c *i)
 159 {
 160   Bit32u eip;
 161   Bit16u cs_raw;
 162
 163   invalidate_prefetch_q();
 164
 165 #if BX_DEBUGGER
 166   BX_CPU_THIS_PTR show_flag |= Flag_ret;
 167 #endif
 168
 169   BX_CPU_THIS_PTR speculative_rsp = 1;
 170   BX_CPU_THIS_PTR prev_rsp = RSP;
 171
 172   if (protected_mode()) {
 173     BX_CPU_THIS_PTR return_protected(i, 0);
 174     goto done;
 175   }
 176
 177   eip = pop_32();
 178
 179   // CS.LIMIT can't change when in real/v8086 mode
 180   if (eip > BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.limit_scaled) {
 181     BX_ERROR(("RETfar32: instruction pointer not within code segment limits"));
 182     exception(BX_GP_EXCEPTION, 0, 0);
 183   }
 184
 185   cs_raw = (Bit16u) pop_32(); /* 32bit pop, MSW discarded */
 186
 187   load_seg_reg(&BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS], cs_raw);
 188   EIP = eip;
 189
 190 done:
 191   BX_CPU_THIS_PTR speculative_rsp = 0;
 192
 193   BX_INSTR_FAR_BRANCH(BX_CPU_ID, BX_INSTR_IS_RET,
 194                       BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value, EIP);
 195 }
 196
 197 void BX_CPP_AttrRegparmN(1) BX_CPU_C::CALL_Jd(bxInstruction_c *i)
 198 {
 199 #if BX_DEBUGGER
 200   BX_CPU_THIS_PTR show_flag |= Flag_call;
 201 #endif
 202
 203   Bit32u new_EIP = EIP + i->Id();
 204
 205   BX_CPU_THIS_PTR speculative_rsp = 1;
 206   BX_CPU_THIS_PTR prev_rsp = ESP;
 207
 208   /* push 32 bit EA of next instruction */
 209   push_32(EIP);
 210
 211   branch_near32(new_EIP);
 212
 213   BX_CPU_THIS_PTR speculative_rsp = 0;
 214
 215   BX_INSTR_UCNEAR_BRANCH(BX_CPU_ID, BX_INSTR_IS_CALL, EIP);
 216 }
 217
 218 void BX_CPP_AttrRegparmN(1) BX_CPU_C::CALL32_Ap(bxInstruction_c *i)
 219 {
 220   BX_ASSERT(BX_CPU_THIS_PTR cpu_mode != BX_MODE_LONG_64);
 221
 222   Bit16u cs_raw;
 223   Bit32u disp32;
 224
 225   invalidate_prefetch_q();
 226
 227 #if BX_DEBUGGER
 228   BX_CPU_THIS_PTR show_flag |= Flag_call;
 229 #endif
 230
 231   disp32 = i->Id();
 232   cs_raw = i->Iw2();
 233
 234   BX_CPU_THIS_PTR speculative_rsp = 1;
 235   BX_CPU_THIS_PTR prev_rsp = ESP;
 236
 237   if (protected_mode()) {
 238     BX_CPU_THIS_PTR call_protected(i, cs_raw, disp32);
 239     goto done;
 240   }
 241
 242   // CS.LIMIT can't change when in real/v8086 mode
 243   if (disp32 > BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.limit_scaled) {
 244     BX_ERROR(("CALL32_Ap: instruction pointer not within code segment limits"));
 245     exception(BX_GP_EXCEPTION, 0, 0);
 246   }
 247
 248   push_32(BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value);
 249   push_32(EIP);
 250
 251   load_seg_reg(&BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS], cs_raw);
 252   EIP = disp32;
 253
 254 done:
 255   BX_CPU_THIS_PTR speculative_rsp = 0;
 256
 257   BX_INSTR_FAR_BRANCH(BX_CPU_ID, BX_INSTR_IS_CALL,
 258                       BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value, EIP);
 259 }
 260
 261 void BX_CPP_AttrRegparmN(1) BX_CPU_C::CALL_EdR(bxInstruction_c *i)
 262 {
 263 #if BX_DEBUGGER
 264   BX_CPU_THIS_PTR show_flag |= Flag_call;
 265 #endif
 266
 267   Bit32u new_EIP = BX_READ_32BIT_REG(i->rm());
 268
 269   BX_CPU_THIS_PTR speculative_rsp = 1;
 270   BX_CPU_THIS_PTR prev_rsp = ESP;
 271
 272   /* push 32 bit EA of next instruction */
 273   push_32(EIP);
 274
 275   branch_near32(new_EIP);
 276
 277   BX_CPU_THIS_PTR speculative_rsp = 0;
 278
 279   BX_INSTR_UCNEAR_BRANCH(BX_CPU_ID, BX_INSTR_IS_CALL, EIP);
 280 }
 281
 282 void BX_CPP_AttrRegparmN(1) BX_CPU_C::CALL32_Ep(bxInstruction_c *i)
 283 {
 284   Bit16u cs_raw;
 285   Bit32u op1_32;
 286
 287   invalidate_prefetch_q();
 288
 289 #if BX_DEBUGGER
 290   BX_CPU_THIS_PTR show_flag |= Flag_call;
 291 #endif
 292
 293   bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
 294
 295   /* pointer, segment address pair */
 296   op1_32 = read_virtual_dword(i->seg(), eaddr);
 297   cs_raw = read_virtual_word (i->seg(), eaddr+4);
 298
 299   BX_CPU_THIS_PTR speculative_rsp = 1;
 300   BX_CPU_THIS_PTR prev_rsp = RSP;
 301
 302   if (protected_mode()) {
 303     BX_CPU_THIS_PTR call_protected(i, cs_raw, op1_32);
 304     goto done;
 305   }
 306
 307   // CS.LIMIT can't change when in real/v8086 mode
 308   if (op1_32 > BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.limit_scaled) {
 309     BX_ERROR(("CALL32_Ep: instruction pointer not within code segment limits"));
 310     exception(BX_GP_EXCEPTION, 0, 0);
 311   }
 312
 313   push_32(BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value);
 314   push_32(EIP);
 315
 316   load_seg_reg(&BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS], cs_raw);
 317   EIP = op1_32;
 318
 319 done:
 320   BX_CPU_THIS_PTR speculative_rsp = 0;
 321
 322   BX_INSTR_FAR_BRANCH(BX_CPU_ID, BX_INSTR_IS_CALL,
 323                       BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value, EIP);
 324 }
 325
 326 void BX_CPP_AttrRegparmN(1) BX_CPU_C::JMP_Jd(bxInstruction_c *i)
 327 {
 328   Bit32u new_EIP = EIP + (Bit32s) i->Id();
 329   branch_near32(new_EIP);
 330   BX_INSTR_UCNEAR_BRANCH(BX_CPU_ID, BX_INSTR_IS_JMP, new_EIP);
 331 }
 332
 333 void BX_CPP_AttrRegparmN(1) BX_CPU_C::JO_Jd(bxInstruction_c *i)
 334 {
 335   if (get_OF()) {
 336     Bit32u new_EIP = EIP + (Bit32s) i->Id();
 337     branch_near32(new_EIP);
 338     BX_INSTR_CNEAR_BRANCH_TAKEN(BX_CPU_ID, new_EIP);
 339   }
 340 #if BX_INSTRUMENTATION
 341   else {
 342     BX_INSTR_CNEAR_BRANCH_NOT_TAKEN(BX_CPU_ID);
 343   }
 344 #endif
 345 }
 346
 347 void BX_CPP_AttrRegparmN(1) BX_CPU_C::JNO_Jd(bxInstruction_c *i)
 348 {
 349   if (! get_OF()) {
 350     Bit32u new_EIP = EIP + (Bit32s) i->Id();
 351     branch_near32(new_EIP);
 352     BX_INSTR_CNEAR_BRANCH_TAKEN(BX_CPU_ID, new_EIP);
 353   }
 354 #if BX_INSTRUMENTATION
 355   else {
 356     BX_INSTR_CNEAR_BRANCH_NOT_TAKEN(BX_CPU_ID);
 357   }
 358 #endif
 359 }
 360
 361 void BX_CPP_AttrRegparmN(1) BX_CPU_C::JB_Jd(bxInstruction_c *i)
 362 {
 363   if (get_CF()) {
 364     Bit32u new_EIP = EIP + (Bit32s) i->Id();
 365     branch_near32(new_EIP);
 366     BX_INSTR_CNEAR_BRANCH_TAKEN(BX_CPU_ID, new_EIP);
 367   }
 368 #if BX_INSTRUMENTATION
 369   else {
 370     BX_INSTR_CNEAR_BRANCH_NOT_TAKEN(BX_CPU_ID);
 371   }
 372 #endif
 373 }
 374
 375 void BX_CPP_AttrRegparmN(1) BX_CPU_C::JNB_Jd(bxInstruction_c *i)
 376 {
 377   if (! get_CF()) {
 378     Bit32u new_EIP = EIP + (Bit32s) i->Id();
 379     branch_near32(new_EIP);
 380     BX_INSTR_CNEAR_BRANCH_TAKEN(BX_CPU_ID, new_EIP);
 381   }
 382 #if BX_INSTRUMENTATION
 383   else {
 384     BX_INSTR_CNEAR_BRANCH_NOT_TAKEN(BX_CPU_ID);
 385   }
 386 #endif
 387 }
 388
 389 void BX_CPP_AttrRegparmN(1) BX_CPU_C::JZ_Jd(bxInstruction_c *i)
 390 {
 391   if (get_ZF()) {
 392     Bit32u new_EIP = EIP + (Bit32s) i->Id();
 393     branch_near32(new_EIP);
 394     BX_INSTR_CNEAR_BRANCH_TAKEN(BX_CPU_ID, new_EIP);
 395   }
 396 #if BX_INSTRUMENTATION
 397   else {
 398     BX_INSTR_CNEAR_BRANCH_NOT_TAKEN(BX_CPU_ID);
 399   }
 400 #endif
 401 }
 402
 403 void BX_CPP_AttrRegparmN(1) BX_CPU_C::JNZ_Jd(bxInstruction_c *i)
 404 {
 405   if (! get_ZF()) {
 406     Bit32u new_EIP = EIP + (Bit32s) i->Id();
 407     branch_near32(new_EIP);
 408     BX_INSTR_CNEAR_BRANCH_TAKEN(BX_CPU_ID, new_EIP);
 409   }
 410 #if BX_INSTRUMENTATION
 411   else {
 412     BX_INSTR_CNEAR_BRANCH_NOT_TAKEN(BX_CPU_ID);
 413   }
 414 #endif
 415 }
 416
 417 void BX_CPP_AttrRegparmN(1) BX_CPU_C::JBE_Jd(bxInstruction_c *i)
 418 {
 419   if (get_CF() || get_ZF()) {
 420     Bit32u new_EIP = EIP + (Bit32s) i->Id();
 421     branch_near32(new_EIP);
 422     BX_INSTR_CNEAR_BRANCH_TAKEN(BX_CPU_ID, new_EIP);
 423   }
 424 #if BX_INSTRUMENTATION
 425   else {
 426     BX_INSTR_CNEAR_BRANCH_NOT_TAKEN(BX_CPU_ID);
 427   }
 428 #endif
 429 }
 430
 431 void BX_CPP_AttrRegparmN(1) BX_CPU_C::JNBE_Jd(bxInstruction_c *i)
 432 {
 433   if (! (get_CF() || get_ZF())) {
 434     Bit32u new_EIP = EIP + (Bit32s) i->Id();
 435     branch_near32(new_EIP);
 436     BX_INSTR_CNEAR_BRANCH_TAKEN(BX_CPU_ID, new_EIP);
 437   }
 438 #if BX_INSTRUMENTATION
 439   else {
 440     BX_INSTR_CNEAR_BRANCH_NOT_TAKEN(BX_CPU_ID);
 441   }
 442 #endif
 443 }
 444
 445 void BX_CPP_AttrRegparmN(1) BX_CPU_C::JS_Jd(bxInstruction_c *i)
 446 {
 447   if (get_SF()) {
 448     Bit32u new_EIP = EIP + (Bit32s) i->Id();
 449     branch_near32(new_EIP);
 450     BX_INSTR_CNEAR_BRANCH_TAKEN(BX_CPU_ID, new_EIP);
 451   }
 452 #if BX_INSTRUMENTATION
 453   else {
 454     BX_INSTR_CNEAR_BRANCH_NOT_TAKEN(BX_CPU_ID);
 455   }
 456 #endif
 457 }
 458
 459 void BX_CPP_AttrRegparmN(1) BX_CPU_C::JNS_Jd(bxInstruction_c *i)
 460 {
 461   if (! get_SF()) {
 462     Bit32u new_EIP = EIP + (Bit32s) i->Id();
 463     branch_near32(new_EIP);
 464     BX_INSTR_CNEAR_BRANCH_TAKEN(BX_CPU_ID, new_EIP);
 465   }
 466 #if BX_INSTRUMENTATION
 467   else {
 468     BX_INSTR_CNEAR_BRANCH_NOT_TAKEN(BX_CPU_ID);
 469   }
 470 #endif
 471 }
 472
 473 void BX_CPP_AttrRegparmN(1) BX_CPU_C::JP_Jd(bxInstruction_c *i)
 474 {
 475   if (get_PF()) {
 476     Bit32u new_EIP = EIP + (Bit32s) i->Id();
 477     branch_near32(new_EIP);
 478     BX_INSTR_CNEAR_BRANCH_TAKEN(BX_CPU_ID, new_EIP);
 479   }
 480 #if BX_INSTRUMENTATION
 481   else {
 482     BX_INSTR_CNEAR_BRANCH_NOT_TAKEN(BX_CPU_ID);
 483   }
 484 #endif
 485 }
 486
 487 void BX_CPP_AttrRegparmN(1) BX_CPU_C::JNP_Jd(bxInstruction_c *i)
 488 {
 489   if (! get_PF()) {
 490     Bit32u new_EIP = EIP + (Bit32s) i->Id();
 491     branch_near32(new_EIP);
 492     BX_INSTR_CNEAR_BRANCH_TAKEN(BX_CPU_ID, new_EIP);
 493   }
 494 #if BX_INSTRUMENTATION
 495   else {
 496     BX_INSTR_CNEAR_BRANCH_NOT_TAKEN(BX_CPU_ID);
 497   }
 498 #endif
 499 }
 500
 501 void BX_CPP_AttrRegparmN(1) BX_CPU_C::JL_Jd(bxInstruction_c *i)
 502 {
 503   if (getB_SF() != getB_OF()) {
 504     Bit32u new_EIP = EIP + (Bit32s) i->Id();
 505     branch_near32(new_EIP);
 506     BX_INSTR_CNEAR_BRANCH_TAKEN(BX_CPU_ID, new_EIP);
 507   }
 508 #if BX_INSTRUMENTATION
 509   else {
 510     BX_INSTR_CNEAR_BRANCH_NOT_TAKEN(BX_CPU_ID);
 511   }
 512 #endif
 513 }
 514
 515 void BX_CPP_AttrRegparmN(1) BX_CPU_C::JNL_Jd(bxInstruction_c *i)
 516 {
 517   if (getB_SF() == getB_OF()) {
 518     Bit32u new_EIP = EIP + (Bit32s) i->Id();
 519     branch_near32(new_EIP);
 520     BX_INSTR_CNEAR_BRANCH_TAKEN(BX_CPU_ID, new_EIP);
 521   }
 522 #if BX_INSTRUMENTATION
 523   else {
 524     BX_INSTR_CNEAR_BRANCH_NOT_TAKEN(BX_CPU_ID);
 525   }
 526 #endif
 527 }
 528
 529 void BX_CPP_AttrRegparmN(1) BX_CPU_C::JLE_Jd(bxInstruction_c *i)
 530 {
 531   if (get_ZF() || (getB_SF() != getB_OF())) {
 532     Bit32u new_EIP = EIP + (Bit32s) i->Id();
 533     branch_near32(new_EIP);
 534     BX_INSTR_CNEAR_BRANCH_TAKEN(BX_CPU_ID, new_EIP);
 535   }
 536 #if BX_INSTRUMENTATION
 537   else {
 538     BX_INSTR_CNEAR_BRANCH_NOT_TAKEN(BX_CPU_ID);
 539   }
 540 #endif
 541 }
 542
 543 void BX_CPP_AttrRegparmN(1) BX_CPU_C::JNLE_Jd(bxInstruction_c *i)
 544 {
 545   if (! get_ZF() && (getB_SF() == getB_OF())) {
 546     Bit32u new_EIP = EIP + (Bit32s) i->Id();
 547     branch_near32(new_EIP);
 548     BX_INSTR_CNEAR_BRANCH_TAKEN(BX_CPU_ID, new_EIP);
 549   }
 550 #if BX_INSTRUMENTATION
 551   else {
 552     BX_INSTR_CNEAR_BRANCH_NOT_TAKEN(BX_CPU_ID);
 553   }
 554 #endif
 555 }
 556
 557 void BX_CPP_AttrRegparmN(1) BX_CPU_C::JMP_Ap(bxInstruction_c *i)
 558 {
 559   BX_ASSERT(BX_CPU_THIS_PTR cpu_mode != BX_MODE_LONG_64);
 560
 561   Bit32u disp32;
 562   Bit16u cs_raw;
 563
 564   invalidate_prefetch_q();
 565
 566   if (i->os32L()) {
 567     disp32 = i->Id();
 568   }
 569   else {
 570     disp32 = i->Iw();
 571   }
 572   cs_raw = i->Iw2();
 573
 574   // jump_protected doesn't affect ESP so it is ESP safe
 575   if (protected_mode()) {
 576     BX_CPU_THIS_PTR jump_protected(i, cs_raw, disp32);
 577     goto done;
 578   }
 579
 580   // CS.LIMIT can't change when in real/v8086 mode
 581   if (disp32 > BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.limit_scaled) {
 582     BX_ERROR(("JMP_Ap: instruction pointer not within code segment limits"));
 583     exception(BX_GP_EXCEPTION, 0, 0);
 584   }
 585
 586   load_seg_reg(&BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS], cs_raw);
 587   EIP = disp32;
 588
 589 done:
 590   BX_INSTR_FAR_BRANCH(BX_CPU_ID, BX_INSTR_IS_JMP,
 591                       BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value, EIP);
 592 }
 593
 594 void BX_CPP_AttrRegparmN(1) BX_CPU_C::JMP_EdR(bxInstruction_c *i)
 595 {
 596   Bit32u new_EIP = BX_READ_32BIT_REG(i->rm());
 597   branch_near32(new_EIP);
 598   BX_INSTR_UCNEAR_BRANCH(BX_CPU_ID, BX_INSTR_IS_JMP, new_EIP);
 599 }
 600
 601 /* Far indirect jump */
 602 void BX_CPP_AttrRegparmN(1) BX_CPU_C::JMP32_Ep(bxInstruction_c *i)
 603 {
 604   Bit16u cs_raw;
 605   Bit32u op1_32;
 606
 607   invalidate_prefetch_q();
 608
 609   bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
 610
 611   /* pointer, segment address pair */
 612   op1_32 = read_virtual_dword(i->seg(), eaddr);
 613   cs_raw = read_virtual_word (i->seg(), eaddr+4);
 614
 615   // jump_protected doesn't affect RSP so it is RSP safe
 616   if (protected_mode()) {
 617     BX_CPU_THIS_PTR jump_protected(i, cs_raw, op1_32);
 618     goto done;
 619   }
 620
 621   // CS.LIMIT can't change when in real/v8086 mode
 622   if (op1_32 > BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.limit_scaled) {
 623     BX_ERROR(("JMP32_Ep: instruction pointer not within code segment limits"));
 624     exception(BX_GP_EXCEPTION, 0, 0);
 625   }
 626
 627   load_seg_reg(&BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS], cs_raw);
 628   EIP = op1_32;
 629
 630 done:
 631   BX_INSTR_FAR_BRANCH(BX_CPU_ID, BX_INSTR_IS_JMP,
 632                       BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value, EIP);
 633 }
 634
 635 void BX_CPP_AttrRegparmN(1) BX_CPU_C::IRET32(bxInstruction_c *i)
 636 {
 637   BX_ASSERT(BX_CPU_THIS_PTR cpu_mode != BX_MODE_LONG_64);
 638
 639   Bit32u eip, eflags32;
 640   Bit16u cs_raw;
 641
 642   invalidate_prefetch_q();
 643
 644 #if BX_DEBUGGER
 645   BX_CPU_THIS_PTR show_flag |= Flag_iret;
 646 #endif
 647
 648   BX_CPU_THIS_PTR nmi_disable = 0;
 649
 650   BX_CPU_THIS_PTR speculative_rsp = 1;
 651   BX_CPU_THIS_PTR prev_rsp = ESP;
 652
 653   if (v8086_mode()) {
 654     // IOPL check in stack_return_from_v86()
 655     iret32_stack_return_from_v86(i);
 656     goto done;
 657   }
 658
 659   if (protected_mode()) {
 660     iret_protected(i);
 661     goto done;
 662   }
 663
 664   eip      =          pop_32();
 665   cs_raw   = (Bit16u) pop_32(); // #SS has higher priority
 666   eflags32 =          pop_32();
 667
 668   // CS.LIMIT can't change when in real/v8086 mode
 669   if (eip > BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.limit_scaled) {
 670     BX_ERROR(("IRET32: instruction pointer not within code segment limits"));
 671     exception(BX_GP_EXCEPTION, 0, 0);
 672   }
 673
 674   load_seg_reg(&BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS], cs_raw);
 675   EIP = eip;
 676   writeEFlags(eflags32, 0x00257fd5); // VIF, VIP, VM unchanged
 677
 678 done:
 679   BX_CPU_THIS_PTR speculative_rsp = 0;
 680
 681   BX_INSTR_FAR_BRANCH(BX_CPU_ID, BX_INSTR_IS_IRET,
 682                       BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value, EIP);
 683 }
 684
 685 void BX_CPP_AttrRegparmN(1) BX_CPU_C::JECXZ_Jb(bxInstruction_c *i)
 686 {
 687   // it is impossible to get this instruction in long mode
 688   BX_ASSERT(i->as64L() == 0);
 689
 690   Bit32u temp_ECX;
 691
 692   if (i->as32L())
 693     temp_ECX = ECX;
 694   else
 695     temp_ECX = CX;
 696
 697   if (temp_ECX == 0) {
 698     Bit32u new_EIP = EIP + (Bit32s) i->Id();
 699     branch_near32(new_EIP);
 700     BX_INSTR_CNEAR_BRANCH_TAKEN(BX_CPU_ID, new_EIP);
 701   }
 702 #if BX_INSTRUMENTATION
 703   else {
 704     BX_INSTR_CNEAR_BRANCH_NOT_TAKEN(BX_CPU_ID);
 705   }
 706 #endif
 707 }
 708
 709 //
 710 // There is some weirdness in LOOP instructions definition. If an exception
 711 // was generated during the instruction execution (for example #GP fault
 712 // because EIP was beyond CS segment limits) CPU state should restore the
 713 // state prior to instruction execution.
 714 //
 715 // The final point that we are not allowed to decrement ECX register before
 716 // it is known that no exceptions can happen.
 717 //
 718
 719 void BX_CPP_AttrRegparmN(1) BX_CPU_C::LOOPNE32_Jb(bxInstruction_c *i)
 720 {
 721   // it is impossible to get this instruction in long mode
 722   BX_ASSERT(i->as64L() == 0);
 723
 724   if (i->as32L()) {
 725     Bit32u count = ECX;
 726
 727     count--;
 728     if (count != 0 && (get_ZF()==0)) {
 729       Bit32u new_EIP = EIP + (Bit32s) i->Id();
 730       branch_near32(new_EIP);
 731       BX_INSTR_CNEAR_BRANCH_TAKEN(BX_CPU_ID, new_EIP);
 732     }
 733 #if BX_INSTRUMENTATION
 734     else {
 735       BX_INSTR_CNEAR_BRANCH_NOT_TAKEN(BX_CPU_ID);
 736     }
 737 #endif
 738
 739     ECX = count;
 740   }
 741   else {
 742     Bit16u count = CX;
 743
 744     count--;
 745     if (count != 0 && (get_ZF()==0)) {
 746       Bit32u new_EIP = EIP + (Bit32s) i->Id();
 747       branch_near32(new_EIP);
 748       BX_INSTR_CNEAR_BRANCH_TAKEN(BX_CPU_ID, new_EIP);
 749     }
 750 #if BX_INSTRUMENTATION
 751     else {
 752       BX_INSTR_CNEAR_BRANCH_NOT_TAKEN(BX_CPU_ID);
 753     }
 754 #endif
 755
 756     CX = count;
 757   }
 758 }
 759
 760 void BX_CPP_AttrRegparmN(1) BX_CPU_C::LOOPE32_Jb(bxInstruction_c *i)
 761 {
 762   // it is impossible to get this instruction in long mode
 763   BX_ASSERT(i->as64L() == 0);
 764
 765   if (i->as32L()) {
 766     Bit32u count = ECX;
 767
 768     count--;
 769     if (count != 0 && get_ZF()) {
 770       Bit32u new_EIP = EIP + (Bit32s) i->Id();
 771       branch_near32(new_EIP);
 772       BX_INSTR_CNEAR_BRANCH_TAKEN(BX_CPU_ID, new_EIP);
 773     }
 774 #if BX_INSTRUMENTATION
 775     else {
 776       BX_INSTR_CNEAR_BRANCH_NOT_TAKEN(BX_CPU_ID);
 777     }
 778 #endif
 779
 780     ECX = count;
 781   }
 782   else {
 783     Bit16u count = CX;
 784
 785     count--;
 786     if (count != 0 && get_ZF()) {
 787       Bit32u new_EIP = EIP + (Bit32s) i->Id();
 788       branch_near32(new_EIP);
 789       BX_INSTR_CNEAR_BRANCH_TAKEN(BX_CPU_ID, new_EIP);
 790     }
 791 #if BX_INSTRUMENTATION
 792     else {
 793       BX_INSTR_CNEAR_BRANCH_NOT_TAKEN(BX_CPU_ID);
 794     }
 795 #endif
 796
 797     CX = count;
 798   }
 799 }
 800
 801 void BX_CPP_AttrRegparmN(1) BX_CPU_C::LOOP32_Jb(bxInstruction_c *i)
 802 {
 803   // it is impossible to get this instruction in long mode
 804   BX_ASSERT(i->as64L() == 0);
 805
 806   if (i->as32L()) {
 807     Bit32u count = ECX;
 808
 809     count--;
 810     if (count != 0) {
 811       Bit32u new_EIP = EIP + (Bit32s) i->Id();
 812       branch_near32(new_EIP);
 813       BX_INSTR_CNEAR_BRANCH_TAKEN(BX_CPU_ID, new_EIP);
 814     }
 815 #if BX_INSTRUMENTATION
 816     else {
 817       BX_INSTR_CNEAR_BRANCH_NOT_TAKEN(BX_CPU_ID);
 818     }
 819 #endif
 820
 821     ECX = count;
 822   }
 823   else {
 824     Bit16u count = CX;
 825
 826     count--;
 827     if (count != 0) {
 828       Bit32u new_EIP = EIP + (Bit32s) i->Id();
 829       branch_near32(new_EIP);
 830       BX_INSTR_CNEAR_BRANCH_TAKEN(BX_CPU_ID, new_EIP);
 831     }
 832 #if BX_INSTRUMENTATION
 833     else {
 834       BX_INSTR_CNEAR_BRANCH_NOT_TAKEN(BX_CPU_ID);
 835     }
 836 #endif
 837
 838     CX = count;
 839   }
 840 }
 841
 842 #endif