cpu/mult16.cc

   1 /////////////////////////////////////////////////////////////////////////
   2 // $Id: mult16.cc,v 1.21 2006/03/06 22:03:01 sshwarts Exp $
   3 /////////////////////////////////////////////////////////////////////////
   4 //
   5 //  Copyright (C) 2001  MandrakeSoft S.A.
   6 //
   7 //    MandrakeSoft S.A.
   8 //    43, rue d'Aboukir
   9 //    75002 Paris - France
  10 //    http://www.linux-mandrake.com/
  11 //    http://www.mandrakesoft.com/
  12 //
  13 //  This library is free software; you can redistribute it and/or
  14 //  modify it under the terms of the GNU Lesser General Public
  15 //  License as published by the Free Software Foundation; either
  16 //  version 2 of the License, or (at your option) any later version.
  17 //
  18 //  This library is distributed in the hope that it will be useful,
  19 //  but WITHOUT ANY WARRANTY; without even the implied warranty of
  20 //  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  21 //  Lesser General Public License for more details.
  22 //
  23 //  You should have received a copy of the GNU Lesser General Public
  24 //  License along with this library; if not, write to the Free Software
  25 //  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  26
  27
  28 #define NEED_CPU_REG_SHORTCUTS 1
  29 #include "bochs.h"
  30 #include "cpu.h"
  31 #define LOG_THIS BX_CPU_THIS_PTR
  32
  33
  34 void BX_CPU_C::MUL_AXEw(bxInstruction_c *i)
  35 {
  36   Bit16u op1_16, op2_16;
  37
  38   op1_16 = AX;
  39
  40   /* op2 is a register or memory reference */
  41   if (i->modC0()) {
  42     op2_16 = BX_READ_16BIT_REG(i->rm());
  43   }
  44   else {
  45     /* pointer, segment address pair */
  46     read_virtual_word(i->seg(), RMAddr(i), &op2_16);
  47   }
  48
  49   Bit32u product_32  = ((Bit32u) op1_16) * ((Bit32u) op2_16);
  50   Bit16u product_16l = (product_32 & 0xFFFF);
  51   Bit16u product_16h =  product_32 >> 16;
  52
  53   /* set EFLAGS */
  54   SET_FLAGS_OSZAPC_S1S2_16(product_16l, product_16h, BX_INSTR_MUL16);
  55
  56   /* now write product back to destination */
  57   AX = product_16l;
  58   DX = product_16h;
  59 }
  60
  61 void BX_CPU_C::IMUL_AXEw(bxInstruction_c *i)
  62 {
  63   Bit16s op1_16, op2_16;
  64
  65   op1_16 = AX;
  66
  67   /* op2 is a register or memory reference */
  68   if (i->modC0()) {
  69     op2_16 = BX_READ_16BIT_REG(i->rm());
  70   }
  71   else {
  72     /* pointer, segment address pair */
  73     read_virtual_word(i->seg(), RMAddr(i), (Bit16u *) &op2_16);
  74   }
  75
  76   Bit32s product_32  = ((Bit32s) op1_16) * ((Bit32s) op2_16);
  77   Bit16u product_16l = (product_32 & 0xFFFF);
  78   Bit16u product_16h = product_32 >> 16;
  79
  80   /* now write product back to destination */
  81   AX = product_16l;
  82   DX = product_16h;
  83
  84   /* set eflags:
  85    * IMUL r/m16: condition for clearing CF & OF:
  86    *   DX:AX = sign-extend of AX
  87    */
  88   SET_FLAGS_OSZAPC_S1S2_16(product_16l, product_16h, BX_INSTR_IMUL16);
  89 }
  90
  91 void BX_CPU_C::DIV_AXEw(bxInstruction_c *i)
  92 {
  93   Bit16u op2_16, remainder_16, quotient_16l;
  94   Bit32u op1_32, quotient_32;
  95
  96   op1_32 = (((Bit32u) DX) << 16) | ((Bit32u) AX);
  97
  98   /* op2 is a register or memory reference */
  99   if (i->modC0()) {
 100     op2_16 = BX_READ_16BIT_REG(i->rm());
 101   }
 102   else {
 103     /* pointer, segment address pair */
 104     read_virtual_word(i->seg(), RMAddr(i), &op2_16);
 105   }
 106
 107   if (op2_16 == 0)
 108     exception(BX_DE_EXCEPTION, 0, 0);
 109
 110   quotient_32  = op1_32 / op2_16;
 111   remainder_16 = op1_32 % op2_16;
 112   quotient_16l = quotient_32 & 0xFFFF;
 113
 114   if (quotient_32 != quotient_16l)
 115     exception(BX_DE_EXCEPTION, 0, 0);
 116
 117   /* set EFLAGS:
 118    * DIV affects the following flags: O,S,Z,A,P,C are undefined
 119    */
 120
 121 #if INTEL_DIV_FLAG_BUG == 1
 122   assert_CF();
 123 #endif
 124
 125   /* now write quotient back to destination */
 126   AX = quotient_16l;
 127   DX = remainder_16;
 128 }
 129
 130 void BX_CPU_C::IDIV_AXEw(bxInstruction_c *i)
 131 {
 132   Bit16s op2_16, remainder_16, quotient_16l;
 133   Bit32s op1_32, quotient_32;
 134
 135   op1_32 = ((((Bit32u) DX) << 16) | ((Bit32u) AX));
 136
 137   /* op2 is a register or memory reference */
 138   if (i->modC0()) {
 139     op2_16 = BX_READ_16BIT_REG(i->rm());
 140   }
 141   else {
 142     /* pointer, segment address pair */
 143     read_virtual_word(i->seg(), RMAddr(i), (Bit16u *) &op2_16);
 144   }
 145
 146   if (op2_16 == 0)
 147     exception(BX_DE_EXCEPTION, 0, 0);
 148
 149   /* check MIN_INT divided by -1 case */
 150   if ((op1_32 == ((Bit32s)0x80000000)) && (op2_16 == -1))
 151     exception(BX_DE_EXCEPTION, 0, 0);
 152
 153   quotient_32  = op1_32 / op2_16;
 154   remainder_16 = op1_32 % op2_16;
 155   quotient_16l = quotient_32 & 0xFFFF;
 156
 157   if (quotient_32 != quotient_16l)
 158     exception(BX_DE_EXCEPTION, 0, 0);
 159
 160   /* set EFLAGS:
 161    * IDIV affects the following flags: O,S,Z,A,P,C are undefined
 162    */
 163
 164 #if INTEL_DIV_FLAG_BUG == 1
 165   assert_CF();
 166 #endif
 167
 168   /* now write quotient back to destination */
 169   AX = quotient_16l;
 170   DX = remainder_16;
 171 }
 172
 173 void BX_CPU_C::IMUL_GwEwIw(bxInstruction_c *i)
 174 {
 175   Bit16s op2_16, op3_16;
 176
 177   op3_16 = i->Iw();
 178
 179   /* op2 is a register or memory reference */
 180   if (i->modC0()) {
 181     op2_16 = BX_READ_16BIT_REG(i->rm());
 182   }
 183   else {
 184     /* pointer, segment address pair */
 185     read_virtual_word(i->seg(), RMAddr(i), (Bit16u *) &op2_16);
 186   }
 187
 188   Bit32s product_32  = op2_16 * op3_16;
 189   Bit16u product_16l = (product_32 & 0xFFFF);
 190   Bit16u product_16h = (product_32 >> 16);
 191
 192   /* now write product back to destination */
 193   BX_WRITE_16BIT_REG(i->nnn(), product_16l);
 194
 195   /* set eflags:
 196    * IMUL r16,r/m16,imm16: condition for clearing CF & OF:
 197    *   result exactly fits within r16
 198    */
 199   SET_FLAGS_OSZAPC_S1S2_16(product_16l, product_16h, BX_INSTR_IMUL16);
 200 }
 201
 202 void BX_CPU_C::IMUL_GwEw(bxInstruction_c *i)
 203 {
 204   Bit16s op1_16, op2_16;
 205
 206   /* op2 is a register or memory reference */
 207   if (i->modC0()) {
 208     op2_16 = BX_READ_16BIT_REG(i->rm());
 209   }
 210   else {
 211     /* pointer, segment address pair */
 212     read_virtual_word(i->seg(), RMAddr(i), (Bit16u *) &op2_16);
 213   }
 214
 215   op1_16 = BX_READ_16BIT_REG(i->nnn());
 216
 217   Bit32s product_32  = op1_16 * op2_16;
 218   Bit16u product_16l = (product_32 & 0xFFFF);
 219   Bit16u product_16h = (product_32 >> 16);
 220
 221   /* now write product back to destination */
 222   BX_WRITE_16BIT_REG(i->nnn(), product_16l);
 223
 224   /* set eflags:
 225    * IMUL r16,r/m16,imm16: condition for clearing CF & OF:
 226    *   result exactly fits within r16
 227    */
 228   SET_FLAGS_OSZAPC_S1S2_16(product_16l, product_16h, BX_INSTR_IMUL16);
 229 }