iodev/pci.cc

   1 /////////////////////////////////////////////////////////////////////////
   2 // $Id: pci.cc,v 1.56 2008/01/26 22:24:02 sshwarts Exp $
   3 /////////////////////////////////////////////////////////////////////////
   4 //
   5 //  Copyright (C) 2002  MandrakeSoft S.A.
   6 //
   7 //    MandrakeSoft S.A.
   8 //    43, rue d'Aboukir
   9 //    75002 Paris - France
  10 //    http://www.linux-mandrake.com/
  11 //    http://www.mandrakesoft.com/
  12 //
  13 //  This library is free software; you can redistribute it and/or
  14 //  modify it under the terms of the GNU Lesser General Public
  15 //  License as published by the Free Software Foundation; either
  16 //  version 2 of the License, or (at your option) any later version.
  17 //
  18 //  This library is distributed in the hope that it will be useful,
  19 //  but WITHOUT ANY WARRANTY; without even the implied warranty of
  20 //  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  21 //  Lesser General Public License for more details.
  22 //
  23 //  You should have received a copy of the GNU Lesser General Public
  24 //  License along with this library; if not, write to the Free Software
  25 //  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  26
  27 //
  28 // i440FX Support - PMC/DBX
  29 //
  30
  31 // Define BX_PLUGGABLE in files that can be compiled into plugins.  For
  32 // platforms that require a special tag on exported symbols, BX_PLUGGABLE
  33 // is used to know when we are exporting symbols and when we are importing.
  34 #define BX_PLUGGABLE
  35
  36 #include "iodev.h"
  37 #if BX_SUPPORT_PCI
  38
  39 #define LOG_THIS thePciBridge->
  40
  41 bx_pci_bridge_c *thePciBridge = NULL;
  42
  43 int libpci_LTX_plugin_init(plugin_t *plugin, plugintype_t type, int argc, char *argv[])
  44 {
  45   thePciBridge = new bx_pci_bridge_c();
  46   bx_devices.pluginPciBridge = thePciBridge;
  47   BX_REGISTER_DEVICE_DEVMODEL(plugin, type, thePciBridge, BX_PLUGIN_PCI);
  48   return(0); // Success
  49 }
  50
  51 void libpci_LTX_plugin_fini(void)
  52 {
  53   delete thePciBridge;
  54 }
  55
  56 bx_pci_bridge_c::bx_pci_bridge_c()
  57 {
  58   put("PCI");
  59   settype(PCILOG);
  60 }
  61
  62 bx_pci_bridge_c::~bx_pci_bridge_c()
  63 {
  64   print_i440fx_state();
  65   BX_DEBUG(("Exit"));
  66 }
  67
  68 void bx_pci_bridge_c::init(void)
  69 {
  70   // called once when bochs initializes
  71   unsigned i;
  72   BX_PCI_THIS num_pci_handlers = 0;
  73
  74   /* set unused elements to appropriate values */
  75   for (i=0; i < BX_MAX_PCI_DEVICES; i++) {
  76     BX_PCI_THIS pci_handler[i].handler = NULL;
  77   }
  78
  79   for (i=0; i < 0x100; i++) {
  80     BX_PCI_THIS pci_handler_id[i] = BX_MAX_PCI_DEVICES;  // not assigned
  81   }
  82
  83   for (i=0; i < BX_N_PCI_SLOTS; i++) {
  84     BX_PCI_THIS slot_used[i] = 0;  // no device connected
  85   }
  86   BX_PCI_THIS slots_checked = 0;
  87
  88   // confAddr accepts dword i/o only
  89   DEV_register_ioread_handler(this, read_handler, 0x0CF8, "i440FX", 4);
  90   DEV_register_iowrite_handler(this, write_handler, 0x0CF8, "i440FX", 4);
  91
  92   for (i=0x0CFC; i<=0x0CFF; i++) {
  93     DEV_register_ioread_handler(this, read_handler, i, "i440FX", 7);
  94   }
  95   for (i=0x0CFC; i<=0x0CFF; i++) {
  96     DEV_register_iowrite_handler(this, write_handler, i, "i440FX", 7);
  97   }
  98
  99   Bit8u devfunc = BX_PCI_DEVICE(0,0);
 100   DEV_register_pci_handlers(this, &devfunc, BX_PLUGIN_PCI, "440FX Host bridge");
 101
 102   for (i=0; i<256; i++)
 103     BX_PCI_THIS s.i440fx.pci_conf[i] = 0x0;
 104   // readonly registers
 105   BX_PCI_THIS s.i440fx.pci_conf[0x00] = 0x86;
 106   BX_PCI_THIS s.i440fx.pci_conf[0x01] = 0x80;
 107   BX_PCI_THIS s.i440fx.pci_conf[0x02] = 0x37;
 108   BX_PCI_THIS s.i440fx.pci_conf[0x03] = 0x12;
 109   BX_PCI_THIS s.i440fx.pci_conf[0x0b] = 0x06;
 110 }
 111
 112   void
 113 bx_pci_bridge_c::reset(unsigned type)
 114 {
 115   unsigned i;
 116   char devname[80];
 117   char *device;
 118
 119   if (!BX_PCI_THIS slots_checked) {
 120     for (i=0; i<BX_N_PCI_SLOTS; i++) {
 121       sprintf(devname, "pci.slot.%d", i+1);
 122       device = SIM->get_param_string(devname)->getptr();
 123       if ((strlen(device) > 0) && !BX_PCI_THIS slot_used[i]) {
 124         BX_PANIC(("Unknown plugin '%s' at PCI slot #%d", device, i+1));
 125       }
 126     }
 127     BX_PCI_THIS slots_checked = 1;
 128   }
 129
 130   BX_PCI_THIS s.i440fx.confAddr = 0;
 131   BX_PCI_THIS s.i440fx.confData = 0;
 132
 133   BX_PCI_THIS s.i440fx.pci_conf[0x04] = 0x06;
 134   BX_PCI_THIS s.i440fx.pci_conf[0x05] = 0x00;
 135   BX_PCI_THIS s.i440fx.pci_conf[0x06] = 0x80;
 136   BX_PCI_THIS s.i440fx.pci_conf[0x07] = 0x02;
 137   BX_PCI_THIS s.i440fx.pci_conf[0x0d] = 0x00;
 138   BX_PCI_THIS s.i440fx.pci_conf[0x0f] = 0x00;
 139   BX_PCI_THIS s.i440fx.pci_conf[0x50] = 0x00;
 140   BX_PCI_THIS s.i440fx.pci_conf[0x51] = 0x01;
 141   BX_PCI_THIS s.i440fx.pci_conf[0x52] = 0x00;
 142   BX_PCI_THIS s.i440fx.pci_conf[0x53] = 0x80;
 143   BX_PCI_THIS s.i440fx.pci_conf[0x54] = 0x00;
 144   BX_PCI_THIS s.i440fx.pci_conf[0x55] = 0x00;
 145   BX_PCI_THIS s.i440fx.pci_conf[0x56] = 0x00;
 146   BX_PCI_THIS s.i440fx.pci_conf[0x57] = 0x01;
 147   BX_PCI_THIS s.i440fx.pci_conf[0x58] = 0x10;
 148   for (i=0x59; i<0x60; i++)
 149     BX_PCI_THIS s.i440fx.pci_conf[i] = 0x00;
 150   BX_PCI_THIS s.i440fx.pci_conf[0x72] = 0x02;
 151 }
 152
 153 void bx_pci_bridge_c::register_state(void)
 154 {
 155   bx_list_c *list = new bx_list_c(SIM->get_bochs_root(), "pci_bridge", "PCI Bridge State", 3);
 156   BXRS_HEX_PARAM_FIELD(list, confAddr, BX_PCI_THIS s.i440fx.confAddr);
 157   BXRS_HEX_PARAM_FIELD(list, confData, BX_PCI_THIS s.i440fx.confData);
 158   bx_list_c *pci_conf = new bx_list_c(list, "pci_conf", 256);
 159   for (unsigned i=0; i<256; i++) {
 160     char name[6];
 161     sprintf(name, "0x%02x", i);
 162     new bx_shadow_num_c(pci_conf, name, &BX_PCI_THIS s.i440fx.pci_conf[i], BASE_HEX);
 163   }
 164 }
 165
 166 void bx_pci_bridge_c::after_restore_state(void)
 167 {
 168   BX_PCI_THIS smram_control(BX_PCI_THIS s.i440fx.pci_conf[0x72]);
 169 }
 170
 171 // static IO port read callback handler
 172 // redirects to non-static class handler to avoid virtual functions
 173
 174 Bit32u bx_pci_bridge_c::read_handler(void *this_ptr, Bit32u address, unsigned io_len)
 175 {
 176 #if !BX_USE_PCI_SMF
 177   bx_pci_bridge_c *class_ptr = (bx_pci_bridge_c *) this_ptr;
 178   return class_ptr->read(address, io_len);
 179 }
 180
 181 Bit32u bx_pci_bridge_c::read(Bit32u address, unsigned io_len)
 182 {
 183 #else
 184   UNUSED(this_ptr);
 185 #endif // !BX_USE_PCI_SMF
 186
 187   switch (address) {
 188     case 0x0CF8:
 189       return BX_PCI_THIS s.i440fx.confAddr;
 190     case 0x0CFC:
 191     case 0x0CFD:
 192     case 0x0CFE:
 193     case 0x0CFF:
 194     {
 195       Bit32u handle, retval;
 196       Bit8u devfunc, regnum;
 197
 198       if ((BX_PCI_THIS s.i440fx.confAddr & 0x80FF0000) == 0x80000000) {
 199         devfunc = (BX_PCI_THIS s.i440fx.confAddr >> 8) & 0xff;
 200         regnum = (BX_PCI_THIS s.i440fx.confAddr & 0xfc) + (address & 0x03);
 201         handle = BX_PCI_THIS pci_handler_id[devfunc];
 202         if ((io_len <= 4) && (handle < BX_MAX_PCI_DEVICES))
 203           retval = BX_PCI_THIS pci_handler[handle].handler->pci_read_handler(regnum, io_len);
 204         else
 205           retval = 0xFFFFFFFF;
 206       }
 207       else
 208         retval = 0xFFFFFFFF;
 209       BX_PCI_THIS s.i440fx.confData = retval;
 210       return retval;
 211     }
 212   }
 213
 214   BX_PANIC(("unsupported IO read to port 0x%x", (unsigned) address));
 215   return(0xffffffff);
 216 }
 217
 218 // static IO port write callback handler
 219 // redirects to non-static class handler to avoid virtual functions
 220
 221 void bx_pci_bridge_c::write_handler(void *this_ptr, Bit32u address, Bit32u value, unsigned io_len)
 222 {
 223 #if !BX_USE_PCI_SMF
 224   bx_pci_bridge_c *class_ptr = (bx_pci_bridge_c *) this_ptr;
 225   class_ptr->write(address, value, io_len);
 226 }
 227
 228 void bx_pci_bridge_c::write(Bit32u address, Bit32u value, unsigned io_len)
 229 {
 230 #else
 231   UNUSED(this_ptr);
 232 #endif // !BX_USE_PCI_SMF
 233
 234   switch (address) {
 235     case 0xCF8:
 236       BX_PCI_THIS s.i440fx.confAddr = value;
 237       if ((value & 0x80FFFF00) == 0x80000000) {
 238         BX_DEBUG(("440FX PMC register 0x%02x selected", value & 0xfc));
 239       } else if ((value & 0x80000000) == 0x80000000) {
 240         BX_DEBUG(("440FX request for bus 0x%02x device 0x%02x function 0x%02x",
 241                   (value >> 16) & 0xFF, (value >> 11) & 0x1F, (value >> 8) & 0x07));
 242       }
 243       break;
 244
 245     case 0xCFC:
 246     case 0xCFD:
 247     case 0xCFE:
 248     case 0xCFF:
 249       if ((BX_PCI_THIS s.i440fx.confAddr & 0x80FF0000) == 0x80000000) {
 250         Bit8u devfunc = (BX_PCI_THIS s.i440fx.confAddr >> 8) & 0xff;
 251         Bit8u regnum = (BX_PCI_THIS s.i440fx.confAddr & 0xfc) + (address & 0x03);
 252         Bit32u handle = BX_PCI_THIS pci_handler_id[devfunc];
 253         if ((io_len <= 4) && (handle < BX_MAX_PCI_DEVICES)) {
 254           if (((regnum>=4) && (regnum<=7)) || (regnum==12) || (regnum==13) || (regnum>14)) {
 255             BX_PCI_THIS pci_handler[handle].handler->pci_write_handler(regnum, value, io_len);
 256             BX_PCI_THIS s.i440fx.confData = value << (8 * (address & 0x03));
 257           }
 258           else
 259             BX_DEBUG(("read only register, write ignored"));
 260         }
 261       }
 262       break;
 263
 264     default:
 265       BX_PANIC(("IO write to port 0x%x", (unsigned) address));
 266   }
 267 }
 268
 269 // pci configuration space read callback handler
 270 Bit32u bx_pci_bridge_c::pci_read_handler(Bit8u address, unsigned io_len)
 271 {
 272   Bit32u val440fx = 0;
 273
 274   if (io_len <= 4) {
 275     for (unsigned i=0; i<io_len; i++) {
 276       val440fx |= (BX_PCI_THIS s.i440fx.pci_conf[address+i] << (i*8));
 277     }
 278     BX_DEBUG(("440FX PMC read register 0x%02x value 0x%08x", address, val440fx));
 279     return val440fx;
 280   }
 281   else
 282     return(0xffffffff);
 283 }
 284
 285 // pci configuration space write callback handler
 286 void bx_pci_bridge_c::pci_write_handler(Bit8u address, Bit32u value, unsigned io_len)
 287 {
 288   Bit8u value8;
 289
 290   if ((address >= 0x10) && (address < 0x34))
 291     return;
 292   if (io_len <= 4) {
 293     for (unsigned i=0; i<io_len; i++) {
 294       value8 = (value >> (i*8)) & 0xFF;
 295       switch (address+i) {
 296         case 0x04:
 297           BX_PCI_THIS s.i440fx.pci_conf[address+i] = (value8 & 0x40) | 0x06;
 298           break;
 299         case 0x06:
 300         case 0x0c:
 301           break;
 302         case 0x59:
 303         case 0x5A:
 304         case 0x5B:
 305         case 0x5C:
 306         case 0x5D:
 307         case 0x5E:
 308         case 0x5F:
 309           BX_INFO(("440FX PMC write to PAM register %x (TLB Flush)", address+i));
 310           BX_PCI_THIS s.i440fx.pci_conf[address+i] = value8;
 311           bx_pc_system.MemoryMappingChanged();
 312           break;
 313         case 0x72:
 314           smram_control(value);  // SMRAM conrol register
 315           break;
 316         default:
 317           BX_PCI_THIS s.i440fx.pci_conf[address+i] = value8;
 318           BX_DEBUG(("440FX PMC write register 0x%02x value 0x%02x", address+i, value8));
 319       }
 320     }
 321   }
 322 }
 323
 324 void bx_pci_bridge_c::smram_control(Bit8u value8)
 325 {
 326   //
 327   // From i440FX chipset manual:
 328   //
 329   // [7:7] Reserved.
 330   // [6:6] SMM Space Open (DOPEN), when DOPEN=1 and DLCK=0, SMM space DRAM
 331   //       became visible even CPU not indicte SMM mode access. This is
 332   //       indended to help BIOS to initialize SMM space.
 333   // [5:5] SMM Space Closed (DCLS), when DCLS=1, SMM space is not accessible
 334   //       for data references, even if CPU indicates SMM mode access. Code
 335   //       references may still access SMM space DRAM.
 336   // [4:4] SMM Space Locked (DLCK), when DLCK=1, DOPEN is set to 0 and
 337   //       both DLCK and DOPEN became R/O. DLCK can only be cleared by
 338   //       a power-on reset.
 339   // [3:3] SMRAM Enable (SMRAME)
 340   // [2:0] SMM space base segment, program the location of SMM space
 341   //       reserved.
 342   //
 343
 344   // SMRAM space access cycles:
 345
 346   // | SMRAME | DLCK | DCLS | DOPEN | CPU_SMM |    | Code | Data |
 347   // ------------------------------------------    ---------------
 348   // |    0   |  X   |  X   |   X   |    X    | -> |  PCI |  PCI |
 349   // |    1   |  0   |  X   |   0   |    0    | -> |  PCI |  PCI |
 350   // |    1   |  0   |  0   |   0   |    1    | -> | DRAM | DRAM |
 351   // |    1   |  0   |  0   |   1   |    X    | -> | DRAM | DRAM |
 352   // |    1   |  1   |  0   |   X   |    1    | -> | DRAM | DRAM |
 353   // |    1   |  0   |  1   |   0   |    1    | -> | DRAM |  PCI |
 354   // |    1   |  0   |  1   |   1   |    X    | -> | ---- | ---- |
 355   // |    1   |  1   |  X   |   X   |    0    | -> |  PCI |  PCI |
 356   // |    1   |  1   |  1   |   X   |    1    | -> | DRAM |  PCI |
 357   // ------------------------------------------    ---------------
 358
 359   value8 = (value8 & 0x78) | 0x2; // ignore reserved bits
 360
 361   if (BX_PCI_THIS s.i440fx.pci_conf[0x72] & 0x10)
 362   {
 363     value8 &= 0xbf; // set DOPEN=0, DLCK=1
 364     value8 |= 0x10;
 365   }
 366
 367   if ((value8 & 0x08) == 0) {
 368     bx_devices.mem->disable_smram();
 369   }
 370   else {
 371     bx_bool DOPEN = (value8 & 0x40) > 0, DCLS = (value8 & 0x20) > 0;
 372     if(DOPEN && DCLS) BX_PANIC(("SMRAM control: DOPEN not mutually exclusive with DCLS !"));
 373     bx_devices.mem->enable_smram(DOPEN, DCLS);
 374   }
 375
 376   BX_INFO(("setting SMRAM control register to 0x%02x", value8));
 377   BX_PCI_THIS s.i440fx.pci_conf[0x72] = value8;
 378 }
 379
 380 Bit8u bx_pci_bridge_c::rd_memType(Bit32u addr)
 381 {
 382    switch ((addr & 0xFC000) >> 12) {
 383       case 0xC0:
 384            return (BX_PCI_THIS s.i440fx.pci_conf[0x5A] & 0x1);
 385       case 0xC4:
 386            return ((BX_PCI_THIS s.i440fx.pci_conf[0x5A] >> 4) & 0x1);
 387       case 0xC8:
 388            return (BX_PCI_THIS s.i440fx.pci_conf[0x5B] & 0x1);
 389       case 0xCC:
 390            return ((BX_PCI_THIS s.i440fx.pci_conf[0x5B] >> 4) & 0x1);
 391
 392       case 0xD0:
 393            return (BX_PCI_THIS s.i440fx.pci_conf[0x5C] & 0x1);
 394       case 0xD4:
 395            return ((BX_PCI_THIS s.i440fx.pci_conf[0x5C] >> 4) & 0x1);
 396       case 0xD8:
 397            return (BX_PCI_THIS s.i440fx.pci_conf[0x5D] & 0x1);
 398       case 0xDC:
 399            return ((BX_PCI_THIS s.i440fx.pci_conf[0x5D] >> 4) & 0x1);
 400
 401       case 0xE0:
 402            return (BX_PCI_THIS s.i440fx.pci_conf[0x5E] & 0x1);
 403       case 0xE4:
 404            return ((BX_PCI_THIS s.i440fx.pci_conf[0x5E] >> 4) & 0x1);
 405       case 0xE8:
 406            return (BX_PCI_THIS s.i440fx.pci_conf[0x5F] & 0x1);
 407       case 0xEC:
 408            return ((BX_PCI_THIS s.i440fx.pci_conf[0x5F] >> 4) & 0x1);
 409
 410       case 0xF0:
 411       case 0xF4:
 412       case 0xF8:
 413       case 0xFC:
 414            return ((BX_PCI_THIS s.i440fx.pci_conf[0x59] >> 4) & 0x1);
 415
 416       default:
 417            BX_PANIC(("rd_memType () Error: Memory Type not known !"));
 418            break;
 419    }
 420
 421    return(0); // keep compiler happy
 422 }
 423
 424 Bit8u bx_pci_bridge_c::wr_memType(Bit32u addr)
 425 {
 426    switch ((addr & 0xFC000) >> 12) {
 427       case 0xC0:
 428            return ((BX_PCI_THIS s.i440fx.pci_conf[0x5A] >> 1) & 0x1);
 429       case 0xC4:
 430            return ((BX_PCI_THIS s.i440fx.pci_conf[0x5A] >> 5) & 0x1);
 431       case 0xC8:
 432            return ((BX_PCI_THIS s.i440fx.pci_conf[0x5B] >> 1) & 0x1);
 433       case 0xCC:
 434            return ((BX_PCI_THIS s.i440fx.pci_conf[0x5B] >> 5) & 0x1);
 435
 436       case 0xD0:
 437            return ((BX_PCI_THIS s.i440fx.pci_conf[0x5C] >> 1) & 0x1);
 438       case 0xD4:
 439            return ((BX_PCI_THIS s.i440fx.pci_conf[0x5C] >> 5) & 0x1);
 440       case 0xD8:
 441            return ((BX_PCI_THIS s.i440fx.pci_conf[0x5D] >> 1) & 0x1);
 442       case 0xDC:
 443            return ((BX_PCI_THIS s.i440fx.pci_conf[0x5D] >> 5) & 0x1);
 444
 445       case 0xE0:
 446            return ((BX_PCI_THIS s.i440fx.pci_conf[0x5E] >> 1) & 0x1);
 447       case 0xE4:
 448            return ((BX_PCI_THIS s.i440fx.pci_conf[0x5E] >> 5) & 0x1);
 449       case 0xE8:
 450            return ((BX_PCI_THIS s.i440fx.pci_conf[0x5F] >> 1) & 0x1);
 451       case 0xEC:
 452            return ((BX_PCI_THIS s.i440fx.pci_conf[0x5F] >> 5) & 0x1);
 453
 454       case 0xF0:
 455       case 0xF4:
 456       case 0xF8:
 457       case 0xFC:
 458            return ((BX_PCI_THIS s.i440fx.pci_conf[0x59] >> 5) & 0x1);
 459
 460       default:
 461            BX_PANIC(("wr_memType () Error: Memory Type not known !"));
 462            break;
 463    }
 464
 465    return(0); // keep compiler happy
 466 }
 467
 468 void bx_pci_bridge_c::print_i440fx_state()
 469 {
 470   int i;
 471
 472   BX_DEBUG(("i440fxConfAddr:0x%08x", BX_PCI_THIS s.i440fx.confAddr));
 473   BX_DEBUG(("i440fxConfData:0x%08x", BX_PCI_THIS s.i440fx.confData));
 474
 475 #ifdef DUMP_FULL_I440FX
 476   for (i=0; i<256; i++) {
 477     BX_DEBUG(("i440fxArray%02x:0x%02x", i, BX_PCI_THIS s.i440fx.pci_conf[i]));
 478   }
 479 #else /* DUMP_FULL_I440FX */
 480   for (i=0x59; i<0x60; i++) {
 481     BX_DEBUG(("i440fxArray%02x:0x%02x", i, BX_PCI_THIS s.i440fx.pci_conf[i]));
 482   }
 483 #endif /* DUMP_FULL_I440FX */
 484 }
 485
 486 bx_bool bx_pci_bridge_c::register_pci_handlers(bx_pci_device_stub_c *dev,
 487                                         Bit8u *devfunc, const char *name,
 488                                         const char *descr)
 489 {
 490   unsigned i, handle;
 491   char devname[80];
 492   char *device;
 493
 494   if (strcmp(name, "pci") && strcmp(name, "pci2isa") && strcmp(name, "pci_ide")
 495       && (*devfunc == 0x00)) {
 496     for (i = 0; i < BX_N_PCI_SLOTS; i++) {
 497       sprintf(devname, "pci.slot.%d", i+1);
 498       device = SIM->get_param_string(devname)->getptr();
 499       if ((strlen(device) > 0) && (!strcmp(name, device))) {
 500         *devfunc = (i + 2) << 3;
 501         BX_PCI_THIS slot_used[i] = 1;
 502         BX_INFO(("PCI slot #%d used by plugin '%s'", i+1, name));
 503         break;
 504       }
 505     }
 506     if (*devfunc == 0x00) {
 507       BX_ERROR(("Plugin '%s' not connected to a PCI slot", name));
 508     }
 509   }
 510   /* check if device/function is available */
 511   if (BX_PCI_THIS pci_handler_id[*devfunc] == BX_MAX_PCI_DEVICES) {
 512     if (BX_PCI_THIS num_pci_handlers >= BX_MAX_PCI_DEVICES) {
 513       BX_INFO(("too many PCI devices installed."));
 514       BX_PANIC(("  try increasing BX_MAX_PCI_DEVICES"));
 515       return false;
 516     }
 517     handle = BX_PCI_THIS num_pci_handlers++;
 518     BX_PCI_THIS pci_handler[handle].handler = dev;
 519     BX_PCI_THIS pci_handler_id[*devfunc] = handle;
 520     BX_INFO(("%s present at device %d, function %d", descr, *devfunc >> 3,
 521              *devfunc & 0x07));
 522     return true; // device/function mapped successfully
 523   }
 524   else {
 525     return false; // device/function not available, return false.
 526   }
 527 }
 528
 529 bx_bool bx_pci_bridge_c::is_pci_device(const char *name)
 530 {
 531   unsigned i;
 532   char devname[80];
 533   char *device;
 534
 535   for (i = 0; i < BX_N_PCI_SLOTS; i++) {
 536     sprintf(devname, "pci.slot.%d", i+1);
 537     device = SIM->get_param_string(devname)->getptr();
 538     if ((strlen(device) > 0) && (!strcmp(name, device))) {
 539       return 1;
 540     }
 541   }
 542   return 0;
 543 }
 544
 545 bx_bool bx_pci_bridge_c::pci_set_base_mem(void *this_ptr, memory_handler_t f1, memory_handler_t f2,
 546                            Bit32u *addr, Bit8u *pci_conf, unsigned size)
 547 {
 548   Bit32u newbase;
 549
 550   Bit32u oldbase = *addr;
 551   Bit32u mask = ~(size - 1);
 552   Bit8u pci_flags = pci_conf[0x00] & 0x0f;
 553   pci_conf[0x00] &= (mask & 0xf0);
 554   pci_conf[0x01] &= (mask >> 8) & 0xff;
 555   pci_conf[0x02] &= (mask >> 16) & 0xff;
 556   pci_conf[0x03] &= (mask >> 24) & 0xff;
 557   ReadHostDWordFromLittleEndian(pci_conf, newbase);
 558   pci_conf[0x00] |= pci_flags;
 559   if ((newbase != mask) && (newbase != oldbase)) { // skip PCI probe
 560     if (oldbase > 0) {
 561       DEV_unregister_memory_handlers(f1, f2, oldbase, oldbase + size - 1);
 562     }
 563     if (newbase > 0) {
 564       DEV_register_memory_handlers(this_ptr, f1, f2, newbase, newbase + size - 1);
 565     }
 566     *addr = newbase;
 567     return 1;
 568   }
 569   return 0;
 570 }
 571
 572 bx_bool bx_pci_bridge_c::pci_set_base_io(void *this_ptr, bx_read_handler_t f1, bx_write_handler_t f2,
 573                           Bit32u *addr, Bit8u *pci_conf, unsigned size,
 574                           const Bit8u *iomask, const char *name)
 575 {
 576   unsigned i;
 577   Bit32u newbase;
 578
 579   Bit32u oldbase = *addr;
 580   Bit16u mask = ~(size - 1);
 581   Bit8u pci_flags = pci_conf[0x00] & 0x03;
 582   pci_conf[0x00] &= (mask & 0xfc);
 583   pci_conf[0x01] &= (mask >> 8);
 584   ReadHostDWordFromLittleEndian(pci_conf, newbase);
 585   pci_conf[0x00] |= pci_flags;
 586   if (((newbase & 0xfffc) != mask) && (newbase != oldbase)) { // skip PCI probe
 587     if (oldbase > 0) {
 588       for (i=0; i<size; i++) {
 589         if (iomask[i] > 0) {
 590           DEV_unregister_ioread_handler(this_ptr, f1, oldbase + i, iomask[i]);
 591           DEV_unregister_iowrite_handler(this_ptr, f2, oldbase + i, iomask[i]);
 592         }
 593       }
 594     }
 595     if (newbase > 0) {
 596       for (i=0; i<size; i++) {
 597         if (iomask[i] > 0) {
 598           DEV_register_ioread_handler(this_ptr, f1, newbase + i, name, iomask[i]);
 599           DEV_register_iowrite_handler(this_ptr, f2, newbase + i, name, iomask[i]);
 600         }
 601       }
 602     }
 603     *addr = newbase;
 604     return 1;
 605   }
 606   return 0;
 607 }
 608
 609 #endif /* BX_SUPPORT_PCI */