cpu/debugstuff.cc

   1 /////////////////////////////////////////////////////////////////////////
   2 // $Id: debugstuff.cc,v 1.99 2008/12/06 10:21:55 sshwarts Exp $
   3 /////////////////////////////////////////////////////////////////////////
   4 //
   5 //  Copyright (C) 2001  MandrakeSoft S.A.
   6 //
   7 //    MandrakeSoft S.A.
   8 //    43, rue d'Aboukir
   9 //    75002 Paris - France
  10 //    http://www.linux-mandrake.com/
  11 //    http://www.mandrakesoft.com/
  12 //
  13 //  This library is free software; you can redistribute it and/or
  14 //  modify it under the terms of the GNU Lesser General Public
  15 //  License as published by the Free Software Foundation; either
  16 //  version 2 of the License, or (at your option) any later version.
  17 //
  18 //  This library is distributed in the hope that it will be useful,
  19 //  but WITHOUT ANY WARRANTY; without even the implied warranty of
  20 //  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  21 //  Lesser General Public License for more details.
  22 //
  23 //  You should have received a copy of the GNU Lesser General Public
  24 //  License along with this library; if not, write to the Free Software
  25 //  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  26 //
  27 /////////////////////////////////////////////////////////////////////////
  28
  29 #define NEED_CPU_REG_SHORTCUTS 1
  30 #include "bochs.h"
  31 #include "cpu.h"
  32 #define LOG_THIS BX_CPU_THIS_PTR
  33
  34 #if BX_DISASM
  35
  36 void BX_CPU_C::debug_disasm_instruction(bx_address offset)
  37 {
  38 #if BX_DEBUGGER
  39   bx_dbg_disassemble_current(BX_CPU_ID, 1); // only one cpu, print time stamp
  40 #else
  41   bx_phy_address phy_addr;
  42   Bit8u  instr_buf[16];
  43   char   char_buf[512];
  44   size_t i=0;
  45
  46   static char letters[] = "0123456789ABCDEF";
  47   static disassembler bx_disassemble;
  48   unsigned remainsInPage = 0x1000 - PAGE_OFFSET(offset);
  49
  50   bx_bool valid = dbg_xlate_linear2phy(BX_CPU_THIS_PTR get_laddr(BX_SEG_REG_CS, offset), &phy_addr);
  51   if (valid) {
  52     BX_MEM(0)->dbg_fetch_mem(BX_CPU_THIS, phy_addr, 16, instr_buf);
  53     unsigned isize = bx_disassemble.disasm(
  54         BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.d_b,
  55         BX_CPU_THIS_PTR cpu_mode == BX_MODE_LONG_64,
  56         BX_CPU_THIS_PTR get_segment_base(BX_SEG_REG_CS), offset,
  57         instr_buf, char_buf+i);
  58     if (isize <= remainsInPage) {
  59       i=strlen(char_buf);
  60       char_buf[i++] = ' ';
  61       char_buf[i++] = ':';
  62       char_buf[i++] = ' ';
  63       for (unsigned j=0; j<isize; j++) {
  64         char_buf[i++] = letters[(instr_buf[j] >> 4) & 0xf];
  65         char_buf[i++] = letters[(instr_buf[j] >> 0) & 0xf];
  66       }
  67       char_buf[i] = 0;
  68       BX_INFO((">> %s", char_buf));
  69     }
  70     else {
  71       BX_INFO(("(instruction unavailable) page split instruction"));
  72     }
  73   }
  74   else {
  75     BX_INFO(("(instruction unavailable) page not present"));
  76   }
  77 #endif  // #if BX_DEBUGGER
  78 }
  79
  80 #endif  // #if BX_DISASM
  81
  82 const char* cpu_mode_string(unsigned cpu_mode)
  83 {
  84   static const char *cpu_mode_name[] = {
  85      "real mode",
  86      "v8086 mode",
  87      "protected mode",
  88      "compatibility mode",
  89      "long mode",
  90      "unknown mode"
  91   };
  92
  93   if(cpu_mode >= 5) cpu_mode = 5;
  94   return cpu_mode_name[cpu_mode];
  95 }
  96
  97 const char* cpu_state_string(Bit32u debug_trap)
  98 {
  99   unsigned cpu_state = 5; // unknown state
 100
 101   static const char *cpu_state_name[] = {
 102      "active",
 103      "executing mwait",
 104      "waiting for SIPI",
 105      "in shutdown",
 106      "halted",
 107      "unknown state"
 108   };
 109
 110   if(debug_trap & BX_DEBUG_TRAP_HALT) cpu_state = 4;
 111   else if (debug_trap & BX_DEBUG_TRAP_SHUTDOWN) cpu_state = 3;
 112   else if (debug_trap & BX_DEBUG_TRAP_WAIT_FOR_SIPI) cpu_state = 2;
 113   else if (debug_trap & BX_DEBUG_TRAP_MWAIT) cpu_state = 1;
 114   else if (debug_trap & BX_DEBUG_TRAP_SPECIAL) cpu_state = 5;
 115   else cpu_state = 0;
 116   return cpu_state_name[cpu_state];
 117 }
 118
 119 void BX_CPU_C::debug(bx_address offset)
 120 {
 121   BX_INFO(("CPU is in %s (%s)", cpu_mode_string(BX_CPU_THIS_PTR get_cpu_mode()),
 122     cpu_state_string(BX_CPU_THIS_PTR debug_trap)));
 123   BX_INFO(("CS.d_b = %u bit",
 124     BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.d_b ? 32 : 16));
 125   BX_INFO(("SS.d_b = %u bit",
 126     BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.d_b ? 32 : 16));
 127 #if BX_SUPPORT_X86_64
 128   BX_INFO(("EFER   = 0x%08x", BX_CPU_THIS_PTR efer.get32()));
 129   BX_INFO(("| RAX=%08x%08x  RBX=%08x%08x",
 130           (unsigned) (RAX >> 32), (unsigned) EAX,
 131           (unsigned) (RBX >> 32), (unsigned) EBX));
 132   BX_INFO(("| RCX=%08x%08x  RDX=%08x%08x",
 133           (unsigned) (RCX >> 32), (unsigned) ECX,
 134           (unsigned) (RDX >> 32), (unsigned) EDX));
 135   BX_INFO(("| RSP=%08x%08x  RBP=%08x%08x",
 136           (unsigned) (RSP >> 32), (unsigned) ESP,
 137           (unsigned) (RBP >> 32), (unsigned) EBP));
 138   BX_INFO(("| RSI=%08x%08x  RDI=%08x%08x",
 139           (unsigned) (RSI >> 32), (unsigned) ESI,
 140           (unsigned) (RDI >> 32), (unsigned) EDI));
 141   BX_INFO(("|  R8=%08x%08x   R9=%08x%08x",
 142           (unsigned) (R8  >> 32), (unsigned) (R8  & 0xFFFFFFFF),
 143           (unsigned) (R9  >> 32), (unsigned) (R9  & 0xFFFFFFFF)));
 144   BX_INFO(("| R10=%08x%08x  R11=%08x%08x",
 145           (unsigned) (R10 >> 32), (unsigned) (R10 & 0xFFFFFFFF),
 146           (unsigned) (R11 >> 32), (unsigned) (R11 & 0xFFFFFFFF)));
 147   BX_INFO(("| R12=%08x%08x  R13=%08x%08x",
 148           (unsigned) (R12 >> 32), (unsigned) (R12 & 0xFFFFFFFF),
 149           (unsigned) (R13 >> 32), (unsigned) (R13 & 0xFFFFFFFF)));
 150   BX_INFO(("| R14=%08x%08x  R15=%08x%08x",
 151           (unsigned) (R14 >> 32), (unsigned) (R14 & 0xFFFFFFFF),
 152           (unsigned) (R15 >> 32), (unsigned) (R15 & 0xFFFFFFFF)));
 153 #else
 154   BX_INFO(("| EAX=%08x  EBX=%08x  ECX=%08x  EDX=%08x",
 155           (unsigned) EAX, (unsigned) EBX, (unsigned) ECX, (unsigned) EDX));
 156   BX_INFO(("| ESP=%08x  EBP=%08x  ESI=%08x  EDI=%08x",
 157           (unsigned) ESP, (unsigned) EBP, (unsigned) ESI, (unsigned) EDI));
 158 #endif
 159   BX_INFO(("| IOPL=%1u %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s",
 160     BX_CPU_THIS_PTR get_IOPL(),
 161     BX_CPU_THIS_PTR get_ID() ? "ID" : "id",
 162     BX_CPU_THIS_PTR get_VIP() ? "VIP" : "vip",
 163     BX_CPU_THIS_PTR get_VIF() ? "VIF" : "vif",
 164     BX_CPU_THIS_PTR get_AC() ? "AC" : "ac",
 165     BX_CPU_THIS_PTR get_VM() ? "VM" : "vm",
 166     BX_CPU_THIS_PTR get_RF() ? "RF" : "rf",
 167     BX_CPU_THIS_PTR get_NT() ? "NT" : "nt",
 168     BX_CPU_THIS_PTR get_OF() ? "OF" : "of",
 169     BX_CPU_THIS_PTR get_DF() ? "DF" : "df",
 170     BX_CPU_THIS_PTR get_IF() ? "IF" : "if",
 171     BX_CPU_THIS_PTR get_TF() ? "TF" : "tf",
 172     BX_CPU_THIS_PTR get_SF() ? "SF" : "sf",
 173     BX_CPU_THIS_PTR get_ZF() ? "ZF" : "zf",
 174     BX_CPU_THIS_PTR get_AF() ? "AF" : "af",
 175     BX_CPU_THIS_PTR get_PF() ? "PF" : "pf",
 176     BX_CPU_THIS_PTR get_CF() ? "CF" : "cf"));
 177
 178   BX_INFO(("| SEG selector     base    limit G D"));
 179   BX_INFO(("| SEG sltr(index|ti|rpl)     base    limit G D"));
 180   BX_INFO(("|  CS:%04x( %04x| %01u|  %1u) %08x %08x %1u %1u",
 181     (unsigned) BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value,
 182     (unsigned) BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.index,
 183     (unsigned) BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.ti,
 184     (unsigned) BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.rpl,
 185     (unsigned) BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.base,
 186     (unsigned) BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.limit,
 187     (unsigned) BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.g,
 188     (unsigned) BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.d_b));
 189   BX_INFO(("|  DS:%04x( %04x| %01u|  %1u) %08x %08x %1u %1u",
 190     (unsigned) BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS].selector.value,
 191     (unsigned) BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS].selector.index,
 192     (unsigned) BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS].selector.ti,
 193     (unsigned) BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS].selector.rpl,
 194     (unsigned) BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS].cache.u.segment.base,
 195     (unsigned) BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS].cache.u.segment.limit,
 196     (unsigned) BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS].cache.u.segment.g,
 197     (unsigned) BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS].cache.u.segment.d_b));
 198   BX_INFO(("|  SS:%04x( %04x| %01u|  %1u) %08x %08x %1u %1u",
 199     (unsigned) BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].selector.value,
 200     (unsigned) BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].selector.index,
 201     (unsigned) BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].selector.ti,
 202     (unsigned) BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].selector.rpl,
 203     (unsigned) BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.base,
 204     (unsigned) BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.limit,
 205     (unsigned) BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.g,
 206     (unsigned) BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.d_b));
 207   BX_INFO(("|  ES:%04x( %04x| %01u|  %1u) %08x %08x %1u %1u",
 208     (unsigned) BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES].selector.value,
 209     (unsigned) BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES].selector.index,
 210     (unsigned) BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES].selector.ti,
 211     (unsigned) BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES].selector.rpl,
 212     (unsigned) BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES].cache.u.segment.base,
 213     (unsigned) BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES].cache.u.segment.limit,
 214     (unsigned) BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES].cache.u.segment.g,
 215     (unsigned) BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES].cache.u.segment.d_b));
 216   BX_INFO(("|  FS:%04x( %04x| %01u|  %1u) %08x %08x %1u %1u",
 217     (unsigned) BX_CPU_THIS_PTR sregs[BX_SEG_REG_FS].selector.value,
 218     (unsigned) BX_CPU_THIS_PTR sregs[BX_SEG_REG_FS].selector.index,
 219     (unsigned) BX_CPU_THIS_PTR sregs[BX_SEG_REG_FS].selector.ti,
 220     (unsigned) BX_CPU_THIS_PTR sregs[BX_SEG_REG_FS].selector.rpl,
 221     (unsigned) BX_CPU_THIS_PTR sregs[BX_SEG_REG_FS].cache.u.segment.base,
 222     (unsigned) BX_CPU_THIS_PTR sregs[BX_SEG_REG_FS].cache.u.segment.limit,
 223     (unsigned) BX_CPU_THIS_PTR sregs[BX_SEG_REG_FS].cache.u.segment.g,
 224     (unsigned) BX_CPU_THIS_PTR sregs[BX_SEG_REG_FS].cache.u.segment.d_b));
 225   BX_INFO(("|  GS:%04x( %04x| %01u|  %1u) %08x %08x %1u %1u",
 226     (unsigned) BX_CPU_THIS_PTR sregs[BX_SEG_REG_GS].selector.value,
 227     (unsigned) BX_CPU_THIS_PTR sregs[BX_SEG_REG_GS].selector.index,
 228     (unsigned) BX_CPU_THIS_PTR sregs[BX_SEG_REG_GS].selector.ti,
 229     (unsigned) BX_CPU_THIS_PTR sregs[BX_SEG_REG_GS].selector.rpl,
 230     (unsigned) BX_CPU_THIS_PTR sregs[BX_SEG_REG_GS].cache.u.segment.base,
 231     (unsigned) BX_CPU_THIS_PTR sregs[BX_SEG_REG_GS].cache.u.segment.limit,
 232     (unsigned) BX_CPU_THIS_PTR sregs[BX_SEG_REG_GS].cache.u.segment.g,
 233     (unsigned) BX_CPU_THIS_PTR sregs[BX_SEG_REG_GS].cache.u.segment.d_b));
 234 #if BX_SUPPORT_X86_64
 235   BX_INFO(("|  MSR_FS_BASE:%08x%08x",
 236     (unsigned) (MSR_FSBASE >> 32), (unsigned) (MSR_FSBASE & 0xFFFFFFFF)));
 237   BX_INFO(("|  MSR_GS_BASE:%08x%08x",
 238     (unsigned) (MSR_GSBASE >> 32), (unsigned) (MSR_GSBASE & 0xFFFFFFFF)));
 239 #endif
 240
 241 #if BX_SUPPORT_X86_64
 242   BX_INFO(("| RIP=%08x%08x (%08x%08x)",
 243     (unsigned) (BX_CPU_THIS_PTR gen_reg[BX_64BIT_REG_RIP].dword.hrx),
 244     (unsigned) (EIP),
 245     (unsigned) (BX_CPU_THIS_PTR prev_rip >> 32),
 246     (unsigned) (BX_CPU_THIS_PTR prev_rip & 0xffffffff)));
 247   BX_INFO(("| CR0=0x%08x CR2=0x%08x%08x",
 248     (unsigned) (BX_CPU_THIS_PTR cr0.get32()),
 249     (unsigned) (BX_CPU_THIS_PTR cr2 >> 32),
 250     (unsigned) (BX_CPU_THIS_PTR cr2 & 0xffffffff)));
 251   BX_INFO(("| CR3=0x%08x CR4=0x%08x",
 252     (unsigned) BX_CPU_THIS_PTR cr3, BX_CPU_THIS_PTR cr4.get32()));
 253 #else
 254   BX_INFO(("| EIP=%08x (%08x)", (unsigned) EIP,
 255     (unsigned) BX_CPU_THIS_PTR prev_rip));
 256
 257 #if BX_CPU_LEVEL >= 2 && BX_CPU_LEVEL < 4
 258   BX_INFO(("| CR0=0x%08x CR2=0x%08x CR3=0x%08x",
 259     BX_CPU_THIS_PTR cr0.get32(),
 260     BX_CPU_THIS_PTR cr2,
 261     BX_CPU_THIS_PTR cr3));
 262 #elif BX_CPU_LEVEL >= 4
 263   BX_INFO(("| CR0=0x%08x CR2=0x%08x",
 264     BX_CPU_THIS_PTR cr0.get32(),
 265     BX_CPU_THIS_PTR cr2));
 266   BX_INFO(("| CR3=0x%08x CR4=0x%08x",
 267     BX_CPU_THIS_PTR cr3,
 268     BX_CPU_THIS_PTR cr4.get32()));
 269 #endif
 270
 271 #endif // BX_SUPPORT_X86_64
 272
 273 #if BX_DISASM
 274   debug_disasm_instruction(offset);
 275 #endif  // #if BX_DISASM
 276 }
 277
 278
 279 #if BX_DEBUGGER
 280 Bit32u BX_CPU_C::dbg_get_reg(unsigned reg)
 281 {
 282   Bit32u return_val32;
 283
 284   switch (reg) {
 285     case BX_DBG_REG_EIP: return(EIP);
 286     case BX_DBG_REG_EFLAGS:
 287       return_val32 = BX_CPU_THIS_PTR read_eflags();
 288       return(return_val32);
 289     case BX_DBG_REG_CS: return(BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value);
 290     case BX_DBG_REG_SS: return(BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].selector.value);
 291     case BX_DBG_REG_DS: return(BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS].selector.value);
 292     case BX_DBG_REG_ES: return(BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES].selector.value);
 293     case BX_DBG_REG_FS: return(BX_CPU_THIS_PTR sregs[BX_SEG_REG_FS].selector.value);
 294     case BX_DBG_REG_GS: return(BX_CPU_THIS_PTR sregs[BX_SEG_REG_GS].selector.value);
 295     case BX_DBG_REG_CR0:
 296       return BX_CPU_THIS_PTR cr0.get32();
 297     case BX_DBG_REG_CR2:
 298       return BX_CPU_THIS_PTR cr2;
 299     case BX_DBG_REG_CR3:
 300       return BX_CPU_THIS_PTR cr3;
 301 #if BX_CPU_LEVEL >= 4
 302     case BX_DBG_REG_CR4:
 303       return BX_CPU_THIS_PTR cr4.get32();
 304 #endif
 305     default:
 306       BX_PANIC(("get_reg: request for unknown register"));
 307       return(0);
 308   }
 309 }
 310
 311 bx_bool BX_CPU_C::dbg_set_reg(unsigned reg, Bit32u val)
 312 {
 313   // returns 1=OK, 0=can't change
 314   bx_segment_reg_t *seg;
 315   Bit32u current_sys_bits;
 316
 317   switch (reg) {
 318     case BX_DBG_REG_EIP: EIP = val; return(1);
 319     case BX_DBG_REG_EFLAGS:
 320       BX_INFO(("dbg_set_reg: can not handle eflags yet."));
 321       if (val & 0xffff0000) {
 322         BX_INFO(("dbg_set_reg: can not set upper 16 bits of eflags."));
 323         return(0);
 324       }
 325       // make sure none of the system bits are being changed
 326       current_sys_bits = ((BX_CPU_THIS_PTR getB_NT()) << 14) |
 327                          (BX_CPU_THIS_PTR get_IOPL () << 12) |
 328                          ((BX_CPU_THIS_PTR getB_TF()) << 8);
 329       if (current_sys_bits != (val & 0x0000f100)) {
 330         BX_INFO(("dbg_set_reg: can not modify NT, IOPL, or TF."));
 331         return(0);
 332       }
 333       BX_CPU_THIS_PTR set_CF(val & 0x01); val >>= 2;
 334       BX_CPU_THIS_PTR set_PF(val & 0x01); val >>= 2;
 335       BX_CPU_THIS_PTR set_AF(val & 0x01); val >>= 2;
 336       BX_CPU_THIS_PTR set_ZF(val & 0x01); val >>= 1;
 337       BX_CPU_THIS_PTR set_SF(val & 0x01); val >>= 2;
 338       BX_CPU_THIS_PTR set_IF(val & 0x01); val >>= 1;
 339       BX_CPU_THIS_PTR set_DF(val & 0x01); val >>= 1;
 340       BX_CPU_THIS_PTR set_OF(val & 0x01);
 341       if (BX_CPU_THIS_PTR get_IF())
 342         BX_CPU_THIS_PTR async_event = 1;
 343       return(1);
 344     case BX_DBG_REG_CS:
 345       seg = &BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS];
 346       break;
 347     case BX_DBG_REG_SS:
 348       seg = &BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS];
 349       break;
 350     case BX_DBG_REG_DS:
 351       seg = &BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS];
 352       break;
 353     case BX_DBG_REG_ES:
 354       seg = &BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES];
 355       break;
 356     case BX_DBG_REG_FS:
 357       seg = &BX_CPU_THIS_PTR sregs[BX_SEG_REG_FS];
 358       break;
 359     case BX_DBG_REG_GS:
 360       seg = &BX_CPU_THIS_PTR sregs[BX_SEG_REG_GS];
 361       break;
 362     default:
 363       BX_PANIC(("dbg_set_reg: unrecognized register ID (%u)", reg));
 364       return(0);
 365   }
 366
 367   if (real_mode()) {
 368     seg->selector.value = val;
 369     seg->cache.valid = 1;
 370     seg->cache.p = 1;
 371     seg->cache.dpl = 0;
 372     seg->cache.segment = 1; // regular segment
 373     seg->cache.type = BX_DATA_READ_WRITE_ACCESSED;
 374     seg->cache.u.segment.base = val << 4;
 375     seg->cache.u.segment.limit        = 0xffff;
 376     seg->cache.u.segment.limit_scaled = 0xffff;
 377     seg->cache.u.segment.g     = 0;      // byte granular
 378     seg->cache.u.segment.d_b   = 0;      // default 16bit size
 379     seg->cache.u.segment.avl   = 0;
 380     return(1); // ok
 381   }
 382
 383   return(0); // can't change when not in real mode
 384 }
 385
 386 unsigned BX_CPU_C::dbg_query_pending(void)
 387 {
 388   unsigned ret = 0;
 389
 390   if (BX_HRQ) {  // DMA Hold Request
 391     ret |= BX_DBG_PENDING_DMA;
 392   }
 393
 394   if (BX_CPU_THIS_PTR INTR && BX_CPU_THIS_PTR get_IF()) {
 395     ret |= BX_DBG_PENDING_IRQ;
 396   }
 397
 398   return(ret);
 399 }
 400
 401 bx_bool BX_CPU_C::dbg_get_sreg(bx_dbg_sreg_t *sreg, unsigned sreg_no)
 402 {
 403   if (sreg_no > 5)
 404     return(0);
 405   sreg->sel   = BX_CPU_THIS_PTR sregs[sreg_no].selector.value;
 406   sreg->des_l = get_descriptor_l(&BX_CPU_THIS_PTR sregs[sreg_no].cache);
 407   sreg->des_h = get_descriptor_h(&BX_CPU_THIS_PTR sregs[sreg_no].cache);
 408   sreg->valid = BX_CPU_THIS_PTR sregs[sreg_no].cache.valid;
 409   return(1);
 410 }
 411
 412 void BX_CPU_C::dbg_get_tr(bx_dbg_sreg_t *sreg)
 413 {
 414   sreg->sel   = BX_CPU_THIS_PTR tr.selector.value;
 415   sreg->des_l = get_descriptor_l(&BX_CPU_THIS_PTR tr.cache);
 416   sreg->des_h = get_descriptor_h(&BX_CPU_THIS_PTR tr.cache);
 417   sreg->valid = BX_CPU_THIS_PTR tr.cache.valid;
 418 }
 419
 420 void BX_CPU_C::dbg_get_ldtr(bx_dbg_sreg_t *sreg)
 421 {
 422   sreg->sel   = BX_CPU_THIS_PTR ldtr.selector.value;
 423   sreg->des_l = get_descriptor_l(&BX_CPU_THIS_PTR ldtr.cache);
 424   sreg->des_h = get_descriptor_h(&BX_CPU_THIS_PTR ldtr.cache);
 425   sreg->valid = BX_CPU_THIS_PTR ldtr.cache.valid;
 426 }
 427
 428 void BX_CPU_C::dbg_get_gdtr(bx_dbg_global_sreg_t *sreg)
 429 {
 430   sreg->base  = BX_CPU_THIS_PTR gdtr.base;
 431   sreg->limit = BX_CPU_THIS_PTR gdtr.limit;
 432 }
 433
 434 void BX_CPU_C::dbg_get_idtr(bx_dbg_global_sreg_t *sreg)
 435 {
 436   sreg->base  = BX_CPU_THIS_PTR idtr.base;
 437   sreg->limit = BX_CPU_THIS_PTR idtr.limit;
 438 }
 439
 440 #endif  // #if BX_DEBUGGER
 441
 442 void BX_CPU_C::atexit(void)
 443 {
 444   debug(BX_CPU_THIS_PTR prev_rip);
 445 }