iodev/pci2isa.cc

   1 /////////////////////////////////////////////////////////////////////////
   2 // $Id: pci2isa.cc,v 1.43 2008/01/26 22:24:02 sshwarts Exp $
   3 /////////////////////////////////////////////////////////////////////////
   4 //
   5 //  Copyright (C) 2002  MandrakeSoft S.A.
   6 //
   7 //    MandrakeSoft S.A.
   8 //    43, rue d'Aboukir
   9 //    75002 Paris - France
  10 //    http://www.linux-mandrake.com/
  11 //    http://www.mandrakesoft.com/
  12 //
  13 //  This library is free software; you can redistribute it and/or
  14 //  modify it under the terms of the GNU Lesser General Public
  15 //  License as published by the Free Software Foundation; either
  16 //  version 2 of the License, or (at your option) any later version.
  17 //
  18 //  This library is distributed in the hope that it will be useful,
  19 //  but WITHOUT ANY WARRANTY; without even the implied warranty of
  20 //  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  21 //  Lesser General Public License for more details.
  22 //
  23 //  You should have received a copy of the GNU Lesser General Public
  24 //  License along with this library; if not, write to the Free Software
  25 //  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  26
  27 //
  28 // i440FX Support - PCI-to-ISA bridge (PIIX3)
  29 //
  30
  31 // Define BX_PLUGGABLE in files that can be compiled into plugins.  For
  32 // platforms that require a special tag on exported symbols, BX_PLUGGABLE
  33 // is used to know when we are exporting symbols and when we are importing.
  34 #define BX_PLUGGABLE
  35
  36 #include "iodev.h"
  37 #if BX_SUPPORT_PCI
  38
  39 #define LOG_THIS thePci2IsaBridge->
  40
  41 bx_piix3_c *thePci2IsaBridge = NULL;
  42
  43 int libpci2isa_LTX_plugin_init(plugin_t *plugin, plugintype_t type, int argc, char *argv[])
  44 {
  45   thePci2IsaBridge = new bx_piix3_c();
  46   bx_devices.pluginPci2IsaBridge = thePci2IsaBridge;
  47   BX_REGISTER_DEVICE_DEVMODEL(plugin, type, thePci2IsaBridge, BX_PLUGIN_PCI2ISA);
  48   return(0); // Success
  49 }
  50
  51 void libpci2isa_LTX_plugin_fini(void)
  52 {
  53   delete thePci2IsaBridge;
  54 }
  55
  56 bx_piix3_c::bx_piix3_c()
  57 {
  58   put("P2I");
  59   settype(PCI2ISALOG);
  60 }
  61
  62 bx_piix3_c::~bx_piix3_c()
  63 {
  64   BX_DEBUG(("Exit"));
  65 }
  66
  67 void bx_piix3_c::init(void)
  68 {
  69   unsigned i;
  70   // called once when bochs initializes
  71
  72   Bit8u devfunc = BX_PCI_DEVICE(1,0);
  73   DEV_register_pci_handlers(this, &devfunc, BX_PLUGIN_PCI2ISA,
  74       "PIIX3 PCI-to-ISA bridge");
  75
  76   DEV_register_iowrite_handler(this, write_handler, 0x00B2, "PIIX3 PCI-to-ISA bridge", 1);
  77   DEV_register_iowrite_handler(this, write_handler, 0x00B3, "PIIX3 PCI-to-ISA bridge", 1);
  78   DEV_register_iowrite_handler(this, write_handler, 0x04D0, "PIIX3 PCI-to-ISA bridge", 1);
  79   DEV_register_iowrite_handler(this, write_handler, 0x04D1, "PIIX3 PCI-to-ISA bridge", 1);
  80   DEV_register_iowrite_handler(this, write_handler, 0x0CF9, "PIIX3 PCI-to-ISA bridge", 1);
  81
  82   DEV_register_ioread_handler(this, read_handler, 0x00B2, "PIIX3 PCI-to-ISA bridge", 1);
  83   DEV_register_ioread_handler(this, read_handler, 0x00B3, "PIIX3 PCI-to-ISA bridge", 1);
  84   DEV_register_ioread_handler(this, read_handler, 0x04D0, "PIIX3 PCI-to-ISA bridge", 1);
  85   DEV_register_ioread_handler(this, read_handler, 0x04D1, "PIIX3 PCI-to-ISA bridge", 1);
  86   DEV_register_ioread_handler(this, read_handler, 0x0CF9, "PIIX3 PCI-to-ISA bridge", 1);
  87
  88   for (i=0; i<256; i++)
  89     BX_P2I_THIS s.pci_conf[i] = 0x0;
  90   for (i=0; i<16; i++)
  91     BX_P2I_THIS s.irq_registry[i] = 0x0;
  92   for (i=0; i<16; i++)
  93     BX_P2I_THIS s.irq_level[i] = 0x0;
  94   // readonly registers
  95   BX_P2I_THIS s.pci_conf[0x00] = 0x86;
  96   BX_P2I_THIS s.pci_conf[0x01] = 0x80;
  97   BX_P2I_THIS s.pci_conf[0x02] = 0x00;
  98   BX_P2I_THIS s.pci_conf[0x03] = 0x70;
  99   BX_P2I_THIS s.pci_conf[0x04] = 0x07;
 100   BX_P2I_THIS s.pci_conf[0x0a] = 0x01;
 101   BX_P2I_THIS s.pci_conf[0x0b] = 0x06;
 102   BX_P2I_THIS s.pci_conf[0x0e] = 0x80;
 103   // irq routing registers
 104   BX_P2I_THIS s.pci_conf[0x60] = 0x80;
 105   BX_P2I_THIS s.pci_conf[0x61] = 0x80;
 106   BX_P2I_THIS s.pci_conf[0x62] = 0x80;
 107   BX_P2I_THIS s.pci_conf[0x63] = 0x80;
 108 }
 109
 110 void bx_piix3_c::reset(unsigned type)
 111 {
 112   BX_P2I_THIS s.pci_conf[0x05] = 0x00;
 113   BX_P2I_THIS s.pci_conf[0x06] = 0x00;
 114   BX_P2I_THIS s.pci_conf[0x07] = 0x02;
 115   BX_P2I_THIS s.pci_conf[0x4c] = 0x4d;
 116   BX_P2I_THIS s.pci_conf[0x4e] = 0x03;
 117   BX_P2I_THIS s.pci_conf[0x4f] = 0x00;
 118   BX_P2I_THIS s.pci_conf[0x69] = 0x02;
 119   BX_P2I_THIS s.pci_conf[0x70] = 0x80;
 120   BX_P2I_THIS s.pci_conf[0x76] = 0x0c;
 121   BX_P2I_THIS s.pci_conf[0x77] = 0x0c;
 122   BX_P2I_THIS s.pci_conf[0x78] = 0x02;
 123   BX_P2I_THIS s.pci_conf[0x79] = 0x00;
 124   BX_P2I_THIS s.pci_conf[0x80] = 0x00;
 125   BX_P2I_THIS s.pci_conf[0x82] = 0x00;
 126   BX_P2I_THIS s.pci_conf[0xa0] = 0x08;
 127   BX_P2I_THIS s.pci_conf[0xa2] = 0x00;
 128   BX_P2I_THIS s.pci_conf[0xa3] = 0x00;
 129   BX_P2I_THIS s.pci_conf[0xa4] = 0x00;
 130   BX_P2I_THIS s.pci_conf[0xa5] = 0x00;
 131   BX_P2I_THIS s.pci_conf[0xa6] = 0x00;
 132   BX_P2I_THIS s.pci_conf[0xa7] = 0x00;
 133   BX_P2I_THIS s.pci_conf[0xa8] = 0x0f;
 134   BX_P2I_THIS s.pci_conf[0xaa] = 0x00;
 135   BX_P2I_THIS s.pci_conf[0xab] = 0x00;
 136   BX_P2I_THIS s.pci_conf[0xac] = 0x00;
 137   BX_P2I_THIS s.pci_conf[0xae] = 0x00;
 138
 139   for (unsigned i = 0; i < 4; i++) {
 140     pci_set_irq(0x08, i+1, 0);
 141     pci_unregister_irq(i);
 142   }
 143
 144   BX_P2I_THIS s.elcr1 = 0x00;
 145   BX_P2I_THIS s.elcr2 = 0x00;
 146   BX_P2I_THIS s.pci_reset = 0x00;
 147   BX_P2I_THIS s.apms = 0x00;
 148   BX_P2I_THIS s.apmc = 0x00;
 149 }
 150
 151 void bx_piix3_c::register_state(void)
 152 {
 153   unsigned i;
 154   char name[6];
 155
 156   bx_list_c *list = new bx_list_c(SIM->get_bochs_root(), "pci2isa", "PCI-to-ISA Bridge State", 8);
 157
 158   register_pci_state(list, BX_P2I_THIS s.pci_conf);
 159
 160   BXRS_HEX_PARAM_FIELD(list, elcr1, BX_P2I_THIS s.elcr1);
 161   BXRS_HEX_PARAM_FIELD(list, elcr2, BX_P2I_THIS s.elcr2);
 162   BXRS_HEX_PARAM_FIELD(list, apmc, BX_P2I_THIS s.apmc);
 163   BXRS_HEX_PARAM_FIELD(list, apms, BX_P2I_THIS s.apms);
 164   BXRS_HEX_PARAM_FIELD(list, pci_reset, BX_P2I_THIS s.pci_reset);
 165
 166   bx_list_c *irqr = new bx_list_c(list, "irq_registry", 16);
 167   for (i=0; i<16; i++) {
 168     sprintf(name, "%d", i);
 169     new bx_shadow_num_c(irqr, name, &BX_P2I_THIS s.irq_registry[i]);
 170   }
 171   bx_list_c *irql = new bx_list_c(list, "irq_level", 16);
 172   for (i=0; i<16; i++) {
 173     sprintf(name, "%d", i);
 174     new bx_shadow_num_c(irql, name, &BX_P2I_THIS s.irq_level[i]);
 175   }
 176 }
 177
 178 void bx_piix3_c::after_restore_state(void)
 179 {
 180   for (unsigned i=0; i<16; i++) {
 181     if (BX_P2I_THIS s.irq_registry[i]) {
 182       DEV_register_irq(i, "PIIX3 IRQ routing");
 183     }
 184   }
 185 }
 186
 187 void bx_piix3_c::pci_register_irq(unsigned pirq, unsigned irq)
 188 {
 189   if ((irq < 16) && (((1 << irq) & 0xdef8) > 0)) {
 190     if (BX_P2I_THIS s.pci_conf[0x60 + pirq] < 16) {
 191       pci_unregister_irq(pirq);
 192     }
 193     BX_P2I_THIS s.pci_conf[0x60 + pirq] = irq;
 194     if (!BX_P2I_THIS s.irq_registry[irq]) {
 195       DEV_register_irq(irq, "PIIX3 IRQ routing");
 196     }
 197     BX_P2I_THIS s.irq_registry[irq] |= (1 << pirq);
 198   }
 199 }
 200
 201 void bx_piix3_c::pci_unregister_irq(unsigned pirq)
 202 {
 203   Bit8u irq =  BX_P2I_THIS s.pci_conf[0x60 + pirq];
 204   if (irq < 16) {
 205     BX_P2I_THIS s.irq_registry[irq] &= ~(1 << pirq);
 206     if (!BX_P2I_THIS s.irq_registry[irq]) {
 207       BX_P2I_THIS pci_set_irq(0x08, pirq+1, 0);
 208       DEV_unregister_irq(irq, "PIIX3 IRQ routing");
 209     }
 210     BX_P2I_THIS s.pci_conf[0x60 + pirq] = 0x80;
 211   }
 212 }
 213
 214 void bx_piix3_c::pci_set_irq(Bit8u devfunc, unsigned line, bx_bool level)
 215 {
 216   Bit8u pirq = ((devfunc >> 3) + line - 2) & 0x03;
 217 #if BX_SUPPORT_APIC
 218   // forward this function call to the ioapic too
 219   if (DEV_ioapic_present()) {
 220     bx_devices.ioapic->set_irq_level(pirq + 16, level);
 221   }
 222 #endif
 223   Bit8u irq = BX_P2I_THIS s.pci_conf[0x60 + pirq];
 224   if ((irq < 16) && (((1 << irq) & 0xdef8) > 0)) {
 225     if (level == 1) {
 226       if (!BX_P2I_THIS s.irq_level[irq]) {
 227         DEV_pic_raise_irq(irq);
 228         BX_DEBUG(("PIRQ%c -> IRQ %d = 1", pirq+65, irq));
 229       }
 230       BX_P2I_THIS s.irq_level[irq] |= (1 << (devfunc >> 3));
 231     } else {
 232       BX_P2I_THIS s.irq_level[irq] &= ~(1 << (devfunc >> 3));
 233       if (!BX_P2I_THIS s.irq_level[irq]) {
 234         DEV_pic_lower_irq(irq);
 235         BX_DEBUG(("PIRQ%c -> IRQ %d = 0", pirq+65, irq));
 236       }
 237     }
 238   }
 239 }
 240
 241 // static IO port read callback handler
 242 // redirects to non-static class handler to avoid virtual functions
 243
 244 Bit32u bx_piix3_c::read_handler(void *this_ptr, Bit32u address, unsigned io_len)
 245 {
 246 #if !BX_USE_P2I_SMF
 247   bx_piix3_c *class_ptr = (bx_piix3_c *) this_ptr;
 248   return class_ptr->read(address, io_len);
 249 }
 250
 251 Bit32u bx_piix3_c::read(Bit32u address, unsigned io_len)
 252 {
 253 #else
 254   UNUSED(this_ptr);
 255 #endif // !BX_USE_P2I_SMF
 256
 257   switch (address) {
 258     case 0x00b2:
 259       return(BX_P2I_THIS s.apmc);
 260
 261     case 0x00b3:
 262       return(BX_P2I_THIS s.apms);
 263
 264     case 0x04d0:
 265       return(BX_P2I_THIS s.elcr1);
 266
 267     case 0x04d1:
 268       return(BX_P2I_THIS s.elcr2);
 269
 270     case 0x0cf9:
 271       return(BX_P2I_THIS s.pci_reset);
 272   }
 273
 274   return(0xffffffff);
 275 }
 276
 277 // static IO port write callback handler
 278 // redirects to non-static class handler to avoid virtual functions
 279
 280 void bx_piix3_c::write_handler(void *this_ptr, Bit32u address, Bit32u value, unsigned io_len)
 281 {
 282 #if !BX_USE_P2I_SMF
 283   bx_piix3_c *class_ptr = (bx_piix3_c *) this_ptr;
 284   class_ptr->write(address, value, io_len);
 285 }
 286
 287 void bx_piix3_c::write(Bit32u address, Bit32u value, unsigned io_len)
 288 {
 289 #else
 290   UNUSED(this_ptr);
 291 #endif // !BX_USE_P2I_SMF
 292
 293   switch (address) {
 294     case 0x00b2:
 295 #if BX_SUPPORT_ACPI
 296       DEV_acpi_generate_smi((Bit8u)value);
 297 #else
 298       BX_ERROR(("write %08x: APM command register not supported yet", value));
 299 #endif
 300       BX_P2I_THIS s.apmc = value & 0xff;
 301       break;
 302     case 0x00b3:
 303       BX_P2I_THIS s.apms = value & 0xff;
 304       break;
 305     case 0x04d0:
 306       value &= 0xf8;
 307       if (value != BX_P2I_THIS s.elcr1) {
 308         BX_P2I_THIS s.elcr1 = value;
 309         BX_INFO(("write: ELCR1 = 0x%02x", BX_P2I_THIS s.elcr1));
 310         DEV_pic_set_mode(1, BX_P2I_THIS s.elcr1); // master PIC
 311       }
 312       break;
 313     case 0x04d1:
 314       value &= 0xde;
 315       if (value != BX_P2I_THIS s.elcr2) {
 316         BX_P2I_THIS s.elcr2 = value;
 317         BX_INFO(("write: ELCR2 = 0x%02x", BX_P2I_THIS s.elcr2));
 318         DEV_pic_set_mode(0, BX_P2I_THIS s.elcr2); // slave PIC
 319       }
 320       break;
 321     case 0x0cf9:
 322       BX_INFO(("write: CPU reset register = 0x%02x", value));
 323       BX_P2I_THIS s.pci_reset = value & 0x02;
 324       if (value & 0x04) {
 325         if (BX_P2I_THIS s.pci_reset) {
 326           bx_pc_system.Reset(BX_RESET_HARDWARE);
 327         } else {
 328           bx_pc_system.Reset(BX_RESET_SOFTWARE);
 329         }
 330       }
 331       break;
 332   }
 333 }
 334
 335 // pci configuration space read callback handler
 336 Bit32u bx_piix3_c::pci_read_handler(Bit8u address, unsigned io_len)
 337 {
 338   Bit32u value = 0;
 339
 340   if (io_len <= 4) {
 341     for (unsigned i=0; i<io_len; i++) {
 342       value |= (BX_P2I_THIS s.pci_conf[address+i] << (i*8));
 343     }
 344     BX_DEBUG(("PIIX3 PCI-to-ISA read register 0x%02x value 0x%08x", address, value));
 345     return value;
 346   }
 347   else
 348     return 0xffffffff;
 349 }
 350
 351 // pci configuration space write callback handler
 352 void bx_piix3_c::pci_write_handler(Bit8u address, Bit32u value, unsigned io_len)
 353 {
 354   if ((address >= 0x10) && (address < 0x34))
 355     return;
 356   if (io_len <= 4) {
 357     for (unsigned i=0; i<io_len; i++) {
 358       Bit8u value8 = (value >> (i*8)) & 0xFF;
 359       switch (address+i) {
 360         case 0x04:
 361         case 0x06:
 362           break;
 363         case 0x60:
 364         case 0x61:
 365         case 0x62:
 366         case 0x63:
 367           if (value8 != BX_P2I_THIS s.pci_conf[address+i]) {
 368             if (value8 >= 0x80) {
 369               pci_unregister_irq((address+i) & 0x03);
 370             } else {
 371               pci_register_irq((address+i) & 0x03, value8);
 372             }
 373             BX_INFO(("PCI IRQ routing: PIRQ%c# set to 0x%02x", address+i-31,
 374                      value8));
 375           }
 376           break;
 377         default:
 378           BX_P2I_THIS s.pci_conf[address+i] = value8;
 379           BX_DEBUG(("PIIX3 PCI-to-ISA write register 0x%02x value 0x%02x", address+i,
 380                     value8));
 381       }
 382     }
 383   }
 384 }
 385
 386 #endif /* BX_SUPPORT_PCI */