?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
- added instructions how to update the online documentation
[bochs-mirror.git] / bios / rombios32.c
blobef98a419f6e14b08fc858ab9c9a83732b4343259
1 /////////////////////////////////////////////////////////////////////////
2 // $Id: rombios32.c,v 1.39 2008/12/04 18:48:33 sshwarts Exp $
3 /////////////////////////////////////////////////////////////////////////
4 //
5 // 32 bit Bochs BIOS init code
6 // Copyright (C) 2006 Fabrice Bellard
7 //
8 // This library is free software; you can redistribute it and/or
9 // modify it under the terms of the GNU Lesser General Public
10 // License as published by the Free Software Foundation; either
11 // version 2 of the License, or (at your option) any later version.
12 //
13 // This library is distributed in the hope that it will be useful,
14 // but WITHOUT ANY WARRANTY; without even the implied warranty of
15 // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 // Lesser General Public License for more details.
17 //
18 // You should have received a copy of the GNU Lesser General Public
19 // License along with this library; if not, write to the Free Software
20 // Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
21 #include <stdarg.h>
22 #include <stddef.h>
23
24 #include "rombios.h"
25
26 typedef signed char int8_t;
27 typedef short int16_t;
28 typedef int int32_t;
29 typedef long long int64_t;
30 typedef unsigned char uint8_t;
31 typedef unsigned short uint16_t;
32 typedef unsigned int uint32_t;
33 typedef unsigned long long uint64_t;
34
35 /* if true, put the MP float table and ACPI RSDT in EBDA and the MP
36 table in RAM. Unfortunately, Linux has bugs with that, so we prefer
37 to modify the BIOS in shadow RAM */
38 //#define BX_USE_EBDA_TABLES
39
40 /* define it if the (emulated) hardware supports SMM mode */
41 #define BX_USE_SMM
42
43 #define cpuid(index, eax, ebx, ecx, edx) \
44 asm volatile ("cpuid" \
45 : "=a" (eax), "=b" (ebx), "=c" (ecx), "=d" (edx) \
46 : "0" (index))
47
48 #define wbinvd() asm volatile("wbinvd")
49
50 #define CPUID_APIC (1 << 9)
51
52 #define APIC_BASE ((uint8_t *)0xfee00000)
53 #define APIC_ICR_LOW 0x300
54 #define APIC_SVR 0x0F0
55 #define APIC_ID 0x020
56 #define APIC_LVT3 0x370
57
58 #define APIC_ENABLED 0x0100
59
60 #define AP_BOOT_ADDR 0x9f000
61
62 #define MPTABLE_MAX_SIZE 0x00002000
63 #define SMI_CMD_IO_ADDR 0xb2
64
65 #define BIOS_TMP_STORAGE 0x00030000 /* 64 KB used to copy the BIOS to shadow RAM */
66
67 static inline void outl(int addr, int val)
68 {
69 asm volatile ("outl %1, %w0" : : "d" (addr), "a" (val));
70 }
71
72 static inline void outw(int addr, int val)
73 {
74 asm volatile ("outw %w1, %w0" : : "d" (addr), "a" (val));
75 }
76
77 static inline void outb(int addr, int val)
78 {
79 asm volatile ("outb %b1, %w0" : : "d" (addr), "a" (val));
80 }
81
82 static inline uint32_t inl(int addr)
83 {
84 uint32_t val;
85 asm volatile ("inl %w1, %0" : "=a" (val) : "d" (addr));
86 return val;
87 }
88
89 static inline uint16_t inw(int addr)
90 {
91 uint16_t val;
92 asm volatile ("inw %w1, %w0" : "=a" (val) : "d" (addr));
93 return val;
94 }
95
96 static inline uint8_t inb(int addr)
97 {
98 uint8_t val;
99 asm volatile ("inb %w1, %b0" : "=a" (val) : "d" (addr));
100 return val;
101 }
102
103 static inline void writel(void *addr, uint32_t val)
104 {
105 *(volatile uint32_t *)addr = val;
106 }
107
108 static inline void writew(void *addr, uint16_t val)
109 {
110 *(volatile uint16_t *)addr = val;
111 }
112
113 static inline void writeb(void *addr, uint8_t val)
114 {
115 *(volatile uint8_t *)addr = val;
116 }
117
118 static inline uint32_t readl(const void *addr)
119 {
120 return *(volatile const uint32_t *)addr;
121 }
122
123 static inline uint16_t readw(const void *addr)
124 {
125 return *(volatile const uint16_t *)addr;
126 }
127
128 static inline uint8_t readb(const void *addr)
129 {
130 return *(volatile const uint8_t *)addr;
131 }
132
133 static inline void putc(int c)
134 {
135 outb(INFO_PORT, c);
136 }
137
138 static inline int isdigit(int c)
139 {
140 return c >= '0' && c <= '9';
141 }
142
143 void *memset(void *d1, int val, size_t len)
144 {
145 uint8_t *d = d1;
146
147 while (len--) {
148 *d++ = val;
149 }
150 return d1;
151 }
152
153 void *memcpy(void *d1, const void *s1, size_t len)
154 {
155 uint8_t *d = d1;
156 const uint8_t *s = s1;
157
158 while (len--) {
159 *d++ = *s++;
160 }
161 return d1;
162 }
163
164 void *memmove(void *d1, const void *s1, size_t len)
165 {
166 uint8_t *d = d1;
167 const uint8_t *s = s1;
168
169 if (d <= s) {
170 while (len--) {
171 *d++ = *s++;
172 }
173 } else {
174 d += len;
175 s += len;
176 while (len--) {
177 *--d = *--s;
178 }
179 }
180 return d1;
181 }
182
183 int memcmp(const void *s1, const void *s2, size_t len)
184 {
185 const int8_t *p1 = s1;
186 const int8_t *p2 = s2;
187
188 while (len--) {
189 int r = *p1++ - *p2++;
190 if(r)
191 return r;
192 }
193
194 return 0;
195 }
196
197 size_t strlen(const char *s)
198 {
199 const char *s1;
200 for(s1 = s; *s1 != '\0'; s1++);
201 return s1 - s;
202 }
203
204 /* from BSD ppp sources */
205 int vsnprintf(char *buf, int buflen, const char *fmt, va_list args)
206 {
207 int c, i, n;
208 int width, prec, fillch;
209 int base, len, neg;
210 unsigned long val = 0;
211 const char *f;
212 char *str, *buf0;
213 char num[32];
214 static const char hexchars[] = "0123456789abcdef";
215
216 buf0 = buf;
217 --buflen;
218 while (buflen > 0) {
219 for (f = fmt; *f != '%' && *f != 0; ++f)
220 ;
221 if (f > fmt) {
222 len = f - fmt;
223 if (len > buflen)
224 len = buflen;
225 memcpy(buf, fmt, len);
226 buf += len;
227 buflen -= len;
228 fmt = f;
229 }
230 if (*fmt == 0)
231 break;
232 c = *++fmt;
233 width = prec = 0;
234 fillch = ' ';
235 if (c == '0') {
236 fillch = '0';
237 c = *++fmt;
238 }
239 if (c == '*') {
240 width = va_arg(args, int);
241 c = *++fmt;
242 } else {
243 while (isdigit(c)) {
244 width = width * 10 + c - '0';
245 c = *++fmt;
246 }
247 }
248 if (c == '.') {
249 c = *++fmt;
250 if (c == '*') {
251 prec = va_arg(args, int);
252 c = *++fmt;
253 } else {
254 while (isdigit(c)) {
255 prec = prec * 10 + c - '0';
256 c = *++fmt;
257 }
258 }
259 }
260 /* modifiers */
261 switch(c) {
262 case 'l':
263 c = *++fmt;
264 break;
265 default:
266 break;
267 }
268 str = 0;
269 base = 0;
270 neg = 0;
271 ++fmt;
272 switch (c) {
273 case 'd':
274 i = va_arg(args, int);
275 if (i < 0) {
276 neg = 1;
277 val = -i;
278 } else
279 val = i;
280 base = 10;
281 break;
282 case 'o':
283 val = va_arg(args, unsigned int);
284 base = 8;
285 break;
286 case 'x':
287 case 'X':
288 val = va_arg(args, unsigned int);
289 base = 16;
290 break;
291 case 'p':
292 val = (unsigned long) va_arg(args, void *);
293 base = 16;
294 neg = 2;
295 break;
296 case 's':
297 str = va_arg(args, char *);
298 break;
299 case 'c':
300 num[0] = va_arg(args, int);
301 num[1] = 0;
302 str = num;
303 break;
304 default:
305 *buf++ = '%';
306 if (c != '%')
307 --fmt; /* so %z outputs %z etc. */
308 --buflen;
309 continue;
310 }
311 if (base != 0) {
312 str = num + sizeof(num);
313 *--str = 0;
314 while (str > num + neg) {
315 *--str = hexchars[val % base];
316 val = val / base;
317 if (--prec <= 0 && val == 0)
318 break;
319 }
320 switch (neg) {
321 case 1:
322 *--str = '-';
323 break;
324 case 2:
325 *--str = 'x';
326 *--str = '0';
327 break;
328 }
329 len = num + sizeof(num) - 1 - str;
330 } else {
331 len = strlen(str);
332 if (prec > 0 && len > prec)
333 len = prec;
334 }
335 if (width > 0) {
336 if (width > buflen)
337 width = buflen;
338 if ((n = width - len) > 0) {
339 buflen -= n;
340 for (; n > 0; --n)
341 *buf++ = fillch;
342 }
343 }
344 if (len > buflen)
345 len = buflen;
346 memcpy(buf, str, len);
347 buf += len;
348 buflen -= len;
349 }
350 *buf = 0;
351 return buf - buf0;
352 }
353
354 void bios_printf(int flags, const char *fmt, ...)
355 {
356 va_list ap;
357 char buf[1024];
358 const char *s;
359
360 if ((flags & BIOS_PRINTF_DEBHALT) == BIOS_PRINTF_DEBHALT)
361 outb(PANIC_PORT2, 0x00);
362
363 va_start(ap, fmt);
364 vsnprintf(buf, sizeof(buf), fmt, ap);
365 s = buf;
366 while (*s)
367 putc(*s++);
368 va_end(ap);
369 }
370
371 void delay_ms(int n)
372 {
373 int i, j;
374 for(i = 0; i < n; i++) {
375 #ifdef BX_QEMU
376 /* approximative ! */
377 for(j = 0; j < 1000000; j++);
378 #else
379 {
380 int r1, r2;
381 j = 66;
382 r1 = inb(0x61) & 0x10;
383 do {
384 r2 = inb(0x61) & 0x10;
385 if (r1 != r2) {
386 j--;
387 r1 = r2;
388 }
389 } while (j > 0);
390 }
391 #endif
392 }
393 }
394
395 uint16_t smp_cpus;
396 uint32_t cpuid_signature;
397 uint32_t cpuid_features;
398 uint32_t cpuid_ext_features;
399 unsigned long ram_size;
400 uint8_t bios_uuid[16];
401 #ifdef BX_USE_EBDA_TABLES
402 unsigned long ebda_cur_addr;
403 #endif
404 int acpi_enabled;
405 uint32_t pm_io_base, smb_io_base;
406 int pm_sci_int;
407 unsigned long bios_table_cur_addr;
408 unsigned long bios_table_end_addr;
409
410 #ifdef BX_QEMU
411 #define QEMU_CFG_CTL_PORT 0x510
412 #define QEMU_CFG_DATA_PORT 0x511
413 #define QEMU_CFG_SIGNATURE 0x00
414 #define QEMU_CFG_ID 0x01
415 #define QEMU_CFG_UUID 0x02
416
417 int qemu_cfg_port;
418
419 void qemu_cfg_select(int f)
420 {
421 outw(QEMU_CFG_CTL_PORT, f);
422 }
423
424 int qemu_cfg_port_probe()
425 {
426 char *sig = "QEMU";
427 int i;
428
429 qemu_cfg_select(QEMU_CFG_SIGNATURE);
430
431 for (i = 0; i < 4; i++)
432 if (inb(QEMU_CFG_DATA_PORT) != sig[i])
433 return 0;
434
435 return 1;
436 }
437
438 void qemu_cfg_read(uint8_t *buf, int len)
439 {
440 while (len--)
441 *(buf++) = inb(QEMU_CFG_DATA_PORT);
442 }
443 #endif
444
445 void uuid_probe(void)
446 {
447 #ifdef BX_QEMU
448 if(qemu_cfg_port) {
449 qemu_cfg_select(QEMU_CFG_UUID);
450 qemu_cfg_read(bios_uuid, 16);
451 return;
452 }
453 #endif
454 memset(bios_uuid, 0, 16);
455 }
456
457 void cpu_probe(void)
458 {
459 uint32_t eax, ebx, ecx, edx;
460 cpuid(1, eax, ebx, ecx, edx);
461 cpuid_signature = eax;
462 cpuid_features = edx;
463 cpuid_ext_features = ecx;
464 }
465
466 static int cmos_readb(int addr)
467 {
468 outb(0x70, addr);
469 return inb(0x71);
470 }
471
472 void ram_probe(void)
473 {
474 if (cmos_readb(0x34) | cmos_readb(0x35))
475 ram_size = (cmos_readb(0x34) | (cmos_readb(0x35) << 8)) * 65536 +
476 16 * 1024 * 1024;
477 else
478 ram_size = (cmos_readb(0x30) | (cmos_readb(0x31) << 8)) * 1024 +
479 1 * 1024 * 1024;
480 BX_INFO("ram_size=0x%08lx\n", ram_size);
481 #ifdef BX_USE_EBDA_TABLES
482 ebda_cur_addr = ((*(uint16_t *)(0x40e)) << 4) + 0x380;
483 BX_INFO("ebda_cur_addr: 0x%08lx\n", ebda_cur_addr);
484 #endif
485 }
486
487 /****************************************************/
488 /* SMP probe */
489
490 extern uint8_t smp_ap_boot_code_start;
491 extern uint8_t smp_ap_boot_code_end;
492
493 /* find the number of CPUs by launching a SIPI to them */
494 void smp_probe(void)
495 {
496 uint32_t val, sipi_vector;
497
498 writew(&smp_cpus, 1);
499 if (cpuid_features & CPUID_APIC) {
500
501 /* enable local APIC */
502 val = readl(APIC_BASE + APIC_SVR);
503 val |= APIC_ENABLED;
504 writel(APIC_BASE + APIC_SVR, val);
505
506 /* copy AP boot code */
507 memcpy((void *)AP_BOOT_ADDR, &smp_ap_boot_code_start,
508 &smp_ap_boot_code_end - &smp_ap_boot_code_start);
509
510 /* broadcast SIPI */
511 writel(APIC_BASE + APIC_ICR_LOW, 0x000C4500);
512 sipi_vector = AP_BOOT_ADDR >> 12;
513 writel(APIC_BASE + APIC_ICR_LOW, 0x000C4600 | sipi_vector);
514
515 delay_ms(10);
516 }
517 BX_INFO("Found %d cpu(s)\n", readw(&smp_cpus));
518 }
519
520 /****************************************************/
521 /* PCI init */
522
523 #define PCI_ADDRESS_SPACE_MEM 0x00
524 #define PCI_ADDRESS_SPACE_IO 0x01
525 #define PCI_ADDRESS_SPACE_MEM_PREFETCH 0x08
526
527 #define PCI_ROM_SLOT 6
528 #define PCI_NUM_REGIONS 7
529
530 #define PCI_DEVICES_MAX 64
531
532 #define PCI_VENDOR_ID 0x00 /* 16 bits */
533 #define PCI_DEVICE_ID 0x02 /* 16 bits */
534 #define PCI_COMMAND 0x04 /* 16 bits */
535 #define PCI_COMMAND_IO 0x1 /* Enable response in I/O space */
536 #define PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */
537 #define PCI_CLASS_DEVICE 0x0a /* Device class */
538 #define PCI_INTERRUPT_LINE 0x3c /* 8 bits */
539 #define PCI_INTERRUPT_PIN 0x3d /* 8 bits */
540 #define PCI_MIN_GNT 0x3e /* 8 bits */
541 #define PCI_MAX_LAT 0x3f /* 8 bits */
542
543 #define PCI_VENDOR_ID_INTEL 0x8086
544 #define PCI_DEVICE_ID_INTEL_82441 0x1237
545 #define PCI_DEVICE_ID_INTEL_82371SB_0 0x7000
546 #define PCI_DEVICE_ID_INTEL_82371SB_1 0x7010
547 #define PCI_DEVICE_ID_INTEL_82371AB_0 0x7110
548 #define PCI_DEVICE_ID_INTEL_82371AB 0x7111
549 #define PCI_DEVICE_ID_INTEL_82371AB_3 0x7113
550
551 #define PCI_VENDOR_ID_IBM 0x1014
552 #define PCI_VENDOR_ID_APPLE 0x106b
553
554 typedef struct PCIDevice {
555 int bus;
556 int devfn;
557 } PCIDevice;
558
559 static uint32_t pci_bios_io_addr;
560 static uint32_t pci_bios_mem_addr;
561 static uint32_t pci_bios_bigmem_addr;
562 /* host irqs corresponding to PCI irqs A-D */
563 static uint8_t pci_irqs[4] = { 11, 9, 11, 9 };
564 static PCIDevice i440_pcidev;
565
566 static void pci_config_writel(PCIDevice *d, uint32_t addr, uint32_t val)
567 {
568 outl(0xcf8, 0x80000000 | (d->bus << 16) | (d->devfn << 8) | (addr & 0xfc));
569 outl(0xcfc, val);
570 }
571
572 static void pci_config_writew(PCIDevice *d, uint32_t addr, uint32_t val)
573 {
574 outl(0xcf8, 0x80000000 | (d->bus << 16) | (d->devfn << 8) | (addr & 0xfc));
575 outw(0xcfc + (addr & 2), val);
576 }
577
578 static void pci_config_writeb(PCIDevice *d, uint32_t addr, uint32_t val)
579 {
580 outl(0xcf8, 0x80000000 | (d->bus << 16) | (d->devfn << 8) | (addr & 0xfc));
581 outb(0xcfc + (addr & 3), val);
582 }
583
584 static uint32_t pci_config_readl(PCIDevice *d, uint32_t addr)
585 {
586 outl(0xcf8, 0x80000000 | (d->bus << 16) | (d->devfn << 8) | (addr & 0xfc));
587 return inl(0xcfc);
588 }
589
590 static uint32_t pci_config_readw(PCIDevice *d, uint32_t addr)
591 {
592 outl(0xcf8, 0x80000000 | (d->bus << 16) | (d->devfn << 8) | (addr & 0xfc));
593 return inw(0xcfc + (addr & 2));
594 }
595
596 static uint32_t pci_config_readb(PCIDevice *d, uint32_t addr)
597 {
598 outl(0xcf8, 0x80000000 | (d->bus << 16) | (d->devfn << 8) | (addr & 0xfc));
599 return inb(0xcfc + (addr & 3));
600 }
601
602 static void pci_set_io_region_addr(PCIDevice *d, int region_num, uint32_t addr)
603 {
604 uint16_t cmd;
605 uint32_t ofs, old_addr;
606
607 if ( region_num == PCI_ROM_SLOT ) {
608 ofs = 0x30;
609 }else{
610 ofs = 0x10 + region_num * 4;
611 }
612
613 old_addr = pci_config_readl(d, ofs);
614
615 pci_config_writel(d, ofs, addr);
616 BX_INFO("region %d: 0x%08x\n", region_num, addr);
617
618 /* enable memory mappings */
619 cmd = pci_config_readw(d, PCI_COMMAND);
620 if ( region_num == PCI_ROM_SLOT )
621 cmd |= 2;
622 else if (old_addr & PCI_ADDRESS_SPACE_IO)
623 cmd |= 1;
624 else
625 cmd |= 2;
626 pci_config_writew(d, PCI_COMMAND, cmd);
627 }
628
629 /* return the global irq number corresponding to a given device irq
630 pin. We could also use the bus number to have a more precise
631 mapping. */
632 static int pci_slot_get_pirq(PCIDevice *pci_dev, int irq_num)
633 {
634 int slot_addend;
635 slot_addend = (pci_dev->devfn >> 3) - 1;
636 return (irq_num + slot_addend) & 3;
637 }
638
639 static void find_bios_table_area(void)
640 {
641 unsigned long addr;
642 for(addr = 0xf0000; addr < 0x100000; addr += 16) {
643 if (*(uint32_t *)addr == 0xaafb4442) {
644 bios_table_cur_addr = addr + 8;
645 bios_table_end_addr = bios_table_cur_addr + *(uint32_t *)(addr + 4);
646 BX_INFO("bios_table_addr: 0x%08lx end=0x%08lx\n",
647 bios_table_cur_addr, bios_table_end_addr);
648 return;
649 }
650 }
651 return;
652 }
653
654 static void bios_shadow_init(PCIDevice *d)
655 {
656 int v;
657
658 if (bios_table_cur_addr == 0)
659 return;
660
661 /* remap the BIOS to shadow RAM an keep it read/write while we
662 are writing tables */
663 v = pci_config_readb(d, 0x59);
664 v &= 0xcf;
665 pci_config_writeb(d, 0x59, v);
666 memcpy((void *)BIOS_TMP_STORAGE, (void *)0x000f0000, 0x10000);
667 v |= 0x30;
668 pci_config_writeb(d, 0x59, v);
669 memcpy((void *)0x000f0000, (void *)BIOS_TMP_STORAGE, 0x10000);
670
671 i440_pcidev = *d;
672 }
673
674 static void bios_lock_shadow_ram(void)
675 {
676 PCIDevice *d = &i440_pcidev;
677 int v;
678
679 wbinvd();
680 v = pci_config_readb(d, 0x59);
681 v = (v & 0x0f) | (0x10);
682 pci_config_writeb(d, 0x59, v);
683 }
684
685 static void pci_bios_init_bridges(PCIDevice *d)
686 {
687 uint16_t vendor_id, device_id;
688
689 vendor_id = pci_config_readw(d, PCI_VENDOR_ID);
690 device_id = pci_config_readw(d, PCI_DEVICE_ID);
691
692 if (vendor_id == PCI_VENDOR_ID_INTEL &&
693 (device_id == PCI_DEVICE_ID_INTEL_82371SB_0 ||
694 device_id == PCI_DEVICE_ID_INTEL_82371AB_0)) {
695 int i, irq;
696 uint8_t elcr[2];
697
698 /* PIIX3/PIIX4 PCI to ISA bridge */
699
700 elcr[0] = 0x00;
701 elcr[1] = 0x00;
702 for(i = 0; i < 4; i++) {
703 irq = pci_irqs[i];
704 /* set to trigger level */
705 elcr[irq >> 3] |= (1 << (irq & 7));
706 /* activate irq remapping in PIIX */
707 pci_config_writeb(d, 0x60 + i, irq);
708 }
709 outb(0x4d0, elcr[0]);
710 outb(0x4d1, elcr[1]);
711 BX_INFO("PIIX3/PIIX4 init: elcr=%02x %02x\n",
712 elcr[0], elcr[1]);
713 } else if (vendor_id == PCI_VENDOR_ID_INTEL && device_id == PCI_DEVICE_ID_INTEL_82441) {
714 /* i440 PCI bridge */
715 bios_shadow_init(d);
716 }
717 }
718
719 extern uint8_t smm_relocation_start, smm_relocation_end;
720 extern uint8_t smm_code_start, smm_code_end;
721
722 #ifdef BX_USE_SMM
723 static void smm_init(PCIDevice *d)
724 {
725 uint32_t value;
726
727 /* check if SMM init is already done */
728 value = pci_config_readl(d, 0x58);
729 if ((value & (1 << 25)) == 0) {
730
731 /* enable the SMM memory window */
732 pci_config_writeb(&i440_pcidev, 0x72, 0x02 | 0x48);
733
734 /* save original memory content */
735 memcpy((void *)0xa8000, (void *)0x38000, 0x8000);
736
737 /* copy the SMM relocation code */
738 memcpy((void *)0x38000, &smm_relocation_start,
739 &smm_relocation_end - &smm_relocation_start);
740
741 /* enable SMI generation when writing to the APMC register */
742 pci_config_writel(d, 0x58, value | (1 << 25));
743
744 /* init APM status port */
745 outb(0xb3, 0x01);
746
747 /* raise an SMI interrupt */
748 outb(0xb2, 0x00);
749
750 /* wait until SMM code executed */
751 while (inb(0xb3) != 0x00);
752
753 /* restore original memory content */
754 memcpy((void *)0x38000, (void *)0xa8000, 0x8000);
755
756 /* copy the SMM code */
757 memcpy((void *)0xa8000, &smm_code_start,
758 &smm_code_end - &smm_code_start);
759 wbinvd();
760
761 /* close the SMM memory window and enable normal SMM */
762 pci_config_writeb(&i440_pcidev, 0x72, 0x02 | 0x08);
763 }
764 }
765 #endif
766
767 static void piix4_pm_enable(PCIDevice *d)
768 {
769 /* PIIX4 Power Management device (for ACPI) */
770 pci_config_writel(d, 0x40, PM_IO_BASE | 1);
771 pci_config_writeb(d, 0x80, 0x01); /* enable PM io space */
772 pci_config_writel(d, 0x90, SMB_IO_BASE | 1);
773 pci_config_writeb(d, 0xd2, 0x09); /* enable SMBus io space */
774 #ifdef BX_USE_SMM
775 smm_init(d);
776 #endif
777 }
778
779 static void pci_bios_init_device(PCIDevice *d)
780 {
781 int class;
782 uint32_t *paddr;
783 int i, pin, pic_irq, vendor_id, device_id;
784
785 class = pci_config_readw(d, PCI_CLASS_DEVICE);
786 vendor_id = pci_config_readw(d, PCI_VENDOR_ID);
787 device_id = pci_config_readw(d, PCI_DEVICE_ID);
788 BX_INFO("PCI: bus=%d devfn=0x%02x: vendor_id=0x%04x device_id=0x%04x class=0x%04x\n",
789 d->bus, d->devfn, vendor_id, device_id, class);
790 switch(class) {
791 case 0x0101: /* Mass storage controller - IDE interface */
792 if (vendor_id == PCI_VENDOR_ID_INTEL &&
793 (device_id == PCI_DEVICE_ID_INTEL_82371SB_1 ||
794 device_id == PCI_DEVICE_ID_INTEL_82371AB)) {
795 /* PIIX3/PIIX4 IDE */
796 pci_config_writew(d, 0x40, 0x8000); // enable IDE0
797 pci_config_writew(d, 0x42, 0x8000); // enable IDE1
798 goto default_map;
799 } else {
800 /* IDE: we map it as in ISA mode */
801 pci_set_io_region_addr(d, 0, 0x1f0);
802 pci_set_io_region_addr(d, 1, 0x3f4);
803 pci_set_io_region_addr(d, 2, 0x170);
804 pci_set_io_region_addr(d, 3, 0x374);
805 }
806 break;
807 case 0x0300: /* Display controller - VGA compatible controller */
808 if (vendor_id != 0x1234)
809 goto default_map;
810 /* VGA: map frame buffer to default Bochs VBE address */
811 pci_set_io_region_addr(d, 0, 0xE0000000);
812 break;
813 case 0x0800: /* Generic system peripheral - PIC */
814 if (vendor_id == PCI_VENDOR_ID_IBM) {
815 /* IBM */
816 if (device_id == 0x0046 || device_id == 0xFFFF) {
817 /* MPIC & MPIC2 */
818 pci_set_io_region_addr(d, 0, 0x80800000 + 0x00040000);
819 }
820 }
821 break;
822 case 0xff00:
823 if (vendor_id == PCI_VENDOR_ID_APPLE &&
824 (device_id == 0x0017 || device_id == 0x0022)) {
825 /* macio bridge */
826 pci_set_io_region_addr(d, 0, 0x80800000);
827 }
828 break;
829 default:
830 default_map:
831 /* default memory mappings */
832 for(i = 0; i < PCI_NUM_REGIONS; i++) {
833 int ofs;
834 uint32_t val, size ;
835
836 if (i == PCI_ROM_SLOT)
837 ofs = 0x30;
838 else
839 ofs = 0x10 + i * 4;
840 pci_config_writel(d, ofs, 0xffffffff);
841 val = pci_config_readl(d, ofs);
842 if (val != 0) {
843 size = (~(val & ~0xf)) + 1;
844 if (val & PCI_ADDRESS_SPACE_IO)
845 paddr = &pci_bios_io_addr;
846 else if (size >= 0x04000000)
847 paddr = &pci_bios_bigmem_addr;
848 else
849 paddr = &pci_bios_mem_addr;
850 *paddr = (*paddr + size - 1) & ~(size - 1);
851 pci_set_io_region_addr(d, i, *paddr);
852 *paddr += size;
853 }
854 }
855 break;
856 }
857
858 /* map the interrupt */
859 pin = pci_config_readb(d, PCI_INTERRUPT_PIN);
860 if (pin != 0) {
861 pin = pci_slot_get_pirq(d, pin - 1);
862 pic_irq = pci_irqs[pin];
863 pci_config_writeb(d, PCI_INTERRUPT_LINE, pic_irq);
864 }
865
866 if (vendor_id == PCI_VENDOR_ID_INTEL && device_id == PCI_DEVICE_ID_INTEL_82371AB_3) {
867 /* PIIX4 Power Management device (for ACPI) */
868 pm_io_base = PM_IO_BASE;
869 smb_io_base = SMB_IO_BASE;
870 pm_sci_int = pci_config_readb(d, PCI_INTERRUPT_LINE);
871 piix4_pm_enable(d);
872 acpi_enabled = 1;
873 }
874 }
875
876 void pci_for_each_device(void (*init_func)(PCIDevice *d))
877 {
878 PCIDevice d1, *d = &d1;
879 int bus, devfn;
880 uint16_t vendor_id, device_id;
881
882 for(bus = 0; bus < 1; bus++) {
883 for(devfn = 0; devfn < 256; devfn++) {
884 d->bus = bus;
885 d->devfn = devfn;
886 vendor_id = pci_config_readw(d, PCI_VENDOR_ID);
887 device_id = pci_config_readw(d, PCI_DEVICE_ID);
888 if (vendor_id != 0xffff || device_id != 0xffff) {
889 init_func(d);
890 }
891 }
892 }
893 }
894
895 void pci_bios_init(void)
896 {
897 pci_bios_io_addr = 0xc000;
898 pci_bios_mem_addr = 0xf0000000;
899 pci_bios_bigmem_addr = ram_size;
900 if (pci_bios_bigmem_addr < 0x90000000)
901 pci_bios_bigmem_addr = 0x90000000;
902
903 pci_for_each_device(pci_bios_init_bridges);
904
905 pci_for_each_device(pci_bios_init_device);
906 }
907
908 /****************************************************/
909 /* Multi Processor table init */
910
911 static void putb(uint8_t **pp, int val)
912 {
913 uint8_t *q;
914 q = *pp;
915 *q++ = val;
916 *pp = q;
917 }
918
919 static void putstr(uint8_t **pp, const char *str)
920 {
921 uint8_t *q;
922 q = *pp;
923 while (*str)
924 *q++ = *str++;
925 *pp = q;
926 }
927
928 static void putle16(uint8_t **pp, int val)
929 {
930 uint8_t *q;
931 q = *pp;
932 *q++ = val;
933 *q++ = val >> 8;
934 *pp = q;
935 }
936
937 static void putle32(uint8_t **pp, int val)
938 {
939 uint8_t *q;
940 q = *pp;
941 *q++ = val;
942 *q++ = val >> 8;
943 *q++ = val >> 16;
944 *q++ = val >> 24;
945 *pp = q;
946 }
947
948 static int mpf_checksum(const uint8_t *data, int len)
949 {
950 int sum, i;
951 sum = 0;
952 for(i = 0; i < len; i++)
953 sum += data[i];
954 return sum & 0xff;
955 }
956
957 static unsigned long align(unsigned long addr, unsigned long v)
958 {
959 return (addr + v - 1) & ~(v - 1);
960 }
961
962 static void mptable_init(void)
963 {
964 uint8_t *mp_config_table, *q, *float_pointer_struct;
965 int ioapic_id, i, len;
966 int mp_config_table_size;
967
968 #ifdef BX_QEMU
969 if (smp_cpus <= 1)
970 return;
971 #endif
972
973 #ifdef BX_USE_EBDA_TABLES
974 mp_config_table = (uint8_t *)(ram_size - ACPI_DATA_SIZE - MPTABLE_MAX_SIZE);
975 #else
976 bios_table_cur_addr = align(bios_table_cur_addr, 16);
977 mp_config_table = (uint8_t *)bios_table_cur_addr;
978 #endif
979 q = mp_config_table;
980 putstr(&q, "PCMP"); /* "PCMP signature */
981 putle16(&q, 0); /* table length (patched later) */
982 putb(&q, 4); /* spec rev */
983 putb(&q, 0); /* checksum (patched later) */
984 #ifdef BX_QEMU
985 putstr(&q, "QEMUCPU "); /* OEM id */
986 #else
987 putstr(&q, "BOCHSCPU");
988 #endif
989 putstr(&q, "0.1 "); /* vendor id */
990 putle32(&q, 0); /* OEM table ptr */
991 putle16(&q, 0); /* OEM table size */
992 putle16(&q, smp_cpus + 18); /* entry count */
993 putle32(&q, 0xfee00000); /* local APIC addr */
994 putle16(&q, 0); /* ext table length */
995 putb(&q, 0); /* ext table checksum */
996 putb(&q, 0); /* reserved */
997
998 for(i = 0; i < smp_cpus; i++) {
999 putb(&q, 0); /* entry type = processor */
1000 putb(&q, i); /* APIC id */
1001 putb(&q, 0x11); /* local APIC version number */
1002 if (i == 0)
1003 putb(&q, 3); /* cpu flags: enabled, bootstrap cpu */
1004 else
1005 putb(&q, 1); /* cpu flags: enabled */
1006 putb(&q, 0); /* cpu signature */
1007 putb(&q, 6);
1008 putb(&q, 0);
1009 putb(&q, 0);
1010 putle16(&q, 0x201); /* feature flags */
1011 putle16(&q, 0);
1012
1013 putle16(&q, 0); /* reserved */
1014 putle16(&q, 0);
1015 putle16(&q, 0);
1016 putle16(&q, 0);
1017 }
1018
1019 /* isa bus */
1020 putb(&q, 1); /* entry type = bus */
1021 putb(&q, 0); /* bus ID */
1022 putstr(&q, "ISA ");
1023
1024 /* ioapic */
1025 ioapic_id = smp_cpus;
1026 putb(&q, 2); /* entry type = I/O APIC */
1027 putb(&q, ioapic_id); /* apic ID */
1028 putb(&q, 0x11); /* I/O APIC version number */
1029 putb(&q, 1); /* enable */
1030 putle32(&q, 0xfec00000); /* I/O APIC addr */
1031
1032 /* irqs */
1033 for(i = 0; i < 16; i++) {
1034 putb(&q, 3); /* entry type = I/O interrupt */
1035 putb(&q, 0); /* interrupt type = vectored interrupt */
1036 putb(&q, 0); /* flags: po=0, el=0 */
1037 putb(&q, 0);
1038 putb(&q, 0); /* source bus ID = ISA */
1039 putb(&q, i); /* source bus IRQ */
1040 putb(&q, ioapic_id); /* dest I/O APIC ID */
1041 putb(&q, i); /* dest I/O APIC interrupt in */
1042 }
1043 /* patch length */
1044 len = q - mp_config_table;
1045 mp_config_table[4] = len;
1046 mp_config_table[5] = len >> 8;
1047
1048 mp_config_table[7] = -mpf_checksum(mp_config_table, q - mp_config_table);
1049
1050 mp_config_table_size = q - mp_config_table;
1051
1052 #ifndef BX_USE_EBDA_TABLES
1053 bios_table_cur_addr += mp_config_table_size;
1054 #endif
1055
1056 /* floating pointer structure */
1057 #ifdef BX_USE_EBDA_TABLES
1058 ebda_cur_addr = align(ebda_cur_addr, 16);
1059 float_pointer_struct = (uint8_t *)ebda_cur_addr;
1060 #else
1061 bios_table_cur_addr = align(bios_table_cur_addr, 16);
1062 float_pointer_struct = (uint8_t *)bios_table_cur_addr;
1063 #endif
1064 q = float_pointer_struct;
1065 putstr(&q, "_MP_");
1066 /* pointer to MP config table */
1067 putle32(&q, (unsigned long)mp_config_table);
1068
1069 putb(&q, 1); /* length in 16 byte units */
1070 putb(&q, 4); /* MP spec revision */
1071 putb(&q, 0); /* checksum (patched later) */
1072 putb(&q, 0); /* MP feature byte 1 */
1073
1074 putb(&q, 0);
1075 putb(&q, 0);
1076 putb(&q, 0);
1077 putb(&q, 0);
1078 float_pointer_struct[10] =
1079 -mpf_checksum(float_pointer_struct, q - float_pointer_struct);
1080 #ifdef BX_USE_EBDA_TABLES
1081 ebda_cur_addr += (q - float_pointer_struct);
1082 #else
1083 bios_table_cur_addr += (q - float_pointer_struct);
1084 #endif
1085 BX_INFO("MP table addr=0x%08lx MPC table addr=0x%08lx size=0x%x\n",
1086 (unsigned long)float_pointer_struct,
1087 (unsigned long)mp_config_table,
1088 mp_config_table_size);
1089 }
1090
1091 /****************************************************/
1092 /* ACPI tables init */
1093
1094 /* Table structure from Linux kernel (the ACPI tables are under the
1095 BSD license) */
1096
1097 #define ACPI_TABLE_HEADER_DEF /* ACPI common table header */ \
1098 uint8_t signature [4]; /* ACPI signature (4 ASCII characters) */\
1099 uint32_t length; /* Length of table, in bytes, including header */\
1100 uint8_t revision; /* ACPI Specification minor version # */\
1101 uint8_t checksum; /* To make sum of entire table == 0 */\
1102 uint8_t oem_id [6]; /* OEM identification */\
1103 uint8_t oem_table_id [8]; /* OEM table identification */\
1104 uint32_t oem_revision; /* OEM revision number */\
1105 uint8_t asl_compiler_id [4]; /* ASL compiler vendor ID */\
1106 uint32_t asl_compiler_revision; /* ASL compiler revision number */
1107
1108
1109 struct acpi_table_header /* ACPI common table header */
1110 {
1111 ACPI_TABLE_HEADER_DEF
1112 };
1113
1114 struct rsdp_descriptor /* Root System Descriptor Pointer */
1115 {
1116 uint8_t signature [8]; /* ACPI signature, contains "RSD PTR " */
1117 uint8_t checksum; /* To make sum of struct == 0 */
1118 uint8_t oem_id [6]; /* OEM identification */
1119 uint8_t revision; /* Must be 0 for 1.0, 2 for 2.0 */
1120 uint32_t rsdt_physical_address; /* 32-bit physical address of RSDT */
1121 uint32_t length; /* XSDT Length in bytes including hdr */
1122 uint64_t xsdt_physical_address; /* 64-bit physical address of XSDT */
1123 uint8_t extended_checksum; /* Checksum of entire table */
1124 uint8_t reserved [3]; /* Reserved field must be 0 */
1125 };
1126
1127 /*
1128 * ACPI 1.0 Root System Description Table (RSDT)
1129 */
1130 struct rsdt_descriptor_rev1
1131 {
1132 ACPI_TABLE_HEADER_DEF /* ACPI common table header */
1133 uint32_t table_offset_entry [3]; /* Array of pointers to other */
1134 /* ACPI tables */
1135 };
1136
1137 /*
1138 * ACPI 1.0 Firmware ACPI Control Structure (FACS)
1139 */
1140 struct facs_descriptor_rev1
1141 {
1142 uint8_t signature[4]; /* ACPI Signature */
1143 uint32_t length; /* Length of structure, in bytes */
1144 uint32_t hardware_signature; /* Hardware configuration signature */
1145 uint32_t firmware_waking_vector; /* ACPI OS waking vector */
1146 uint32_t global_lock; /* Global Lock */
1147 uint32_t S4bios_f : 1; /* Indicates if S4BIOS support is present */
1148 uint32_t reserved1 : 31; /* Must be 0 */
1149 uint8_t resverved3 [40]; /* Reserved - must be zero */
1150 };
1151
1152
1153 /*
1154 * ACPI 1.0 Fixed ACPI Description Table (FADT)
1155 */
1156 struct fadt_descriptor_rev1
1157 {
1158 ACPI_TABLE_HEADER_DEF /* ACPI common table header */
1159 uint32_t firmware_ctrl; /* Physical address of FACS */
1160 uint32_t dsdt; /* Physical address of DSDT */
1161 uint8_t model; /* System Interrupt Model */
1162 uint8_t reserved1; /* Reserved */
1163 uint16_t sci_int; /* System vector of SCI interrupt */
1164 uint32_t smi_cmd; /* Port address of SMI command port */
1165 uint8_t acpi_enable; /* Value to write to smi_cmd to enable ACPI */
1166 uint8_t acpi_disable; /* Value to write to smi_cmd to disable ACPI */
1167 uint8_t S4bios_req; /* Value to write to SMI CMD to enter S4BIOS state */
1168 uint8_t reserved2; /* Reserved - must be zero */
1169 uint32_t pm1a_evt_blk; /* Port address of Power Mgt 1a acpi_event Reg Blk */
1170 uint32_t pm1b_evt_blk; /* Port address of Power Mgt 1b acpi_event Reg Blk */
1171 uint32_t pm1a_cnt_blk; /* Port address of Power Mgt 1a Control Reg Blk */
1172 uint32_t pm1b_cnt_blk; /* Port address of Power Mgt 1b Control Reg Blk */
1173 uint32_t pm2_cnt_blk; /* Port address of Power Mgt 2 Control Reg Blk */
1174 uint32_t pm_tmr_blk; /* Port address of Power Mgt Timer Ctrl Reg Blk */
1175 uint32_t gpe0_blk; /* Port addr of General Purpose acpi_event 0 Reg Blk */
1176 uint32_t gpe1_blk; /* Port addr of General Purpose acpi_event 1 Reg Blk */
1177 uint8_t pm1_evt_len; /* Byte length of ports at pm1_x_evt_blk */
1178 uint8_t pm1_cnt_len; /* Byte length of ports at pm1_x_cnt_blk */
1179 uint8_t pm2_cnt_len; /* Byte Length of ports at pm2_cnt_blk */
1180 uint8_t pm_tmr_len; /* Byte Length of ports at pm_tm_blk */
1181 uint8_t gpe0_blk_len; /* Byte Length of ports at gpe0_blk */
1182 uint8_t gpe1_blk_len; /* Byte Length of ports at gpe1_blk */
1183 uint8_t gpe1_base; /* Offset in gpe model where gpe1 events start */
1184 uint8_t reserved3; /* Reserved */
1185 uint16_t plvl2_lat; /* Worst case HW latency to enter/exit C2 state */
1186 uint16_t plvl3_lat; /* Worst case HW latency to enter/exit C3 state */
1187 uint16_t flush_size; /* Size of area read to flush caches */
1188 uint16_t flush_stride; /* Stride used in flushing caches */
1189 uint8_t duty_offset; /* Bit location of duty cycle field in p_cnt reg */
1190 uint8_t duty_width; /* Bit width of duty cycle field in p_cnt reg */
1191 uint8_t day_alrm; /* Index to day-of-month alarm in RTC CMOS RAM */
1192 uint8_t mon_alrm; /* Index to month-of-year alarm in RTC CMOS RAM */
1193 uint8_t century; /* Index to century in RTC CMOS RAM */
1194 uint8_t reserved4; /* Reserved */
1195 uint8_t reserved4a; /* Reserved */
1196 uint8_t reserved4b; /* Reserved */
1197 #if 0
1198 uint32_t wb_invd : 1; /* The wbinvd instruction works properly */
1199 uint32_t wb_invd_flush : 1; /* The wbinvd flushes but does not invalidate */
1200 uint32_t proc_c1 : 1; /* All processors support C1 state */
1201 uint32_t plvl2_up : 1; /* C2 state works on MP system */
1202 uint32_t pwr_button : 1; /* Power button is handled as a generic feature */
1203 uint32_t sleep_button : 1; /* Sleep button is handled as a generic feature, or not present */
1204 uint32_t fixed_rTC : 1; /* RTC wakeup stat not in fixed register space */
1205 uint32_t rtcs4 : 1; /* RTC wakeup stat not possible from S4 */
1206 uint32_t tmr_val_ext : 1; /* The tmr_val width is 32 bits (0 = 24 bits) */
1207 uint32_t reserved5 : 23; /* Reserved - must be zero */
1208 #else
1209 uint32_t flags;
1210 #endif
1211 };
1212
1213 /*
1214 * MADT values and structures
1215 */
1216
1217 /* Values for MADT PCATCompat */
1218
1219 #define DUAL_PIC 0
1220 #define MULTIPLE_APIC 1
1221
1222
1223 /* Master MADT */
1224
1225 struct multiple_apic_table
1226 {
1227 ACPI_TABLE_HEADER_DEF /* ACPI common table header */
1228 uint32_t local_apic_address; /* Physical address of local APIC */
1229 #if 0
1230 uint32_t PCATcompat : 1; /* A one indicates system also has dual 8259s */
1231 uint32_t reserved1 : 31;
1232 #else
1233 uint32_t flags;
1234 #endif
1235 };
1236
1237
1238 /* Values for Type in APIC_HEADER_DEF */
1239
1240 #define APIC_PROCESSOR 0
1241 #define APIC_IO 1
1242 #define APIC_XRUPT_OVERRIDE 2
1243 #define APIC_NMI 3
1244 #define APIC_LOCAL_NMI 4
1245 #define APIC_ADDRESS_OVERRIDE 5
1246 #define APIC_IO_SAPIC 6
1247 #define APIC_LOCAL_SAPIC 7
1248 #define APIC_XRUPT_SOURCE 8
1249 #define APIC_RESERVED 9 /* 9 and greater are reserved */
1250
1251 /*
1252 * MADT sub-structures (Follow MULTIPLE_APIC_DESCRIPTION_TABLE)
1253 */
1254 #define APIC_HEADER_DEF /* Common APIC sub-structure header */\
1255 uint8_t type; \
1256 uint8_t length;
1257
1258 /* Sub-structures for MADT */
1259
1260 struct madt_processor_apic
1261 {
1262 APIC_HEADER_DEF
1263 uint8_t processor_id; /* ACPI processor id */
1264 uint8_t local_apic_id; /* Processor's local APIC id */
1265 #if 0
1266 uint32_t processor_enabled: 1; /* Processor is usable if set */
1267 uint32_t reserved2 : 31; /* Reserved, must be zero */
1268 #else
1269 uint32_t flags;
1270 #endif
1271 };
1272
1273 struct madt_io_apic
1274 {
1275 APIC_HEADER_DEF
1276 uint8_t io_apic_id; /* I/O APIC ID */
1277 uint8_t reserved; /* Reserved - must be zero */
1278 uint32_t address; /* APIC physical address */
1279 uint32_t interrupt; /* Global system interrupt where INTI
1280 * lines start */
1281 };
1282
1283 #include "acpi-dsdt.hex"
1284
1285 static inline uint16_t cpu_to_le16(uint16_t x)
1286 {
1287 return x;
1288 }
1289
1290 static inline uint32_t cpu_to_le32(uint32_t x)
1291 {
1292 return x;
1293 }
1294
1295 static int acpi_checksum(const uint8_t *data, int len)
1296 {
1297 int sum, i;
1298 sum = 0;
1299 for(i = 0; i < len; i++)
1300 sum += data[i];
1301 return (-sum) & 0xff;
1302 }
1303
1304 static void acpi_build_table_header(struct acpi_table_header *h,
1305 char *sig, int len, uint8_t rev)
1306 {
1307 memcpy(h->signature, sig, 4);
1308 h->length = cpu_to_le32(len);
1309 h->revision = rev;
1310 #ifdef BX_QEMU
1311 memcpy(h->oem_id, "QEMU ", 6);
1312 memcpy(h->oem_table_id, "QEMU", 4);
1313 #else
1314 memcpy(h->oem_id, "BOCHS ", 6);
1315 memcpy(h->oem_table_id, "BXPC", 4);
1316 #endif
1317 memcpy(h->oem_table_id + 4, sig, 4);
1318 h->oem_revision = cpu_to_le32(1);
1319 #ifdef BX_QEMU
1320 memcpy(h->asl_compiler_id, "QEMU", 4);
1321 #else
1322 memcpy(h->asl_compiler_id, "BXPC", 4);
1323 #endif
1324 h->asl_compiler_revision = cpu_to_le32(1);
1325 h->checksum = acpi_checksum((void *)h, len);
1326 }
1327
1328 int acpi_build_processor_ssdt(uint8_t *ssdt)
1329 {
1330 uint8_t *ssdt_ptr = ssdt;
1331 int i, length;
1332 int acpi_cpus = smp_cpus > 0xff ? 0xff : smp_cpus;
1333
1334 ssdt_ptr[9] = 0; // checksum;
1335 ssdt_ptr += sizeof(struct acpi_table_header);
1336
1337 // caluculate the length of processor block and scope block excluding PkgLength
1338 length = 0x0d * acpi_cpus + 4;
1339
1340 // build processor scope header
1341 *(ssdt_ptr++) = 0x10; // ScopeOp
1342 if (length <= 0x3e) {
1343 *(ssdt_ptr++) = length + 1;
1344 } else {
1345 *(ssdt_ptr++) = 0x7F;
1346 *(ssdt_ptr++) = (length + 2) >> 6;
1347 }
1348 *(ssdt_ptr++) = '_'; // Name
1349 *(ssdt_ptr++) = 'P';
1350 *(ssdt_ptr++) = 'R';
1351 *(ssdt_ptr++) = '_';
1352
1353 // build object for each processor
1354 for(i=0;i<acpi_cpus;i++) {
1355 *(ssdt_ptr++) = 0x5B; // ProcessorOp
1356 *(ssdt_ptr++) = 0x83;
1357 *(ssdt_ptr++) = 0x0B; // Length
1358 *(ssdt_ptr++) = 'C'; // Name (CPUxx)
1359 *(ssdt_ptr++) = 'P';
1360 if ((i & 0xf0) != 0)
1361 *(ssdt_ptr++) = (i >> 4) < 0xa ? (i >> 4) + '0' : (i >> 4) + 'A' - 0xa;
1362 else
1363 *(ssdt_ptr++) = 'U';
1364 *(ssdt_ptr++) = (i & 0xf) < 0xa ? (i & 0xf) + '0' : (i & 0xf) + 'A' - 0xa;
1365 *(ssdt_ptr++) = i;
1366 *(ssdt_ptr++) = 0x10; // Processor block address
1367 *(ssdt_ptr++) = 0xb0;
1368 *(ssdt_ptr++) = 0;
1369 *(ssdt_ptr++) = 0;
1370 *(ssdt_ptr++) = 6; // Processor block length
1371 }
1372
1373 acpi_build_table_header((struct acpi_table_header *)ssdt,
1374 "SSDT", ssdt_ptr - ssdt, 1);
1375
1376 return ssdt_ptr - ssdt;
1377 }
1378
1379 /* base_addr must be a multiple of 4KB */
1380 void acpi_bios_init(void)
1381 {
1382 struct rsdp_descriptor *rsdp;
1383 struct rsdt_descriptor_rev1 *rsdt;
1384 struct fadt_descriptor_rev1 *fadt;
1385 struct facs_descriptor_rev1 *facs;
1386 struct multiple_apic_table *madt;
1387 uint8_t *dsdt, *ssdt;
1388 uint32_t base_addr, rsdt_addr, fadt_addr, addr, facs_addr, dsdt_addr, ssdt_addr;
1389 uint32_t acpi_tables_size, madt_addr, madt_size;
1390 int i;
1391
1392 /* reserve memory space for tables */
1393 #ifdef BX_USE_EBDA_TABLES
1394 ebda_cur_addr = align(ebda_cur_addr, 16);
1395 rsdp = (void *)(ebda_cur_addr);
1396 ebda_cur_addr += sizeof(*rsdp);
1397 #else
1398 bios_table_cur_addr = align(bios_table_cur_addr, 16);
1399 rsdp = (void *)(bios_table_cur_addr);
1400 bios_table_cur_addr += sizeof(*rsdp);
1401 #endif
1402
1403 addr = base_addr = ram_size - ACPI_DATA_SIZE;
1404 rsdt_addr = addr;
1405 rsdt = (void *)(addr);
1406 addr += sizeof(*rsdt);
1407
1408 fadt_addr = addr;
1409 fadt = (void *)(addr);
1410 addr += sizeof(*fadt);
1411
1412 /* XXX: FACS should be in RAM */
1413 addr = (addr + 63) & ~63; /* 64 byte alignment for FACS */
1414 facs_addr = addr;
1415 facs = (void *)(addr);
1416 addr += sizeof(*facs);
1417
1418 dsdt_addr = addr;
1419 dsdt = (void *)(addr);
1420 addr += sizeof(AmlCode);
1421
1422 ssdt_addr = addr;
1423 ssdt = (void *)(addr);
1424 addr += acpi_build_processor_ssdt(ssdt);
1425
1426 addr = (addr + 7) & ~7;
1427 madt_addr = addr;
1428 madt_size = sizeof(*madt) +
1429 sizeof(struct madt_processor_apic) * smp_cpus +
1430 sizeof(struct madt_io_apic);
1431 madt = (void *)(addr);
1432 addr += madt_size;
1433
1434 acpi_tables_size = addr - base_addr;
1435
1436 BX_INFO("ACPI tables: RSDP addr=0x%08lx ACPI DATA addr=0x%08lx size=0x%x\n",
1437 (unsigned long)rsdp,
1438 (unsigned long)rsdt, acpi_tables_size);
1439
1440 /* RSDP */
1441 memset(rsdp, 0, sizeof(*rsdp));
1442 memcpy(rsdp->signature, "RSD PTR ", 8);
1443 #ifdef BX_QEMU
1444 memcpy(rsdp->oem_id, "QEMU ", 6);
1445 #else
1446 memcpy(rsdp->oem_id, "BOCHS ", 6);
1447 #endif
1448 rsdp->rsdt_physical_address = cpu_to_le32(rsdt_addr);
1449 rsdp->checksum = acpi_checksum((void *)rsdp, 20);
1450
1451 /* RSDT */
1452 memset(rsdt, 0, sizeof(*rsdt));
1453 rsdt->table_offset_entry[0] = cpu_to_le32(fadt_addr);
1454 rsdt->table_offset_entry[1] = cpu_to_le32(madt_addr);
1455 rsdt->table_offset_entry[2] = cpu_to_le32(ssdt_addr);
1456 acpi_build_table_header((struct acpi_table_header *)rsdt,
1457 "RSDT", sizeof(*rsdt), 1);
1458
1459 /* FADT */
1460 memset(fadt, 0, sizeof(*fadt));
1461 fadt->firmware_ctrl = cpu_to_le32(facs_addr);
1462 fadt->dsdt = cpu_to_le32(dsdt_addr);
1463 fadt->model = 1;
1464 fadt->reserved1 = 0;
1465 fadt->sci_int = cpu_to_le16(pm_sci_int);
1466 fadt->smi_cmd = cpu_to_le32(SMI_CMD_IO_ADDR);
1467 fadt->acpi_enable = 0xf1;
1468 fadt->acpi_disable = 0xf0;
1469 fadt->pm1a_evt_blk = cpu_to_le32(pm_io_base);
1470 fadt->pm1a_cnt_blk = cpu_to_le32(pm_io_base + 0x04);
1471 fadt->pm_tmr_blk = cpu_to_le32(pm_io_base + 0x08);
1472 fadt->pm1_evt_len = 4;
1473 fadt->pm1_cnt_len = 2;
1474 fadt->pm_tmr_len = 4;
1475 fadt->plvl2_lat = cpu_to_le16(0xfff); // C2 state not supported
1476 fadt->plvl3_lat = cpu_to_le16(0xfff); // C3 state not supported
1477 /* WBINVD + PROC_C1 + PWR_BUTTON + SLP_BUTTON + FIX_RTC */
1478 fadt->flags = cpu_to_le32((1 << 0) | (1 << 2) | (1 << 4) | (1 << 5) | (1 << 6));
1479 acpi_build_table_header((struct acpi_table_header *)fadt, "FACP",
1480 sizeof(*fadt), 1);
1481
1482 /* FACS */
1483 memset(facs, 0, sizeof(*facs));
1484 memcpy(facs->signature, "FACS", 4);
1485 facs->length = cpu_to_le32(sizeof(*facs));
1486 BX_INFO("Firmware waking vector %p\n", &facs->firmware_waking_vector);
1487
1488 /* DSDT */
1489 memcpy(dsdt, AmlCode, sizeof(AmlCode));
1490
1491 /* MADT */
1492 {
1493 struct madt_processor_apic *apic;
1494 struct madt_io_apic *io_apic;
1495
1496 memset(madt, 0, madt_size);
1497 madt->local_apic_address = cpu_to_le32(0xfee00000);
1498 madt->flags = cpu_to_le32(1);
1499 apic = (void *)(madt + 1);
1500 for(i=0;i<smp_cpus;i++) {
1501 apic->type = APIC_PROCESSOR;
1502 apic->length = sizeof(*apic);
1503 apic->processor_id = i;
1504 apic->local_apic_id = i;
1505 apic->flags = cpu_to_le32(1);
1506 apic++;
1507 }
1508 io_apic = (void *)apic;
1509 io_apic->type = APIC_IO;
1510 io_apic->length = sizeof(*io_apic);
1511 io_apic->io_apic_id = smp_cpus;
1512 io_apic->address = cpu_to_le32(0xfec00000);
1513 io_apic->interrupt = cpu_to_le32(0);
1514
1515 acpi_build_table_header((struct acpi_table_header *)madt,
1516 "APIC", madt_size, 1);
1517 }
1518 }
1519
1520 /* SMBIOS entry point -- must be written to a 16-bit aligned address
1521 between 0xf0000 and 0xfffff.
1522 */
1523 struct smbios_entry_point {
1524 char anchor_string[4];
1525 uint8_t checksum;
1526 uint8_t length;
1527 uint8_t smbios_major_version;
1528 uint8_t smbios_minor_version;
1529 uint16_t max_structure_size;
1530 uint8_t entry_point_revision;
1531 uint8_t formatted_area[5];
1532 char intermediate_anchor_string[5];
1533 uint8_t intermediate_checksum;
1534 uint16_t structure_table_length;
1535 uint32_t structure_table_address;
1536 uint16_t number_of_structures;
1537 uint8_t smbios_bcd_revision;
1538 } __attribute__((__packed__));
1539
1540 /* This goes at the beginning of every SMBIOS structure. */
1541 struct smbios_structure_header {
1542 uint8_t type;
1543 uint8_t length;
1544 uint16_t handle;
1545 } __attribute__((__packed__));
1546
1547 /* SMBIOS type 0 - BIOS Information */
1548 struct smbios_type_0 {
1549 struct smbios_structure_header header;
1550 uint8_t vendor_str;
1551 uint8_t bios_version_str;
1552 uint16_t bios_starting_address_segment;
1553 uint8_t bios_release_date_str;
1554 uint8_t bios_rom_size;
1555 uint8_t bios_characteristics[8];
1556 uint8_t bios_characteristics_extension_bytes[2];
1557 uint8_t system_bios_major_release;
1558 uint8_t system_bios_minor_release;
1559 uint8_t embedded_controller_major_release;
1560 uint8_t embedded_controller_minor_release;
1561 } __attribute__((__packed__));
1562
1563 /* SMBIOS type 1 - System Information */
1564 struct smbios_type_1 {
1565 struct smbios_structure_header header;
1566 uint8_t manufacturer_str;
1567 uint8_t product_name_str;
1568 uint8_t version_str;
1569 uint8_t serial_number_str;
1570 uint8_t uuid[16];
1571 uint8_t wake_up_type;
1572 uint8_t sku_number_str;
1573 uint8_t family_str;
1574 } __attribute__((__packed__));
1575
1576 /* SMBIOS type 3 - System Enclosure (v2.3) */
1577 struct smbios_type_3 {
1578 struct smbios_structure_header header;
1579 uint8_t manufacturer_str;
1580 uint8_t type;
1581 uint8_t version_str;
1582 uint8_t serial_number_str;
1583 uint8_t asset_tag_number_str;
1584 uint8_t boot_up_state;
1585 uint8_t power_supply_state;
1586 uint8_t thermal_state;
1587 uint8_t security_status;
1588 uint32_t oem_defined;
1589 uint8_t height;
1590 uint8_t number_of_power_cords;
1591 uint8_t contained_element_count;
1592 // contained elements follow
1593 } __attribute__((__packed__));
1594
1595 /* SMBIOS type 4 - Processor Information (v2.0) */
1596 struct smbios_type_4 {
1597 struct smbios_structure_header header;
1598 uint8_t socket_designation_str;
1599 uint8_t processor_type;
1600 uint8_t processor_family;
1601 uint8_t processor_manufacturer_str;
1602 uint32_t processor_id[2];
1603 uint8_t processor_version_str;
1604 uint8_t voltage;
1605 uint16_t external_clock;
1606 uint16_t max_speed;
1607 uint16_t current_speed;
1608 uint8_t status;
1609 uint8_t processor_upgrade;
1610 uint16_t l1_cache_handle;
1611 uint16_t l2_cache_handle;
1612 uint16_t l3_cache_handle;
1613 } __attribute__((__packed__));
1614
1615 /* SMBIOS type 16 - Physical Memory Array
1616 * Associated with one type 17 (Memory Device).
1617 */
1618 struct smbios_type_16 {
1619 struct smbios_structure_header header;
1620 uint8_t location;
1621 uint8_t use;
1622 uint8_t error_correction;
1623 uint32_t maximum_capacity;
1624 uint16_t memory_error_information_handle;
1625 uint16_t number_of_memory_devices;
1626 } __attribute__((__packed__));
1627
1628 /* SMBIOS type 17 - Memory Device
1629 * Associated with one type 19
1630 */
1631 struct smbios_type_17 {
1632 struct smbios_structure_header header;
1633 uint16_t physical_memory_array_handle;
1634 uint16_t memory_error_information_handle;
1635 uint16_t total_width;
1636 uint16_t data_width;
1637 uint16_t size;
1638 uint8_t form_factor;
1639 uint8_t device_set;
1640 uint8_t device_locator_str;
1641 uint8_t bank_locator_str;
1642 uint8_t memory_type;
1643 uint16_t type_detail;
1644 } __attribute__((__packed__));
1645
1646 /* SMBIOS type 19 - Memory Array Mapped Address */
1647 struct smbios_type_19 {
1648 struct smbios_structure_header header;
1649 uint32_t starting_address;
1650 uint32_t ending_address;
1651 uint16_t memory_array_handle;
1652 uint8_t partition_width;
1653 } __attribute__((__packed__));
1654
1655 /* SMBIOS type 20 - Memory Device Mapped Address */
1656 struct smbios_type_20 {
1657 struct smbios_structure_header header;
1658 uint32_t starting_address;
1659 uint32_t ending_address;
1660 uint16_t memory_device_handle;
1661 uint16_t memory_array_mapped_address_handle;
1662 uint8_t partition_row_position;
1663 uint8_t interleave_position;
1664 uint8_t interleaved_data_depth;
1665 } __attribute__((__packed__));
1666
1667 /* SMBIOS type 32 - System Boot Information */
1668 struct smbios_type_32 {
1669 struct smbios_structure_header header;
1670 uint8_t reserved[6];
1671 uint8_t boot_status;
1672 } __attribute__((__packed__));
1673
1674 /* SMBIOS type 127 -- End-of-table */
1675 struct smbios_type_127 {
1676 struct smbios_structure_header header;
1677 } __attribute__((__packed__));
1678
1679 static void
1680 smbios_entry_point_init(void *start,
1681 uint16_t max_structure_size,
1682 uint16_t structure_table_length,
1683 uint32_t structure_table_address,
1684 uint16_t number_of_structures)
1685 {
1686 uint8_t sum;
1687 int i;
1688 struct smbios_entry_point *ep = (struct smbios_entry_point *)start;
1689
1690 memcpy(ep->anchor_string, "_SM_", 4);
1691 ep->length = 0x1f;
1692 ep->smbios_major_version = 2;
1693 ep->smbios_minor_version = 4;
1694 ep->max_structure_size = max_structure_size;
1695 ep->entry_point_revision = 0;
1696 memset(ep->formatted_area, 0, 5);
1697 memcpy(ep->intermediate_anchor_string, "_DMI_", 5);
1698
1699 ep->structure_table_length = structure_table_length;
1700 ep->structure_table_address = structure_table_address;
1701 ep->number_of_structures = number_of_structures;
1702 ep->smbios_bcd_revision = 0x24;
1703
1704 ep->checksum = 0;
1705 ep->intermediate_checksum = 0;
1706
1707 sum = 0;
1708 for (i = 0; i < 0x10; i++)
1709 sum += ((int8_t *)start)[i];
1710 ep->checksum = -sum;
1711
1712 sum = 0;
1713 for (i = 0x10; i < ep->length; i++)
1714 sum += ((int8_t *)start)[i];
1715 ep->intermediate_checksum = -sum;
1716 }
1717
1718 /* Type 0 -- BIOS Information */
1719 #define RELEASE_DATE_STR "01/01/2007"
1720 static void *
1721 smbios_type_0_init(void *start)
1722 {
1723 struct smbios_type_0 *p = (struct smbios_type_0 *)start;
1724
1725 p->header.type = 0;
1726 p->header.length = sizeof(struct smbios_type_0);
1727 p->header.handle = 0;
1728
1729 p->vendor_str = 1;
1730 p->bios_version_str = 1;
1731 p->bios_starting_address_segment = 0xe800;
1732 p->bios_release_date_str = 2;
1733 p->bios_rom_size = 0; /* FIXME */
1734
1735 memset(p->bios_characteristics, 0, 8);
1736 p->bios_characteristics[0] = 0x08; /* BIOS characteristics not supported */
1737 p->bios_characteristics_extension_bytes[0] = 0;
1738 p->bios_characteristics_extension_bytes[1] = 0;
1739
1740 p->system_bios_major_release = 1;
1741 p->system_bios_minor_release = 0;
1742 p->embedded_controller_major_release = 0xff;
1743 p->embedded_controller_minor_release = 0xff;
1744
1745 start += sizeof(struct smbios_type_0);
1746 memcpy((char *)start, BX_APPNAME, sizeof(BX_APPNAME));
1747 start += sizeof(BX_APPNAME);
1748 memcpy((char *)start, RELEASE_DATE_STR, sizeof(RELEASE_DATE_STR));
1749 start += sizeof(RELEASE_DATE_STR);
1750 *((uint8_t *)start) = 0;
1751
1752 return start+1;
1753 }
1754
1755 /* Type 1 -- System Information */
1756 static void *
1757 smbios_type_1_init(void *start)
1758 {
1759 struct smbios_type_1 *p = (struct smbios_type_1 *)start;
1760 p->header.type = 1;
1761 p->header.length = sizeof(struct smbios_type_1);
1762 p->header.handle = 0x100;
1763
1764 p->manufacturer_str = 0;
1765 p->product_name_str = 0;
1766 p->version_str = 0;
1767 p->serial_number_str = 0;
1768
1769 memcpy(p->uuid, bios_uuid, 16);
1770
1771 p->wake_up_type = 0x06; /* power switch */
1772 p->sku_number_str = 0;
1773 p->family_str = 0;
1774
1775 start += sizeof(struct smbios_type_1);
1776 *((uint16_t *)start) = 0;
1777
1778 return start+2;
1779 }
1780
1781 /* Type 3 -- System Enclosure */
1782 static void *
1783 smbios_type_3_init(void *start)
1784 {
1785 struct smbios_type_3 *p = (struct smbios_type_3 *)start;
1786
1787 p->header.type = 3;
1788 p->header.length = sizeof(struct smbios_type_3);
1789 p->header.handle = 0x300;
1790
1791 p->manufacturer_str = 0;
1792 p->type = 0x01; /* other */
1793 p->version_str = 0;
1794 p->serial_number_str = 0;
1795 p->asset_tag_number_str = 0;
1796 p->boot_up_state = 0x03; /* safe */
1797 p->power_supply_state = 0x03; /* safe */
1798 p->thermal_state = 0x03; /* safe */
1799 p->security_status = 0x02; /* unknown */
1800 p->oem_defined = 0;
1801 p->height = 0;
1802 p->number_of_power_cords = 0;
1803 p->contained_element_count = 0;
1804
1805 start += sizeof(struct smbios_type_3);
1806 *((uint16_t *)start) = 0;
1807
1808 return start+2;
1809 }
1810
1811 /* Type 4 -- Processor Information */
1812 static void *
1813 smbios_type_4_init(void *start, unsigned int cpu_number)
1814 {
1815 struct smbios_type_4 *p = (struct smbios_type_4 *)start;
1816
1817 p->header.type = 4;
1818 p->header.length = sizeof(struct smbios_type_4);
1819 p->header.handle = 0x400 + cpu_number;
1820
1821 p->socket_designation_str = 1;
1822 p->processor_type = 0x03; /* CPU */
1823 p->processor_family = 0x01; /* other */
1824 p->processor_manufacturer_str = 0;
1825
1826 p->processor_id[0] = cpuid_signature;
1827 p->processor_id[1] = cpuid_features;
1828
1829 p->processor_version_str = 0;
1830 p->voltage = 0;
1831 p->external_clock = 0;
1832
1833 p->max_speed = 0; /* unknown */
1834 p->current_speed = 0; /* unknown */
1835
1836 p->status = 0x41; /* socket populated, CPU enabled */
1837 p->processor_upgrade = 0x01; /* other */
1838
1839 p->l1_cache_handle = 0xffff; /* cache information structure not provided */
1840 p->l2_cache_handle = 0xffff;
1841 p->l3_cache_handle = 0xffff;
1842
1843 start += sizeof(struct smbios_type_4);
1844
1845 memcpy((char *)start, "CPU " "\0" "" "\0" "", 7);
1846 ((char *)start)[4] = cpu_number + '0';
1847
1848 return start+7;
1849 }
1850
1851 /* Type 16 -- Physical Memory Array */
1852 static void *
1853 smbios_type_16_init(void *start, uint32_t memsize)
1854 {
1855 struct smbios_type_16 *p = (struct smbios_type_16*)start;
1856
1857 p->header.type = 16;
1858 p->header.length = sizeof(struct smbios_type_16);
1859 p->header.handle = 0x1000;
1860
1861 p->location = 0x01; /* other */
1862 p->use = 0x03; /* system memory */
1863 p->error_correction = 0x01; /* other */
1864 p->maximum_capacity = memsize * 1024;
1865 p->memory_error_information_handle = 0xfffe; /* none provided */
1866 p->number_of_memory_devices = 1;
1867
1868 start += sizeof(struct smbios_type_16);
1869 *((uint16_t *)start) = 0;
1870
1871 return start + 2;
1872 }
1873
1874 /* Type 17 -- Memory Device */
1875 static void *
1876 smbios_type_17_init(void *start, uint32_t memory_size_mb)
1877 {
1878 struct smbios_type_17 *p = (struct smbios_type_17 *)start;
1879
1880 p->header.type = 17;
1881 p->header.length = sizeof(struct smbios_type_17);
1882 p->header.handle = 0x1100;
1883
1884 p->physical_memory_array_handle = 0x1000;
1885 p->total_width = 64;
1886 p->data_width = 64;
1887 /* truncate memory_size_mb to 16 bits and clear most significant
1888 bit [indicates size in MB] */
1889 p->size = (uint16_t) memory_size_mb & 0x7fff;
1890 p->form_factor = 0x09; /* DIMM */
1891 p->device_set = 0;
1892 p->device_locator_str = 1;
1893 p->bank_locator_str = 0;
1894 p->memory_type = 0x07; /* RAM */
1895 p->type_detail = 0;
1896
1897 start += sizeof(struct smbios_type_17);
1898 memcpy((char *)start, "DIMM 1", 7);
1899 start += 7;
1900 *((uint8_t *)start) = 0;
1901
1902 return start+1;
1903 }
1904
1905 /* Type 19 -- Memory Array Mapped Address */
1906 static void *
1907 smbios_type_19_init(void *start, uint32_t memory_size_mb)
1908 {
1909 struct smbios_type_19 *p = (struct smbios_type_19 *)start;
1910
1911 p->header.type = 19;
1912 p->header.length = sizeof(struct smbios_type_19);
1913 p->header.handle = 0x1300;
1914
1915 p->starting_address = 0;
1916 p->ending_address = (memory_size_mb-1) * 1024;
1917 p->memory_array_handle = 0x1000;
1918 p->partition_width = 1;
1919
1920 start += sizeof(struct smbios_type_19);
1921 *((uint16_t *)start) = 0;
1922
1923 return start + 2;
1924 }
1925
1926 /* Type 20 -- Memory Device Mapped Address */
1927 static void *
1928 smbios_type_20_init(void *start, uint32_t memory_size_mb)
1929 {
1930 struct smbios_type_20 *p = (struct smbios_type_20 *)start;
1931
1932 p->header.type = 20;
1933 p->header.length = sizeof(struct smbios_type_20);
1934 p->header.handle = 0x1400;
1935
1936 p->starting_address = 0;
1937 p->ending_address = (memory_size_mb-1)*1024;
1938 p->memory_device_handle = 0x1100;
1939 p->memory_array_mapped_address_handle = 0x1300;
1940 p->partition_row_position = 1;
1941 p->interleave_position = 0;
1942 p->interleaved_data_depth = 0;
1943
1944 start += sizeof(struct smbios_type_20);
1945
1946 *((uint16_t *)start) = 0;
1947 return start+2;
1948 }
1949
1950 /* Type 32 -- System Boot Information */
1951 static void *
1952 smbios_type_32_init(void *start)
1953 {
1954 struct smbios_type_32 *p = (struct smbios_type_32 *)start;
1955
1956 p->header.type = 32;
1957 p->header.length = sizeof(struct smbios_type_32);
1958 p->header.handle = 0x2000;
1959 memset(p->reserved, 0, 6);
1960 p->boot_status = 0; /* no errors detected */
1961
1962 start += sizeof(struct smbios_type_32);
1963 *((uint16_t *)start) = 0;
1964
1965 return start+2;
1966 }
1967
1968 /* Type 127 -- End of Table */
1969 static void *
1970 smbios_type_127_init(void *start)
1971 {
1972 struct smbios_type_127 *p = (struct smbios_type_127 *)start;
1973
1974 p->header.type = 127;
1975 p->header.length = sizeof(struct smbios_type_127);
1976 p->header.handle = 0x7f00;
1977
1978 start += sizeof(struct smbios_type_127);
1979 *((uint16_t *)start) = 0;
1980
1981 return start + 2;
1982 }
1983
1984 void smbios_init(void)
1985 {
1986 unsigned cpu_num, nr_structs = 0, max_struct_size = 0;
1987 char *start, *p, *q;
1988 int memsize = ram_size / (1024 * 1024);
1989
1990 #ifdef BX_USE_EBDA_TABLES
1991 ebda_cur_addr = align(ebda_cur_addr, 16);
1992 start = (void *)(ebda_cur_addr);
1993 #else
1994 bios_table_cur_addr = align(bios_table_cur_addr, 16);
1995 start = (void *)(bios_table_cur_addr);
1996 #endif
1997
1998 p = (char *)start + sizeof(struct smbios_entry_point);
1999
2000 #define add_struct(fn) { \
2001 q = (fn); \
2002 nr_structs++; \
2003 if ((q - p) > max_struct_size) \
2004 max_struct_size = q - p; \
2005 p = q; \
2006 }
2007
2008 add_struct(smbios_type_0_init(p));
2009 add_struct(smbios_type_1_init(p));
2010 add_struct(smbios_type_3_init(p));
2011 for (cpu_num = 1; cpu_num <= smp_cpus; cpu_num++)
2012 add_struct(smbios_type_4_init(p, cpu_num));
2013 add_struct(smbios_type_16_init(p, memsize));
2014 add_struct(smbios_type_17_init(p, memsize));
2015 add_struct(smbios_type_19_init(p, memsize));
2016 add_struct(smbios_type_20_init(p, memsize));
2017 add_struct(smbios_type_32_init(p));
2018 add_struct(smbios_type_127_init(p));
2019
2020 #undef add_struct
2021
2022 smbios_entry_point_init(
2023 start, max_struct_size,
2024 (p - (char *)start) - sizeof(struct smbios_entry_point),
2025 (uint32_t)(start + sizeof(struct smbios_entry_point)),
2026 nr_structs);
2027
2028 #ifdef BX_USE_EBDA_TABLES
2029 ebda_cur_addr += (p - (char *)start);
2030 #else
2031 bios_table_cur_addr += (p - (char *)start);
2032 #endif
2033
2034 BX_INFO("SMBIOS table addr=0x%08lx\n", (unsigned long)start);
2035 }
2036
2037 static uint32_t find_resume_vector(void)
2038 {
2039 unsigned long addr, start, end;
2040
2041 #ifdef BX_USE_EBDA_TABLES
2042 start = align(ebda_cur_addr, 16);
2043 end = 0xa000 << 4;
2044 #else
2045 if (bios_table_cur_addr == 0)
2046 return 0;
2047 start = align(bios_table_cur_addr, 16);
2048 end = bios_table_end_addr;
2049 #endif
2050
2051 for (addr = start; addr < end; addr += 16) {
2052 if (!memcmp((void*)addr, "RSD PTR ", 8)) {
2053 struct rsdp_descriptor *rsdp = (void*)addr;
2054 struct rsdt_descriptor_rev1 *rsdt = (void*)rsdp->rsdt_physical_address;
2055 struct fadt_descriptor_rev1 *fadt = (void*)rsdt->table_offset_entry[0];
2056 struct facs_descriptor_rev1 *facs = (void*)fadt->firmware_ctrl;
2057 return facs->firmware_waking_vector;
2058 }
2059 }
2060
2061 return 0;
2062 }
2063
2064 static void find_440fx(PCIDevice *d)
2065 {
2066 uint16_t vendor_id, device_id;
2067
2068 vendor_id = pci_config_readw(d, PCI_VENDOR_ID);
2069 device_id = pci_config_readw(d, PCI_DEVICE_ID);
2070
2071 if (vendor_id == PCI_VENDOR_ID_INTEL && device_id == PCI_DEVICE_ID_INTEL_82441)
2072 i440_pcidev = *d;
2073 }
2074
2075 static void reinit_piix4_pm(PCIDevice *d)
2076 {
2077 uint16_t vendor_id, device_id;
2078
2079 vendor_id = pci_config_readw(d, PCI_VENDOR_ID);
2080 device_id = pci_config_readw(d, PCI_DEVICE_ID);
2081
2082 if (vendor_id == PCI_VENDOR_ID_INTEL && device_id == PCI_DEVICE_ID_INTEL_82371AB_3)
2083 piix4_pm_enable(d);
2084 }
2085
2086 void rombios32_init(uint32_t *s3_resume_vector, uint8_t *shutdown_flag)
2087 {
2088 BX_INFO("Starting rombios32\n");
2089 BX_INFO("Shutdown flag %x\n", *shutdown_flag);
2090
2091 #ifdef BX_QEMU
2092 qemu_cfg_port = qemu_cfg_port_probe();
2093 #endif
2094
2095 ram_probe();
2096
2097 cpu_probe();
2098
2099 smp_probe();
2100
2101 find_bios_table_area();
2102
2103 if (*shutdown_flag == 0xfe) {
2104 /* redirect bios read access to RAM */
2105 pci_for_each_device(find_440fx);
2106 bios_lock_shadow_ram(); /* bios is already copied */
2107 *s3_resume_vector = find_resume_vector();
2108 if (!*s3_resume_vector) {
2109 BX_INFO("This is S3 resume but wakeup vector is NULL\n");
2110 } else {
2111 BX_INFO("S3 resume vector %p\n", *s3_resume_vector);
2112 pci_for_each_device(reinit_piix4_pm);
2113 }
2114 return;
2115 }
2116
2117 pci_bios_init();
2118
2119 if (bios_table_cur_addr != 0) {
2120
2121 mptable_init();
2122
2123 uuid_probe();
2124
2125 smbios_init();
2126
2127 if (acpi_enabled)
2128 acpi_bios_init();
2129
2130 bios_lock_shadow_ram();
2131
2132 BX_INFO("bios_table_cur_addr: 0x%08lx\n", bios_table_cur_addr);
2133 if (bios_table_cur_addr > bios_table_end_addr)
2134 BX_PANIC("bios_table_end_addr overflow!\n");
2135 #ifdef BX_USE_EBDA_TABLES
2136 BX_INFO("ebda_cur_addr: 0x%08lx\n", ebda_cur_addr);
2137 if (ebda_cur_addr > 0xA0000)
2138 BX_PANIC("ebda_cur_addr overflow!\n");
2139 #endif
2140 }
2141 }
Mirror of Bochs CVS