cpu/exception.cc

   1 /////////////////////////////////////////////////////////////////////////
   2 // $Id: exception.cc,v 1.123 2008/11/09 22:08:21 sshwarts Exp $
   3 /////////////////////////////////////////////////////////////////////////
   4 //
   5 //  Copyright (C) 2001  MandrakeSoft S.A.
   6 //
   7 //    MandrakeSoft S.A.
   8 //    43, rue d'Aboukir
   9 //    75002 Paris - France
  10 //    http://www.linux-mandrake.com/
  11 //    http://www.mandrakesoft.com/
  12 //
  13 //  This library is free software; you can redistribute it and/or
  14 //  modify it under the terms of the GNU Lesser General Public
  15 //  License as published by the Free Software Foundation; either
  16 //  version 2 of the License, or (at your option) any later version.
  17 //
  18 //  This library is distributed in the hope that it will be useful,
  19 //  but WITHOUT ANY WARRANTY; without even the implied warranty of
  20 //  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  21 //  Lesser General Public License for more details.
  22 //
  23 //  You should have received a copy of the GNU Lesser General Public
  24 //  License along with this library; if not, write to the Free Software
  25 //  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  26 //
  27 /////////////////////////////////////////////////////////////////////////
  28
  29 #define NEED_CPU_REG_SHORTCUTS 1
  30 #include "bochs.h"
  31 #include "cpu.h"
  32 #define LOG_THIS BX_CPU_THIS_PTR
  33
  34 #include "iodev/iodev.h"
  35
  36 #if BX_SUPPORT_X86_64==0
  37 // Make life easier merging cpu64 & cpu code.
  38 #define RIP EIP
  39 #define RSP ESP
  40 #endif
  41
  42 /* Exception classes.  These are used as indexes into the 'is_exception_OK'
  43  * array below, and are stored in the 'exception' array also
  44  */
  45 #define BX_ET_BENIGN       0
  46 #define BX_ET_CONTRIBUTORY 1
  47 #define BX_ET_PAGE_FAULT   2
  48
  49 #define BX_ET_DOUBLE_FAULT 10
  50
  51 static const bx_bool is_exception_OK[3][3] = {
  52     { 1, 1, 1 }, /* 1st exception is BENIGN */
  53     { 1, 0, 1 }, /* 1st exception is CONTRIBUTORY */
  54     { 1, 0, 0 }  /* 1st exception is PAGE_FAULT */
  55 };
  56
  57 #define BX_EXCEPTION_CLASS_TRAP  0
  58 #define BX_EXCEPTION_CLASS_FAULT 1
  59 #define BX_EXCEPTION_CLASS_ABORT 2
  60
  61 #if BX_SUPPORT_X86_64
  62 void BX_CPU_C::long_mode_int(Bit8u vector, bx_bool is_INT, bx_bool is_error_code, Bit16u error_code)
  63 {
  64   // long mode interrupt
  65   Bit64u desctmp1, desctmp2;
  66
  67   bx_descriptor_t gate_descriptor, cs_descriptor;
  68   bx_selector_t cs_selector;
  69
  70   // interrupt vector must be within IDT table limits,
  71   // else #GP(vector number*16 + 2 + EXT)
  72   if ((vector*16 + 15) > BX_CPU_THIS_PTR idtr.limit) {
  73     BX_ERROR(("interrupt(long mode): vector must be within IDT table limits, IDT.limit = 0x%x", BX_CPU_THIS_PTR idtr.limit));
  74     exception(BX_GP_EXCEPTION, vector*16 + 2, 0);
  75   }
  76
  77   desctmp1 = system_read_qword(BX_CPU_THIS_PTR idtr.base + vector*16);
  78   desctmp2 = system_read_qword(BX_CPU_THIS_PTR idtr.base + vector*16 + 8);
  79
  80   if (desctmp2 & BX_CONST64(0x00001F0000000000)) {
  81     BX_ERROR(("interrupt(long mode): IDT entry extended attributes DWORD4 TYPE != 0"));
  82     exception(BX_GP_EXCEPTION, vector*16 + 2, 0);
  83   }
  84
  85   Bit32u dword1 = GET32L(desctmp1);
  86   Bit32u dword2 = GET32H(desctmp1);
  87   Bit32u dword3 = GET32L(desctmp2);
  88
  89   parse_descriptor(dword1, dword2, &gate_descriptor);
  90
  91   if ((gate_descriptor.valid==0) || gate_descriptor.segment)
  92   {
  93     BX_ERROR(("interrupt(long mode): gate descriptor is not valid sys seg"));
  94     exception(BX_GP_EXCEPTION, vector*16 + 2, 0);
  95   }
  96
  97   // descriptor AR byte must indicate interrupt gate, trap gate,
  98   // or task gate, else #GP(vector*16 + 2 + EXT)
  99   if (gate_descriptor.type != BX_386_INTERRUPT_GATE &&
 100       gate_descriptor.type != BX_386_TRAP_GATE)
 101   {
 102     BX_ERROR(("interrupt(long mode): unsupported gate type %u",
 103         (unsigned) gate_descriptor.type));
 104     exception(BX_GP_EXCEPTION, vector*16 + 2, 0);
 105   }
 106
 107   // if software interrupt, then gate descripor DPL must be >= CPL,
 108   // else #GP(vector * 16 + 2 + EXT)
 109   if (is_INT && (gate_descriptor.dpl < CPL))
 110   {
 111     BX_ERROR(("interrupt(long mode): is_INT && (dpl < CPL)"));
 112     exception(BX_GP_EXCEPTION, vector*16 + 2, 0);
 113   }
 114
 115   // Gate must be present, else #NP(vector * 16 + 2 + EXT)
 116   if (! IS_PRESENT(gate_descriptor)) {
 117     BX_ERROR(("interrupt(long mode): p == 0"));
 118     exception(BX_NP_EXCEPTION, vector*16 + 2, 0);
 119   }
 120
 121   Bit16u gate_dest_selector = gate_descriptor.u.gate.dest_selector;
 122   Bit64u gate_dest_offset   = ((Bit64u)dword3 << 32) |
 123                        gate_descriptor.u.gate.dest_offset;
 124
 125   unsigned ist = gate_descriptor.u.gate.param_count & 0x7;
 126
 127   // examine CS selector and descriptor given in gate descriptor
 128   // selector must be non-null else #GP(EXT)
 129   if ((gate_dest_selector & 0xfffc) == 0) {
 130     BX_ERROR(("int_trap_gate(long mode): selector null"));
 131     exception(BX_GP_EXCEPTION, 0, 0);
 132   }
 133
 134   parse_selector(gate_dest_selector, &cs_selector);
 135
 136   // selector must be within its descriptor table limits
 137   // else #GP(selector+EXT)
 138   fetch_raw_descriptor(&cs_selector, &dword1, &dword2, BX_GP_EXCEPTION);
 139   parse_descriptor(dword1, dword2, &cs_descriptor);
 140
 141   // descriptor AR byte must indicate code seg
 142   // and code segment descriptor DPL<=CPL, else #GP(selector+EXT)
 143   if (cs_descriptor.valid==0 || cs_descriptor.segment==0 ||
 144       IS_DATA_SEGMENT(cs_descriptor.type) ||
 145       cs_descriptor.dpl>CPL)
 146   {
 147     BX_ERROR(("interrupt(long mode): not accessable or not code segment"));
 148     exception(BX_GP_EXCEPTION, cs_selector.value & 0xfffc, 0);
 149   }
 150
 151   // check that it's a 64 bit segment
 152   if (! IS_LONG64_SEGMENT(cs_descriptor) || cs_descriptor.u.segment.d_b)
 153   {
 154     BX_ERROR(("interrupt(long mode): must be 64 bit segment"));
 155     exception(BX_GP_EXCEPTION, cs_selector.value & 0xfffc, 0);
 156   }
 157
 158   // segment must be present, else #NP(selector + EXT)
 159   if (! IS_PRESENT(cs_descriptor)) {
 160     BX_ERROR(("interrupt(long mode): segment not present"));
 161     exception(BX_NP_EXCEPTION, cs_selector.value & 0xfffc, 0);
 162   }
 163
 164   // if code segment is non-conforming and DPL < CPL then
 165   // INTERRUPT TO INNER PRIVILEGE:
 166   if (IS_CODE_SEGMENT_NON_CONFORMING(cs_descriptor.type) && cs_descriptor.dpl<CPL)
 167   {
 168     Bit64u RSP_for_cpl_x;
 169
 170     BX_DEBUG(("interrupt(long mode): INTERRUPT TO INNER PRIVILEGE"));
 171
 172     // check selector and descriptor for new stack in current TSS
 173     if (ist != 0) {
 174       BX_DEBUG(("interrupt(long mode): trap to IST, vector = %d", ist));
 175       RSP_for_cpl_x = get_RSP_from_TSS(ist+3);
 176     }
 177     else {
 178       RSP_for_cpl_x = get_RSP_from_TSS(cs_descriptor.dpl);
 179     }
 180
 181     RSP_for_cpl_x &= BX_CONST64(0xfffffffffffffff0);
 182
 183     Bit64u old_CS  = BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value;
 184     Bit64u old_RIP = RIP;
 185     Bit64u old_SS  = BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].selector.value;
 186     Bit64u old_RSP = RSP;
 187
 188     if (! IsCanonical(RSP_for_cpl_x)) {
 189       // #SS(selector) when changing priviledge level
 190       BX_ERROR(("interrupt(long mode): canonical address failure %08x%08x",
 191          GET32H(RSP_for_cpl_x), GET32L(RSP_for_cpl_x)));
 192       exception(BX_SS_EXCEPTION, old_SS & 0xfffc, 0);
 193     }
 194
 195     // push old stack long pointer onto new stack
 196     write_new_stack_qword_64(RSP_for_cpl_x -  8, cs_descriptor.dpl, old_SS);
 197     write_new_stack_qword_64(RSP_for_cpl_x - 16, cs_descriptor.dpl, old_RSP);
 198     write_new_stack_qword_64(RSP_for_cpl_x - 24, cs_descriptor.dpl, read_eflags());
 199     // push long pointer to return address onto new stack
 200     write_new_stack_qword_64(RSP_for_cpl_x - 32, cs_descriptor.dpl, old_CS);
 201     write_new_stack_qword_64(RSP_for_cpl_x - 40, cs_descriptor.dpl, old_RIP);
 202     RSP_for_cpl_x -= 40;
 203
 204     if (is_error_code) {
 205       RSP_for_cpl_x -= 8;
 206       write_new_stack_qword_64(RSP_for_cpl_x, cs_descriptor.dpl, error_code);
 207     }
 208
 209     bx_selector_t ss_selector;
 210     bx_descriptor_t ss_descriptor;
 211
 212     // set up a null descriptor
 213     parse_selector(0, &ss_selector);
 214     parse_descriptor(0, 0, &ss_descriptor);
 215
 216     // load CS:RIP (guaranteed to be in 64 bit mode)
 217     branch_far64(&cs_selector, &cs_descriptor, gate_dest_offset, cs_descriptor.dpl);
 218
 219     // set up null SS descriptor
 220     load_ss(&ss_selector, &ss_descriptor, cs_descriptor.dpl);
 221     RSP = RSP_for_cpl_x;
 222
 223     // if INTERRUPT GATE set IF to 0
 224     if (!(gate_descriptor.type & 1)) // even is int-gate
 225       BX_CPU_THIS_PTR clear_IF();
 226     BX_CPU_THIS_PTR clear_TF();
 227     BX_CPU_THIS_PTR clear_VM();
 228     BX_CPU_THIS_PTR clear_RF();
 229     BX_CPU_THIS_PTR clear_NT();
 230     return;
 231   }
 232
 233   // if code segment is conforming OR code segment DPL = CPL then
 234   // INTERRUPT TO SAME PRIVILEGE LEVEL:
 235   if (IS_CODE_SEGMENT_CONFORMING(cs_descriptor.type) || cs_descriptor.dpl==CPL)
 236   {
 237     BX_DEBUG(("interrupt(long mode): INTERRUPT TO SAME PRIVILEGE"));
 238
 239     Bit64u old_RSP = RSP;
 240
 241     // check selector and descriptor for new stack in current TSS
 242     if (ist > 0) {
 243       BX_DEBUG(("interrupt(long mode): trap to IST, vector = %d", ist));
 244       RSP = get_RSP_from_TSS(ist+3);
 245     }
 246
 247     // align stack
 248     RSP &= BX_CONST64(0xfffffffffffffff0);
 249
 250     // push flags onto stack
 251     // push current CS selector onto stack
 252     // push return offset onto stack
 253     write_new_stack_qword_64(RSP - 8,  cs_descriptor.dpl,
 254          BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].selector.value);
 255     write_new_stack_qword_64(RSP - 16, cs_descriptor.dpl, old_RSP);
 256     write_new_stack_qword_64(RSP - 24, cs_descriptor.dpl, read_eflags());
 257     write_new_stack_qword_64(RSP - 32, cs_descriptor.dpl,
 258          BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value);
 259     write_new_stack_qword_64(RSP - 40, cs_descriptor.dpl, RIP);
 260     RSP -= 40;
 261
 262     if (is_error_code) {
 263       RSP -= 8;
 264       write_new_stack_qword_64(RSP, cs_descriptor.dpl, error_code);
 265     }
 266
 267     // set the RPL field of CS to CPL
 268     branch_far64(&cs_selector, &cs_descriptor, gate_dest_offset, CPL);
 269
 270     // if interrupt gate then set IF to 0
 271     if (!(gate_descriptor.type & 1)) // even is int-gate
 272       BX_CPU_THIS_PTR clear_IF();
 273     BX_CPU_THIS_PTR clear_TF();
 274     BX_CPU_THIS_PTR clear_VM();
 275     BX_CPU_THIS_PTR clear_RF();
 276     BX_CPU_THIS_PTR clear_NT();
 277     return;
 278   }
 279
 280   // else #GP(CS selector + ext)
 281   BX_ERROR(("interrupt(long mode): bad descriptor type=%u, descriptor.dpl=%u, CPL=%u",
 282     (unsigned) cs_descriptor.type, (unsigned) cs_descriptor.dpl, (unsigned) CPL));
 283   BX_ERROR(("cs.segment = %u", (unsigned) cs_descriptor.segment));
 284   exception(BX_GP_EXCEPTION, cs_selector.value & 0xfffc, 0);
 285 }
 286 #endif
 287
 288 void BX_CPU_C::protected_mode_int(Bit8u vector, bx_bool is_INT, bx_bool is_error_code, Bit16u error_code)
 289 {
 290   // protected mode interrupt
 291   Bit32u dword1, dword2;
 292   bx_descriptor_t gate_descriptor, cs_descriptor;
 293   bx_selector_t cs_selector;
 294
 295   Bit16u raw_tss_selector;
 296   bx_selector_t   tss_selector;
 297   bx_descriptor_t tss_descriptor;
 298
 299   Bit16u gate_dest_selector;
 300   Bit32u gate_dest_offset;
 301
 302   // interrupt vector must be within IDT table limits,
 303   // else #GP(vector number*8 + 2 + EXT)
 304   if ((vector*8 + 7) > BX_CPU_THIS_PTR idtr.limit) {
 305     BX_DEBUG(("interrupt(): vector must be within IDT table limits, IDT.limit = 0x%x", BX_CPU_THIS_PTR idtr.limit));
 306     exception(BX_GP_EXCEPTION, vector*8 + 2, 0);
 307   }
 308
 309   Bit64u desctmp = system_read_qword(BX_CPU_THIS_PTR idtr.base + vector*8);
 310
 311   dword1 = GET32L(desctmp);
 312   dword2 = GET32H(desctmp);
 313
 314   parse_descriptor(dword1, dword2, &gate_descriptor);
 315
 316   if ((gate_descriptor.valid==0) || gate_descriptor.segment) {
 317     BX_DEBUG(("interrupt(): gate descriptor is not valid sys seg (vector=0x%02x)", vector));
 318     exception(BX_GP_EXCEPTION, vector*8 + 2, 0);
 319   }
 320
 321   // descriptor AR byte must indicate interrupt gate, trap gate,
 322   // or task gate, else #GP(vector*8 + 2 + EXT)
 323   switch (gate_descriptor.type) {
 324   case BX_TASK_GATE:
 325   case BX_286_INTERRUPT_GATE:
 326   case BX_286_TRAP_GATE:
 327   case BX_386_INTERRUPT_GATE:
 328   case BX_386_TRAP_GATE:
 329     break;
 330   default:
 331     BX_ERROR(("interrupt(): gate.type(%u) != {5,6,7,14,15}",
 332       (unsigned) gate_descriptor.type));
 333     exception(BX_GP_EXCEPTION, vector*8 + 2, 0);
 334   }
 335
 336   // if software interrupt, then gate descripor DPL must be >= CPL,
 337   // else #GP(vector * 8 + 2 + EXT)
 338   if (is_INT && (gate_descriptor.dpl < CPL)) {
 339     BX_DEBUG(("interrupt(): is_INT && (dpl < CPL)"));
 340     exception(BX_GP_EXCEPTION, vector*8 + 2, 0);
 341   }
 342
 343   // Gate must be present, else #NP(vector * 8 + 2 + EXT)
 344   if (! IS_PRESENT(gate_descriptor)) {
 345     BX_ERROR(("interrupt(): gate not present"));
 346     exception(BX_NP_EXCEPTION, vector*8 + 2, 0);
 347   }
 348
 349   switch (gate_descriptor.type) {
 350   case BX_TASK_GATE:
 351     // examine selector to TSS, given in task gate descriptor
 352     raw_tss_selector = gate_descriptor.u.taskgate.tss_selector;
 353     parse_selector(raw_tss_selector, &tss_selector);
 354
 355     // must specify global in the local/global bit,
 356     //      else #GP(TSS selector)
 357     if (tss_selector.ti) {
 358       BX_ERROR(("interrupt: tss_selector.ti=1 from gate descriptor - #GP(tss_selector)"));
 359       exception(BX_GP_EXCEPTION, raw_tss_selector & 0xfffc, 0);
 360     }
 361
 362     // index must be within GDT limits, else #TS(TSS selector)
 363     fetch_raw_descriptor(&tss_selector, &dword1, &dword2, BX_GP_EXCEPTION);
 364
 365     parse_descriptor(dword1, dword2, &tss_descriptor);
 366
 367     // AR byte must specify available TSS,
 368     //   else #GP(TSS selector)
 369     if (tss_descriptor.valid==0 || tss_descriptor.segment) {
 370       BX_ERROR(("exception: TSS selector points to invalid or bad TSS - #GP(tss_selector)"));
 371       exception(BX_GP_EXCEPTION, raw_tss_selector & 0xfffc, 0);
 372     }
 373
 374     if (tss_descriptor.type!=BX_SYS_SEGMENT_AVAIL_286_TSS &&
 375         tss_descriptor.type!=BX_SYS_SEGMENT_AVAIL_386_TSS)
 376     {
 377       BX_ERROR(("exception: TSS selector points to bad TSS - #GP(tss_selector)"));
 378       exception(BX_GP_EXCEPTION, raw_tss_selector & 0xfffc, 0);
 379     }
 380
 381     // TSS must be present, else #NP(TSS selector)
 382     if (! IS_PRESENT(tss_descriptor)) {
 383       BX_ERROR(("exception: TSS descriptor.p == 0"));
 384       exception(BX_NP_EXCEPTION, raw_tss_selector & 0xfffc, 0);
 385     }
 386
 387     // switch tasks with nesting to TSS
 388     task_switch(&tss_selector, &tss_descriptor,
 389                     BX_TASK_FROM_CALL_OR_INT, dword1, dword2);
 390
 391     // if interrupt was caused by fault with error code
 392     //   stack limits must allow push of 2 more bytes, else #SS(0)
 393     // push error code onto stack
 394
 395     if (is_error_code) {
 396       if (tss_descriptor.type >= 9) // TSS386
 397         push_32(error_code);
 398       else
 399         push_16(error_code);
 400     }
 401
 402     // instruction pointer must be in CS limit, else #GP(0)
 403     if (EIP > BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.limit_scaled) {
 404       BX_ERROR(("exception(): EIP > CS.limit"));
 405       exception(BX_GP_EXCEPTION, 0, 0);
 406     }
 407
 408     return;
 409
 410   case BX_286_INTERRUPT_GATE:
 411   case BX_286_TRAP_GATE:
 412   case BX_386_INTERRUPT_GATE:
 413   case BX_386_TRAP_GATE:
 414     gate_dest_selector = gate_descriptor.u.gate.dest_selector;
 415     gate_dest_offset   = gate_descriptor.u.gate.dest_offset;
 416
 417     // examine CS selector and descriptor given in gate descriptor
 418     // selector must be non-null else #GP(EXT)
 419     if ((gate_dest_selector & 0xfffc) == 0) {
 420       BX_ERROR(("int_trap_gate(): selector null"));
 421       exception(BX_GP_EXCEPTION, 0, 0);
 422     }
 423
 424     parse_selector(gate_dest_selector, &cs_selector);
 425
 426     // selector must be within its descriptor table limits
 427     // else #GP(selector+EXT)
 428     fetch_raw_descriptor(&cs_selector, &dword1, &dword2, BX_GP_EXCEPTION);
 429     parse_descriptor(dword1, dword2, &cs_descriptor);
 430
 431     // descriptor AR byte must indicate code seg
 432     // and code segment descriptor DPL<=CPL, else #GP(selector+EXT)
 433     if (cs_descriptor.valid==0 || cs_descriptor.segment==0 ||
 434         IS_DATA_SEGMENT(cs_descriptor.type) ||
 435         cs_descriptor.dpl>CPL)
 436     {
 437       BX_ERROR(("interrupt(): not accessable or not code segment cs=0x%04x", cs_selector.value));
 438       exception(BX_GP_EXCEPTION, cs_selector.value & 0xfffc, 0);
 439     }
 440
 441     // segment must be present, else #NP(selector + EXT)
 442     if (! IS_PRESENT(cs_descriptor)) {
 443       BX_ERROR(("interrupt(): segment not present"));
 444       exception(BX_NP_EXCEPTION, cs_selector.value & 0xfffc, 0);
 445     }
 446
 447     if (cs_descriptor.dpl > CPL) {
 448       BX_ERROR(("interrupt(): code segment DPL(%d) > CPL", cs_descriptor.dpl));
 449       exception(BX_GP_EXCEPTION, cs_selector.value & 0xfffc, 0);
 450     }
 451
 452     // if code segment is non-conforming and DPL < CPL then
 453     // INTERRUPT TO INNER PRIVILEGE
 454     if(IS_CODE_SEGMENT_NON_CONFORMING(cs_descriptor.type) && (cs_descriptor.dpl < CPL))
 455     {
 456       Bit16u old_SS, old_CS, SS_for_cpl_x;
 457       Bit32u ESP_for_cpl_x, old_EIP, old_ESP;
 458       bx_descriptor_t ss_descriptor;
 459       bx_selector_t   ss_selector;
 460       int is_v8086_mode = v8086_mode();
 461
 462       BX_DEBUG(("interrupt(): INTERRUPT TO INNER PRIVILEGE"));
 463
 464       if (is_v8086_mode && cs_descriptor.dpl != 0) {
 465         // if code segment DPL != 0 then #GP(new code segment selector)
 466         BX_ERROR(("interrupt(): code segment DPL(%d) != 0 in v8086 mode", cs_descriptor.dpl));
 467         exception(BX_GP_EXCEPTION, cs_selector.value & 0xfffc, 0);
 468       }
 469
 470       // check selector and descriptor for new stack in current TSS
 471       get_SS_ESP_from_TSS(cs_descriptor.dpl,
 472                               &SS_for_cpl_x, &ESP_for_cpl_x);
 473
 474       // Selector must be non-null else #TS(EXT)
 475       if ((SS_for_cpl_x & 0xfffc) == 0) {
 476         BX_ERROR(("interrupt(): SS selector null"));
 477         exception(BX_TS_EXCEPTION, 0, 0); /* TS(ext) */
 478       }
 479
 480       // selector index must be within its descriptor table limits
 481       // else #TS(SS selector + EXT)
 482       parse_selector(SS_for_cpl_x, &ss_selector);
 483       // fetch 2 dwords of descriptor; call handles out of limits checks
 484       fetch_raw_descriptor(&ss_selector, &dword1, &dword2, BX_TS_EXCEPTION);
 485       parse_descriptor(dword1, dword2, &ss_descriptor);
 486
 487       // selector rpl must = dpl of code segment,
 488       // else #TS(SS selector + ext)
 489       if (ss_selector.rpl != cs_descriptor.dpl) {
 490         BX_ERROR(("interrupt(): SS.rpl != CS.dpl"));
 491         exception(BX_TS_EXCEPTION, SS_for_cpl_x & 0xfffc, 0);
 492       }
 493
 494       // stack seg DPL must = DPL of code segment,
 495       // else #TS(SS selector + ext)
 496       if (ss_descriptor.dpl != cs_descriptor.dpl) {
 497         BX_ERROR(("interrupt(): SS.dpl != CS.dpl"));
 498         exception(BX_TS_EXCEPTION, SS_for_cpl_x & 0xfffc, 0);
 499       }
 500
 501       // descriptor must indicate writable data segment,
 502       // else #TS(SS selector + EXT)
 503       if (ss_descriptor.valid==0 || ss_descriptor.segment==0 ||
 504            IS_CODE_SEGMENT(ss_descriptor.type) ||
 505           !IS_DATA_SEGMENT_WRITEABLE(ss_descriptor.type))
 506       {
 507         BX_ERROR(("interrupt(): SS is not writable data segment"));
 508         exception(BX_TS_EXCEPTION, SS_for_cpl_x & 0xfffc, 0);
 509       }
 510
 511       // seg must be present, else #SS(SS selector + ext)
 512       if (! IS_PRESENT(ss_descriptor)) {
 513         BX_ERROR(("interrupt(): SS not present"));
 514         exception(BX_SS_EXCEPTION, SS_for_cpl_x & 0xfffc, 0);
 515       }
 516
 517       // IP must be within CS segment boundaries, else #GP(0)
 518       if (gate_dest_offset > cs_descriptor.u.segment.limit_scaled) {
 519         BX_DEBUG(("interrupt(): gate EIP > CS.limit"));
 520         exception(BX_GP_EXCEPTION, 0, 0);
 521       }
 522
 523       old_ESP = ESP;
 524       old_SS  = BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].selector.value;
 525       old_EIP = EIP;
 526       old_CS  = BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value;
 527
 528       // Prepare new stack segment
 529       bx_segment_reg_t new_stack;
 530       new_stack.selector = ss_selector;
 531       new_stack.cache = ss_descriptor;
 532       new_stack.selector.rpl = cs_descriptor.dpl;
 533       // add cpl to the selector value
 534       new_stack.selector.value = (0xfffc & new_stack.selector.value) |
 535         new_stack.selector.rpl;
 536
 537       if (ss_descriptor.u.segment.d_b) {
 538         Bit32u temp_ESP = ESP_for_cpl_x;
 539
 540         if (is_v8086_mode)
 541         {
 542           if (gate_descriptor.type>=14) { // 386 int/trap gate
 543             write_new_stack_dword_32(&new_stack, temp_ESP-4,  cs_descriptor.dpl,
 544                 BX_CPU_THIS_PTR sregs[BX_SEG_REG_GS].selector.value);
 545             write_new_stack_dword_32(&new_stack, temp_ESP-8,  cs_descriptor.dpl,
 546                 BX_CPU_THIS_PTR sregs[BX_SEG_REG_FS].selector.value);
 547             write_new_stack_dword_32(&new_stack, temp_ESP-12, cs_descriptor.dpl,
 548                 BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS].selector.value);
 549             write_new_stack_dword_32(&new_stack, temp_ESP-16, cs_descriptor.dpl,
 550                 BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES].selector.value);
 551             temp_ESP -= 16;
 552           }
 553           else {
 554             write_new_stack_word_32(&new_stack, temp_ESP-2, cs_descriptor.dpl,
 555                 BX_CPU_THIS_PTR sregs[BX_SEG_REG_GS].selector.value);
 556             write_new_stack_word_32(&new_stack, temp_ESP-4, cs_descriptor.dpl,
 557                 BX_CPU_THIS_PTR sregs[BX_SEG_REG_FS].selector.value);
 558             write_new_stack_word_32(&new_stack, temp_ESP-6, cs_descriptor.dpl,
 559                 BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS].selector.value);
 560             write_new_stack_word_32(&new_stack, temp_ESP-8, cs_descriptor.dpl,
 561                 BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES].selector.value);
 562             temp_ESP -= 8;
 563           }
 564         }
 565
 566         if (gate_descriptor.type>=14) { // 386 int/trap gate
 567           // push long pointer to old stack onto new stack
 568           write_new_stack_dword_32(&new_stack, temp_ESP-4,  cs_descriptor.dpl, old_SS);
 569           write_new_stack_dword_32(&new_stack, temp_ESP-8,  cs_descriptor.dpl, old_ESP);
 570           write_new_stack_dword_32(&new_stack, temp_ESP-12, cs_descriptor.dpl, read_eflags());
 571           write_new_stack_dword_32(&new_stack, temp_ESP-16, cs_descriptor.dpl, old_CS);
 572           write_new_stack_dword_32(&new_stack, temp_ESP-20, cs_descriptor.dpl, old_EIP);
 573           temp_ESP -= 20;
 574
 575           if (is_error_code) {
 576             temp_ESP -= 4;
 577             write_new_stack_dword_32(&new_stack, temp_ESP, cs_descriptor.dpl, error_code);
 578           }
 579         }
 580         else {                          // 286 int/trap gate
 581           // push long pointer to old stack onto new stack
 582           write_new_stack_word_32(&new_stack, temp_ESP-2,  cs_descriptor.dpl, old_SS);
 583           write_new_stack_word_32(&new_stack, temp_ESP-4,  cs_descriptor.dpl, (Bit16u) old_ESP);
 584           write_new_stack_word_32(&new_stack, temp_ESP-6,  cs_descriptor.dpl, (Bit16u) read_eflags());
 585           write_new_stack_word_32(&new_stack, temp_ESP-8,  cs_descriptor.dpl, old_CS);
 586           write_new_stack_word_32(&new_stack, temp_ESP-10, cs_descriptor.dpl, (Bit16u) old_EIP);
 587           temp_ESP -= 10;
 588
 589           if (is_error_code) {
 590             temp_ESP -= 2;
 591             write_new_stack_word_32(&new_stack, temp_ESP, cs_descriptor.dpl, error_code);
 592           }
 593         }
 594
 595         ESP = temp_ESP;
 596       }
 597       else {
 598         Bit16u temp_SP = (Bit16u) ESP_for_cpl_x;
 599
 600         if (is_v8086_mode)
 601         {
 602           if (gate_descriptor.type>=14) { // 386 int/trap gate
 603             write_new_stack_dword_32(&new_stack, (Bit16u)(temp_SP-4),  cs_descriptor.dpl,
 604                 BX_CPU_THIS_PTR sregs[BX_SEG_REG_GS].selector.value);
 605             write_new_stack_dword_32(&new_stack, (Bit16u)(temp_SP-8),  cs_descriptor.dpl,
 606                 BX_CPU_THIS_PTR sregs[BX_SEG_REG_FS].selector.value);
 607             write_new_stack_dword_32(&new_stack, (Bit16u)(temp_SP-12), cs_descriptor.dpl,
 608                 BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS].selector.value);
 609             write_new_stack_dword_32(&new_stack, (Bit16u)(temp_SP-16), cs_descriptor.dpl,
 610                 BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES].selector.value);
 611             temp_SP -= 16;
 612           }
 613           else {
 614             write_new_stack_word_32(&new_stack, (Bit16u)(temp_SP-2), cs_descriptor.dpl,
 615                 BX_CPU_THIS_PTR sregs[BX_SEG_REG_GS].selector.value);
 616             write_new_stack_word_32(&new_stack, (Bit16u)(temp_SP-4), cs_descriptor.dpl,
 617                 BX_CPU_THIS_PTR sregs[BX_SEG_REG_FS].selector.value);
 618             write_new_stack_word_32(&new_stack, (Bit16u)(temp_SP-6), cs_descriptor.dpl,
 619                 BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS].selector.value);
 620             write_new_stack_word_32(&new_stack, (Bit16u)(temp_SP-8), cs_descriptor.dpl,
 621                 BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES].selector.value);
 622             temp_SP -= 8;
 623           }
 624         }
 625
 626         if (gate_descriptor.type>=14) { // 386 int/trap gate
 627           // push long pointer to old stack onto new stack
 628           write_new_stack_dword_32(&new_stack, (Bit16u)(temp_SP-4),  cs_descriptor.dpl, old_SS);
 629           write_new_stack_dword_32(&new_stack, (Bit16u)(temp_SP-8),  cs_descriptor.dpl, old_ESP);
 630           write_new_stack_dword_32(&new_stack, (Bit16u)(temp_SP-12), cs_descriptor.dpl, read_eflags());
 631           write_new_stack_dword_32(&new_stack, (Bit16u)(temp_SP-16), cs_descriptor.dpl, old_CS);
 632           write_new_stack_dword_32(&new_stack, (Bit16u)(temp_SP-20), cs_descriptor.dpl, old_EIP);
 633           temp_SP -= 20;
 634
 635           if (is_error_code) {
 636             temp_SP -= 4;
 637             write_new_stack_dword_32(&new_stack, temp_SP, cs_descriptor.dpl, error_code);
 638           }
 639         }
 640         else {                          // 286 int/trap gate
 641           // push long pointer to old stack onto new stack
 642           write_new_stack_word_32(&new_stack, (Bit16u)(temp_SP-2),  cs_descriptor.dpl, old_SS);
 643           write_new_stack_word_32(&new_stack, (Bit16u)(temp_SP-4),  cs_descriptor.dpl, (Bit16u) old_ESP);
 644           write_new_stack_word_32(&new_stack, (Bit16u)(temp_SP-6),  cs_descriptor.dpl, (Bit16u) read_eflags());
 645           write_new_stack_word_32(&new_stack, (Bit16u)(temp_SP-8),  cs_descriptor.dpl, old_CS);
 646           write_new_stack_word_32(&new_stack, (Bit16u)(temp_SP-10), cs_descriptor.dpl, (Bit16u) old_EIP);
 647           temp_SP -= 10;
 648
 649           if (is_error_code) {
 650             temp_SP -= 2;
 651             write_new_stack_word_32(&new_stack, temp_SP, cs_descriptor.dpl, error_code);
 652           }
 653         }
 654
 655         SP = temp_SP;
 656       }
 657
 658       // load new SS:eSP values from TSS
 659       load_ss(&ss_selector, &ss_descriptor, cs_descriptor.dpl);
 660
 661       // load new CS:eIP values from gate
 662       // set CPL to new code segment DPL
 663       // set RPL of CS to CPL
 664       load_cs(&cs_selector, &cs_descriptor, cs_descriptor.dpl);
 665       EIP = gate_dest_offset;
 666
 667       // if INTERRUPT GATE set IF to 0
 668       if (!(gate_descriptor.type & 1)) // even is int-gate
 669         BX_CPU_THIS_PTR clear_IF();
 670       BX_CPU_THIS_PTR clear_TF();
 671       BX_CPU_THIS_PTR clear_VM();
 672       BX_CPU_THIS_PTR clear_RF();
 673       BX_CPU_THIS_PTR clear_NT();
 674
 675       if (is_v8086_mode)
 676       {
 677         BX_CPU_THIS_PTR sregs[BX_SEG_REG_GS].cache.valid = 0;
 678         BX_CPU_THIS_PTR sregs[BX_SEG_REG_GS].selector.value = 0;
 679         BX_CPU_THIS_PTR sregs[BX_SEG_REG_FS].cache.valid = 0;
 680         BX_CPU_THIS_PTR sregs[BX_SEG_REG_FS].selector.value = 0;
 681         BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS].cache.valid = 0;
 682         BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS].selector.value = 0;
 683         BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES].cache.valid = 0;
 684         BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES].selector.value = 0;
 685       }
 686
 687       return;
 688     }
 689     else
 690     {
 691       BX_DEBUG(("interrupt(): INTERRUPT TO SAME PRIVILEGE"));
 692
 693       if (v8086_mode() && (IS_CODE_SEGMENT_CONFORMING(cs_descriptor.type) || cs_descriptor.dpl != 0)) {
 694         // if code segment DPL != 0 then #GP(new code segment selector)
 695         BX_ERROR(("interrupt(): code segment conforming or DPL(%d) != 0 in v8086 mode", cs_descriptor.dpl));
 696         exception(BX_GP_EXCEPTION, cs_selector.value & 0xfffc, 0);
 697       }
 698
 699       // EIP must be in CS limit else #GP(0)
 700       if (gate_dest_offset > cs_descriptor.u.segment.limit_scaled) {
 701         BX_ERROR(("interrupt(): IP > CS descriptor limit"));
 702         exception(BX_GP_EXCEPTION, 0, 0);
 703       }
 704
 705       // push flags onto stack
 706       // push current CS selector onto stack
 707       // push return offset onto stack
 708       if (gate_descriptor.type >= 14) { // 386 gate
 709         push_32(read_eflags());
 710         push_32(BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value);
 711         push_32(EIP);
 712         if (is_error_code)
 713           push_32(error_code);
 714       }
 715       else { // 286 gate
 716         push_16((Bit16u) read_eflags());
 717         push_16(BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value);
 718         push_16(IP);
 719         if (is_error_code)
 720           push_16(error_code);
 721       }
 722
 723       // load CS:IP from gate
 724       // load CS descriptor
 725       // set the RPL field of CS to CPL
 726       load_cs(&cs_selector, &cs_descriptor, CPL);
 727       EIP = gate_dest_offset;
 728
 729       // if interrupt gate then set IF to 0
 730       if (!(gate_descriptor.type & 1)) // even is int-gate
 731         BX_CPU_THIS_PTR clear_IF();
 732       BX_CPU_THIS_PTR clear_TF();
 733       BX_CPU_THIS_PTR clear_NT();
 734       BX_CPU_THIS_PTR clear_VM();
 735       BX_CPU_THIS_PTR clear_RF();
 736       return;
 737     }
 738
 739   default:
 740     BX_PANIC(("bad descriptor type in interrupt()!"));
 741     break;
 742   }
 743 }
 744
 745 void BX_CPU_C::real_mode_int(Bit8u vector, bx_bool is_INT, bx_bool is_error_code, Bit16u error_code)
 746 {
 747   // real mode interrupt
 748   Bit16u cs_selector;
 749
 750   if ((vector*4+3) > BX_CPU_THIS_PTR idtr.limit) {
 751     BX_ERROR(("interrupt(real mode) vector > idtr.limit"));
 752     exception(BX_GP_EXCEPTION, 0, 0);
 753   }
 754
 755   push_16((Bit16u) read_eflags());
 756   push_16(BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value);
 757   push_16(IP);
 758
 759   EIP         = system_read_word(BX_CPU_THIS_PTR idtr.base + 4 * vector);
 760   cs_selector = system_read_word(BX_CPU_THIS_PTR idtr.base + 4 * vector + 2);
 761   load_seg_reg(&BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS], cs_selector);
 762
 763   /* INT affects the following flags: I,T */
 764   BX_CPU_THIS_PTR clear_IF();
 765   BX_CPU_THIS_PTR clear_TF();
 766 #if BX_CPU_LEVEL >= 4
 767   BX_CPU_THIS_PTR clear_AC();
 768 #endif
 769   BX_CPU_THIS_PTR clear_RF();
 770 }
 771
 772 void BX_CPU_C::interrupt(Bit8u vector, bx_bool is_INT, bx_bool is_error_code, Bit16u error_code)
 773 {
 774 #if BX_DEBUGGER
 775   BX_CPU_THIS_PTR show_flag |= Flag_intsig;
 776 #if BX_DEBUG_LINUX
 777   if (bx_dbg.linux_syscall) {
 778     if (vector == 0x80) bx_dbg_linux_syscall(BX_CPU_ID);
 779   }
 780 #endif
 781   bx_dbg_interrupt(BX_CPU_ID, vector, error_code);
 782 #endif
 783
 784   BX_DEBUG(("interrupt(): vector = %u, INT = %u, EXT = %u",
 785       (unsigned) vector, (unsigned) is_INT, (unsigned) BX_CPU_THIS_PTR EXT));
 786
 787   BX_INSTR_INTERRUPT(BX_CPU_ID, vector);
 788   invalidate_prefetch_q();
 789
 790   // Discard any traps and inhibits for new context; traps will
 791   // resume upon return.
 792   BX_CPU_THIS_PTR debug_trap = 0;
 793   BX_CPU_THIS_PTR inhibit_mask = 0;
 794
 795   BX_CPU_THIS_PTR save_cs = BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS];
 796   BX_CPU_THIS_PTR save_ss = BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS];
 797   BX_CPU_THIS_PTR save_eip = RIP;
 798   BX_CPU_THIS_PTR save_esp = RSP;
 799
 800 #if BX_SUPPORT_X86_64
 801   if (long_mode()) {
 802     long_mode_int(vector, is_INT, is_error_code, error_code);
 803     return;
 804   }
 805 #endif
 806
 807   if(real_mode()) {
 808     real_mode_int(vector, is_INT, is_error_code, error_code);
 809   }
 810   else {
 811     protected_mode_int(vector, is_INT, is_error_code, error_code);
 812   }
 813 }
 814
 815 // vector:     0..255: vector in IDT
 816 // error_code: if exception generates and error, push this error code
 817 // trap:       override exception class to TRAP
 818 void BX_CPU_C::exception(unsigned vector, Bit16u error_code, bx_bool trap)
 819 {
 820   unsigned exception_type = 0, exception_class = BX_EXCEPTION_CLASS_FAULT;
 821   bx_bool push_error = 0;
 822
 823   BX_INSTR_EXCEPTION(BX_CPU_ID, vector);
 824
 825 #if BX_DEBUGGER
 826   bx_dbg_exception(BX_CPU_ID, vector, error_code);
 827 #endif
 828
 829   BX_DEBUG(("exception(0x%02x): error_code=%04x", vector, error_code));
 830
 831   // if not initial error, restore previous register values from
 832   // previous attempt to handle exception
 833   if (BX_CPU_THIS_PTR errorno) {
 834     BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS] = BX_CPU_THIS_PTR save_cs;
 835     BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS] = BX_CPU_THIS_PTR save_ss;
 836     RIP = BX_CPU_THIS_PTR save_eip;
 837     RSP = BX_CPU_THIS_PTR save_esp;
 838   }
 839
 840   if (BX_CPU_THIS_PTR errorno > 0) {
 841     if (BX_CPU_THIS_PTR errorno > 2 || BX_CPU_THIS_PTR curr_exception == BX_ET_DOUBLE_FAULT) {
 842       debug(BX_CPU_THIS_PTR prev_rip); // print debug information to the log
 843 #if BX_DEBUGGER
 844       // trap into debugger (similar as done when PANIC occured)
 845       bx_debug_break();
 846 #endif
 847       if (SIM->get_param_bool(BXPN_RESET_ON_TRIPLE_FAULT)->get()) {
 848         BX_ERROR(("exception(): 3rd (%d) exception with no resolution, shutdown status is %02xh, resetting", vector, DEV_cmos_get_reg(0x0f)));
 849         bx_pc_system.Reset(BX_RESET_SOFTWARE);
 850       }
 851       else {
 852         BX_PANIC(("exception(): 3rd (%d) exception with no resolution", vector));
 853         BX_ERROR(("WARNING: Any simulation after this point is completely bogus !"));
 854         shutdown();
 855       }
 856       longjmp(BX_CPU_THIS_PTR jmp_buf_env, 1); // go back to main decode loop
 857     }
 858   }
 859
 860   // note: fault-class exceptions _except_ #DB set RF in
 861   //       eflags image.
 862
 863   switch (vector) {
 864     case BX_DE_EXCEPTION: // DIV by 0
 865       push_error = 0;
 866       exception_class = BX_EXCEPTION_CLASS_FAULT;
 867       exception_type  = BX_ET_CONTRIBUTORY;
 868       break;
 869     case BX_DB_EXCEPTION: // debug exceptions
 870       push_error = 0;
 871       // Instruction fetch breakpoint  - FAULT
 872       // Data read or write breakpoint - TRAP
 873       // I/O read or write breakpoint  - TRAP
 874       // General detect condition      - FAULT
 875       // Single-step                   - TRAP
 876       // Task-switch                   - TRAP
 877       exception_class = BX_EXCEPTION_CLASS_FAULT;
 878       exception_type  = BX_ET_BENIGN;
 879       break;
 880     case 2:               // NMI
 881       push_error = 0;
 882       exception_type  = BX_ET_BENIGN;
 883       break;
 884     case BX_BP_EXCEPTION: // breakpoint
 885       push_error = 0;
 886       exception_class = BX_EXCEPTION_CLASS_TRAP;
 887       exception_type  = BX_ET_BENIGN;
 888       break;
 889     case BX_OF_EXCEPTION: // overflow
 890       push_error = 0;
 891       exception_class = BX_EXCEPTION_CLASS_TRAP;
 892       exception_type  = BX_ET_BENIGN;
 893       break;
 894     case BX_BR_EXCEPTION: // bounds check
 895       push_error = 0;
 896       exception_class = BX_EXCEPTION_CLASS_FAULT;
 897       exception_type  = BX_ET_BENIGN;
 898       break;
 899     case BX_UD_EXCEPTION: // invalid opcode
 900       push_error = 0;
 901       exception_class = BX_EXCEPTION_CLASS_FAULT;
 902       exception_type  = BX_ET_BENIGN;
 903       break;
 904     case BX_NM_EXCEPTION: // device not available
 905       push_error = 0;
 906       exception_class = BX_EXCEPTION_CLASS_FAULT;
 907       exception_type  = BX_ET_BENIGN;
 908       break;
 909     case BX_DF_EXCEPTION: // double fault
 910       push_error = 1;
 911       error_code = 0;
 912       exception_class = BX_EXCEPTION_CLASS_ABORT;
 913       exception_type  = BX_ET_DOUBLE_FAULT;
 914       break;
 915     case 9:               // coprocessor segment overrun (286,386 only)
 916       push_error = 0;
 917       exception_class = BX_EXCEPTION_CLASS_ABORT;
 918       exception_type  = BX_ET_BENIGN;
 919       BX_PANIC(("exception(9): unfinished"));
 920       break;
 921     case BX_TS_EXCEPTION: // invalid TSS
 922       push_error = 1;
 923       exception_class = BX_EXCEPTION_CLASS_FAULT;
 924       exception_type  = BX_ET_CONTRIBUTORY;
 925       break;
 926     case BX_NP_EXCEPTION: // segment not present
 927       push_error = 1;
 928       exception_class = BX_EXCEPTION_CLASS_FAULT;
 929       exception_type  = BX_ET_CONTRIBUTORY;
 930       break;
 931     case BX_SS_EXCEPTION: // stack fault
 932       push_error = 1;
 933       exception_class = BX_EXCEPTION_CLASS_FAULT;
 934       exception_type  = BX_ET_CONTRIBUTORY;
 935       break;
 936     case BX_GP_EXCEPTION: // general protection
 937       push_error = 1;
 938       exception_class = BX_EXCEPTION_CLASS_FAULT;
 939       exception_type  = BX_ET_CONTRIBUTORY;
 940       break;
 941     case BX_PF_EXCEPTION: // page fault
 942       push_error = 1;
 943       exception_class = BX_EXCEPTION_CLASS_FAULT;
 944       exception_type  = BX_ET_PAGE_FAULT;
 945       break;
 946     case 15:              // reserved
 947       BX_PANIC(("exception(15): reserved"));
 948       push_error = 0;
 949       exception_type = 0;
 950       break;
 951     case BX_MF_EXCEPTION: // floating-point error
 952       push_error = 0;
 953       exception_class = BX_EXCEPTION_CLASS_FAULT;
 954       exception_type  = BX_ET_BENIGN;
 955       break;
 956 #if BX_CPU_LEVEL >= 4
 957     case BX_AC_EXCEPTION: // alignment check
 958       push_error = 1;
 959       exception_class = BX_EXCEPTION_CLASS_FAULT;
 960       exception_type  = BX_ET_BENIGN;
 961       break;
 962 #endif
 963 #if BX_CPU_LEVEL >= 5
 964     case BX_MC_EXCEPTION: // machine check
 965       BX_PANIC(("exception(): machine-check, vector 18 not implemented"));
 966       push_error = 0;
 967       exception_class = BX_EXCEPTION_CLASS_ABORT;
 968       exception_type  = BX_ET_BENIGN;
 969       break;
 970 #if BX_SUPPORT_SSE
 971     case BX_XM_EXCEPTION: // SIMD Floating-Point exception
 972       push_error = 0;
 973       exception_class = BX_EXCEPTION_CLASS_FAULT;
 974       exception_type  = BX_ET_BENIGN;
 975       break;
 976 #endif
 977 #endif
 978     default:
 979       BX_PANIC(("exception(%u): bad vector", (unsigned) vector));
 980       exception_type = BX_ET_BENIGN;
 981       push_error = 0;    // keep compiler happy for now
 982       break;
 983   }
 984
 985   if (trap) {
 986     exception_class = BX_EXCEPTION_CLASS_TRAP;
 987   }
 988   else {
 989     if (exception_class == BX_EXCEPTION_CLASS_FAULT)
 990     {
 991       // restore RIP/RSP to value before error occurred
 992       RIP = BX_CPU_THIS_PTR prev_rip;
 993       if (BX_CPU_THIS_PTR speculative_rsp)
 994         RSP = BX_CPU_THIS_PTR prev_rsp;
 995
 996       if (vector != BX_DB_EXCEPTION) BX_CPU_THIS_PTR assert_RF();
 997     }
 998   }
 999
1000   // clear GD flag in the DR7 prior entering debug exception handler
1001   if (vector == BX_DB_EXCEPTION)
1002     BX_CPU_THIS_PTR dr7 &= ~0x00002000;
1003
1004   if (exception_type != BX_ET_PAGE_FAULT) {
1005     // Page faults have different format
1006     error_code = (error_code & 0xfffe) | BX_CPU_THIS_PTR EXT;
1007   }
1008   else {
1009     // FIXME: special format error returned for page faults ?
1010   }
1011   BX_CPU_THIS_PTR EXT = 1;
1012
1013   /* if we've already had 1st exception, see if 2nd causes a
1014    * Double Fault instead.  Otherwise, just record 1st exception
1015    */
1016   if (BX_CPU_THIS_PTR errorno > 0 && exception_type != BX_ET_DOUBLE_FAULT) {
1017     if (! is_exception_OK[BX_CPU_THIS_PTR curr_exception][exception_type]) {
1018       exception(BX_DF_EXCEPTION, 0, 0);
1019     }
1020   }
1021
1022   BX_CPU_THIS_PTR curr_exception = exception_type;
1023   BX_CPU_THIS_PTR errorno++;
1024
1025   if (real_mode()) {
1026     // not INT, no error code pushed
1027     BX_CPU_THIS_PTR interrupt(vector, 0, 0, 0);
1028     BX_CPU_THIS_PTR errorno = 0; // error resolved
1029     longjmp(BX_CPU_THIS_PTR jmp_buf_env, 1); // go back to main decode loop
1030   }
1031   else {
1032     BX_CPU_THIS_PTR interrupt(vector, 0, push_error, error_code);
1033     BX_CPU_THIS_PTR errorno = 0; // error resolved
1034     longjmp(BX_CPU_THIS_PTR jmp_buf_env, 1); // go back to main decode loop
1035   }
1036 }