cpu/logical32.cc

   1 /////////////////////////////////////////////////////////////////////////
   2 // $Id: logical32.cc,v 1.43 2008/08/11 20:34:05 sshwarts Exp $
   3 /////////////////////////////////////////////////////////////////////////
   4 //
   5 //  Copyright (C) 2001  MandrakeSoft S.A.
   6 //
   7 //    MandrakeSoft S.A.
   8 //    43, rue d'Aboukir
   9 //    75002 Paris - France
  10 //    http://www.linux-mandrake.com/
  11 //    http://www.mandrakesoft.com/
  12 //
  13 //  This library is free software; you can redistribute it and/or
  14 //  modify it under the terms of the GNU Lesser General Public
  15 //  License as published by the Free Software Foundation; either
  16 //  version 2 of the License, or (at your option) any later version.
  17 //
  18 //  This library is distributed in the hope that it will be useful,
  19 //  but WITHOUT ANY WARRANTY; without even the implied warranty of
  20 //  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  21 //  Lesser General Public License for more details.
  22 //
  23 //  You should have received a copy of the GNU Lesser General Public
  24 //  License along with this library; if not, write to the Free Software
  25 //  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  26 /////////////////////////////////////////////////////////////////////////
  27
  28 #define NEED_CPU_REG_SHORTCUTS 1
  29 #include "bochs.h"
  30 #include "cpu.h"
  31 #define LOG_THIS BX_CPU_THIS_PTR
  32
  33 #if BX_SUPPORT_X86_64==0
  34 // Make life easier for merging cpu64 and cpu32 code.
  35 #define RAX EAX
  36 #endif
  37
  38 void BX_CPP_AttrRegparmN(1) BX_CPU_C::XOR_EdGdM(bxInstruction_c *i)
  39 {
  40   Bit32u op1_32, op2_32;
  41
  42   bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
  43
  44   op1_32 = read_RMW_virtual_dword(i->seg(), eaddr);
  45   op2_32 = BX_READ_32BIT_REG(i->nnn());
  46   op1_32 ^= op2_32;
  47   write_RMW_virtual_dword(op1_32);
  48
  49   SET_FLAGS_OSZAPC_LOGIC_32(op1_32);
  50 }
  51
  52 void BX_CPP_AttrRegparmN(1) BX_CPU_C::XOR_GdEdR(bxInstruction_c *i)
  53 {
  54   Bit32u op1_32, op2_32;
  55
  56   op1_32 = BX_READ_32BIT_REG(i->nnn());
  57   op2_32 = BX_READ_32BIT_REG(i->rm());
  58   op1_32 ^= op2_32;
  59   BX_WRITE_32BIT_REGZ(i->nnn(), op1_32);
  60
  61   SET_FLAGS_OSZAPC_LOGIC_32(op1_32);
  62 }
  63
  64 void BX_CPP_AttrRegparmN(1) BX_CPU_C::XOR_EAXId(bxInstruction_c *i)
  65 {
  66   Bit32u op1_32;
  67
  68   op1_32 = EAX;
  69   op1_32 ^= i->Id();
  70   RAX = op1_32;
  71
  72   SET_FLAGS_OSZAPC_LOGIC_32(op1_32);
  73 }
  74
  75 void BX_CPP_AttrRegparmN(1) BX_CPU_C::XOR_EdIdM(bxInstruction_c *i)
  76 {
  77   Bit32u op1_32;
  78
  79   bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
  80
  81   op1_32 = read_RMW_virtual_dword(i->seg(), eaddr);
  82   op1_32 ^= i->Id();
  83   write_RMW_virtual_dword(op1_32);
  84
  85   SET_FLAGS_OSZAPC_LOGIC_32(op1_32);
  86 }
  87
  88 void BX_CPP_AttrRegparmN(1) BX_CPU_C::XOR_EdIdR(bxInstruction_c *i)
  89 {
  90   Bit32u op1_32 = BX_READ_32BIT_REG(i->rm());
  91   op1_32 ^= i->Id();
  92   BX_WRITE_32BIT_REGZ(i->rm(), op1_32);
  93
  94   SET_FLAGS_OSZAPC_LOGIC_32(op1_32);
  95 }
  96
  97 void BX_CPP_AttrRegparmN(1) BX_CPU_C::OR_EdIdM(bxInstruction_c *i)
  98 {
  99   Bit32u op1_32;
 100
 101   bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
 102
 103   op1_32 = read_RMW_virtual_dword(i->seg(), eaddr);
 104   op1_32 |= i->Id();
 105   write_RMW_virtual_dword(op1_32);
 106
 107   SET_FLAGS_OSZAPC_LOGIC_32(op1_32);
 108 }
 109
 110 void BX_CPP_AttrRegparmN(1) BX_CPU_C::OR_EdIdR(bxInstruction_c *i)
 111 {
 112   Bit32u op1_32 = BX_READ_32BIT_REG(i->rm());
 113   op1_32 |= i->Id();
 114   BX_WRITE_32BIT_REGZ(i->rm(), op1_32);
 115
 116   SET_FLAGS_OSZAPC_LOGIC_32(op1_32);
 117 }
 118
 119 void BX_CPP_AttrRegparmN(1) BX_CPU_C::NOT_EdM(bxInstruction_c *i)
 120 {
 121   Bit32u op1_32;
 122
 123   bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
 124
 125   op1_32 = read_RMW_virtual_dword(i->seg(), eaddr);
 126   op1_32 = ~op1_32;
 127   write_RMW_virtual_dword(op1_32);
 128 }
 129
 130 void BX_CPP_AttrRegparmN(1) BX_CPU_C::NOT_EdR(bxInstruction_c *i)
 131 {
 132   Bit32u op1_32 = BX_READ_32BIT_REG(i->rm());
 133   op1_32 = ~op1_32;
 134   BX_WRITE_32BIT_REGZ(i->rm(), op1_32);
 135 }
 136
 137 void BX_CPP_AttrRegparmN(1) BX_CPU_C::OR_EdGdM(bxInstruction_c *i)
 138 {
 139   Bit32u op1_32, op2_32;
 140
 141   bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
 142
 143   op1_32 = read_RMW_virtual_dword(i->seg(), eaddr);
 144   op2_32 = BX_READ_32BIT_REG(i->nnn());
 145   op1_32 |= op2_32;
 146   write_RMW_virtual_dword(op1_32);
 147
 148   SET_FLAGS_OSZAPC_LOGIC_32(op1_32);
 149 }
 150
 151 void BX_CPP_AttrRegparmN(1) BX_CPU_C::OR_GdEdR(bxInstruction_c *i)
 152 {
 153   Bit32u op1_32, op2_32;
 154
 155   op1_32 = BX_READ_32BIT_REG(i->nnn());
 156   op2_32 = BX_READ_32BIT_REG(i->rm());
 157   op1_32 |= op2_32;
 158   BX_WRITE_32BIT_REGZ(i->nnn(), op1_32);
 159
 160   SET_FLAGS_OSZAPC_LOGIC_32(op1_32);
 161 }
 162
 163 void BX_CPP_AttrRegparmN(1) BX_CPU_C::OR_EAXId(bxInstruction_c *i)
 164 {
 165   Bit32u op1_32, op2_32;
 166
 167   op1_32 = EAX;
 168   op2_32 = i->Id();
 169   op1_32 |= op2_32;
 170   RAX = op1_32;
 171
 172   SET_FLAGS_OSZAPC_LOGIC_32(op1_32);
 173 }
 174
 175 void BX_CPP_AttrRegparmN(1) BX_CPU_C::AND_EdGdM(bxInstruction_c *i)
 176 {
 177   Bit32u op1_32, op2_32;
 178
 179   bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
 180
 181   op1_32 = read_RMW_virtual_dword(i->seg(), eaddr);
 182   op2_32 = BX_READ_32BIT_REG(i->nnn());
 183   op1_32 &= op2_32;
 184   write_RMW_virtual_dword(op1_32);
 185
 186   SET_FLAGS_OSZAPC_LOGIC_32(op1_32);
 187 }
 188
 189 void BX_CPP_AttrRegparmN(1) BX_CPU_C::AND_GdEdR(bxInstruction_c *i)
 190 {
 191   Bit32u op1_32, op2_32;
 192
 193   op1_32 = BX_READ_32BIT_REG(i->nnn());
 194   op2_32 = BX_READ_32BIT_REG(i->rm());
 195   op1_32 &= op2_32;
 196   BX_WRITE_32BIT_REGZ(i->nnn(), op1_32);
 197
 198   SET_FLAGS_OSZAPC_LOGIC_32(op1_32);
 199 }
 200
 201 void BX_CPP_AttrRegparmN(1) BX_CPU_C::AND_EAXId(bxInstruction_c *i)
 202 {
 203   Bit32u op1_32, op2_32;
 204
 205   op1_32 = EAX;
 206   op2_32 = i->Id();
 207   op1_32 &= op2_32;
 208   RAX = op1_32;
 209
 210   SET_FLAGS_OSZAPC_LOGIC_32(op1_32);
 211 }
 212
 213 void BX_CPP_AttrRegparmN(1) BX_CPU_C::AND_EdIdM(bxInstruction_c *i)
 214 {
 215   Bit32u op1_32;
 216
 217   bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
 218
 219   op1_32 = read_RMW_virtual_dword(i->seg(), eaddr);
 220   op1_32 &= i->Id();
 221   write_RMW_virtual_dword(op1_32);
 222
 223   SET_FLAGS_OSZAPC_LOGIC_32(op1_32);
 224 }
 225
 226 void BX_CPP_AttrRegparmN(1) BX_CPU_C::AND_EdIdR(bxInstruction_c *i)
 227 {
 228   Bit32u op1_32 = BX_READ_32BIT_REG(i->rm());
 229   op1_32 &= i->Id();
 230   BX_WRITE_32BIT_REGZ(i->rm(), op1_32);
 231
 232   SET_FLAGS_OSZAPC_LOGIC_32(op1_32);
 233 }
 234
 235 void BX_CPP_AttrRegparmN(1) BX_CPU_C::TEST_EdGdR(bxInstruction_c *i)
 236 {
 237   Bit32u op1_32, op2_32;
 238
 239   op1_32 = BX_READ_32BIT_REG(i->rm());
 240   op2_32 = BX_READ_32BIT_REG(i->nnn());
 241   op1_32 &= op2_32;
 242
 243   SET_FLAGS_OSZAPC_LOGIC_32(op1_32);
 244 }
 245
 246 void BX_CPP_AttrRegparmN(1) BX_CPU_C::TEST_EAXId(bxInstruction_c *i)
 247 {
 248   Bit32u op1_32, op2_32;
 249
 250   op1_32 = EAX;
 251   op2_32 = i->Id();
 252   op1_32 &= op2_32;
 253
 254   SET_FLAGS_OSZAPC_LOGIC_32(op1_32);
 255 }
 256
 257 void BX_CPP_AttrRegparmN(1) BX_CPU_C::TEST_EdIdR(bxInstruction_c *i)
 258 {
 259   Bit32u op1_32 = BX_READ_32BIT_REG(i->rm());
 260   op1_32 &= i->Id();
 261   SET_FLAGS_OSZAPC_LOGIC_32(op1_32);
 262 }