cpu/smm.h

   1 /////////////////////////////////////////////////////////////////////////
   2 // $Id: smm.h,v 1.5 2008/02/02 21:46:53 sshwarts Exp $
   3 /////////////////////////////////////////////////////////////////////////
   4 //
   5 //   Copyright (c) 2006 Stanislav Shwartsman
   6 //          Written by Stanislav Shwartsman [sshwarts at sourceforge net]
   7 //
   8 //  This library is free software; you can redistribute it and/or
   9 //  modify it under the terms of the GNU Lesser General Public
  10 //  License as published by the Free Software Foundation; either
  11 //  version 2 of the License, or (at your option) any later version.
  12 //
  13 //  This library is distributed in the hope that it will be useful,
  14 //  but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 //  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  16 //  Lesser General Public License for more details.
  17 //
  18 //  You should have received a copy of the GNU Lesser General Public
  19 //  License along with this library; if not, write to the Free Software
  20 //  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  21 /////////////////////////////////////////////////////////////////////////
  22
  23 #ifndef BX_SMM_H
  24 #define BX_SMM_H
  25
  26 /* SMM feature masks */
  27 #define SMM_IO_INSTRUCTION_RESTART  (0x00010000)
  28 #define SMM_SMBASE_RELOCATION       (0x00020000)
  29
  30 #define SMM_SAVE_STATE_MAP_SIZE 128
  31
  32 #if BX_SUPPORT_X86_64
  33
  34 // for x86-64 configuration using AMD Athlon 64 512-byte SMM save state map
  35 // revision ID according to QEMU/Bochs BIOS
  36 #define SMM_REVISION_ID (0x00000064 | SMM_SMBASE_RELOCATION)
  37
  38 #define SMRAM_OFFSET_RAX_HI32  0x7ffc
  39 #define SMRAM_OFFSET_RAX_LO32  0x7ff8
  40 #define SMRAM_OFFSET_RCX_HI32  0x7ff4
  41 #define SMRAM_OFFSET_RCX_LO32  0x7ff0
  42 #define SMRAM_OFFSET_RDX_HI32  0x7fec
  43 #define SMRAM_OFFSET_RDX_LO32  0x7fe8
  44 #define SMRAM_OFFSET_RBX_HI32  0x7fe4
  45 #define SMRAM_OFFSET_RBX_LO32  0x7fe0
  46 #define SMRAM_OFFSET_RSP_HI32  0x7fdc
  47 #define SMRAM_OFFSET_RSP_LO32  0x7fd8
  48 #define SMRAM_OFFSET_RBP_HI32  0x7fd4
  49 #define SMRAM_OFFSET_RBP_LO32  0x7fd0
  50 #define SMRAM_OFFSET_RSI_HI32  0x7fcc
  51 #define SMRAM_OFFSET_RSI_LO32  0x7fc8
  52 #define SMRAM_OFFSET_RDI_HI32  0x7fc4
  53 #define SMRAM_OFFSET_RDI_LO32  0x7fc0
  54 #define SMRAM_OFFSET_R8_HI32   0x7fbc
  55 #define SMRAM_OFFSET_R8_LO32   0x7fb8
  56 #define SMRAM_OFFSET_R9_HI32   0x7fb4
  57 #define SMRAM_OFFSET_R9_LO32   0x7fb0
  58 #define SMRAM_OFFSET_R10_HI32  0x7fac
  59 #define SMRAM_OFFSET_R10_LO32  0x7fa8
  60 #define SMRAM_OFFSET_R11_HI32  0x7fa4
  61 #define SMRAM_OFFSET_R11_LO32  0x7fa0
  62 #define SMRAM_OFFSET_R12_HI32  0x7f9c
  63 #define SMRAM_OFFSET_R12_LO32  0x7f98
  64 #define SMRAM_OFFSET_R13_HI32  0x7f94
  65 #define SMRAM_OFFSET_R13_LO32  0x7f90
  66 #define SMRAM_OFFSET_R14_HI32  0x7f8c
  67 #define SMRAM_OFFSET_R14_LO32  0x7f88
  68 #define SMRAM_OFFSET_R15_HI32  0x7f84
  69 #define SMRAM_OFFSET_R15_LO32  0x7f80
  70 #define SMRAM_OFFSET_RIP_HI32  0x7f7c
  71 #define SMRAM_OFFSET_RIP_LO32  0x7f78
  72 // Hi32 part of RFLAGS64       0x7f74    (always zero)
  73 #define SMRAM_OFFSET_RFLAGS32  0x7f70
  74 // Hi32 part of 64-bit DR6     0x7f6c    (always zero)
  75 #define SMRAM_OFFSET_DR6       0x7f68
  76 // Hi32 part of 64-bit DR7     0x7f64    (always zero)
  77 #define SMRAM_OFFSET_DR7       0x7f60
  78 // Hi32 part of 64-bit CR0     0x7f5c    (always zero)
  79 #define SMRAM_OFFSET_CR0       0x7f58
  80 // Hi32 part of 64-bit CR3     0x7f54    (always zero, 32-bit physical address)
  81 #define SMRAM_OFFSET_CR3       0x7f50
  82 // Hi32 part of 64-bit CR4     0x7f4c    (always zero)
  83 #define SMRAM_OFFSET_CR4       0x7f48
  84 // reserved                    0x7f44
  85 // reserved                    0x7f40
  86 // reserved                    0x7f3c
  87 // reserved                    0x7f38
  88 // reserved                    0x7f34
  89 // reserved                    0x7f30
  90 // reserved                    0x7f2c
  91 // reserved                    0x7f28
  92 // reserved                    0x7f24
  93 // reserved                    0x7f20
  94 // reserved                    0x7f1c
  95 // reserved                    0x7f18
  96 // reserved                    0x7f14
  97 // reserved                    0x7f10
  98 // reserved                    0x7f0c
  99 // reserved                    0x7f08
 100 // reserved                    0x7f04
 101 #define SMRAM_SMBASE_OFFSET    0x7f00
 102 #define SMRAM_SMM_REVISION_ID  0x7efc
 103 // reserved                    0x7ef8
 104 // reserved                    0x7ef4
 105 // reserved                    0x7ef0
 106 // reserved                    0x7eec
 107 // reserved                    0x7ee8
 108 // reserved                    0x7ee4
 109 // reserved                    0x7ee0
 110 // reserved                    0x7edc
 111 // reserved                    0x7ed8
 112 // High part of 64-bit EFER    0x7ed4    (always zero)
 113 #define SMRAM_OFFSET_EFER      0x7ed0
 114 // reserved                    0x7ecc
 115 #define SMRAM_IO_INSTRUCTION_RESTART 0x7ec8
 116 #define SMRAM_AUTOHALT_RESTART       0x7ec8
 117 #define SMRAM_NMI_MASK               0x7ec8
 118 // reserved                    0x7ec4
 119 #define SMRAM_SMM_IO_TRAP      0x7ec0
 120 // reserved                    0x7ebc
 121 // reserved                    0x7eb8
 122 // reserved                    0x7eb4
 123 // reserved                    0x7eb0
 124 // reserved                    0x7eac
 125 // reserved                    0x7ea8
 126 // reserved                    0x7ea4
 127 // reserved                    0x7ea0
 128 #define SMRAM_TR_BASE_HI32     0x7e9c
 129 #define SMRAM_TR_BASE_LO32     0x7e98
 130 #define SMRAM_TR_LIMIT         0x7e94
 131 #define SMRAM_TR_SELECTOR_AR   0x7e90
 132 #define SMRAM_IDTR_BASE_HI32   0x7e8c
 133 #define SMRAM_IDTR_BASE_LO32   0x7e88
 134 #define SMRAM_IDTR_LIMIT       0x7e84
 135 // reserved                    0x7e80
 136 #define SMRAM_LDTR_BASE_HI32   0x7e7c
 137 #define SMRAM_LDTR_BASE_LO32   0x7e78
 138 #define SMRAM_LDTR_LIMIT       0x7e74
 139 #define SMRAM_LDTR_SELECTOR_AR 0x7e70
 140 #define SMRAM_GDTR_BASE_HI32   0x7e6c
 141 #define SMRAM_GDTR_BASE_LO32   0x7e68
 142 #define SMRAM_GDTR_LIMIT       0x7e64
 143 // reserved                    0x7e60
 144 #define SMRAM_GS_BASE_HI32     0x7e5c
 145 #define SMRAM_GS_BASE_LO32     0x7e58
 146 #define SMRAM_GS_LIMIT         0x7e54
 147 #define SMRAM_GS_SELECTOR_AR   0x7e50
 148 #define SMRAM_FS_BASE_HI32     0x7e4c
 149 #define SMRAM_FS_BASE_LO32     0x7e48
 150 #define SMRAM_FS_LIMIT         0x7e44
 151 #define SMRAM_FS_SELECTOR_AR   0x7e40
 152 #define SMRAM_DS_BASE_HI32     0x7e3c
 153 #define SMRAM_DS_BASE_LO32     0x7e38
 154 #define SMRAM_DS_LIMIT         0x7e34
 155 #define SMRAM_DS_SELECTOR_AR   0x7e30
 156 #define SMRAM_SS_BASE_HI32     0x7e2c
 157 #define SMRAM_SS_BASE_LO32     0x7e28
 158 #define SMRAM_SS_LIMIT         0x7e24
 159 #define SMRAM_SS_SELECTOR_AR   0x7e20
 160 #define SMRAM_CS_BASE_HI32     0x7e1c
 161 #define SMRAM_CS_BASE_LO32     0x7e18
 162 #define SMRAM_CS_LIMIT         0x7e14
 163 #define SMRAM_CS_SELECTOR_AR   0x7e10
 164 #define SMRAM_ES_BASE_HI32     0x7e0c
 165 #define SMRAM_ES_BASE_LO32     0x7e08
 166 #define SMRAM_ES_LIMIT         0x7e04
 167 #define SMRAM_ES_SELECTOR_AR   0x7e00
 168
 169 #else  /* BX_SUPPORT_X86_64 == 0 */
 170
 171 // for x86-32 configuration using Intel P6 512-byte SMM save state map
 172 #define SMM_REVISION_ID (0x00000000 | SMM_SMBASE_RELOCATION)
 173
 174 // source for Intel P6 SMM save state map used: www.sandpile.org
 175
 176 #define SMRAM_OFFSET_CR0       0x7ffc
 177 #define SMRAM_OFFSET_CR3       0x7ff8
 178 #define SMRAM_OFFSET_EFLAGS    0x7ff4
 179 #define SMRAM_OFFSET_EIP       0x7ff0
 180 #define SMRAM_OFFSET_EDI       0x7fec
 181 #define SMRAM_OFFSET_ESI       0x7fe8
 182 #define SMRAM_OFFSET_EBP       0x7fe4
 183 #define SMRAM_OFFSET_ESP       0x7fe0
 184 #define SMRAM_OFFSET_EBX       0x7fdc
 185 #define SMRAM_OFFSET_EDX       0x7fd8
 186 #define SMRAM_OFFSET_ECX       0x7fd4
 187 #define SMRAM_OFFSET_EAX       0x7fd0
 188 #define SMRAM_OFFSET_DR6       0x7fcc
 189 #define SMRAM_OFFSET_DR7       0x7fc8
 190 #define SMRAM_TR_SELECTOR      0x7fc4
 191 #define SMRAM_LDTR_SELECTOR    0x7fc0
 192 #define SMRAM_GS_SELECTOR      0x7fbc
 193 #define SMRAM_FS_SELECTOR      0x7fb8
 194 #define SMRAM_DS_SELECTOR      0x7fb4
 195 #define SMRAM_SS_SELECTOR      0x7fb0
 196 #define SMRAM_CS_SELECTOR      0x7fac
 197 #define SMRAM_ES_SELECTOR      0x7fa8
 198 #define SMRAM_SS_BASE          0x7fa4
 199 #define SMRAM_SS_LIMIT         0x7fa0
 200 #define SMRAM_SS_SELECTOR_AR   0x7f9c
 201 #define SMRAM_CS_BASE          0x7f98
 202 #define SMRAM_CS_LIMIT         0x7f94
 203 #define SMRAM_CS_SELECTOR_AR   0x7f90
 204 #define SMRAM_ES_BASE          0x7f8c
 205 #define SMRAM_ES_LIMIT         0x7f88
 206 #define SMRAM_ES_SELECTOR_AR   0x7f84
 207 #define SMRAM_LDTR_BASE        0x7f80
 208 #define SMRAM_LDTR_LIMIT       0x7f7c
 209 #define SMRAM_LDTR_SELECTOR_AR 0x7f78
 210 #define SMRAM_GDTR_BASE        0x7f74
 211 #define SMRAM_GDTR_LIMIT       0x7f70
 212 // reserved                    0x7f6c
 213 // reserved                    0x7f68
 214 #define SMRAM_TR_BASE          0x7f64
 215 #define SMRAM_TR_LIMIT         0x7f60
 216 #define SMRAM_TR_SELECTOR_AR   0x7f5c
 217 #define SMRAM_IDTR_BASE        0x7f58
 218 #define SMRAM_IDTR_LIMIT       0x7f54
 219 // reserved                    0x7f50
 220 #define SMRAM_GS_BASE          0x7f4c
 221 #define SMRAM_GS_LIMIT         0x7f48
 222 #define SMRAM_GS_SELECTOR_AR   0x7f44
 223 #define SMRAM_FS_BASE          0x7f40
 224 #define SMRAM_FS_LIMIT         0x7f3c
 225 #define SMRAM_FS_SELECTOR_AR   0x7f38
 226 #define SMRAM_DS_BASE          0x7f34
 227 #define SMRAM_DS_LIMIT         0x7f30
 228 #define SMRAM_DS_SELECTOR_AR   0x7f2c
 229 // reserved                    0x7f28
 230 // reserved                    0x7f24
 231 // reserved                    0x7f20
 232 // reserved                    0x7f1c
 233 // reserved                    0x7f18
 234 #define SMRAM_OFFSET_CR4       0x7f14
 235 // reserved                    0x7f10    (used for I/O restart)
 236 // reserved                    0x7f0c    (used for I/O restart)
 237 // reserved                    0x7f08    (used for I/O restart)
 238 // reserved                    0x7f04    (used for I/O restart)
 239 #define SMRAM_IO_INSTRUCTION_RESTART 0x7f00
 240 #define SMRAM_AUTOHALT_RESTART       0x7f00
 241 #define SMRAM_SMM_REVISION_ID  0x7efc
 242 #define SMRAM_SMBASE_OFFSET    0x7ef8
 243 // reserved                    0x7ef4
 244 // reserved                    0x7ef0
 245 // reserved                    0x7eec
 246 // reserved                    0x7ee8
 247 // reserved                    0x7ee4
 248 // reserved                    0x7ee0
 249 // reserved                    0x7edc
 250 // reserved                    0x7ed8
 251 // reserved                    0x7ed4
 252 // reserved                    0x7ed0
 253 // reserved                    0x7ecc
 254 // reserved                    0x7ec8
 255 // reserved                    0x7ec4
 256 // reserved                    0x7ec0
 257 // reserved                    0x7ebc
 258 // reserved                    0x7eb8
 259 // reserved                    0x7eb4
 260 // reserved                    0x7eb0
 261 // reserved                    0x7eac
 262 // reserved                    0x7ea8
 263 // reserved                    0x7ea4
 264 // reserved                    0x7ea0
 265 // reserved                    0x7e9c
 266 // reserved                    0x7e98
 267 // reserved                    0x7e94
 268 // reserved                    0x7e90
 269 // reserved                    0x7e8c
 270 // reserved                    0x7e88
 271 // reserved                    0x7e84
 272 // reserved                    0x7e80
 273 // reserved                    0x7e7c
 274 // reserved                    0x7e78
 275 // reserved                    0x7e74
 276 // reserved                    0x7e70
 277 // reserved                    0x7e6c
 278 // reserved                    0x7e68
 279 // reserved                    0x7e64
 280 // reserved                    0x7e60
 281 // reserved                    0x7e5c
 282 // reserved                    0x7e58
 283 // reserved                    0x7e54
 284 // reserved                    0x7e50
 285 // reserved                    0x7e4c
 286 // reserved                    0x7e48
 287 // reserved                    0x7e44
 288 // reserved                    0x7e40
 289 // reserved                    0x7e3c
 290 // reserved                    0x7e38
 291 // reserved                    0x7e34
 292 // reserved                    0x7e30
 293 // reserved                    0x7e2c
 294 // reserved                    0x7e28
 295 // reserved                    0x7e24
 296 // reserved                    0x7e20
 297 // reserved                    0x7e1c
 298 // reserved                    0x7e18
 299 // reserved                    0x7e14
 300 // reserved                    0x7e10
 301 // reserved                    0x7e0c
 302 // reserved                    0x7e08
 303 // reserved                    0x7e04
 304 // reserved                    0x7e00
 305
 306 #endif /* BX_SUPPORT_X86_64 */
 307
 308 #endif