cpu/xmm.h

   1 /////////////////////////////////////////////////////////////////////////
   2 // $Id: xmm.h,v 1.23 2007/07/15 19:03:39 sshwarts Exp $
   3 /////////////////////////////////////////////////////////////////////////
   4 //
   5 //   Copyright (c) 2003 Stanislav Shwartsman
   6 //          Written by Stanislav Shwartsman [sshwarts at sourceforge net]
   7 //
   8 //  This library is free software; you can redistribute it and/or
   9 //  modify it under the terms of the GNU Lesser General Public
  10 //  License as published by the Free Software Foundation; either
  11 //  version 2 of the License, or (at your option) any later version.
  12 //
  13 //  This library is distributed in the hope that it will be useful,
  14 //  but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 //  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  16 //  Lesser General Public License for more details.
  17 //
  18 //  You should have received a copy of the GNU Lesser General Public
  19 //  License along with this library; if not, write to the Free Software
  20 //  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  21 //
  22
  23 #ifndef BX_SSE_EXTENSIONS_H
  24 #define BX_SSE_EXTENSIONS_H
  25
  26 /* XMM REGISTER */
  27
  28 typedef union bx_xmm_reg_t {
  29    Bit8s   _sbyte[16];
  30    Bit16s  _s16[8];
  31    Bit32s  _s32[4];
  32    Bit64s  _s64[2];
  33    Bit8u   _ubyte[16];
  34    Bit16u  _u16[8];
  35    Bit32u  _u32[4];
  36    Bit64u  _u64[2];
  37 } BxPackedXmmRegister;
  38
  39 #ifdef BX_BIG_ENDIAN
  40 #define xmm64s(i)   _s64[1 - (i)]
  41 #define xmm32s(i)   _s32[3 - (i)]
  42 #define xmm16s(i)   _s16[7 - (i)]
  43 #define xmmsbyte(i) _sbyte[15 - (i)]
  44 #define xmmubyte(i) _ubyte[15 - (i)]
  45 #define xmm16u(i)   _u16[7 - (i)]
  46 #define xmm32u(i)   _u32[3 - (i)]
  47 #define xmm64u(i)   _u64[1 - (i)]
  48 #else
  49 #define xmm64s(i)   _s64[(i)]
  50 #define xmm32s(i)   _s32[(i)]
  51 #define xmm16s(i)   _s16[(i)]
  52 #define xmmsbyte(i) _sbyte[(i)]
  53 #define xmmubyte(i) _ubyte[(i)]
  54 #define xmm16u(i)   _u16[(i)]
  55 #define xmm32u(i)   _u32[(i)]
  56 #define xmm64u(i)   _u64[(i)]
  57 #endif
  58
  59 #if BX_SUPPORT_SSE >= 1
  60
  61 #if BX_SUPPORT_X86_64
  62 #  define BX_XMM_REGISTERS 16
  63 #else
  64 #  define BX_XMM_REGISTERS 8
  65 #endif
  66
  67 /* read XMM register */
  68 #define BX_READ_XMM_REG(index) (BX_CPU_THIS_PTR xmm[index])
  69
  70 /* read only high 64 bit of the register */
  71 #define BX_READ_XMM_REG_HI_QWORD(index) \
  72     ((BX_CPU_THIS_PTR xmm[index]).xmm64u(1))
  73
  74 /* read only low 64 bit of the register */
  75 #define BX_READ_XMM_REG_LO_QWORD(index) \
  76     ((BX_CPU_THIS_PTR xmm[index]).xmm64u(0))
  77
  78 /* read only low 32 bit of the register */
  79 #define BX_READ_XMM_REG_LO_DWORD(index) \
  80     ((BX_CPU_THIS_PTR xmm[index]).xmm32u(0))
  81
  82 /* read only low 16 bit of the register */
  83 #define BX_READ_XMM_REG_LO_WORD(index) \
  84     ((BX_CPU_THIS_PTR xmm[index]).xmm16u(0))
  85
  86 /* short names for above macroses */
  87 #define BX_XMM_REG_HI_QWORD BX_READ_XMM_REG_HI_QWORD
  88 #define BX_XMM_REG_LO_QWORD BX_READ_XMM_REG_LO_QWORD
  89 #define BX_XMM_REG_LO_DWORD BX_READ_XMM_REG_LO_DWORD
  90
  91 /* store XMM register */
  92 #define BX_WRITE_XMM_REG(index, reg) \
  93     { BX_CPU_THIS_PTR xmm[index] = (reg); }
  94
  95 /* store only high 64 bit of the register, rest of the register unchanged */
  96 #define BX_WRITE_XMM_REG_HI_QWORD(index, reg64) \
  97     { (BX_CPU_THIS_PTR xmm[index]).xmm64u(1) = (reg64); }
  98
  99 /* store only low 64 bit of the register, rest of the register unchanged */
 100 #define BX_WRITE_XMM_REG_LO_QWORD(index, reg64) \
 101     { (BX_CPU_THIS_PTR xmm[index]).xmm64u(0) = (reg64); }
 102
 103 /* store only low 32 bit of the register, rest of the register unchanged */
 104 #define BX_WRITE_XMM_REG_LO_DWORD(index, reg32) \
 105     { (BX_CPU_THIS_PTR xmm[index]).xmm32u(0) = (reg32); }
 106
 107
 108 /* MXCSR REGISTER */
 109
 110 /* 31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16
 111  * ==|==|=====|==|==|==|==|==|==|==|==|==|==|==|==  (reserved)
 112  *  0| 0| 0| 0| 0| 0| 0| 0| 0| 0| 0| 0| 0| 0|MM| 0
 113  *
 114  * 15|14|13|12|11|10| 9| 8| 7| 6| 5| 4| 3| 2| 1| 0
 115  * ==|==|=====|==|==|==|==|==|==|==|==|==|==|==|==
 116  * FZ| R C |PM|UM|OM|ZM|DM|IM|DZ|PE|UE|OE|ZE|DE|IE
 117  */
 118
 119 /* MXCSR REGISTER FIELDS DESCRIPTION */
 120
 121 /*
 122  * IE  0    Invalid-Operation Exception             0
 123  * DE  1    Denormalized-Operand Exception          0
 124  * ZE  2    Zero-Divide Exception                   0
 125  * OE  3    Overflow Exception                      0
 126  * UE  4    Underflow Exception                     0
 127  * PE  5    Precision Exception                     0
 128  * DZ  6    Denormals are Zeros                     0
 129  * IM  7    Invalid-Operation Exception Mask        1
 130  * DM  8    Denormalized-Operand Exception Mask     1
 131  * ZM  9    Zero-Divide Exception Mask              1
 132  * OM 10    Overflow Exception Mask                 1
 133  * UM 11    Underflow Exception Mask                1
 134  * PM 12    Precision Exception Mask                1
 135  * RC 13-14 Floating-Point Rounding Control         00
 136  * FZ 15    Flush-to-Zero for Masked Underflow      0
 137  * RZ 16    Reserved                                0
 138  * MM 17    Misaligned Exceptuion Mask              0
 139  */
 140
 141 #define MXCSR_EXCEPTIONS                 0x0000003F
 142 #define MXCSR_DAZ                        0x00000040
 143 #define MXCSR_MASKED_EXCEPTIONS          0x00001F80
 144 #define MXCSR_ROUNDING_CONTROL           0x00006000
 145 #define MXCSR_FLUSH_MASKED_UNDERFLOW     0x00008000
 146 #define MXCSR_MISALIGNED_EXCEPTION_MASK  0x00020000
 147
 148 #define MXCSR_IE 0x00000001
 149 #define MXCSR_DE 0x00000002
 150 #define MXCSR_ZE 0x00000004
 151 #define MXCSR_OE 0x00000008
 152 #define MXCSR_UE 0x00000010
 153 #define MXCSR_PE 0x00000020
 154
 155 #define MXCSR_IM 0x00000080
 156 #define MXCSR_DM 0x00000100
 157 #define MXCSR_ZM 0x00000200
 158 #define MXCSR_OM 0x00000400
 159 #define MXCSR_UM 0x00000800
 160 #define MXCSR_PM 0x00001000
 161
 162 #define MXCSR_RESET 0x00001F80  /* reset value of the MXCSR register */
 163
 164 struct BOCHSAPI bx_mxcsr_t
 165 {
 166   Bit32u mxcsr;
 167
 168   bx_mxcsr_t (Bit32u val = MXCSR_RESET)
 169         : mxcsr(val) {}
 170
 171 #define IMPLEMENT_MXCSR_ACCESSOR(name, bitmask, bitnum)        \
 172   int get_##name () const {                                    \
 173     return (mxcsr & (bitmask)) >> (bitnum);                    \
 174   }
 175
 176   IMPLEMENT_MXCSR_ACCESSOR(exceptions_masks, MXCSR_MASKED_EXCEPTIONS, 7);
 177   IMPLEMENT_MXCSR_ACCESSOR(DAZ, MXCSR_DAZ, 6);
 178   IMPLEMENT_MXCSR_ACCESSOR(rounding_mode, MXCSR_ROUNDING_CONTROL, 13);
 179   IMPLEMENT_MXCSR_ACCESSOR(flush_masked_underflow, MXCSR_FLUSH_MASKED_UNDERFLOW, 15);
 180   IMPLEMENT_MXCSR_ACCESSOR(misaligned_exception_mask, MXCSR_MISALIGNED_EXCEPTION_MASK, 17);
 181
 182   IMPLEMENT_MXCSR_ACCESSOR(IE, MXCSR_IE, 0);
 183   IMPLEMENT_MXCSR_ACCESSOR(DE, MXCSR_DE, 1);
 184   IMPLEMENT_MXCSR_ACCESSOR(ZE, MXCSR_ZE, 2);
 185   IMPLEMENT_MXCSR_ACCESSOR(OE, MXCSR_OE, 3);
 186   IMPLEMENT_MXCSR_ACCESSOR(UE, MXCSR_UE, 4);
 187   IMPLEMENT_MXCSR_ACCESSOR(PE, MXCSR_PE, 5);
 188
 189   IMPLEMENT_MXCSR_ACCESSOR(IM, MXCSR_IM, 7);
 190   IMPLEMENT_MXCSR_ACCESSOR(DM, MXCSR_DM, 8);
 191   IMPLEMENT_MXCSR_ACCESSOR(ZM, MXCSR_ZM, 9);
 192   IMPLEMENT_MXCSR_ACCESSOR(OM, MXCSR_OM, 10);
 193   IMPLEMENT_MXCSR_ACCESSOR(UM, MXCSR_UM, 11);
 194   IMPLEMENT_MXCSR_ACCESSOR(PM, MXCSR_PM, 12);
 195
 196   void set_exceptions(int status) {
 197     mxcsr |= (status & MXCSR_EXCEPTIONS);
 198   }
 199
 200 };
 201
 202 /* reset reserved bits */
 203 #define MXCSR_MASK (0x0000FFBF |                 \
 204          (BX_SUPPORT_DAZ ? MXCSR_DAZ : 0) |      \
 205          (BX_SUPPORT_MISALIGNED_SSE ? MXCSR_MISALIGNED_EXCEPTION_MASK : 0))
 206
 207 #if defined(NEED_CPU_REG_SHORTCUTS)
 208 #define MXCSR (BX_CPU_THIS_PTR mxcsr)
 209 #endif
 210
 211 /* INTEGER SATURATION */
 212
 213 /*
 214   SaturateWordSToByteS   converts   a signed 16-bit value to a
 215   signed  8-bit  value. If the signed 16-bit value is less than -128, it
 216   is  represented  by  the saturated value -128 (0x80). If it is greater
 217   than 127, it is represented by the saturated value 127 (0x7F).
 218 */
 219 Bit8s SaturateWordSToByteS(Bit16s value)
 220 BX_CPP_AttrRegparmN(1);
 221
 222 /*
 223   SaturateDwordSToWordS  converts  a  signed 32-bit value to a
 224   signed  16-bit  value. If the signed 32-bit value is less than -32768,
 225   it  is  represented  by  the saturated value -32768 (0x8000). If it is
 226   greater  than  32767,  it  is represented by the saturated value 32767
 227   (0x7FFF).
 228 */
 229 Bit16s SaturateDwordSToWordS(Bit32s value)
 230 BX_CPP_AttrRegparmN(1);
 231
 232 /*
 233   SaturateWordSToByteU  converts a signed 16-bit value to an
 234   unsigned  8-bit value. If the signed 16-bit value is less than zero it
 235   is  represented  by  the  saturated value zero (0x00).If it is greater
 236   than 255 it is represented by the saturated value 255 (0xFF).
 237 */
 238 Bit8u SaturateWordSToByteU(Bit16s value)
 239 BX_CPP_AttrRegparmN(1);
 240
 241 /*
 242   SaturateDwordSToWordU  converts  a signed 32-bit value
 243   to  an  unsigned  16-bit value. If the signed 32-bit value is less
 244   than   zero,   it   is  represented  by  the saturated value 65535
 245   (0x0000).  If  it  is greater  than  65535,  it  is represented by
 246   the saturated value 65535 (0xFFFF).
 247 */
 248 Bit16u SaturateDwordSToWordU(Bit32s value)
 249 BX_CPP_AttrRegparmN(1);
 250
 251 #endif // BX_SUPPORT_SSE
 252
 253 #endif